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[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-trans-pcie.c
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63 #include <linux/pci.h>
64 #include <linux/pci-aspm.h>
65 #include <linux/interrupt.h>
66 #include <linux/debugfs.h>
67 #include <linux/bitops.h>
68 #include <linux/gfp.h>
69
70 #include "iwl-trans.h"
71 #include "iwl-trans-pcie-int.h"
72 #include "iwl-csr.h"
73 #include "iwl-prph.h"
74 #include "iwl-shared.h"
75 #include "iwl-eeprom.h"
76 #include "iwl-agn-hw.h"
77
78 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
79 {
80 struct iwl_trans_pcie *trans_pcie =
81 IWL_TRANS_GET_PCIE_TRANS(trans);
82 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
83 struct device *dev = bus(trans)->dev;
84
85 memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
86
87 spin_lock_init(&rxq->lock);
88
89 if (WARN_ON(rxq->bd || rxq->rb_stts))
90 return -EINVAL;
91
92 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
93 rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
94 &rxq->bd_dma, GFP_KERNEL);
95 if (!rxq->bd)
96 goto err_bd;
97
98 /*Allocate the driver's pointer to receive buffer status */
99 rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
100 &rxq->rb_stts_dma, GFP_KERNEL);
101 if (!rxq->rb_stts)
102 goto err_rb_stts;
103
104 return 0;
105
106 err_rb_stts:
107 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
108 rxq->bd, rxq->bd_dma);
109 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
110 rxq->bd = NULL;
111 err_bd:
112 return -ENOMEM;
113 }
114
115 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
116 {
117 struct iwl_trans_pcie *trans_pcie =
118 IWL_TRANS_GET_PCIE_TRANS(trans);
119 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
120 int i;
121
122 /* Fill the rx_used queue with _all_ of the Rx buffers */
123 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
124 /* In the reset function, these buffers may have been allocated
125 * to an SKB, so we need to unmap and free potential storage */
126 if (rxq->pool[i].page != NULL) {
127 dma_unmap_page(bus(trans)->dev, rxq->pool[i].page_dma,
128 PAGE_SIZE << hw_params(trans).rx_page_order,
129 DMA_FROM_DEVICE);
130 __free_pages(rxq->pool[i].page,
131 hw_params(trans).rx_page_order);
132 rxq->pool[i].page = NULL;
133 }
134 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
135 }
136 }
137
138 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
139 struct iwl_rx_queue *rxq)
140 {
141 u32 rb_size;
142 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
143 u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
144
145 if (iwlagn_mod_params.amsdu_size_8K)
146 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
147 else
148 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
149
150 /* Stop Rx DMA */
151 iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
152
153 /* Reset driver's Rx queue write index */
154 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
155
156 /* Tell device where to find RBD circular buffer in DRAM */
157 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_BASE_REG,
158 (u32)(rxq->bd_dma >> 8));
159
160 /* Tell device where in DRAM to update its Rx status */
161 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_STTS_WPTR_REG,
162 rxq->rb_stts_dma >> 4);
163
164 /* Enable Rx DMA
165 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
166 * the credit mechanism in 5000 HW RX FIFO
167 * Direct rx interrupts to hosts
168 * Rx buffer size 4 or 8k
169 * RB timeout 0x10
170 * 256 RBDs
171 */
172 iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG,
173 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
174 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
175 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
176 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
177 rb_size|
178 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
179 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
180
181 /* Set interrupt coalescing timer to default (2048 usecs) */
182 iwl_write8(bus(trans), CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
183 }
184
185 static int iwl_rx_init(struct iwl_trans *trans)
186 {
187 struct iwl_trans_pcie *trans_pcie =
188 IWL_TRANS_GET_PCIE_TRANS(trans);
189 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
190
191 int i, err;
192 unsigned long flags;
193
194 if (!rxq->bd) {
195 err = iwl_trans_rx_alloc(trans);
196 if (err)
197 return err;
198 }
199
200 spin_lock_irqsave(&rxq->lock, flags);
201 INIT_LIST_HEAD(&rxq->rx_free);
202 INIT_LIST_HEAD(&rxq->rx_used);
203
204 iwl_trans_rxq_free_rx_bufs(trans);
205
206 for (i = 0; i < RX_QUEUE_SIZE; i++)
207 rxq->queue[i] = NULL;
208
209 /* Set us so that we have processed and used all buffers, but have
210 * not restocked the Rx queue with fresh buffers */
211 rxq->read = rxq->write = 0;
212 rxq->write_actual = 0;
213 rxq->free_count = 0;
214 spin_unlock_irqrestore(&rxq->lock, flags);
215
216 iwlagn_rx_replenish(trans);
217
218 iwl_trans_rx_hw_init(trans, rxq);
219
220 spin_lock_irqsave(&trans->shrd->lock, flags);
221 rxq->need_update = 1;
222 iwl_rx_queue_update_write_ptr(trans, rxq);
223 spin_unlock_irqrestore(&trans->shrd->lock, flags);
224
225 return 0;
226 }
227
228 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
229 {
230 struct iwl_trans_pcie *trans_pcie =
231 IWL_TRANS_GET_PCIE_TRANS(trans);
232 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
233
234 unsigned long flags;
235
236 /*if rxq->bd is NULL, it means that nothing has been allocated,
237 * exit now */
238 if (!rxq->bd) {
239 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
240 return;
241 }
242
243 spin_lock_irqsave(&rxq->lock, flags);
244 iwl_trans_rxq_free_rx_bufs(trans);
245 spin_unlock_irqrestore(&rxq->lock, flags);
246
247 dma_free_coherent(bus(trans)->dev, sizeof(__le32) * RX_QUEUE_SIZE,
248 rxq->bd, rxq->bd_dma);
249 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
250 rxq->bd = NULL;
251
252 if (rxq->rb_stts)
253 dma_free_coherent(bus(trans)->dev,
254 sizeof(struct iwl_rb_status),
255 rxq->rb_stts, rxq->rb_stts_dma);
256 else
257 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
258 memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
259 rxq->rb_stts = NULL;
260 }
261
262 static int iwl_trans_rx_stop(struct iwl_trans *trans)
263 {
264
265 /* stop Rx DMA */
266 iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
267 return iwl_poll_direct_bit(bus(trans), FH_MEM_RSSR_RX_STATUS_REG,
268 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
269 }
270
271 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
272 struct iwl_dma_ptr *ptr, size_t size)
273 {
274 if (WARN_ON(ptr->addr))
275 return -EINVAL;
276
277 ptr->addr = dma_alloc_coherent(bus(trans)->dev, size,
278 &ptr->dma, GFP_KERNEL);
279 if (!ptr->addr)
280 return -ENOMEM;
281 ptr->size = size;
282 return 0;
283 }
284
285 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
286 struct iwl_dma_ptr *ptr)
287 {
288 if (unlikely(!ptr->addr))
289 return;
290
291 dma_free_coherent(bus(trans)->dev, ptr->size, ptr->addr, ptr->dma);
292 memset(ptr, 0, sizeof(*ptr));
293 }
294
295 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
296 struct iwl_tx_queue *txq, int slots_num,
297 u32 txq_id)
298 {
299 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
300 int i;
301
302 if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds))
303 return -EINVAL;
304
305 txq->q.n_window = slots_num;
306
307 txq->meta = kcalloc(slots_num, sizeof(txq->meta[0]), GFP_KERNEL);
308 txq->cmd = kcalloc(slots_num, sizeof(txq->cmd[0]), GFP_KERNEL);
309
310 if (!txq->meta || !txq->cmd)
311 goto error;
312
313 if (txq_id == trans->shrd->cmd_queue)
314 for (i = 0; i < slots_num; i++) {
315 txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
316 GFP_KERNEL);
317 if (!txq->cmd[i])
318 goto error;
319 }
320
321 /* Alloc driver data array and TFD circular buffer */
322 /* Driver private data, only for Tx (not command) queues,
323 * not shared with device. */
324 if (txq_id != trans->shrd->cmd_queue) {
325 txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->skbs[0]),
326 GFP_KERNEL);
327 if (!txq->skbs) {
328 IWL_ERR(trans, "kmalloc for auxiliary BD "
329 "structures failed\n");
330 goto error;
331 }
332 } else {
333 txq->skbs = NULL;
334 }
335
336 /* Circular buffer of transmit frame descriptors (TFDs),
337 * shared with device */
338 txq->tfds = dma_alloc_coherent(bus(trans)->dev, tfd_sz,
339 &txq->q.dma_addr, GFP_KERNEL);
340 if (!txq->tfds) {
341 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
342 goto error;
343 }
344 txq->q.id = txq_id;
345
346 return 0;
347 error:
348 kfree(txq->skbs);
349 txq->skbs = NULL;
350 /* since txq->cmd has been zeroed,
351 * all non allocated cmd[i] will be NULL */
352 if (txq->cmd && txq_id == trans->shrd->cmd_queue)
353 for (i = 0; i < slots_num; i++)
354 kfree(txq->cmd[i]);
355 kfree(txq->meta);
356 kfree(txq->cmd);
357 txq->meta = NULL;
358 txq->cmd = NULL;
359
360 return -ENOMEM;
361
362 }
363
364 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
365 int slots_num, u32 txq_id)
366 {
367 int ret;
368
369 txq->need_update = 0;
370 memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
371
372 /*
373 * For the default queues 0-3, set up the swq_id
374 * already -- all others need to get one later
375 * (if they need one at all).
376 */
377 if (txq_id < 4)
378 iwl_set_swq_id(txq, txq_id, txq_id);
379
380 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
381 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
382 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
383
384 /* Initialize queue's high/low-water marks, and head/tail indexes */
385 ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
386 txq_id);
387 if (ret)
388 return ret;
389
390 /*
391 * Tell nic where to find circular buffer of Tx Frame Descriptors for
392 * given Tx queue, and enable the DMA channel used for that queue.
393 * Circular buffer (TFD queue in DRAM) physical base address */
394 iwl_write_direct32(bus(trans), FH_MEM_CBBC_QUEUE(txq_id),
395 txq->q.dma_addr >> 8);
396
397 return 0;
398 }
399
400 /**
401 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
402 */
403 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
404 {
405 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
406 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
407 struct iwl_queue *q = &txq->q;
408 enum dma_data_direction dma_dir;
409 unsigned long flags;
410 spinlock_t *lock;
411
412 if (!q->n_bd)
413 return;
414
415 /* In the command queue, all the TBs are mapped as BIDI
416 * so unmap them as such.
417 */
418 if (txq_id == trans->shrd->cmd_queue) {
419 dma_dir = DMA_BIDIRECTIONAL;
420 lock = &trans->hcmd_lock;
421 } else {
422 dma_dir = DMA_TO_DEVICE;
423 lock = &trans->shrd->sta_lock;
424 }
425
426 spin_lock_irqsave(lock, flags);
427 while (q->write_ptr != q->read_ptr) {
428 /* The read_ptr needs to bound by q->n_window */
429 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr),
430 dma_dir);
431 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
432 }
433 spin_unlock_irqrestore(lock, flags);
434 }
435
436 /**
437 * iwl_tx_queue_free - Deallocate DMA queue.
438 * @txq: Transmit queue to deallocate.
439 *
440 * Empty queue by removing and destroying all BD's.
441 * Free all buffers.
442 * 0-fill, but do not free "txq" descriptor structure.
443 */
444 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
445 {
446 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
447 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
448 struct device *dev = bus(trans)->dev;
449 int i;
450 if (WARN_ON(!txq))
451 return;
452
453 iwl_tx_queue_unmap(trans, txq_id);
454
455 /* De-alloc array of command/tx buffers */
456
457 if (txq_id == trans->shrd->cmd_queue)
458 for (i = 0; i < txq->q.n_window; i++)
459 kfree(txq->cmd[i]);
460
461 /* De-alloc circular buffer of TFDs */
462 if (txq->q.n_bd) {
463 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
464 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
465 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
466 }
467
468 /* De-alloc array of per-TFD driver data */
469 kfree(txq->skbs);
470 txq->skbs = NULL;
471
472 /* deallocate arrays */
473 kfree(txq->cmd);
474 kfree(txq->meta);
475 txq->cmd = NULL;
476 txq->meta = NULL;
477
478 /* 0-fill queue descriptor structure */
479 memset(txq, 0, sizeof(*txq));
480 }
481
482 /**
483 * iwl_trans_tx_free - Free TXQ Context
484 *
485 * Destroy all TX DMA queues and structures
486 */
487 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
488 {
489 int txq_id;
490 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
491
492 /* Tx queues */
493 if (trans_pcie->txq) {
494 for (txq_id = 0;
495 txq_id < hw_params(trans).max_txq_num; txq_id++)
496 iwl_tx_queue_free(trans, txq_id);
497 }
498
499 kfree(trans_pcie->txq);
500 trans_pcie->txq = NULL;
501
502 iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
503
504 iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
505 }
506
507 /**
508 * iwl_trans_tx_alloc - allocate TX context
509 * Allocate all Tx DMA structures and initialize them
510 *
511 * @param priv
512 * @return error code
513 */
514 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
515 {
516 int ret;
517 int txq_id, slots_num;
518 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
519
520 u16 scd_bc_tbls_size = hw_params(trans).max_txq_num *
521 sizeof(struct iwlagn_scd_bc_tbl);
522
523 /*It is not allowed to alloc twice, so warn when this happens.
524 * We cannot rely on the previous allocation, so free and fail */
525 if (WARN_ON(trans_pcie->txq)) {
526 ret = -EINVAL;
527 goto error;
528 }
529
530 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
531 scd_bc_tbls_size);
532 if (ret) {
533 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
534 goto error;
535 }
536
537 /* Alloc keep-warm buffer */
538 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
539 if (ret) {
540 IWL_ERR(trans, "Keep Warm allocation failed\n");
541 goto error;
542 }
543
544 trans_pcie->txq = kcalloc(hw_params(trans).max_txq_num,
545 sizeof(struct iwl_tx_queue), GFP_KERNEL);
546 if (!trans_pcie->txq) {
547 IWL_ERR(trans, "Not enough memory for txq\n");
548 ret = ENOMEM;
549 goto error;
550 }
551
552 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
553 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
554 slots_num = (txq_id == trans->shrd->cmd_queue) ?
555 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
556 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
557 slots_num, txq_id);
558 if (ret) {
559 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
560 goto error;
561 }
562 }
563
564 return 0;
565
566 error:
567 iwl_trans_pcie_tx_free(trans);
568
569 return ret;
570 }
571 static int iwl_tx_init(struct iwl_trans *trans)
572 {
573 int ret;
574 int txq_id, slots_num;
575 unsigned long flags;
576 bool alloc = false;
577 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
578
579 if (!trans_pcie->txq) {
580 ret = iwl_trans_tx_alloc(trans);
581 if (ret)
582 goto error;
583 alloc = true;
584 }
585
586 spin_lock_irqsave(&trans->shrd->lock, flags);
587
588 /* Turn off all Tx DMA fifos */
589 iwl_write_prph(bus(trans), SCD_TXFACT, 0);
590
591 /* Tell NIC where to find the "keep warm" buffer */
592 iwl_write_direct32(bus(trans), FH_KW_MEM_ADDR_REG,
593 trans_pcie->kw.dma >> 4);
594
595 spin_unlock_irqrestore(&trans->shrd->lock, flags);
596
597 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
598 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
599 slots_num = (txq_id == trans->shrd->cmd_queue) ?
600 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
601 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
602 slots_num, txq_id);
603 if (ret) {
604 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
605 goto error;
606 }
607 }
608
609 return 0;
610 error:
611 /*Upon error, free only if we allocated something */
612 if (alloc)
613 iwl_trans_pcie_tx_free(trans);
614 return ret;
615 }
616
617 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
618 {
619 /*
620 * (for documentation purposes)
621 * to set power to V_AUX, do:
622
623 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
624 iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
625 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
626 ~APMG_PS_CTRL_MSK_PWR_SRC);
627 */
628
629 iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
630 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
631 ~APMG_PS_CTRL_MSK_PWR_SRC);
632 }
633
634 static int iwl_nic_init(struct iwl_trans *trans)
635 {
636 unsigned long flags;
637
638 /* nic_init */
639 spin_lock_irqsave(&trans->shrd->lock, flags);
640 iwl_apm_init(priv(trans));
641
642 /* Set interrupt coalescing calibration timer to default (512 usecs) */
643 iwl_write8(bus(trans), CSR_INT_COALESCING,
644 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
645
646 spin_unlock_irqrestore(&trans->shrd->lock, flags);
647
648 iwl_set_pwr_vmain(trans);
649
650 iwl_nic_config(priv(trans));
651
652 #ifndef CONFIG_IWLWIFI_IDI
653 /* Allocate the RX queue, or reset if it is already allocated */
654 iwl_rx_init(trans);
655 #endif
656
657 /* Allocate or reset and init all Tx and Command queues */
658 if (iwl_tx_init(trans))
659 return -ENOMEM;
660
661 if (hw_params(trans).shadow_reg_enable) {
662 /* enable shadow regs in HW */
663 iwl_set_bit(bus(trans), CSR_MAC_SHADOW_REG_CTRL,
664 0x800FFFFF);
665 }
666
667 set_bit(STATUS_INIT, &trans->shrd->status);
668
669 return 0;
670 }
671
672 #define HW_READY_TIMEOUT (50)
673
674 /* Note: returns poll_bit return value, which is >= 0 if success */
675 static int iwl_set_hw_ready(struct iwl_trans *trans)
676 {
677 int ret;
678
679 iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
680 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
681
682 /* See if we got it */
683 ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
684 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
685 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
686 HW_READY_TIMEOUT);
687
688 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
689 return ret;
690 }
691
692 /* Note: returns standard 0/-ERROR code */
693 static int iwl_trans_pcie_prepare_card_hw(struct iwl_trans *trans)
694 {
695 int ret;
696
697 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
698
699 ret = iwl_set_hw_ready(trans);
700 if (ret >= 0)
701 return 0;
702
703 /* If HW is not ready, prepare the conditions to check again */
704 iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
705 CSR_HW_IF_CONFIG_REG_PREPARE);
706
707 ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
708 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
709 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
710
711 if (ret < 0)
712 return ret;
713
714 /* HW should be ready by now, check again. */
715 ret = iwl_set_hw_ready(trans);
716 if (ret >= 0)
717 return 0;
718 return ret;
719 }
720
721 #define IWL_AC_UNSET -1
722
723 struct queue_to_fifo_ac {
724 s8 fifo, ac;
725 };
726
727 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
728 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
729 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
730 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
731 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
732 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
733 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
734 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
735 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
736 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
737 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
738 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
739 };
740
741 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
742 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
743 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
744 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
745 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
746 { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
747 { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
748 { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
749 { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
750 { IWL_TX_FIFO_BE_IPAN, 2, },
751 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
752 { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
753 };
754
755 static const u8 iwlagn_bss_ac_to_fifo[] = {
756 IWL_TX_FIFO_VO,
757 IWL_TX_FIFO_VI,
758 IWL_TX_FIFO_BE,
759 IWL_TX_FIFO_BK,
760 };
761 static const u8 iwlagn_bss_ac_to_queue[] = {
762 0, 1, 2, 3,
763 };
764 static const u8 iwlagn_pan_ac_to_fifo[] = {
765 IWL_TX_FIFO_VO_IPAN,
766 IWL_TX_FIFO_VI_IPAN,
767 IWL_TX_FIFO_BE_IPAN,
768 IWL_TX_FIFO_BK_IPAN,
769 };
770 static const u8 iwlagn_pan_ac_to_queue[] = {
771 7, 6, 5, 4,
772 };
773
774 static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
775 {
776 int ret;
777 struct iwl_trans_pcie *trans_pcie =
778 IWL_TRANS_GET_PCIE_TRANS(trans);
779
780 trans->shrd->ucode_owner = IWL_OWNERSHIP_DRIVER;
781 trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue;
782 trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue;
783
784 trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo;
785 trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo;
786
787 trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0;
788 trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE;
789
790 if ((hw_params(trans).sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
791 iwl_trans_pcie_prepare_card_hw(trans)) {
792 IWL_WARN(trans, "Exit HW not ready\n");
793 return -EIO;
794 }
795
796 /* If platform's RF_KILL switch is NOT set to KILL */
797 if (iwl_read32(bus(trans), CSR_GP_CNTRL) &
798 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
799 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
800 else
801 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
802
803 if (iwl_is_rfkill(trans->shrd)) {
804 iwl_set_hw_rfkill_state(priv(trans), true);
805 iwl_enable_interrupts(trans);
806 return -ERFKILL;
807 }
808
809 iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF);
810
811 ret = iwl_nic_init(trans);
812 if (ret) {
813 IWL_ERR(trans, "Unable to init nic\n");
814 return ret;
815 }
816
817 /* make sure rfkill handshake bits are cleared */
818 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
819 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR,
820 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
821
822 /* clear (again), then enable host interrupts */
823 iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF);
824 iwl_enable_interrupts(trans);
825
826 /* really make sure rfkill handshake bits are cleared */
827 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
828 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
829
830 return 0;
831 }
832
833 /*
834 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
835 * must be called under priv->shrd->lock and mac access
836 */
837 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
838 {
839 iwl_write_prph(bus(trans), SCD_TXFACT, mask);
840 }
841
842 static void iwl_tx_start(struct iwl_trans *trans)
843 {
844 const struct queue_to_fifo_ac *queue_to_fifo;
845 struct iwl_trans_pcie *trans_pcie =
846 IWL_TRANS_GET_PCIE_TRANS(trans);
847 u32 a;
848 unsigned long flags;
849 int i, chan;
850 u32 reg_val;
851
852 spin_lock_irqsave(&trans->shrd->lock, flags);
853
854 trans_pcie->scd_base_addr =
855 iwl_read_prph(bus(trans), SCD_SRAM_BASE_ADDR);
856 a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
857 /* reset conext data memory */
858 for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
859 a += 4)
860 iwl_write_targ_mem(bus(trans), a, 0);
861 /* reset tx status memory */
862 for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
863 a += 4)
864 iwl_write_targ_mem(bus(trans), a, 0);
865 for (; a < trans_pcie->scd_base_addr +
866 SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num);
867 a += 4)
868 iwl_write_targ_mem(bus(trans), a, 0);
869
870 iwl_write_prph(bus(trans), SCD_DRAM_BASE_ADDR,
871 trans_pcie->scd_bc_tbls.dma >> 10);
872
873 /* Enable DMA channel */
874 for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
875 iwl_write_direct32(bus(trans), FH_TCSR_CHNL_TX_CONFIG_REG(chan),
876 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
877 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
878
879 /* Update FH chicken bits */
880 reg_val = iwl_read_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG);
881 iwl_write_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG,
882 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
883
884 iwl_write_prph(bus(trans), SCD_QUEUECHAIN_SEL,
885 SCD_QUEUECHAIN_SEL_ALL(trans));
886 iwl_write_prph(bus(trans), SCD_AGGR_SEL, 0);
887
888 /* initiate the queues */
889 for (i = 0; i < hw_params(trans).max_txq_num; i++) {
890 iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(i), 0);
891 iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR, 0 | (i << 8));
892 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
893 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
894 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
895 SCD_CONTEXT_QUEUE_OFFSET(i) +
896 sizeof(u32),
897 ((SCD_WIN_SIZE <<
898 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
899 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
900 ((SCD_FRAME_LIMIT <<
901 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
902 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
903 }
904
905 iwl_write_prph(bus(trans), SCD_INTERRUPT_MASK,
906 IWL_MASK(0, hw_params(trans).max_txq_num));
907
908 /* Activate all Tx DMA/FIFO channels */
909 iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
910
911 /* map queues to FIFOs */
912 if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS))
913 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
914 else
915 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
916
917 iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0);
918
919 /* make sure all queue are not stopped */
920 memset(&trans_pcie->queue_stopped[0], 0,
921 sizeof(trans_pcie->queue_stopped));
922 for (i = 0; i < 4; i++)
923 atomic_set(&trans_pcie->queue_stop_count[i], 0);
924
925 /* reset to 0 to enable all the queue first */
926 trans_pcie->txq_ctx_active_msk = 0;
927
928 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
929 IWLAGN_FIRST_AMPDU_QUEUE);
930 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
931 IWLAGN_FIRST_AMPDU_QUEUE);
932
933 for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
934 int fifo = queue_to_fifo[i].fifo;
935 int ac = queue_to_fifo[i].ac;
936
937 iwl_txq_ctx_activate(trans_pcie, i);
938
939 if (fifo == IWL_TX_FIFO_UNUSED)
940 continue;
941
942 if (ac != IWL_AC_UNSET)
943 iwl_set_swq_id(&trans_pcie->txq[i], ac, i);
944 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
945 fifo, 0);
946 }
947
948 spin_unlock_irqrestore(&trans->shrd->lock, flags);
949
950 /* Enable L1-Active */
951 iwl_clear_bits_prph(bus(trans), APMG_PCIDEV_STT_REG,
952 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
953 }
954
955 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
956 {
957 iwl_reset_ict(trans);
958 iwl_tx_start(trans);
959 }
960
961 /**
962 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
963 */
964 static int iwl_trans_tx_stop(struct iwl_trans *trans)
965 {
966 int ch, txq_id;
967 unsigned long flags;
968 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
969
970 /* Turn off all Tx DMA fifos */
971 spin_lock_irqsave(&trans->shrd->lock, flags);
972
973 iwl_trans_txq_set_sched(trans, 0);
974
975 /* Stop each Tx DMA channel, and wait for it to be idle */
976 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
977 iwl_write_direct32(bus(trans),
978 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
979 if (iwl_poll_direct_bit(bus(trans), FH_TSSR_TX_STATUS_REG,
980 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
981 1000))
982 IWL_ERR(trans, "Failing on timeout while stopping"
983 " DMA channel %d [0x%08x]", ch,
984 iwl_read_direct32(bus(trans),
985 FH_TSSR_TX_STATUS_REG));
986 }
987 spin_unlock_irqrestore(&trans->shrd->lock, flags);
988
989 if (!trans_pcie->txq) {
990 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
991 return 0;
992 }
993
994 /* Unmap DMA from host system and free skb's */
995 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
996 iwl_tx_queue_unmap(trans, txq_id);
997
998 return 0;
999 }
1000
1001 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1002 {
1003 unsigned long flags;
1004 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1005
1006 /* tell the device to stop sending interrupts */
1007 spin_lock_irqsave(&trans->shrd->lock, flags);
1008 iwl_disable_interrupts(trans);
1009 spin_unlock_irqrestore(&trans->shrd->lock, flags);
1010
1011 /* device going down, Stop using ICT table */
1012 iwl_disable_ict(trans);
1013
1014 /*
1015 * If a HW restart happens during firmware loading,
1016 * then the firmware loading might call this function
1017 * and later it might be called again due to the
1018 * restart. So don't process again if the device is
1019 * already dead.
1020 */
1021 if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) {
1022 iwl_trans_tx_stop(trans);
1023 #ifndef CONFIG_IWLWIFI_IDI
1024 iwl_trans_rx_stop(trans);
1025 #endif
1026 /* Power-down device's busmaster DMA clocks */
1027 iwl_write_prph(bus(trans), APMG_CLK_DIS_REG,
1028 APMG_CLK_VAL_DMA_CLK_RQT);
1029 udelay(5);
1030 }
1031
1032 /* Make sure (redundant) we've released our request to stay awake */
1033 iwl_clear_bit(bus(trans), CSR_GP_CNTRL,
1034 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1035
1036 /* Stop the device, and put it in low power state */
1037 iwl_apm_stop(priv(trans));
1038
1039 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1040 * Clean again the interrupt here
1041 */
1042 spin_lock_irqsave(&trans->shrd->lock, flags);
1043 iwl_disable_interrupts(trans);
1044 spin_unlock_irqrestore(&trans->shrd->lock, flags);
1045
1046 /* wait to make sure we flush pending tasklet*/
1047 synchronize_irq(trans->irq);
1048 tasklet_kill(&trans_pcie->irq_tasklet);
1049
1050 /* stop and reset the on-board processor */
1051 iwl_write32(bus(trans), CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1052 }
1053
1054 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1055 struct iwl_device_cmd *dev_cmd, enum iwl_rxon_context_id ctx,
1056 u8 sta_id, u8 tid)
1057 {
1058 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1059 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1060 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1061 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1062 struct iwl_cmd_meta *out_meta;
1063 struct iwl_tx_queue *txq;
1064 struct iwl_queue *q;
1065
1066 dma_addr_t phys_addr = 0;
1067 dma_addr_t txcmd_phys;
1068 dma_addr_t scratch_phys;
1069 u16 len, firstlen, secondlen;
1070 u8 wait_write_ptr = 0;
1071 u8 txq_id;
1072 bool is_agg = false;
1073 __le16 fc = hdr->frame_control;
1074 u8 hdr_len = ieee80211_hdrlen(fc);
1075 u16 __maybe_unused wifi_seq;
1076
1077 /*
1078 * Send this frame after DTIM -- there's a special queue
1079 * reserved for this for contexts that support AP mode.
1080 */
1081 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1082 txq_id = trans_pcie->mcast_queue[ctx];
1083
1084 /*
1085 * The microcode will clear the more data
1086 * bit in the last frame it transmits.
1087 */
1088 hdr->frame_control |=
1089 cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1090 } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
1091 txq_id = IWL_AUX_QUEUE;
1092 else
1093 txq_id =
1094 trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)];
1095
1096 /* aggregation is on for this <sta,tid> */
1097 if (info->flags & IEEE80211_TX_CTL_AMPDU) {
1098 WARN_ON(tid >= IWL_MAX_TID_COUNT);
1099 txq_id = trans_pcie->agg_txq[sta_id][tid];
1100 is_agg = true;
1101 }
1102
1103 txq = &trans_pcie->txq[txq_id];
1104 q = &txq->q;
1105
1106 /* In AGG mode, the index in the ring must correspond to the WiFi
1107 * sequence number. This is a HW requirements to help the SCD to parse
1108 * the BA.
1109 * Check here that the packets are in the right place on the ring.
1110 */
1111 #ifdef CONFIG_IWLWIFI_DEBUG
1112 wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1113 WARN_ONCE(is_agg && ((wifi_seq & 0xff) != q->write_ptr),
1114 "Q: %d WiFi Seq %d tfdNum %d",
1115 txq_id, wifi_seq, q->write_ptr);
1116 #endif
1117
1118 /* Set up driver data for this TFD */
1119 txq->skbs[q->write_ptr] = skb;
1120 txq->cmd[q->write_ptr] = dev_cmd;
1121
1122 dev_cmd->hdr.cmd = REPLY_TX;
1123 dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1124 INDEX_TO_SEQ(q->write_ptr)));
1125
1126 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1127 out_meta = &txq->meta[q->write_ptr];
1128
1129 /*
1130 * Use the first empty entry in this queue's command buffer array
1131 * to contain the Tx command and MAC header concatenated together
1132 * (payload data will be in another buffer).
1133 * Size of this varies, due to varying MAC header length.
1134 * If end is not dword aligned, we'll have 2 extra bytes at the end
1135 * of the MAC header (device reads on dword boundaries).
1136 * We'll tell device about this padding later.
1137 */
1138 len = sizeof(struct iwl_tx_cmd) +
1139 sizeof(struct iwl_cmd_header) + hdr_len;
1140 firstlen = (len + 3) & ~3;
1141
1142 /* Tell NIC about any 2-byte padding after MAC header */
1143 if (firstlen != len)
1144 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1145
1146 /* Physical address of this Tx command's header (not MAC header!),
1147 * within command buffer array. */
1148 txcmd_phys = dma_map_single(bus(trans)->dev,
1149 &dev_cmd->hdr, firstlen,
1150 DMA_BIDIRECTIONAL);
1151 if (unlikely(dma_mapping_error(bus(trans)->dev, txcmd_phys)))
1152 return -1;
1153 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1154 dma_unmap_len_set(out_meta, len, firstlen);
1155
1156 if (!ieee80211_has_morefrags(fc)) {
1157 txq->need_update = 1;
1158 } else {
1159 wait_write_ptr = 1;
1160 txq->need_update = 0;
1161 }
1162
1163 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1164 * if any (802.11 null frames have no payload). */
1165 secondlen = skb->len - hdr_len;
1166 if (secondlen > 0) {
1167 phys_addr = dma_map_single(bus(trans)->dev, skb->data + hdr_len,
1168 secondlen, DMA_TO_DEVICE);
1169 if (unlikely(dma_mapping_error(bus(trans)->dev, phys_addr))) {
1170 dma_unmap_single(bus(trans)->dev,
1171 dma_unmap_addr(out_meta, mapping),
1172 dma_unmap_len(out_meta, len),
1173 DMA_BIDIRECTIONAL);
1174 return -1;
1175 }
1176 }
1177
1178 /* Attach buffers to TFD */
1179 iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1180 if (secondlen > 0)
1181 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1182 secondlen, 0);
1183
1184 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1185 offsetof(struct iwl_tx_cmd, scratch);
1186
1187 /* take back ownership of DMA buffer to enable update */
1188 dma_sync_single_for_cpu(bus(trans)->dev, txcmd_phys, firstlen,
1189 DMA_BIDIRECTIONAL);
1190 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1191 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1192
1193 IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1194 le16_to_cpu(dev_cmd->hdr.sequence));
1195 IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1196 iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1197 iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1198
1199 /* Set up entry for this TFD in Tx byte-count array */
1200 iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1201
1202 dma_sync_single_for_device(bus(trans)->dev, txcmd_phys, firstlen,
1203 DMA_BIDIRECTIONAL);
1204
1205 trace_iwlwifi_dev_tx(priv(trans),
1206 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1207 sizeof(struct iwl_tfd),
1208 &dev_cmd->hdr, firstlen,
1209 skb->data + hdr_len, secondlen);
1210
1211 /* Tell device the write index *just past* this latest filled TFD */
1212 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1213 iwl_txq_update_write_ptr(trans, txq);
1214
1215 /*
1216 * At this point the frame is "transmitted" successfully
1217 * and we will get a TX status notification eventually,
1218 * regardless of the value of ret. "ret" only indicates
1219 * whether or not we should update the write pointer.
1220 */
1221 if (iwl_queue_space(q) < q->high_mark) {
1222 if (wait_write_ptr) {
1223 txq->need_update = 1;
1224 iwl_txq_update_write_ptr(trans, txq);
1225 } else {
1226 iwl_stop_queue(trans, txq, "Queue is full");
1227 }
1228 }
1229 return 0;
1230 }
1231
1232 static void iwl_trans_pcie_kick_nic(struct iwl_trans *trans)
1233 {
1234 /* Remove all resets to allow NIC to operate */
1235 iwl_write32(bus(trans), CSR_RESET, 0);
1236 }
1237
1238 static int iwl_trans_pcie_request_irq(struct iwl_trans *trans)
1239 {
1240 struct iwl_trans_pcie *trans_pcie =
1241 IWL_TRANS_GET_PCIE_TRANS(trans);
1242 int err;
1243
1244 trans_pcie->inta_mask = CSR_INI_SET_MASK;
1245
1246 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1247 iwl_irq_tasklet, (unsigned long)trans);
1248
1249 iwl_alloc_isr_ict(trans);
1250
1251 err = request_irq(trans->irq, iwl_isr_ict, IRQF_SHARED,
1252 DRV_NAME, trans);
1253 if (err) {
1254 IWL_ERR(trans, "Error allocating IRQ %d\n", trans->irq);
1255 iwl_free_isr_ict(trans);
1256 return err;
1257 }
1258
1259 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1260 return 0;
1261 }
1262
1263 static int iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid,
1264 int txq_id, int ssn, u32 status,
1265 struct sk_buff_head *skbs)
1266 {
1267 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1268 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1269 /* n_bd is usually 256 => n_bd - 1 = 0xff */
1270 int tfd_num = ssn & (txq->q.n_bd - 1);
1271 int freed = 0;
1272
1273 txq->time_stamp = jiffies;
1274
1275 if (unlikely(txq_id >= IWLAGN_FIRST_AMPDU_QUEUE &&
1276 txq_id != trans_pcie->agg_txq[sta_id][tid])) {
1277 /*
1278 * FIXME: this is a uCode bug which need to be addressed,
1279 * log the information and return for now.
1280 * Since it is can possibly happen very often and in order
1281 * not to fill the syslog, don't use IWL_ERR or IWL_WARN
1282 */
1283 IWL_DEBUG_TX_QUEUES(trans, "Bad queue mapping txq_id %d, "
1284 "agg_txq[sta_id[tid] %d", txq_id,
1285 trans_pcie->agg_txq[sta_id][tid]);
1286 return 1;
1287 }
1288
1289 if (txq->q.read_ptr != tfd_num) {
1290 IWL_DEBUG_TX_REPLY(trans, "[Q %d | AC %d] %d -> %d (%d)\n",
1291 txq_id, iwl_get_queue_ac(txq), txq->q.read_ptr,
1292 tfd_num, ssn);
1293 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1294 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1295 (!txq->sched_retry ||
1296 status != TX_STATUS_FAIL_PASSIVE_NO_RX))
1297 iwl_wake_queue(trans, txq, "Packets reclaimed");
1298 }
1299 return 0;
1300 }
1301
1302 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1303 {
1304 iowrite8(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1305 }
1306
1307 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1308 {
1309 iowrite32(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1310 }
1311
1312 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1313 {
1314 u32 val = ioread32(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1315 return val;
1316 }
1317
1318 static void iwl_trans_pcie_free(struct iwl_trans *trans)
1319 {
1320 struct iwl_trans_pcie *trans_pcie =
1321 IWL_TRANS_GET_PCIE_TRANS(trans);
1322
1323 iwl_calib_free_results(trans);
1324 iwl_trans_pcie_tx_free(trans);
1325 #ifndef CONFIG_IWLWIFI_IDI
1326 iwl_trans_pcie_rx_free(trans);
1327 #endif
1328 free_irq(trans->irq, trans);
1329 iwl_free_isr_ict(trans);
1330
1331 pci_disable_msi(trans_pcie->pci_dev);
1332 pci_iounmap(trans_pcie->pci_dev, trans_pcie->hw_base);
1333 pci_release_regions(trans_pcie->pci_dev);
1334 pci_disable_device(trans_pcie->pci_dev);
1335
1336 trans->shrd->trans = NULL;
1337 kfree(trans);
1338 }
1339
1340 #ifdef CONFIG_PM_SLEEP
1341 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1342 {
1343 /*
1344 * This function is called when system goes into suspend state
1345 * mac80211 will call iwlagn_mac_stop() from the mac80211 suspend
1346 * function first but since iwlagn_mac_stop() has no knowledge of
1347 * who the caller is,
1348 * it will not call apm_ops.stop() to stop the DMA operation.
1349 * Calling apm_ops.stop here to make sure we stop the DMA.
1350 *
1351 * But of course ... if we have configured WoWLAN then we did other
1352 * things already :-)
1353 */
1354 if (!trans->shrd->wowlan) {
1355 iwl_apm_stop(priv(trans));
1356 } else {
1357 iwl_disable_interrupts(trans);
1358 iwl_clear_bit(bus(trans), CSR_GP_CNTRL,
1359 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1360 }
1361
1362 return 0;
1363 }
1364
1365 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1366 {
1367 bool hw_rfkill = false;
1368
1369 iwl_enable_interrupts(trans);
1370
1371 if (!(iwl_read32(bus(trans), CSR_GP_CNTRL) &
1372 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1373 hw_rfkill = true;
1374
1375 if (hw_rfkill)
1376 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1377 else
1378 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1379
1380 iwl_set_hw_rfkill_state(priv(trans), hw_rfkill);
1381
1382 return 0;
1383 }
1384 #endif /* CONFIG_PM_SLEEP */
1385
1386 static void iwl_trans_pcie_wake_any_queue(struct iwl_trans *trans,
1387 enum iwl_rxon_context_id ctx,
1388 const char *msg)
1389 {
1390 u8 ac, txq_id;
1391 struct iwl_trans_pcie *trans_pcie =
1392 IWL_TRANS_GET_PCIE_TRANS(trans);
1393
1394 for (ac = 0; ac < AC_NUM; ac++) {
1395 txq_id = trans_pcie->ac_to_queue[ctx][ac];
1396 IWL_DEBUG_TX_QUEUES(trans, "Queue Status: Q[%d] %s\n",
1397 ac,
1398 (atomic_read(&trans_pcie->queue_stop_count[ac]) > 0)
1399 ? "stopped" : "awake");
1400 iwl_wake_queue(trans, &trans_pcie->txq[txq_id], msg);
1401 }
1402 }
1403
1404 static void iwl_trans_pcie_stop_queue(struct iwl_trans *trans, int txq_id,
1405 const char *msg)
1406 {
1407 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1408
1409 iwl_stop_queue(trans, &trans_pcie->txq[txq_id], msg);
1410 }
1411
1412 #define IWL_FLUSH_WAIT_MS 2000
1413
1414 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1415 {
1416 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1417 struct iwl_tx_queue *txq;
1418 struct iwl_queue *q;
1419 int cnt;
1420 unsigned long now = jiffies;
1421 int ret = 0;
1422
1423 /* waiting for all the tx frames complete might take a while */
1424 for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1425 if (cnt == trans->shrd->cmd_queue)
1426 continue;
1427 txq = &trans_pcie->txq[cnt];
1428 q = &txq->q;
1429 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1430 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1431 msleep(1);
1432
1433 if (q->read_ptr != q->write_ptr) {
1434 IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1435 ret = -ETIMEDOUT;
1436 break;
1437 }
1438 }
1439 return ret;
1440 }
1441
1442 /*
1443 * On every watchdog tick we check (latest) time stamp. If it does not
1444 * change during timeout period and queue is not empty we reset firmware.
1445 */
1446 static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt)
1447 {
1448 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1449 struct iwl_tx_queue *txq = &trans_pcie->txq[cnt];
1450 struct iwl_queue *q = &txq->q;
1451 unsigned long timeout;
1452
1453 if (q->read_ptr == q->write_ptr) {
1454 txq->time_stamp = jiffies;
1455 return 0;
1456 }
1457
1458 timeout = txq->time_stamp +
1459 msecs_to_jiffies(hw_params(trans).wd_timeout);
1460
1461 if (time_after(jiffies, timeout)) {
1462 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id,
1463 hw_params(trans).wd_timeout);
1464 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1465 q->read_ptr, q->write_ptr);
1466 IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n",
1467 iwl_read_prph(bus(trans), SCD_QUEUE_RDPTR(cnt))
1468 & (TFD_QUEUE_SIZE_MAX - 1),
1469 iwl_read_prph(bus(trans), SCD_QUEUE_WRPTR(cnt)));
1470 return 1;
1471 }
1472
1473 return 0;
1474 }
1475
1476 static const char *get_fh_string(int cmd)
1477 {
1478 switch (cmd) {
1479 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1480 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1481 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1482 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1483 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1484 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1485 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1486 IWL_CMD(FH_TSSR_TX_STATUS_REG);
1487 IWL_CMD(FH_TSSR_TX_ERROR_REG);
1488 default:
1489 return "UNKNOWN";
1490 }
1491 }
1492
1493 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1494 {
1495 int i;
1496 #ifdef CONFIG_IWLWIFI_DEBUG
1497 int pos = 0;
1498 size_t bufsz = 0;
1499 #endif
1500 static const u32 fh_tbl[] = {
1501 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1502 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1503 FH_RSCSR_CHNL0_WPTR,
1504 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1505 FH_MEM_RSSR_SHARED_CTRL_REG,
1506 FH_MEM_RSSR_RX_STATUS_REG,
1507 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1508 FH_TSSR_TX_STATUS_REG,
1509 FH_TSSR_TX_ERROR_REG
1510 };
1511 #ifdef CONFIG_IWLWIFI_DEBUG
1512 if (display) {
1513 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1514 *buf = kmalloc(bufsz, GFP_KERNEL);
1515 if (!*buf)
1516 return -ENOMEM;
1517 pos += scnprintf(*buf + pos, bufsz - pos,
1518 "FH register values:\n");
1519 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1520 pos += scnprintf(*buf + pos, bufsz - pos,
1521 " %34s: 0X%08x\n",
1522 get_fh_string(fh_tbl[i]),
1523 iwl_read_direct32(bus(trans), fh_tbl[i]));
1524 }
1525 return pos;
1526 }
1527 #endif
1528 IWL_ERR(trans, "FH register values:\n");
1529 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1530 IWL_ERR(trans, " %34s: 0X%08x\n",
1531 get_fh_string(fh_tbl[i]),
1532 iwl_read_direct32(bus(trans), fh_tbl[i]));
1533 }
1534 return 0;
1535 }
1536
1537 static const char *get_csr_string(int cmd)
1538 {
1539 switch (cmd) {
1540 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1541 IWL_CMD(CSR_INT_COALESCING);
1542 IWL_CMD(CSR_INT);
1543 IWL_CMD(CSR_INT_MASK);
1544 IWL_CMD(CSR_FH_INT_STATUS);
1545 IWL_CMD(CSR_GPIO_IN);
1546 IWL_CMD(CSR_RESET);
1547 IWL_CMD(CSR_GP_CNTRL);
1548 IWL_CMD(CSR_HW_REV);
1549 IWL_CMD(CSR_EEPROM_REG);
1550 IWL_CMD(CSR_EEPROM_GP);
1551 IWL_CMD(CSR_OTP_GP_REG);
1552 IWL_CMD(CSR_GIO_REG);
1553 IWL_CMD(CSR_GP_UCODE_REG);
1554 IWL_CMD(CSR_GP_DRIVER_REG);
1555 IWL_CMD(CSR_UCODE_DRV_GP1);
1556 IWL_CMD(CSR_UCODE_DRV_GP2);
1557 IWL_CMD(CSR_LED_REG);
1558 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1559 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1560 IWL_CMD(CSR_ANA_PLL_CFG);
1561 IWL_CMD(CSR_HW_REV_WA_REG);
1562 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1563 default:
1564 return "UNKNOWN";
1565 }
1566 }
1567
1568 void iwl_dump_csr(struct iwl_trans *trans)
1569 {
1570 int i;
1571 static const u32 csr_tbl[] = {
1572 CSR_HW_IF_CONFIG_REG,
1573 CSR_INT_COALESCING,
1574 CSR_INT,
1575 CSR_INT_MASK,
1576 CSR_FH_INT_STATUS,
1577 CSR_GPIO_IN,
1578 CSR_RESET,
1579 CSR_GP_CNTRL,
1580 CSR_HW_REV,
1581 CSR_EEPROM_REG,
1582 CSR_EEPROM_GP,
1583 CSR_OTP_GP_REG,
1584 CSR_GIO_REG,
1585 CSR_GP_UCODE_REG,
1586 CSR_GP_DRIVER_REG,
1587 CSR_UCODE_DRV_GP1,
1588 CSR_UCODE_DRV_GP2,
1589 CSR_LED_REG,
1590 CSR_DRAM_INT_TBL_REG,
1591 CSR_GIO_CHICKEN_BITS,
1592 CSR_ANA_PLL_CFG,
1593 CSR_HW_REV_WA_REG,
1594 CSR_DBG_HPET_MEM_REG
1595 };
1596 IWL_ERR(trans, "CSR values:\n");
1597 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1598 "CSR_INT_PERIODIC_REG)\n");
1599 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1600 IWL_ERR(trans, " %25s: 0X%08x\n",
1601 get_csr_string(csr_tbl[i]),
1602 iwl_read32(bus(trans), csr_tbl[i]));
1603 }
1604 }
1605
1606 #ifdef CONFIG_IWLWIFI_DEBUGFS
1607 /* create and remove of files */
1608 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1609 if (!debugfs_create_file(#name, mode, parent, trans, \
1610 &iwl_dbgfs_##name##_ops)) \
1611 return -ENOMEM; \
1612 } while (0)
1613
1614 /* file operation */
1615 #define DEBUGFS_READ_FUNC(name) \
1616 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1617 char __user *user_buf, \
1618 size_t count, loff_t *ppos);
1619
1620 #define DEBUGFS_WRITE_FUNC(name) \
1621 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1622 const char __user *user_buf, \
1623 size_t count, loff_t *ppos);
1624
1625
1626 static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file)
1627 {
1628 file->private_data = inode->i_private;
1629 return 0;
1630 }
1631
1632 #define DEBUGFS_READ_FILE_OPS(name) \
1633 DEBUGFS_READ_FUNC(name); \
1634 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1635 .read = iwl_dbgfs_##name##_read, \
1636 .open = iwl_dbgfs_open_file_generic, \
1637 .llseek = generic_file_llseek, \
1638 };
1639
1640 #define DEBUGFS_WRITE_FILE_OPS(name) \
1641 DEBUGFS_WRITE_FUNC(name); \
1642 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1643 .write = iwl_dbgfs_##name##_write, \
1644 .open = iwl_dbgfs_open_file_generic, \
1645 .llseek = generic_file_llseek, \
1646 };
1647
1648 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1649 DEBUGFS_READ_FUNC(name); \
1650 DEBUGFS_WRITE_FUNC(name); \
1651 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1652 .write = iwl_dbgfs_##name##_write, \
1653 .read = iwl_dbgfs_##name##_read, \
1654 .open = iwl_dbgfs_open_file_generic, \
1655 .llseek = generic_file_llseek, \
1656 };
1657
1658 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1659 char __user *user_buf,
1660 size_t count, loff_t *ppos)
1661 {
1662 struct iwl_trans *trans = file->private_data;
1663 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1664 struct iwl_tx_queue *txq;
1665 struct iwl_queue *q;
1666 char *buf;
1667 int pos = 0;
1668 int cnt;
1669 int ret;
1670 const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num;
1671
1672 if (!trans_pcie->txq) {
1673 IWL_ERR(trans, "txq not ready\n");
1674 return -EAGAIN;
1675 }
1676 buf = kzalloc(bufsz, GFP_KERNEL);
1677 if (!buf)
1678 return -ENOMEM;
1679
1680 for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1681 txq = &trans_pcie->txq[cnt];
1682 q = &txq->q;
1683 pos += scnprintf(buf + pos, bufsz - pos,
1684 "hwq %.2d: read=%u write=%u stop=%d"
1685 " swq_id=%#.2x (ac %d/hwq %d)\n",
1686 cnt, q->read_ptr, q->write_ptr,
1687 !!test_bit(cnt, trans_pcie->queue_stopped),
1688 txq->swq_id, txq->swq_id & 3,
1689 (txq->swq_id >> 2) & 0x1f);
1690 if (cnt >= 4)
1691 continue;
1692 /* for the ACs, display the stop count too */
1693 pos += scnprintf(buf + pos, bufsz - pos,
1694 " stop-count: %d\n",
1695 atomic_read(&trans_pcie->queue_stop_count[cnt]));
1696 }
1697 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1698 kfree(buf);
1699 return ret;
1700 }
1701
1702 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1703 char __user *user_buf,
1704 size_t count, loff_t *ppos) {
1705 struct iwl_trans *trans = file->private_data;
1706 struct iwl_trans_pcie *trans_pcie =
1707 IWL_TRANS_GET_PCIE_TRANS(trans);
1708 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1709 char buf[256];
1710 int pos = 0;
1711 const size_t bufsz = sizeof(buf);
1712
1713 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1714 rxq->read);
1715 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1716 rxq->write);
1717 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1718 rxq->free_count);
1719 if (rxq->rb_stts) {
1720 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1721 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1722 } else {
1723 pos += scnprintf(buf + pos, bufsz - pos,
1724 "closed_rb_num: Not Allocated\n");
1725 }
1726 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1727 }
1728
1729 static ssize_t iwl_dbgfs_log_event_read(struct file *file,
1730 char __user *user_buf,
1731 size_t count, loff_t *ppos)
1732 {
1733 struct iwl_trans *trans = file->private_data;
1734 char *buf;
1735 int pos = 0;
1736 ssize_t ret = -ENOMEM;
1737
1738 ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
1739 if (buf) {
1740 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1741 kfree(buf);
1742 }
1743 return ret;
1744 }
1745
1746 static ssize_t iwl_dbgfs_log_event_write(struct file *file,
1747 const char __user *user_buf,
1748 size_t count, loff_t *ppos)
1749 {
1750 struct iwl_trans *trans = file->private_data;
1751 u32 event_log_flag;
1752 char buf[8];
1753 int buf_size;
1754
1755 memset(buf, 0, sizeof(buf));
1756 buf_size = min(count, sizeof(buf) - 1);
1757 if (copy_from_user(buf, user_buf, buf_size))
1758 return -EFAULT;
1759 if (sscanf(buf, "%d", &event_log_flag) != 1)
1760 return -EFAULT;
1761 if (event_log_flag == 1)
1762 iwl_dump_nic_event_log(trans, true, NULL, false);
1763
1764 return count;
1765 }
1766
1767 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1768 char __user *user_buf,
1769 size_t count, loff_t *ppos) {
1770
1771 struct iwl_trans *trans = file->private_data;
1772 struct iwl_trans_pcie *trans_pcie =
1773 IWL_TRANS_GET_PCIE_TRANS(trans);
1774 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1775
1776 int pos = 0;
1777 char *buf;
1778 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1779 ssize_t ret;
1780
1781 buf = kzalloc(bufsz, GFP_KERNEL);
1782 if (!buf) {
1783 IWL_ERR(trans, "Can not allocate Buffer\n");
1784 return -ENOMEM;
1785 }
1786
1787 pos += scnprintf(buf + pos, bufsz - pos,
1788 "Interrupt Statistics Report:\n");
1789
1790 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1791 isr_stats->hw);
1792 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1793 isr_stats->sw);
1794 if (isr_stats->sw || isr_stats->hw) {
1795 pos += scnprintf(buf + pos, bufsz - pos,
1796 "\tLast Restarting Code: 0x%X\n",
1797 isr_stats->err_code);
1798 }
1799 #ifdef CONFIG_IWLWIFI_DEBUG
1800 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1801 isr_stats->sch);
1802 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1803 isr_stats->alive);
1804 #endif
1805 pos += scnprintf(buf + pos, bufsz - pos,
1806 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1807
1808 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1809 isr_stats->ctkill);
1810
1811 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1812 isr_stats->wakeup);
1813
1814 pos += scnprintf(buf + pos, bufsz - pos,
1815 "Rx command responses:\t\t %u\n", isr_stats->rx);
1816
1817 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1818 isr_stats->tx);
1819
1820 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1821 isr_stats->unhandled);
1822
1823 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1824 kfree(buf);
1825 return ret;
1826 }
1827
1828 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1829 const char __user *user_buf,
1830 size_t count, loff_t *ppos)
1831 {
1832 struct iwl_trans *trans = file->private_data;
1833 struct iwl_trans_pcie *trans_pcie =
1834 IWL_TRANS_GET_PCIE_TRANS(trans);
1835 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1836
1837 char buf[8];
1838 int buf_size;
1839 u32 reset_flag;
1840
1841 memset(buf, 0, sizeof(buf));
1842 buf_size = min(count, sizeof(buf) - 1);
1843 if (copy_from_user(buf, user_buf, buf_size))
1844 return -EFAULT;
1845 if (sscanf(buf, "%x", &reset_flag) != 1)
1846 return -EFAULT;
1847 if (reset_flag == 0)
1848 memset(isr_stats, 0, sizeof(*isr_stats));
1849
1850 return count;
1851 }
1852
1853 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1854 const char __user *user_buf,
1855 size_t count, loff_t *ppos)
1856 {
1857 struct iwl_trans *trans = file->private_data;
1858 char buf[8];
1859 int buf_size;
1860 int csr;
1861
1862 memset(buf, 0, sizeof(buf));
1863 buf_size = min(count, sizeof(buf) - 1);
1864 if (copy_from_user(buf, user_buf, buf_size))
1865 return -EFAULT;
1866 if (sscanf(buf, "%d", &csr) != 1)
1867 return -EFAULT;
1868
1869 iwl_dump_csr(trans);
1870
1871 return count;
1872 }
1873
1874 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1875 char __user *user_buf,
1876 size_t count, loff_t *ppos)
1877 {
1878 struct iwl_trans *trans = file->private_data;
1879 char *buf;
1880 int pos = 0;
1881 ssize_t ret = -EFAULT;
1882
1883 ret = pos = iwl_dump_fh(trans, &buf, true);
1884 if (buf) {
1885 ret = simple_read_from_buffer(user_buf,
1886 count, ppos, buf, pos);
1887 kfree(buf);
1888 }
1889
1890 return ret;
1891 }
1892
1893 DEBUGFS_READ_WRITE_FILE_OPS(log_event);
1894 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1895 DEBUGFS_READ_FILE_OPS(fh_reg);
1896 DEBUGFS_READ_FILE_OPS(rx_queue);
1897 DEBUGFS_READ_FILE_OPS(tx_queue);
1898 DEBUGFS_WRITE_FILE_OPS(csr);
1899
1900 /*
1901 * Create the debugfs files and directories
1902 *
1903 */
1904 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1905 struct dentry *dir)
1906 {
1907 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1908 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1909 DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
1910 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1911 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1912 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1913 return 0;
1914 }
1915 #else
1916 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1917 struct dentry *dir)
1918 { return 0; }
1919
1920 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1921
1922 const struct iwl_trans_ops trans_ops_pcie = {
1923 .request_irq = iwl_trans_pcie_request_irq,
1924 .fw_alive = iwl_trans_pcie_fw_alive,
1925 .start_device = iwl_trans_pcie_start_device,
1926 .prepare_card_hw = iwl_trans_pcie_prepare_card_hw,
1927 .stop_device = iwl_trans_pcie_stop_device,
1928
1929 .wake_any_queue = iwl_trans_pcie_wake_any_queue,
1930
1931 .send_cmd = iwl_trans_pcie_send_cmd,
1932
1933 .tx = iwl_trans_pcie_tx,
1934 .reclaim = iwl_trans_pcie_reclaim,
1935
1936 .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
1937 .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc,
1938 .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
1939
1940 .kick_nic = iwl_trans_pcie_kick_nic,
1941
1942 .free = iwl_trans_pcie_free,
1943 .stop_queue = iwl_trans_pcie_stop_queue,
1944
1945 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1946
1947 .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
1948 .check_stuck_queue = iwl_trans_pcie_check_stuck_queue,
1949
1950 #ifdef CONFIG_PM_SLEEP
1951 .suspend = iwl_trans_pcie_suspend,
1952 .resume = iwl_trans_pcie_resume,
1953 #endif
1954 .write8 = iwl_trans_pcie_write8,
1955 .write32 = iwl_trans_pcie_write32,
1956 .read32 = iwl_trans_pcie_read32,
1957 };
1958
1959 /* PCI registers */
1960 #define PCI_CFG_RETRY_TIMEOUT 0x041
1961
1962 struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd,
1963 struct pci_dev *pdev,
1964 const struct pci_device_id *ent)
1965 {
1966 struct iwl_trans_pcie *trans_pcie;
1967 struct iwl_trans *trans;
1968 u16 pci_cmd;
1969 int err;
1970
1971 trans = kzalloc(sizeof(struct iwl_trans) +
1972 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
1973
1974 if (WARN_ON(!trans))
1975 return NULL;
1976
1977 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1978
1979 trans->ops = &trans_ops_pcie;
1980 trans->shrd = shrd;
1981 trans_pcie->trans = trans;
1982 spin_lock_init(&trans->hcmd_lock);
1983
1984 /* W/A - seems to solve weird behavior. We need to remove this if we
1985 * don't want to stay in L1 all the time. This wastes a lot of power */
1986 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
1987 PCIE_LINK_STATE_CLKPM);
1988
1989 if (pci_enable_device(pdev)) {
1990 err = -ENODEV;
1991 goto out_no_pci;
1992 }
1993
1994 pci_set_master(pdev);
1995
1996 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
1997 if (!err)
1998 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
1999 if (err) {
2000 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2001 if (!err)
2002 err = pci_set_consistent_dma_mask(pdev,
2003 DMA_BIT_MASK(32));
2004 /* both attempts failed: */
2005 if (err) {
2006 dev_printk(KERN_ERR, &pdev->dev,
2007 "No suitable DMA available.\n");
2008 goto out_pci_disable_device;
2009 }
2010 }
2011
2012 err = pci_request_regions(pdev, DRV_NAME);
2013 if (err) {
2014 dev_printk(KERN_ERR, &pdev->dev, "pci_request_regions failed");
2015 goto out_pci_disable_device;
2016 }
2017
2018 trans_pcie->hw_base = pci_iomap(pdev, 0, 0);
2019 if (!trans_pcie->hw_base) {
2020 dev_printk(KERN_ERR, &pdev->dev, "pci_iomap failed");
2021 err = -ENODEV;
2022 goto out_pci_release_regions;
2023 }
2024
2025 dev_printk(KERN_INFO, &pdev->dev,
2026 "pci_resource_len = 0x%08llx\n",
2027 (unsigned long long) pci_resource_len(pdev, 0));
2028 dev_printk(KERN_INFO, &pdev->dev,
2029 "pci_resource_base = %p\n", trans_pcie->hw_base);
2030
2031 dev_printk(KERN_INFO, &pdev->dev,
2032 "HW Revision ID = 0x%X\n", pdev->revision);
2033
2034 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2035 * PCI Tx retries from interfering with C3 CPU state */
2036 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2037
2038 err = pci_enable_msi(pdev);
2039 if (err)
2040 dev_printk(KERN_ERR, &pdev->dev,
2041 "pci_enable_msi failed(0X%x)", err);
2042
2043 trans->dev = &pdev->dev;
2044 trans->irq = pdev->irq;
2045 trans_pcie->pci_dev = pdev;
2046
2047 /* TODO: Move this away, not needed if not MSI */
2048 /* enable rfkill interrupt: hw bug w/a */
2049 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2050 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2051 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2052 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2053 }
2054
2055 return trans;
2056
2057 out_pci_release_regions:
2058 pci_release_regions(pdev);
2059 out_pci_disable_device:
2060 pci_disable_device(pdev);
2061 out_no_pci:
2062 kfree(trans);
2063 return NULL;
2064 }
2065
Linux kernel - Deliverables
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