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Merge tag 'batman-adv-for-davem' of git://git.open-mesh.org/linux-merge
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-trans-pcie.c
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63 #include <linux/pci.h>
64 #include <linux/pci-aspm.h>
65 #include <linux/interrupt.h>
66 #include <linux/debugfs.h>
67 #include <linux/sched.h>
68 #include <linux/bitops.h>
69 #include <linux/gfp.h>
70
71 #include "iwl-trans.h"
72 #include "iwl-trans-pcie-int.h"
73 #include "iwl-csr.h"
74 #include "iwl-prph.h"
75 #include "iwl-shared.h"
76 #include "iwl-eeprom.h"
77 #include "iwl-agn-hw.h"
78
79 #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
80
81 #define SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie) \
82 (((1<<cfg(trans)->base_params->num_of_queues) - 1) &\
83 (~(1<<(trans_pcie)->cmd_queue)))
84
85 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
86 {
87 struct iwl_trans_pcie *trans_pcie =
88 IWL_TRANS_GET_PCIE_TRANS(trans);
89 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
90 struct device *dev = trans->dev;
91
92 memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
93
94 spin_lock_init(&rxq->lock);
95
96 if (WARN_ON(rxq->bd || rxq->rb_stts))
97 return -EINVAL;
98
99 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
100 rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
101 &rxq->bd_dma, GFP_KERNEL);
102 if (!rxq->bd)
103 goto err_bd;
104
105 /*Allocate the driver's pointer to receive buffer status */
106 rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
107 &rxq->rb_stts_dma, GFP_KERNEL);
108 if (!rxq->rb_stts)
109 goto err_rb_stts;
110
111 return 0;
112
113 err_rb_stts:
114 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
115 rxq->bd, rxq->bd_dma);
116 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
117 rxq->bd = NULL;
118 err_bd:
119 return -ENOMEM;
120 }
121
122 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
123 {
124 struct iwl_trans_pcie *trans_pcie =
125 IWL_TRANS_GET_PCIE_TRANS(trans);
126 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
127 int i;
128
129 /* Fill the rx_used queue with _all_ of the Rx buffers */
130 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
131 /* In the reset function, these buffers may have been allocated
132 * to an SKB, so we need to unmap and free potential storage */
133 if (rxq->pool[i].page != NULL) {
134 dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
135 PAGE_SIZE << hw_params(trans).rx_page_order,
136 DMA_FROM_DEVICE);
137 __free_pages(rxq->pool[i].page,
138 hw_params(trans).rx_page_order);
139 rxq->pool[i].page = NULL;
140 }
141 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
142 }
143 }
144
145 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
146 struct iwl_rx_queue *rxq)
147 {
148 u32 rb_size;
149 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
150 u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
151
152 if (iwlagn_mod_params.amsdu_size_8K)
153 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
154 else
155 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
156
157 /* Stop Rx DMA */
158 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
159
160 /* Reset driver's Rx queue write index */
161 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
162
163 /* Tell device where to find RBD circular buffer in DRAM */
164 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
165 (u32)(rxq->bd_dma >> 8));
166
167 /* Tell device where in DRAM to update its Rx status */
168 iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
169 rxq->rb_stts_dma >> 4);
170
171 /* Enable Rx DMA
172 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
173 * the credit mechanism in 5000 HW RX FIFO
174 * Direct rx interrupts to hosts
175 * Rx buffer size 4 or 8k
176 * RB timeout 0x10
177 * 256 RBDs
178 */
179 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
180 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
181 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
182 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
183 rb_size|
184 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
185 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
186
187 /* Set interrupt coalescing timer to default (2048 usecs) */
188 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
189 }
190
191 static int iwl_rx_init(struct iwl_trans *trans)
192 {
193 struct iwl_trans_pcie *trans_pcie =
194 IWL_TRANS_GET_PCIE_TRANS(trans);
195 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
196
197 int i, err;
198 unsigned long flags;
199
200 if (!rxq->bd) {
201 err = iwl_trans_rx_alloc(trans);
202 if (err)
203 return err;
204 }
205
206 spin_lock_irqsave(&rxq->lock, flags);
207 INIT_LIST_HEAD(&rxq->rx_free);
208 INIT_LIST_HEAD(&rxq->rx_used);
209
210 iwl_trans_rxq_free_rx_bufs(trans);
211
212 for (i = 0; i < RX_QUEUE_SIZE; i++)
213 rxq->queue[i] = NULL;
214
215 /* Set us so that we have processed and used all buffers, but have
216 * not restocked the Rx queue with fresh buffers */
217 rxq->read = rxq->write = 0;
218 rxq->write_actual = 0;
219 rxq->free_count = 0;
220 spin_unlock_irqrestore(&rxq->lock, flags);
221
222 iwlagn_rx_replenish(trans);
223
224 iwl_trans_rx_hw_init(trans, rxq);
225
226 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
227 rxq->need_update = 1;
228 iwl_rx_queue_update_write_ptr(trans, rxq);
229 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
230
231 return 0;
232 }
233
234 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
235 {
236 struct iwl_trans_pcie *trans_pcie =
237 IWL_TRANS_GET_PCIE_TRANS(trans);
238 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
239
240 unsigned long flags;
241
242 /*if rxq->bd is NULL, it means that nothing has been allocated,
243 * exit now */
244 if (!rxq->bd) {
245 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
246 return;
247 }
248
249 spin_lock_irqsave(&rxq->lock, flags);
250 iwl_trans_rxq_free_rx_bufs(trans);
251 spin_unlock_irqrestore(&rxq->lock, flags);
252
253 dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
254 rxq->bd, rxq->bd_dma);
255 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
256 rxq->bd = NULL;
257
258 if (rxq->rb_stts)
259 dma_free_coherent(trans->dev,
260 sizeof(struct iwl_rb_status),
261 rxq->rb_stts, rxq->rb_stts_dma);
262 else
263 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
264 memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
265 rxq->rb_stts = NULL;
266 }
267
268 static int iwl_trans_rx_stop(struct iwl_trans *trans)
269 {
270
271 /* stop Rx DMA */
272 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
273 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
274 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
275 }
276
277 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
278 struct iwl_dma_ptr *ptr, size_t size)
279 {
280 if (WARN_ON(ptr->addr))
281 return -EINVAL;
282
283 ptr->addr = dma_alloc_coherent(trans->dev, size,
284 &ptr->dma, GFP_KERNEL);
285 if (!ptr->addr)
286 return -ENOMEM;
287 ptr->size = size;
288 return 0;
289 }
290
291 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
292 struct iwl_dma_ptr *ptr)
293 {
294 if (unlikely(!ptr->addr))
295 return;
296
297 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
298 memset(ptr, 0, sizeof(*ptr));
299 }
300
301 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
302 struct iwl_tx_queue *txq, int slots_num,
303 u32 txq_id)
304 {
305 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
306 int i;
307 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
308
309 if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds))
310 return -EINVAL;
311
312 txq->q.n_window = slots_num;
313
314 txq->meta = kcalloc(slots_num, sizeof(txq->meta[0]), GFP_KERNEL);
315 txq->cmd = kcalloc(slots_num, sizeof(txq->cmd[0]), GFP_KERNEL);
316
317 if (!txq->meta || !txq->cmd)
318 goto error;
319
320 if (txq_id == trans_pcie->cmd_queue)
321 for (i = 0; i < slots_num; i++) {
322 txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
323 GFP_KERNEL);
324 if (!txq->cmd[i])
325 goto error;
326 }
327
328 /* Alloc driver data array and TFD circular buffer */
329 /* Driver private data, only for Tx (not command) queues,
330 * not shared with device. */
331 if (txq_id != trans_pcie->cmd_queue) {
332 txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->skbs[0]),
333 GFP_KERNEL);
334 if (!txq->skbs) {
335 IWL_ERR(trans, "kmalloc for auxiliary BD "
336 "structures failed\n");
337 goto error;
338 }
339 } else {
340 txq->skbs = NULL;
341 }
342
343 /* Circular buffer of transmit frame descriptors (TFDs),
344 * shared with device */
345 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
346 &txq->q.dma_addr, GFP_KERNEL);
347 if (!txq->tfds) {
348 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
349 goto error;
350 }
351 txq->q.id = txq_id;
352
353 return 0;
354 error:
355 kfree(txq->skbs);
356 txq->skbs = NULL;
357 /* since txq->cmd has been zeroed,
358 * all non allocated cmd[i] will be NULL */
359 if (txq->cmd && txq_id == trans_pcie->cmd_queue)
360 for (i = 0; i < slots_num; i++)
361 kfree(txq->cmd[i]);
362 kfree(txq->meta);
363 kfree(txq->cmd);
364 txq->meta = NULL;
365 txq->cmd = NULL;
366
367 return -ENOMEM;
368
369 }
370
371 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
372 int slots_num, u32 txq_id)
373 {
374 int ret;
375
376 txq->need_update = 0;
377 memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
378
379 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
380 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
381 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
382
383 /* Initialize queue's high/low-water marks, and head/tail indexes */
384 ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
385 txq_id);
386 if (ret)
387 return ret;
388
389 spin_lock_init(&txq->lock);
390
391 /*
392 * Tell nic where to find circular buffer of Tx Frame Descriptors for
393 * given Tx queue, and enable the DMA channel used for that queue.
394 * Circular buffer (TFD queue in DRAM) physical base address */
395 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
396 txq->q.dma_addr >> 8);
397
398 return 0;
399 }
400
401 /**
402 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
403 */
404 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
405 {
406 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
407 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
408 struct iwl_queue *q = &txq->q;
409 enum dma_data_direction dma_dir;
410
411 if (!q->n_bd)
412 return;
413
414 /* In the command queue, all the TBs are mapped as BIDI
415 * so unmap them as such.
416 */
417 if (txq_id == trans_pcie->cmd_queue)
418 dma_dir = DMA_BIDIRECTIONAL;
419 else
420 dma_dir = DMA_TO_DEVICE;
421
422 spin_lock_bh(&txq->lock);
423 while (q->write_ptr != q->read_ptr) {
424 /* The read_ptr needs to bound by q->n_window */
425 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr),
426 dma_dir);
427 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
428 }
429 spin_unlock_bh(&txq->lock);
430 }
431
432 /**
433 * iwl_tx_queue_free - Deallocate DMA queue.
434 * @txq: Transmit queue to deallocate.
435 *
436 * Empty queue by removing and destroying all BD's.
437 * Free all buffers.
438 * 0-fill, but do not free "txq" descriptor structure.
439 */
440 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
441 {
442 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
443 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
444 struct device *dev = trans->dev;
445 int i;
446 if (WARN_ON(!txq))
447 return;
448
449 iwl_tx_queue_unmap(trans, txq_id);
450
451 /* De-alloc array of command/tx buffers */
452
453 if (txq_id == trans_pcie->cmd_queue)
454 for (i = 0; i < txq->q.n_window; i++)
455 kfree(txq->cmd[i]);
456
457 /* De-alloc circular buffer of TFDs */
458 if (txq->q.n_bd) {
459 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
460 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
461 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
462 }
463
464 /* De-alloc array of per-TFD driver data */
465 kfree(txq->skbs);
466 txq->skbs = NULL;
467
468 /* deallocate arrays */
469 kfree(txq->cmd);
470 kfree(txq->meta);
471 txq->cmd = NULL;
472 txq->meta = NULL;
473
474 /* 0-fill queue descriptor structure */
475 memset(txq, 0, sizeof(*txq));
476 }
477
478 /**
479 * iwl_trans_tx_free - Free TXQ Context
480 *
481 * Destroy all TX DMA queues and structures
482 */
483 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
484 {
485 int txq_id;
486 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
487
488 /* Tx queues */
489 if (trans_pcie->txq) {
490 for (txq_id = 0;
491 txq_id < cfg(trans)->base_params->num_of_queues; txq_id++)
492 iwl_tx_queue_free(trans, txq_id);
493 }
494
495 kfree(trans_pcie->txq);
496 trans_pcie->txq = NULL;
497
498 iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
499
500 iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
501 }
502
503 /**
504 * iwl_trans_tx_alloc - allocate TX context
505 * Allocate all Tx DMA structures and initialize them
506 *
507 * @param priv
508 * @return error code
509 */
510 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
511 {
512 int ret;
513 int txq_id, slots_num;
514 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
515
516 u16 scd_bc_tbls_size = cfg(trans)->base_params->num_of_queues *
517 sizeof(struct iwlagn_scd_bc_tbl);
518
519 /*It is not allowed to alloc twice, so warn when this happens.
520 * We cannot rely on the previous allocation, so free and fail */
521 if (WARN_ON(trans_pcie->txq)) {
522 ret = -EINVAL;
523 goto error;
524 }
525
526 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
527 scd_bc_tbls_size);
528 if (ret) {
529 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
530 goto error;
531 }
532
533 /* Alloc keep-warm buffer */
534 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
535 if (ret) {
536 IWL_ERR(trans, "Keep Warm allocation failed\n");
537 goto error;
538 }
539
540 trans_pcie->txq = kcalloc(cfg(trans)->base_params->num_of_queues,
541 sizeof(struct iwl_tx_queue), GFP_KERNEL);
542 if (!trans_pcie->txq) {
543 IWL_ERR(trans, "Not enough memory for txq\n");
544 ret = ENOMEM;
545 goto error;
546 }
547
548 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
549 for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues;
550 txq_id++) {
551 slots_num = (txq_id == trans_pcie->cmd_queue) ?
552 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
553 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
554 slots_num, txq_id);
555 if (ret) {
556 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
557 goto error;
558 }
559 }
560
561 return 0;
562
563 error:
564 iwl_trans_pcie_tx_free(trans);
565
566 return ret;
567 }
568 static int iwl_tx_init(struct iwl_trans *trans)
569 {
570 int ret;
571 int txq_id, slots_num;
572 unsigned long flags;
573 bool alloc = false;
574 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
575
576 if (!trans_pcie->txq) {
577 ret = iwl_trans_tx_alloc(trans);
578 if (ret)
579 goto error;
580 alloc = true;
581 }
582
583 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
584
585 /* Turn off all Tx DMA fifos */
586 iwl_write_prph(trans, SCD_TXFACT, 0);
587
588 /* Tell NIC where to find the "keep warm" buffer */
589 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
590 trans_pcie->kw.dma >> 4);
591
592 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
593
594 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
595 for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues;
596 txq_id++) {
597 slots_num = (txq_id == trans_pcie->cmd_queue) ?
598 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
599 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
600 slots_num, txq_id);
601 if (ret) {
602 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
603 goto error;
604 }
605 }
606
607 return 0;
608 error:
609 /*Upon error, free only if we allocated something */
610 if (alloc)
611 iwl_trans_pcie_tx_free(trans);
612 return ret;
613 }
614
615 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
616 {
617 /*
618 * (for documentation purposes)
619 * to set power to V_AUX, do:
620
621 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
622 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
623 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
624 ~APMG_PS_CTRL_MSK_PWR_SRC);
625 */
626
627 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
628 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
629 ~APMG_PS_CTRL_MSK_PWR_SRC);
630 }
631
632 /* PCI registers */
633 #define PCI_CFG_RETRY_TIMEOUT 0x041
634 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
635 #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
636
637 static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
638 {
639 int pos;
640 u16 pci_lnk_ctl;
641 struct iwl_trans_pcie *trans_pcie =
642 IWL_TRANS_GET_PCIE_TRANS(trans);
643
644 struct pci_dev *pci_dev = trans_pcie->pci_dev;
645
646 pos = pci_pcie_cap(pci_dev);
647 pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
648 return pci_lnk_ctl;
649 }
650
651 static void iwl_apm_config(struct iwl_trans *trans)
652 {
653 /*
654 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
655 * Check if BIOS (or OS) enabled L1-ASPM on this device.
656 * If so (likely), disable L0S, so device moves directly L0->L1;
657 * costs negligible amount of power savings.
658 * If not (unlikely), enable L0S, so there is at least some
659 * power savings, even without L1.
660 */
661 u16 lctl = iwl_pciexp_link_ctrl(trans);
662
663 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
664 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
665 /* L1-ASPM enabled; disable(!) L0S */
666 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
667 dev_printk(KERN_INFO, trans->dev,
668 "L1 Enabled; Disabling L0S\n");
669 } else {
670 /* L1-ASPM disabled; enable(!) L0S */
671 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
672 dev_printk(KERN_INFO, trans->dev,
673 "L1 Disabled; Enabling L0S\n");
674 }
675 trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
676 }
677
678 /*
679 * Start up NIC's basic functionality after it has been reset
680 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
681 * NOTE: This does not load uCode nor start the embedded processor
682 */
683 static int iwl_apm_init(struct iwl_trans *trans)
684 {
685 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
686 int ret = 0;
687 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
688
689 /*
690 * Use "set_bit" below rather than "write", to preserve any hardware
691 * bits already set by default after reset.
692 */
693
694 /* Disable L0S exit timer (platform NMI Work/Around) */
695 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
696 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
697
698 /*
699 * Disable L0s without affecting L1;
700 * don't wait for ICH L0s (ICH bug W/A)
701 */
702 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
703 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
704
705 /* Set FH wait threshold to maximum (HW error during stress W/A) */
706 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
707
708 /*
709 * Enable HAP INTA (interrupt from management bus) to
710 * wake device's PCI Express link L1a -> L0s
711 */
712 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
713 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
714
715 iwl_apm_config(trans);
716
717 /* Configure analog phase-lock-loop before activating to D0A */
718 if (cfg(trans)->base_params->pll_cfg_val)
719 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
720 cfg(trans)->base_params->pll_cfg_val);
721
722 /*
723 * Set "initialization complete" bit to move adapter from
724 * D0U* --> D0A* (powered-up active) state.
725 */
726 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
727
728 /*
729 * Wait for clock stabilization; once stabilized, access to
730 * device-internal resources is supported, e.g. iwl_write_prph()
731 * and accesses to uCode SRAM.
732 */
733 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
734 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
735 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
736 if (ret < 0) {
737 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
738 goto out;
739 }
740
741 /*
742 * Enable DMA clock and wait for it to stabilize.
743 *
744 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
745 * do not disable clocks. This preserves any hardware bits already
746 * set by default in "CLK_CTRL_REG" after reset.
747 */
748 iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
749 udelay(20);
750
751 /* Disable L1-Active */
752 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
753 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
754
755 set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
756
757 out:
758 return ret;
759 }
760
761 static int iwl_apm_stop_master(struct iwl_trans *trans)
762 {
763 int ret = 0;
764
765 /* stop device's busmaster DMA activity */
766 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
767
768 ret = iwl_poll_bit(trans, CSR_RESET,
769 CSR_RESET_REG_FLAG_MASTER_DISABLED,
770 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
771 if (ret)
772 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
773
774 IWL_DEBUG_INFO(trans, "stop master\n");
775
776 return ret;
777 }
778
779 static void iwl_apm_stop(struct iwl_trans *trans)
780 {
781 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
782 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
783
784 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
785
786 /* Stop device's DMA activity */
787 iwl_apm_stop_master(trans);
788
789 /* Reset the entire device */
790 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
791
792 udelay(10);
793
794 /*
795 * Clear "initialization complete" bit to move adapter from
796 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
797 */
798 iwl_clear_bit(trans, CSR_GP_CNTRL,
799 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
800 }
801
802 static int iwl_nic_init(struct iwl_trans *trans)
803 {
804 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
805 unsigned long flags;
806
807 /* nic_init */
808 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
809 iwl_apm_init(trans);
810
811 /* Set interrupt coalescing calibration timer to default (512 usecs) */
812 iwl_write8(trans, CSR_INT_COALESCING,
813 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
814
815 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
816
817 iwl_set_pwr_vmain(trans);
818
819 iwl_op_mode_nic_config(trans->op_mode);
820
821 #ifndef CONFIG_IWLWIFI_IDI
822 /* Allocate the RX queue, or reset if it is already allocated */
823 iwl_rx_init(trans);
824 #endif
825
826 /* Allocate or reset and init all Tx and Command queues */
827 if (iwl_tx_init(trans))
828 return -ENOMEM;
829
830 if (cfg(trans)->base_params->shadow_reg_enable) {
831 /* enable shadow regs in HW */
832 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL,
833 0x800FFFFF);
834 }
835
836 return 0;
837 }
838
839 #define HW_READY_TIMEOUT (50)
840
841 /* Note: returns poll_bit return value, which is >= 0 if success */
842 static int iwl_set_hw_ready(struct iwl_trans *trans)
843 {
844 int ret;
845
846 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
847 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
848
849 /* See if we got it */
850 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
851 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
852 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
853 HW_READY_TIMEOUT);
854
855 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
856 return ret;
857 }
858
859 /* Note: returns standard 0/-ERROR code */
860 static int iwl_prepare_card_hw(struct iwl_trans *trans)
861 {
862 int ret;
863
864 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
865
866 ret = iwl_set_hw_ready(trans);
867 /* If the card is ready, exit 0 */
868 if (ret >= 0)
869 return 0;
870
871 /* If HW is not ready, prepare the conditions to check again */
872 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
873 CSR_HW_IF_CONFIG_REG_PREPARE);
874
875 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
876 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
877 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
878
879 if (ret < 0)
880 return ret;
881
882 /* HW should be ready by now, check again. */
883 ret = iwl_set_hw_ready(trans);
884 if (ret >= 0)
885 return 0;
886 return ret;
887 }
888
889 /*
890 * ucode
891 */
892 static int iwl_load_section(struct iwl_trans *trans, u8 section_num,
893 const struct fw_desc *section)
894 {
895 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
896 dma_addr_t phy_addr = section->p_addr;
897 u32 byte_cnt = section->len;
898 u32 dst_addr = section->offset;
899 int ret;
900
901 trans_pcie->ucode_write_complete = false;
902
903 iwl_write_direct32(trans,
904 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
905 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
906
907 iwl_write_direct32(trans,
908 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
909
910 iwl_write_direct32(trans,
911 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
912 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
913
914 iwl_write_direct32(trans,
915 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
916 (iwl_get_dma_hi_addr(phy_addr)
917 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
918
919 iwl_write_direct32(trans,
920 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
921 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
922 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
923 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
924
925 iwl_write_direct32(trans,
926 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
927 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
928 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
929 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
930
931 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
932 section_num);
933 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
934 trans_pcie->ucode_write_complete, 5 * HZ);
935 if (!ret) {
936 IWL_ERR(trans, "Could not load the [%d] uCode section\n",
937 section_num);
938 return -ETIMEDOUT;
939 }
940
941 return 0;
942 }
943
944 static int iwl_load_given_ucode(struct iwl_trans *trans,
945 const struct fw_img *image)
946 {
947 int ret = 0;
948 int i;
949
950 for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
951 if (!image->sec[i].p_addr)
952 break;
953
954 ret = iwl_load_section(trans, i, &image->sec[i]);
955 if (ret)
956 return ret;
957 }
958
959 /* Remove all resets to allow NIC to operate */
960 iwl_write32(trans, CSR_RESET, 0);
961
962 return 0;
963 }
964
965 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
966 const struct fw_img *fw)
967 {
968 int ret;
969 bool hw_rfkill;
970
971 /* This may fail if AMT took ownership of the device */
972 if (iwl_prepare_card_hw(trans)) {
973 IWL_WARN(trans, "Exit HW not ready\n");
974 return -EIO;
975 }
976
977 /* If platform's RF_KILL switch is NOT set to KILL */
978 hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
979 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
980 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
981
982 if (hw_rfkill) {
983 iwl_enable_rfkill_int(trans);
984 return -ERFKILL;
985 }
986
987 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
988
989 ret = iwl_nic_init(trans);
990 if (ret) {
991 IWL_ERR(trans, "Unable to init nic\n");
992 return ret;
993 }
994
995 /* make sure rfkill handshake bits are cleared */
996 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
997 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
998 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
999
1000 /* clear (again), then enable host interrupts */
1001 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1002 iwl_enable_interrupts(trans);
1003
1004 /* really make sure rfkill handshake bits are cleared */
1005 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1006 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1007
1008 /* Load the given image to the HW */
1009 return iwl_load_given_ucode(trans, fw);
1010 }
1011
1012 /*
1013 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1014 * must be called under the irq lock and with MAC access
1015 */
1016 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
1017 {
1018 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1019 IWL_TRANS_GET_PCIE_TRANS(trans);
1020
1021 lockdep_assert_held(&trans_pcie->irq_lock);
1022
1023 iwl_write_prph(trans, SCD_TXFACT, mask);
1024 }
1025
1026 static void iwl_tx_start(struct iwl_trans *trans)
1027 {
1028 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1029 u32 a;
1030 unsigned long flags;
1031 int i, chan;
1032 u32 reg_val;
1033
1034 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1035
1036 trans_pcie->scd_base_addr =
1037 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
1038 a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
1039 /* reset conext data memory */
1040 for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
1041 a += 4)
1042 iwl_write_targ_mem(trans, a, 0);
1043 /* reset tx status memory */
1044 for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
1045 a += 4)
1046 iwl_write_targ_mem(trans, a, 0);
1047 for (; a < trans_pcie->scd_base_addr +
1048 SCD_TRANS_TBL_OFFSET_QUEUE(
1049 cfg(trans)->base_params->num_of_queues);
1050 a += 4)
1051 iwl_write_targ_mem(trans, a, 0);
1052
1053 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
1054 trans_pcie->scd_bc_tbls.dma >> 10);
1055
1056 /* Enable DMA channel */
1057 for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
1058 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1059 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1060 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1061
1062 /* Update FH chicken bits */
1063 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
1064 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1065 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1066
1067 iwl_write_prph(trans, SCD_QUEUECHAIN_SEL,
1068 SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie));
1069 iwl_write_prph(trans, SCD_AGGR_SEL, 0);
1070
1071 /* initiate the queues */
1072 for (i = 0; i < cfg(trans)->base_params->num_of_queues; i++) {
1073 iwl_write_prph(trans, SCD_QUEUE_RDPTR(i), 0);
1074 iwl_write_direct32(trans, HBUS_TARG_WRPTR, 0 | (i << 8));
1075 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1076 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
1077 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1078 SCD_CONTEXT_QUEUE_OFFSET(i) +
1079 sizeof(u32),
1080 ((SCD_WIN_SIZE <<
1081 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1082 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1083 ((SCD_FRAME_LIMIT <<
1084 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1085 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1086 }
1087
1088 iwl_write_prph(trans, SCD_INTERRUPT_MASK,
1089 IWL_MASK(0, cfg(trans)->base_params->num_of_queues));
1090
1091 /* Activate all Tx DMA/FIFO channels */
1092 iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
1093
1094 iwl_trans_set_wr_ptrs(trans, trans_pcie->cmd_queue, 0);
1095
1096 /* make sure all queue are not stopped/used */
1097 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
1098 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
1099
1100 for (i = 0; i < trans_pcie->n_q_to_fifo; i++) {
1101 int fifo = trans_pcie->setup_q_to_fifo[i];
1102
1103 set_bit(i, trans_pcie->queue_used);
1104
1105 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
1106 fifo, true);
1107 }
1108
1109 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1110
1111 /* Enable L1-Active */
1112 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1113 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1114 }
1115
1116 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
1117 {
1118 iwl_reset_ict(trans);
1119 iwl_tx_start(trans);
1120 }
1121
1122 /**
1123 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1124 */
1125 static int iwl_trans_tx_stop(struct iwl_trans *trans)
1126 {
1127 int ch, txq_id, ret;
1128 unsigned long flags;
1129 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1130
1131 /* Turn off all Tx DMA fifos */
1132 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1133
1134 iwl_trans_txq_set_sched(trans, 0);
1135
1136 /* Stop each Tx DMA channel, and wait for it to be idle */
1137 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
1138 iwl_write_direct32(trans,
1139 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
1140 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
1141 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
1142 1000);
1143 if (ret < 0)
1144 IWL_ERR(trans, "Failing on timeout while stopping"
1145 " DMA channel %d [0x%08x]", ch,
1146 iwl_read_direct32(trans,
1147 FH_TSSR_TX_STATUS_REG));
1148 }
1149 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1150
1151 if (!trans_pcie->txq) {
1152 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
1153 return 0;
1154 }
1155
1156 /* Unmap DMA from host system and free skb's */
1157 for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues;
1158 txq_id++)
1159 iwl_tx_queue_unmap(trans, txq_id);
1160
1161 return 0;
1162 }
1163
1164 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1165 {
1166 unsigned long flags;
1167 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1168
1169 /* tell the device to stop sending interrupts */
1170 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1171 iwl_disable_interrupts(trans);
1172 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1173
1174 /* device going down, Stop using ICT table */
1175 iwl_disable_ict(trans);
1176
1177 /*
1178 * If a HW restart happens during firmware loading,
1179 * then the firmware loading might call this function
1180 * and later it might be called again due to the
1181 * restart. So don't process again if the device is
1182 * already dead.
1183 */
1184 if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
1185 iwl_trans_tx_stop(trans);
1186 #ifndef CONFIG_IWLWIFI_IDI
1187 iwl_trans_rx_stop(trans);
1188 #endif
1189 /* Power-down device's busmaster DMA clocks */
1190 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1191 APMG_CLK_VAL_DMA_CLK_RQT);
1192 udelay(5);
1193 }
1194
1195 /* Make sure (redundant) we've released our request to stay awake */
1196 iwl_clear_bit(trans, CSR_GP_CNTRL,
1197 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1198
1199 /* Stop the device, and put it in low power state */
1200 iwl_apm_stop(trans);
1201
1202 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1203 * Clean again the interrupt here
1204 */
1205 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1206 iwl_disable_interrupts(trans);
1207 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1208
1209 /* wait to make sure we flush pending tasklet*/
1210 synchronize_irq(trans_pcie->irq);
1211 tasklet_kill(&trans_pcie->irq_tasklet);
1212
1213 cancel_work_sync(&trans_pcie->rx_replenish);
1214
1215 /* stop and reset the on-board processor */
1216 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1217 }
1218
1219 static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
1220 {
1221 /* let the ucode operate on its own */
1222 iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
1223 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
1224
1225 iwl_disable_interrupts(trans);
1226 iwl_clear_bit(trans, CSR_GP_CNTRL,
1227 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1228 }
1229
1230 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1231 struct iwl_device_cmd *dev_cmd, int txq_id)
1232 {
1233 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1234 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1235 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1236 struct iwl_cmd_meta *out_meta;
1237 struct iwl_tx_queue *txq;
1238 struct iwl_queue *q;
1239 dma_addr_t phys_addr = 0;
1240 dma_addr_t txcmd_phys;
1241 dma_addr_t scratch_phys;
1242 u16 len, firstlen, secondlen;
1243 u8 wait_write_ptr = 0;
1244 __le16 fc = hdr->frame_control;
1245 u8 hdr_len = ieee80211_hdrlen(fc);
1246 u16 __maybe_unused wifi_seq;
1247
1248 txq = &trans_pcie->txq[txq_id];
1249 q = &txq->q;
1250
1251 if (unlikely(!test_bit(txq_id, trans_pcie->queue_used))) {
1252 WARN_ON_ONCE(1);
1253 return -EINVAL;
1254 }
1255
1256 spin_lock(&txq->lock);
1257
1258 /* Set up driver data for this TFD */
1259 txq->skbs[q->write_ptr] = skb;
1260 txq->cmd[q->write_ptr] = dev_cmd;
1261
1262 dev_cmd->hdr.cmd = REPLY_TX;
1263 dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1264 INDEX_TO_SEQ(q->write_ptr)));
1265
1266 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1267 out_meta = &txq->meta[q->write_ptr];
1268
1269 /*
1270 * Use the first empty entry in this queue's command buffer array
1271 * to contain the Tx command and MAC header concatenated together
1272 * (payload data will be in another buffer).
1273 * Size of this varies, due to varying MAC header length.
1274 * If end is not dword aligned, we'll have 2 extra bytes at the end
1275 * of the MAC header (device reads on dword boundaries).
1276 * We'll tell device about this padding later.
1277 */
1278 len = sizeof(struct iwl_tx_cmd) +
1279 sizeof(struct iwl_cmd_header) + hdr_len;
1280 firstlen = (len + 3) & ~3;
1281
1282 /* Tell NIC about any 2-byte padding after MAC header */
1283 if (firstlen != len)
1284 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1285
1286 /* Physical address of this Tx command's header (not MAC header!),
1287 * within command buffer array. */
1288 txcmd_phys = dma_map_single(trans->dev,
1289 &dev_cmd->hdr, firstlen,
1290 DMA_BIDIRECTIONAL);
1291 if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1292 goto out_err;
1293 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1294 dma_unmap_len_set(out_meta, len, firstlen);
1295
1296 if (!ieee80211_has_morefrags(fc)) {
1297 txq->need_update = 1;
1298 } else {
1299 wait_write_ptr = 1;
1300 txq->need_update = 0;
1301 }
1302
1303 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1304 * if any (802.11 null frames have no payload). */
1305 secondlen = skb->len - hdr_len;
1306 if (secondlen > 0) {
1307 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1308 secondlen, DMA_TO_DEVICE);
1309 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1310 dma_unmap_single(trans->dev,
1311 dma_unmap_addr(out_meta, mapping),
1312 dma_unmap_len(out_meta, len),
1313 DMA_BIDIRECTIONAL);
1314 goto out_err;
1315 }
1316 }
1317
1318 /* Attach buffers to TFD */
1319 iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1320 if (secondlen > 0)
1321 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1322 secondlen, 0);
1323
1324 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1325 offsetof(struct iwl_tx_cmd, scratch);
1326
1327 /* take back ownership of DMA buffer to enable update */
1328 dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1329 DMA_BIDIRECTIONAL);
1330 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1331 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1332
1333 IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1334 le16_to_cpu(dev_cmd->hdr.sequence));
1335 IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1336
1337 /* Set up entry for this TFD in Tx byte-count array */
1338 iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1339
1340 dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1341 DMA_BIDIRECTIONAL);
1342
1343 trace_iwlwifi_dev_tx(trans->dev,
1344 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1345 sizeof(struct iwl_tfd),
1346 &dev_cmd->hdr, firstlen,
1347 skb->data + hdr_len, secondlen);
1348
1349 /* Tell device the write index *just past* this latest filled TFD */
1350 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1351 iwl_txq_update_write_ptr(trans, txq);
1352
1353 /*
1354 * At this point the frame is "transmitted" successfully
1355 * and we will get a TX status notification eventually,
1356 * regardless of the value of ret. "ret" only indicates
1357 * whether or not we should update the write pointer.
1358 */
1359 if (iwl_queue_space(q) < q->high_mark) {
1360 if (wait_write_ptr) {
1361 txq->need_update = 1;
1362 iwl_txq_update_write_ptr(trans, txq);
1363 } else {
1364 iwl_stop_queue(trans, txq);
1365 }
1366 }
1367 spin_unlock(&txq->lock);
1368 return 0;
1369 out_err:
1370 spin_unlock(&txq->lock);
1371 return -1;
1372 }
1373
1374 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1375 {
1376 struct iwl_trans_pcie *trans_pcie =
1377 IWL_TRANS_GET_PCIE_TRANS(trans);
1378 int err;
1379 bool hw_rfkill;
1380
1381 trans_pcie->inta_mask = CSR_INI_SET_MASK;
1382
1383 if (!trans_pcie->irq_requested) {
1384 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1385 iwl_irq_tasklet, (unsigned long)trans);
1386
1387 iwl_alloc_isr_ict(trans);
1388
1389 err = request_irq(trans_pcie->irq, iwl_isr_ict, IRQF_SHARED,
1390 DRV_NAME, trans);
1391 if (err) {
1392 IWL_ERR(trans, "Error allocating IRQ %d\n",
1393 trans_pcie->irq);
1394 goto error;
1395 }
1396
1397 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1398 trans_pcie->irq_requested = true;
1399 }
1400
1401 err = iwl_prepare_card_hw(trans);
1402 if (err) {
1403 IWL_ERR(trans, "Error while preparing HW: %d", err);
1404 goto err_free_irq;
1405 }
1406
1407 iwl_apm_init(trans);
1408
1409 hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
1410 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1411 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1412
1413 return err;
1414
1415 err_free_irq:
1416 free_irq(trans_pcie->irq, trans);
1417 error:
1418 iwl_free_isr_ict(trans);
1419 tasklet_kill(&trans_pcie->irq_tasklet);
1420 return err;
1421 }
1422
1423 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans)
1424 {
1425 iwl_apm_stop(trans);
1426
1427 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1428
1429 /* Even if we stop the HW, we still want the RF kill interrupt */
1430 iwl_enable_rfkill_int(trans);
1431 }
1432
1433 static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
1434 struct sk_buff_head *skbs)
1435 {
1436 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1437 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1438 /* n_bd is usually 256 => n_bd - 1 = 0xff */
1439 int tfd_num = ssn & (txq->q.n_bd - 1);
1440 int freed = 0;
1441
1442 spin_lock(&txq->lock);
1443
1444 txq->time_stamp = jiffies;
1445
1446 if (txq->q.read_ptr != tfd_num) {
1447 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
1448 txq_id, txq->q.read_ptr, tfd_num, ssn);
1449 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1450 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1451 iwl_wake_queue(trans, txq);
1452 }
1453
1454 spin_unlock(&txq->lock);
1455 }
1456
1457 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1458 {
1459 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1460 }
1461
1462 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1463 {
1464 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1465 }
1466
1467 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1468 {
1469 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1470 }
1471
1472 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1473 const struct iwl_trans_config *trans_cfg)
1474 {
1475 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1476
1477 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1478 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1479 trans_pcie->n_no_reclaim_cmds = 0;
1480 else
1481 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1482 if (trans_pcie->n_no_reclaim_cmds)
1483 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1484 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1485
1486 trans_pcie->n_q_to_fifo = trans_cfg->n_queue_to_fifo;
1487
1488 if (WARN_ON(trans_pcie->n_q_to_fifo > IWL_MAX_HW_QUEUES))
1489 trans_pcie->n_q_to_fifo = IWL_MAX_HW_QUEUES;
1490
1491 /* at least the command queue must be mapped */
1492 WARN_ON(!trans_pcie->n_q_to_fifo);
1493
1494 memcpy(trans_pcie->setup_q_to_fifo, trans_cfg->queue_to_fifo,
1495 trans_pcie->n_q_to_fifo * sizeof(u8));
1496 }
1497
1498 static void iwl_trans_pcie_free(struct iwl_trans *trans)
1499 {
1500 struct iwl_trans_pcie *trans_pcie =
1501 IWL_TRANS_GET_PCIE_TRANS(trans);
1502
1503 iwl_trans_pcie_tx_free(trans);
1504 #ifndef CONFIG_IWLWIFI_IDI
1505 iwl_trans_pcie_rx_free(trans);
1506 #endif
1507 if (trans_pcie->irq_requested == true) {
1508 free_irq(trans_pcie->irq, trans);
1509 iwl_free_isr_ict(trans);
1510 }
1511
1512 pci_disable_msi(trans_pcie->pci_dev);
1513 iounmap(trans_pcie->hw_base);
1514 pci_release_regions(trans_pcie->pci_dev);
1515 pci_disable_device(trans_pcie->pci_dev);
1516
1517 trans->shrd->trans = NULL;
1518 kfree(trans);
1519 }
1520
1521 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1522 {
1523 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1524
1525 if (state)
1526 set_bit(STATUS_POWER_PMI, &trans_pcie->status);
1527 else
1528 clear_bit(STATUS_POWER_PMI, &trans_pcie->status);
1529 }
1530
1531 #ifdef CONFIG_PM_SLEEP
1532 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1533 {
1534 return 0;
1535 }
1536
1537 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1538 {
1539 bool hw_rfkill;
1540
1541 hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
1542 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1543
1544 if (hw_rfkill)
1545 iwl_enable_rfkill_int(trans);
1546 else
1547 iwl_enable_interrupts(trans);
1548
1549 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1550
1551 return 0;
1552 }
1553 #endif /* CONFIG_PM_SLEEP */
1554
1555 #define IWL_FLUSH_WAIT_MS 2000
1556
1557 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1558 {
1559 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1560 struct iwl_tx_queue *txq;
1561 struct iwl_queue *q;
1562 int cnt;
1563 unsigned long now = jiffies;
1564 int ret = 0;
1565
1566 /* waiting for all the tx frames complete might take a while */
1567 for (cnt = 0; cnt < cfg(trans)->base_params->num_of_queues; cnt++) {
1568 if (cnt == trans_pcie->cmd_queue)
1569 continue;
1570 txq = &trans_pcie->txq[cnt];
1571 q = &txq->q;
1572 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1573 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1574 msleep(1);
1575
1576 if (q->read_ptr != q->write_ptr) {
1577 IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1578 ret = -ETIMEDOUT;
1579 break;
1580 }
1581 }
1582 return ret;
1583 }
1584
1585 /*
1586 * On every watchdog tick we check (latest) time stamp. If it does not
1587 * change during timeout period and queue is not empty we reset firmware.
1588 */
1589 static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt)
1590 {
1591 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1592 struct iwl_tx_queue *txq = &trans_pcie->txq[cnt];
1593 struct iwl_queue *q = &txq->q;
1594 unsigned long timeout;
1595
1596 if (q->read_ptr == q->write_ptr) {
1597 txq->time_stamp = jiffies;
1598 return 0;
1599 }
1600
1601 timeout = txq->time_stamp +
1602 msecs_to_jiffies(hw_params(trans).wd_timeout);
1603
1604 if (time_after(jiffies, timeout)) {
1605 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id,
1606 hw_params(trans).wd_timeout);
1607 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1608 q->read_ptr, q->write_ptr);
1609 IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n",
1610 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt))
1611 & (TFD_QUEUE_SIZE_MAX - 1),
1612 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1613 return 1;
1614 }
1615
1616 return 0;
1617 }
1618
1619 static const char *get_fh_string(int cmd)
1620 {
1621 switch (cmd) {
1622 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1623 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1624 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1625 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1626 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1627 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1628 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1629 IWL_CMD(FH_TSSR_TX_STATUS_REG);
1630 IWL_CMD(FH_TSSR_TX_ERROR_REG);
1631 default:
1632 return "UNKNOWN";
1633 }
1634 }
1635
1636 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1637 {
1638 int i;
1639 #ifdef CONFIG_IWLWIFI_DEBUG
1640 int pos = 0;
1641 size_t bufsz = 0;
1642 #endif
1643 static const u32 fh_tbl[] = {
1644 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1645 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1646 FH_RSCSR_CHNL0_WPTR,
1647 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1648 FH_MEM_RSSR_SHARED_CTRL_REG,
1649 FH_MEM_RSSR_RX_STATUS_REG,
1650 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1651 FH_TSSR_TX_STATUS_REG,
1652 FH_TSSR_TX_ERROR_REG
1653 };
1654 #ifdef CONFIG_IWLWIFI_DEBUG
1655 if (display) {
1656 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1657 *buf = kmalloc(bufsz, GFP_KERNEL);
1658 if (!*buf)
1659 return -ENOMEM;
1660 pos += scnprintf(*buf + pos, bufsz - pos,
1661 "FH register values:\n");
1662 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1663 pos += scnprintf(*buf + pos, bufsz - pos,
1664 " %34s: 0X%08x\n",
1665 get_fh_string(fh_tbl[i]),
1666 iwl_read_direct32(trans, fh_tbl[i]));
1667 }
1668 return pos;
1669 }
1670 #endif
1671 IWL_ERR(trans, "FH register values:\n");
1672 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1673 IWL_ERR(trans, " %34s: 0X%08x\n",
1674 get_fh_string(fh_tbl[i]),
1675 iwl_read_direct32(trans, fh_tbl[i]));
1676 }
1677 return 0;
1678 }
1679
1680 static const char *get_csr_string(int cmd)
1681 {
1682 switch (cmd) {
1683 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1684 IWL_CMD(CSR_INT_COALESCING);
1685 IWL_CMD(CSR_INT);
1686 IWL_CMD(CSR_INT_MASK);
1687 IWL_CMD(CSR_FH_INT_STATUS);
1688 IWL_CMD(CSR_GPIO_IN);
1689 IWL_CMD(CSR_RESET);
1690 IWL_CMD(CSR_GP_CNTRL);
1691 IWL_CMD(CSR_HW_REV);
1692 IWL_CMD(CSR_EEPROM_REG);
1693 IWL_CMD(CSR_EEPROM_GP);
1694 IWL_CMD(CSR_OTP_GP_REG);
1695 IWL_CMD(CSR_GIO_REG);
1696 IWL_CMD(CSR_GP_UCODE_REG);
1697 IWL_CMD(CSR_GP_DRIVER_REG);
1698 IWL_CMD(CSR_UCODE_DRV_GP1);
1699 IWL_CMD(CSR_UCODE_DRV_GP2);
1700 IWL_CMD(CSR_LED_REG);
1701 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1702 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1703 IWL_CMD(CSR_ANA_PLL_CFG);
1704 IWL_CMD(CSR_HW_REV_WA_REG);
1705 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1706 default:
1707 return "UNKNOWN";
1708 }
1709 }
1710
1711 void iwl_dump_csr(struct iwl_trans *trans)
1712 {
1713 int i;
1714 static const u32 csr_tbl[] = {
1715 CSR_HW_IF_CONFIG_REG,
1716 CSR_INT_COALESCING,
1717 CSR_INT,
1718 CSR_INT_MASK,
1719 CSR_FH_INT_STATUS,
1720 CSR_GPIO_IN,
1721 CSR_RESET,
1722 CSR_GP_CNTRL,
1723 CSR_HW_REV,
1724 CSR_EEPROM_REG,
1725 CSR_EEPROM_GP,
1726 CSR_OTP_GP_REG,
1727 CSR_GIO_REG,
1728 CSR_GP_UCODE_REG,
1729 CSR_GP_DRIVER_REG,
1730 CSR_UCODE_DRV_GP1,
1731 CSR_UCODE_DRV_GP2,
1732 CSR_LED_REG,
1733 CSR_DRAM_INT_TBL_REG,
1734 CSR_GIO_CHICKEN_BITS,
1735 CSR_ANA_PLL_CFG,
1736 CSR_HW_REV_WA_REG,
1737 CSR_DBG_HPET_MEM_REG
1738 };
1739 IWL_ERR(trans, "CSR values:\n");
1740 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1741 "CSR_INT_PERIODIC_REG)\n");
1742 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1743 IWL_ERR(trans, " %25s: 0X%08x\n",
1744 get_csr_string(csr_tbl[i]),
1745 iwl_read32(trans, csr_tbl[i]));
1746 }
1747 }
1748
1749 #ifdef CONFIG_IWLWIFI_DEBUGFS
1750 /* create and remove of files */
1751 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1752 if (!debugfs_create_file(#name, mode, parent, trans, \
1753 &iwl_dbgfs_##name##_ops)) \
1754 return -ENOMEM; \
1755 } while (0)
1756
1757 /* file operation */
1758 #define DEBUGFS_READ_FUNC(name) \
1759 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1760 char __user *user_buf, \
1761 size_t count, loff_t *ppos);
1762
1763 #define DEBUGFS_WRITE_FUNC(name) \
1764 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1765 const char __user *user_buf, \
1766 size_t count, loff_t *ppos);
1767
1768
1769 #define DEBUGFS_READ_FILE_OPS(name) \
1770 DEBUGFS_READ_FUNC(name); \
1771 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1772 .read = iwl_dbgfs_##name##_read, \
1773 .open = simple_open, \
1774 .llseek = generic_file_llseek, \
1775 };
1776
1777 #define DEBUGFS_WRITE_FILE_OPS(name) \
1778 DEBUGFS_WRITE_FUNC(name); \
1779 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1780 .write = iwl_dbgfs_##name##_write, \
1781 .open = simple_open, \
1782 .llseek = generic_file_llseek, \
1783 };
1784
1785 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1786 DEBUGFS_READ_FUNC(name); \
1787 DEBUGFS_WRITE_FUNC(name); \
1788 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1789 .write = iwl_dbgfs_##name##_write, \
1790 .read = iwl_dbgfs_##name##_read, \
1791 .open = simple_open, \
1792 .llseek = generic_file_llseek, \
1793 };
1794
1795 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1796 char __user *user_buf,
1797 size_t count, loff_t *ppos)
1798 {
1799 struct iwl_trans *trans = file->private_data;
1800 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1801 struct iwl_tx_queue *txq;
1802 struct iwl_queue *q;
1803 char *buf;
1804 int pos = 0;
1805 int cnt;
1806 int ret;
1807 size_t bufsz;
1808
1809 bufsz = sizeof(char) * 64 * cfg(trans)->base_params->num_of_queues;
1810
1811 if (!trans_pcie->txq) {
1812 IWL_ERR(trans, "txq not ready\n");
1813 return -EAGAIN;
1814 }
1815 buf = kzalloc(bufsz, GFP_KERNEL);
1816 if (!buf)
1817 return -ENOMEM;
1818
1819 for (cnt = 0; cnt < cfg(trans)->base_params->num_of_queues; cnt++) {
1820 txq = &trans_pcie->txq[cnt];
1821 q = &txq->q;
1822 pos += scnprintf(buf + pos, bufsz - pos,
1823 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1824 cnt, q->read_ptr, q->write_ptr,
1825 !!test_bit(cnt, trans_pcie->queue_used),
1826 !!test_bit(cnt, trans_pcie->queue_stopped));
1827 }
1828 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1829 kfree(buf);
1830 return ret;
1831 }
1832
1833 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1834 char __user *user_buf,
1835 size_t count, loff_t *ppos) {
1836 struct iwl_trans *trans = file->private_data;
1837 struct iwl_trans_pcie *trans_pcie =
1838 IWL_TRANS_GET_PCIE_TRANS(trans);
1839 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1840 char buf[256];
1841 int pos = 0;
1842 const size_t bufsz = sizeof(buf);
1843
1844 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1845 rxq->read);
1846 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1847 rxq->write);
1848 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1849 rxq->free_count);
1850 if (rxq->rb_stts) {
1851 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1852 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1853 } else {
1854 pos += scnprintf(buf + pos, bufsz - pos,
1855 "closed_rb_num: Not Allocated\n");
1856 }
1857 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1858 }
1859
1860 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1861 char __user *user_buf,
1862 size_t count, loff_t *ppos) {
1863
1864 struct iwl_trans *trans = file->private_data;
1865 struct iwl_trans_pcie *trans_pcie =
1866 IWL_TRANS_GET_PCIE_TRANS(trans);
1867 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1868
1869 int pos = 0;
1870 char *buf;
1871 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1872 ssize_t ret;
1873
1874 buf = kzalloc(bufsz, GFP_KERNEL);
1875 if (!buf) {
1876 IWL_ERR(trans, "Can not allocate Buffer\n");
1877 return -ENOMEM;
1878 }
1879
1880 pos += scnprintf(buf + pos, bufsz - pos,
1881 "Interrupt Statistics Report:\n");
1882
1883 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1884 isr_stats->hw);
1885 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1886 isr_stats->sw);
1887 if (isr_stats->sw || isr_stats->hw) {
1888 pos += scnprintf(buf + pos, bufsz - pos,
1889 "\tLast Restarting Code: 0x%X\n",
1890 isr_stats->err_code);
1891 }
1892 #ifdef CONFIG_IWLWIFI_DEBUG
1893 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1894 isr_stats->sch);
1895 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1896 isr_stats->alive);
1897 #endif
1898 pos += scnprintf(buf + pos, bufsz - pos,
1899 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1900
1901 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1902 isr_stats->ctkill);
1903
1904 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1905 isr_stats->wakeup);
1906
1907 pos += scnprintf(buf + pos, bufsz - pos,
1908 "Rx command responses:\t\t %u\n", isr_stats->rx);
1909
1910 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1911 isr_stats->tx);
1912
1913 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1914 isr_stats->unhandled);
1915
1916 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1917 kfree(buf);
1918 return ret;
1919 }
1920
1921 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1922 const char __user *user_buf,
1923 size_t count, loff_t *ppos)
1924 {
1925 struct iwl_trans *trans = file->private_data;
1926 struct iwl_trans_pcie *trans_pcie =
1927 IWL_TRANS_GET_PCIE_TRANS(trans);
1928 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1929
1930 char buf[8];
1931 int buf_size;
1932 u32 reset_flag;
1933
1934 memset(buf, 0, sizeof(buf));
1935 buf_size = min(count, sizeof(buf) - 1);
1936 if (copy_from_user(buf, user_buf, buf_size))
1937 return -EFAULT;
1938 if (sscanf(buf, "%x", &reset_flag) != 1)
1939 return -EFAULT;
1940 if (reset_flag == 0)
1941 memset(isr_stats, 0, sizeof(*isr_stats));
1942
1943 return count;
1944 }
1945
1946 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1947 const char __user *user_buf,
1948 size_t count, loff_t *ppos)
1949 {
1950 struct iwl_trans *trans = file->private_data;
1951 char buf[8];
1952 int buf_size;
1953 int csr;
1954
1955 memset(buf, 0, sizeof(buf));
1956 buf_size = min(count, sizeof(buf) - 1);
1957 if (copy_from_user(buf, user_buf, buf_size))
1958 return -EFAULT;
1959 if (sscanf(buf, "%d", &csr) != 1)
1960 return -EFAULT;
1961
1962 iwl_dump_csr(trans);
1963
1964 return count;
1965 }
1966
1967 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1968 char __user *user_buf,
1969 size_t count, loff_t *ppos)
1970 {
1971 struct iwl_trans *trans = file->private_data;
1972 char *buf;
1973 int pos = 0;
1974 ssize_t ret = -EFAULT;
1975
1976 ret = pos = iwl_dump_fh(trans, &buf, true);
1977 if (buf) {
1978 ret = simple_read_from_buffer(user_buf,
1979 count, ppos, buf, pos);
1980 kfree(buf);
1981 }
1982
1983 return ret;
1984 }
1985
1986 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1987 DEBUGFS_READ_FILE_OPS(fh_reg);
1988 DEBUGFS_READ_FILE_OPS(rx_queue);
1989 DEBUGFS_READ_FILE_OPS(tx_queue);
1990 DEBUGFS_WRITE_FILE_OPS(csr);
1991
1992 /*
1993 * Create the debugfs files and directories
1994 *
1995 */
1996 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1997 struct dentry *dir)
1998 {
1999 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2000 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2001 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2002 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2003 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2004 return 0;
2005 }
2006 #else
2007 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2008 struct dentry *dir)
2009 { return 0; }
2010
2011 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2012
2013 const struct iwl_trans_ops trans_ops_pcie = {
2014 .start_hw = iwl_trans_pcie_start_hw,
2015 .stop_hw = iwl_trans_pcie_stop_hw,
2016 .fw_alive = iwl_trans_pcie_fw_alive,
2017 .start_fw = iwl_trans_pcie_start_fw,
2018 .stop_device = iwl_trans_pcie_stop_device,
2019
2020 .wowlan_suspend = iwl_trans_pcie_wowlan_suspend,
2021
2022 .send_cmd = iwl_trans_pcie_send_cmd,
2023
2024 .tx = iwl_trans_pcie_tx,
2025 .reclaim = iwl_trans_pcie_reclaim,
2026
2027 .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
2028 .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
2029
2030 .free = iwl_trans_pcie_free,
2031
2032 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2033
2034 .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2035 .check_stuck_queue = iwl_trans_pcie_check_stuck_queue,
2036
2037 #ifdef CONFIG_PM_SLEEP
2038 .suspend = iwl_trans_pcie_suspend,
2039 .resume = iwl_trans_pcie_resume,
2040 #endif
2041 .write8 = iwl_trans_pcie_write8,
2042 .write32 = iwl_trans_pcie_write32,
2043 .read32 = iwl_trans_pcie_read32,
2044 .configure = iwl_trans_pcie_configure,
2045 .set_pmi = iwl_trans_pcie_set_pmi,
2046 };
2047
2048 struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd,
2049 struct pci_dev *pdev,
2050 const struct pci_device_id *ent)
2051 {
2052 struct iwl_trans_pcie *trans_pcie;
2053 struct iwl_trans *trans;
2054 u16 pci_cmd;
2055 int err;
2056
2057 trans = kzalloc(sizeof(struct iwl_trans) +
2058 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2059
2060 if (WARN_ON(!trans))
2061 return NULL;
2062
2063 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2064
2065 trans->ops = &trans_ops_pcie;
2066 trans->shrd = shrd;
2067 trans_pcie->trans = trans;
2068 spin_lock_init(&trans_pcie->irq_lock);
2069 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2070
2071 /* W/A - seems to solve weird behavior. We need to remove this if we
2072 * don't want to stay in L1 all the time. This wastes a lot of power */
2073 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2074 PCIE_LINK_STATE_CLKPM);
2075
2076 if (pci_enable_device(pdev)) {
2077 err = -ENODEV;
2078 goto out_no_pci;
2079 }
2080
2081 pci_set_master(pdev);
2082
2083 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2084 if (!err)
2085 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2086 if (err) {
2087 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2088 if (!err)
2089 err = pci_set_consistent_dma_mask(pdev,
2090 DMA_BIT_MASK(32));
2091 /* both attempts failed: */
2092 if (err) {
2093 dev_printk(KERN_ERR, &pdev->dev,
2094 "No suitable DMA available.\n");
2095 goto out_pci_disable_device;
2096 }
2097 }
2098
2099 err = pci_request_regions(pdev, DRV_NAME);
2100 if (err) {
2101 dev_printk(KERN_ERR, &pdev->dev, "pci_request_regions failed");
2102 goto out_pci_disable_device;
2103 }
2104
2105 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2106 if (!trans_pcie->hw_base) {
2107 dev_printk(KERN_ERR, &pdev->dev, "pci_ioremap_bar failed");
2108 err = -ENODEV;
2109 goto out_pci_release_regions;
2110 }
2111
2112 dev_printk(KERN_INFO, &pdev->dev,
2113 "pci_resource_len = 0x%08llx\n",
2114 (unsigned long long) pci_resource_len(pdev, 0));
2115 dev_printk(KERN_INFO, &pdev->dev,
2116 "pci_resource_base = %p\n", trans_pcie->hw_base);
2117
2118 dev_printk(KERN_INFO, &pdev->dev,
2119 "HW Revision ID = 0x%X\n", pdev->revision);
2120
2121 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2122 * PCI Tx retries from interfering with C3 CPU state */
2123 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2124
2125 err = pci_enable_msi(pdev);
2126 if (err)
2127 dev_printk(KERN_ERR, &pdev->dev,
2128 "pci_enable_msi failed(0X%x)", err);
2129
2130 trans->dev = &pdev->dev;
2131 trans_pcie->irq = pdev->irq;
2132 trans_pcie->pci_dev = pdev;
2133 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2134 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2135 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2136 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2137
2138 /* TODO: Move this away, not needed if not MSI */
2139 /* enable rfkill interrupt: hw bug w/a */
2140 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2141 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2142 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2143 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2144 }
2145
2146 /* Initialize the wait queue for commands */
2147 init_waitqueue_head(&trans->wait_command_queue);
2148
2149 return trans;
2150
2151 out_pci_release_regions:
2152 pci_release_regions(pdev);
2153 out_pci_disable_device:
2154 pci_disable_device(pdev);
2155 out_no_pci:
2156 kfree(trans);
2157 return NULL;
2158 }
2159
Linux kernel - Deliverables
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