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iwlwifi: add fw_alive to transport layer API, kill tx_start
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-trans-pcie.c
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63 #include <linux/interrupt.h>
64 #include <linux/debugfs.h>
65 #include <linux/bitops.h>
66 #include <linux/gfp.h>
67
68 #include "iwl-trans.h"
69 #include "iwl-trans-pcie-int.h"
70 #include "iwl-csr.h"
71 #include "iwl-prph.h"
72 #include "iwl-shared.h"
73 #include "iwl-eeprom.h"
74 #include "iwl-agn-hw.h"
75
76 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
77 {
78 struct iwl_trans_pcie *trans_pcie =
79 IWL_TRANS_GET_PCIE_TRANS(trans);
80 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
81 struct device *dev = bus(trans)->dev;
82
83 memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
84
85 spin_lock_init(&rxq->lock);
86
87 if (WARN_ON(rxq->bd || rxq->rb_stts))
88 return -EINVAL;
89
90 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
91 rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
92 &rxq->bd_dma, GFP_KERNEL);
93 if (!rxq->bd)
94 goto err_bd;
95
96 /*Allocate the driver's pointer to receive buffer status */
97 rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
98 &rxq->rb_stts_dma, GFP_KERNEL);
99 if (!rxq->rb_stts)
100 goto err_rb_stts;
101
102 return 0;
103
104 err_rb_stts:
105 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
106 rxq->bd, rxq->bd_dma);
107 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
108 rxq->bd = NULL;
109 err_bd:
110 return -ENOMEM;
111 }
112
113 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
114 {
115 struct iwl_trans_pcie *trans_pcie =
116 IWL_TRANS_GET_PCIE_TRANS(trans);
117 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
118 int i;
119
120 /* Fill the rx_used queue with _all_ of the Rx buffers */
121 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
122 /* In the reset function, these buffers may have been allocated
123 * to an SKB, so we need to unmap and free potential storage */
124 if (rxq->pool[i].page != NULL) {
125 dma_unmap_page(bus(trans)->dev, rxq->pool[i].page_dma,
126 PAGE_SIZE << hw_params(trans).rx_page_order,
127 DMA_FROM_DEVICE);
128 __free_pages(rxq->pool[i].page,
129 hw_params(trans).rx_page_order);
130 rxq->pool[i].page = NULL;
131 }
132 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
133 }
134 }
135
136 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
137 struct iwl_rx_queue *rxq)
138 {
139 u32 rb_size;
140 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
141 u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
142
143 if (iwlagn_mod_params.amsdu_size_8K)
144 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
145 else
146 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
147
148 /* Stop Rx DMA */
149 iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
150
151 /* Reset driver's Rx queue write index */
152 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
153
154 /* Tell device where to find RBD circular buffer in DRAM */
155 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_BASE_REG,
156 (u32)(rxq->bd_dma >> 8));
157
158 /* Tell device where in DRAM to update its Rx status */
159 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_STTS_WPTR_REG,
160 rxq->rb_stts_dma >> 4);
161
162 /* Enable Rx DMA
163 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
164 * the credit mechanism in 5000 HW RX FIFO
165 * Direct rx interrupts to hosts
166 * Rx buffer size 4 or 8k
167 * RB timeout 0x10
168 * 256 RBDs
169 */
170 iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG,
171 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
172 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
173 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
174 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
175 rb_size|
176 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
177 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
178
179 /* Set interrupt coalescing timer to default (2048 usecs) */
180 iwl_write8(bus(trans), CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
181 }
182
183 static int iwl_rx_init(struct iwl_trans *trans)
184 {
185 struct iwl_trans_pcie *trans_pcie =
186 IWL_TRANS_GET_PCIE_TRANS(trans);
187 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
188
189 int i, err;
190 unsigned long flags;
191
192 if (!rxq->bd) {
193 err = iwl_trans_rx_alloc(trans);
194 if (err)
195 return err;
196 }
197
198 spin_lock_irqsave(&rxq->lock, flags);
199 INIT_LIST_HEAD(&rxq->rx_free);
200 INIT_LIST_HEAD(&rxq->rx_used);
201
202 iwl_trans_rxq_free_rx_bufs(trans);
203
204 for (i = 0; i < RX_QUEUE_SIZE; i++)
205 rxq->queue[i] = NULL;
206
207 /* Set us so that we have processed and used all buffers, but have
208 * not restocked the Rx queue with fresh buffers */
209 rxq->read = rxq->write = 0;
210 rxq->write_actual = 0;
211 rxq->free_count = 0;
212 spin_unlock_irqrestore(&rxq->lock, flags);
213
214 iwlagn_rx_replenish(trans);
215
216 iwl_trans_rx_hw_init(trans, rxq);
217
218 spin_lock_irqsave(&trans->shrd->lock, flags);
219 rxq->need_update = 1;
220 iwl_rx_queue_update_write_ptr(trans, rxq);
221 spin_unlock_irqrestore(&trans->shrd->lock, flags);
222
223 return 0;
224 }
225
226 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
227 {
228 struct iwl_trans_pcie *trans_pcie =
229 IWL_TRANS_GET_PCIE_TRANS(trans);
230 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
231
232 unsigned long flags;
233
234 /*if rxq->bd is NULL, it means that nothing has been allocated,
235 * exit now */
236 if (!rxq->bd) {
237 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
238 return;
239 }
240
241 spin_lock_irqsave(&rxq->lock, flags);
242 iwl_trans_rxq_free_rx_bufs(trans);
243 spin_unlock_irqrestore(&rxq->lock, flags);
244
245 dma_free_coherent(bus(trans)->dev, sizeof(__le32) * RX_QUEUE_SIZE,
246 rxq->bd, rxq->bd_dma);
247 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
248 rxq->bd = NULL;
249
250 if (rxq->rb_stts)
251 dma_free_coherent(bus(trans)->dev,
252 sizeof(struct iwl_rb_status),
253 rxq->rb_stts, rxq->rb_stts_dma);
254 else
255 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
256 memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
257 rxq->rb_stts = NULL;
258 }
259
260 static int iwl_trans_rx_stop(struct iwl_trans *trans)
261 {
262
263 /* stop Rx DMA */
264 iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
265 return iwl_poll_direct_bit(bus(trans), FH_MEM_RSSR_RX_STATUS_REG,
266 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
267 }
268
269 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
270 struct iwl_dma_ptr *ptr, size_t size)
271 {
272 if (WARN_ON(ptr->addr))
273 return -EINVAL;
274
275 ptr->addr = dma_alloc_coherent(bus(trans)->dev, size,
276 &ptr->dma, GFP_KERNEL);
277 if (!ptr->addr)
278 return -ENOMEM;
279 ptr->size = size;
280 return 0;
281 }
282
283 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
284 struct iwl_dma_ptr *ptr)
285 {
286 if (unlikely(!ptr->addr))
287 return;
288
289 dma_free_coherent(bus(trans)->dev, ptr->size, ptr->addr, ptr->dma);
290 memset(ptr, 0, sizeof(*ptr));
291 }
292
293 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
294 struct iwl_tx_queue *txq, int slots_num,
295 u32 txq_id)
296 {
297 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
298 int i;
299
300 if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds))
301 return -EINVAL;
302
303 txq->q.n_window = slots_num;
304
305 txq->meta = kcalloc(slots_num, sizeof(txq->meta[0]), GFP_KERNEL);
306 txq->cmd = kcalloc(slots_num, sizeof(txq->cmd[0]), GFP_KERNEL);
307
308 if (!txq->meta || !txq->cmd)
309 goto error;
310
311 if (txq_id == trans->shrd->cmd_queue)
312 for (i = 0; i < slots_num; i++) {
313 txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
314 GFP_KERNEL);
315 if (!txq->cmd[i])
316 goto error;
317 }
318
319 /* Alloc driver data array and TFD circular buffer */
320 /* Driver private data, only for Tx (not command) queues,
321 * not shared with device. */
322 if (txq_id != trans->shrd->cmd_queue) {
323 txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->skbs[0]),
324 GFP_KERNEL);
325 if (!txq->skbs) {
326 IWL_ERR(trans, "kmalloc for auxiliary BD "
327 "structures failed\n");
328 goto error;
329 }
330 } else {
331 txq->skbs = NULL;
332 }
333
334 /* Circular buffer of transmit frame descriptors (TFDs),
335 * shared with device */
336 txq->tfds = dma_alloc_coherent(bus(trans)->dev, tfd_sz,
337 &txq->q.dma_addr, GFP_KERNEL);
338 if (!txq->tfds) {
339 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
340 goto error;
341 }
342 txq->q.id = txq_id;
343
344 return 0;
345 error:
346 kfree(txq->skbs);
347 txq->skbs = NULL;
348 /* since txq->cmd has been zeroed,
349 * all non allocated cmd[i] will be NULL */
350 if (txq->cmd && txq_id == trans->shrd->cmd_queue)
351 for (i = 0; i < slots_num; i++)
352 kfree(txq->cmd[i]);
353 kfree(txq->meta);
354 kfree(txq->cmd);
355 txq->meta = NULL;
356 txq->cmd = NULL;
357
358 return -ENOMEM;
359
360 }
361
362 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
363 int slots_num, u32 txq_id)
364 {
365 int ret;
366
367 txq->need_update = 0;
368 memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
369
370 /*
371 * For the default queues 0-3, set up the swq_id
372 * already -- all others need to get one later
373 * (if they need one at all).
374 */
375 if (txq_id < 4)
376 iwl_set_swq_id(txq, txq_id, txq_id);
377
378 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
379 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
380 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
381
382 /* Initialize queue's high/low-water marks, and head/tail indexes */
383 ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
384 txq_id);
385 if (ret)
386 return ret;
387
388 /*
389 * Tell nic where to find circular buffer of Tx Frame Descriptors for
390 * given Tx queue, and enable the DMA channel used for that queue.
391 * Circular buffer (TFD queue in DRAM) physical base address */
392 iwl_write_direct32(bus(trans), FH_MEM_CBBC_QUEUE(txq_id),
393 txq->q.dma_addr >> 8);
394
395 return 0;
396 }
397
398 /**
399 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
400 */
401 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
402 {
403 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
404 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
405 struct iwl_queue *q = &txq->q;
406 enum dma_data_direction dma_dir;
407 unsigned long flags;
408 spinlock_t *lock;
409
410 if (!q->n_bd)
411 return;
412
413 /* In the command queue, all the TBs are mapped as BIDI
414 * so unmap them as such.
415 */
416 if (txq_id == trans->shrd->cmd_queue) {
417 dma_dir = DMA_BIDIRECTIONAL;
418 lock = &trans->hcmd_lock;
419 } else {
420 dma_dir = DMA_TO_DEVICE;
421 lock = &trans->shrd->sta_lock;
422 }
423
424 spin_lock_irqsave(lock, flags);
425 while (q->write_ptr != q->read_ptr) {
426 /* The read_ptr needs to bound by q->n_window */
427 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr),
428 dma_dir);
429 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
430 }
431 spin_unlock_irqrestore(lock, flags);
432 }
433
434 /**
435 * iwl_tx_queue_free - Deallocate DMA queue.
436 * @txq: Transmit queue to deallocate.
437 *
438 * Empty queue by removing and destroying all BD's.
439 * Free all buffers.
440 * 0-fill, but do not free "txq" descriptor structure.
441 */
442 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
443 {
444 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
445 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
446 struct device *dev = bus(trans)->dev;
447 int i;
448 if (WARN_ON(!txq))
449 return;
450
451 iwl_tx_queue_unmap(trans, txq_id);
452
453 /* De-alloc array of command/tx buffers */
454
455 if (txq_id == trans->shrd->cmd_queue)
456 for (i = 0; i < txq->q.n_window; i++)
457 kfree(txq->cmd[i]);
458
459 /* De-alloc circular buffer of TFDs */
460 if (txq->q.n_bd) {
461 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
462 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
463 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
464 }
465
466 /* De-alloc array of per-TFD driver data */
467 kfree(txq->skbs);
468 txq->skbs = NULL;
469
470 /* deallocate arrays */
471 kfree(txq->cmd);
472 kfree(txq->meta);
473 txq->cmd = NULL;
474 txq->meta = NULL;
475
476 /* 0-fill queue descriptor structure */
477 memset(txq, 0, sizeof(*txq));
478 }
479
480 /**
481 * iwl_trans_tx_free - Free TXQ Context
482 *
483 * Destroy all TX DMA queues and structures
484 */
485 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
486 {
487 int txq_id;
488 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
489
490 /* Tx queues */
491 if (trans_pcie->txq) {
492 for (txq_id = 0;
493 txq_id < hw_params(trans).max_txq_num; txq_id++)
494 iwl_tx_queue_free(trans, txq_id);
495 }
496
497 kfree(trans_pcie->txq);
498 trans_pcie->txq = NULL;
499
500 iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
501
502 iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
503 }
504
505 /**
506 * iwl_trans_tx_alloc - allocate TX context
507 * Allocate all Tx DMA structures and initialize them
508 *
509 * @param priv
510 * @return error code
511 */
512 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
513 {
514 int ret;
515 int txq_id, slots_num;
516 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
517
518 u16 scd_bc_tbls_size = hw_params(trans).max_txq_num *
519 sizeof(struct iwlagn_scd_bc_tbl);
520
521 /*It is not allowed to alloc twice, so warn when this happens.
522 * We cannot rely on the previous allocation, so free and fail */
523 if (WARN_ON(trans_pcie->txq)) {
524 ret = -EINVAL;
525 goto error;
526 }
527
528 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
529 scd_bc_tbls_size);
530 if (ret) {
531 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
532 goto error;
533 }
534
535 /* Alloc keep-warm buffer */
536 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
537 if (ret) {
538 IWL_ERR(trans, "Keep Warm allocation failed\n");
539 goto error;
540 }
541
542 trans_pcie->txq = kcalloc(hw_params(trans).max_txq_num,
543 sizeof(struct iwl_tx_queue), GFP_KERNEL);
544 if (!trans_pcie->txq) {
545 IWL_ERR(trans, "Not enough memory for txq\n");
546 ret = ENOMEM;
547 goto error;
548 }
549
550 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
551 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
552 slots_num = (txq_id == trans->shrd->cmd_queue) ?
553 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
554 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
555 slots_num, txq_id);
556 if (ret) {
557 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
558 goto error;
559 }
560 }
561
562 return 0;
563
564 error:
565 iwl_trans_pcie_tx_free(trans);
566
567 return ret;
568 }
569 static int iwl_tx_init(struct iwl_trans *trans)
570 {
571 int ret;
572 int txq_id, slots_num;
573 unsigned long flags;
574 bool alloc = false;
575 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
576
577 if (!trans_pcie->txq) {
578 ret = iwl_trans_tx_alloc(trans);
579 if (ret)
580 goto error;
581 alloc = true;
582 }
583
584 spin_lock_irqsave(&trans->shrd->lock, flags);
585
586 /* Turn off all Tx DMA fifos */
587 iwl_write_prph(bus(trans), SCD_TXFACT, 0);
588
589 /* Tell NIC where to find the "keep warm" buffer */
590 iwl_write_direct32(bus(trans), FH_KW_MEM_ADDR_REG,
591 trans_pcie->kw.dma >> 4);
592
593 spin_unlock_irqrestore(&trans->shrd->lock, flags);
594
595 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
596 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
597 slots_num = (txq_id == trans->shrd->cmd_queue) ?
598 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
599 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
600 slots_num, txq_id);
601 if (ret) {
602 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
603 goto error;
604 }
605 }
606
607 return 0;
608 error:
609 /*Upon error, free only if we allocated something */
610 if (alloc)
611 iwl_trans_pcie_tx_free(trans);
612 return ret;
613 }
614
615 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
616 {
617 /*
618 * (for documentation purposes)
619 * to set power to V_AUX, do:
620
621 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
622 iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
623 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
624 ~APMG_PS_CTRL_MSK_PWR_SRC);
625 */
626
627 iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
628 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
629 ~APMG_PS_CTRL_MSK_PWR_SRC);
630 }
631
632 static int iwl_nic_init(struct iwl_trans *trans)
633 {
634 unsigned long flags;
635
636 /* nic_init */
637 spin_lock_irqsave(&trans->shrd->lock, flags);
638 iwl_apm_init(priv(trans));
639
640 /* Set interrupt coalescing calibration timer to default (512 usecs) */
641 iwl_write8(bus(trans), CSR_INT_COALESCING,
642 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
643
644 spin_unlock_irqrestore(&trans->shrd->lock, flags);
645
646 iwl_set_pwr_vmain(trans);
647
648 iwl_nic_config(priv(trans));
649
650 /* Allocate the RX queue, or reset if it is already allocated */
651 iwl_rx_init(trans);
652
653 /* Allocate or reset and init all Tx and Command queues */
654 if (iwl_tx_init(trans))
655 return -ENOMEM;
656
657 if (hw_params(trans).shadow_reg_enable) {
658 /* enable shadow regs in HW */
659 iwl_set_bit(bus(trans), CSR_MAC_SHADOW_REG_CTRL,
660 0x800FFFFF);
661 }
662
663 set_bit(STATUS_INIT, &trans->shrd->status);
664
665 return 0;
666 }
667
668 #define HW_READY_TIMEOUT (50)
669
670 /* Note: returns poll_bit return value, which is >= 0 if success */
671 static int iwl_set_hw_ready(struct iwl_trans *trans)
672 {
673 int ret;
674
675 iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
676 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
677
678 /* See if we got it */
679 ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
680 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
681 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
682 HW_READY_TIMEOUT);
683
684 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
685 return ret;
686 }
687
688 /* Note: returns standard 0/-ERROR code */
689 static int iwl_trans_pcie_prepare_card_hw(struct iwl_trans *trans)
690 {
691 int ret;
692
693 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
694
695 ret = iwl_set_hw_ready(trans);
696 if (ret >= 0)
697 return 0;
698
699 /* If HW is not ready, prepare the conditions to check again */
700 iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
701 CSR_HW_IF_CONFIG_REG_PREPARE);
702
703 ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
704 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
705 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
706
707 if (ret < 0)
708 return ret;
709
710 /* HW should be ready by now, check again. */
711 ret = iwl_set_hw_ready(trans);
712 if (ret >= 0)
713 return 0;
714 return ret;
715 }
716
717 #define IWL_AC_UNSET -1
718
719 struct queue_to_fifo_ac {
720 s8 fifo, ac;
721 };
722
723 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
724 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
725 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
726 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
727 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
728 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
729 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
730 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
731 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
732 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
733 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
734 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
735 };
736
737 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
738 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
739 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
740 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
741 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
742 { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
743 { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
744 { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
745 { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
746 { IWL_TX_FIFO_BE_IPAN, 2, },
747 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
748 { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
749 };
750
751 static const u8 iwlagn_bss_ac_to_fifo[] = {
752 IWL_TX_FIFO_VO,
753 IWL_TX_FIFO_VI,
754 IWL_TX_FIFO_BE,
755 IWL_TX_FIFO_BK,
756 };
757 static const u8 iwlagn_bss_ac_to_queue[] = {
758 0, 1, 2, 3,
759 };
760 static const u8 iwlagn_pan_ac_to_fifo[] = {
761 IWL_TX_FIFO_VO_IPAN,
762 IWL_TX_FIFO_VI_IPAN,
763 IWL_TX_FIFO_BE_IPAN,
764 IWL_TX_FIFO_BK_IPAN,
765 };
766 static const u8 iwlagn_pan_ac_to_queue[] = {
767 7, 6, 5, 4,
768 };
769
770 static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
771 {
772 int ret;
773 struct iwl_trans_pcie *trans_pcie =
774 IWL_TRANS_GET_PCIE_TRANS(trans);
775
776 trans->shrd->ucode_owner = IWL_OWNERSHIP_DRIVER;
777 trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue;
778 trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue;
779
780 trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo;
781 trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo;
782
783 trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0;
784 trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE;
785
786 if ((hw_params(trans).sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
787 iwl_trans_pcie_prepare_card_hw(trans)) {
788 IWL_WARN(trans, "Exit HW not ready\n");
789 return -EIO;
790 }
791
792 /* If platform's RF_KILL switch is NOT set to KILL */
793 if (iwl_read32(bus(trans), CSR_GP_CNTRL) &
794 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
795 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
796 else
797 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
798
799 if (iwl_is_rfkill(trans->shrd)) {
800 iwl_set_hw_rfkill_state(priv(trans), true);
801 iwl_enable_interrupts(trans);
802 return -ERFKILL;
803 }
804
805 iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF);
806
807 ret = iwl_nic_init(trans);
808 if (ret) {
809 IWL_ERR(trans, "Unable to init nic\n");
810 return ret;
811 }
812
813 /* make sure rfkill handshake bits are cleared */
814 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
815 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR,
816 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
817
818 /* clear (again), then enable host interrupts */
819 iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF);
820 iwl_enable_interrupts(trans);
821
822 /* really make sure rfkill handshake bits are cleared */
823 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
824 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
825
826 return 0;
827 }
828
829 /*
830 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
831 * must be called under priv->shrd->lock and mac access
832 */
833 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
834 {
835 iwl_write_prph(bus(trans), SCD_TXFACT, mask);
836 }
837
838 static void iwl_tx_start(struct iwl_trans *trans)
839 {
840 const struct queue_to_fifo_ac *queue_to_fifo;
841 struct iwl_trans_pcie *trans_pcie =
842 IWL_TRANS_GET_PCIE_TRANS(trans);
843 u32 a;
844 unsigned long flags;
845 int i, chan;
846 u32 reg_val;
847
848 spin_lock_irqsave(&trans->shrd->lock, flags);
849
850 trans_pcie->scd_base_addr =
851 iwl_read_prph(bus(trans), SCD_SRAM_BASE_ADDR);
852 a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
853 /* reset conext data memory */
854 for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
855 a += 4)
856 iwl_write_targ_mem(bus(trans), a, 0);
857 /* reset tx status memory */
858 for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
859 a += 4)
860 iwl_write_targ_mem(bus(trans), a, 0);
861 for (; a < trans_pcie->scd_base_addr +
862 SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num);
863 a += 4)
864 iwl_write_targ_mem(bus(trans), a, 0);
865
866 iwl_write_prph(bus(trans), SCD_DRAM_BASE_ADDR,
867 trans_pcie->scd_bc_tbls.dma >> 10);
868
869 /* Enable DMA channel */
870 for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
871 iwl_write_direct32(bus(trans), FH_TCSR_CHNL_TX_CONFIG_REG(chan),
872 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
873 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
874
875 /* Update FH chicken bits */
876 reg_val = iwl_read_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG);
877 iwl_write_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG,
878 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
879
880 iwl_write_prph(bus(trans), SCD_QUEUECHAIN_SEL,
881 SCD_QUEUECHAIN_SEL_ALL(trans));
882 iwl_write_prph(bus(trans), SCD_AGGR_SEL, 0);
883
884 /* initiate the queues */
885 for (i = 0; i < hw_params(trans).max_txq_num; i++) {
886 iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(i), 0);
887 iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR, 0 | (i << 8));
888 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
889 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
890 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
891 SCD_CONTEXT_QUEUE_OFFSET(i) +
892 sizeof(u32),
893 ((SCD_WIN_SIZE <<
894 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
895 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
896 ((SCD_FRAME_LIMIT <<
897 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
898 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
899 }
900
901 iwl_write_prph(bus(trans), SCD_INTERRUPT_MASK,
902 IWL_MASK(0, hw_params(trans).max_txq_num));
903
904 /* Activate all Tx DMA/FIFO channels */
905 iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
906
907 /* map queues to FIFOs */
908 if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS))
909 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
910 else
911 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
912
913 iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0);
914
915 /* make sure all queue are not stopped */
916 memset(&trans_pcie->queue_stopped[0], 0,
917 sizeof(trans_pcie->queue_stopped));
918 for (i = 0; i < 4; i++)
919 atomic_set(&trans_pcie->queue_stop_count[i], 0);
920
921 /* reset to 0 to enable all the queue first */
922 trans_pcie->txq_ctx_active_msk = 0;
923
924 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
925 IWLAGN_FIRST_AMPDU_QUEUE);
926 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
927 IWLAGN_FIRST_AMPDU_QUEUE);
928
929 for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
930 int fifo = queue_to_fifo[i].fifo;
931 int ac = queue_to_fifo[i].ac;
932
933 iwl_txq_ctx_activate(trans_pcie, i);
934
935 if (fifo == IWL_TX_FIFO_UNUSED)
936 continue;
937
938 if (ac != IWL_AC_UNSET)
939 iwl_set_swq_id(&trans_pcie->txq[i], ac, i);
940 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
941 fifo, 0);
942 }
943
944 spin_unlock_irqrestore(&trans->shrd->lock, flags);
945
946 /* Enable L1-Active */
947 iwl_clear_bits_prph(bus(trans), APMG_PCIDEV_STT_REG,
948 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
949 }
950
951 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
952 {
953 iwl_reset_ict(trans);
954 iwl_tx_start(trans);
955 }
956
957 /**
958 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
959 */
960 static int iwl_trans_tx_stop(struct iwl_trans *trans)
961 {
962 int ch, txq_id;
963 unsigned long flags;
964 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
965
966 /* Turn off all Tx DMA fifos */
967 spin_lock_irqsave(&trans->shrd->lock, flags);
968
969 iwl_trans_txq_set_sched(trans, 0);
970
971 /* Stop each Tx DMA channel, and wait for it to be idle */
972 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
973 iwl_write_direct32(bus(trans),
974 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
975 if (iwl_poll_direct_bit(bus(trans), FH_TSSR_TX_STATUS_REG,
976 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
977 1000))
978 IWL_ERR(trans, "Failing on timeout while stopping"
979 " DMA channel %d [0x%08x]", ch,
980 iwl_read_direct32(bus(trans),
981 FH_TSSR_TX_STATUS_REG));
982 }
983 spin_unlock_irqrestore(&trans->shrd->lock, flags);
984
985 if (!trans_pcie->txq) {
986 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
987 return 0;
988 }
989
990 /* Unmap DMA from host system and free skb's */
991 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
992 iwl_tx_queue_unmap(trans, txq_id);
993
994 return 0;
995 }
996
997 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
998 {
999 unsigned long flags;
1000 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1001
1002 /* tell the device to stop sending interrupts */
1003 spin_lock_irqsave(&trans->shrd->lock, flags);
1004 iwl_disable_interrupts(trans);
1005 spin_unlock_irqrestore(&trans->shrd->lock, flags);
1006
1007 /* device going down, Stop using ICT table */
1008 iwl_disable_ict(trans);
1009
1010 /*
1011 * If a HW restart happens during firmware loading,
1012 * then the firmware loading might call this function
1013 * and later it might be called again due to the
1014 * restart. So don't process again if the device is
1015 * already dead.
1016 */
1017 if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) {
1018 iwl_trans_tx_stop(trans);
1019 iwl_trans_rx_stop(trans);
1020
1021 /* Power-down device's busmaster DMA clocks */
1022 iwl_write_prph(bus(trans), APMG_CLK_DIS_REG,
1023 APMG_CLK_VAL_DMA_CLK_RQT);
1024 udelay(5);
1025 }
1026
1027 /* Make sure (redundant) we've released our request to stay awake */
1028 iwl_clear_bit(bus(trans), CSR_GP_CNTRL,
1029 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1030
1031 /* Stop the device, and put it in low power state */
1032 iwl_apm_stop(priv(trans));
1033
1034 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1035 * Clean again the interrupt here
1036 */
1037 spin_lock_irqsave(&trans->shrd->lock, flags);
1038 iwl_disable_interrupts(trans);
1039 spin_unlock_irqrestore(&trans->shrd->lock, flags);
1040
1041 /* wait to make sure we flush pending tasklet*/
1042 synchronize_irq(bus(trans)->irq);
1043 tasklet_kill(&trans_pcie->irq_tasklet);
1044
1045 /* stop and reset the on-board processor */
1046 iwl_write32(bus(trans), CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1047 }
1048
1049 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1050 struct iwl_device_cmd *dev_cmd, enum iwl_rxon_context_id ctx,
1051 u8 sta_id, u8 tid)
1052 {
1053 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1054 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1055 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1056 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1057 struct iwl_cmd_meta *out_meta;
1058 struct iwl_tx_queue *txq;
1059 struct iwl_queue *q;
1060
1061 dma_addr_t phys_addr = 0;
1062 dma_addr_t txcmd_phys;
1063 dma_addr_t scratch_phys;
1064 u16 len, firstlen, secondlen;
1065 u8 wait_write_ptr = 0;
1066 u8 txq_id;
1067 bool is_agg = false;
1068 __le16 fc = hdr->frame_control;
1069 u8 hdr_len = ieee80211_hdrlen(fc);
1070 u16 __maybe_unused wifi_seq;
1071
1072 /*
1073 * Send this frame after DTIM -- there's a special queue
1074 * reserved for this for contexts that support AP mode.
1075 */
1076 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1077 txq_id = trans_pcie->mcast_queue[ctx];
1078
1079 /*
1080 * The microcode will clear the more data
1081 * bit in the last frame it transmits.
1082 */
1083 hdr->frame_control |=
1084 cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1085 } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
1086 txq_id = IWL_AUX_QUEUE;
1087 else
1088 txq_id =
1089 trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)];
1090
1091 /* aggregation is on for this <sta,tid> */
1092 if (info->flags & IEEE80211_TX_CTL_AMPDU) {
1093 WARN_ON(tid >= IWL_MAX_TID_COUNT);
1094 txq_id = trans_pcie->agg_txq[sta_id][tid];
1095 is_agg = true;
1096 }
1097
1098 txq = &trans_pcie->txq[txq_id];
1099 q = &txq->q;
1100
1101 /* In AGG mode, the index in the ring must correspond to the WiFi
1102 * sequence number. This is a HW requirements to help the SCD to parse
1103 * the BA.
1104 * Check here that the packets are in the right place on the ring.
1105 */
1106 #ifdef CONFIG_IWLWIFI_DEBUG
1107 wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1108 WARN_ONCE(is_agg && ((wifi_seq & 0xff) != q->write_ptr),
1109 "Q: %d WiFi Seq %d tfdNum %d",
1110 txq_id, wifi_seq, q->write_ptr);
1111 #endif
1112
1113 /* Set up driver data for this TFD */
1114 txq->skbs[q->write_ptr] = skb;
1115 txq->cmd[q->write_ptr] = dev_cmd;
1116
1117 dev_cmd->hdr.cmd = REPLY_TX;
1118 dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1119 INDEX_TO_SEQ(q->write_ptr)));
1120
1121 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1122 out_meta = &txq->meta[q->write_ptr];
1123
1124 /*
1125 * Use the first empty entry in this queue's command buffer array
1126 * to contain the Tx command and MAC header concatenated together
1127 * (payload data will be in another buffer).
1128 * Size of this varies, due to varying MAC header length.
1129 * If end is not dword aligned, we'll have 2 extra bytes at the end
1130 * of the MAC header (device reads on dword boundaries).
1131 * We'll tell device about this padding later.
1132 */
1133 len = sizeof(struct iwl_tx_cmd) +
1134 sizeof(struct iwl_cmd_header) + hdr_len;
1135 firstlen = (len + 3) & ~3;
1136
1137 /* Tell NIC about any 2-byte padding after MAC header */
1138 if (firstlen != len)
1139 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1140
1141 /* Physical address of this Tx command's header (not MAC header!),
1142 * within command buffer array. */
1143 txcmd_phys = dma_map_single(bus(trans)->dev,
1144 &dev_cmd->hdr, firstlen,
1145 DMA_BIDIRECTIONAL);
1146 if (unlikely(dma_mapping_error(bus(trans)->dev, txcmd_phys)))
1147 return -1;
1148 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1149 dma_unmap_len_set(out_meta, len, firstlen);
1150
1151 if (!ieee80211_has_morefrags(fc)) {
1152 txq->need_update = 1;
1153 } else {
1154 wait_write_ptr = 1;
1155 txq->need_update = 0;
1156 }
1157
1158 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1159 * if any (802.11 null frames have no payload). */
1160 secondlen = skb->len - hdr_len;
1161 if (secondlen > 0) {
1162 phys_addr = dma_map_single(bus(trans)->dev, skb->data + hdr_len,
1163 secondlen, DMA_TO_DEVICE);
1164 if (unlikely(dma_mapping_error(bus(trans)->dev, phys_addr))) {
1165 dma_unmap_single(bus(trans)->dev,
1166 dma_unmap_addr(out_meta, mapping),
1167 dma_unmap_len(out_meta, len),
1168 DMA_BIDIRECTIONAL);
1169 return -1;
1170 }
1171 }
1172
1173 /* Attach buffers to TFD */
1174 iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1175 if (secondlen > 0)
1176 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1177 secondlen, 0);
1178
1179 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1180 offsetof(struct iwl_tx_cmd, scratch);
1181
1182 /* take back ownership of DMA buffer to enable update */
1183 dma_sync_single_for_cpu(bus(trans)->dev, txcmd_phys, firstlen,
1184 DMA_BIDIRECTIONAL);
1185 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1186 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1187
1188 IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1189 le16_to_cpu(dev_cmd->hdr.sequence));
1190 IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1191 iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1192 iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1193
1194 /* Set up entry for this TFD in Tx byte-count array */
1195 iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1196
1197 dma_sync_single_for_device(bus(trans)->dev, txcmd_phys, firstlen,
1198 DMA_BIDIRECTIONAL);
1199
1200 trace_iwlwifi_dev_tx(priv(trans),
1201 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1202 sizeof(struct iwl_tfd),
1203 &dev_cmd->hdr, firstlen,
1204 skb->data + hdr_len, secondlen);
1205
1206 /* Tell device the write index *just past* this latest filled TFD */
1207 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1208 iwl_txq_update_write_ptr(trans, txq);
1209
1210 /*
1211 * At this point the frame is "transmitted" successfully
1212 * and we will get a TX status notification eventually,
1213 * regardless of the value of ret. "ret" only indicates
1214 * whether or not we should update the write pointer.
1215 */
1216 if (iwl_queue_space(q) < q->high_mark) {
1217 if (wait_write_ptr) {
1218 txq->need_update = 1;
1219 iwl_txq_update_write_ptr(trans, txq);
1220 } else {
1221 iwl_stop_queue(trans, txq, "Queue is full");
1222 }
1223 }
1224 return 0;
1225 }
1226
1227 static void iwl_trans_pcie_kick_nic(struct iwl_trans *trans)
1228 {
1229 /* Remove all resets to allow NIC to operate */
1230 iwl_write32(bus(trans), CSR_RESET, 0);
1231 }
1232
1233 static int iwl_trans_pcie_request_irq(struct iwl_trans *trans)
1234 {
1235 struct iwl_trans_pcie *trans_pcie =
1236 IWL_TRANS_GET_PCIE_TRANS(trans);
1237 int err;
1238
1239 trans_pcie->inta_mask = CSR_INI_SET_MASK;
1240
1241 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1242 iwl_irq_tasklet, (unsigned long)trans);
1243
1244 iwl_alloc_isr_ict(trans);
1245
1246 err = request_irq(bus(trans)->irq, iwl_isr_ict, IRQF_SHARED,
1247 DRV_NAME, trans);
1248 if (err) {
1249 IWL_ERR(trans, "Error allocating IRQ %d\n", bus(trans)->irq);
1250 iwl_free_isr_ict(trans);
1251 return err;
1252 }
1253
1254 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1255 return 0;
1256 }
1257
1258 static int iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid,
1259 int txq_id, int ssn, u32 status,
1260 struct sk_buff_head *skbs)
1261 {
1262 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1263 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1264 /* n_bd is usually 256 => n_bd - 1 = 0xff */
1265 int tfd_num = ssn & (txq->q.n_bd - 1);
1266 int freed = 0;
1267
1268 txq->time_stamp = jiffies;
1269
1270 if (unlikely(txq_id >= IWLAGN_FIRST_AMPDU_QUEUE &&
1271 txq_id != trans_pcie->agg_txq[sta_id][tid])) {
1272 /*
1273 * FIXME: this is a uCode bug which need to be addressed,
1274 * log the information and return for now.
1275 * Since it is can possibly happen very often and in order
1276 * not to fill the syslog, don't use IWL_ERR or IWL_WARN
1277 */
1278 IWL_DEBUG_TX_QUEUES(trans, "Bad queue mapping txq_id %d, "
1279 "agg_txq[sta_id[tid] %d", txq_id,
1280 trans_pcie->agg_txq[sta_id][tid]);
1281 return 1;
1282 }
1283
1284 if (txq->q.read_ptr != tfd_num) {
1285 IWL_DEBUG_TX_REPLY(trans, "[Q %d | AC %d] %d -> %d (%d)\n",
1286 txq_id, iwl_get_queue_ac(txq), txq->q.read_ptr,
1287 tfd_num, ssn);
1288 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1289 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1290 (!txq->sched_retry ||
1291 status != TX_STATUS_FAIL_PASSIVE_NO_RX))
1292 iwl_wake_queue(trans, txq, "Packets reclaimed");
1293 }
1294 return 0;
1295 }
1296
1297 static void iwl_trans_pcie_free(struct iwl_trans *trans)
1298 {
1299 iwl_calib_free_results(trans);
1300 iwl_trans_pcie_tx_free(trans);
1301 iwl_trans_pcie_rx_free(trans);
1302 free_irq(bus(trans)->irq, trans);
1303 iwl_free_isr_ict(trans);
1304 trans->shrd->trans = NULL;
1305 kfree(trans);
1306 }
1307
1308 #ifdef CONFIG_PM_SLEEP
1309 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1310 {
1311 /*
1312 * This function is called when system goes into suspend state
1313 * mac80211 will call iwlagn_mac_stop() from the mac80211 suspend
1314 * function first but since iwlagn_mac_stop() has no knowledge of
1315 * who the caller is,
1316 * it will not call apm_ops.stop() to stop the DMA operation.
1317 * Calling apm_ops.stop here to make sure we stop the DMA.
1318 *
1319 * But of course ... if we have configured WoWLAN then we did other
1320 * things already :-)
1321 */
1322 if (!trans->shrd->wowlan) {
1323 iwl_apm_stop(priv(trans));
1324 } else {
1325 iwl_disable_interrupts(trans);
1326 iwl_clear_bit(bus(trans), CSR_GP_CNTRL,
1327 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1328 }
1329
1330 return 0;
1331 }
1332
1333 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1334 {
1335 bool hw_rfkill = false;
1336
1337 iwl_enable_interrupts(trans);
1338
1339 if (!(iwl_read32(bus(trans), CSR_GP_CNTRL) &
1340 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1341 hw_rfkill = true;
1342
1343 if (hw_rfkill)
1344 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1345 else
1346 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1347
1348 iwl_set_hw_rfkill_state(priv(trans), hw_rfkill);
1349
1350 return 0;
1351 }
1352 #endif /* CONFIG_PM_SLEEP */
1353
1354 static void iwl_trans_pcie_wake_any_queue(struct iwl_trans *trans,
1355 enum iwl_rxon_context_id ctx,
1356 const char *msg)
1357 {
1358 u8 ac, txq_id;
1359 struct iwl_trans_pcie *trans_pcie =
1360 IWL_TRANS_GET_PCIE_TRANS(trans);
1361
1362 for (ac = 0; ac < AC_NUM; ac++) {
1363 txq_id = trans_pcie->ac_to_queue[ctx][ac];
1364 IWL_DEBUG_TX_QUEUES(trans, "Queue Status: Q[%d] %s\n",
1365 ac,
1366 (atomic_read(&trans_pcie->queue_stop_count[ac]) > 0)
1367 ? "stopped" : "awake");
1368 iwl_wake_queue(trans, &trans_pcie->txq[txq_id], msg);
1369 }
1370 }
1371
1372 const struct iwl_trans_ops trans_ops_pcie;
1373
1374 static struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd)
1375 {
1376 struct iwl_trans *iwl_trans = kzalloc(sizeof(struct iwl_trans) +
1377 sizeof(struct iwl_trans_pcie),
1378 GFP_KERNEL);
1379 if (iwl_trans) {
1380 struct iwl_trans_pcie *trans_pcie =
1381 IWL_TRANS_GET_PCIE_TRANS(iwl_trans);
1382 iwl_trans->ops = &trans_ops_pcie;
1383 iwl_trans->shrd = shrd;
1384 trans_pcie->trans = iwl_trans;
1385 spin_lock_init(&iwl_trans->hcmd_lock);
1386 }
1387
1388 return iwl_trans;
1389 }
1390
1391 static void iwl_trans_pcie_stop_queue(struct iwl_trans *trans, int txq_id,
1392 const char *msg)
1393 {
1394 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1395
1396 iwl_stop_queue(trans, &trans_pcie->txq[txq_id], msg);
1397 }
1398
1399 #define IWL_FLUSH_WAIT_MS 2000
1400
1401 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1402 {
1403 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1404 struct iwl_tx_queue *txq;
1405 struct iwl_queue *q;
1406 int cnt;
1407 unsigned long now = jiffies;
1408 int ret = 0;
1409
1410 /* waiting for all the tx frames complete might take a while */
1411 for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1412 if (cnt == trans->shrd->cmd_queue)
1413 continue;
1414 txq = &trans_pcie->txq[cnt];
1415 q = &txq->q;
1416 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1417 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1418 msleep(1);
1419
1420 if (q->read_ptr != q->write_ptr) {
1421 IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1422 ret = -ETIMEDOUT;
1423 break;
1424 }
1425 }
1426 return ret;
1427 }
1428
1429 /*
1430 * On every watchdog tick we check (latest) time stamp. If it does not
1431 * change during timeout period and queue is not empty we reset firmware.
1432 */
1433 static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt)
1434 {
1435 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1436 struct iwl_tx_queue *txq = &trans_pcie->txq[cnt];
1437 struct iwl_queue *q = &txq->q;
1438 unsigned long timeout;
1439
1440 if (q->read_ptr == q->write_ptr) {
1441 txq->time_stamp = jiffies;
1442 return 0;
1443 }
1444
1445 timeout = txq->time_stamp +
1446 msecs_to_jiffies(hw_params(trans).wd_timeout);
1447
1448 if (time_after(jiffies, timeout)) {
1449 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id,
1450 hw_params(trans).wd_timeout);
1451 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1452 q->read_ptr, q->write_ptr);
1453 IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n",
1454 iwl_read_prph(bus(trans), SCD_QUEUE_RDPTR(cnt))
1455 & (TFD_QUEUE_SIZE_MAX - 1),
1456 iwl_read_prph(bus(trans), SCD_QUEUE_WRPTR(cnt)));
1457 return 1;
1458 }
1459
1460 return 0;
1461 }
1462
1463 static const char *get_fh_string(int cmd)
1464 {
1465 switch (cmd) {
1466 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1467 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1468 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1469 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1470 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1471 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1472 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1473 IWL_CMD(FH_TSSR_TX_STATUS_REG);
1474 IWL_CMD(FH_TSSR_TX_ERROR_REG);
1475 default:
1476 return "UNKNOWN";
1477 }
1478 }
1479
1480 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1481 {
1482 int i;
1483 #ifdef CONFIG_IWLWIFI_DEBUG
1484 int pos = 0;
1485 size_t bufsz = 0;
1486 #endif
1487 static const u32 fh_tbl[] = {
1488 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1489 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1490 FH_RSCSR_CHNL0_WPTR,
1491 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1492 FH_MEM_RSSR_SHARED_CTRL_REG,
1493 FH_MEM_RSSR_RX_STATUS_REG,
1494 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1495 FH_TSSR_TX_STATUS_REG,
1496 FH_TSSR_TX_ERROR_REG
1497 };
1498 #ifdef CONFIG_IWLWIFI_DEBUG
1499 if (display) {
1500 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1501 *buf = kmalloc(bufsz, GFP_KERNEL);
1502 if (!*buf)
1503 return -ENOMEM;
1504 pos += scnprintf(*buf + pos, bufsz - pos,
1505 "FH register values:\n");
1506 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1507 pos += scnprintf(*buf + pos, bufsz - pos,
1508 " %34s: 0X%08x\n",
1509 get_fh_string(fh_tbl[i]),
1510 iwl_read_direct32(bus(trans), fh_tbl[i]));
1511 }
1512 return pos;
1513 }
1514 #endif
1515 IWL_ERR(trans, "FH register values:\n");
1516 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1517 IWL_ERR(trans, " %34s: 0X%08x\n",
1518 get_fh_string(fh_tbl[i]),
1519 iwl_read_direct32(bus(trans), fh_tbl[i]));
1520 }
1521 return 0;
1522 }
1523
1524 static const char *get_csr_string(int cmd)
1525 {
1526 switch (cmd) {
1527 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1528 IWL_CMD(CSR_INT_COALESCING);
1529 IWL_CMD(CSR_INT);
1530 IWL_CMD(CSR_INT_MASK);
1531 IWL_CMD(CSR_FH_INT_STATUS);
1532 IWL_CMD(CSR_GPIO_IN);
1533 IWL_CMD(CSR_RESET);
1534 IWL_CMD(CSR_GP_CNTRL);
1535 IWL_CMD(CSR_HW_REV);
1536 IWL_CMD(CSR_EEPROM_REG);
1537 IWL_CMD(CSR_EEPROM_GP);
1538 IWL_CMD(CSR_OTP_GP_REG);
1539 IWL_CMD(CSR_GIO_REG);
1540 IWL_CMD(CSR_GP_UCODE_REG);
1541 IWL_CMD(CSR_GP_DRIVER_REG);
1542 IWL_CMD(CSR_UCODE_DRV_GP1);
1543 IWL_CMD(CSR_UCODE_DRV_GP2);
1544 IWL_CMD(CSR_LED_REG);
1545 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1546 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1547 IWL_CMD(CSR_ANA_PLL_CFG);
1548 IWL_CMD(CSR_HW_REV_WA_REG);
1549 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1550 default:
1551 return "UNKNOWN";
1552 }
1553 }
1554
1555 void iwl_dump_csr(struct iwl_trans *trans)
1556 {
1557 int i;
1558 static const u32 csr_tbl[] = {
1559 CSR_HW_IF_CONFIG_REG,
1560 CSR_INT_COALESCING,
1561 CSR_INT,
1562 CSR_INT_MASK,
1563 CSR_FH_INT_STATUS,
1564 CSR_GPIO_IN,
1565 CSR_RESET,
1566 CSR_GP_CNTRL,
1567 CSR_HW_REV,
1568 CSR_EEPROM_REG,
1569 CSR_EEPROM_GP,
1570 CSR_OTP_GP_REG,
1571 CSR_GIO_REG,
1572 CSR_GP_UCODE_REG,
1573 CSR_GP_DRIVER_REG,
1574 CSR_UCODE_DRV_GP1,
1575 CSR_UCODE_DRV_GP2,
1576 CSR_LED_REG,
1577 CSR_DRAM_INT_TBL_REG,
1578 CSR_GIO_CHICKEN_BITS,
1579 CSR_ANA_PLL_CFG,
1580 CSR_HW_REV_WA_REG,
1581 CSR_DBG_HPET_MEM_REG
1582 };
1583 IWL_ERR(trans, "CSR values:\n");
1584 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1585 "CSR_INT_PERIODIC_REG)\n");
1586 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1587 IWL_ERR(trans, " %25s: 0X%08x\n",
1588 get_csr_string(csr_tbl[i]),
1589 iwl_read32(bus(trans), csr_tbl[i]));
1590 }
1591 }
1592
1593 #ifdef CONFIG_IWLWIFI_DEBUGFS
1594 /* create and remove of files */
1595 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1596 if (!debugfs_create_file(#name, mode, parent, trans, \
1597 &iwl_dbgfs_##name##_ops)) \
1598 return -ENOMEM; \
1599 } while (0)
1600
1601 /* file operation */
1602 #define DEBUGFS_READ_FUNC(name) \
1603 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1604 char __user *user_buf, \
1605 size_t count, loff_t *ppos);
1606
1607 #define DEBUGFS_WRITE_FUNC(name) \
1608 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1609 const char __user *user_buf, \
1610 size_t count, loff_t *ppos);
1611
1612
1613 static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file)
1614 {
1615 file->private_data = inode->i_private;
1616 return 0;
1617 }
1618
1619 #define DEBUGFS_READ_FILE_OPS(name) \
1620 DEBUGFS_READ_FUNC(name); \
1621 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1622 .read = iwl_dbgfs_##name##_read, \
1623 .open = iwl_dbgfs_open_file_generic, \
1624 .llseek = generic_file_llseek, \
1625 };
1626
1627 #define DEBUGFS_WRITE_FILE_OPS(name) \
1628 DEBUGFS_WRITE_FUNC(name); \
1629 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1630 .write = iwl_dbgfs_##name##_write, \
1631 .open = iwl_dbgfs_open_file_generic, \
1632 .llseek = generic_file_llseek, \
1633 };
1634
1635 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1636 DEBUGFS_READ_FUNC(name); \
1637 DEBUGFS_WRITE_FUNC(name); \
1638 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1639 .write = iwl_dbgfs_##name##_write, \
1640 .read = iwl_dbgfs_##name##_read, \
1641 .open = iwl_dbgfs_open_file_generic, \
1642 .llseek = generic_file_llseek, \
1643 };
1644
1645 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1646 char __user *user_buf,
1647 size_t count, loff_t *ppos)
1648 {
1649 struct iwl_trans *trans = file->private_data;
1650 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1651 struct iwl_tx_queue *txq;
1652 struct iwl_queue *q;
1653 char *buf;
1654 int pos = 0;
1655 int cnt;
1656 int ret;
1657 const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num;
1658
1659 if (!trans_pcie->txq) {
1660 IWL_ERR(trans, "txq not ready\n");
1661 return -EAGAIN;
1662 }
1663 buf = kzalloc(bufsz, GFP_KERNEL);
1664 if (!buf)
1665 return -ENOMEM;
1666
1667 for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1668 txq = &trans_pcie->txq[cnt];
1669 q = &txq->q;
1670 pos += scnprintf(buf + pos, bufsz - pos,
1671 "hwq %.2d: read=%u write=%u stop=%d"
1672 " swq_id=%#.2x (ac %d/hwq %d)\n",
1673 cnt, q->read_ptr, q->write_ptr,
1674 !!test_bit(cnt, trans_pcie->queue_stopped),
1675 txq->swq_id, txq->swq_id & 3,
1676 (txq->swq_id >> 2) & 0x1f);
1677 if (cnt >= 4)
1678 continue;
1679 /* for the ACs, display the stop count too */
1680 pos += scnprintf(buf + pos, bufsz - pos,
1681 " stop-count: %d\n",
1682 atomic_read(&trans_pcie->queue_stop_count[cnt]));
1683 }
1684 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1685 kfree(buf);
1686 return ret;
1687 }
1688
1689 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1690 char __user *user_buf,
1691 size_t count, loff_t *ppos) {
1692 struct iwl_trans *trans = file->private_data;
1693 struct iwl_trans_pcie *trans_pcie =
1694 IWL_TRANS_GET_PCIE_TRANS(trans);
1695 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1696 char buf[256];
1697 int pos = 0;
1698 const size_t bufsz = sizeof(buf);
1699
1700 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1701 rxq->read);
1702 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1703 rxq->write);
1704 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1705 rxq->free_count);
1706 if (rxq->rb_stts) {
1707 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1708 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1709 } else {
1710 pos += scnprintf(buf + pos, bufsz - pos,
1711 "closed_rb_num: Not Allocated\n");
1712 }
1713 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1714 }
1715
1716 static ssize_t iwl_dbgfs_log_event_read(struct file *file,
1717 char __user *user_buf,
1718 size_t count, loff_t *ppos)
1719 {
1720 struct iwl_trans *trans = file->private_data;
1721 char *buf;
1722 int pos = 0;
1723 ssize_t ret = -ENOMEM;
1724
1725 ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
1726 if (buf) {
1727 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1728 kfree(buf);
1729 }
1730 return ret;
1731 }
1732
1733 static ssize_t iwl_dbgfs_log_event_write(struct file *file,
1734 const char __user *user_buf,
1735 size_t count, loff_t *ppos)
1736 {
1737 struct iwl_trans *trans = file->private_data;
1738 u32 event_log_flag;
1739 char buf[8];
1740 int buf_size;
1741
1742 memset(buf, 0, sizeof(buf));
1743 buf_size = min(count, sizeof(buf) - 1);
1744 if (copy_from_user(buf, user_buf, buf_size))
1745 return -EFAULT;
1746 if (sscanf(buf, "%d", &event_log_flag) != 1)
1747 return -EFAULT;
1748 if (event_log_flag == 1)
1749 iwl_dump_nic_event_log(trans, true, NULL, false);
1750
1751 return count;
1752 }
1753
1754 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1755 char __user *user_buf,
1756 size_t count, loff_t *ppos) {
1757
1758 struct iwl_trans *trans = file->private_data;
1759 struct iwl_trans_pcie *trans_pcie =
1760 IWL_TRANS_GET_PCIE_TRANS(trans);
1761 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1762
1763 int pos = 0;
1764 char *buf;
1765 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1766 ssize_t ret;
1767
1768 buf = kzalloc(bufsz, GFP_KERNEL);
1769 if (!buf) {
1770 IWL_ERR(trans, "Can not allocate Buffer\n");
1771 return -ENOMEM;
1772 }
1773
1774 pos += scnprintf(buf + pos, bufsz - pos,
1775 "Interrupt Statistics Report:\n");
1776
1777 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1778 isr_stats->hw);
1779 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1780 isr_stats->sw);
1781 if (isr_stats->sw || isr_stats->hw) {
1782 pos += scnprintf(buf + pos, bufsz - pos,
1783 "\tLast Restarting Code: 0x%X\n",
1784 isr_stats->err_code);
1785 }
1786 #ifdef CONFIG_IWLWIFI_DEBUG
1787 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1788 isr_stats->sch);
1789 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1790 isr_stats->alive);
1791 #endif
1792 pos += scnprintf(buf + pos, bufsz - pos,
1793 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1794
1795 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1796 isr_stats->ctkill);
1797
1798 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1799 isr_stats->wakeup);
1800
1801 pos += scnprintf(buf + pos, bufsz - pos,
1802 "Rx command responses:\t\t %u\n", isr_stats->rx);
1803
1804 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1805 isr_stats->tx);
1806
1807 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1808 isr_stats->unhandled);
1809
1810 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1811 kfree(buf);
1812 return ret;
1813 }
1814
1815 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1816 const char __user *user_buf,
1817 size_t count, loff_t *ppos)
1818 {
1819 struct iwl_trans *trans = file->private_data;
1820 struct iwl_trans_pcie *trans_pcie =
1821 IWL_TRANS_GET_PCIE_TRANS(trans);
1822 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1823
1824 char buf[8];
1825 int buf_size;
1826 u32 reset_flag;
1827
1828 memset(buf, 0, sizeof(buf));
1829 buf_size = min(count, sizeof(buf) - 1);
1830 if (copy_from_user(buf, user_buf, buf_size))
1831 return -EFAULT;
1832 if (sscanf(buf, "%x", &reset_flag) != 1)
1833 return -EFAULT;
1834 if (reset_flag == 0)
1835 memset(isr_stats, 0, sizeof(*isr_stats));
1836
1837 return count;
1838 }
1839
1840 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1841 const char __user *user_buf,
1842 size_t count, loff_t *ppos)
1843 {
1844 struct iwl_trans *trans = file->private_data;
1845 char buf[8];
1846 int buf_size;
1847 int csr;
1848
1849 memset(buf, 0, sizeof(buf));
1850 buf_size = min(count, sizeof(buf) - 1);
1851 if (copy_from_user(buf, user_buf, buf_size))
1852 return -EFAULT;
1853 if (sscanf(buf, "%d", &csr) != 1)
1854 return -EFAULT;
1855
1856 iwl_dump_csr(trans);
1857
1858 return count;
1859 }
1860
1861 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1862 char __user *user_buf,
1863 size_t count, loff_t *ppos)
1864 {
1865 struct iwl_trans *trans = file->private_data;
1866 char *buf;
1867 int pos = 0;
1868 ssize_t ret = -EFAULT;
1869
1870 ret = pos = iwl_dump_fh(trans, &buf, true);
1871 if (buf) {
1872 ret = simple_read_from_buffer(user_buf,
1873 count, ppos, buf, pos);
1874 kfree(buf);
1875 }
1876
1877 return ret;
1878 }
1879
1880 DEBUGFS_READ_WRITE_FILE_OPS(log_event);
1881 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1882 DEBUGFS_READ_FILE_OPS(fh_reg);
1883 DEBUGFS_READ_FILE_OPS(rx_queue);
1884 DEBUGFS_READ_FILE_OPS(tx_queue);
1885 DEBUGFS_WRITE_FILE_OPS(csr);
1886
1887 /*
1888 * Create the debugfs files and directories
1889 *
1890 */
1891 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1892 struct dentry *dir)
1893 {
1894 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1895 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1896 DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
1897 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1898 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1899 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1900 return 0;
1901 }
1902 #else
1903 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1904 struct dentry *dir)
1905 { return 0; }
1906
1907 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1908
1909 const struct iwl_trans_ops trans_ops_pcie = {
1910 .alloc = iwl_trans_pcie_alloc,
1911 .request_irq = iwl_trans_pcie_request_irq,
1912 .fw_alive = iwl_trans_pcie_fw_alive,
1913 .start_device = iwl_trans_pcie_start_device,
1914 .prepare_card_hw = iwl_trans_pcie_prepare_card_hw,
1915 .stop_device = iwl_trans_pcie_stop_device,
1916
1917 .wake_any_queue = iwl_trans_pcie_wake_any_queue,
1918
1919 .send_cmd = iwl_trans_pcie_send_cmd,
1920
1921 .tx = iwl_trans_pcie_tx,
1922 .reclaim = iwl_trans_pcie_reclaim,
1923
1924 .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
1925 .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc,
1926 .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
1927
1928 .kick_nic = iwl_trans_pcie_kick_nic,
1929
1930 .free = iwl_trans_pcie_free,
1931 .stop_queue = iwl_trans_pcie_stop_queue,
1932
1933 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1934
1935 .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
1936 .check_stuck_queue = iwl_trans_pcie_check_stuck_queue,
1937
1938 #ifdef CONFIG_PM_SLEEP
1939 .suspend = iwl_trans_pcie_suspend,
1940 .resume = iwl_trans_pcie_resume,
1941 #endif
1942 };
Linux kernel - Deliverables
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