1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *****************************************************************************/
63 #include <linux/pci.h>
64 #include <linux/pci-aspm.h>
65 #include <linux/interrupt.h>
66 #include <linux/debugfs.h>
67 #include <linux/bitops.h>
68 #include <linux/gfp.h>
70 #include "iwl-trans.h"
71 #include "iwl-trans-pcie-int.h"
74 #include "iwl-shared.h"
75 #include "iwl-eeprom.h"
76 #include "iwl-agn-hw.h"
78 static int iwl_trans_rx_alloc(struct iwl_trans
*trans
)
80 struct iwl_trans_pcie
*trans_pcie
=
81 IWL_TRANS_GET_PCIE_TRANS(trans
);
82 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
83 struct device
*dev
= bus(trans
)->dev
;
85 memset(&trans_pcie
->rxq
, 0, sizeof(trans_pcie
->rxq
));
87 spin_lock_init(&rxq
->lock
);
89 if (WARN_ON(rxq
->bd
|| rxq
->rb_stts
))
92 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
93 rxq
->bd
= dma_zalloc_coherent(dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
94 &rxq
->bd_dma
, GFP_KERNEL
);
98 /*Allocate the driver's pointer to receive buffer status */
99 rxq
->rb_stts
= dma_zalloc_coherent(dev
, sizeof(*rxq
->rb_stts
),
100 &rxq
->rb_stts_dma
, GFP_KERNEL
);
107 dma_free_coherent(dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
108 rxq
->bd
, rxq
->bd_dma
);
109 memset(&rxq
->bd_dma
, 0, sizeof(rxq
->bd_dma
));
115 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans
*trans
)
117 struct iwl_trans_pcie
*trans_pcie
=
118 IWL_TRANS_GET_PCIE_TRANS(trans
);
119 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
122 /* Fill the rx_used queue with _all_ of the Rx buffers */
123 for (i
= 0; i
< RX_FREE_BUFFERS
+ RX_QUEUE_SIZE
; i
++) {
124 /* In the reset function, these buffers may have been allocated
125 * to an SKB, so we need to unmap and free potential storage */
126 if (rxq
->pool
[i
].page
!= NULL
) {
127 dma_unmap_page(bus(trans
)->dev
, rxq
->pool
[i
].page_dma
,
128 PAGE_SIZE
<< hw_params(trans
).rx_page_order
,
130 __free_pages(rxq
->pool
[i
].page
,
131 hw_params(trans
).rx_page_order
);
132 rxq
->pool
[i
].page
= NULL
;
134 list_add_tail(&rxq
->pool
[i
].list
, &rxq
->rx_used
);
138 static void iwl_trans_rx_hw_init(struct iwl_trans
*trans
,
139 struct iwl_rx_queue
*rxq
)
142 const u32 rfdnlog
= RX_QUEUE_SIZE_LOG
; /* 256 RBDs */
143 u32 rb_timeout
= RX_RB_TIMEOUT
; /* FIXME: RX_RB_TIMEOUT for all devices? */
145 if (iwlagn_mod_params
.amsdu_size_8K
)
146 rb_size
= FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K
;
148 rb_size
= FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K
;
151 iwl_write_direct32(bus(trans
), FH_MEM_RCSR_CHNL0_CONFIG_REG
, 0);
153 /* Reset driver's Rx queue write index */
154 iwl_write_direct32(bus(trans
), FH_RSCSR_CHNL0_RBDCB_WPTR_REG
, 0);
156 /* Tell device where to find RBD circular buffer in DRAM */
157 iwl_write_direct32(bus(trans
), FH_RSCSR_CHNL0_RBDCB_BASE_REG
,
158 (u32
)(rxq
->bd_dma
>> 8));
160 /* Tell device where in DRAM to update its Rx status */
161 iwl_write_direct32(bus(trans
), FH_RSCSR_CHNL0_STTS_WPTR_REG
,
162 rxq
->rb_stts_dma
>> 4);
165 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
166 * the credit mechanism in 5000 HW RX FIFO
167 * Direct rx interrupts to hosts
168 * Rx buffer size 4 or 8k
172 iwl_write_direct32(bus(trans
), FH_MEM_RCSR_CHNL0_CONFIG_REG
,
173 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL
|
174 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY
|
175 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL
|
176 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK
|
178 (rb_timeout
<< FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS
)|
179 (rfdnlog
<< FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS
));
181 /* Set interrupt coalescing timer to default (2048 usecs) */
182 iwl_write8(bus(trans
), CSR_INT_COALESCING
, IWL_HOST_INT_TIMEOUT_DEF
);
185 static int iwl_rx_init(struct iwl_trans
*trans
)
187 struct iwl_trans_pcie
*trans_pcie
=
188 IWL_TRANS_GET_PCIE_TRANS(trans
);
189 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
195 err
= iwl_trans_rx_alloc(trans
);
200 spin_lock_irqsave(&rxq
->lock
, flags
);
201 INIT_LIST_HEAD(&rxq
->rx_free
);
202 INIT_LIST_HEAD(&rxq
->rx_used
);
204 iwl_trans_rxq_free_rx_bufs(trans
);
206 for (i
= 0; i
< RX_QUEUE_SIZE
; i
++)
207 rxq
->queue
[i
] = NULL
;
209 /* Set us so that we have processed and used all buffers, but have
210 * not restocked the Rx queue with fresh buffers */
211 rxq
->read
= rxq
->write
= 0;
212 rxq
->write_actual
= 0;
214 spin_unlock_irqrestore(&rxq
->lock
, flags
);
216 iwlagn_rx_replenish(trans
);
218 iwl_trans_rx_hw_init(trans
, rxq
);
220 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
221 rxq
->need_update
= 1;
222 iwl_rx_queue_update_write_ptr(trans
, rxq
);
223 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
228 static void iwl_trans_pcie_rx_free(struct iwl_trans
*trans
)
230 struct iwl_trans_pcie
*trans_pcie
=
231 IWL_TRANS_GET_PCIE_TRANS(trans
);
232 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
236 /*if rxq->bd is NULL, it means that nothing has been allocated,
239 IWL_DEBUG_INFO(trans
, "Free NULL rx context\n");
243 spin_lock_irqsave(&rxq
->lock
, flags
);
244 iwl_trans_rxq_free_rx_bufs(trans
);
245 spin_unlock_irqrestore(&rxq
->lock
, flags
);
247 dma_free_coherent(bus(trans
)->dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
248 rxq
->bd
, rxq
->bd_dma
);
249 memset(&rxq
->bd_dma
, 0, sizeof(rxq
->bd_dma
));
253 dma_free_coherent(bus(trans
)->dev
,
254 sizeof(struct iwl_rb_status
),
255 rxq
->rb_stts
, rxq
->rb_stts_dma
);
257 IWL_DEBUG_INFO(trans
, "Free rxq->rb_stts which is NULL\n");
258 memset(&rxq
->rb_stts_dma
, 0, sizeof(rxq
->rb_stts_dma
));
262 static int iwl_trans_rx_stop(struct iwl_trans
*trans
)
266 iwl_write_direct32(bus(trans
), FH_MEM_RCSR_CHNL0_CONFIG_REG
, 0);
267 return iwl_poll_direct_bit(bus(trans
), FH_MEM_RSSR_RX_STATUS_REG
,
268 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE
, 1000);
271 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans
*trans
,
272 struct iwl_dma_ptr
*ptr
, size_t size
)
274 if (WARN_ON(ptr
->addr
))
277 ptr
->addr
= dma_alloc_coherent(bus(trans
)->dev
, size
,
278 &ptr
->dma
, GFP_KERNEL
);
285 static inline void iwlagn_free_dma_ptr(struct iwl_trans
*trans
,
286 struct iwl_dma_ptr
*ptr
)
288 if (unlikely(!ptr
->addr
))
291 dma_free_coherent(bus(trans
)->dev
, ptr
->size
, ptr
->addr
, ptr
->dma
);
292 memset(ptr
, 0, sizeof(*ptr
));
295 static int iwl_trans_txq_alloc(struct iwl_trans
*trans
,
296 struct iwl_tx_queue
*txq
, int slots_num
,
299 size_t tfd_sz
= sizeof(struct iwl_tfd
) * TFD_QUEUE_SIZE_MAX
;
302 if (WARN_ON(txq
->meta
|| txq
->cmd
|| txq
->skbs
|| txq
->tfds
))
305 txq
->q
.n_window
= slots_num
;
307 txq
->meta
= kcalloc(slots_num
, sizeof(txq
->meta
[0]), GFP_KERNEL
);
308 txq
->cmd
= kcalloc(slots_num
, sizeof(txq
->cmd
[0]), GFP_KERNEL
);
310 if (!txq
->meta
|| !txq
->cmd
)
313 if (txq_id
== trans
->shrd
->cmd_queue
)
314 for (i
= 0; i
< slots_num
; i
++) {
315 txq
->cmd
[i
] = kmalloc(sizeof(struct iwl_device_cmd
),
321 /* Alloc driver data array and TFD circular buffer */
322 /* Driver private data, only for Tx (not command) queues,
323 * not shared with device. */
324 if (txq_id
!= trans
->shrd
->cmd_queue
) {
325 txq
->skbs
= kcalloc(TFD_QUEUE_SIZE_MAX
, sizeof(txq
->skbs
[0]),
328 IWL_ERR(trans
, "kmalloc for auxiliary BD "
329 "structures failed\n");
336 /* Circular buffer of transmit frame descriptors (TFDs),
337 * shared with device */
338 txq
->tfds
= dma_alloc_coherent(bus(trans
)->dev
, tfd_sz
,
339 &txq
->q
.dma_addr
, GFP_KERNEL
);
341 IWL_ERR(trans
, "dma_alloc_coherent(%zd) failed\n", tfd_sz
);
350 /* since txq->cmd has been zeroed,
351 * all non allocated cmd[i] will be NULL */
352 if (txq
->cmd
&& txq_id
== trans
->shrd
->cmd_queue
)
353 for (i
= 0; i
< slots_num
; i
++)
364 static int iwl_trans_txq_init(struct iwl_trans
*trans
, struct iwl_tx_queue
*txq
,
365 int slots_num
, u32 txq_id
)
369 txq
->need_update
= 0;
370 memset(txq
->meta
, 0, sizeof(txq
->meta
[0]) * slots_num
);
373 * For the default queues 0-3, set up the swq_id
374 * already -- all others need to get one later
375 * (if they need one at all).
378 iwl_set_swq_id(txq
, txq_id
, txq_id
);
380 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
381 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
382 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX
& (TFD_QUEUE_SIZE_MAX
- 1));
384 /* Initialize queue's high/low-water marks, and head/tail indexes */
385 ret
= iwl_queue_init(&txq
->q
, TFD_QUEUE_SIZE_MAX
, slots_num
,
391 * Tell nic where to find circular buffer of Tx Frame Descriptors for
392 * given Tx queue, and enable the DMA channel used for that queue.
393 * Circular buffer (TFD queue in DRAM) physical base address */
394 iwl_write_direct32(bus(trans
), FH_MEM_CBBC_QUEUE(txq_id
),
395 txq
->q
.dma_addr
>> 8);
401 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
403 static void iwl_tx_queue_unmap(struct iwl_trans
*trans
, int txq_id
)
405 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
406 struct iwl_tx_queue
*txq
= &trans_pcie
->txq
[txq_id
];
407 struct iwl_queue
*q
= &txq
->q
;
408 enum dma_data_direction dma_dir
;
415 /* In the command queue, all the TBs are mapped as BIDI
416 * so unmap them as such.
418 if (txq_id
== trans
->shrd
->cmd_queue
) {
419 dma_dir
= DMA_BIDIRECTIONAL
;
420 lock
= &trans
->hcmd_lock
;
422 dma_dir
= DMA_TO_DEVICE
;
423 lock
= &trans
->shrd
->sta_lock
;
426 spin_lock_irqsave(lock
, flags
);
427 while (q
->write_ptr
!= q
->read_ptr
) {
428 /* The read_ptr needs to bound by q->n_window */
429 iwlagn_txq_free_tfd(trans
, txq
, get_cmd_index(q
, q
->read_ptr
),
431 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
);
433 spin_unlock_irqrestore(lock
, flags
);
437 * iwl_tx_queue_free - Deallocate DMA queue.
438 * @txq: Transmit queue to deallocate.
440 * Empty queue by removing and destroying all BD's.
442 * 0-fill, but do not free "txq" descriptor structure.
444 static void iwl_tx_queue_free(struct iwl_trans
*trans
, int txq_id
)
446 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
447 struct iwl_tx_queue
*txq
= &trans_pcie
->txq
[txq_id
];
448 struct device
*dev
= bus(trans
)->dev
;
453 iwl_tx_queue_unmap(trans
, txq_id
);
455 /* De-alloc array of command/tx buffers */
457 if (txq_id
== trans
->shrd
->cmd_queue
)
458 for (i
= 0; i
< txq
->q
.n_window
; i
++)
461 /* De-alloc circular buffer of TFDs */
463 dma_free_coherent(dev
, sizeof(struct iwl_tfd
) *
464 txq
->q
.n_bd
, txq
->tfds
, txq
->q
.dma_addr
);
465 memset(&txq
->q
.dma_addr
, 0, sizeof(txq
->q
.dma_addr
));
468 /* De-alloc array of per-TFD driver data */
472 /* deallocate arrays */
478 /* 0-fill queue descriptor structure */
479 memset(txq
, 0, sizeof(*txq
));
483 * iwl_trans_tx_free - Free TXQ Context
485 * Destroy all TX DMA queues and structures
487 static void iwl_trans_pcie_tx_free(struct iwl_trans
*trans
)
490 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
493 if (trans_pcie
->txq
) {
495 txq_id
< hw_params(trans
).max_txq_num
; txq_id
++)
496 iwl_tx_queue_free(trans
, txq_id
);
499 kfree(trans_pcie
->txq
);
500 trans_pcie
->txq
= NULL
;
502 iwlagn_free_dma_ptr(trans
, &trans_pcie
->kw
);
504 iwlagn_free_dma_ptr(trans
, &trans_pcie
->scd_bc_tbls
);
508 * iwl_trans_tx_alloc - allocate TX context
509 * Allocate all Tx DMA structures and initialize them
514 static int iwl_trans_tx_alloc(struct iwl_trans
*trans
)
517 int txq_id
, slots_num
;
518 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
520 u16 scd_bc_tbls_size
= hw_params(trans
).max_txq_num
*
521 sizeof(struct iwlagn_scd_bc_tbl
);
523 /*It is not allowed to alloc twice, so warn when this happens.
524 * We cannot rely on the previous allocation, so free and fail */
525 if (WARN_ON(trans_pcie
->txq
)) {
530 ret
= iwlagn_alloc_dma_ptr(trans
, &trans_pcie
->scd_bc_tbls
,
533 IWL_ERR(trans
, "Scheduler BC Table allocation failed\n");
537 /* Alloc keep-warm buffer */
538 ret
= iwlagn_alloc_dma_ptr(trans
, &trans_pcie
->kw
, IWL_KW_SIZE
);
540 IWL_ERR(trans
, "Keep Warm allocation failed\n");
544 trans_pcie
->txq
= kcalloc(hw_params(trans
).max_txq_num
,
545 sizeof(struct iwl_tx_queue
), GFP_KERNEL
);
546 if (!trans_pcie
->txq
) {
547 IWL_ERR(trans
, "Not enough memory for txq\n");
552 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
553 for (txq_id
= 0; txq_id
< hw_params(trans
).max_txq_num
; txq_id
++) {
554 slots_num
= (txq_id
== trans
->shrd
->cmd_queue
) ?
555 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
556 ret
= iwl_trans_txq_alloc(trans
, &trans_pcie
->txq
[txq_id
],
559 IWL_ERR(trans
, "Tx %d queue alloc failed\n", txq_id
);
567 iwl_trans_pcie_tx_free(trans
);
571 static int iwl_tx_init(struct iwl_trans
*trans
)
574 int txq_id
, slots_num
;
577 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
579 if (!trans_pcie
->txq
) {
580 ret
= iwl_trans_tx_alloc(trans
);
586 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
588 /* Turn off all Tx DMA fifos */
589 iwl_write_prph(bus(trans
), SCD_TXFACT
, 0);
591 /* Tell NIC where to find the "keep warm" buffer */
592 iwl_write_direct32(bus(trans
), FH_KW_MEM_ADDR_REG
,
593 trans_pcie
->kw
.dma
>> 4);
595 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
597 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
598 for (txq_id
= 0; txq_id
< hw_params(trans
).max_txq_num
; txq_id
++) {
599 slots_num
= (txq_id
== trans
->shrd
->cmd_queue
) ?
600 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
601 ret
= iwl_trans_txq_init(trans
, &trans_pcie
->txq
[txq_id
],
604 IWL_ERR(trans
, "Tx %d queue init failed\n", txq_id
);
611 /*Upon error, free only if we allocated something */
613 iwl_trans_pcie_tx_free(trans
);
617 static void iwl_set_pwr_vmain(struct iwl_trans
*trans
)
620 * (for documentation purposes)
621 * to set power to V_AUX, do:
623 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
624 iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
625 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
626 ~APMG_PS_CTRL_MSK_PWR_SRC);
629 iwl_set_bits_mask_prph(bus(trans
), APMG_PS_CTRL_REG
,
630 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN
,
631 ~APMG_PS_CTRL_MSK_PWR_SRC
);
634 static int iwl_nic_init(struct iwl_trans
*trans
)
639 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
640 iwl_apm_init(priv(trans
));
642 /* Set interrupt coalescing calibration timer to default (512 usecs) */
643 iwl_write8(bus(trans
), CSR_INT_COALESCING
,
644 IWL_HOST_INT_CALIB_TIMEOUT_DEF
);
646 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
648 iwl_set_pwr_vmain(trans
);
650 iwl_nic_config(priv(trans
));
652 #ifndef CONFIG_IWLWIFI_IDI
653 /* Allocate the RX queue, or reset if it is already allocated */
657 /* Allocate or reset and init all Tx and Command queues */
658 if (iwl_tx_init(trans
))
661 if (hw_params(trans
).shadow_reg_enable
) {
662 /* enable shadow regs in HW */
663 iwl_set_bit(bus(trans
), CSR_MAC_SHADOW_REG_CTRL
,
667 set_bit(STATUS_INIT
, &trans
->shrd
->status
);
672 #define HW_READY_TIMEOUT (50)
674 /* Note: returns poll_bit return value, which is >= 0 if success */
675 static int iwl_set_hw_ready(struct iwl_trans
*trans
)
679 iwl_set_bit(bus(trans
), CSR_HW_IF_CONFIG_REG
,
680 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
);
682 /* See if we got it */
683 ret
= iwl_poll_bit(bus(trans
), CSR_HW_IF_CONFIG_REG
,
684 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
685 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
688 IWL_DEBUG_INFO(trans
, "hardware%s ready\n", ret
< 0 ? " not" : "");
692 /* Note: returns standard 0/-ERROR code */
693 static int iwl_trans_pcie_prepare_card_hw(struct iwl_trans
*trans
)
697 IWL_DEBUG_INFO(trans
, "iwl_trans_prepare_card_hw enter\n");
699 ret
= iwl_set_hw_ready(trans
);
703 /* If HW is not ready, prepare the conditions to check again */
704 iwl_set_bit(bus(trans
), CSR_HW_IF_CONFIG_REG
,
705 CSR_HW_IF_CONFIG_REG_PREPARE
);
707 ret
= iwl_poll_bit(bus(trans
), CSR_HW_IF_CONFIG_REG
,
708 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE
,
709 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE
, 150000);
714 /* HW should be ready by now, check again. */
715 ret
= iwl_set_hw_ready(trans
);
721 #define IWL_AC_UNSET -1
723 struct queue_to_fifo_ac
{
727 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo
[] = {
728 { IWL_TX_FIFO_VO
, IEEE80211_AC_VO
, },
729 { IWL_TX_FIFO_VI
, IEEE80211_AC_VI
, },
730 { IWL_TX_FIFO_BE
, IEEE80211_AC_BE
, },
731 { IWL_TX_FIFO_BK
, IEEE80211_AC_BK
, },
732 { IWLAGN_CMD_FIFO_NUM
, IWL_AC_UNSET
, },
733 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
734 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
735 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
736 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
737 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
738 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
741 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo
[] = {
742 { IWL_TX_FIFO_VO
, IEEE80211_AC_VO
, },
743 { IWL_TX_FIFO_VI
, IEEE80211_AC_VI
, },
744 { IWL_TX_FIFO_BE
, IEEE80211_AC_BE
, },
745 { IWL_TX_FIFO_BK
, IEEE80211_AC_BK
, },
746 { IWL_TX_FIFO_BK_IPAN
, IEEE80211_AC_BK
, },
747 { IWL_TX_FIFO_BE_IPAN
, IEEE80211_AC_BE
, },
748 { IWL_TX_FIFO_VI_IPAN
, IEEE80211_AC_VI
, },
749 { IWL_TX_FIFO_VO_IPAN
, IEEE80211_AC_VO
, },
750 { IWL_TX_FIFO_BE_IPAN
, 2, },
751 { IWLAGN_CMD_FIFO_NUM
, IWL_AC_UNSET
, },
752 { IWL_TX_FIFO_AUX
, IWL_AC_UNSET
, },
755 static const u8 iwlagn_bss_ac_to_fifo
[] = {
761 static const u8 iwlagn_bss_ac_to_queue
[] = {
764 static const u8 iwlagn_pan_ac_to_fifo
[] = {
770 static const u8 iwlagn_pan_ac_to_queue
[] = {
774 static int iwl_trans_pcie_start_device(struct iwl_trans
*trans
)
777 struct iwl_trans_pcie
*trans_pcie
=
778 IWL_TRANS_GET_PCIE_TRANS(trans
);
780 trans
->shrd
->ucode_owner
= IWL_OWNERSHIP_DRIVER
;
781 trans_pcie
->ac_to_queue
[IWL_RXON_CTX_BSS
] = iwlagn_bss_ac_to_queue
;
782 trans_pcie
->ac_to_queue
[IWL_RXON_CTX_PAN
] = iwlagn_pan_ac_to_queue
;
784 trans_pcie
->ac_to_fifo
[IWL_RXON_CTX_BSS
] = iwlagn_bss_ac_to_fifo
;
785 trans_pcie
->ac_to_fifo
[IWL_RXON_CTX_PAN
] = iwlagn_pan_ac_to_fifo
;
787 trans_pcie
->mcast_queue
[IWL_RXON_CTX_BSS
] = 0;
788 trans_pcie
->mcast_queue
[IWL_RXON_CTX_PAN
] = IWL_IPAN_MCAST_QUEUE
;
790 if ((hw_params(trans
).sku
& EEPROM_SKU_CAP_AMT_ENABLE
) &&
791 iwl_trans_pcie_prepare_card_hw(trans
)) {
792 IWL_WARN(trans
, "Exit HW not ready\n");
796 /* If platform's RF_KILL switch is NOT set to KILL */
797 if (iwl_read32(bus(trans
), CSR_GP_CNTRL
) &
798 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW
)
799 clear_bit(STATUS_RF_KILL_HW
, &trans
->shrd
->status
);
801 set_bit(STATUS_RF_KILL_HW
, &trans
->shrd
->status
);
803 if (iwl_is_rfkill(trans
->shrd
)) {
804 iwl_set_hw_rfkill_state(priv(trans
), true);
805 iwl_enable_interrupts(trans
);
809 iwl_write32(bus(trans
), CSR_INT
, 0xFFFFFFFF);
811 ret
= iwl_nic_init(trans
);
813 IWL_ERR(trans
, "Unable to init nic\n");
817 /* make sure rfkill handshake bits are cleared */
818 iwl_write32(bus(trans
), CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
819 iwl_write32(bus(trans
), CSR_UCODE_DRV_GP1_CLR
,
820 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED
);
822 /* clear (again), then enable host interrupts */
823 iwl_write32(bus(trans
), CSR_INT
, 0xFFFFFFFF);
824 iwl_enable_interrupts(trans
);
826 /* really make sure rfkill handshake bits are cleared */
827 iwl_write32(bus(trans
), CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
828 iwl_write32(bus(trans
), CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
834 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
835 * must be called under priv->shrd->lock and mac access
837 static void iwl_trans_txq_set_sched(struct iwl_trans
*trans
, u32 mask
)
839 iwl_write_prph(bus(trans
), SCD_TXFACT
, mask
);
842 static void iwl_tx_start(struct iwl_trans
*trans
)
844 const struct queue_to_fifo_ac
*queue_to_fifo
;
845 struct iwl_trans_pcie
*trans_pcie
=
846 IWL_TRANS_GET_PCIE_TRANS(trans
);
852 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
854 trans_pcie
->scd_base_addr
=
855 iwl_read_prph(bus(trans
), SCD_SRAM_BASE_ADDR
);
856 a
= trans_pcie
->scd_base_addr
+ SCD_CONTEXT_MEM_LOWER_BOUND
;
857 /* reset conext data memory */
858 for (; a
< trans_pcie
->scd_base_addr
+ SCD_CONTEXT_MEM_UPPER_BOUND
;
860 iwl_write_targ_mem(bus(trans
), a
, 0);
861 /* reset tx status memory */
862 for (; a
< trans_pcie
->scd_base_addr
+ SCD_TX_STTS_MEM_UPPER_BOUND
;
864 iwl_write_targ_mem(bus(trans
), a
, 0);
865 for (; a
< trans_pcie
->scd_base_addr
+
866 SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans
).max_txq_num
);
868 iwl_write_targ_mem(bus(trans
), a
, 0);
870 iwl_write_prph(bus(trans
), SCD_DRAM_BASE_ADDR
,
871 trans_pcie
->scd_bc_tbls
.dma
>> 10);
873 /* Enable DMA channel */
874 for (chan
= 0; chan
< FH_TCSR_CHNL_NUM
; chan
++)
875 iwl_write_direct32(bus(trans
), FH_TCSR_CHNL_TX_CONFIG_REG(chan
),
876 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
877 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE
);
879 /* Update FH chicken bits */
880 reg_val
= iwl_read_direct32(bus(trans
), FH_TX_CHICKEN_BITS_REG
);
881 iwl_write_direct32(bus(trans
), FH_TX_CHICKEN_BITS_REG
,
882 reg_val
| FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN
);
884 iwl_write_prph(bus(trans
), SCD_QUEUECHAIN_SEL
,
885 SCD_QUEUECHAIN_SEL_ALL(trans
));
886 iwl_write_prph(bus(trans
), SCD_AGGR_SEL
, 0);
888 /* initiate the queues */
889 for (i
= 0; i
< hw_params(trans
).max_txq_num
; i
++) {
890 iwl_write_prph(bus(trans
), SCD_QUEUE_RDPTR(i
), 0);
891 iwl_write_direct32(bus(trans
), HBUS_TARG_WRPTR
, 0 | (i
<< 8));
892 iwl_write_targ_mem(bus(trans
), trans_pcie
->scd_base_addr
+
893 SCD_CONTEXT_QUEUE_OFFSET(i
), 0);
894 iwl_write_targ_mem(bus(trans
), trans_pcie
->scd_base_addr
+
895 SCD_CONTEXT_QUEUE_OFFSET(i
) +
898 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS
) &
899 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK
) |
901 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS
) &
902 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK
));
905 iwl_write_prph(bus(trans
), SCD_INTERRUPT_MASK
,
906 IWL_MASK(0, hw_params(trans
).max_txq_num
));
908 /* Activate all Tx DMA/FIFO channels */
909 iwl_trans_txq_set_sched(trans
, IWL_MASK(0, 7));
911 /* map queues to FIFOs */
912 if (trans
->shrd
->valid_contexts
!= BIT(IWL_RXON_CTX_BSS
))
913 queue_to_fifo
= iwlagn_ipan_queue_to_tx_fifo
;
915 queue_to_fifo
= iwlagn_default_queue_to_tx_fifo
;
917 iwl_trans_set_wr_ptrs(trans
, trans
->shrd
->cmd_queue
, 0);
919 /* make sure all queue are not stopped */
920 memset(&trans_pcie
->queue_stopped
[0], 0,
921 sizeof(trans_pcie
->queue_stopped
));
922 for (i
= 0; i
< 4; i
++)
923 atomic_set(&trans_pcie
->queue_stop_count
[i
], 0);
925 /* reset to 0 to enable all the queue first */
926 trans_pcie
->txq_ctx_active_msk
= 0;
928 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo
) <
929 IWLAGN_FIRST_AMPDU_QUEUE
);
930 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo
) <
931 IWLAGN_FIRST_AMPDU_QUEUE
);
933 for (i
= 0; i
< IWLAGN_FIRST_AMPDU_QUEUE
; i
++) {
934 int fifo
= queue_to_fifo
[i
].fifo
;
935 int ac
= queue_to_fifo
[i
].ac
;
937 iwl_txq_ctx_activate(trans_pcie
, i
);
939 if (fifo
== IWL_TX_FIFO_UNUSED
)
942 if (ac
!= IWL_AC_UNSET
)
943 iwl_set_swq_id(&trans_pcie
->txq
[i
], ac
, i
);
944 iwl_trans_tx_queue_set_status(trans
, &trans_pcie
->txq
[i
],
948 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
950 /* Enable L1-Active */
951 iwl_clear_bits_prph(bus(trans
), APMG_PCIDEV_STT_REG
,
952 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
955 static void iwl_trans_pcie_fw_alive(struct iwl_trans
*trans
)
957 iwl_reset_ict(trans
);
962 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
964 static int iwl_trans_tx_stop(struct iwl_trans
*trans
)
968 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
970 /* Turn off all Tx DMA fifos */
971 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
973 iwl_trans_txq_set_sched(trans
, 0);
975 /* Stop each Tx DMA channel, and wait for it to be idle */
976 for (ch
= 0; ch
< FH_TCSR_CHNL_NUM
; ch
++) {
977 iwl_write_direct32(bus(trans
),
978 FH_TCSR_CHNL_TX_CONFIG_REG(ch
), 0x0);
979 if (iwl_poll_direct_bit(bus(trans
), FH_TSSR_TX_STATUS_REG
,
980 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch
),
982 IWL_ERR(trans
, "Failing on timeout while stopping"
983 " DMA channel %d [0x%08x]", ch
,
984 iwl_read_direct32(bus(trans
),
985 FH_TSSR_TX_STATUS_REG
));
987 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
989 if (!trans_pcie
->txq
) {
990 IWL_WARN(trans
, "Stopping tx queues that aren't allocated...");
994 /* Unmap DMA from host system and free skb's */
995 for (txq_id
= 0; txq_id
< hw_params(trans
).max_txq_num
; txq_id
++)
996 iwl_tx_queue_unmap(trans
, txq_id
);
1001 static void iwl_trans_pcie_stop_device(struct iwl_trans
*trans
)
1003 unsigned long flags
;
1004 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1006 /* tell the device to stop sending interrupts */
1007 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
1008 iwl_disable_interrupts(trans
);
1009 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
1011 /* device going down, Stop using ICT table */
1012 iwl_disable_ict(trans
);
1015 * If a HW restart happens during firmware loading,
1016 * then the firmware loading might call this function
1017 * and later it might be called again due to the
1018 * restart. So don't process again if the device is
1021 if (test_bit(STATUS_DEVICE_ENABLED
, &trans
->shrd
->status
)) {
1022 iwl_trans_tx_stop(trans
);
1023 #ifndef CONFIG_IWLWIFI_IDI
1024 iwl_trans_rx_stop(trans
);
1026 /* Power-down device's busmaster DMA clocks */
1027 iwl_write_prph(bus(trans
), APMG_CLK_DIS_REG
,
1028 APMG_CLK_VAL_DMA_CLK_RQT
);
1032 /* Make sure (redundant) we've released our request to stay awake */
1033 iwl_clear_bit(bus(trans
), CSR_GP_CNTRL
,
1034 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1036 /* Stop the device, and put it in low power state */
1037 iwl_apm_stop(priv(trans
));
1039 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1040 * Clean again the interrupt here
1042 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
1043 iwl_disable_interrupts(trans
);
1044 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
1046 /* wait to make sure we flush pending tasklet*/
1047 synchronize_irq(trans
->irq
);
1048 tasklet_kill(&trans_pcie
->irq_tasklet
);
1050 /* stop and reset the on-board processor */
1051 iwl_write32(bus(trans
), CSR_RESET
, CSR_RESET_REG_FLAG_NEVO_RESET
);
1054 static int iwl_trans_pcie_tx(struct iwl_trans
*trans
, struct sk_buff
*skb
,
1055 struct iwl_device_cmd
*dev_cmd
, enum iwl_rxon_context_id ctx
,
1058 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1059 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1060 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1061 struct iwl_tx_cmd
*tx_cmd
= (struct iwl_tx_cmd
*) dev_cmd
->payload
;
1062 struct iwl_cmd_meta
*out_meta
;
1063 struct iwl_tx_queue
*txq
;
1064 struct iwl_queue
*q
;
1066 dma_addr_t phys_addr
= 0;
1067 dma_addr_t txcmd_phys
;
1068 dma_addr_t scratch_phys
;
1069 u16 len
, firstlen
, secondlen
;
1070 u8 wait_write_ptr
= 0;
1072 bool is_agg
= false;
1073 __le16 fc
= hdr
->frame_control
;
1074 u8 hdr_len
= ieee80211_hdrlen(fc
);
1075 u16 __maybe_unused wifi_seq
;
1078 * Send this frame after DTIM -- there's a special queue
1079 * reserved for this for contexts that support AP mode.
1081 if (info
->flags
& IEEE80211_TX_CTL_SEND_AFTER_DTIM
) {
1082 txq_id
= trans_pcie
->mcast_queue
[ctx
];
1085 * The microcode will clear the more data
1086 * bit in the last frame it transmits.
1088 hdr
->frame_control
|=
1089 cpu_to_le16(IEEE80211_FCTL_MOREDATA
);
1090 } else if (info
->flags
& IEEE80211_TX_CTL_TX_OFFCHAN
)
1091 txq_id
= IWL_AUX_QUEUE
;
1094 trans_pcie
->ac_to_queue
[ctx
][skb_get_queue_mapping(skb
)];
1096 /* aggregation is on for this <sta,tid> */
1097 if (info
->flags
& IEEE80211_TX_CTL_AMPDU
) {
1098 WARN_ON(tid
>= IWL_MAX_TID_COUNT
);
1099 txq_id
= trans_pcie
->agg_txq
[sta_id
][tid
];
1103 txq
= &trans_pcie
->txq
[txq_id
];
1106 /* In AGG mode, the index in the ring must correspond to the WiFi
1107 * sequence number. This is a HW requirements to help the SCD to parse
1109 * Check here that the packets are in the right place on the ring.
1111 #ifdef CONFIG_IWLWIFI_DEBUG
1112 wifi_seq
= SEQ_TO_SN(le16_to_cpu(hdr
->seq_ctrl
));
1113 WARN_ONCE(is_agg
&& ((wifi_seq
& 0xff) != q
->write_ptr
),
1114 "Q: %d WiFi Seq %d tfdNum %d",
1115 txq_id
, wifi_seq
, q
->write_ptr
);
1118 /* Set up driver data for this TFD */
1119 txq
->skbs
[q
->write_ptr
] = skb
;
1120 txq
->cmd
[q
->write_ptr
] = dev_cmd
;
1122 dev_cmd
->hdr
.cmd
= REPLY_TX
;
1123 dev_cmd
->hdr
.sequence
= cpu_to_le16((u16
)(QUEUE_TO_SEQ(txq_id
) |
1124 INDEX_TO_SEQ(q
->write_ptr
)));
1126 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1127 out_meta
= &txq
->meta
[q
->write_ptr
];
1130 * Use the first empty entry in this queue's command buffer array
1131 * to contain the Tx command and MAC header concatenated together
1132 * (payload data will be in another buffer).
1133 * Size of this varies, due to varying MAC header length.
1134 * If end is not dword aligned, we'll have 2 extra bytes at the end
1135 * of the MAC header (device reads on dword boundaries).
1136 * We'll tell device about this padding later.
1138 len
= sizeof(struct iwl_tx_cmd
) +
1139 sizeof(struct iwl_cmd_header
) + hdr_len
;
1140 firstlen
= (len
+ 3) & ~3;
1142 /* Tell NIC about any 2-byte padding after MAC header */
1143 if (firstlen
!= len
)
1144 tx_cmd
->tx_flags
|= TX_CMD_FLG_MH_PAD_MSK
;
1146 /* Physical address of this Tx command's header (not MAC header!),
1147 * within command buffer array. */
1148 txcmd_phys
= dma_map_single(bus(trans
)->dev
,
1149 &dev_cmd
->hdr
, firstlen
,
1151 if (unlikely(dma_mapping_error(bus(trans
)->dev
, txcmd_phys
)))
1153 dma_unmap_addr_set(out_meta
, mapping
, txcmd_phys
);
1154 dma_unmap_len_set(out_meta
, len
, firstlen
);
1156 if (!ieee80211_has_morefrags(fc
)) {
1157 txq
->need_update
= 1;
1160 txq
->need_update
= 0;
1163 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1164 * if any (802.11 null frames have no payload). */
1165 secondlen
= skb
->len
- hdr_len
;
1166 if (secondlen
> 0) {
1167 phys_addr
= dma_map_single(bus(trans
)->dev
, skb
->data
+ hdr_len
,
1168 secondlen
, DMA_TO_DEVICE
);
1169 if (unlikely(dma_mapping_error(bus(trans
)->dev
, phys_addr
))) {
1170 dma_unmap_single(bus(trans
)->dev
,
1171 dma_unmap_addr(out_meta
, mapping
),
1172 dma_unmap_len(out_meta
, len
),
1178 /* Attach buffers to TFD */
1179 iwlagn_txq_attach_buf_to_tfd(trans
, txq
, txcmd_phys
, firstlen
, 1);
1181 iwlagn_txq_attach_buf_to_tfd(trans
, txq
, phys_addr
,
1184 scratch_phys
= txcmd_phys
+ sizeof(struct iwl_cmd_header
) +
1185 offsetof(struct iwl_tx_cmd
, scratch
);
1187 /* take back ownership of DMA buffer to enable update */
1188 dma_sync_single_for_cpu(bus(trans
)->dev
, txcmd_phys
, firstlen
,
1190 tx_cmd
->dram_lsb_ptr
= cpu_to_le32(scratch_phys
);
1191 tx_cmd
->dram_msb_ptr
= iwl_get_dma_hi_addr(scratch_phys
);
1193 IWL_DEBUG_TX(trans
, "sequence nr = 0X%x\n",
1194 le16_to_cpu(dev_cmd
->hdr
.sequence
));
1195 IWL_DEBUG_TX(trans
, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd
->tx_flags
));
1196 iwl_print_hex_dump(trans
, IWL_DL_TX
, (u8
*)tx_cmd
, sizeof(*tx_cmd
));
1197 iwl_print_hex_dump(trans
, IWL_DL_TX
, (u8
*)tx_cmd
->hdr
, hdr_len
);
1199 /* Set up entry for this TFD in Tx byte-count array */
1200 iwl_trans_txq_update_byte_cnt_tbl(trans
, txq
, le16_to_cpu(tx_cmd
->len
));
1202 dma_sync_single_for_device(bus(trans
)->dev
, txcmd_phys
, firstlen
,
1205 trace_iwlwifi_dev_tx(priv(trans
),
1206 &((struct iwl_tfd
*)txq
->tfds
)[txq
->q
.write_ptr
],
1207 sizeof(struct iwl_tfd
),
1208 &dev_cmd
->hdr
, firstlen
,
1209 skb
->data
+ hdr_len
, secondlen
);
1211 /* Tell device the write index *just past* this latest filled TFD */
1212 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
1213 iwl_txq_update_write_ptr(trans
, txq
);
1216 * At this point the frame is "transmitted" successfully
1217 * and we will get a TX status notification eventually,
1218 * regardless of the value of ret. "ret" only indicates
1219 * whether or not we should update the write pointer.
1221 if (iwl_queue_space(q
) < q
->high_mark
) {
1222 if (wait_write_ptr
) {
1223 txq
->need_update
= 1;
1224 iwl_txq_update_write_ptr(trans
, txq
);
1226 iwl_stop_queue(trans
, txq
, "Queue is full");
1232 static void iwl_trans_pcie_kick_nic(struct iwl_trans
*trans
)
1234 /* Remove all resets to allow NIC to operate */
1235 iwl_write32(bus(trans
), CSR_RESET
, 0);
1238 static int iwl_trans_pcie_request_irq(struct iwl_trans
*trans
)
1240 struct iwl_trans_pcie
*trans_pcie
=
1241 IWL_TRANS_GET_PCIE_TRANS(trans
);
1244 trans_pcie
->inta_mask
= CSR_INI_SET_MASK
;
1246 tasklet_init(&trans_pcie
->irq_tasklet
, (void (*)(unsigned long))
1247 iwl_irq_tasklet
, (unsigned long)trans
);
1249 iwl_alloc_isr_ict(trans
);
1251 err
= request_irq(trans
->irq
, iwl_isr_ict
, IRQF_SHARED
,
1254 IWL_ERR(trans
, "Error allocating IRQ %d\n", trans
->irq
);
1255 iwl_free_isr_ict(trans
);
1259 INIT_WORK(&trans_pcie
->rx_replenish
, iwl_bg_rx_replenish
);
1263 static int iwl_trans_pcie_reclaim(struct iwl_trans
*trans
, int sta_id
, int tid
,
1264 int txq_id
, int ssn
, u32 status
,
1265 struct sk_buff_head
*skbs
)
1267 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1268 struct iwl_tx_queue
*txq
= &trans_pcie
->txq
[txq_id
];
1269 /* n_bd is usually 256 => n_bd - 1 = 0xff */
1270 int tfd_num
= ssn
& (txq
->q
.n_bd
- 1);
1273 txq
->time_stamp
= jiffies
;
1275 if (unlikely(txq_id
>= IWLAGN_FIRST_AMPDU_QUEUE
&&
1276 txq_id
!= trans_pcie
->agg_txq
[sta_id
][tid
])) {
1278 * FIXME: this is a uCode bug which need to be addressed,
1279 * log the information and return for now.
1280 * Since it is can possibly happen very often and in order
1281 * not to fill the syslog, don't use IWL_ERR or IWL_WARN
1283 IWL_DEBUG_TX_QUEUES(trans
, "Bad queue mapping txq_id %d, "
1284 "agg_txq[sta_id[tid] %d", txq_id
,
1285 trans_pcie
->agg_txq
[sta_id
][tid
]);
1289 if (txq
->q
.read_ptr
!= tfd_num
) {
1290 IWL_DEBUG_TX_REPLY(trans
, "[Q %d | AC %d] %d -> %d (%d)\n",
1291 txq_id
, iwl_get_queue_ac(txq
), txq
->q
.read_ptr
,
1293 freed
= iwl_tx_queue_reclaim(trans
, txq_id
, tfd_num
, skbs
);
1294 if (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
&&
1295 (!txq
->sched_retry
||
1296 status
!= TX_STATUS_FAIL_PASSIVE_NO_RX
))
1297 iwl_wake_queue(trans
, txq
, "Packets reclaimed");
1302 static void iwl_trans_pcie_write8(struct iwl_trans
*trans
, u32 ofs
, u8 val
)
1304 iowrite8(val
, IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1307 static void iwl_trans_pcie_write32(struct iwl_trans
*trans
, u32 ofs
, u32 val
)
1309 iowrite32(val
, IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1312 static u32
iwl_trans_pcie_read32(struct iwl_trans
*trans
, u32 ofs
)
1314 u32 val
= ioread32(IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1318 static void iwl_trans_pcie_free(struct iwl_trans
*trans
)
1320 struct iwl_trans_pcie
*trans_pcie
=
1321 IWL_TRANS_GET_PCIE_TRANS(trans
);
1323 iwl_calib_free_results(trans
);
1324 iwl_trans_pcie_tx_free(trans
);
1325 #ifndef CONFIG_IWLWIFI_IDI
1326 iwl_trans_pcie_rx_free(trans
);
1328 free_irq(trans
->irq
, trans
);
1329 iwl_free_isr_ict(trans
);
1331 pci_disable_msi(trans_pcie
->pci_dev
);
1332 pci_iounmap(trans_pcie
->pci_dev
, trans_pcie
->hw_base
);
1333 pci_release_regions(trans_pcie
->pci_dev
);
1334 pci_disable_device(trans_pcie
->pci_dev
);
1336 trans
->shrd
->trans
= NULL
;
1340 #ifdef CONFIG_PM_SLEEP
1341 static int iwl_trans_pcie_suspend(struct iwl_trans
*trans
)
1344 * This function is called when system goes into suspend state
1345 * mac80211 will call iwlagn_mac_stop() from the mac80211 suspend
1346 * function first but since iwlagn_mac_stop() has no knowledge of
1347 * who the caller is,
1348 * it will not call apm_ops.stop() to stop the DMA operation.
1349 * Calling apm_ops.stop here to make sure we stop the DMA.
1351 * But of course ... if we have configured WoWLAN then we did other
1352 * things already :-)
1354 if (!trans
->shrd
->wowlan
) {
1355 iwl_apm_stop(priv(trans
));
1357 iwl_disable_interrupts(trans
);
1358 iwl_clear_bit(bus(trans
), CSR_GP_CNTRL
,
1359 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1365 static int iwl_trans_pcie_resume(struct iwl_trans
*trans
)
1367 bool hw_rfkill
= false;
1369 iwl_enable_interrupts(trans
);
1371 if (!(iwl_read32(bus(trans
), CSR_GP_CNTRL
) &
1372 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW
))
1376 set_bit(STATUS_RF_KILL_HW
, &trans
->shrd
->status
);
1378 clear_bit(STATUS_RF_KILL_HW
, &trans
->shrd
->status
);
1380 iwl_set_hw_rfkill_state(priv(trans
), hw_rfkill
);
1384 #endif /* CONFIG_PM_SLEEP */
1386 static void iwl_trans_pcie_wake_any_queue(struct iwl_trans
*trans
,
1387 enum iwl_rxon_context_id ctx
,
1391 struct iwl_trans_pcie
*trans_pcie
=
1392 IWL_TRANS_GET_PCIE_TRANS(trans
);
1394 for (ac
= 0; ac
< AC_NUM
; ac
++) {
1395 txq_id
= trans_pcie
->ac_to_queue
[ctx
][ac
];
1396 IWL_DEBUG_TX_QUEUES(trans
, "Queue Status: Q[%d] %s\n",
1398 (atomic_read(&trans_pcie
->queue_stop_count
[ac
]) > 0)
1399 ? "stopped" : "awake");
1400 iwl_wake_queue(trans
, &trans_pcie
->txq
[txq_id
], msg
);
1404 static void iwl_trans_pcie_stop_queue(struct iwl_trans
*trans
, int txq_id
,
1407 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1409 iwl_stop_queue(trans
, &trans_pcie
->txq
[txq_id
], msg
);
1412 #define IWL_FLUSH_WAIT_MS 2000
1414 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans
*trans
)
1416 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1417 struct iwl_tx_queue
*txq
;
1418 struct iwl_queue
*q
;
1420 unsigned long now
= jiffies
;
1423 /* waiting for all the tx frames complete might take a while */
1424 for (cnt
= 0; cnt
< hw_params(trans
).max_txq_num
; cnt
++) {
1425 if (cnt
== trans
->shrd
->cmd_queue
)
1427 txq
= &trans_pcie
->txq
[cnt
];
1429 while (q
->read_ptr
!= q
->write_ptr
&& !time_after(jiffies
,
1430 now
+ msecs_to_jiffies(IWL_FLUSH_WAIT_MS
)))
1433 if (q
->read_ptr
!= q
->write_ptr
) {
1434 IWL_ERR(trans
, "fail to flush all tx fifo queues\n");
1443 * On every watchdog tick we check (latest) time stamp. If it does not
1444 * change during timeout period and queue is not empty we reset firmware.
1446 static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans
*trans
, int cnt
)
1448 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1449 struct iwl_tx_queue
*txq
= &trans_pcie
->txq
[cnt
];
1450 struct iwl_queue
*q
= &txq
->q
;
1451 unsigned long timeout
;
1453 if (q
->read_ptr
== q
->write_ptr
) {
1454 txq
->time_stamp
= jiffies
;
1458 timeout
= txq
->time_stamp
+
1459 msecs_to_jiffies(hw_params(trans
).wd_timeout
);
1461 if (time_after(jiffies
, timeout
)) {
1462 IWL_ERR(trans
, "Queue %d stuck for %u ms.\n", q
->id
,
1463 hw_params(trans
).wd_timeout
);
1464 IWL_ERR(trans
, "Current SW read_ptr %d write_ptr %d\n",
1465 q
->read_ptr
, q
->write_ptr
);
1466 IWL_ERR(trans
, "Current HW read_ptr %d write_ptr %d\n",
1467 iwl_read_prph(bus(trans
), SCD_QUEUE_RDPTR(cnt
))
1468 & (TFD_QUEUE_SIZE_MAX
- 1),
1469 iwl_read_prph(bus(trans
), SCD_QUEUE_WRPTR(cnt
)));
1476 static const char *get_fh_string(int cmd
)
1479 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG
);
1480 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG
);
1481 IWL_CMD(FH_RSCSR_CHNL0_WPTR
);
1482 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG
);
1483 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG
);
1484 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG
);
1485 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
);
1486 IWL_CMD(FH_TSSR_TX_STATUS_REG
);
1487 IWL_CMD(FH_TSSR_TX_ERROR_REG
);
1493 int iwl_dump_fh(struct iwl_trans
*trans
, char **buf
, bool display
)
1496 #ifdef CONFIG_IWLWIFI_DEBUG
1500 static const u32 fh_tbl
[] = {
1501 FH_RSCSR_CHNL0_STTS_WPTR_REG
,
1502 FH_RSCSR_CHNL0_RBDCB_BASE_REG
,
1503 FH_RSCSR_CHNL0_WPTR
,
1504 FH_MEM_RCSR_CHNL0_CONFIG_REG
,
1505 FH_MEM_RSSR_SHARED_CTRL_REG
,
1506 FH_MEM_RSSR_RX_STATUS_REG
,
1507 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
,
1508 FH_TSSR_TX_STATUS_REG
,
1509 FH_TSSR_TX_ERROR_REG
1511 #ifdef CONFIG_IWLWIFI_DEBUG
1513 bufsz
= ARRAY_SIZE(fh_tbl
) * 48 + 40;
1514 *buf
= kmalloc(bufsz
, GFP_KERNEL
);
1517 pos
+= scnprintf(*buf
+ pos
, bufsz
- pos
,
1518 "FH register values:\n");
1519 for (i
= 0; i
< ARRAY_SIZE(fh_tbl
); i
++) {
1520 pos
+= scnprintf(*buf
+ pos
, bufsz
- pos
,
1522 get_fh_string(fh_tbl
[i
]),
1523 iwl_read_direct32(bus(trans
), fh_tbl
[i
]));
1528 IWL_ERR(trans
, "FH register values:\n");
1529 for (i
= 0; i
< ARRAY_SIZE(fh_tbl
); i
++) {
1530 IWL_ERR(trans
, " %34s: 0X%08x\n",
1531 get_fh_string(fh_tbl
[i
]),
1532 iwl_read_direct32(bus(trans
), fh_tbl
[i
]));
1537 static const char *get_csr_string(int cmd
)
1540 IWL_CMD(CSR_HW_IF_CONFIG_REG
);
1541 IWL_CMD(CSR_INT_COALESCING
);
1543 IWL_CMD(CSR_INT_MASK
);
1544 IWL_CMD(CSR_FH_INT_STATUS
);
1545 IWL_CMD(CSR_GPIO_IN
);
1547 IWL_CMD(CSR_GP_CNTRL
);
1548 IWL_CMD(CSR_HW_REV
);
1549 IWL_CMD(CSR_EEPROM_REG
);
1550 IWL_CMD(CSR_EEPROM_GP
);
1551 IWL_CMD(CSR_OTP_GP_REG
);
1552 IWL_CMD(CSR_GIO_REG
);
1553 IWL_CMD(CSR_GP_UCODE_REG
);
1554 IWL_CMD(CSR_GP_DRIVER_REG
);
1555 IWL_CMD(CSR_UCODE_DRV_GP1
);
1556 IWL_CMD(CSR_UCODE_DRV_GP2
);
1557 IWL_CMD(CSR_LED_REG
);
1558 IWL_CMD(CSR_DRAM_INT_TBL_REG
);
1559 IWL_CMD(CSR_GIO_CHICKEN_BITS
);
1560 IWL_CMD(CSR_ANA_PLL_CFG
);
1561 IWL_CMD(CSR_HW_REV_WA_REG
);
1562 IWL_CMD(CSR_DBG_HPET_MEM_REG
);
1568 void iwl_dump_csr(struct iwl_trans
*trans
)
1571 static const u32 csr_tbl
[] = {
1572 CSR_HW_IF_CONFIG_REG
,
1590 CSR_DRAM_INT_TBL_REG
,
1591 CSR_GIO_CHICKEN_BITS
,
1594 CSR_DBG_HPET_MEM_REG
1596 IWL_ERR(trans
, "CSR values:\n");
1597 IWL_ERR(trans
, "(2nd byte of CSR_INT_COALESCING is "
1598 "CSR_INT_PERIODIC_REG)\n");
1599 for (i
= 0; i
< ARRAY_SIZE(csr_tbl
); i
++) {
1600 IWL_ERR(trans
, " %25s: 0X%08x\n",
1601 get_csr_string(csr_tbl
[i
]),
1602 iwl_read32(bus(trans
), csr_tbl
[i
]));
1606 #ifdef CONFIG_IWLWIFI_DEBUGFS
1607 /* create and remove of files */
1608 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1609 if (!debugfs_create_file(#name, mode, parent, trans, \
1610 &iwl_dbgfs_##name##_ops)) \
1614 /* file operation */
1615 #define DEBUGFS_READ_FUNC(name) \
1616 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1617 char __user *user_buf, \
1618 size_t count, loff_t *ppos);
1620 #define DEBUGFS_WRITE_FUNC(name) \
1621 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1622 const char __user *user_buf, \
1623 size_t count, loff_t *ppos);
1626 static int iwl_dbgfs_open_file_generic(struct inode
*inode
, struct file
*file
)
1628 file
->private_data
= inode
->i_private
;
1632 #define DEBUGFS_READ_FILE_OPS(name) \
1633 DEBUGFS_READ_FUNC(name); \
1634 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1635 .read = iwl_dbgfs_##name##_read, \
1636 .open = iwl_dbgfs_open_file_generic, \
1637 .llseek = generic_file_llseek, \
1640 #define DEBUGFS_WRITE_FILE_OPS(name) \
1641 DEBUGFS_WRITE_FUNC(name); \
1642 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1643 .write = iwl_dbgfs_##name##_write, \
1644 .open = iwl_dbgfs_open_file_generic, \
1645 .llseek = generic_file_llseek, \
1648 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1649 DEBUGFS_READ_FUNC(name); \
1650 DEBUGFS_WRITE_FUNC(name); \
1651 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1652 .write = iwl_dbgfs_##name##_write, \
1653 .read = iwl_dbgfs_##name##_read, \
1654 .open = iwl_dbgfs_open_file_generic, \
1655 .llseek = generic_file_llseek, \
1658 static ssize_t
iwl_dbgfs_tx_queue_read(struct file
*file
,
1659 char __user
*user_buf
,
1660 size_t count
, loff_t
*ppos
)
1662 struct iwl_trans
*trans
= file
->private_data
;
1663 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1664 struct iwl_tx_queue
*txq
;
1665 struct iwl_queue
*q
;
1670 const size_t bufsz
= sizeof(char) * 64 * hw_params(trans
).max_txq_num
;
1672 if (!trans_pcie
->txq
) {
1673 IWL_ERR(trans
, "txq not ready\n");
1676 buf
= kzalloc(bufsz
, GFP_KERNEL
);
1680 for (cnt
= 0; cnt
< hw_params(trans
).max_txq_num
; cnt
++) {
1681 txq
= &trans_pcie
->txq
[cnt
];
1683 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1684 "hwq %.2d: read=%u write=%u stop=%d"
1685 " swq_id=%#.2x (ac %d/hwq %d)\n",
1686 cnt
, q
->read_ptr
, q
->write_ptr
,
1687 !!test_bit(cnt
, trans_pcie
->queue_stopped
),
1688 txq
->swq_id
, txq
->swq_id
& 3,
1689 (txq
->swq_id
>> 2) & 0x1f);
1692 /* for the ACs, display the stop count too */
1693 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1694 " stop-count: %d\n",
1695 atomic_read(&trans_pcie
->queue_stop_count
[cnt
]));
1697 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1702 static ssize_t
iwl_dbgfs_rx_queue_read(struct file
*file
,
1703 char __user
*user_buf
,
1704 size_t count
, loff_t
*ppos
) {
1705 struct iwl_trans
*trans
= file
->private_data
;
1706 struct iwl_trans_pcie
*trans_pcie
=
1707 IWL_TRANS_GET_PCIE_TRANS(trans
);
1708 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
1711 const size_t bufsz
= sizeof(buf
);
1713 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "read: %u\n",
1715 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "write: %u\n",
1717 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "free_count: %u\n",
1720 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "closed_rb_num: %u\n",
1721 le16_to_cpu(rxq
->rb_stts
->closed_rb_num
) & 0x0FFF);
1723 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1724 "closed_rb_num: Not Allocated\n");
1726 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1729 static ssize_t
iwl_dbgfs_log_event_read(struct file
*file
,
1730 char __user
*user_buf
,
1731 size_t count
, loff_t
*ppos
)
1733 struct iwl_trans
*trans
= file
->private_data
;
1736 ssize_t ret
= -ENOMEM
;
1738 ret
= pos
= iwl_dump_nic_event_log(trans
, true, &buf
, true);
1740 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1746 static ssize_t
iwl_dbgfs_log_event_write(struct file
*file
,
1747 const char __user
*user_buf
,
1748 size_t count
, loff_t
*ppos
)
1750 struct iwl_trans
*trans
= file
->private_data
;
1755 memset(buf
, 0, sizeof(buf
));
1756 buf_size
= min(count
, sizeof(buf
) - 1);
1757 if (copy_from_user(buf
, user_buf
, buf_size
))
1759 if (sscanf(buf
, "%d", &event_log_flag
) != 1)
1761 if (event_log_flag
== 1)
1762 iwl_dump_nic_event_log(trans
, true, NULL
, false);
1767 static ssize_t
iwl_dbgfs_interrupt_read(struct file
*file
,
1768 char __user
*user_buf
,
1769 size_t count
, loff_t
*ppos
) {
1771 struct iwl_trans
*trans
= file
->private_data
;
1772 struct iwl_trans_pcie
*trans_pcie
=
1773 IWL_TRANS_GET_PCIE_TRANS(trans
);
1774 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
1778 int bufsz
= 24 * 64; /* 24 items * 64 char per item */
1781 buf
= kzalloc(bufsz
, GFP_KERNEL
);
1783 IWL_ERR(trans
, "Can not allocate Buffer\n");
1787 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1788 "Interrupt Statistics Report:\n");
1790 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "HW Error:\t\t\t %u\n",
1792 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "SW Error:\t\t\t %u\n",
1794 if (isr_stats
->sw
|| isr_stats
->hw
) {
1795 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1796 "\tLast Restarting Code: 0x%X\n",
1797 isr_stats
->err_code
);
1799 #ifdef CONFIG_IWLWIFI_DEBUG
1800 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Frame transmitted:\t\t %u\n",
1802 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Alive interrupt:\t\t %u\n",
1805 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1806 "HW RF KILL switch toggled:\t %u\n", isr_stats
->rfkill
);
1808 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "CT KILL:\t\t\t %u\n",
1811 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Wakeup Interrupt:\t\t %u\n",
1814 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1815 "Rx command responses:\t\t %u\n", isr_stats
->rx
);
1817 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Tx/FH interrupt:\t\t %u\n",
1820 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Unexpected INTA:\t\t %u\n",
1821 isr_stats
->unhandled
);
1823 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1828 static ssize_t
iwl_dbgfs_interrupt_write(struct file
*file
,
1829 const char __user
*user_buf
,
1830 size_t count
, loff_t
*ppos
)
1832 struct iwl_trans
*trans
= file
->private_data
;
1833 struct iwl_trans_pcie
*trans_pcie
=
1834 IWL_TRANS_GET_PCIE_TRANS(trans
);
1835 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
1841 memset(buf
, 0, sizeof(buf
));
1842 buf_size
= min(count
, sizeof(buf
) - 1);
1843 if (copy_from_user(buf
, user_buf
, buf_size
))
1845 if (sscanf(buf
, "%x", &reset_flag
) != 1)
1847 if (reset_flag
== 0)
1848 memset(isr_stats
, 0, sizeof(*isr_stats
));
1853 static ssize_t
iwl_dbgfs_csr_write(struct file
*file
,
1854 const char __user
*user_buf
,
1855 size_t count
, loff_t
*ppos
)
1857 struct iwl_trans
*trans
= file
->private_data
;
1862 memset(buf
, 0, sizeof(buf
));
1863 buf_size
= min(count
, sizeof(buf
) - 1);
1864 if (copy_from_user(buf
, user_buf
, buf_size
))
1866 if (sscanf(buf
, "%d", &csr
) != 1)
1869 iwl_dump_csr(trans
);
1874 static ssize_t
iwl_dbgfs_fh_reg_read(struct file
*file
,
1875 char __user
*user_buf
,
1876 size_t count
, loff_t
*ppos
)
1878 struct iwl_trans
*trans
= file
->private_data
;
1881 ssize_t ret
= -EFAULT
;
1883 ret
= pos
= iwl_dump_fh(trans
, &buf
, true);
1885 ret
= simple_read_from_buffer(user_buf
,
1886 count
, ppos
, buf
, pos
);
1893 DEBUGFS_READ_WRITE_FILE_OPS(log_event
);
1894 DEBUGFS_READ_WRITE_FILE_OPS(interrupt
);
1895 DEBUGFS_READ_FILE_OPS(fh_reg
);
1896 DEBUGFS_READ_FILE_OPS(rx_queue
);
1897 DEBUGFS_READ_FILE_OPS(tx_queue
);
1898 DEBUGFS_WRITE_FILE_OPS(csr
);
1901 * Create the debugfs files and directories
1904 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans
*trans
,
1907 DEBUGFS_ADD_FILE(rx_queue
, dir
, S_IRUSR
);
1908 DEBUGFS_ADD_FILE(tx_queue
, dir
, S_IRUSR
);
1909 DEBUGFS_ADD_FILE(log_event
, dir
, S_IWUSR
| S_IRUSR
);
1910 DEBUGFS_ADD_FILE(interrupt
, dir
, S_IWUSR
| S_IRUSR
);
1911 DEBUGFS_ADD_FILE(csr
, dir
, S_IWUSR
);
1912 DEBUGFS_ADD_FILE(fh_reg
, dir
, S_IRUSR
);
1916 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans
*trans
,
1920 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1922 const struct iwl_trans_ops trans_ops_pcie
= {
1923 .request_irq
= iwl_trans_pcie_request_irq
,
1924 .fw_alive
= iwl_trans_pcie_fw_alive
,
1925 .start_device
= iwl_trans_pcie_start_device
,
1926 .prepare_card_hw
= iwl_trans_pcie_prepare_card_hw
,
1927 .stop_device
= iwl_trans_pcie_stop_device
,
1929 .wake_any_queue
= iwl_trans_pcie_wake_any_queue
,
1931 .send_cmd
= iwl_trans_pcie_send_cmd
,
1933 .tx
= iwl_trans_pcie_tx
,
1934 .reclaim
= iwl_trans_pcie_reclaim
,
1936 .tx_agg_disable
= iwl_trans_pcie_tx_agg_disable
,
1937 .tx_agg_alloc
= iwl_trans_pcie_tx_agg_alloc
,
1938 .tx_agg_setup
= iwl_trans_pcie_tx_agg_setup
,
1940 .kick_nic
= iwl_trans_pcie_kick_nic
,
1942 .free
= iwl_trans_pcie_free
,
1943 .stop_queue
= iwl_trans_pcie_stop_queue
,
1945 .dbgfs_register
= iwl_trans_pcie_dbgfs_register
,
1947 .wait_tx_queue_empty
= iwl_trans_pcie_wait_tx_queue_empty
,
1948 .check_stuck_queue
= iwl_trans_pcie_check_stuck_queue
,
1950 #ifdef CONFIG_PM_SLEEP
1951 .suspend
= iwl_trans_pcie_suspend
,
1952 .resume
= iwl_trans_pcie_resume
,
1954 .write8
= iwl_trans_pcie_write8
,
1955 .write32
= iwl_trans_pcie_write32
,
1956 .read32
= iwl_trans_pcie_read32
,
1960 #define PCI_CFG_RETRY_TIMEOUT 0x041
1962 struct iwl_trans
*iwl_trans_pcie_alloc(struct iwl_shared
*shrd
,
1963 struct pci_dev
*pdev
,
1964 const struct pci_device_id
*ent
)
1966 struct iwl_trans_pcie
*trans_pcie
;
1967 struct iwl_trans
*trans
;
1971 trans
= kzalloc(sizeof(struct iwl_trans
) +
1972 sizeof(struct iwl_trans_pcie
), GFP_KERNEL
);
1974 if (WARN_ON(!trans
))
1977 trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1979 trans
->ops
= &trans_ops_pcie
;
1981 trans_pcie
->trans
= trans
;
1982 spin_lock_init(&trans
->hcmd_lock
);
1984 /* W/A - seems to solve weird behavior. We need to remove this if we
1985 * don't want to stay in L1 all the time. This wastes a lot of power */
1986 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
|
1987 PCIE_LINK_STATE_CLKPM
);
1989 if (pci_enable_device(pdev
)) {
1994 pci_set_master(pdev
);
1996 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(36));
1998 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(36));
2000 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
2002 err
= pci_set_consistent_dma_mask(pdev
,
2004 /* both attempts failed: */
2006 dev_printk(KERN_ERR
, &pdev
->dev
,
2007 "No suitable DMA available.\n");
2008 goto out_pci_disable_device
;
2012 err
= pci_request_regions(pdev
, DRV_NAME
);
2014 dev_printk(KERN_ERR
, &pdev
->dev
, "pci_request_regions failed");
2015 goto out_pci_disable_device
;
2018 trans_pcie
->hw_base
= pci_iomap(pdev
, 0, 0);
2019 if (!trans_pcie
->hw_base
) {
2020 dev_printk(KERN_ERR
, &pdev
->dev
, "pci_iomap failed");
2022 goto out_pci_release_regions
;
2025 dev_printk(KERN_INFO
, &pdev
->dev
,
2026 "pci_resource_len = 0x%08llx\n",
2027 (unsigned long long) pci_resource_len(pdev
, 0));
2028 dev_printk(KERN_INFO
, &pdev
->dev
,
2029 "pci_resource_base = %p\n", trans_pcie
->hw_base
);
2031 dev_printk(KERN_INFO
, &pdev
->dev
,
2032 "HW Revision ID = 0x%X\n", pdev
->revision
);
2034 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2035 * PCI Tx retries from interfering with C3 CPU state */
2036 pci_write_config_byte(pdev
, PCI_CFG_RETRY_TIMEOUT
, 0x00);
2038 err
= pci_enable_msi(pdev
);
2040 dev_printk(KERN_ERR
, &pdev
->dev
,
2041 "pci_enable_msi failed(0X%x)", err
);
2043 trans
->dev
= &pdev
->dev
;
2044 trans
->irq
= pdev
->irq
;
2045 trans_pcie
->pci_dev
= pdev
;
2047 /* TODO: Move this away, not needed if not MSI */
2048 /* enable rfkill interrupt: hw bug w/a */
2049 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
2050 if (pci_cmd
& PCI_COMMAND_INTX_DISABLE
) {
2051 pci_cmd
&= ~PCI_COMMAND_INTX_DISABLE
;
2052 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
2057 out_pci_release_regions
:
2058 pci_release_regions(pdev
);
2059 out_pci_disable_device
:
2060 pci_disable_device(pdev
);