1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *****************************************************************************/
63 #include <linux/pci.h>
64 #include <linux/pci-aspm.h>
65 #include <linux/interrupt.h>
66 #include <linux/debugfs.h>
67 #include <linux/sched.h>
68 #include <linux/bitops.h>
69 #include <linux/gfp.h>
71 #include "iwl-trans.h"
72 #include "iwl-trans-pcie-int.h"
75 #include "iwl-shared.h"
76 #include "iwl-eeprom.h"
77 #include "iwl-agn-hw.h"
80 #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
82 static int iwl_trans_rx_alloc(struct iwl_trans
*trans
)
84 struct iwl_trans_pcie
*trans_pcie
=
85 IWL_TRANS_GET_PCIE_TRANS(trans
);
86 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
87 struct device
*dev
= trans
->dev
;
89 memset(&trans_pcie
->rxq
, 0, sizeof(trans_pcie
->rxq
));
91 spin_lock_init(&rxq
->lock
);
93 if (WARN_ON(rxq
->bd
|| rxq
->rb_stts
))
96 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
97 rxq
->bd
= dma_zalloc_coherent(dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
98 &rxq
->bd_dma
, GFP_KERNEL
);
102 /*Allocate the driver's pointer to receive buffer status */
103 rxq
->rb_stts
= dma_zalloc_coherent(dev
, sizeof(*rxq
->rb_stts
),
104 &rxq
->rb_stts_dma
, GFP_KERNEL
);
111 dma_free_coherent(dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
112 rxq
->bd
, rxq
->bd_dma
);
113 memset(&rxq
->bd_dma
, 0, sizeof(rxq
->bd_dma
));
119 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans
*trans
)
121 struct iwl_trans_pcie
*trans_pcie
=
122 IWL_TRANS_GET_PCIE_TRANS(trans
);
123 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
126 /* Fill the rx_used queue with _all_ of the Rx buffers */
127 for (i
= 0; i
< RX_FREE_BUFFERS
+ RX_QUEUE_SIZE
; i
++) {
128 /* In the reset function, these buffers may have been allocated
129 * to an SKB, so we need to unmap and free potential storage */
130 if (rxq
->pool
[i
].page
!= NULL
) {
131 dma_unmap_page(trans
->dev
, rxq
->pool
[i
].page_dma
,
132 PAGE_SIZE
<< hw_params(trans
).rx_page_order
,
134 __free_pages(rxq
->pool
[i
].page
,
135 hw_params(trans
).rx_page_order
);
136 rxq
->pool
[i
].page
= NULL
;
138 list_add_tail(&rxq
->pool
[i
].list
, &rxq
->rx_used
);
142 static void iwl_trans_rx_hw_init(struct iwl_trans
*trans
,
143 struct iwl_rx_queue
*rxq
)
146 const u32 rfdnlog
= RX_QUEUE_SIZE_LOG
; /* 256 RBDs */
147 u32 rb_timeout
= RX_RB_TIMEOUT
; /* FIXME: RX_RB_TIMEOUT for all devices? */
149 if (iwlagn_mod_params
.amsdu_size_8K
)
150 rb_size
= FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K
;
152 rb_size
= FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K
;
155 iwl_write_direct32(trans
, FH_MEM_RCSR_CHNL0_CONFIG_REG
, 0);
157 /* Reset driver's Rx queue write index */
158 iwl_write_direct32(trans
, FH_RSCSR_CHNL0_RBDCB_WPTR_REG
, 0);
160 /* Tell device where to find RBD circular buffer in DRAM */
161 iwl_write_direct32(trans
, FH_RSCSR_CHNL0_RBDCB_BASE_REG
,
162 (u32
)(rxq
->bd_dma
>> 8));
164 /* Tell device where in DRAM to update its Rx status */
165 iwl_write_direct32(trans
, FH_RSCSR_CHNL0_STTS_WPTR_REG
,
166 rxq
->rb_stts_dma
>> 4);
169 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
170 * the credit mechanism in 5000 HW RX FIFO
171 * Direct rx interrupts to hosts
172 * Rx buffer size 4 or 8k
176 iwl_write_direct32(trans
, FH_MEM_RCSR_CHNL0_CONFIG_REG
,
177 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL
|
178 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY
|
179 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL
|
180 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK
|
182 (rb_timeout
<< FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS
)|
183 (rfdnlog
<< FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS
));
185 /* Set interrupt coalescing timer to default (2048 usecs) */
186 iwl_write8(trans
, CSR_INT_COALESCING
, IWL_HOST_INT_TIMEOUT_DEF
);
189 static int iwl_rx_init(struct iwl_trans
*trans
)
191 struct iwl_trans_pcie
*trans_pcie
=
192 IWL_TRANS_GET_PCIE_TRANS(trans
);
193 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
199 err
= iwl_trans_rx_alloc(trans
);
204 spin_lock_irqsave(&rxq
->lock
, flags
);
205 INIT_LIST_HEAD(&rxq
->rx_free
);
206 INIT_LIST_HEAD(&rxq
->rx_used
);
208 iwl_trans_rxq_free_rx_bufs(trans
);
210 for (i
= 0; i
< RX_QUEUE_SIZE
; i
++)
211 rxq
->queue
[i
] = NULL
;
213 /* Set us so that we have processed and used all buffers, but have
214 * not restocked the Rx queue with fresh buffers */
215 rxq
->read
= rxq
->write
= 0;
216 rxq
->write_actual
= 0;
218 spin_unlock_irqrestore(&rxq
->lock
, flags
);
220 iwlagn_rx_replenish(trans
);
222 iwl_trans_rx_hw_init(trans
, rxq
);
224 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
225 rxq
->need_update
= 1;
226 iwl_rx_queue_update_write_ptr(trans
, rxq
);
227 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
232 static void iwl_trans_pcie_rx_free(struct iwl_trans
*trans
)
234 struct iwl_trans_pcie
*trans_pcie
=
235 IWL_TRANS_GET_PCIE_TRANS(trans
);
236 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
240 /*if rxq->bd is NULL, it means that nothing has been allocated,
243 IWL_DEBUG_INFO(trans
, "Free NULL rx context\n");
247 spin_lock_irqsave(&rxq
->lock
, flags
);
248 iwl_trans_rxq_free_rx_bufs(trans
);
249 spin_unlock_irqrestore(&rxq
->lock
, flags
);
251 dma_free_coherent(trans
->dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
252 rxq
->bd
, rxq
->bd_dma
);
253 memset(&rxq
->bd_dma
, 0, sizeof(rxq
->bd_dma
));
257 dma_free_coherent(trans
->dev
,
258 sizeof(struct iwl_rb_status
),
259 rxq
->rb_stts
, rxq
->rb_stts_dma
);
261 IWL_DEBUG_INFO(trans
, "Free rxq->rb_stts which is NULL\n");
262 memset(&rxq
->rb_stts_dma
, 0, sizeof(rxq
->rb_stts_dma
));
266 static int iwl_trans_rx_stop(struct iwl_trans
*trans
)
270 iwl_write_direct32(trans
, FH_MEM_RCSR_CHNL0_CONFIG_REG
, 0);
271 return iwl_poll_direct_bit(trans
, FH_MEM_RSSR_RX_STATUS_REG
,
272 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE
, 1000);
275 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans
*trans
,
276 struct iwl_dma_ptr
*ptr
, size_t size
)
278 if (WARN_ON(ptr
->addr
))
281 ptr
->addr
= dma_alloc_coherent(trans
->dev
, size
,
282 &ptr
->dma
, GFP_KERNEL
);
289 static inline void iwlagn_free_dma_ptr(struct iwl_trans
*trans
,
290 struct iwl_dma_ptr
*ptr
)
292 if (unlikely(!ptr
->addr
))
295 dma_free_coherent(trans
->dev
, ptr
->size
, ptr
->addr
, ptr
->dma
);
296 memset(ptr
, 0, sizeof(*ptr
));
299 static int iwl_trans_txq_alloc(struct iwl_trans
*trans
,
300 struct iwl_tx_queue
*txq
, int slots_num
,
303 size_t tfd_sz
= sizeof(struct iwl_tfd
) * TFD_QUEUE_SIZE_MAX
;
306 if (WARN_ON(txq
->meta
|| txq
->cmd
|| txq
->skbs
|| txq
->tfds
))
309 txq
->q
.n_window
= slots_num
;
311 txq
->meta
= kcalloc(slots_num
, sizeof(txq
->meta
[0]), GFP_KERNEL
);
312 txq
->cmd
= kcalloc(slots_num
, sizeof(txq
->cmd
[0]), GFP_KERNEL
);
314 if (!txq
->meta
|| !txq
->cmd
)
317 if (txq_id
== trans
->shrd
->cmd_queue
)
318 for (i
= 0; i
< slots_num
; i
++) {
319 txq
->cmd
[i
] = kmalloc(sizeof(struct iwl_device_cmd
),
325 /* Alloc driver data array and TFD circular buffer */
326 /* Driver private data, only for Tx (not command) queues,
327 * not shared with device. */
328 if (txq_id
!= trans
->shrd
->cmd_queue
) {
329 txq
->skbs
= kcalloc(TFD_QUEUE_SIZE_MAX
, sizeof(txq
->skbs
[0]),
332 IWL_ERR(trans
, "kmalloc for auxiliary BD "
333 "structures failed\n");
340 /* Circular buffer of transmit frame descriptors (TFDs),
341 * shared with device */
342 txq
->tfds
= dma_alloc_coherent(trans
->dev
, tfd_sz
,
343 &txq
->q
.dma_addr
, GFP_KERNEL
);
345 IWL_ERR(trans
, "dma_alloc_coherent(%zd) failed\n", tfd_sz
);
354 /* since txq->cmd has been zeroed,
355 * all non allocated cmd[i] will be NULL */
356 if (txq
->cmd
&& txq_id
== trans
->shrd
->cmd_queue
)
357 for (i
= 0; i
< slots_num
; i
++)
368 static int iwl_trans_txq_init(struct iwl_trans
*trans
, struct iwl_tx_queue
*txq
,
369 int slots_num
, u32 txq_id
)
373 txq
->need_update
= 0;
374 memset(txq
->meta
, 0, sizeof(txq
->meta
[0]) * slots_num
);
377 * For the default queues 0-3, set up the swq_id
378 * already -- all others need to get one later
379 * (if they need one at all).
382 iwl_set_swq_id(txq
, txq_id
, txq_id
);
384 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
385 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
386 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX
& (TFD_QUEUE_SIZE_MAX
- 1));
388 /* Initialize queue's high/low-water marks, and head/tail indexes */
389 ret
= iwl_queue_init(&txq
->q
, TFD_QUEUE_SIZE_MAX
, slots_num
,
394 spin_lock_init(&txq
->lock
);
397 * Tell nic where to find circular buffer of Tx Frame Descriptors for
398 * given Tx queue, and enable the DMA channel used for that queue.
399 * Circular buffer (TFD queue in DRAM) physical base address */
400 iwl_write_direct32(trans
, FH_MEM_CBBC_QUEUE(txq_id
),
401 txq
->q
.dma_addr
>> 8);
407 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
409 static void iwl_tx_queue_unmap(struct iwl_trans
*trans
, int txq_id
)
411 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
412 struct iwl_tx_queue
*txq
= &trans_pcie
->txq
[txq_id
];
413 struct iwl_queue
*q
= &txq
->q
;
414 enum dma_data_direction dma_dir
;
419 /* In the command queue, all the TBs are mapped as BIDI
420 * so unmap them as such.
422 if (txq_id
== trans
->shrd
->cmd_queue
)
423 dma_dir
= DMA_BIDIRECTIONAL
;
425 dma_dir
= DMA_TO_DEVICE
;
427 spin_lock_bh(&txq
->lock
);
428 while (q
->write_ptr
!= q
->read_ptr
) {
429 /* The read_ptr needs to bound by q->n_window */
430 iwlagn_txq_free_tfd(trans
, txq
, get_cmd_index(q
, q
->read_ptr
),
432 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
);
434 spin_unlock_bh(&txq
->lock
);
438 * iwl_tx_queue_free - Deallocate DMA queue.
439 * @txq: Transmit queue to deallocate.
441 * Empty queue by removing and destroying all BD's.
443 * 0-fill, but do not free "txq" descriptor structure.
445 static void iwl_tx_queue_free(struct iwl_trans
*trans
, int txq_id
)
447 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
448 struct iwl_tx_queue
*txq
= &trans_pcie
->txq
[txq_id
];
449 struct device
*dev
= trans
->dev
;
454 iwl_tx_queue_unmap(trans
, txq_id
);
456 /* De-alloc array of command/tx buffers */
458 if (txq_id
== trans
->shrd
->cmd_queue
)
459 for (i
= 0; i
< txq
->q
.n_window
; i
++)
462 /* De-alloc circular buffer of TFDs */
464 dma_free_coherent(dev
, sizeof(struct iwl_tfd
) *
465 txq
->q
.n_bd
, txq
->tfds
, txq
->q
.dma_addr
);
466 memset(&txq
->q
.dma_addr
, 0, sizeof(txq
->q
.dma_addr
));
469 /* De-alloc array of per-TFD driver data */
473 /* deallocate arrays */
479 /* 0-fill queue descriptor structure */
480 memset(txq
, 0, sizeof(*txq
));
484 * iwl_trans_tx_free - Free TXQ Context
486 * Destroy all TX DMA queues and structures
488 static void iwl_trans_pcie_tx_free(struct iwl_trans
*trans
)
491 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
494 if (trans_pcie
->txq
) {
496 txq_id
< hw_params(trans
).max_txq_num
; txq_id
++)
497 iwl_tx_queue_free(trans
, txq_id
);
500 kfree(trans_pcie
->txq
);
501 trans_pcie
->txq
= NULL
;
503 iwlagn_free_dma_ptr(trans
, &trans_pcie
->kw
);
505 iwlagn_free_dma_ptr(trans
, &trans_pcie
->scd_bc_tbls
);
509 * iwl_trans_tx_alloc - allocate TX context
510 * Allocate all Tx DMA structures and initialize them
515 static int iwl_trans_tx_alloc(struct iwl_trans
*trans
)
518 int txq_id
, slots_num
;
519 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
521 u16 scd_bc_tbls_size
= hw_params(trans
).max_txq_num
*
522 sizeof(struct iwlagn_scd_bc_tbl
);
524 /*It is not allowed to alloc twice, so warn when this happens.
525 * We cannot rely on the previous allocation, so free and fail */
526 if (WARN_ON(trans_pcie
->txq
)) {
531 ret
= iwlagn_alloc_dma_ptr(trans
, &trans_pcie
->scd_bc_tbls
,
534 IWL_ERR(trans
, "Scheduler BC Table allocation failed\n");
538 /* Alloc keep-warm buffer */
539 ret
= iwlagn_alloc_dma_ptr(trans
, &trans_pcie
->kw
, IWL_KW_SIZE
);
541 IWL_ERR(trans
, "Keep Warm allocation failed\n");
545 trans_pcie
->txq
= kcalloc(hw_params(trans
).max_txq_num
,
546 sizeof(struct iwl_tx_queue
), GFP_KERNEL
);
547 if (!trans_pcie
->txq
) {
548 IWL_ERR(trans
, "Not enough memory for txq\n");
553 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
554 for (txq_id
= 0; txq_id
< hw_params(trans
).max_txq_num
; txq_id
++) {
555 slots_num
= (txq_id
== trans
->shrd
->cmd_queue
) ?
556 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
557 ret
= iwl_trans_txq_alloc(trans
, &trans_pcie
->txq
[txq_id
],
560 IWL_ERR(trans
, "Tx %d queue alloc failed\n", txq_id
);
568 iwl_trans_pcie_tx_free(trans
);
572 static int iwl_tx_init(struct iwl_trans
*trans
)
575 int txq_id
, slots_num
;
578 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
580 if (!trans_pcie
->txq
) {
581 ret
= iwl_trans_tx_alloc(trans
);
587 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
589 /* Turn off all Tx DMA fifos */
590 iwl_write_prph(trans
, SCD_TXFACT
, 0);
592 /* Tell NIC where to find the "keep warm" buffer */
593 iwl_write_direct32(trans
, FH_KW_MEM_ADDR_REG
,
594 trans_pcie
->kw
.dma
>> 4);
596 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
598 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
599 for (txq_id
= 0; txq_id
< hw_params(trans
).max_txq_num
; txq_id
++) {
600 slots_num
= (txq_id
== trans
->shrd
->cmd_queue
) ?
601 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
602 ret
= iwl_trans_txq_init(trans
, &trans_pcie
->txq
[txq_id
],
605 IWL_ERR(trans
, "Tx %d queue init failed\n", txq_id
);
612 /*Upon error, free only if we allocated something */
614 iwl_trans_pcie_tx_free(trans
);
618 static void iwl_set_pwr_vmain(struct iwl_trans
*trans
)
621 * (for documentation purposes)
622 * to set power to V_AUX, do:
624 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
625 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
626 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
627 ~APMG_PS_CTRL_MSK_PWR_SRC);
630 iwl_set_bits_mask_prph(trans
, APMG_PS_CTRL_REG
,
631 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN
,
632 ~APMG_PS_CTRL_MSK_PWR_SRC
);
636 #define PCI_CFG_RETRY_TIMEOUT 0x041
637 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
638 #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
640 static u16
iwl_pciexp_link_ctrl(struct iwl_trans
*trans
)
644 struct iwl_trans_pcie
*trans_pcie
=
645 IWL_TRANS_GET_PCIE_TRANS(trans
);
647 struct pci_dev
*pci_dev
= trans_pcie
->pci_dev
;
649 pos
= pci_pcie_cap(pci_dev
);
650 pci_read_config_word(pci_dev
, pos
+ PCI_EXP_LNKCTL
, &pci_lnk_ctl
);
654 static void iwl_apm_config(struct iwl_trans
*trans
)
657 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
658 * Check if BIOS (or OS) enabled L1-ASPM on this device.
659 * If so (likely), disable L0S, so device moves directly L0->L1;
660 * costs negligible amount of power savings.
661 * If not (unlikely), enable L0S, so there is at least some
662 * power savings, even without L1.
664 u16 lctl
= iwl_pciexp_link_ctrl(trans
);
666 if ((lctl
& PCI_CFG_LINK_CTRL_VAL_L1_EN
) ==
667 PCI_CFG_LINK_CTRL_VAL_L1_EN
) {
668 /* L1-ASPM enabled; disable(!) L0S */
669 iwl_set_bit(trans
, CSR_GIO_REG
, CSR_GIO_REG_VAL_L0S_ENABLED
);
670 dev_printk(KERN_INFO
, trans
->dev
,
671 "L1 Enabled; Disabling L0S\n");
673 /* L1-ASPM disabled; enable(!) L0S */
674 iwl_clear_bit(trans
, CSR_GIO_REG
, CSR_GIO_REG_VAL_L0S_ENABLED
);
675 dev_printk(KERN_INFO
, trans
->dev
,
676 "L1 Disabled; Enabling L0S\n");
678 trans
->pm_support
= !(lctl
& PCI_CFG_LINK_CTRL_VAL_L0S_EN
);
682 * Start up NIC's basic functionality after it has been reset
683 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
684 * NOTE: This does not load uCode nor start the embedded processor
686 static int iwl_apm_init(struct iwl_trans
*trans
)
689 IWL_DEBUG_INFO(trans
, "Init card's basic functions\n");
692 * Use "set_bit" below rather than "write", to preserve any hardware
693 * bits already set by default after reset.
696 /* Disable L0S exit timer (platform NMI Work/Around) */
697 iwl_set_bit(trans
, CSR_GIO_CHICKEN_BITS
,
698 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER
);
701 * Disable L0s without affecting L1;
702 * don't wait for ICH L0s (ICH bug W/A)
704 iwl_set_bit(trans
, CSR_GIO_CHICKEN_BITS
,
705 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX
);
707 /* Set FH wait threshold to maximum (HW error during stress W/A) */
708 iwl_set_bit(trans
, CSR_DBG_HPET_MEM_REG
, CSR_DBG_HPET_MEM_REG_VAL
);
711 * Enable HAP INTA (interrupt from management bus) to
712 * wake device's PCI Express link L1a -> L0s
714 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
715 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A
);
717 iwl_apm_config(trans
);
719 /* Configure analog phase-lock-loop before activating to D0A */
720 if (cfg(trans
)->base_params
->pll_cfg_val
)
721 iwl_set_bit(trans
, CSR_ANA_PLL_CFG
,
722 cfg(trans
)->base_params
->pll_cfg_val
);
725 * Set "initialization complete" bit to move adapter from
726 * D0U* --> D0A* (powered-up active) state.
728 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
731 * Wait for clock stabilization; once stabilized, access to
732 * device-internal resources is supported, e.g. iwl_write_prph()
733 * and accesses to uCode SRAM.
735 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
736 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
737 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
, 25000);
739 IWL_DEBUG_INFO(trans
, "Failed to init the card\n");
744 * Enable DMA clock and wait for it to stabilize.
746 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
747 * do not disable clocks. This preserves any hardware bits already
748 * set by default in "CLK_CTRL_REG" after reset.
750 iwl_write_prph(trans
, APMG_CLK_EN_REG
, APMG_CLK_VAL_DMA_CLK_RQT
);
753 /* Disable L1-Active */
754 iwl_set_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
755 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
757 set_bit(STATUS_DEVICE_ENABLED
, &trans
->shrd
->status
);
763 static int iwl_apm_stop_master(struct iwl_trans
*trans
)
767 /* stop device's busmaster DMA activity */
768 iwl_set_bit(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_STOP_MASTER
);
770 ret
= iwl_poll_bit(trans
, CSR_RESET
,
771 CSR_RESET_REG_FLAG_MASTER_DISABLED
,
772 CSR_RESET_REG_FLAG_MASTER_DISABLED
, 100);
774 IWL_WARN(trans
, "Master Disable Timed Out, 100 usec\n");
776 IWL_DEBUG_INFO(trans
, "stop master\n");
781 static void iwl_apm_stop(struct iwl_trans
*trans
)
783 IWL_DEBUG_INFO(trans
, "Stop card, put in low power state\n");
785 clear_bit(STATUS_DEVICE_ENABLED
, &trans
->shrd
->status
);
787 /* Stop device's DMA activity */
788 iwl_apm_stop_master(trans
);
790 /* Reset the entire device */
791 iwl_set_bit(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
796 * Clear "initialization complete" bit to move adapter from
797 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
799 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
800 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
803 static int iwl_nic_init(struct iwl_trans
*trans
)
805 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
809 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
812 /* Set interrupt coalescing calibration timer to default (512 usecs) */
813 iwl_write8(trans
, CSR_INT_COALESCING
,
814 IWL_HOST_INT_CALIB_TIMEOUT_DEF
);
816 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
818 iwl_set_pwr_vmain(trans
);
820 iwl_nic_config(priv(trans
));
822 #ifndef CONFIG_IWLWIFI_IDI
823 /* Allocate the RX queue, or reset if it is already allocated */
827 /* Allocate or reset and init all Tx and Command queues */
828 if (iwl_tx_init(trans
))
831 if (cfg(trans
)->base_params
->shadow_reg_enable
) {
832 /* enable shadow regs in HW */
833 iwl_set_bit(trans
, CSR_MAC_SHADOW_REG_CTRL
,
837 set_bit(STATUS_INIT
, &trans
->shrd
->status
);
842 #define HW_READY_TIMEOUT (50)
844 /* Note: returns poll_bit return value, which is >= 0 if success */
845 static int iwl_set_hw_ready(struct iwl_trans
*trans
)
849 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
850 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
);
852 /* See if we got it */
853 ret
= iwl_poll_bit(trans
, CSR_HW_IF_CONFIG_REG
,
854 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
855 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
858 IWL_DEBUG_INFO(trans
, "hardware%s ready\n", ret
< 0 ? " not" : "");
862 /* Note: returns standard 0/-ERROR code */
863 static int iwl_prepare_card_hw(struct iwl_trans
*trans
)
867 IWL_DEBUG_INFO(trans
, "iwl_trans_prepare_card_hw enter\n");
869 ret
= iwl_set_hw_ready(trans
);
870 /* If the card is ready, exit 0 */
874 /* If HW is not ready, prepare the conditions to check again */
875 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
876 CSR_HW_IF_CONFIG_REG_PREPARE
);
878 ret
= iwl_poll_bit(trans
, CSR_HW_IF_CONFIG_REG
,
879 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE
,
880 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE
, 150000);
885 /* HW should be ready by now, check again. */
886 ret
= iwl_set_hw_ready(trans
);
892 #define IWL_AC_UNSET -1
894 struct queue_to_fifo_ac
{
898 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo
[] = {
899 { IWL_TX_FIFO_VO
, IEEE80211_AC_VO
, },
900 { IWL_TX_FIFO_VI
, IEEE80211_AC_VI
, },
901 { IWL_TX_FIFO_BE
, IEEE80211_AC_BE
, },
902 { IWL_TX_FIFO_BK
, IEEE80211_AC_BK
, },
903 { IWLAGN_CMD_FIFO_NUM
, IWL_AC_UNSET
, },
904 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
905 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
906 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
907 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
908 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
909 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
912 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo
[] = {
913 { IWL_TX_FIFO_VO
, IEEE80211_AC_VO
, },
914 { IWL_TX_FIFO_VI
, IEEE80211_AC_VI
, },
915 { IWL_TX_FIFO_BE
, IEEE80211_AC_BE
, },
916 { IWL_TX_FIFO_BK
, IEEE80211_AC_BK
, },
917 { IWL_TX_FIFO_BK_IPAN
, IEEE80211_AC_BK
, },
918 { IWL_TX_FIFO_BE_IPAN
, IEEE80211_AC_BE
, },
919 { IWL_TX_FIFO_VI_IPAN
, IEEE80211_AC_VI
, },
920 { IWL_TX_FIFO_VO_IPAN
, IEEE80211_AC_VO
, },
921 { IWL_TX_FIFO_BE_IPAN
, 2, },
922 { IWLAGN_CMD_FIFO_NUM
, IWL_AC_UNSET
, },
923 { IWL_TX_FIFO_AUX
, IWL_AC_UNSET
, },
926 static const u8 iwlagn_bss_ac_to_fifo
[] = {
932 static const u8 iwlagn_bss_ac_to_queue
[] = {
935 static const u8 iwlagn_pan_ac_to_fifo
[] = {
941 static const u8 iwlagn_pan_ac_to_queue
[] = {
948 static int iwl_load_section(struct iwl_trans
*trans
, const char *name
,
949 const struct fw_desc
*image
, u32 dst_addr
)
951 dma_addr_t phy_addr
= image
->p_addr
;
952 u32 byte_cnt
= image
->len
;
955 trans
->ucode_write_complete
= 0;
957 iwl_write_direct32(trans
,
958 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
959 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE
);
961 iwl_write_direct32(trans
,
962 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL
), dst_addr
);
964 iwl_write_direct32(trans
,
965 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL
),
966 phy_addr
& FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK
);
968 iwl_write_direct32(trans
,
969 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL
),
970 (iwl_get_dma_hi_addr(phy_addr
)
971 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT
) | byte_cnt
);
973 iwl_write_direct32(trans
,
974 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL
),
975 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM
|
976 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX
|
977 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID
);
979 iwl_write_direct32(trans
,
980 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
981 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
982 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE
|
983 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD
);
985 IWL_DEBUG_FW(trans
, "%s uCode section being loaded...\n", name
);
986 ret
= wait_event_timeout(trans
->shrd
->wait_command_queue
,
987 trans
->ucode_write_complete
, 5 * HZ
);
989 IWL_ERR(trans
, "Could not load the %s uCode section\n",
997 static int iwl_load_given_ucode(struct iwl_trans
*trans
,
998 const struct fw_img
*image
)
1002 ret
= iwl_load_section(trans
, "INST", &image
->code
,
1003 IWLAGN_RTC_INST_LOWER_BOUND
);
1007 ret
= iwl_load_section(trans
, "DATA", &image
->data
,
1008 IWLAGN_RTC_DATA_LOWER_BOUND
);
1012 /* Remove all resets to allow NIC to operate */
1013 iwl_write32(trans
, CSR_RESET
, 0);
1018 static int iwl_trans_pcie_start_fw(struct iwl_trans
*trans
,
1019 const struct fw_img
*fw
)
1022 struct iwl_trans_pcie
*trans_pcie
=
1023 IWL_TRANS_GET_PCIE_TRANS(trans
);
1026 trans
->shrd
->ucode_owner
= IWL_OWNERSHIP_DRIVER
;
1027 trans_pcie
->ac_to_queue
[IWL_RXON_CTX_BSS
] = iwlagn_bss_ac_to_queue
;
1028 trans_pcie
->ac_to_queue
[IWL_RXON_CTX_PAN
] = iwlagn_pan_ac_to_queue
;
1030 trans_pcie
->ac_to_fifo
[IWL_RXON_CTX_BSS
] = iwlagn_bss_ac_to_fifo
;
1031 trans_pcie
->ac_to_fifo
[IWL_RXON_CTX_PAN
] = iwlagn_pan_ac_to_fifo
;
1033 trans_pcie
->mcast_queue
[IWL_RXON_CTX_BSS
] = 0;
1034 trans_pcie
->mcast_queue
[IWL_RXON_CTX_PAN
] = IWL_IPAN_MCAST_QUEUE
;
1036 /* This may fail if AMT took ownership of the device */
1037 if (iwl_prepare_card_hw(trans
)) {
1038 IWL_WARN(trans
, "Exit HW not ready\n");
1042 /* If platform's RF_KILL switch is NOT set to KILL */
1043 hw_rfkill
= !(iwl_read32(trans
, CSR_GP_CNTRL
) &
1044 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW
);
1045 iwl_op_mode_hw_rf_kill(trans
->op_mode
, hw_rfkill
);
1048 iwl_enable_interrupts(trans
);
1052 iwl_write32(trans
, CSR_INT
, 0xFFFFFFFF);
1054 ret
= iwl_nic_init(trans
);
1056 IWL_ERR(trans
, "Unable to init nic\n");
1060 /* make sure rfkill handshake bits are cleared */
1061 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
1062 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
,
1063 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED
);
1065 /* clear (again), then enable host interrupts */
1066 iwl_write32(trans
, CSR_INT
, 0xFFFFFFFF);
1067 iwl_enable_interrupts(trans
);
1069 /* really make sure rfkill handshake bits are cleared */
1070 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
1071 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
1073 /* Load the given image to the HW */
1074 iwl_load_given_ucode(trans
, fw
);
1080 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1081 * must be called under the irq lock and with MAC access
1083 static void iwl_trans_txq_set_sched(struct iwl_trans
*trans
, u32 mask
)
1085 struct iwl_trans_pcie __maybe_unused
*trans_pcie
=
1086 IWL_TRANS_GET_PCIE_TRANS(trans
);
1088 lockdep_assert_held(&trans_pcie
->irq_lock
);
1090 iwl_write_prph(trans
, SCD_TXFACT
, mask
);
1093 static void iwl_tx_start(struct iwl_trans
*trans
)
1095 const struct queue_to_fifo_ac
*queue_to_fifo
;
1096 struct iwl_trans_pcie
*trans_pcie
=
1097 IWL_TRANS_GET_PCIE_TRANS(trans
);
1099 unsigned long flags
;
1103 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
1105 trans_pcie
->scd_base_addr
=
1106 iwl_read_prph(trans
, SCD_SRAM_BASE_ADDR
);
1107 a
= trans_pcie
->scd_base_addr
+ SCD_CONTEXT_MEM_LOWER_BOUND
;
1108 /* reset conext data memory */
1109 for (; a
< trans_pcie
->scd_base_addr
+ SCD_CONTEXT_MEM_UPPER_BOUND
;
1111 iwl_write_targ_mem(trans
, a
, 0);
1112 /* reset tx status memory */
1113 for (; a
< trans_pcie
->scd_base_addr
+ SCD_TX_STTS_MEM_UPPER_BOUND
;
1115 iwl_write_targ_mem(trans
, a
, 0);
1116 for (; a
< trans_pcie
->scd_base_addr
+
1117 SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans
).max_txq_num
);
1119 iwl_write_targ_mem(trans
, a
, 0);
1121 iwl_write_prph(trans
, SCD_DRAM_BASE_ADDR
,
1122 trans_pcie
->scd_bc_tbls
.dma
>> 10);
1124 /* Enable DMA channel */
1125 for (chan
= 0; chan
< FH_TCSR_CHNL_NUM
; chan
++)
1126 iwl_write_direct32(trans
, FH_TCSR_CHNL_TX_CONFIG_REG(chan
),
1127 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
1128 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE
);
1130 /* Update FH chicken bits */
1131 reg_val
= iwl_read_direct32(trans
, FH_TX_CHICKEN_BITS_REG
);
1132 iwl_write_direct32(trans
, FH_TX_CHICKEN_BITS_REG
,
1133 reg_val
| FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN
);
1135 iwl_write_prph(trans
, SCD_QUEUECHAIN_SEL
,
1136 SCD_QUEUECHAIN_SEL_ALL(trans
));
1137 iwl_write_prph(trans
, SCD_AGGR_SEL
, 0);
1139 /* initiate the queues */
1140 for (i
= 0; i
< hw_params(trans
).max_txq_num
; i
++) {
1141 iwl_write_prph(trans
, SCD_QUEUE_RDPTR(i
), 0);
1142 iwl_write_direct32(trans
, HBUS_TARG_WRPTR
, 0 | (i
<< 8));
1143 iwl_write_targ_mem(trans
, trans_pcie
->scd_base_addr
+
1144 SCD_CONTEXT_QUEUE_OFFSET(i
), 0);
1145 iwl_write_targ_mem(trans
, trans_pcie
->scd_base_addr
+
1146 SCD_CONTEXT_QUEUE_OFFSET(i
) +
1149 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS
) &
1150 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK
) |
1151 ((SCD_FRAME_LIMIT
<<
1152 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS
) &
1153 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK
));
1156 iwl_write_prph(trans
, SCD_INTERRUPT_MASK
,
1157 IWL_MASK(0, hw_params(trans
).max_txq_num
));
1159 /* Activate all Tx DMA/FIFO channels */
1160 iwl_trans_txq_set_sched(trans
, IWL_MASK(0, 7));
1162 /* map queues to FIFOs */
1163 if (trans
->shrd
->valid_contexts
!= BIT(IWL_RXON_CTX_BSS
))
1164 queue_to_fifo
= iwlagn_ipan_queue_to_tx_fifo
;
1166 queue_to_fifo
= iwlagn_default_queue_to_tx_fifo
;
1168 iwl_trans_set_wr_ptrs(trans
, trans
->shrd
->cmd_queue
, 0);
1170 /* make sure all queue are not stopped */
1171 memset(&trans_pcie
->queue_stopped
[0], 0,
1172 sizeof(trans_pcie
->queue_stopped
));
1173 for (i
= 0; i
< 4; i
++)
1174 atomic_set(&trans_pcie
->queue_stop_count
[i
], 0);
1176 /* reset to 0 to enable all the queue first */
1177 trans_pcie
->txq_ctx_active_msk
= 0;
1179 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo
) <
1180 IWLAGN_FIRST_AMPDU_QUEUE
);
1181 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo
) <
1182 IWLAGN_FIRST_AMPDU_QUEUE
);
1184 for (i
= 0; i
< IWLAGN_FIRST_AMPDU_QUEUE
; i
++) {
1185 int fifo
= queue_to_fifo
[i
].fifo
;
1186 int ac
= queue_to_fifo
[i
].ac
;
1188 iwl_txq_ctx_activate(trans_pcie
, i
);
1190 if (fifo
== IWL_TX_FIFO_UNUSED
)
1193 if (ac
!= IWL_AC_UNSET
)
1194 iwl_set_swq_id(&trans_pcie
->txq
[i
], ac
, i
);
1195 iwl_trans_tx_queue_set_status(trans
, &trans_pcie
->txq
[i
],
1199 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
1201 /* Enable L1-Active */
1202 iwl_clear_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
1203 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
1206 static void iwl_trans_pcie_fw_alive(struct iwl_trans
*trans
)
1208 iwl_reset_ict(trans
);
1209 iwl_tx_start(trans
);
1213 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1215 static int iwl_trans_tx_stop(struct iwl_trans
*trans
)
1218 unsigned long flags
;
1219 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1221 /* Turn off all Tx DMA fifos */
1222 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
1224 iwl_trans_txq_set_sched(trans
, 0);
1226 /* Stop each Tx DMA channel, and wait for it to be idle */
1227 for (ch
= 0; ch
< FH_TCSR_CHNL_NUM
; ch
++) {
1228 iwl_write_direct32(trans
,
1229 FH_TCSR_CHNL_TX_CONFIG_REG(ch
), 0x0);
1230 if (iwl_poll_direct_bit(trans
, FH_TSSR_TX_STATUS_REG
,
1231 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch
),
1233 IWL_ERR(trans
, "Failing on timeout while stopping"
1234 " DMA channel %d [0x%08x]", ch
,
1235 iwl_read_direct32(trans
,
1236 FH_TSSR_TX_STATUS_REG
));
1238 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
1240 if (!trans_pcie
->txq
) {
1241 IWL_WARN(trans
, "Stopping tx queues that aren't allocated...");
1245 /* Unmap DMA from host system and free skb's */
1246 for (txq_id
= 0; txq_id
< hw_params(trans
).max_txq_num
; txq_id
++)
1247 iwl_tx_queue_unmap(trans
, txq_id
);
1252 static void iwl_trans_pcie_stop_device(struct iwl_trans
*trans
)
1254 unsigned long flags
;
1255 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1257 /* tell the device to stop sending interrupts */
1258 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
1259 iwl_disable_interrupts(trans
);
1260 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
1262 /* device going down, Stop using ICT table */
1263 iwl_disable_ict(trans
);
1266 * If a HW restart happens during firmware loading,
1267 * then the firmware loading might call this function
1268 * and later it might be called again due to the
1269 * restart. So don't process again if the device is
1272 if (test_bit(STATUS_DEVICE_ENABLED
, &trans
->shrd
->status
)) {
1273 iwl_trans_tx_stop(trans
);
1274 #ifndef CONFIG_IWLWIFI_IDI
1275 iwl_trans_rx_stop(trans
);
1277 /* Power-down device's busmaster DMA clocks */
1278 iwl_write_prph(trans
, APMG_CLK_DIS_REG
,
1279 APMG_CLK_VAL_DMA_CLK_RQT
);
1283 /* Make sure (redundant) we've released our request to stay awake */
1284 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
1285 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1287 /* Stop the device, and put it in low power state */
1288 iwl_apm_stop(trans
);
1290 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1291 * Clean again the interrupt here
1293 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
1294 iwl_disable_interrupts(trans
);
1295 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
1297 /* wait to make sure we flush pending tasklet*/
1298 synchronize_irq(trans
->irq
);
1299 tasklet_kill(&trans_pcie
->irq_tasklet
);
1301 cancel_work_sync(&trans_pcie
->rx_replenish
);
1303 /* stop and reset the on-board processor */
1304 iwl_write32(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_NEVO_RESET
);
1307 static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans
*trans
)
1309 /* let the ucode operate on its own */
1310 iwl_write32(trans
, CSR_UCODE_DRV_GP1_SET
,
1311 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE
);
1313 iwl_disable_interrupts(trans
);
1314 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
1315 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1318 static int iwl_trans_pcie_tx(struct iwl_trans
*trans
, struct sk_buff
*skb
,
1319 struct iwl_device_cmd
*dev_cmd
, enum iwl_rxon_context_id ctx
,
1322 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1323 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1324 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1325 struct iwl_tx_cmd
*tx_cmd
= (struct iwl_tx_cmd
*) dev_cmd
->payload
;
1326 struct iwl_cmd_meta
*out_meta
;
1327 struct iwl_tx_queue
*txq
;
1328 struct iwl_queue
*q
;
1330 dma_addr_t phys_addr
= 0;
1331 dma_addr_t txcmd_phys
;
1332 dma_addr_t scratch_phys
;
1333 u16 len
, firstlen
, secondlen
;
1334 u8 wait_write_ptr
= 0;
1336 bool is_agg
= false;
1337 __le16 fc
= hdr
->frame_control
;
1338 u8 hdr_len
= ieee80211_hdrlen(fc
);
1339 u16 __maybe_unused wifi_seq
;
1342 * Send this frame after DTIM -- there's a special queue
1343 * reserved for this for contexts that support AP mode.
1345 if (info
->flags
& IEEE80211_TX_CTL_SEND_AFTER_DTIM
) {
1346 txq_id
= trans_pcie
->mcast_queue
[ctx
];
1349 * The microcode will clear the more data
1350 * bit in the last frame it transmits.
1352 hdr
->frame_control
|=
1353 cpu_to_le16(IEEE80211_FCTL_MOREDATA
);
1354 } else if (info
->flags
& IEEE80211_TX_CTL_TX_OFFCHAN
)
1355 txq_id
= IWL_AUX_QUEUE
;
1358 trans_pcie
->ac_to_queue
[ctx
][skb_get_queue_mapping(skb
)];
1360 /* aggregation is on for this <sta,tid> */
1361 if (info
->flags
& IEEE80211_TX_CTL_AMPDU
) {
1362 WARN_ON(tid
>= IWL_MAX_TID_COUNT
);
1363 txq_id
= trans_pcie
->agg_txq
[sta_id
][tid
];
1367 txq
= &trans_pcie
->txq
[txq_id
];
1370 spin_lock(&txq
->lock
);
1372 /* In AGG mode, the index in the ring must correspond to the WiFi
1373 * sequence number. This is a HW requirements to help the SCD to parse
1375 * Check here that the packets are in the right place on the ring.
1377 #ifdef CONFIG_IWLWIFI_DEBUG
1378 wifi_seq
= SEQ_TO_SN(le16_to_cpu(hdr
->seq_ctrl
));
1379 WARN_ONCE(is_agg
&& ((wifi_seq
& 0xff) != q
->write_ptr
),
1380 "Q: %d WiFi Seq %d tfdNum %d",
1381 txq_id
, wifi_seq
, q
->write_ptr
);
1384 /* Set up driver data for this TFD */
1385 txq
->skbs
[q
->write_ptr
] = skb
;
1386 txq
->cmd
[q
->write_ptr
] = dev_cmd
;
1388 dev_cmd
->hdr
.cmd
= REPLY_TX
;
1389 dev_cmd
->hdr
.sequence
= cpu_to_le16((u16
)(QUEUE_TO_SEQ(txq_id
) |
1390 INDEX_TO_SEQ(q
->write_ptr
)));
1392 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1393 out_meta
= &txq
->meta
[q
->write_ptr
];
1396 * Use the first empty entry in this queue's command buffer array
1397 * to contain the Tx command and MAC header concatenated together
1398 * (payload data will be in another buffer).
1399 * Size of this varies, due to varying MAC header length.
1400 * If end is not dword aligned, we'll have 2 extra bytes at the end
1401 * of the MAC header (device reads on dword boundaries).
1402 * We'll tell device about this padding later.
1404 len
= sizeof(struct iwl_tx_cmd
) +
1405 sizeof(struct iwl_cmd_header
) + hdr_len
;
1406 firstlen
= (len
+ 3) & ~3;
1408 /* Tell NIC about any 2-byte padding after MAC header */
1409 if (firstlen
!= len
)
1410 tx_cmd
->tx_flags
|= TX_CMD_FLG_MH_PAD_MSK
;
1412 /* Physical address of this Tx command's header (not MAC header!),
1413 * within command buffer array. */
1414 txcmd_phys
= dma_map_single(trans
->dev
,
1415 &dev_cmd
->hdr
, firstlen
,
1417 if (unlikely(dma_mapping_error(trans
->dev
, txcmd_phys
)))
1419 dma_unmap_addr_set(out_meta
, mapping
, txcmd_phys
);
1420 dma_unmap_len_set(out_meta
, len
, firstlen
);
1422 if (!ieee80211_has_morefrags(fc
)) {
1423 txq
->need_update
= 1;
1426 txq
->need_update
= 0;
1429 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1430 * if any (802.11 null frames have no payload). */
1431 secondlen
= skb
->len
- hdr_len
;
1432 if (secondlen
> 0) {
1433 phys_addr
= dma_map_single(trans
->dev
, skb
->data
+ hdr_len
,
1434 secondlen
, DMA_TO_DEVICE
);
1435 if (unlikely(dma_mapping_error(trans
->dev
, phys_addr
))) {
1436 dma_unmap_single(trans
->dev
,
1437 dma_unmap_addr(out_meta
, mapping
),
1438 dma_unmap_len(out_meta
, len
),
1444 /* Attach buffers to TFD */
1445 iwlagn_txq_attach_buf_to_tfd(trans
, txq
, txcmd_phys
, firstlen
, 1);
1447 iwlagn_txq_attach_buf_to_tfd(trans
, txq
, phys_addr
,
1450 scratch_phys
= txcmd_phys
+ sizeof(struct iwl_cmd_header
) +
1451 offsetof(struct iwl_tx_cmd
, scratch
);
1453 /* take back ownership of DMA buffer to enable update */
1454 dma_sync_single_for_cpu(trans
->dev
, txcmd_phys
, firstlen
,
1456 tx_cmd
->dram_lsb_ptr
= cpu_to_le32(scratch_phys
);
1457 tx_cmd
->dram_msb_ptr
= iwl_get_dma_hi_addr(scratch_phys
);
1459 IWL_DEBUG_TX(trans
, "sequence nr = 0X%x\n",
1460 le16_to_cpu(dev_cmd
->hdr
.sequence
));
1461 IWL_DEBUG_TX(trans
, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd
->tx_flags
));
1462 iwl_print_hex_dump(trans
, IWL_DL_TX
, (u8
*)tx_cmd
, sizeof(*tx_cmd
));
1463 iwl_print_hex_dump(trans
, IWL_DL_TX
, (u8
*)tx_cmd
->hdr
, hdr_len
);
1465 /* Set up entry for this TFD in Tx byte-count array */
1466 iwl_trans_txq_update_byte_cnt_tbl(trans
, txq
, le16_to_cpu(tx_cmd
->len
));
1468 dma_sync_single_for_device(trans
->dev
, txcmd_phys
, firstlen
,
1471 trace_iwlwifi_dev_tx(priv(trans
),
1472 &((struct iwl_tfd
*)txq
->tfds
)[txq
->q
.write_ptr
],
1473 sizeof(struct iwl_tfd
),
1474 &dev_cmd
->hdr
, firstlen
,
1475 skb
->data
+ hdr_len
, secondlen
);
1477 /* Tell device the write index *just past* this latest filled TFD */
1478 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
1479 iwl_txq_update_write_ptr(trans
, txq
);
1482 * At this point the frame is "transmitted" successfully
1483 * and we will get a TX status notification eventually,
1484 * regardless of the value of ret. "ret" only indicates
1485 * whether or not we should update the write pointer.
1487 if (iwl_queue_space(q
) < q
->high_mark
) {
1488 if (wait_write_ptr
) {
1489 txq
->need_update
= 1;
1490 iwl_txq_update_write_ptr(trans
, txq
);
1492 iwl_stop_queue(trans
, txq
, "Queue is full");
1495 spin_unlock(&txq
->lock
);
1498 spin_unlock(&txq
->lock
);
1502 static int iwl_trans_pcie_start_hw(struct iwl_trans
*trans
)
1504 struct iwl_trans_pcie
*trans_pcie
=
1505 IWL_TRANS_GET_PCIE_TRANS(trans
);
1509 trans_pcie
->inta_mask
= CSR_INI_SET_MASK
;
1511 if (!trans_pcie
->irq_requested
) {
1512 tasklet_init(&trans_pcie
->irq_tasklet
, (void (*)(unsigned long))
1513 iwl_irq_tasklet
, (unsigned long)trans
);
1515 iwl_alloc_isr_ict(trans
);
1517 err
= request_irq(trans
->irq
, iwl_isr_ict
, IRQF_SHARED
,
1520 IWL_ERR(trans
, "Error allocating IRQ %d\n",
1525 INIT_WORK(&trans_pcie
->rx_replenish
, iwl_bg_rx_replenish
);
1526 trans_pcie
->irq_requested
= true;
1529 err
= iwl_prepare_card_hw(trans
);
1531 IWL_ERR(trans
, "Error while preparing HW: %d", err
);
1535 iwl_apm_init(trans
);
1537 hw_rfkill
= !(iwl_read32(trans
, CSR_GP_CNTRL
) &
1538 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW
);
1539 iwl_op_mode_hw_rf_kill(trans
->op_mode
, hw_rfkill
);
1544 free_irq(trans
->irq
, trans
);
1546 iwl_free_isr_ict(trans
);
1547 tasklet_kill(&trans_pcie
->irq_tasklet
);
1551 static void iwl_trans_pcie_stop_hw(struct iwl_trans
*trans
)
1553 iwl_apm_stop(trans
);
1555 iwl_write32(trans
, CSR_INT
, 0xFFFFFFFF);
1557 /* Even if we stop the HW, we still want the RF kill interrupt */
1558 IWL_DEBUG_ISR(trans
, "Enabling rfkill interrupt\n");
1559 iwl_write32(trans
, CSR_INT_MASK
, CSR_INT_BIT_RF_KILL
);
1562 static int iwl_trans_pcie_reclaim(struct iwl_trans
*trans
, int sta_id
, int tid
,
1563 int txq_id
, int ssn
, u32 status
,
1564 struct sk_buff_head
*skbs
)
1566 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1567 struct iwl_tx_queue
*txq
= &trans_pcie
->txq
[txq_id
];
1568 /* n_bd is usually 256 => n_bd - 1 = 0xff */
1569 int tfd_num
= ssn
& (txq
->q
.n_bd
- 1);
1572 spin_lock(&txq
->lock
);
1574 txq
->time_stamp
= jiffies
;
1576 if (unlikely(txq_id
>= IWLAGN_FIRST_AMPDU_QUEUE
&&
1577 tid
!= IWL_TID_NON_QOS
&&
1578 txq_id
!= trans_pcie
->agg_txq
[sta_id
][tid
])) {
1580 * FIXME: this is a uCode bug which need to be addressed,
1581 * log the information and return for now.
1582 * Since it is can possibly happen very often and in order
1583 * not to fill the syslog, don't use IWL_ERR or IWL_WARN
1585 IWL_DEBUG_TX_QUEUES(trans
, "Bad queue mapping txq_id %d, "
1586 "agg_txq[sta_id[tid] %d", txq_id
,
1587 trans_pcie
->agg_txq
[sta_id
][tid
]);
1588 spin_unlock(&txq
->lock
);
1592 if (txq
->q
.read_ptr
!= tfd_num
) {
1593 IWL_DEBUG_TX_REPLY(trans
, "[Q %d | AC %d] %d -> %d (%d)\n",
1594 txq_id
, iwl_get_queue_ac(txq
), txq
->q
.read_ptr
,
1596 freed
= iwl_tx_queue_reclaim(trans
, txq_id
, tfd_num
, skbs
);
1597 if (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
&&
1598 (!txq
->sched_retry
||
1599 status
!= TX_STATUS_FAIL_PASSIVE_NO_RX
))
1600 iwl_wake_queue(trans
, txq
, "Packets reclaimed");
1603 spin_unlock(&txq
->lock
);
1607 static void iwl_trans_pcie_write8(struct iwl_trans
*trans
, u32 ofs
, u8 val
)
1609 iowrite8(val
, IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1612 static void iwl_trans_pcie_write32(struct iwl_trans
*trans
, u32 ofs
, u32 val
)
1614 iowrite32(val
, IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1617 static u32
iwl_trans_pcie_read32(struct iwl_trans
*trans
, u32 ofs
)
1619 u32 val
= ioread32(IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1623 static void iwl_trans_pcie_free(struct iwl_trans
*trans
)
1625 struct iwl_trans_pcie
*trans_pcie
=
1626 IWL_TRANS_GET_PCIE_TRANS(trans
);
1628 iwl_trans_pcie_tx_free(trans
);
1629 #ifndef CONFIG_IWLWIFI_IDI
1630 iwl_trans_pcie_rx_free(trans
);
1632 if (trans_pcie
->irq_requested
== true) {
1633 free_irq(trans
->irq
, trans
);
1634 iwl_free_isr_ict(trans
);
1637 pci_disable_msi(trans_pcie
->pci_dev
);
1638 pci_iounmap(trans_pcie
->pci_dev
, trans_pcie
->hw_base
);
1639 pci_release_regions(trans_pcie
->pci_dev
);
1640 pci_disable_device(trans_pcie
->pci_dev
);
1642 trans
->shrd
->trans
= NULL
;
1646 #ifdef CONFIG_PM_SLEEP
1647 static int iwl_trans_pcie_suspend(struct iwl_trans
*trans
)
1652 static int iwl_trans_pcie_resume(struct iwl_trans
*trans
)
1656 iwl_enable_interrupts(trans
);
1658 hw_rfkill
= !(iwl_read32(trans
, CSR_GP_CNTRL
) &
1659 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW
);
1660 iwl_op_mode_hw_rf_kill(trans
->op_mode
, hw_rfkill
);
1664 #endif /* CONFIG_PM_SLEEP */
1666 static void iwl_trans_pcie_wake_any_queue(struct iwl_trans
*trans
,
1667 enum iwl_rxon_context_id ctx
,
1671 struct iwl_trans_pcie
*trans_pcie
=
1672 IWL_TRANS_GET_PCIE_TRANS(trans
);
1674 for (ac
= 0; ac
< AC_NUM
; ac
++) {
1675 txq_id
= trans_pcie
->ac_to_queue
[ctx
][ac
];
1676 IWL_DEBUG_TX_QUEUES(trans
, "Queue Status: Q[%d] %s\n",
1678 (atomic_read(&trans_pcie
->queue_stop_count
[ac
]) > 0)
1679 ? "stopped" : "awake");
1680 iwl_wake_queue(trans
, &trans_pcie
->txq
[txq_id
], msg
);
1684 static void iwl_trans_pcie_stop_queue(struct iwl_trans
*trans
, int txq_id
,
1687 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1689 iwl_stop_queue(trans
, &trans_pcie
->txq
[txq_id
], msg
);
1692 #define IWL_FLUSH_WAIT_MS 2000
1694 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans
*trans
)
1696 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1697 struct iwl_tx_queue
*txq
;
1698 struct iwl_queue
*q
;
1700 unsigned long now
= jiffies
;
1703 /* waiting for all the tx frames complete might take a while */
1704 for (cnt
= 0; cnt
< hw_params(trans
).max_txq_num
; cnt
++) {
1705 if (cnt
== trans
->shrd
->cmd_queue
)
1707 txq
= &trans_pcie
->txq
[cnt
];
1709 while (q
->read_ptr
!= q
->write_ptr
&& !time_after(jiffies
,
1710 now
+ msecs_to_jiffies(IWL_FLUSH_WAIT_MS
)))
1713 if (q
->read_ptr
!= q
->write_ptr
) {
1714 IWL_ERR(trans
, "fail to flush all tx fifo queues\n");
1723 * On every watchdog tick we check (latest) time stamp. If it does not
1724 * change during timeout period and queue is not empty we reset firmware.
1726 static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans
*trans
, int cnt
)
1728 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1729 struct iwl_tx_queue
*txq
= &trans_pcie
->txq
[cnt
];
1730 struct iwl_queue
*q
= &txq
->q
;
1731 unsigned long timeout
;
1733 if (q
->read_ptr
== q
->write_ptr
) {
1734 txq
->time_stamp
= jiffies
;
1738 timeout
= txq
->time_stamp
+
1739 msecs_to_jiffies(hw_params(trans
).wd_timeout
);
1741 if (time_after(jiffies
, timeout
)) {
1742 IWL_ERR(trans
, "Queue %d stuck for %u ms.\n", q
->id
,
1743 hw_params(trans
).wd_timeout
);
1744 IWL_ERR(trans
, "Current SW read_ptr %d write_ptr %d\n",
1745 q
->read_ptr
, q
->write_ptr
);
1746 IWL_ERR(trans
, "Current HW read_ptr %d write_ptr %d\n",
1747 iwl_read_prph(trans
, SCD_QUEUE_RDPTR(cnt
))
1748 & (TFD_QUEUE_SIZE_MAX
- 1),
1749 iwl_read_prph(trans
, SCD_QUEUE_WRPTR(cnt
)));
1756 static const char *get_fh_string(int cmd
)
1759 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG
);
1760 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG
);
1761 IWL_CMD(FH_RSCSR_CHNL0_WPTR
);
1762 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG
);
1763 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG
);
1764 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG
);
1765 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
);
1766 IWL_CMD(FH_TSSR_TX_STATUS_REG
);
1767 IWL_CMD(FH_TSSR_TX_ERROR_REG
);
1773 int iwl_dump_fh(struct iwl_trans
*trans
, char **buf
, bool display
)
1776 #ifdef CONFIG_IWLWIFI_DEBUG
1780 static const u32 fh_tbl
[] = {
1781 FH_RSCSR_CHNL0_STTS_WPTR_REG
,
1782 FH_RSCSR_CHNL0_RBDCB_BASE_REG
,
1783 FH_RSCSR_CHNL0_WPTR
,
1784 FH_MEM_RCSR_CHNL0_CONFIG_REG
,
1785 FH_MEM_RSSR_SHARED_CTRL_REG
,
1786 FH_MEM_RSSR_RX_STATUS_REG
,
1787 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
,
1788 FH_TSSR_TX_STATUS_REG
,
1789 FH_TSSR_TX_ERROR_REG
1791 #ifdef CONFIG_IWLWIFI_DEBUG
1793 bufsz
= ARRAY_SIZE(fh_tbl
) * 48 + 40;
1794 *buf
= kmalloc(bufsz
, GFP_KERNEL
);
1797 pos
+= scnprintf(*buf
+ pos
, bufsz
- pos
,
1798 "FH register values:\n");
1799 for (i
= 0; i
< ARRAY_SIZE(fh_tbl
); i
++) {
1800 pos
+= scnprintf(*buf
+ pos
, bufsz
- pos
,
1802 get_fh_string(fh_tbl
[i
]),
1803 iwl_read_direct32(trans
, fh_tbl
[i
]));
1808 IWL_ERR(trans
, "FH register values:\n");
1809 for (i
= 0; i
< ARRAY_SIZE(fh_tbl
); i
++) {
1810 IWL_ERR(trans
, " %34s: 0X%08x\n",
1811 get_fh_string(fh_tbl
[i
]),
1812 iwl_read_direct32(trans
, fh_tbl
[i
]));
1817 static const char *get_csr_string(int cmd
)
1820 IWL_CMD(CSR_HW_IF_CONFIG_REG
);
1821 IWL_CMD(CSR_INT_COALESCING
);
1823 IWL_CMD(CSR_INT_MASK
);
1824 IWL_CMD(CSR_FH_INT_STATUS
);
1825 IWL_CMD(CSR_GPIO_IN
);
1827 IWL_CMD(CSR_GP_CNTRL
);
1828 IWL_CMD(CSR_HW_REV
);
1829 IWL_CMD(CSR_EEPROM_REG
);
1830 IWL_CMD(CSR_EEPROM_GP
);
1831 IWL_CMD(CSR_OTP_GP_REG
);
1832 IWL_CMD(CSR_GIO_REG
);
1833 IWL_CMD(CSR_GP_UCODE_REG
);
1834 IWL_CMD(CSR_GP_DRIVER_REG
);
1835 IWL_CMD(CSR_UCODE_DRV_GP1
);
1836 IWL_CMD(CSR_UCODE_DRV_GP2
);
1837 IWL_CMD(CSR_LED_REG
);
1838 IWL_CMD(CSR_DRAM_INT_TBL_REG
);
1839 IWL_CMD(CSR_GIO_CHICKEN_BITS
);
1840 IWL_CMD(CSR_ANA_PLL_CFG
);
1841 IWL_CMD(CSR_HW_REV_WA_REG
);
1842 IWL_CMD(CSR_DBG_HPET_MEM_REG
);
1848 void iwl_dump_csr(struct iwl_trans
*trans
)
1851 static const u32 csr_tbl
[] = {
1852 CSR_HW_IF_CONFIG_REG
,
1870 CSR_DRAM_INT_TBL_REG
,
1871 CSR_GIO_CHICKEN_BITS
,
1874 CSR_DBG_HPET_MEM_REG
1876 IWL_ERR(trans
, "CSR values:\n");
1877 IWL_ERR(trans
, "(2nd byte of CSR_INT_COALESCING is "
1878 "CSR_INT_PERIODIC_REG)\n");
1879 for (i
= 0; i
< ARRAY_SIZE(csr_tbl
); i
++) {
1880 IWL_ERR(trans
, " %25s: 0X%08x\n",
1881 get_csr_string(csr_tbl
[i
]),
1882 iwl_read32(trans
, csr_tbl
[i
]));
1886 #ifdef CONFIG_IWLWIFI_DEBUGFS
1887 /* create and remove of files */
1888 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1889 if (!debugfs_create_file(#name, mode, parent, trans, \
1890 &iwl_dbgfs_##name##_ops)) \
1894 /* file operation */
1895 #define DEBUGFS_READ_FUNC(name) \
1896 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1897 char __user *user_buf, \
1898 size_t count, loff_t *ppos);
1900 #define DEBUGFS_WRITE_FUNC(name) \
1901 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1902 const char __user *user_buf, \
1903 size_t count, loff_t *ppos);
1906 static int iwl_dbgfs_open_file_generic(struct inode
*inode
, struct file
*file
)
1908 file
->private_data
= inode
->i_private
;
1912 #define DEBUGFS_READ_FILE_OPS(name) \
1913 DEBUGFS_READ_FUNC(name); \
1914 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1915 .read = iwl_dbgfs_##name##_read, \
1916 .open = iwl_dbgfs_open_file_generic, \
1917 .llseek = generic_file_llseek, \
1920 #define DEBUGFS_WRITE_FILE_OPS(name) \
1921 DEBUGFS_WRITE_FUNC(name); \
1922 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1923 .write = iwl_dbgfs_##name##_write, \
1924 .open = iwl_dbgfs_open_file_generic, \
1925 .llseek = generic_file_llseek, \
1928 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1929 DEBUGFS_READ_FUNC(name); \
1930 DEBUGFS_WRITE_FUNC(name); \
1931 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1932 .write = iwl_dbgfs_##name##_write, \
1933 .read = iwl_dbgfs_##name##_read, \
1934 .open = iwl_dbgfs_open_file_generic, \
1935 .llseek = generic_file_llseek, \
1938 static ssize_t
iwl_dbgfs_tx_queue_read(struct file
*file
,
1939 char __user
*user_buf
,
1940 size_t count
, loff_t
*ppos
)
1942 struct iwl_trans
*trans
= file
->private_data
;
1943 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1944 struct iwl_tx_queue
*txq
;
1945 struct iwl_queue
*q
;
1950 const size_t bufsz
= sizeof(char) * 64 * hw_params(trans
).max_txq_num
;
1952 if (!trans_pcie
->txq
) {
1953 IWL_ERR(trans
, "txq not ready\n");
1956 buf
= kzalloc(bufsz
, GFP_KERNEL
);
1960 for (cnt
= 0; cnt
< hw_params(trans
).max_txq_num
; cnt
++) {
1961 txq
= &trans_pcie
->txq
[cnt
];
1963 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1964 "hwq %.2d: read=%u write=%u stop=%d"
1965 " swq_id=%#.2x (ac %d/hwq %d)\n",
1966 cnt
, q
->read_ptr
, q
->write_ptr
,
1967 !!test_bit(cnt
, trans_pcie
->queue_stopped
),
1968 txq
->swq_id
, txq
->swq_id
& 3,
1969 (txq
->swq_id
>> 2) & 0x1f);
1972 /* for the ACs, display the stop count too */
1973 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1974 " stop-count: %d\n",
1975 atomic_read(&trans_pcie
->queue_stop_count
[cnt
]));
1977 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1982 static ssize_t
iwl_dbgfs_rx_queue_read(struct file
*file
,
1983 char __user
*user_buf
,
1984 size_t count
, loff_t
*ppos
) {
1985 struct iwl_trans
*trans
= file
->private_data
;
1986 struct iwl_trans_pcie
*trans_pcie
=
1987 IWL_TRANS_GET_PCIE_TRANS(trans
);
1988 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
1991 const size_t bufsz
= sizeof(buf
);
1993 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "read: %u\n",
1995 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "write: %u\n",
1997 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "free_count: %u\n",
2000 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "closed_rb_num: %u\n",
2001 le16_to_cpu(rxq
->rb_stts
->closed_rb_num
) & 0x0FFF);
2003 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2004 "closed_rb_num: Not Allocated\n");
2006 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
2009 static ssize_t
iwl_dbgfs_log_event_read(struct file
*file
,
2010 char __user
*user_buf
,
2011 size_t count
, loff_t
*ppos
)
2013 struct iwl_trans
*trans
= file
->private_data
;
2016 ssize_t ret
= -ENOMEM
;
2018 ret
= pos
= iwl_dump_nic_event_log(trans
, true, &buf
, true);
2020 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
2026 static ssize_t
iwl_dbgfs_log_event_write(struct file
*file
,
2027 const char __user
*user_buf
,
2028 size_t count
, loff_t
*ppos
)
2030 struct iwl_trans
*trans
= file
->private_data
;
2035 memset(buf
, 0, sizeof(buf
));
2036 buf_size
= min(count
, sizeof(buf
) - 1);
2037 if (copy_from_user(buf
, user_buf
, buf_size
))
2039 if (sscanf(buf
, "%d", &event_log_flag
) != 1)
2041 if (event_log_flag
== 1)
2042 iwl_dump_nic_event_log(trans
, true, NULL
, false);
2047 static ssize_t
iwl_dbgfs_interrupt_read(struct file
*file
,
2048 char __user
*user_buf
,
2049 size_t count
, loff_t
*ppos
) {
2051 struct iwl_trans
*trans
= file
->private_data
;
2052 struct iwl_trans_pcie
*trans_pcie
=
2053 IWL_TRANS_GET_PCIE_TRANS(trans
);
2054 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
2058 int bufsz
= 24 * 64; /* 24 items * 64 char per item */
2061 buf
= kzalloc(bufsz
, GFP_KERNEL
);
2063 IWL_ERR(trans
, "Can not allocate Buffer\n");
2067 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2068 "Interrupt Statistics Report:\n");
2070 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "HW Error:\t\t\t %u\n",
2072 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "SW Error:\t\t\t %u\n",
2074 if (isr_stats
->sw
|| isr_stats
->hw
) {
2075 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2076 "\tLast Restarting Code: 0x%X\n",
2077 isr_stats
->err_code
);
2079 #ifdef CONFIG_IWLWIFI_DEBUG
2080 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Frame transmitted:\t\t %u\n",
2082 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Alive interrupt:\t\t %u\n",
2085 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2086 "HW RF KILL switch toggled:\t %u\n", isr_stats
->rfkill
);
2088 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "CT KILL:\t\t\t %u\n",
2091 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Wakeup Interrupt:\t\t %u\n",
2094 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2095 "Rx command responses:\t\t %u\n", isr_stats
->rx
);
2097 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Tx/FH interrupt:\t\t %u\n",
2100 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Unexpected INTA:\t\t %u\n",
2101 isr_stats
->unhandled
);
2103 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
2108 static ssize_t
iwl_dbgfs_interrupt_write(struct file
*file
,
2109 const char __user
*user_buf
,
2110 size_t count
, loff_t
*ppos
)
2112 struct iwl_trans
*trans
= file
->private_data
;
2113 struct iwl_trans_pcie
*trans_pcie
=
2114 IWL_TRANS_GET_PCIE_TRANS(trans
);
2115 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
2121 memset(buf
, 0, sizeof(buf
));
2122 buf_size
= min(count
, sizeof(buf
) - 1);
2123 if (copy_from_user(buf
, user_buf
, buf_size
))
2125 if (sscanf(buf
, "%x", &reset_flag
) != 1)
2127 if (reset_flag
== 0)
2128 memset(isr_stats
, 0, sizeof(*isr_stats
));
2133 static ssize_t
iwl_dbgfs_csr_write(struct file
*file
,
2134 const char __user
*user_buf
,
2135 size_t count
, loff_t
*ppos
)
2137 struct iwl_trans
*trans
= file
->private_data
;
2142 memset(buf
, 0, sizeof(buf
));
2143 buf_size
= min(count
, sizeof(buf
) - 1);
2144 if (copy_from_user(buf
, user_buf
, buf_size
))
2146 if (sscanf(buf
, "%d", &csr
) != 1)
2149 iwl_dump_csr(trans
);
2154 static ssize_t
iwl_dbgfs_fh_reg_read(struct file
*file
,
2155 char __user
*user_buf
,
2156 size_t count
, loff_t
*ppos
)
2158 struct iwl_trans
*trans
= file
->private_data
;
2161 ssize_t ret
= -EFAULT
;
2163 ret
= pos
= iwl_dump_fh(trans
, &buf
, true);
2165 ret
= simple_read_from_buffer(user_buf
,
2166 count
, ppos
, buf
, pos
);
2173 DEBUGFS_READ_WRITE_FILE_OPS(log_event
);
2174 DEBUGFS_READ_WRITE_FILE_OPS(interrupt
);
2175 DEBUGFS_READ_FILE_OPS(fh_reg
);
2176 DEBUGFS_READ_FILE_OPS(rx_queue
);
2177 DEBUGFS_READ_FILE_OPS(tx_queue
);
2178 DEBUGFS_WRITE_FILE_OPS(csr
);
2181 * Create the debugfs files and directories
2184 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans
*trans
,
2187 DEBUGFS_ADD_FILE(rx_queue
, dir
, S_IRUSR
);
2188 DEBUGFS_ADD_FILE(tx_queue
, dir
, S_IRUSR
);
2189 DEBUGFS_ADD_FILE(log_event
, dir
, S_IWUSR
| S_IRUSR
);
2190 DEBUGFS_ADD_FILE(interrupt
, dir
, S_IWUSR
| S_IRUSR
);
2191 DEBUGFS_ADD_FILE(csr
, dir
, S_IWUSR
);
2192 DEBUGFS_ADD_FILE(fh_reg
, dir
, S_IRUSR
);
2196 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans
*trans
,
2200 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2202 const struct iwl_trans_ops trans_ops_pcie
= {
2203 .start_hw
= iwl_trans_pcie_start_hw
,
2204 .stop_hw
= iwl_trans_pcie_stop_hw
,
2205 .fw_alive
= iwl_trans_pcie_fw_alive
,
2206 .start_fw
= iwl_trans_pcie_start_fw
,
2207 .stop_device
= iwl_trans_pcie_stop_device
,
2209 .wowlan_suspend
= iwl_trans_pcie_wowlan_suspend
,
2211 .wake_any_queue
= iwl_trans_pcie_wake_any_queue
,
2213 .send_cmd
= iwl_trans_pcie_send_cmd
,
2215 .tx
= iwl_trans_pcie_tx
,
2216 .reclaim
= iwl_trans_pcie_reclaim
,
2218 .tx_agg_disable
= iwl_trans_pcie_tx_agg_disable
,
2219 .tx_agg_alloc
= iwl_trans_pcie_tx_agg_alloc
,
2220 .tx_agg_setup
= iwl_trans_pcie_tx_agg_setup
,
2222 .free
= iwl_trans_pcie_free
,
2223 .stop_queue
= iwl_trans_pcie_stop_queue
,
2225 .dbgfs_register
= iwl_trans_pcie_dbgfs_register
,
2227 .wait_tx_queue_empty
= iwl_trans_pcie_wait_tx_queue_empty
,
2228 .check_stuck_queue
= iwl_trans_pcie_check_stuck_queue
,
2230 #ifdef CONFIG_PM_SLEEP
2231 .suspend
= iwl_trans_pcie_suspend
,
2232 .resume
= iwl_trans_pcie_resume
,
2234 .write8
= iwl_trans_pcie_write8
,
2235 .write32
= iwl_trans_pcie_write32
,
2236 .read32
= iwl_trans_pcie_read32
,
2239 struct iwl_trans
*iwl_trans_pcie_alloc(struct iwl_shared
*shrd
,
2240 struct pci_dev
*pdev
,
2241 const struct pci_device_id
*ent
)
2243 struct iwl_trans_pcie
*trans_pcie
;
2244 struct iwl_trans
*trans
;
2248 trans
= kzalloc(sizeof(struct iwl_trans
) +
2249 sizeof(struct iwl_trans_pcie
), GFP_KERNEL
);
2251 if (WARN_ON(!trans
))
2254 trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2256 trans
->ops
= &trans_ops_pcie
;
2258 trans_pcie
->trans
= trans
;
2259 spin_lock_init(&trans_pcie
->irq_lock
);
2261 /* W/A - seems to solve weird behavior. We need to remove this if we
2262 * don't want to stay in L1 all the time. This wastes a lot of power */
2263 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
|
2264 PCIE_LINK_STATE_CLKPM
);
2266 if (pci_enable_device(pdev
)) {
2271 pci_set_master(pdev
);
2273 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(36));
2275 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(36));
2277 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
2279 err
= pci_set_consistent_dma_mask(pdev
,
2281 /* both attempts failed: */
2283 dev_printk(KERN_ERR
, &pdev
->dev
,
2284 "No suitable DMA available.\n");
2285 goto out_pci_disable_device
;
2289 err
= pci_request_regions(pdev
, DRV_NAME
);
2291 dev_printk(KERN_ERR
, &pdev
->dev
, "pci_request_regions failed");
2292 goto out_pci_disable_device
;
2295 trans_pcie
->hw_base
= pci_iomap(pdev
, 0, 0);
2296 if (!trans_pcie
->hw_base
) {
2297 dev_printk(KERN_ERR
, &pdev
->dev
, "pci_iomap failed");
2299 goto out_pci_release_regions
;
2302 dev_printk(KERN_INFO
, &pdev
->dev
,
2303 "pci_resource_len = 0x%08llx\n",
2304 (unsigned long long) pci_resource_len(pdev
, 0));
2305 dev_printk(KERN_INFO
, &pdev
->dev
,
2306 "pci_resource_base = %p\n", trans_pcie
->hw_base
);
2308 dev_printk(KERN_INFO
, &pdev
->dev
,
2309 "HW Revision ID = 0x%X\n", pdev
->revision
);
2311 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2312 * PCI Tx retries from interfering with C3 CPU state */
2313 pci_write_config_byte(pdev
, PCI_CFG_RETRY_TIMEOUT
, 0x00);
2315 err
= pci_enable_msi(pdev
);
2317 dev_printk(KERN_ERR
, &pdev
->dev
,
2318 "pci_enable_msi failed(0X%x)", err
);
2320 trans
->dev
= &pdev
->dev
;
2321 trans
->irq
= pdev
->irq
;
2322 trans_pcie
->pci_dev
= pdev
;
2323 trans
->hw_rev
= iwl_read32(trans
, CSR_HW_REV
);
2324 trans
->hw_id
= (pdev
->device
<< 16) + pdev
->subsystem_device
;
2325 snprintf(trans
->hw_id_str
, sizeof(trans
->hw_id_str
),
2326 "PCI ID: 0x%04X:0x%04X", pdev
->device
, pdev
->subsystem_device
);
2328 /* TODO: Move this away, not needed if not MSI */
2329 /* enable rfkill interrupt: hw bug w/a */
2330 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
2331 if (pci_cmd
& PCI_COMMAND_INTX_DISABLE
) {
2332 pci_cmd
&= ~PCI_COMMAND_INTX_DISABLE
;
2333 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
2338 out_pci_release_regions
:
2339 pci_release_regions(pdev
);
2340 out_pci_disable_device
:
2341 pci_disable_device(pdev
);