1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *****************************************************************************/
63 #include <linux/pci.h>
64 #include <linux/pci-aspm.h>
65 #include <linux/interrupt.h>
66 #include <linux/debugfs.h>
67 #include <linux/sched.h>
68 #include <linux/bitops.h>
69 #include <linux/gfp.h>
72 #include "iwl-trans.h"
73 #include "iwl-trans-pcie-int.h"
76 #include "iwl-eeprom.h"
77 #include "iwl-agn-hw.h"
78 /* FIXME: need to abstract out TX command (once we know what it looks like) */
79 #include "iwl-commands.h"
81 #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
83 #define SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie) \
84 (((1<<trans->cfg->base_params->num_of_queues) - 1) &\
85 (~(1<<(trans_pcie)->cmd_queue)))
87 static int iwl_trans_rx_alloc(struct iwl_trans
*trans
)
89 struct iwl_trans_pcie
*trans_pcie
=
90 IWL_TRANS_GET_PCIE_TRANS(trans
);
91 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
92 struct device
*dev
= trans
->dev
;
94 memset(&trans_pcie
->rxq
, 0, sizeof(trans_pcie
->rxq
));
96 spin_lock_init(&rxq
->lock
);
98 if (WARN_ON(rxq
->bd
|| rxq
->rb_stts
))
101 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
102 rxq
->bd
= dma_zalloc_coherent(dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
103 &rxq
->bd_dma
, GFP_KERNEL
);
107 /*Allocate the driver's pointer to receive buffer status */
108 rxq
->rb_stts
= dma_zalloc_coherent(dev
, sizeof(*rxq
->rb_stts
),
109 &rxq
->rb_stts_dma
, GFP_KERNEL
);
116 dma_free_coherent(dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
117 rxq
->bd
, rxq
->bd_dma
);
118 memset(&rxq
->bd_dma
, 0, sizeof(rxq
->bd_dma
));
124 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans
*trans
)
126 struct iwl_trans_pcie
*trans_pcie
=
127 IWL_TRANS_GET_PCIE_TRANS(trans
);
128 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
131 /* Fill the rx_used queue with _all_ of the Rx buffers */
132 for (i
= 0; i
< RX_FREE_BUFFERS
+ RX_QUEUE_SIZE
; i
++) {
133 /* In the reset function, these buffers may have been allocated
134 * to an SKB, so we need to unmap and free potential storage */
135 if (rxq
->pool
[i
].page
!= NULL
) {
136 dma_unmap_page(trans
->dev
, rxq
->pool
[i
].page_dma
,
137 PAGE_SIZE
<< trans_pcie
->rx_page_order
,
139 __free_pages(rxq
->pool
[i
].page
,
140 trans_pcie
->rx_page_order
);
141 rxq
->pool
[i
].page
= NULL
;
143 list_add_tail(&rxq
->pool
[i
].list
, &rxq
->rx_used
);
147 static void iwl_trans_rx_hw_init(struct iwl_trans
*trans
,
148 struct iwl_rx_queue
*rxq
)
150 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
152 const u32 rfdnlog
= RX_QUEUE_SIZE_LOG
; /* 256 RBDs */
153 u32 rb_timeout
= RX_RB_TIMEOUT
; /* FIXME: RX_RB_TIMEOUT for all devices? */
155 if (trans_pcie
->rx_buf_size_8k
)
156 rb_size
= FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K
;
158 rb_size
= FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K
;
161 iwl_write_direct32(trans
, FH_MEM_RCSR_CHNL0_CONFIG_REG
, 0);
163 /* Reset driver's Rx queue write index */
164 iwl_write_direct32(trans
, FH_RSCSR_CHNL0_RBDCB_WPTR_REG
, 0);
166 /* Tell device where to find RBD circular buffer in DRAM */
167 iwl_write_direct32(trans
, FH_RSCSR_CHNL0_RBDCB_BASE_REG
,
168 (u32
)(rxq
->bd_dma
>> 8));
170 /* Tell device where in DRAM to update its Rx status */
171 iwl_write_direct32(trans
, FH_RSCSR_CHNL0_STTS_WPTR_REG
,
172 rxq
->rb_stts_dma
>> 4);
175 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
176 * the credit mechanism in 5000 HW RX FIFO
177 * Direct rx interrupts to hosts
178 * Rx buffer size 4 or 8k
182 iwl_write_direct32(trans
, FH_MEM_RCSR_CHNL0_CONFIG_REG
,
183 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL
|
184 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY
|
185 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL
|
187 (rb_timeout
<< FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS
)|
188 (rfdnlog
<< FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS
));
190 /* Set interrupt coalescing timer to default (2048 usecs) */
191 iwl_write8(trans
, CSR_INT_COALESCING
, IWL_HOST_INT_TIMEOUT_DEF
);
194 static int iwl_rx_init(struct iwl_trans
*trans
)
196 struct iwl_trans_pcie
*trans_pcie
=
197 IWL_TRANS_GET_PCIE_TRANS(trans
);
198 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
204 err
= iwl_trans_rx_alloc(trans
);
209 spin_lock_irqsave(&rxq
->lock
, flags
);
210 INIT_LIST_HEAD(&rxq
->rx_free
);
211 INIT_LIST_HEAD(&rxq
->rx_used
);
213 iwl_trans_rxq_free_rx_bufs(trans
);
215 for (i
= 0; i
< RX_QUEUE_SIZE
; i
++)
216 rxq
->queue
[i
] = NULL
;
218 /* Set us so that we have processed and used all buffers, but have
219 * not restocked the Rx queue with fresh buffers */
220 rxq
->read
= rxq
->write
= 0;
221 rxq
->write_actual
= 0;
223 spin_unlock_irqrestore(&rxq
->lock
, flags
);
225 iwlagn_rx_replenish(trans
);
227 iwl_trans_rx_hw_init(trans
, rxq
);
229 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
230 rxq
->need_update
= 1;
231 iwl_rx_queue_update_write_ptr(trans
, rxq
);
232 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
237 static void iwl_trans_pcie_rx_free(struct iwl_trans
*trans
)
239 struct iwl_trans_pcie
*trans_pcie
=
240 IWL_TRANS_GET_PCIE_TRANS(trans
);
241 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
245 /*if rxq->bd is NULL, it means that nothing has been allocated,
248 IWL_DEBUG_INFO(trans
, "Free NULL rx context\n");
252 spin_lock_irqsave(&rxq
->lock
, flags
);
253 iwl_trans_rxq_free_rx_bufs(trans
);
254 spin_unlock_irqrestore(&rxq
->lock
, flags
);
256 dma_free_coherent(trans
->dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
257 rxq
->bd
, rxq
->bd_dma
);
258 memset(&rxq
->bd_dma
, 0, sizeof(rxq
->bd_dma
));
262 dma_free_coherent(trans
->dev
,
263 sizeof(struct iwl_rb_status
),
264 rxq
->rb_stts
, rxq
->rb_stts_dma
);
266 IWL_DEBUG_INFO(trans
, "Free rxq->rb_stts which is NULL\n");
267 memset(&rxq
->rb_stts_dma
, 0, sizeof(rxq
->rb_stts_dma
));
271 static int iwl_trans_rx_stop(struct iwl_trans
*trans
)
275 iwl_write_direct32(trans
, FH_MEM_RCSR_CHNL0_CONFIG_REG
, 0);
276 return iwl_poll_direct_bit(trans
, FH_MEM_RSSR_RX_STATUS_REG
,
277 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE
, 1000);
280 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans
*trans
,
281 struct iwl_dma_ptr
*ptr
, size_t size
)
283 if (WARN_ON(ptr
->addr
))
286 ptr
->addr
= dma_alloc_coherent(trans
->dev
, size
,
287 &ptr
->dma
, GFP_KERNEL
);
294 static inline void iwlagn_free_dma_ptr(struct iwl_trans
*trans
,
295 struct iwl_dma_ptr
*ptr
)
297 if (unlikely(!ptr
->addr
))
300 dma_free_coherent(trans
->dev
, ptr
->size
, ptr
->addr
, ptr
->dma
);
301 memset(ptr
, 0, sizeof(*ptr
));
304 static void iwl_trans_pcie_queue_stuck_timer(unsigned long data
)
306 struct iwl_tx_queue
*txq
= (void *)data
;
307 struct iwl_trans_pcie
*trans_pcie
= txq
->trans_pcie
;
308 struct iwl_trans
*trans
= iwl_trans_pcie_get_trans(trans_pcie
);
310 spin_lock(&txq
->lock
);
311 /* check if triggered erroneously */
312 if (txq
->q
.read_ptr
== txq
->q
.write_ptr
) {
313 spin_unlock(&txq
->lock
);
316 spin_unlock(&txq
->lock
);
319 IWL_ERR(trans
, "Queue %d stuck for %u ms.\n", txq
->q
.id
,
320 jiffies_to_msecs(trans_pcie
->wd_timeout
));
321 IWL_ERR(trans
, "Current SW read_ptr %d write_ptr %d\n",
322 txq
->q
.read_ptr
, txq
->q
.write_ptr
);
323 IWL_ERR(trans
, "Current HW read_ptr %d write_ptr %d\n",
324 iwl_read_prph(trans
, SCD_QUEUE_RDPTR(txq
->q
.id
))
325 & (TFD_QUEUE_SIZE_MAX
- 1),
326 iwl_read_prph(trans
, SCD_QUEUE_WRPTR(txq
->q
.id
)));
328 iwl_op_mode_nic_error(trans
->op_mode
);
331 static int iwl_trans_txq_alloc(struct iwl_trans
*trans
,
332 struct iwl_tx_queue
*txq
, int slots_num
,
335 size_t tfd_sz
= sizeof(struct iwl_tfd
) * TFD_QUEUE_SIZE_MAX
;
337 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
339 if (WARN_ON(txq
->entries
|| txq
->tfds
))
342 setup_timer(&txq
->stuck_timer
, iwl_trans_pcie_queue_stuck_timer
,
344 txq
->trans_pcie
= trans_pcie
;
346 txq
->q
.n_window
= slots_num
;
348 txq
->entries
= kcalloc(slots_num
,
349 sizeof(struct iwl_pcie_tx_queue_entry
),
355 if (txq_id
== trans_pcie
->cmd_queue
)
356 for (i
= 0; i
< slots_num
; i
++) {
357 txq
->entries
[i
].cmd
=
358 kmalloc(sizeof(struct iwl_device_cmd
),
360 if (!txq
->entries
[i
].cmd
)
364 /* Circular buffer of transmit frame descriptors (TFDs),
365 * shared with device */
366 txq
->tfds
= dma_alloc_coherent(trans
->dev
, tfd_sz
,
367 &txq
->q
.dma_addr
, GFP_KERNEL
);
369 IWL_ERR(trans
, "dma_alloc_coherent(%zd) failed\n", tfd_sz
);
376 if (txq
->entries
&& txq_id
== trans_pcie
->cmd_queue
)
377 for (i
= 0; i
< slots_num
; i
++)
378 kfree(txq
->entries
[i
].cmd
);
386 static int iwl_trans_txq_init(struct iwl_trans
*trans
, struct iwl_tx_queue
*txq
,
387 int slots_num
, u32 txq_id
)
391 txq
->need_update
= 0;
393 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
394 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
395 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX
& (TFD_QUEUE_SIZE_MAX
- 1));
397 /* Initialize queue's high/low-water marks, and head/tail indexes */
398 ret
= iwl_queue_init(&txq
->q
, TFD_QUEUE_SIZE_MAX
, slots_num
,
403 spin_lock_init(&txq
->lock
);
406 * Tell nic where to find circular buffer of Tx Frame Descriptors for
407 * given Tx queue, and enable the DMA channel used for that queue.
408 * Circular buffer (TFD queue in DRAM) physical base address */
409 iwl_write_direct32(trans
, FH_MEM_CBBC_QUEUE(txq_id
),
410 txq
->q
.dma_addr
>> 8);
416 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
418 static void iwl_tx_queue_unmap(struct iwl_trans
*trans
, int txq_id
)
420 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
421 struct iwl_tx_queue
*txq
= &trans_pcie
->txq
[txq_id
];
422 struct iwl_queue
*q
= &txq
->q
;
423 enum dma_data_direction dma_dir
;
428 /* In the command queue, all the TBs are mapped as BIDI
429 * so unmap them as such.
431 if (txq_id
== trans_pcie
->cmd_queue
)
432 dma_dir
= DMA_BIDIRECTIONAL
;
434 dma_dir
= DMA_TO_DEVICE
;
436 spin_lock_bh(&txq
->lock
);
437 while (q
->write_ptr
!= q
->read_ptr
) {
438 iwlagn_txq_free_tfd(trans
, txq
, dma_dir
);
439 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
);
441 spin_unlock_bh(&txq
->lock
);
445 * iwl_tx_queue_free - Deallocate DMA queue.
446 * @txq: Transmit queue to deallocate.
448 * Empty queue by removing and destroying all BD's.
450 * 0-fill, but do not free "txq" descriptor structure.
452 static void iwl_tx_queue_free(struct iwl_trans
*trans
, int txq_id
)
454 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
455 struct iwl_tx_queue
*txq
= &trans_pcie
->txq
[txq_id
];
456 struct device
*dev
= trans
->dev
;
461 iwl_tx_queue_unmap(trans
, txq_id
);
463 /* De-alloc array of command/tx buffers */
465 if (txq_id
== trans_pcie
->cmd_queue
)
466 for (i
= 0; i
< txq
->q
.n_window
; i
++)
467 kfree(txq
->entries
[i
].cmd
);
469 /* De-alloc circular buffer of TFDs */
471 dma_free_coherent(dev
, sizeof(struct iwl_tfd
) *
472 txq
->q
.n_bd
, txq
->tfds
, txq
->q
.dma_addr
);
473 memset(&txq
->q
.dma_addr
, 0, sizeof(txq
->q
.dma_addr
));
479 del_timer_sync(&txq
->stuck_timer
);
481 /* 0-fill queue descriptor structure */
482 memset(txq
, 0, sizeof(*txq
));
486 * iwl_trans_tx_free - Free TXQ Context
488 * Destroy all TX DMA queues and structures
490 static void iwl_trans_pcie_tx_free(struct iwl_trans
*trans
)
493 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
496 if (trans_pcie
->txq
) {
498 txq_id
< trans
->cfg
->base_params
->num_of_queues
; txq_id
++)
499 iwl_tx_queue_free(trans
, txq_id
);
502 kfree(trans_pcie
->txq
);
503 trans_pcie
->txq
= NULL
;
505 iwlagn_free_dma_ptr(trans
, &trans_pcie
->kw
);
507 iwlagn_free_dma_ptr(trans
, &trans_pcie
->scd_bc_tbls
);
511 * iwl_trans_tx_alloc - allocate TX context
512 * Allocate all Tx DMA structures and initialize them
517 static int iwl_trans_tx_alloc(struct iwl_trans
*trans
)
520 int txq_id
, slots_num
;
521 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
523 u16 scd_bc_tbls_size
= trans
->cfg
->base_params
->num_of_queues
*
524 sizeof(struct iwlagn_scd_bc_tbl
);
526 /*It is not allowed to alloc twice, so warn when this happens.
527 * We cannot rely on the previous allocation, so free and fail */
528 if (WARN_ON(trans_pcie
->txq
)) {
533 ret
= iwlagn_alloc_dma_ptr(trans
, &trans_pcie
->scd_bc_tbls
,
536 IWL_ERR(trans
, "Scheduler BC Table allocation failed\n");
540 /* Alloc keep-warm buffer */
541 ret
= iwlagn_alloc_dma_ptr(trans
, &trans_pcie
->kw
, IWL_KW_SIZE
);
543 IWL_ERR(trans
, "Keep Warm allocation failed\n");
547 trans_pcie
->txq
= kcalloc(trans
->cfg
->base_params
->num_of_queues
,
548 sizeof(struct iwl_tx_queue
), GFP_KERNEL
);
549 if (!trans_pcie
->txq
) {
550 IWL_ERR(trans
, "Not enough memory for txq\n");
555 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
556 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
558 slots_num
= (txq_id
== trans_pcie
->cmd_queue
) ?
559 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
560 ret
= iwl_trans_txq_alloc(trans
, &trans_pcie
->txq
[txq_id
],
563 IWL_ERR(trans
, "Tx %d queue alloc failed\n", txq_id
);
571 iwl_trans_pcie_tx_free(trans
);
575 static int iwl_tx_init(struct iwl_trans
*trans
)
578 int txq_id
, slots_num
;
581 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
583 if (!trans_pcie
->txq
) {
584 ret
= iwl_trans_tx_alloc(trans
);
590 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
592 /* Turn off all Tx DMA fifos */
593 iwl_write_prph(trans
, SCD_TXFACT
, 0);
595 /* Tell NIC where to find the "keep warm" buffer */
596 iwl_write_direct32(trans
, FH_KW_MEM_ADDR_REG
,
597 trans_pcie
->kw
.dma
>> 4);
599 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
601 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
602 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
604 slots_num
= (txq_id
== trans_pcie
->cmd_queue
) ?
605 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
606 ret
= iwl_trans_txq_init(trans
, &trans_pcie
->txq
[txq_id
],
609 IWL_ERR(trans
, "Tx %d queue init failed\n", txq_id
);
616 /*Upon error, free only if we allocated something */
618 iwl_trans_pcie_tx_free(trans
);
622 static void iwl_set_pwr_vmain(struct iwl_trans
*trans
)
625 * (for documentation purposes)
626 * to set power to V_AUX, do:
628 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
629 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
630 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
631 ~APMG_PS_CTRL_MSK_PWR_SRC);
634 iwl_set_bits_mask_prph(trans
, APMG_PS_CTRL_REG
,
635 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN
,
636 ~APMG_PS_CTRL_MSK_PWR_SRC
);
640 #define PCI_CFG_RETRY_TIMEOUT 0x041
641 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
642 #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
644 static u16
iwl_pciexp_link_ctrl(struct iwl_trans
*trans
)
648 struct iwl_trans_pcie
*trans_pcie
=
649 IWL_TRANS_GET_PCIE_TRANS(trans
);
651 struct pci_dev
*pci_dev
= trans_pcie
->pci_dev
;
653 pos
= pci_pcie_cap(pci_dev
);
654 pci_read_config_word(pci_dev
, pos
+ PCI_EXP_LNKCTL
, &pci_lnk_ctl
);
658 static void iwl_apm_config(struct iwl_trans
*trans
)
661 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
662 * Check if BIOS (or OS) enabled L1-ASPM on this device.
663 * If so (likely), disable L0S, so device moves directly L0->L1;
664 * costs negligible amount of power savings.
665 * If not (unlikely), enable L0S, so there is at least some
666 * power savings, even without L1.
668 u16 lctl
= iwl_pciexp_link_ctrl(trans
);
670 if ((lctl
& PCI_CFG_LINK_CTRL_VAL_L1_EN
) ==
671 PCI_CFG_LINK_CTRL_VAL_L1_EN
) {
672 /* L1-ASPM enabled; disable(!) L0S */
673 iwl_set_bit(trans
, CSR_GIO_REG
, CSR_GIO_REG_VAL_L0S_ENABLED
);
674 dev_printk(KERN_INFO
, trans
->dev
,
675 "L1 Enabled; Disabling L0S\n");
677 /* L1-ASPM disabled; enable(!) L0S */
678 iwl_clear_bit(trans
, CSR_GIO_REG
, CSR_GIO_REG_VAL_L0S_ENABLED
);
679 dev_printk(KERN_INFO
, trans
->dev
,
680 "L1 Disabled; Enabling L0S\n");
682 trans
->pm_support
= !(lctl
& PCI_CFG_LINK_CTRL_VAL_L0S_EN
);
686 * Start up NIC's basic functionality after it has been reset
687 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
688 * NOTE: This does not load uCode nor start the embedded processor
690 static int iwl_apm_init(struct iwl_trans
*trans
)
692 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
694 IWL_DEBUG_INFO(trans
, "Init card's basic functions\n");
697 * Use "set_bit" below rather than "write", to preserve any hardware
698 * bits already set by default after reset.
701 /* Disable L0S exit timer (platform NMI Work/Around) */
702 iwl_set_bit(trans
, CSR_GIO_CHICKEN_BITS
,
703 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER
);
706 * Disable L0s without affecting L1;
707 * don't wait for ICH L0s (ICH bug W/A)
709 iwl_set_bit(trans
, CSR_GIO_CHICKEN_BITS
,
710 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX
);
712 /* Set FH wait threshold to maximum (HW error during stress W/A) */
713 iwl_set_bit(trans
, CSR_DBG_HPET_MEM_REG
, CSR_DBG_HPET_MEM_REG_VAL
);
716 * Enable HAP INTA (interrupt from management bus) to
717 * wake device's PCI Express link L1a -> L0s
719 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
720 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A
);
722 iwl_apm_config(trans
);
724 /* Configure analog phase-lock-loop before activating to D0A */
725 if (trans
->cfg
->base_params
->pll_cfg_val
)
726 iwl_set_bit(trans
, CSR_ANA_PLL_CFG
,
727 trans
->cfg
->base_params
->pll_cfg_val
);
730 * Set "initialization complete" bit to move adapter from
731 * D0U* --> D0A* (powered-up active) state.
733 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
736 * Wait for clock stabilization; once stabilized, access to
737 * device-internal resources is supported, e.g. iwl_write_prph()
738 * and accesses to uCode SRAM.
740 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
741 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
742 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
, 25000);
744 IWL_DEBUG_INFO(trans
, "Failed to init the card\n");
749 * Enable DMA clock and wait for it to stabilize.
751 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
752 * do not disable clocks. This preserves any hardware bits already
753 * set by default in "CLK_CTRL_REG" after reset.
755 iwl_write_prph(trans
, APMG_CLK_EN_REG
, APMG_CLK_VAL_DMA_CLK_RQT
);
758 /* Disable L1-Active */
759 iwl_set_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
760 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
762 set_bit(STATUS_DEVICE_ENABLED
, &trans_pcie
->status
);
768 static int iwl_apm_stop_master(struct iwl_trans
*trans
)
772 /* stop device's busmaster DMA activity */
773 iwl_set_bit(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_STOP_MASTER
);
775 ret
= iwl_poll_bit(trans
, CSR_RESET
,
776 CSR_RESET_REG_FLAG_MASTER_DISABLED
,
777 CSR_RESET_REG_FLAG_MASTER_DISABLED
, 100);
779 IWL_WARN(trans
, "Master Disable Timed Out, 100 usec\n");
781 IWL_DEBUG_INFO(trans
, "stop master\n");
786 static void iwl_apm_stop(struct iwl_trans
*trans
)
788 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
789 IWL_DEBUG_INFO(trans
, "Stop card, put in low power state\n");
791 clear_bit(STATUS_DEVICE_ENABLED
, &trans_pcie
->status
);
793 /* Stop device's DMA activity */
794 iwl_apm_stop_master(trans
);
796 /* Reset the entire device */
797 iwl_set_bit(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
802 * Clear "initialization complete" bit to move adapter from
803 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
805 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
806 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
809 static int iwl_nic_init(struct iwl_trans
*trans
)
811 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
815 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
818 /* Set interrupt coalescing calibration timer to default (512 usecs) */
819 iwl_write8(trans
, CSR_INT_COALESCING
,
820 IWL_HOST_INT_CALIB_TIMEOUT_DEF
);
822 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
824 iwl_set_pwr_vmain(trans
);
826 iwl_op_mode_nic_config(trans
->op_mode
);
828 #ifndef CONFIG_IWLWIFI_IDI
829 /* Allocate the RX queue, or reset if it is already allocated */
833 /* Allocate or reset and init all Tx and Command queues */
834 if (iwl_tx_init(trans
))
837 if (trans
->cfg
->base_params
->shadow_reg_enable
) {
838 /* enable shadow regs in HW */
839 iwl_set_bit(trans
, CSR_MAC_SHADOW_REG_CTRL
,
846 #define HW_READY_TIMEOUT (50)
848 /* Note: returns poll_bit return value, which is >= 0 if success */
849 static int iwl_set_hw_ready(struct iwl_trans
*trans
)
853 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
854 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
);
856 /* See if we got it */
857 ret
= iwl_poll_bit(trans
, CSR_HW_IF_CONFIG_REG
,
858 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
859 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
862 IWL_DEBUG_INFO(trans
, "hardware%s ready\n", ret
< 0 ? " not" : "");
866 /* Note: returns standard 0/-ERROR code */
867 static int iwl_prepare_card_hw(struct iwl_trans
*trans
)
871 IWL_DEBUG_INFO(trans
, "iwl_trans_prepare_card_hw enter\n");
873 ret
= iwl_set_hw_ready(trans
);
874 /* If the card is ready, exit 0 */
878 /* If HW is not ready, prepare the conditions to check again */
879 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
880 CSR_HW_IF_CONFIG_REG_PREPARE
);
882 ret
= iwl_poll_bit(trans
, CSR_HW_IF_CONFIG_REG
,
883 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE
,
884 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE
, 150000);
889 /* HW should be ready by now, check again. */
890 ret
= iwl_set_hw_ready(trans
);
899 static int iwl_load_section(struct iwl_trans
*trans
, u8 section_num
,
900 const struct fw_desc
*section
)
902 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
903 dma_addr_t phy_addr
= section
->p_addr
;
904 u32 byte_cnt
= section
->len
;
905 u32 dst_addr
= section
->offset
;
908 trans_pcie
->ucode_write_complete
= false;
910 iwl_write_direct32(trans
,
911 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
912 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE
);
914 iwl_write_direct32(trans
,
915 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL
), dst_addr
);
917 iwl_write_direct32(trans
,
918 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL
),
919 phy_addr
& FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK
);
921 iwl_write_direct32(trans
,
922 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL
),
923 (iwl_get_dma_hi_addr(phy_addr
)
924 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT
) | byte_cnt
);
926 iwl_write_direct32(trans
,
927 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL
),
928 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM
|
929 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX
|
930 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID
);
932 iwl_write_direct32(trans
,
933 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
934 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
935 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE
|
936 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD
);
938 IWL_DEBUG_FW(trans
, "[%d] uCode section being loaded...\n",
940 ret
= wait_event_timeout(trans_pcie
->ucode_write_waitq
,
941 trans_pcie
->ucode_write_complete
, 5 * HZ
);
943 IWL_ERR(trans
, "Could not load the [%d] uCode section\n",
951 static int iwl_load_given_ucode(struct iwl_trans
*trans
,
952 const struct fw_img
*image
)
957 for (i
= 0; i
< IWL_UCODE_SECTION_MAX
; i
++) {
958 if (!image
->sec
[i
].p_addr
)
961 ret
= iwl_load_section(trans
, i
, &image
->sec
[i
]);
966 /* Remove all resets to allow NIC to operate */
967 iwl_write32(trans
, CSR_RESET
, 0);
972 static int iwl_trans_pcie_start_fw(struct iwl_trans
*trans
,
973 const struct fw_img
*fw
)
978 /* This may fail if AMT took ownership of the device */
979 if (iwl_prepare_card_hw(trans
)) {
980 IWL_WARN(trans
, "Exit HW not ready\n");
984 iwl_enable_rfkill_int(trans
);
986 /* If platform's RF_KILL switch is NOT set to KILL */
987 hw_rfkill
= iwl_is_rfkill_set(trans
);
988 iwl_op_mode_hw_rf_kill(trans
->op_mode
, hw_rfkill
);
992 iwl_write32(trans
, CSR_INT
, 0xFFFFFFFF);
994 ret
= iwl_nic_init(trans
);
996 IWL_ERR(trans
, "Unable to init nic\n");
1000 /* make sure rfkill handshake bits are cleared */
1001 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
1002 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
,
1003 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED
);
1005 /* clear (again), then enable host interrupts */
1006 iwl_write32(trans
, CSR_INT
, 0xFFFFFFFF);
1007 iwl_enable_interrupts(trans
);
1009 /* really make sure rfkill handshake bits are cleared */
1010 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
1011 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
1013 /* Load the given image to the HW */
1014 return iwl_load_given_ucode(trans
, fw
);
1018 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1019 * must be called under the irq lock and with MAC access
1021 static void iwl_trans_txq_set_sched(struct iwl_trans
*trans
, u32 mask
)
1023 struct iwl_trans_pcie __maybe_unused
*trans_pcie
=
1024 IWL_TRANS_GET_PCIE_TRANS(trans
);
1026 lockdep_assert_held(&trans_pcie
->irq_lock
);
1028 iwl_write_prph(trans
, SCD_TXFACT
, mask
);
1031 static void iwl_tx_start(struct iwl_trans
*trans
)
1033 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1035 unsigned long flags
;
1039 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
1041 trans_pcie
->scd_base_addr
=
1042 iwl_read_prph(trans
, SCD_SRAM_BASE_ADDR
);
1043 a
= trans_pcie
->scd_base_addr
+ SCD_CONTEXT_MEM_LOWER_BOUND
;
1044 /* reset conext data memory */
1045 for (; a
< trans_pcie
->scd_base_addr
+ SCD_CONTEXT_MEM_UPPER_BOUND
;
1047 iwl_write_targ_mem(trans
, a
, 0);
1048 /* reset tx status memory */
1049 for (; a
< trans_pcie
->scd_base_addr
+ SCD_TX_STTS_MEM_UPPER_BOUND
;
1051 iwl_write_targ_mem(trans
, a
, 0);
1052 for (; a
< trans_pcie
->scd_base_addr
+
1053 SCD_TRANS_TBL_OFFSET_QUEUE(
1054 trans
->cfg
->base_params
->num_of_queues
);
1056 iwl_write_targ_mem(trans
, a
, 0);
1058 iwl_write_prph(trans
, SCD_DRAM_BASE_ADDR
,
1059 trans_pcie
->scd_bc_tbls
.dma
>> 10);
1061 /* Enable DMA channel */
1062 for (chan
= 0; chan
< FH_TCSR_CHNL_NUM
; chan
++)
1063 iwl_write_direct32(trans
, FH_TCSR_CHNL_TX_CONFIG_REG(chan
),
1064 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
1065 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE
);
1067 /* Update FH chicken bits */
1068 reg_val
= iwl_read_direct32(trans
, FH_TX_CHICKEN_BITS_REG
);
1069 iwl_write_direct32(trans
, FH_TX_CHICKEN_BITS_REG
,
1070 reg_val
| FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN
);
1072 iwl_write_prph(trans
, SCD_QUEUECHAIN_SEL
,
1073 SCD_QUEUECHAIN_SEL_ALL(trans
, trans_pcie
));
1074 iwl_write_prph(trans
, SCD_AGGR_SEL
, 0);
1076 /* initiate the queues */
1077 for (i
= 0; i
< trans
->cfg
->base_params
->num_of_queues
; i
++) {
1078 iwl_write_prph(trans
, SCD_QUEUE_RDPTR(i
), 0);
1079 iwl_write_direct32(trans
, HBUS_TARG_WRPTR
, 0 | (i
<< 8));
1080 iwl_write_targ_mem(trans
, trans_pcie
->scd_base_addr
+
1081 SCD_CONTEXT_QUEUE_OFFSET(i
), 0);
1082 iwl_write_targ_mem(trans
, trans_pcie
->scd_base_addr
+
1083 SCD_CONTEXT_QUEUE_OFFSET(i
) +
1086 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS
) &
1087 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK
) |
1088 ((SCD_FRAME_LIMIT
<<
1089 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS
) &
1090 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK
));
1093 iwl_write_prph(trans
, SCD_INTERRUPT_MASK
,
1094 IWL_MASK(0, trans
->cfg
->base_params
->num_of_queues
));
1096 /* Activate all Tx DMA/FIFO channels */
1097 iwl_trans_txq_set_sched(trans
, IWL_MASK(0, 7));
1099 iwl_trans_set_wr_ptrs(trans
, trans_pcie
->cmd_queue
, 0);
1101 /* make sure all queue are not stopped/used */
1102 memset(trans_pcie
->queue_stopped
, 0, sizeof(trans_pcie
->queue_stopped
));
1103 memset(trans_pcie
->queue_used
, 0, sizeof(trans_pcie
->queue_used
));
1105 for (i
= 0; i
< trans_pcie
->n_q_to_fifo
; i
++) {
1106 int fifo
= trans_pcie
->setup_q_to_fifo
[i
];
1108 set_bit(i
, trans_pcie
->queue_used
);
1110 iwl_trans_tx_queue_set_status(trans
, &trans_pcie
->txq
[i
],
1114 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
1116 /* Enable L1-Active */
1117 iwl_clear_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
1118 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
1121 static void iwl_trans_pcie_fw_alive(struct iwl_trans
*trans
)
1123 iwl_reset_ict(trans
);
1124 iwl_tx_start(trans
);
1128 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1130 static int iwl_trans_tx_stop(struct iwl_trans
*trans
)
1132 int ch
, txq_id
, ret
;
1133 unsigned long flags
;
1134 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1136 /* Turn off all Tx DMA fifos */
1137 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
1139 iwl_trans_txq_set_sched(trans
, 0);
1141 /* Stop each Tx DMA channel, and wait for it to be idle */
1142 for (ch
= 0; ch
< FH_TCSR_CHNL_NUM
; ch
++) {
1143 iwl_write_direct32(trans
,
1144 FH_TCSR_CHNL_TX_CONFIG_REG(ch
), 0x0);
1145 ret
= iwl_poll_direct_bit(trans
, FH_TSSR_TX_STATUS_REG
,
1146 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch
),
1149 IWL_ERR(trans
, "Failing on timeout while stopping"
1150 " DMA channel %d [0x%08x]", ch
,
1151 iwl_read_direct32(trans
,
1152 FH_TSSR_TX_STATUS_REG
));
1154 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
1156 if (!trans_pcie
->txq
) {
1157 IWL_WARN(trans
, "Stopping tx queues that aren't allocated...");
1161 /* Unmap DMA from host system and free skb's */
1162 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
1164 iwl_tx_queue_unmap(trans
, txq_id
);
1169 static void iwl_trans_pcie_stop_device(struct iwl_trans
*trans
)
1171 unsigned long flags
;
1172 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1174 /* tell the device to stop sending interrupts */
1175 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
1176 iwl_disable_interrupts(trans
);
1177 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
1179 /* device going down, Stop using ICT table */
1180 iwl_disable_ict(trans
);
1183 * If a HW restart happens during firmware loading,
1184 * then the firmware loading might call this function
1185 * and later it might be called again due to the
1186 * restart. So don't process again if the device is
1189 if (test_bit(STATUS_DEVICE_ENABLED
, &trans_pcie
->status
)) {
1190 iwl_trans_tx_stop(trans
);
1191 #ifndef CONFIG_IWLWIFI_IDI
1192 iwl_trans_rx_stop(trans
);
1194 /* Power-down device's busmaster DMA clocks */
1195 iwl_write_prph(trans
, APMG_CLK_DIS_REG
,
1196 APMG_CLK_VAL_DMA_CLK_RQT
);
1200 /* Make sure (redundant) we've released our request to stay awake */
1201 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
1202 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1204 /* Stop the device, and put it in low power state */
1205 iwl_apm_stop(trans
);
1207 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1208 * Clean again the interrupt here
1210 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
1211 iwl_disable_interrupts(trans
);
1212 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
1214 iwl_enable_rfkill_int(trans
);
1216 /* wait to make sure we flush pending tasklet*/
1217 synchronize_irq(trans_pcie
->irq
);
1218 tasklet_kill(&trans_pcie
->irq_tasklet
);
1220 cancel_work_sync(&trans_pcie
->rx_replenish
);
1222 /* stop and reset the on-board processor */
1223 iwl_write32(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_NEVO_RESET
);
1225 /* clear all status bits */
1226 clear_bit(STATUS_HCMD_ACTIVE
, &trans_pcie
->status
);
1227 clear_bit(STATUS_INT_ENABLED
, &trans_pcie
->status
);
1228 clear_bit(STATUS_DEVICE_ENABLED
, &trans_pcie
->status
);
1229 clear_bit(STATUS_TPOWER_PMI
, &trans_pcie
->status
);
1232 static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans
*trans
)
1234 /* let the ucode operate on its own */
1235 iwl_write32(trans
, CSR_UCODE_DRV_GP1_SET
,
1236 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE
);
1238 iwl_disable_interrupts(trans
);
1239 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
1240 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1243 static int iwl_trans_pcie_tx(struct iwl_trans
*trans
, struct sk_buff
*skb
,
1244 struct iwl_device_cmd
*dev_cmd
, int txq_id
)
1246 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1247 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1248 struct iwl_tx_cmd
*tx_cmd
= (struct iwl_tx_cmd
*) dev_cmd
->payload
;
1249 struct iwl_cmd_meta
*out_meta
;
1250 struct iwl_tx_queue
*txq
;
1251 struct iwl_queue
*q
;
1252 dma_addr_t phys_addr
= 0;
1253 dma_addr_t txcmd_phys
;
1254 dma_addr_t scratch_phys
;
1255 u16 len
, firstlen
, secondlen
;
1256 u8 wait_write_ptr
= 0;
1257 __le16 fc
= hdr
->frame_control
;
1258 u8 hdr_len
= ieee80211_hdrlen(fc
);
1259 u16 __maybe_unused wifi_seq
;
1261 txq
= &trans_pcie
->txq
[txq_id
];
1264 if (unlikely(!test_bit(txq_id
, trans_pcie
->queue_used
))) {
1269 spin_lock(&txq
->lock
);
1271 /* Set up driver data for this TFD */
1272 txq
->entries
[q
->write_ptr
].skb
= skb
;
1273 txq
->entries
[q
->write_ptr
].cmd
= dev_cmd
;
1275 dev_cmd
->hdr
.cmd
= REPLY_TX
;
1276 dev_cmd
->hdr
.sequence
= cpu_to_le16((u16
)(QUEUE_TO_SEQ(txq_id
) |
1277 INDEX_TO_SEQ(q
->write_ptr
)));
1279 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1280 out_meta
= &txq
->entries
[q
->write_ptr
].meta
;
1283 * Use the first empty entry in this queue's command buffer array
1284 * to contain the Tx command and MAC header concatenated together
1285 * (payload data will be in another buffer).
1286 * Size of this varies, due to varying MAC header length.
1287 * If end is not dword aligned, we'll have 2 extra bytes at the end
1288 * of the MAC header (device reads on dword boundaries).
1289 * We'll tell device about this padding later.
1291 len
= sizeof(struct iwl_tx_cmd
) +
1292 sizeof(struct iwl_cmd_header
) + hdr_len
;
1293 firstlen
= (len
+ 3) & ~3;
1295 /* Tell NIC about any 2-byte padding after MAC header */
1296 if (firstlen
!= len
)
1297 tx_cmd
->tx_flags
|= TX_CMD_FLG_MH_PAD_MSK
;
1299 /* Physical address of this Tx command's header (not MAC header!),
1300 * within command buffer array. */
1301 txcmd_phys
= dma_map_single(trans
->dev
,
1302 &dev_cmd
->hdr
, firstlen
,
1304 if (unlikely(dma_mapping_error(trans
->dev
, txcmd_phys
)))
1306 dma_unmap_addr_set(out_meta
, mapping
, txcmd_phys
);
1307 dma_unmap_len_set(out_meta
, len
, firstlen
);
1309 if (!ieee80211_has_morefrags(fc
)) {
1310 txq
->need_update
= 1;
1313 txq
->need_update
= 0;
1316 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1317 * if any (802.11 null frames have no payload). */
1318 secondlen
= skb
->len
- hdr_len
;
1319 if (secondlen
> 0) {
1320 phys_addr
= dma_map_single(trans
->dev
, skb
->data
+ hdr_len
,
1321 secondlen
, DMA_TO_DEVICE
);
1322 if (unlikely(dma_mapping_error(trans
->dev
, phys_addr
))) {
1323 dma_unmap_single(trans
->dev
,
1324 dma_unmap_addr(out_meta
, mapping
),
1325 dma_unmap_len(out_meta
, len
),
1331 /* Attach buffers to TFD */
1332 iwlagn_txq_attach_buf_to_tfd(trans
, txq
, txcmd_phys
, firstlen
, 1);
1334 iwlagn_txq_attach_buf_to_tfd(trans
, txq
, phys_addr
,
1337 scratch_phys
= txcmd_phys
+ sizeof(struct iwl_cmd_header
) +
1338 offsetof(struct iwl_tx_cmd
, scratch
);
1340 /* take back ownership of DMA buffer to enable update */
1341 dma_sync_single_for_cpu(trans
->dev
, txcmd_phys
, firstlen
,
1343 tx_cmd
->dram_lsb_ptr
= cpu_to_le32(scratch_phys
);
1344 tx_cmd
->dram_msb_ptr
= iwl_get_dma_hi_addr(scratch_phys
);
1346 IWL_DEBUG_TX(trans
, "sequence nr = 0X%x\n",
1347 le16_to_cpu(dev_cmd
->hdr
.sequence
));
1348 IWL_DEBUG_TX(trans
, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd
->tx_flags
));
1350 /* Set up entry for this TFD in Tx byte-count array */
1351 iwl_trans_txq_update_byte_cnt_tbl(trans
, txq
, le16_to_cpu(tx_cmd
->len
));
1353 dma_sync_single_for_device(trans
->dev
, txcmd_phys
, firstlen
,
1356 trace_iwlwifi_dev_tx(trans
->dev
,
1357 &((struct iwl_tfd
*)txq
->tfds
)[txq
->q
.write_ptr
],
1358 sizeof(struct iwl_tfd
),
1359 &dev_cmd
->hdr
, firstlen
,
1360 skb
->data
+ hdr_len
, secondlen
);
1362 /* start timer if queue currently empty */
1363 if (q
->read_ptr
== q
->write_ptr
&& trans_pcie
->wd_timeout
)
1364 mod_timer(&txq
->stuck_timer
, jiffies
+ trans_pcie
->wd_timeout
);
1366 /* Tell device the write index *just past* this latest filled TFD */
1367 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
1368 iwl_txq_update_write_ptr(trans
, txq
);
1371 * At this point the frame is "transmitted" successfully
1372 * and we will get a TX status notification eventually,
1373 * regardless of the value of ret. "ret" only indicates
1374 * whether or not we should update the write pointer.
1376 if (iwl_queue_space(q
) < q
->high_mark
) {
1377 if (wait_write_ptr
) {
1378 txq
->need_update
= 1;
1379 iwl_txq_update_write_ptr(trans
, txq
);
1381 iwl_stop_queue(trans
, txq
);
1384 spin_unlock(&txq
->lock
);
1387 spin_unlock(&txq
->lock
);
1391 static int iwl_trans_pcie_start_hw(struct iwl_trans
*trans
)
1393 struct iwl_trans_pcie
*trans_pcie
=
1394 IWL_TRANS_GET_PCIE_TRANS(trans
);
1398 trans_pcie
->inta_mask
= CSR_INI_SET_MASK
;
1400 if (!trans_pcie
->irq_requested
) {
1401 tasklet_init(&trans_pcie
->irq_tasklet
, (void (*)(unsigned long))
1402 iwl_irq_tasklet
, (unsigned long)trans
);
1404 iwl_alloc_isr_ict(trans
);
1406 err
= request_irq(trans_pcie
->irq
, iwl_isr_ict
, IRQF_SHARED
,
1409 IWL_ERR(trans
, "Error allocating IRQ %d\n",
1414 INIT_WORK(&trans_pcie
->rx_replenish
, iwl_bg_rx_replenish
);
1415 trans_pcie
->irq_requested
= true;
1418 err
= iwl_prepare_card_hw(trans
);
1420 IWL_ERR(trans
, "Error while preparing HW: %d", err
);
1424 iwl_apm_init(trans
);
1426 /* From now on, the op_mode will be kept updated about RF kill state */
1427 iwl_enable_rfkill_int(trans
);
1429 hw_rfkill
= iwl_is_rfkill_set(trans
);
1430 iwl_op_mode_hw_rf_kill(trans
->op_mode
, hw_rfkill
);
1435 free_irq(trans_pcie
->irq
, trans
);
1437 iwl_free_isr_ict(trans
);
1438 tasklet_kill(&trans_pcie
->irq_tasklet
);
1442 static void iwl_trans_pcie_stop_hw(struct iwl_trans
*trans
,
1443 bool op_mode_leaving
)
1446 unsigned long flags
;
1447 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1449 iwl_apm_stop(trans
);
1451 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
1452 iwl_disable_interrupts(trans
);
1453 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
1455 iwl_write32(trans
, CSR_INT
, 0xFFFFFFFF);
1457 if (!op_mode_leaving
) {
1459 * Even if we stop the HW, we still want the RF kill
1462 iwl_enable_rfkill_int(trans
);
1465 * Check again since the RF kill state may have changed while
1466 * all the interrupts were disabled, in this case we couldn't
1467 * receive the RF kill interrupt and update the state in the
1470 hw_rfkill
= iwl_is_rfkill_set(trans
);
1471 iwl_op_mode_hw_rf_kill(trans
->op_mode
, hw_rfkill
);
1475 static void iwl_trans_pcie_reclaim(struct iwl_trans
*trans
, int txq_id
, int ssn
,
1476 struct sk_buff_head
*skbs
)
1478 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1479 struct iwl_tx_queue
*txq
= &trans_pcie
->txq
[txq_id
];
1480 /* n_bd is usually 256 => n_bd - 1 = 0xff */
1481 int tfd_num
= ssn
& (txq
->q
.n_bd
- 1);
1484 spin_lock(&txq
->lock
);
1486 if (txq
->q
.read_ptr
!= tfd_num
) {
1487 IWL_DEBUG_TX_REPLY(trans
, "[Q %d] %d -> %d (%d)\n",
1488 txq_id
, txq
->q
.read_ptr
, tfd_num
, ssn
);
1489 freed
= iwl_tx_queue_reclaim(trans
, txq_id
, tfd_num
, skbs
);
1490 if (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
)
1491 iwl_wake_queue(trans
, txq
);
1494 spin_unlock(&txq
->lock
);
1497 static void iwl_trans_pcie_write8(struct iwl_trans
*trans
, u32 ofs
, u8 val
)
1499 writeb(val
, IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1502 static void iwl_trans_pcie_write32(struct iwl_trans
*trans
, u32 ofs
, u32 val
)
1504 writel(val
, IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1507 static u32
iwl_trans_pcie_read32(struct iwl_trans
*trans
, u32 ofs
)
1509 return readl(IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1512 static void iwl_trans_pcie_configure(struct iwl_trans
*trans
,
1513 const struct iwl_trans_config
*trans_cfg
)
1515 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1517 trans_pcie
->cmd_queue
= trans_cfg
->cmd_queue
;
1518 if (WARN_ON(trans_cfg
->n_no_reclaim_cmds
> MAX_NO_RECLAIM_CMDS
))
1519 trans_pcie
->n_no_reclaim_cmds
= 0;
1521 trans_pcie
->n_no_reclaim_cmds
= trans_cfg
->n_no_reclaim_cmds
;
1522 if (trans_pcie
->n_no_reclaim_cmds
)
1523 memcpy(trans_pcie
->no_reclaim_cmds
, trans_cfg
->no_reclaim_cmds
,
1524 trans_pcie
->n_no_reclaim_cmds
* sizeof(u8
));
1526 trans_pcie
->n_q_to_fifo
= trans_cfg
->n_queue_to_fifo
;
1528 if (WARN_ON(trans_pcie
->n_q_to_fifo
> IWL_MAX_HW_QUEUES
))
1529 trans_pcie
->n_q_to_fifo
= IWL_MAX_HW_QUEUES
;
1531 /* at least the command queue must be mapped */
1532 WARN_ON(!trans_pcie
->n_q_to_fifo
);
1534 memcpy(trans_pcie
->setup_q_to_fifo
, trans_cfg
->queue_to_fifo
,
1535 trans_pcie
->n_q_to_fifo
* sizeof(u8
));
1537 trans_pcie
->rx_buf_size_8k
= trans_cfg
->rx_buf_size_8k
;
1538 if (trans_pcie
->rx_buf_size_8k
)
1539 trans_pcie
->rx_page_order
= get_order(8 * 1024);
1541 trans_pcie
->rx_page_order
= get_order(4 * 1024);
1543 trans_pcie
->wd_timeout
=
1544 msecs_to_jiffies(trans_cfg
->queue_watchdog_timeout
);
1546 trans_pcie
->command_names
= trans_cfg
->command_names
;
1549 void iwl_trans_pcie_free(struct iwl_trans
*trans
)
1551 struct iwl_trans_pcie
*trans_pcie
=
1552 IWL_TRANS_GET_PCIE_TRANS(trans
);
1554 iwl_trans_pcie_tx_free(trans
);
1555 #ifndef CONFIG_IWLWIFI_IDI
1556 iwl_trans_pcie_rx_free(trans
);
1558 if (trans_pcie
->irq_requested
== true) {
1559 free_irq(trans_pcie
->irq
, trans
);
1560 iwl_free_isr_ict(trans
);
1563 pci_disable_msi(trans_pcie
->pci_dev
);
1564 iounmap(trans_pcie
->hw_base
);
1565 pci_release_regions(trans_pcie
->pci_dev
);
1566 pci_disable_device(trans_pcie
->pci_dev
);
1571 static void iwl_trans_pcie_set_pmi(struct iwl_trans
*trans
, bool state
)
1573 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1576 set_bit(STATUS_TPOWER_PMI
, &trans_pcie
->status
);
1578 clear_bit(STATUS_TPOWER_PMI
, &trans_pcie
->status
);
1581 #ifdef CONFIG_PM_SLEEP
1582 static int iwl_trans_pcie_suspend(struct iwl_trans
*trans
)
1587 static int iwl_trans_pcie_resume(struct iwl_trans
*trans
)
1591 iwl_enable_rfkill_int(trans
);
1593 hw_rfkill
= iwl_is_rfkill_set(trans
);
1594 iwl_op_mode_hw_rf_kill(trans
->op_mode
, hw_rfkill
);
1597 iwl_enable_interrupts(trans
);
1601 #endif /* CONFIG_PM_SLEEP */
1603 #define IWL_FLUSH_WAIT_MS 2000
1605 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans
*trans
)
1607 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1608 struct iwl_tx_queue
*txq
;
1609 struct iwl_queue
*q
;
1611 unsigned long now
= jiffies
;
1614 /* waiting for all the tx frames complete might take a while */
1615 for (cnt
= 0; cnt
< trans
->cfg
->base_params
->num_of_queues
; cnt
++) {
1616 if (cnt
== trans_pcie
->cmd_queue
)
1618 txq
= &trans_pcie
->txq
[cnt
];
1620 while (q
->read_ptr
!= q
->write_ptr
&& !time_after(jiffies
,
1621 now
+ msecs_to_jiffies(IWL_FLUSH_WAIT_MS
)))
1624 if (q
->read_ptr
!= q
->write_ptr
) {
1625 IWL_ERR(trans
, "fail to flush all tx fifo queues\n");
1633 static const char *get_fh_string(int cmd
)
1635 #define IWL_CMD(x) case x: return #x
1637 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG
);
1638 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG
);
1639 IWL_CMD(FH_RSCSR_CHNL0_WPTR
);
1640 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG
);
1641 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG
);
1642 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG
);
1643 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
);
1644 IWL_CMD(FH_TSSR_TX_STATUS_REG
);
1645 IWL_CMD(FH_TSSR_TX_ERROR_REG
);
1652 int iwl_dump_fh(struct iwl_trans
*trans
, char **buf
, bool display
)
1655 #ifdef CONFIG_IWLWIFI_DEBUG
1659 static const u32 fh_tbl
[] = {
1660 FH_RSCSR_CHNL0_STTS_WPTR_REG
,
1661 FH_RSCSR_CHNL0_RBDCB_BASE_REG
,
1662 FH_RSCSR_CHNL0_WPTR
,
1663 FH_MEM_RCSR_CHNL0_CONFIG_REG
,
1664 FH_MEM_RSSR_SHARED_CTRL_REG
,
1665 FH_MEM_RSSR_RX_STATUS_REG
,
1666 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
,
1667 FH_TSSR_TX_STATUS_REG
,
1668 FH_TSSR_TX_ERROR_REG
1670 #ifdef CONFIG_IWLWIFI_DEBUG
1672 bufsz
= ARRAY_SIZE(fh_tbl
) * 48 + 40;
1673 *buf
= kmalloc(bufsz
, GFP_KERNEL
);
1676 pos
+= scnprintf(*buf
+ pos
, bufsz
- pos
,
1677 "FH register values:\n");
1678 for (i
= 0; i
< ARRAY_SIZE(fh_tbl
); i
++) {
1679 pos
+= scnprintf(*buf
+ pos
, bufsz
- pos
,
1681 get_fh_string(fh_tbl
[i
]),
1682 iwl_read_direct32(trans
, fh_tbl
[i
]));
1687 IWL_ERR(trans
, "FH register values:\n");
1688 for (i
= 0; i
< ARRAY_SIZE(fh_tbl
); i
++) {
1689 IWL_ERR(trans
, " %34s: 0X%08x\n",
1690 get_fh_string(fh_tbl
[i
]),
1691 iwl_read_direct32(trans
, fh_tbl
[i
]));
1696 static const char *get_csr_string(int cmd
)
1698 #define IWL_CMD(x) case x: return #x
1700 IWL_CMD(CSR_HW_IF_CONFIG_REG
);
1701 IWL_CMD(CSR_INT_COALESCING
);
1703 IWL_CMD(CSR_INT_MASK
);
1704 IWL_CMD(CSR_FH_INT_STATUS
);
1705 IWL_CMD(CSR_GPIO_IN
);
1707 IWL_CMD(CSR_GP_CNTRL
);
1708 IWL_CMD(CSR_HW_REV
);
1709 IWL_CMD(CSR_EEPROM_REG
);
1710 IWL_CMD(CSR_EEPROM_GP
);
1711 IWL_CMD(CSR_OTP_GP_REG
);
1712 IWL_CMD(CSR_GIO_REG
);
1713 IWL_CMD(CSR_GP_UCODE_REG
);
1714 IWL_CMD(CSR_GP_DRIVER_REG
);
1715 IWL_CMD(CSR_UCODE_DRV_GP1
);
1716 IWL_CMD(CSR_UCODE_DRV_GP2
);
1717 IWL_CMD(CSR_LED_REG
);
1718 IWL_CMD(CSR_DRAM_INT_TBL_REG
);
1719 IWL_CMD(CSR_GIO_CHICKEN_BITS
);
1720 IWL_CMD(CSR_ANA_PLL_CFG
);
1721 IWL_CMD(CSR_HW_REV_WA_REG
);
1722 IWL_CMD(CSR_DBG_HPET_MEM_REG
);
1729 void iwl_dump_csr(struct iwl_trans
*trans
)
1732 static const u32 csr_tbl
[] = {
1733 CSR_HW_IF_CONFIG_REG
,
1751 CSR_DRAM_INT_TBL_REG
,
1752 CSR_GIO_CHICKEN_BITS
,
1755 CSR_DBG_HPET_MEM_REG
1757 IWL_ERR(trans
, "CSR values:\n");
1758 IWL_ERR(trans
, "(2nd byte of CSR_INT_COALESCING is "
1759 "CSR_INT_PERIODIC_REG)\n");
1760 for (i
= 0; i
< ARRAY_SIZE(csr_tbl
); i
++) {
1761 IWL_ERR(trans
, " %25s: 0X%08x\n",
1762 get_csr_string(csr_tbl
[i
]),
1763 iwl_read32(trans
, csr_tbl
[i
]));
1767 #ifdef CONFIG_IWLWIFI_DEBUGFS
1768 /* create and remove of files */
1769 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1770 if (!debugfs_create_file(#name, mode, parent, trans, \
1771 &iwl_dbgfs_##name##_ops)) \
1775 /* file operation */
1776 #define DEBUGFS_READ_FUNC(name) \
1777 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1778 char __user *user_buf, \
1779 size_t count, loff_t *ppos);
1781 #define DEBUGFS_WRITE_FUNC(name) \
1782 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1783 const char __user *user_buf, \
1784 size_t count, loff_t *ppos);
1787 #define DEBUGFS_READ_FILE_OPS(name) \
1788 DEBUGFS_READ_FUNC(name); \
1789 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1790 .read = iwl_dbgfs_##name##_read, \
1791 .open = simple_open, \
1792 .llseek = generic_file_llseek, \
1795 #define DEBUGFS_WRITE_FILE_OPS(name) \
1796 DEBUGFS_WRITE_FUNC(name); \
1797 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1798 .write = iwl_dbgfs_##name##_write, \
1799 .open = simple_open, \
1800 .llseek = generic_file_llseek, \
1803 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1804 DEBUGFS_READ_FUNC(name); \
1805 DEBUGFS_WRITE_FUNC(name); \
1806 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1807 .write = iwl_dbgfs_##name##_write, \
1808 .read = iwl_dbgfs_##name##_read, \
1809 .open = simple_open, \
1810 .llseek = generic_file_llseek, \
1813 static ssize_t
iwl_dbgfs_tx_queue_read(struct file
*file
,
1814 char __user
*user_buf
,
1815 size_t count
, loff_t
*ppos
)
1817 struct iwl_trans
*trans
= file
->private_data
;
1818 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1819 struct iwl_tx_queue
*txq
;
1820 struct iwl_queue
*q
;
1827 bufsz
= sizeof(char) * 64 * trans
->cfg
->base_params
->num_of_queues
;
1829 if (!trans_pcie
->txq
)
1832 buf
= kzalloc(bufsz
, GFP_KERNEL
);
1836 for (cnt
= 0; cnt
< trans
->cfg
->base_params
->num_of_queues
; cnt
++) {
1837 txq
= &trans_pcie
->txq
[cnt
];
1839 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1840 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1841 cnt
, q
->read_ptr
, q
->write_ptr
,
1842 !!test_bit(cnt
, trans_pcie
->queue_used
),
1843 !!test_bit(cnt
, trans_pcie
->queue_stopped
));
1845 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1850 static ssize_t
iwl_dbgfs_rx_queue_read(struct file
*file
,
1851 char __user
*user_buf
,
1852 size_t count
, loff_t
*ppos
) {
1853 struct iwl_trans
*trans
= file
->private_data
;
1854 struct iwl_trans_pcie
*trans_pcie
=
1855 IWL_TRANS_GET_PCIE_TRANS(trans
);
1856 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
1859 const size_t bufsz
= sizeof(buf
);
1861 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "read: %u\n",
1863 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "write: %u\n",
1865 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "free_count: %u\n",
1868 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "closed_rb_num: %u\n",
1869 le16_to_cpu(rxq
->rb_stts
->closed_rb_num
) & 0x0FFF);
1871 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1872 "closed_rb_num: Not Allocated\n");
1874 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1877 static ssize_t
iwl_dbgfs_interrupt_read(struct file
*file
,
1878 char __user
*user_buf
,
1879 size_t count
, loff_t
*ppos
) {
1881 struct iwl_trans
*trans
= file
->private_data
;
1882 struct iwl_trans_pcie
*trans_pcie
=
1883 IWL_TRANS_GET_PCIE_TRANS(trans
);
1884 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
1888 int bufsz
= 24 * 64; /* 24 items * 64 char per item */
1891 buf
= kzalloc(bufsz
, GFP_KERNEL
);
1895 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1896 "Interrupt Statistics Report:\n");
1898 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "HW Error:\t\t\t %u\n",
1900 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "SW Error:\t\t\t %u\n",
1902 if (isr_stats
->sw
|| isr_stats
->hw
) {
1903 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1904 "\tLast Restarting Code: 0x%X\n",
1905 isr_stats
->err_code
);
1907 #ifdef CONFIG_IWLWIFI_DEBUG
1908 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Frame transmitted:\t\t %u\n",
1910 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Alive interrupt:\t\t %u\n",
1913 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1914 "HW RF KILL switch toggled:\t %u\n", isr_stats
->rfkill
);
1916 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "CT KILL:\t\t\t %u\n",
1919 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Wakeup Interrupt:\t\t %u\n",
1922 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1923 "Rx command responses:\t\t %u\n", isr_stats
->rx
);
1925 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Tx/FH interrupt:\t\t %u\n",
1928 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Unexpected INTA:\t\t %u\n",
1929 isr_stats
->unhandled
);
1931 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1936 static ssize_t
iwl_dbgfs_interrupt_write(struct file
*file
,
1937 const char __user
*user_buf
,
1938 size_t count
, loff_t
*ppos
)
1940 struct iwl_trans
*trans
= file
->private_data
;
1941 struct iwl_trans_pcie
*trans_pcie
=
1942 IWL_TRANS_GET_PCIE_TRANS(trans
);
1943 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
1949 memset(buf
, 0, sizeof(buf
));
1950 buf_size
= min(count
, sizeof(buf
) - 1);
1951 if (copy_from_user(buf
, user_buf
, buf_size
))
1953 if (sscanf(buf
, "%x", &reset_flag
) != 1)
1955 if (reset_flag
== 0)
1956 memset(isr_stats
, 0, sizeof(*isr_stats
));
1961 static ssize_t
iwl_dbgfs_csr_write(struct file
*file
,
1962 const char __user
*user_buf
,
1963 size_t count
, loff_t
*ppos
)
1965 struct iwl_trans
*trans
= file
->private_data
;
1970 memset(buf
, 0, sizeof(buf
));
1971 buf_size
= min(count
, sizeof(buf
) - 1);
1972 if (copy_from_user(buf
, user_buf
, buf_size
))
1974 if (sscanf(buf
, "%d", &csr
) != 1)
1977 iwl_dump_csr(trans
);
1982 static ssize_t
iwl_dbgfs_fh_reg_read(struct file
*file
,
1983 char __user
*user_buf
,
1984 size_t count
, loff_t
*ppos
)
1986 struct iwl_trans
*trans
= file
->private_data
;
1989 ssize_t ret
= -EFAULT
;
1991 ret
= pos
= iwl_dump_fh(trans
, &buf
, true);
1993 ret
= simple_read_from_buffer(user_buf
,
1994 count
, ppos
, buf
, pos
);
2001 static ssize_t
iwl_dbgfs_fw_restart_write(struct file
*file
,
2002 const char __user
*user_buf
,
2003 size_t count
, loff_t
*ppos
)
2005 struct iwl_trans
*trans
= file
->private_data
;
2007 if (!trans
->op_mode
)
2010 iwl_op_mode_nic_error(trans
->op_mode
);
2015 DEBUGFS_READ_WRITE_FILE_OPS(interrupt
);
2016 DEBUGFS_READ_FILE_OPS(fh_reg
);
2017 DEBUGFS_READ_FILE_OPS(rx_queue
);
2018 DEBUGFS_READ_FILE_OPS(tx_queue
);
2019 DEBUGFS_WRITE_FILE_OPS(csr
);
2020 DEBUGFS_WRITE_FILE_OPS(fw_restart
);
2023 * Create the debugfs files and directories
2026 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans
*trans
,
2029 DEBUGFS_ADD_FILE(rx_queue
, dir
, S_IRUSR
);
2030 DEBUGFS_ADD_FILE(tx_queue
, dir
, S_IRUSR
);
2031 DEBUGFS_ADD_FILE(interrupt
, dir
, S_IWUSR
| S_IRUSR
);
2032 DEBUGFS_ADD_FILE(csr
, dir
, S_IWUSR
);
2033 DEBUGFS_ADD_FILE(fh_reg
, dir
, S_IRUSR
);
2034 DEBUGFS_ADD_FILE(fw_restart
, dir
, S_IWUSR
);
2038 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans
*trans
,
2042 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2044 static const struct iwl_trans_ops trans_ops_pcie
= {
2045 .start_hw
= iwl_trans_pcie_start_hw
,
2046 .stop_hw
= iwl_trans_pcie_stop_hw
,
2047 .fw_alive
= iwl_trans_pcie_fw_alive
,
2048 .start_fw
= iwl_trans_pcie_start_fw
,
2049 .stop_device
= iwl_trans_pcie_stop_device
,
2051 .wowlan_suspend
= iwl_trans_pcie_wowlan_suspend
,
2053 .send_cmd
= iwl_trans_pcie_send_cmd
,
2055 .tx
= iwl_trans_pcie_tx
,
2056 .reclaim
= iwl_trans_pcie_reclaim
,
2058 .tx_agg_disable
= iwl_trans_pcie_tx_agg_disable
,
2059 .tx_agg_setup
= iwl_trans_pcie_tx_agg_setup
,
2061 .dbgfs_register
= iwl_trans_pcie_dbgfs_register
,
2063 .wait_tx_queue_empty
= iwl_trans_pcie_wait_tx_queue_empty
,
2065 #ifdef CONFIG_PM_SLEEP
2066 .suspend
= iwl_trans_pcie_suspend
,
2067 .resume
= iwl_trans_pcie_resume
,
2069 .write8
= iwl_trans_pcie_write8
,
2070 .write32
= iwl_trans_pcie_write32
,
2071 .read32
= iwl_trans_pcie_read32
,
2072 .configure
= iwl_trans_pcie_configure
,
2073 .set_pmi
= iwl_trans_pcie_set_pmi
,
2076 struct iwl_trans
*iwl_trans_pcie_alloc(struct pci_dev
*pdev
,
2077 const struct pci_device_id
*ent
,
2078 const struct iwl_cfg
*cfg
)
2080 struct iwl_trans_pcie
*trans_pcie
;
2081 struct iwl_trans
*trans
;
2085 trans
= kzalloc(sizeof(struct iwl_trans
) +
2086 sizeof(struct iwl_trans_pcie
), GFP_KERNEL
);
2088 if (WARN_ON(!trans
))
2091 trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2093 trans
->ops
= &trans_ops_pcie
;
2095 trans_pcie
->trans
= trans
;
2096 spin_lock_init(&trans_pcie
->irq_lock
);
2097 init_waitqueue_head(&trans_pcie
->ucode_write_waitq
);
2099 /* W/A - seems to solve weird behavior. We need to remove this if we
2100 * don't want to stay in L1 all the time. This wastes a lot of power */
2101 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
|
2102 PCIE_LINK_STATE_CLKPM
);
2104 if (pci_enable_device(pdev
)) {
2109 pci_set_master(pdev
);
2111 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(36));
2113 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(36));
2115 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
2117 err
= pci_set_consistent_dma_mask(pdev
,
2119 /* both attempts failed: */
2121 dev_printk(KERN_ERR
, &pdev
->dev
,
2122 "No suitable DMA available.\n");
2123 goto out_pci_disable_device
;
2127 err
= pci_request_regions(pdev
, DRV_NAME
);
2129 dev_printk(KERN_ERR
, &pdev
->dev
, "pci_request_regions failed");
2130 goto out_pci_disable_device
;
2133 trans_pcie
->hw_base
= pci_ioremap_bar(pdev
, 0);
2134 if (!trans_pcie
->hw_base
) {
2135 dev_printk(KERN_ERR
, &pdev
->dev
, "pci_ioremap_bar failed");
2137 goto out_pci_release_regions
;
2140 dev_printk(KERN_INFO
, &pdev
->dev
,
2141 "pci_resource_len = 0x%08llx\n",
2142 (unsigned long long) pci_resource_len(pdev
, 0));
2143 dev_printk(KERN_INFO
, &pdev
->dev
,
2144 "pci_resource_base = %p\n", trans_pcie
->hw_base
);
2146 dev_printk(KERN_INFO
, &pdev
->dev
,
2147 "HW Revision ID = 0x%X\n", pdev
->revision
);
2149 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2150 * PCI Tx retries from interfering with C3 CPU state */
2151 pci_write_config_byte(pdev
, PCI_CFG_RETRY_TIMEOUT
, 0x00);
2153 err
= pci_enable_msi(pdev
);
2155 dev_printk(KERN_ERR
, &pdev
->dev
,
2156 "pci_enable_msi failed(0X%x)", err
);
2158 trans
->dev
= &pdev
->dev
;
2159 trans_pcie
->irq
= pdev
->irq
;
2160 trans_pcie
->pci_dev
= pdev
;
2161 trans
->hw_rev
= iwl_read32(trans
, CSR_HW_REV
);
2162 trans
->hw_id
= (pdev
->device
<< 16) + pdev
->subsystem_device
;
2163 snprintf(trans
->hw_id_str
, sizeof(trans
->hw_id_str
),
2164 "PCI ID: 0x%04X:0x%04X", pdev
->device
, pdev
->subsystem_device
);
2166 /* TODO: Move this away, not needed if not MSI */
2167 /* enable rfkill interrupt: hw bug w/a */
2168 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
2169 if (pci_cmd
& PCI_COMMAND_INTX_DISABLE
) {
2170 pci_cmd
&= ~PCI_COMMAND_INTX_DISABLE
;
2171 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
2174 /* Initialize the wait queue for commands */
2175 init_waitqueue_head(&trans
->wait_command_queue
);
2176 spin_lock_init(&trans
->reg_lock
);
2180 out_pci_release_regions
:
2181 pci_release_regions(pdev
);
2182 out_pci_disable_device
:
2183 pci_disable_device(pdev
);