1 /******************************************************************************
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
29 #include <linux/sched.h>
30 #include <linux/wait.h>
31 #include <linux/gfp.h>
37 #include "iwl-helpers.h"
38 #include "iwl-trans-int-pcie.h"
40 /******************************************************************************
44 ******************************************************************************/
47 * Rx theory of operation
49 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
50 * each of which point to Receive Buffers to be filled by the NIC. These get
51 * used not only for Rx frames, but for any command response or notification
52 * from the NIC. The driver and NIC manage the Rx buffers by means
53 * of indexes into the circular buffer.
56 * The host/firmware share two index registers for managing the Rx buffers.
58 * The READ index maps to the first position that the firmware may be writing
59 * to -- the driver can read up to (but not including) this position and get
61 * The READ index is managed by the firmware once the card is enabled.
63 * The WRITE index maps to the last position the driver has read from -- the
64 * position preceding WRITE is the last slot the firmware can place a packet.
66 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
69 * During initialization, the host sets up the READ queue position to the first
70 * INDEX position, and WRITE to the last (READ - 1 wrapped)
72 * When the firmware places a packet in a buffer, it will advance the READ index
73 * and fire the RX interrupt. The driver can then query the READ index and
74 * process as many packets as possible, moving the WRITE index forward as it
75 * resets the Rx queue buffers with new memory.
77 * The management in the driver is as follows:
78 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
79 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
80 * to replenish the iwl->rxq->rx_free.
81 * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
82 * iwl->rxq is replenished and the READ INDEX is updated (updating the
83 * 'processed' and 'read' driver indexes as well)
84 * + A received packet is processed and handed to the kernel network stack,
85 * detached from the iwl->rxq. The driver 'processed' index is updated.
86 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
87 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
88 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
89 * were enough free buffers and RX_STALLED is set it is cleared.
94 * iwl_rx_queue_alloc() Allocates rx_free
95 * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls
96 * iwl_rx_queue_restock
97 * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
98 * queue, updates firmware pointers, and updates
99 * the WRITE index. If insufficient rx_free buffers
100 * are available, schedules iwl_rx_replenish
102 * -- enable interrupts --
103 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
104 * READ INDEX, detaching the SKB from the pool.
105 * Moves the packet buffer from queue to rx_used.
106 * Calls iwl_rx_queue_restock to refill any empty
113 * iwl_rx_queue_space - Return number of free slots available in queue.
115 static int iwl_rx_queue_space(const struct iwl_rx_queue
*q
)
117 int s
= q
->read
- q
->write
;
120 /* keep some buffer to not confuse full and empty queue */
128 * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
130 void iwl_rx_queue_update_write_ptr(struct iwl_trans
*trans
,
131 struct iwl_rx_queue
*q
)
133 struct iwl_priv
*priv
= priv(trans
);
137 spin_lock_irqsave(&q
->lock
, flags
);
139 if (q
->need_update
== 0)
142 if (priv
->cfg
->base_params
->shadow_reg_enable
) {
143 /* shadow register enabled */
144 /* Device expects a multiple of 8 */
145 q
->write_actual
= (q
->write
& ~0x7);
146 iwl_write32(priv
, FH_RSCSR_CHNL0_WPTR
, q
->write_actual
);
148 /* If power-saving is in use, make sure device is awake */
149 if (test_bit(STATUS_POWER_PMI
, &trans
->shrd
->status
)) {
150 reg
= iwl_read32(priv
, CSR_UCODE_DRV_GP1
);
152 if (reg
& CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP
) {
153 IWL_DEBUG_INFO(trans
,
154 "Rx queue requesting wakeup,"
155 " GP1 = 0x%x\n", reg
);
156 iwl_set_bit(priv
, CSR_GP_CNTRL
,
157 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
161 q
->write_actual
= (q
->write
& ~0x7);
162 iwl_write_direct32(priv
, FH_RSCSR_CHNL0_WPTR
,
165 /* Else device is assumed to be awake */
167 /* Device expects a multiple of 8 */
168 q
->write_actual
= (q
->write
& ~0x7);
169 iwl_write_direct32(priv
, FH_RSCSR_CHNL0_WPTR
,
176 spin_unlock_irqrestore(&q
->lock
, flags
);
180 * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
182 static inline __le32
iwlagn_dma_addr2rbd_ptr(dma_addr_t dma_addr
)
184 return cpu_to_le32((u32
)(dma_addr
>> 8));
188 * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
190 * If there are slots in the RX queue that need to be restocked,
191 * and we have free pre-allocated buffers, fill the ranks as much
192 * as we can, pulling from rx_free.
194 * This moves the 'write' index forward to catch up with 'processed', and
195 * also updates the memory address in the firmware to reference the new
198 static void iwlagn_rx_queue_restock(struct iwl_trans
*trans
)
200 struct iwl_trans_pcie
*trans_pcie
=
201 IWL_TRANS_GET_PCIE_TRANS(trans
);
203 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
204 struct list_head
*element
;
205 struct iwl_rx_mem_buffer
*rxb
;
208 spin_lock_irqsave(&rxq
->lock
, flags
);
209 while ((iwl_rx_queue_space(rxq
) > 0) && (rxq
->free_count
)) {
210 /* The overwritten rxb must be a used one */
211 rxb
= rxq
->queue
[rxq
->write
];
212 BUG_ON(rxb
&& rxb
->page
);
214 /* Get next free Rx buffer, remove from free list */
215 element
= rxq
->rx_free
.next
;
216 rxb
= list_entry(element
, struct iwl_rx_mem_buffer
, list
);
219 /* Point to Rx buffer via next RBD in circular buffer */
220 rxq
->bd
[rxq
->write
] = iwlagn_dma_addr2rbd_ptr(rxb
->page_dma
);
221 rxq
->queue
[rxq
->write
] = rxb
;
222 rxq
->write
= (rxq
->write
+ 1) & RX_QUEUE_MASK
;
225 spin_unlock_irqrestore(&rxq
->lock
, flags
);
226 /* If the pre-allocated buffer pool is dropping low, schedule to
228 if (rxq
->free_count
<= RX_LOW_WATERMARK
)
229 queue_work(trans
->shrd
->workqueue
, &trans_pcie
->rx_replenish
);
232 /* If we've added more space for the firmware to place data, tell it.
233 * Increment device's write pointer in multiples of 8. */
234 if (rxq
->write_actual
!= (rxq
->write
& ~0x7)) {
235 spin_lock_irqsave(&rxq
->lock
, flags
);
236 rxq
->need_update
= 1;
237 spin_unlock_irqrestore(&rxq
->lock
, flags
);
238 iwl_rx_queue_update_write_ptr(trans
, rxq
);
243 * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
245 * When moving to rx_free an SKB is allocated for the slot.
247 * Also restock the Rx queue via iwl_rx_queue_restock.
248 * This is called as a scheduled work item (except for during initialization)
250 static void iwlagn_rx_allocate(struct iwl_trans
*trans
, gfp_t priority
)
252 struct iwl_trans_pcie
*trans_pcie
=
253 IWL_TRANS_GET_PCIE_TRANS(trans
);
255 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
256 struct list_head
*element
;
257 struct iwl_rx_mem_buffer
*rxb
;
260 gfp_t gfp_mask
= priority
;
263 spin_lock_irqsave(&rxq
->lock
, flags
);
264 if (list_empty(&rxq
->rx_used
)) {
265 spin_unlock_irqrestore(&rxq
->lock
, flags
);
268 spin_unlock_irqrestore(&rxq
->lock
, flags
);
270 if (rxq
->free_count
> RX_LOW_WATERMARK
)
271 gfp_mask
|= __GFP_NOWARN
;
273 if (hw_params(trans
).rx_page_order
> 0)
274 gfp_mask
|= __GFP_COMP
;
276 /* Alloc a new receive buffer */
277 page
= alloc_pages(gfp_mask
,
278 hw_params(trans
).rx_page_order
);
281 IWL_DEBUG_INFO(trans
, "alloc_pages failed, "
283 hw_params(trans
).rx_page_order
);
285 if ((rxq
->free_count
<= RX_LOW_WATERMARK
) &&
287 IWL_CRIT(trans
, "Failed to alloc_pages with %s."
288 "Only %u free buffers remaining.\n",
289 priority
== GFP_ATOMIC
?
290 "GFP_ATOMIC" : "GFP_KERNEL",
292 /* We don't reschedule replenish work here -- we will
293 * call the restock method and if it still needs
294 * more buffers it will schedule replenish */
298 spin_lock_irqsave(&rxq
->lock
, flags
);
300 if (list_empty(&rxq
->rx_used
)) {
301 spin_unlock_irqrestore(&rxq
->lock
, flags
);
302 __free_pages(page
, hw_params(trans
).rx_page_order
);
305 element
= rxq
->rx_used
.next
;
306 rxb
= list_entry(element
, struct iwl_rx_mem_buffer
, list
);
309 spin_unlock_irqrestore(&rxq
->lock
, flags
);
313 /* Get physical address of the RB */
314 rxb
->page_dma
= dma_map_page(bus(trans
)->dev
, page
, 0,
315 PAGE_SIZE
<< hw_params(trans
).rx_page_order
,
317 /* dma address must be no more than 36 bits */
318 BUG_ON(rxb
->page_dma
& ~DMA_BIT_MASK(36));
319 /* and also 256 byte aligned! */
320 BUG_ON(rxb
->page_dma
& DMA_BIT_MASK(8));
322 spin_lock_irqsave(&rxq
->lock
, flags
);
324 list_add_tail(&rxb
->list
, &rxq
->rx_free
);
327 spin_unlock_irqrestore(&rxq
->lock
, flags
);
331 void iwlagn_rx_replenish(struct iwl_trans
*trans
)
335 iwlagn_rx_allocate(trans
, GFP_KERNEL
);
337 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
338 iwlagn_rx_queue_restock(trans
);
339 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
342 static void iwlagn_rx_replenish_now(struct iwl_trans
*trans
)
344 iwlagn_rx_allocate(trans
, GFP_ATOMIC
);
346 iwlagn_rx_queue_restock(trans
);
349 void iwl_bg_rx_replenish(struct work_struct
*data
)
351 struct iwl_trans_pcie
*trans_pcie
=
352 container_of(data
, struct iwl_trans_pcie
, rx_replenish
);
353 struct iwl_trans
*trans
= trans_pcie
->trans
;
355 if (test_bit(STATUS_EXIT_PENDING
, &trans
->shrd
->status
))
358 mutex_lock(&trans
->shrd
->mutex
);
359 iwlagn_rx_replenish(trans
);
360 mutex_unlock(&trans
->shrd
->mutex
);
364 * iwl_rx_handle - Main entry function for receiving responses from uCode
366 * Uses the priv->rx_handlers callback function array to invoke
367 * the appropriate handlers, including command responses,
368 * frame-received notifications, and other notifications.
370 static void iwl_rx_handle(struct iwl_trans
*trans
)
372 struct iwl_rx_mem_buffer
*rxb
;
373 struct iwl_rx_packet
*pkt
;
374 struct iwl_trans_pcie
*trans_pcie
=
375 IWL_TRANS_GET_PCIE_TRANS(trans
);
376 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
384 /* uCode's read index (stored in shared DRAM) indicates the last Rx
385 * buffer that the driver may process (last buffer filled by ucode). */
386 r
= le16_to_cpu(rxq
->rb_stts
->closed_rb_num
) & 0x0FFF;
389 /* Rx interrupt, but nothing sent from uCode */
391 IWL_DEBUG_RX(trans
, "r = %d, i = %d\n", r
, i
);
393 /* calculate total frames need to be restock after handling RX */
394 total_empty
= r
- rxq
->write_actual
;
396 total_empty
+= RX_QUEUE_SIZE
;
398 if (total_empty
> (RX_QUEUE_SIZE
/ 2))
406 /* If an RXB doesn't have a Rx queue slot associated with it,
407 * then a bug has been introduced in the queue refilling
408 * routines -- catch it here */
409 if (WARN_ON(rxb
== NULL
)) {
410 i
= (i
+ 1) & RX_QUEUE_MASK
;
414 rxq
->queue
[i
] = NULL
;
416 dma_unmap_page(bus(trans
)->dev
, rxb
->page_dma
,
417 PAGE_SIZE
<< hw_params(trans
).rx_page_order
,
421 IWL_DEBUG_RX(trans
, "r = %d, i = %d, %s, 0x%02x\n", r
,
422 i
, get_cmd_string(pkt
->hdr
.cmd
), pkt
->hdr
.cmd
);
424 len
= le32_to_cpu(pkt
->len_n_flags
) & FH_RSCSR_FRAME_SIZE_MSK
;
425 len
+= sizeof(u32
); /* account for status word */
426 trace_iwlwifi_dev_rx(priv(trans
), pkt
, len
);
428 /* Reclaim a command buffer only if this packet is a response
429 * to a (driver-originated) command.
430 * If the packet (e.g. Rx frame) originated from uCode,
431 * there is no command buffer to reclaim.
432 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
433 * but apparently a few don't get set; catch them here. */
434 reclaim
= !(pkt
->hdr
.sequence
& SEQ_RX_FRAME
) &&
435 (pkt
->hdr
.cmd
!= REPLY_RX_PHY_CMD
) &&
436 (pkt
->hdr
.cmd
!= REPLY_RX
) &&
437 (pkt
->hdr
.cmd
!= REPLY_RX_MPDU_CMD
) &&
438 (pkt
->hdr
.cmd
!= REPLY_COMPRESSED_BA
) &&
439 (pkt
->hdr
.cmd
!= STATISTICS_NOTIFICATION
) &&
440 (pkt
->hdr
.cmd
!= REPLY_TX
);
442 iwl_rx_dispatch(priv(trans
), rxb
);
445 * XXX: After here, we should always check rxb->page
446 * against NULL before touching it or its virtual
447 * memory (pkt). Because some rx_handler might have
448 * already taken or freed the pages.
452 /* Invoke any callbacks, transfer the buffer to caller,
453 * and fire off the (possibly) blocking
454 * iwl_trans_send_cmd()
455 * as we reclaim the driver command queue */
457 iwl_tx_cmd_complete(priv(trans
), rxb
);
459 IWL_WARN(trans
, "Claim null rxb?\n");
462 /* Reuse the page if possible. For notification packets and
463 * SKBs that fail to Rx correctly, add them back into the
464 * rx_free list for reuse later. */
465 spin_lock_irqsave(&rxq
->lock
, flags
);
466 if (rxb
->page
!= NULL
) {
467 rxb
->page_dma
= dma_map_page(bus(trans
)->dev
, rxb
->page
,
469 hw_params(trans
).rx_page_order
,
471 list_add_tail(&rxb
->list
, &rxq
->rx_free
);
474 list_add_tail(&rxb
->list
, &rxq
->rx_used
);
476 spin_unlock_irqrestore(&rxq
->lock
, flags
);
478 i
= (i
+ 1) & RX_QUEUE_MASK
;
479 /* If there are a lot of unused frames,
480 * restock the Rx queue so ucode wont assert. */
485 iwlagn_rx_replenish_now(trans
);
491 /* Backtrack one entry */
494 iwlagn_rx_replenish_now(trans
);
496 iwlagn_rx_queue_restock(trans
);
499 static const char * const desc_lookup_text
[] = {
508 "HW_ERROR_TUNE_LOCK",
509 "HW_ERROR_TEMPERATURE",
513 "NMI_INTERRUPT_HOST",
514 "NMI_INTERRUPT_ACTION_PT",
515 "NMI_INTERRUPT_UNKNOWN",
516 "UCODE_VERSION_MISMATCH",
518 "HW_ERROR_CAL_LOCK_FAIL",
519 "NMI_INTERRUPT_INST_ACTION_PT",
520 "NMI_INTERRUPT_DATA_ACTION_PT",
523 "NMI_INTERRUPT_BREAK_POINT",
530 static struct { char *name
; u8 num
; } advanced_lookup
[] = {
531 { "NMI_INTERRUPT_WDG", 0x34 },
532 { "SYSASSERT", 0x35 },
533 { "UCODE_VERSION_MISMATCH", 0x37 },
534 { "BAD_COMMAND", 0x38 },
535 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
536 { "FATAL_ERROR", 0x3D },
537 { "NMI_TRM_HW_ERR", 0x46 },
538 { "NMI_INTERRUPT_TRM", 0x4C },
539 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
540 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
541 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
542 { "NMI_INTERRUPT_HOST", 0x66 },
543 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
544 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
545 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
546 { "ADVANCED_SYSASSERT", 0 },
549 static const char *desc_lookup(u32 num
)
552 int max
= ARRAY_SIZE(desc_lookup_text
);
555 return desc_lookup_text
[num
];
557 max
= ARRAY_SIZE(advanced_lookup
) - 1;
558 for (i
= 0; i
< max
; i
++) {
559 if (advanced_lookup
[i
].num
== num
)
562 return advanced_lookup
[i
].name
;
565 #define ERROR_START_OFFSET (1 * sizeof(u32))
566 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
568 static void iwl_dump_nic_error_log(struct iwl_priv
*priv
)
571 struct iwl_error_event_table table
;
572 struct iwl_trans
*trans
= trans(priv
);
573 struct iwl_trans_pcie
*trans_pcie
=
574 IWL_TRANS_GET_PCIE_TRANS(trans
);
576 base
= priv
->device_pointers
.error_event_table
;
577 if (priv
->ucode_type
== IWL_UCODE_INIT
) {
579 base
= priv
->init_errlog_ptr
;
582 base
= priv
->inst_errlog_ptr
;
585 if (!iwlagn_hw_valid_rtc_data_addr(base
)) {
587 "Not valid error log pointer 0x%08X for %s uCode\n",
589 (priv
->ucode_type
== IWL_UCODE_INIT
)
594 iwl_read_targ_mem_words(priv
, base
, &table
, sizeof(table
));
596 if (ERROR_START_OFFSET
<= table
.valid
* ERROR_ELEM_SIZE
) {
597 IWL_ERR(priv
, "Start IWL Error Log Dump:\n");
598 IWL_ERR(priv
, "Status: 0x%08lX, count: %d\n",
599 priv
->shrd
->status
, table
.valid
);
602 trans_pcie
->isr_stats
.err_code
= table
.error_id
;
604 trace_iwlwifi_dev_ucode_error(priv
, table
.error_id
, table
.tsf_low
,
605 table
.data1
, table
.data2
, table
.line
,
606 table
.blink1
, table
.blink2
, table
.ilink1
,
607 table
.ilink2
, table
.bcon_time
, table
.gp1
,
608 table
.gp2
, table
.gp3
, table
.ucode_ver
,
609 table
.hw_ver
, table
.brd_ver
);
610 IWL_ERR(priv
, "0x%08X | %-28s\n", table
.error_id
,
611 desc_lookup(table
.error_id
));
612 IWL_ERR(priv
, "0x%08X | uPc\n", table
.pc
);
613 IWL_ERR(priv
, "0x%08X | branchlink1\n", table
.blink1
);
614 IWL_ERR(priv
, "0x%08X | branchlink2\n", table
.blink2
);
615 IWL_ERR(priv
, "0x%08X | interruptlink1\n", table
.ilink1
);
616 IWL_ERR(priv
, "0x%08X | interruptlink2\n", table
.ilink2
);
617 IWL_ERR(priv
, "0x%08X | data1\n", table
.data1
);
618 IWL_ERR(priv
, "0x%08X | data2\n", table
.data2
);
619 IWL_ERR(priv
, "0x%08X | line\n", table
.line
);
620 IWL_ERR(priv
, "0x%08X | beacon time\n", table
.bcon_time
);
621 IWL_ERR(priv
, "0x%08X | tsf low\n", table
.tsf_low
);
622 IWL_ERR(priv
, "0x%08X | tsf hi\n", table
.tsf_hi
);
623 IWL_ERR(priv
, "0x%08X | time gp1\n", table
.gp1
);
624 IWL_ERR(priv
, "0x%08X | time gp2\n", table
.gp2
);
625 IWL_ERR(priv
, "0x%08X | time gp3\n", table
.gp3
);
626 IWL_ERR(priv
, "0x%08X | uCode version\n", table
.ucode_ver
);
627 IWL_ERR(priv
, "0x%08X | hw version\n", table
.hw_ver
);
628 IWL_ERR(priv
, "0x%08X | board version\n", table
.brd_ver
);
629 IWL_ERR(priv
, "0x%08X | hcmd\n", table
.hcmd
);
633 * iwl_irq_handle_error - called for HW or SW error interrupt from card
635 static void iwl_irq_handle_error(struct iwl_priv
*priv
)
637 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
638 if (priv
->cfg
->internal_wimax_coex
&&
639 (!(iwl_read_prph(priv
, APMG_CLK_CTRL_REG
) &
640 APMS_CLK_VAL_MRB_FUNC_MODE
) ||
641 (iwl_read_prph(priv
, APMG_PS_CTRL_REG
) &
642 APMG_PS_CTRL_VAL_RESET_REQ
))) {
644 * Keep the restart process from trying to send host
645 * commands by clearing the ready bit.
647 clear_bit(STATUS_READY
, &priv
->shrd
->status
);
648 clear_bit(STATUS_HCMD_ACTIVE
, &priv
->shrd
->status
);
649 wake_up_interruptible(&priv
->wait_command_queue
);
650 IWL_ERR(priv
, "RF is used by WiMAX\n");
654 IWL_ERR(priv
, "Loaded firmware version: %s\n",
655 priv
->hw
->wiphy
->fw_version
);
657 iwl_dump_nic_error_log(priv
);
659 iwl_dump_fh(priv
, NULL
, false);
660 iwl_dump_nic_event_log(priv
, false, NULL
, false);
661 #ifdef CONFIG_IWLWIFI_DEBUG
662 if (iwl_get_debug_level(priv
->shrd
) & IWL_DL_FW_ERRORS
)
663 iwl_print_rx_config_cmd(priv
,
664 &priv
->contexts
[IWL_RXON_CTX_BSS
]);
667 iwlagn_fw_error(priv
, false);
670 #define EVENT_START_OFFSET (4 * sizeof(u32))
673 * iwl_print_event_log - Dump error event log to syslog
676 static int iwl_print_event_log(struct iwl_priv
*priv
, u32 start_idx
,
677 u32 num_events
, u32 mode
,
678 int pos
, char **buf
, size_t bufsz
)
681 u32 base
; /* SRAM byte address of event log header */
682 u32 event_size
; /* 2 u32s, or 3 u32s if timestamp recorded */
683 u32 ptr
; /* SRAM byte address of log data */
684 u32 ev
, time
, data
; /* event log data */
685 unsigned long reg_flags
;
690 base
= priv
->device_pointers
.log_event_table
;
691 if (priv
->ucode_type
== IWL_UCODE_INIT
) {
693 base
= priv
->init_evtlog_ptr
;
696 base
= priv
->inst_evtlog_ptr
;
700 event_size
= 2 * sizeof(u32
);
702 event_size
= 3 * sizeof(u32
);
704 ptr
= base
+ EVENT_START_OFFSET
+ (start_idx
* event_size
);
706 /* Make sure device is powered up for SRAM reads */
707 spin_lock_irqsave(&priv
->reg_lock
, reg_flags
);
708 iwl_grab_nic_access(priv
);
710 /* Set starting address; reads will auto-increment */
711 iwl_write32(priv
, HBUS_TARG_MEM_RADDR
, ptr
);
714 /* "time" is actually "data" for mode 0 (no timestamp).
715 * place event id # at far right for easier visual parsing. */
716 for (i
= 0; i
< num_events
; i
++) {
717 ev
= iwl_read32(priv
, HBUS_TARG_MEM_RDAT
);
718 time
= iwl_read32(priv
, HBUS_TARG_MEM_RDAT
);
722 pos
+= scnprintf(*buf
+ pos
, bufsz
- pos
,
723 "EVT_LOG:0x%08x:%04u\n",
726 trace_iwlwifi_dev_ucode_event(priv
, 0,
728 IWL_ERR(priv
, "EVT_LOG:0x%08x:%04u\n",
732 data
= iwl_read32(priv
, HBUS_TARG_MEM_RDAT
);
734 pos
+= scnprintf(*buf
+ pos
, bufsz
- pos
,
735 "EVT_LOGT:%010u:0x%08x:%04u\n",
738 IWL_ERR(priv
, "EVT_LOGT:%010u:0x%08x:%04u\n",
740 trace_iwlwifi_dev_ucode_event(priv
, time
,
746 /* Allow device to power down */
747 iwl_release_nic_access(priv
);
748 spin_unlock_irqrestore(&priv
->reg_lock
, reg_flags
);
753 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
755 static int iwl_print_last_event_logs(struct iwl_priv
*priv
, u32 capacity
,
756 u32 num_wraps
, u32 next_entry
,
758 int pos
, char **buf
, size_t bufsz
)
761 * display the newest DEFAULT_LOG_ENTRIES entries
762 * i.e the entries just before the next ont that uCode would fill.
765 if (next_entry
< size
) {
766 pos
= iwl_print_event_log(priv
,
767 capacity
- (size
- next_entry
),
768 size
- next_entry
, mode
,
770 pos
= iwl_print_event_log(priv
, 0,
774 pos
= iwl_print_event_log(priv
, next_entry
- size
,
775 size
, mode
, pos
, buf
, bufsz
);
777 if (next_entry
< size
) {
778 pos
= iwl_print_event_log(priv
, 0, next_entry
,
779 mode
, pos
, buf
, bufsz
);
781 pos
= iwl_print_event_log(priv
, next_entry
- size
,
782 size
, mode
, pos
, buf
, bufsz
);
788 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
790 int iwl_dump_nic_event_log(struct iwl_priv
*priv
, bool full_log
,
791 char **buf
, bool display
)
793 u32 base
; /* SRAM byte address of event log header */
794 u32 capacity
; /* event log capacity in # entries */
795 u32 mode
; /* 0 - no timestamp, 1 - timestamp recorded */
796 u32 num_wraps
; /* # times uCode wrapped to top of log */
797 u32 next_entry
; /* index of next entry to be written by uCode */
798 u32 size
; /* # entries that we'll print */
803 base
= priv
->device_pointers
.log_event_table
;
804 if (priv
->ucode_type
== IWL_UCODE_INIT
) {
805 logsize
= priv
->init_evtlog_size
;
807 base
= priv
->init_evtlog_ptr
;
809 logsize
= priv
->inst_evtlog_size
;
811 base
= priv
->inst_evtlog_ptr
;
814 if (!iwlagn_hw_valid_rtc_data_addr(base
)) {
816 "Invalid event log pointer 0x%08X for %s uCode\n",
818 (priv
->ucode_type
== IWL_UCODE_INIT
)
823 /* event log header */
824 capacity
= iwl_read_targ_mem(priv
, base
);
825 mode
= iwl_read_targ_mem(priv
, base
+ (1 * sizeof(u32
)));
826 num_wraps
= iwl_read_targ_mem(priv
, base
+ (2 * sizeof(u32
)));
827 next_entry
= iwl_read_targ_mem(priv
, base
+ (3 * sizeof(u32
)));
829 if (capacity
> logsize
) {
830 IWL_ERR(priv
, "Log capacity %d is bogus, limit to %d entries\n",
835 if (next_entry
> logsize
) {
836 IWL_ERR(priv
, "Log write index %d is bogus, limit to %d\n",
837 next_entry
, logsize
);
838 next_entry
= logsize
;
841 size
= num_wraps
? capacity
: next_entry
;
843 /* bail out if nothing in log */
845 IWL_ERR(priv
, "Start IWL Event Log Dump: nothing in log\n");
849 /* enable/disable bt channel inhibition */
850 priv
->bt_ch_announce
= iwlagn_mod_params
.bt_ch_announce
;
852 #ifdef CONFIG_IWLWIFI_DEBUG
853 if (!(iwl_get_debug_level(priv
->shrd
) & IWL_DL_FW_ERRORS
) && !full_log
)
854 size
= (size
> DEFAULT_DUMP_EVENT_LOG_ENTRIES
)
855 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES
: size
;
857 size
= (size
> DEFAULT_DUMP_EVENT_LOG_ENTRIES
)
858 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES
: size
;
860 IWL_ERR(priv
, "Start IWL Event Log Dump: display last %u entries\n",
863 #ifdef CONFIG_IWLWIFI_DEBUG
866 bufsz
= capacity
* 48;
869 *buf
= kmalloc(bufsz
, GFP_KERNEL
);
873 if ((iwl_get_debug_level(priv
->shrd
) & IWL_DL_FW_ERRORS
) || full_log
) {
875 * if uCode has wrapped back to top of log,
876 * start at the oldest entry,
877 * i.e the next one that uCode would fill.
880 pos
= iwl_print_event_log(priv
, next_entry
,
881 capacity
- next_entry
, mode
,
883 /* (then/else) start at top of log */
884 pos
= iwl_print_event_log(priv
, 0,
885 next_entry
, mode
, pos
, buf
, bufsz
);
887 pos
= iwl_print_last_event_logs(priv
, capacity
, num_wraps
,
888 next_entry
, size
, mode
,
891 pos
= iwl_print_last_event_logs(priv
, capacity
, num_wraps
,
892 next_entry
, size
, mode
,
898 /* tasklet for iwlagn interrupt */
899 void iwl_irq_tasklet(struct iwl_trans
*trans
)
905 #ifdef CONFIG_IWLWIFI_DEBUG
909 struct iwl_trans_pcie
*trans_pcie
=
910 IWL_TRANS_GET_PCIE_TRANS(trans
);
911 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
914 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
916 /* Ack/clear/reset pending uCode interrupts.
917 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
919 /* There is a hardware bug in the interrupt mask function that some
920 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
921 * they are disabled in the CSR_INT_MASK register. Furthermore the
922 * ICT interrupt handling mechanism has another bug that might cause
923 * these unmasked interrupts fail to be detected. We workaround the
924 * hardware bugs here by ACKing all the possible interrupts so that
925 * interrupt coalescing can still be achieved.
927 iwl_write32(priv(trans
), CSR_INT
,
928 trans_pcie
->inta
| ~trans_pcie
->inta_mask
);
930 inta
= trans_pcie
->inta
;
932 #ifdef CONFIG_IWLWIFI_DEBUG
933 if (iwl_get_debug_level(trans
->shrd
) & IWL_DL_ISR
) {
935 inta_mask
= iwl_read32(priv(trans
), CSR_INT_MASK
);
936 IWL_DEBUG_ISR(trans
, "inta 0x%08x, enabled 0x%08x\n ",
941 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
943 /* saved interrupt in inta variable now we can reset trans_pcie->inta */
944 trans_pcie
->inta
= 0;
946 /* Now service all interrupt bits discovered above. */
947 if (inta
& CSR_INT_BIT_HW_ERR
) {
948 IWL_ERR(trans
, "Hardware error detected. Restarting.\n");
950 /* Tell the device to stop sending interrupts */
951 iwl_disable_interrupts(trans
);
954 iwl_irq_handle_error(priv(trans
));
956 handled
|= CSR_INT_BIT_HW_ERR
;
961 #ifdef CONFIG_IWLWIFI_DEBUG
962 if (iwl_get_debug_level(trans
->shrd
) & (IWL_DL_ISR
)) {
963 /* NIC fires this, but we don't use it, redundant with WAKEUP */
964 if (inta
& CSR_INT_BIT_SCD
) {
965 IWL_DEBUG_ISR(trans
, "Scheduler finished to transmit "
966 "the frame/frames.\n");
970 /* Alive notification via Rx interrupt will do the real work */
971 if (inta
& CSR_INT_BIT_ALIVE
) {
972 IWL_DEBUG_ISR(trans
, "Alive interrupt\n");
977 /* Safely ignore these bits for debug checks below */
978 inta
&= ~(CSR_INT_BIT_SCD
| CSR_INT_BIT_ALIVE
);
980 /* HW RF KILL switch toggled */
981 if (inta
& CSR_INT_BIT_RF_KILL
) {
983 if (!(iwl_read32(priv(trans
), CSR_GP_CNTRL
) &
984 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW
))
987 IWL_WARN(trans
, "RF_KILL bit toggled to %s.\n",
988 hw_rf_kill
? "disable radio" : "enable radio");
992 /* driver only loads ucode once setting the interface up.
993 * the driver allows loading the ucode even if the radio
994 * is killed. Hence update the killswitch state here. The
995 * rfkill handler will care about restarting if needed.
997 if (!test_bit(STATUS_ALIVE
, &trans
->shrd
->status
)) {
999 set_bit(STATUS_RF_KILL_HW
,
1000 &trans
->shrd
->status
);
1002 clear_bit(STATUS_RF_KILL_HW
,
1003 &trans
->shrd
->status
);
1004 wiphy_rfkill_set_hw_state(priv(trans
)->hw
->wiphy
,
1008 handled
|= CSR_INT_BIT_RF_KILL
;
1011 /* Chip got too hot and stopped itself */
1012 if (inta
& CSR_INT_BIT_CT_KILL
) {
1013 IWL_ERR(trans
, "Microcode CT kill error detected.\n");
1014 isr_stats
->ctkill
++;
1015 handled
|= CSR_INT_BIT_CT_KILL
;
1018 /* Error detected by uCode */
1019 if (inta
& CSR_INT_BIT_SW_ERR
) {
1020 IWL_ERR(trans
, "Microcode SW error detected. "
1021 " Restarting 0x%X.\n", inta
);
1023 iwl_irq_handle_error(priv(trans
));
1024 handled
|= CSR_INT_BIT_SW_ERR
;
1027 /* uCode wakes up after power-down sleep */
1028 if (inta
& CSR_INT_BIT_WAKEUP
) {
1029 IWL_DEBUG_ISR(trans
, "Wakeup interrupt\n");
1030 iwl_rx_queue_update_write_ptr(trans
, &trans_pcie
->rxq
);
1031 for (i
= 0; i
< hw_params(trans
).max_txq_num
; i
++)
1032 iwl_txq_update_write_ptr(priv(trans
),
1033 &priv(trans
)->txq
[i
]);
1035 isr_stats
->wakeup
++;
1037 handled
|= CSR_INT_BIT_WAKEUP
;
1040 /* All uCode command responses, including Tx command responses,
1041 * Rx "responses" (frame-received notification), and other
1042 * notifications from uCode come through here*/
1043 if (inta
& (CSR_INT_BIT_FH_RX
| CSR_INT_BIT_SW_RX
|
1044 CSR_INT_BIT_RX_PERIODIC
)) {
1045 IWL_DEBUG_ISR(trans
, "Rx interrupt\n");
1046 if (inta
& (CSR_INT_BIT_FH_RX
| CSR_INT_BIT_SW_RX
)) {
1047 handled
|= (CSR_INT_BIT_FH_RX
| CSR_INT_BIT_SW_RX
);
1048 iwl_write32(priv(trans
), CSR_FH_INT_STATUS
,
1049 CSR_FH_INT_RX_MASK
);
1051 if (inta
& CSR_INT_BIT_RX_PERIODIC
) {
1052 handled
|= CSR_INT_BIT_RX_PERIODIC
;
1053 iwl_write32(priv(trans
),
1054 CSR_INT
, CSR_INT_BIT_RX_PERIODIC
);
1056 /* Sending RX interrupt require many steps to be done in the
1058 * 1- write interrupt to current index in ICT table.
1060 * 3- update RX shared data to indicate last write index.
1061 * 4- send interrupt.
1062 * This could lead to RX race, driver could receive RX interrupt
1063 * but the shared data changes does not reflect this;
1064 * periodic interrupt will detect any dangling Rx activity.
1067 /* Disable periodic interrupt; we use it as just a one-shot. */
1068 iwl_write8(priv(trans
), CSR_INT_PERIODIC_REG
,
1069 CSR_INT_PERIODIC_DIS
);
1070 iwl_rx_handle(trans
);
1073 * Enable periodic interrupt in 8 msec only if we received
1074 * real RX interrupt (instead of just periodic int), to catch
1075 * any dangling Rx interrupt. If it was just the periodic
1076 * interrupt, there was no dangling Rx activity, and no need
1077 * to extend the periodic interrupt; one-shot is enough.
1079 if (inta
& (CSR_INT_BIT_FH_RX
| CSR_INT_BIT_SW_RX
))
1080 iwl_write8(priv(trans
), CSR_INT_PERIODIC_REG
,
1081 CSR_INT_PERIODIC_ENA
);
1086 /* This "Tx" DMA channel is used only for loading uCode */
1087 if (inta
& CSR_INT_BIT_FH_TX
) {
1088 iwl_write32(priv(trans
), CSR_FH_INT_STATUS
, CSR_FH_INT_TX_MASK
);
1089 IWL_DEBUG_ISR(trans
, "uCode load interrupt\n");
1091 handled
|= CSR_INT_BIT_FH_TX
;
1092 /* Wake up uCode load routine, now that load is complete */
1093 priv(trans
)->ucode_write_complete
= 1;
1094 wake_up_interruptible(&priv(trans
)->wait_command_queue
);
1097 if (inta
& ~handled
) {
1098 IWL_ERR(trans
, "Unhandled INTA bits 0x%08x\n", inta
& ~handled
);
1099 isr_stats
->unhandled
++;
1102 if (inta
& ~(trans_pcie
->inta_mask
)) {
1103 IWL_WARN(trans
, "Disabled INTA bits 0x%08x were pending\n",
1104 inta
& ~trans_pcie
->inta_mask
);
1107 /* Re-enable all interrupts */
1108 /* only Re-enable if disabled by irq */
1109 if (test_bit(STATUS_INT_ENABLED
, &trans
->shrd
->status
))
1110 iwl_enable_interrupts(trans
);
1111 /* Re-enable RF_KILL if it occurred */
1112 else if (handled
& CSR_INT_BIT_RF_KILL
)
1113 iwl_enable_rfkill_int(priv(trans
));
1116 /******************************************************************************
1120 ******************************************************************************/
1121 #define ICT_COUNT (PAGE_SIZE/sizeof(u32))
1123 /* Free dram table */
1124 void iwl_free_isr_ict(struct iwl_trans
*trans
)
1126 struct iwl_trans_pcie
*trans_pcie
=
1127 IWL_TRANS_GET_PCIE_TRANS(trans
);
1129 if (trans_pcie
->ict_tbl_vir
) {
1130 dma_free_coherent(bus(trans
)->dev
,
1131 (sizeof(u32
) * ICT_COUNT
) + PAGE_SIZE
,
1132 trans_pcie
->ict_tbl_vir
,
1133 trans_pcie
->ict_tbl_dma
);
1134 trans_pcie
->ict_tbl_vir
= NULL
;
1135 memset(&trans_pcie
->ict_tbl_dma
, 0,
1136 sizeof(trans_pcie
->ict_tbl_dma
));
1137 memset(&trans_pcie
->aligned_ict_tbl_dma
, 0,
1138 sizeof(trans_pcie
->aligned_ict_tbl_dma
));
1143 /* allocate dram shared table it is a PAGE_SIZE aligned
1144 * also reset all data related to ICT table interrupt.
1146 int iwl_alloc_isr_ict(struct iwl_trans
*trans
)
1148 struct iwl_trans_pcie
*trans_pcie
=
1149 IWL_TRANS_GET_PCIE_TRANS(trans
);
1151 /* allocate shrared data table */
1152 trans_pcie
->ict_tbl_vir
=
1153 dma_alloc_coherent(bus(trans
)->dev
,
1154 (sizeof(u32
) * ICT_COUNT
) + PAGE_SIZE
,
1155 &trans_pcie
->ict_tbl_dma
, GFP_KERNEL
);
1156 if (!trans_pcie
->ict_tbl_vir
)
1159 /* align table to PAGE_SIZE boundary */
1160 trans_pcie
->aligned_ict_tbl_dma
=
1161 ALIGN(trans_pcie
->ict_tbl_dma
, PAGE_SIZE
);
1163 IWL_DEBUG_ISR(trans
, "ict dma addr %Lx dma aligned %Lx diff %d\n",
1164 (unsigned long long)trans_pcie
->ict_tbl_dma
,
1165 (unsigned long long)trans_pcie
->aligned_ict_tbl_dma
,
1166 (int)(trans_pcie
->aligned_ict_tbl_dma
-
1167 trans_pcie
->ict_tbl_dma
));
1169 trans_pcie
->ict_tbl
= trans_pcie
->ict_tbl_vir
+
1170 (trans_pcie
->aligned_ict_tbl_dma
-
1171 trans_pcie
->ict_tbl_dma
);
1173 IWL_DEBUG_ISR(trans
, "ict vir addr %p vir aligned %p diff %d\n",
1174 trans_pcie
->ict_tbl
, trans_pcie
->ict_tbl_vir
,
1175 (int)(trans_pcie
->aligned_ict_tbl_dma
-
1176 trans_pcie
->ict_tbl_dma
));
1178 /* reset table and index to all 0 */
1179 memset(trans_pcie
->ict_tbl_vir
, 0,
1180 (sizeof(u32
) * ICT_COUNT
) + PAGE_SIZE
);
1181 trans_pcie
->ict_index
= 0;
1183 /* add periodic RX interrupt */
1184 trans_pcie
->inta_mask
|= CSR_INT_BIT_RX_PERIODIC
;
1188 /* Device is going up inform it about using ICT interrupt table,
1189 * also we need to tell the driver to start using ICT interrupt.
1191 int iwl_reset_ict(struct iwl_priv
*priv
)
1194 unsigned long flags
;
1195 struct iwl_trans
*trans
= trans(priv
);
1196 struct iwl_trans_pcie
*trans_pcie
=
1197 IWL_TRANS_GET_PCIE_TRANS(trans
);
1199 if (!trans_pcie
->ict_tbl_vir
)
1202 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
1203 iwl_disable_interrupts(trans
);
1205 memset(&trans_pcie
->ict_tbl
[0], 0, sizeof(u32
) * ICT_COUNT
);
1207 val
= trans_pcie
->aligned_ict_tbl_dma
>> PAGE_SHIFT
;
1209 val
|= CSR_DRAM_INT_TBL_ENABLE
;
1210 val
|= CSR_DRAM_INIT_TBL_WRAP_CHECK
;
1212 IWL_DEBUG_ISR(trans
, "CSR_DRAM_INT_TBL_REG =0x%X "
1213 "aligned dma address %Lx\n",
1215 (unsigned long long)trans_pcie
->aligned_ict_tbl_dma
);
1217 iwl_write32(priv(trans
), CSR_DRAM_INT_TBL_REG
, val
);
1218 trans_pcie
->use_ict
= true;
1219 trans_pcie
->ict_index
= 0;
1220 iwl_write32(priv(trans
), CSR_INT
, trans_pcie
->inta_mask
);
1221 iwl_enable_interrupts(trans
);
1222 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
1227 /* Device is going down disable ict interrupt usage */
1228 void iwl_disable_ict(struct iwl_trans
*trans
)
1230 struct iwl_trans_pcie
*trans_pcie
=
1231 IWL_TRANS_GET_PCIE_TRANS(trans
);
1233 unsigned long flags
;
1235 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
1236 trans_pcie
->use_ict
= false;
1237 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
1240 static irqreturn_t
iwl_isr(int irq
, void *data
)
1242 struct iwl_trans
*trans
= data
;
1243 struct iwl_trans_pcie
*trans_pcie
;
1244 u32 inta
, inta_mask
;
1245 unsigned long flags
;
1246 #ifdef CONFIG_IWLWIFI_DEBUG
1252 trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1254 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
1256 /* Disable (but don't clear!) interrupts here to avoid
1257 * back-to-back ISRs and sporadic interrupts from our NIC.
1258 * If we have something to service, the tasklet will re-enable ints.
1259 * If we *don't* have something, we'll re-enable before leaving here. */
1260 inta_mask
= iwl_read32(priv(trans
), CSR_INT_MASK
); /* just for debug */
1261 iwl_write32(priv(trans
), CSR_INT_MASK
, 0x00000000);
1263 /* Discover which interrupts are active/pending */
1264 inta
= iwl_read32(priv(trans
), CSR_INT
);
1266 /* Ignore interrupt if there's nothing in NIC to service.
1267 * This may be due to IRQ shared with another device,
1268 * or due to sporadic interrupts thrown from our NIC. */
1270 IWL_DEBUG_ISR(trans
, "Ignore interrupt, inta == 0\n");
1274 if ((inta
== 0xFFFFFFFF) || ((inta
& 0xFFFFFFF0) == 0xa5a5a5a0)) {
1275 /* Hardware disappeared. It might have already raised
1277 IWL_WARN(trans
, "HARDWARE GONE?? INTA == 0x%08x\n", inta
);
1281 #ifdef CONFIG_IWLWIFI_DEBUG
1282 if (iwl_get_debug_level(trans
->shrd
) & (IWL_DL_ISR
)) {
1283 inta_fh
= iwl_read32(priv(trans
), CSR_FH_INT_STATUS
);
1284 IWL_DEBUG_ISR(trans
, "ISR inta 0x%08x, enabled 0x%08x, "
1285 "fh 0x%08x\n", inta
, inta_mask
, inta_fh
);
1289 trans_pcie
->inta
|= inta
;
1290 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1292 tasklet_schedule(&trans_pcie
->irq_tasklet
);
1293 else if (test_bit(STATUS_INT_ENABLED
, &trans
->shrd
->status
) &&
1295 iwl_enable_interrupts(trans
);
1298 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
1302 /* re-enable interrupts here since we don't have anything to service. */
1303 /* only Re-enable if disabled by irq and no schedules tasklet. */
1304 if (test_bit(STATUS_INT_ENABLED
, &trans
->shrd
->status
) &&
1306 iwl_enable_interrupts(trans
);
1308 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
1312 /* interrupt handler using ict table, with this interrupt driver will
1313 * stop using INTA register to get device's interrupt, reading this register
1314 * is expensive, device will write interrupts in ICT dram table, increment
1315 * index then will fire interrupt to driver, driver will OR all ICT table
1316 * entries from current index up to table entry with 0 value. the result is
1317 * the interrupt we need to service, driver will set the entries back to 0 and
1320 irqreturn_t
iwl_isr_ict(int irq
, void *data
)
1322 struct iwl_trans
*trans
= data
;
1323 struct iwl_trans_pcie
*trans_pcie
;
1324 u32 inta
, inta_mask
;
1326 unsigned long flags
;
1331 trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1333 /* dram interrupt table not set yet,
1334 * use legacy interrupt.
1336 if (!trans_pcie
->use_ict
)
1337 return iwl_isr(irq
, data
);
1339 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
1341 /* Disable (but don't clear!) interrupts here to avoid
1342 * back-to-back ISRs and sporadic interrupts from our NIC.
1343 * If we have something to service, the tasklet will re-enable ints.
1344 * If we *don't* have something, we'll re-enable before leaving here.
1346 inta_mask
= iwl_read32(priv(trans
), CSR_INT_MASK
); /* just for debug */
1347 iwl_write32(priv(trans
), CSR_INT_MASK
, 0x00000000);
1350 /* Ignore interrupt if there's nothing in NIC to service.
1351 * This may be due to IRQ shared with another device,
1352 * or due to sporadic interrupts thrown from our NIC. */
1353 if (!trans_pcie
->ict_tbl
[trans_pcie
->ict_index
]) {
1354 IWL_DEBUG_ISR(trans
, "Ignore interrupt, inta == 0\n");
1358 /* read all entries that not 0 start with ict_index */
1359 while (trans_pcie
->ict_tbl
[trans_pcie
->ict_index
]) {
1361 val
|= le32_to_cpu(trans_pcie
->ict_tbl
[trans_pcie
->ict_index
]);
1362 IWL_DEBUG_ISR(trans
, "ICT index %d value 0x%08X\n",
1363 trans_pcie
->ict_index
,
1365 trans_pcie
->ict_tbl
[trans_pcie
->ict_index
]));
1366 trans_pcie
->ict_tbl
[trans_pcie
->ict_index
] = 0;
1367 trans_pcie
->ict_index
=
1368 iwl_queue_inc_wrap(trans_pcie
->ict_index
, ICT_COUNT
);
1372 /* We should not get this value, just ignore it. */
1373 if (val
== 0xffffffff)
1377 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1378 * (bit 15 before shifting it to 31) to clear when using interrupt
1379 * coalescing. fortunately, bits 18 and 19 stay set when this happens
1380 * so we use them to decide on the real state of the Rx bit.
1381 * In order words, bit 15 is set if bit 18 or bit 19 are set.
1386 inta
= (0xff & val
) | ((0xff00 & val
) << 16);
1387 IWL_DEBUG_ISR(trans
, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1388 inta
, inta_mask
, val
);
1390 inta
&= trans_pcie
->inta_mask
;
1391 trans_pcie
->inta
|= inta
;
1393 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1395 tasklet_schedule(&trans_pcie
->irq_tasklet
);
1396 else if (test_bit(STATUS_INT_ENABLED
, &trans
->shrd
->status
) &&
1397 !trans_pcie
->inta
) {
1398 /* Allow interrupt if was disabled by this handler and
1399 * no tasklet was schedules, We should not enable interrupt,
1400 * tasklet will enable it.
1402 iwl_enable_interrupts(trans
);
1405 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
1409 /* re-enable interrupts here since we don't have anything to service.
1410 * only Re-enable if disabled by irq.
1412 if (test_bit(STATUS_INT_ENABLED
, &trans
->shrd
->status
) &&
1414 iwl_enable_interrupts(trans
);
1416 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);