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[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-trans-tx-pcie.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/slab.h>
31 #include <linux/sched.h>
32 #include <net/mac80211.h>
33
34 #include "iwl-agn.h"
35 #include "iwl-dev.h"
36 #include "iwl-core.h"
37 #include "iwl-io.h"
38 #include "iwl-helpers.h"
39 #include "iwl-trans-int-pcie.h"
40
41 /**
42 * iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
43 */
44 void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
45 struct iwl_tx_queue *txq,
46 u16 byte_cnt)
47 {
48 struct iwlagn_scd_bc_tbl *scd_bc_tbl;
49 struct iwl_trans_pcie *trans_pcie =
50 IWL_TRANS_GET_PCIE_TRANS(trans);
51 int write_ptr = txq->q.write_ptr;
52 int txq_id = txq->q.id;
53 u8 sec_ctl = 0;
54 u8 sta_id = 0;
55 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
56 __le16 bc_ent;
57
58 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
59
60 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
61
62 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
63 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
64
65 switch (sec_ctl & TX_CMD_SEC_MSK) {
66 case TX_CMD_SEC_CCM:
67 len += CCMP_MIC_LEN;
68 break;
69 case TX_CMD_SEC_TKIP:
70 len += TKIP_ICV_LEN;
71 break;
72 case TX_CMD_SEC_WEP:
73 len += WEP_IV_LEN + WEP_ICV_LEN;
74 break;
75 }
76
77 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
78
79 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
80
81 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
82 scd_bc_tbl[txq_id].
83 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
84 }
85
86 /**
87 * iwl_txq_update_write_ptr - Send new write index to hardware
88 */
89 void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
90 {
91 u32 reg = 0;
92 int txq_id = txq->q.id;
93
94 if (txq->need_update == 0)
95 return;
96
97 if (priv->cfg->base_params->shadow_reg_enable) {
98 /* shadow register enabled */
99 iwl_write32(bus(priv), HBUS_TARG_WRPTR,
100 txq->q.write_ptr | (txq_id << 8));
101 } else {
102 /* if we're trying to save power */
103 if (test_bit(STATUS_POWER_PMI, &priv->shrd->status)) {
104 /* wake up nic if it's powered down ...
105 * uCode will wake up, and interrupt us again, so next
106 * time we'll skip this part. */
107 reg = iwl_read32(bus(priv), CSR_UCODE_DRV_GP1);
108
109 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
110 IWL_DEBUG_INFO(priv,
111 "Tx queue %d requesting wakeup,"
112 " GP1 = 0x%x\n", txq_id, reg);
113 iwl_set_bit(bus(priv), CSR_GP_CNTRL,
114 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
115 return;
116 }
117
118 iwl_write_direct32(bus(priv), HBUS_TARG_WRPTR,
119 txq->q.write_ptr | (txq_id << 8));
120
121 /*
122 * else not in power-save mode,
123 * uCode will never sleep when we're
124 * trying to tx (during RFKILL, we're not trying to tx).
125 */
126 } else
127 iwl_write32(bus(priv), HBUS_TARG_WRPTR,
128 txq->q.write_ptr | (txq_id << 8));
129 }
130 txq->need_update = 0;
131 }
132
133 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
134 {
135 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
136
137 dma_addr_t addr = get_unaligned_le32(&tb->lo);
138 if (sizeof(dma_addr_t) > sizeof(u32))
139 addr |=
140 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
141
142 return addr;
143 }
144
145 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
146 {
147 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
148
149 return le16_to_cpu(tb->hi_n_len) >> 4;
150 }
151
152 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
153 dma_addr_t addr, u16 len)
154 {
155 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
156 u16 hi_n_len = len << 4;
157
158 put_unaligned_le32(addr, &tb->lo);
159 if (sizeof(dma_addr_t) > sizeof(u32))
160 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
161
162 tb->hi_n_len = cpu_to_le16(hi_n_len);
163
164 tfd->num_tbs = idx + 1;
165 }
166
167 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
168 {
169 return tfd->num_tbs & 0x1f;
170 }
171
172 static void iwlagn_unmap_tfd(struct iwl_trans *trans, struct iwl_cmd_meta *meta,
173 struct iwl_tfd *tfd, enum dma_data_direction dma_dir)
174 {
175 int i;
176 int num_tbs;
177
178 /* Sanity check on number of chunks */
179 num_tbs = iwl_tfd_get_num_tbs(tfd);
180
181 if (num_tbs >= IWL_NUM_OF_TBS) {
182 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
183 /* @todo issue fatal error, it is quite serious situation */
184 return;
185 }
186
187 /* Unmap tx_cmd */
188 if (num_tbs)
189 dma_unmap_single(bus(trans)->dev,
190 dma_unmap_addr(meta, mapping),
191 dma_unmap_len(meta, len),
192 DMA_BIDIRECTIONAL);
193
194 /* Unmap chunks, if any. */
195 for (i = 1; i < num_tbs; i++)
196 dma_unmap_single(bus(trans)->dev, iwl_tfd_tb_get_addr(tfd, i),
197 iwl_tfd_tb_get_len(tfd, i), dma_dir);
198 }
199
200 /**
201 * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
202 * @trans - transport private data
203 * @txq - tx queue
204 * @index - the index of the TFD to be freed
205 *
206 * Does NOT advance any TFD circular buffer read/write indexes
207 * Does NOT free the TFD itself (which is within circular buffer)
208 */
209 void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq,
210 int index)
211 {
212 struct iwl_tfd *tfd_tmp = txq->tfds;
213
214 iwlagn_unmap_tfd(trans, &txq->meta[index], &tfd_tmp[index],
215 DMA_TO_DEVICE);
216
217 /* free SKB */
218 if (txq->txb) {
219 struct sk_buff *skb;
220
221 skb = txq->txb[index].skb;
222
223 /* can be called from irqs-disabled context */
224 if (skb) {
225 dev_kfree_skb_any(skb);
226 txq->txb[index].skb = NULL;
227 }
228 }
229 }
230
231 int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
232 struct iwl_tx_queue *txq,
233 dma_addr_t addr, u16 len,
234 u8 reset)
235 {
236 struct iwl_queue *q;
237 struct iwl_tfd *tfd, *tfd_tmp;
238 u32 num_tbs;
239
240 q = &txq->q;
241 tfd_tmp = txq->tfds;
242 tfd = &tfd_tmp[q->write_ptr];
243
244 if (reset)
245 memset(tfd, 0, sizeof(*tfd));
246
247 num_tbs = iwl_tfd_get_num_tbs(tfd);
248
249 /* Each TFD can point to a maximum 20 Tx buffers */
250 if (num_tbs >= IWL_NUM_OF_TBS) {
251 IWL_ERR(trans, "Error can not send more than %d chunks\n",
252 IWL_NUM_OF_TBS);
253 return -EINVAL;
254 }
255
256 if (WARN_ON(addr & ~DMA_BIT_MASK(36)))
257 return -EINVAL;
258
259 if (unlikely(addr & ~IWL_TX_DMA_MASK))
260 IWL_ERR(trans, "Unaligned address = %llx\n",
261 (unsigned long long)addr);
262
263 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
264
265 return 0;
266 }
267
268 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
269 * DMA services
270 *
271 * Theory of operation
272 *
273 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
274 * of buffer descriptors, each of which points to one or more data buffers for
275 * the device to read from or fill. Driver and device exchange status of each
276 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
277 * entries in each circular buffer, to protect against confusing empty and full
278 * queue states.
279 *
280 * The device reads or writes the data in the queues via the device's several
281 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
282 *
283 * For Tx queue, there are low mark and high mark limits. If, after queuing
284 * the packet for Tx, free space become < low mark, Tx queue stopped. When
285 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
286 * Tx queue resumed.
287 *
288 ***************************************************/
289
290 int iwl_queue_space(const struct iwl_queue *q)
291 {
292 int s = q->read_ptr - q->write_ptr;
293
294 if (q->read_ptr > q->write_ptr)
295 s -= q->n_bd;
296
297 if (s <= 0)
298 s += q->n_window;
299 /* keep some reserve to not confuse empty and full situations */
300 s -= 2;
301 if (s < 0)
302 s = 0;
303 return s;
304 }
305
306 /**
307 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
308 */
309 int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id)
310 {
311 q->n_bd = count;
312 q->n_window = slots_num;
313 q->id = id;
314
315 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
316 * and iwl_queue_dec_wrap are broken. */
317 if (WARN_ON(!is_power_of_2(count)))
318 return -EINVAL;
319
320 /* slots_num must be power-of-two size, otherwise
321 * get_cmd_index is broken. */
322 if (WARN_ON(!is_power_of_2(slots_num)))
323 return -EINVAL;
324
325 q->low_mark = q->n_window / 4;
326 if (q->low_mark < 4)
327 q->low_mark = 4;
328
329 q->high_mark = q->n_window / 8;
330 if (q->high_mark < 2)
331 q->high_mark = 2;
332
333 q->write_ptr = q->read_ptr = 0;
334
335 return 0;
336 }
337
338 static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
339 struct iwl_tx_queue *txq)
340 {
341 struct iwl_trans_pcie *trans_pcie =
342 IWL_TRANS_GET_PCIE_TRANS(trans);
343 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
344 int txq_id = txq->q.id;
345 int read_ptr = txq->q.read_ptr;
346 u8 sta_id = 0;
347 __le16 bc_ent;
348
349 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
350
351 if (txq_id != trans->shrd->cmd_queue)
352 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
353
354 bc_ent = cpu_to_le16(1 | (sta_id << 12));
355 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
356
357 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
358 scd_bc_tbl[txq_id].
359 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
360 }
361
362 static int iwlagn_tx_queue_set_q2ratid(struct iwl_trans *trans, u16 ra_tid,
363 u16 txq_id)
364 {
365 u32 tbl_dw_addr;
366 u32 tbl_dw;
367 u16 scd_q2ratid;
368
369 struct iwl_trans_pcie *trans_pcie =
370 IWL_TRANS_GET_PCIE_TRANS(trans);
371
372 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
373
374 tbl_dw_addr = trans_pcie->scd_base_addr +
375 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
376
377 tbl_dw = iwl_read_targ_mem(bus(trans), tbl_dw_addr);
378
379 if (txq_id & 0x1)
380 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
381 else
382 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
383
384 iwl_write_targ_mem(bus(trans), tbl_dw_addr, tbl_dw);
385
386 return 0;
387 }
388
389 static void iwlagn_tx_queue_stop_scheduler(struct iwl_trans *trans, u16 txq_id)
390 {
391 /* Simply stop the queue, but don't change any configuration;
392 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
393 iwl_write_prph(bus(trans),
394 SCD_QUEUE_STATUS_BITS(txq_id),
395 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
396 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
397 }
398
399 void iwl_trans_set_wr_ptrs(struct iwl_trans *trans,
400 int txq_id, u32 index)
401 {
402 iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR,
403 (index & 0xff) | (txq_id << 8));
404 iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(txq_id), index);
405 }
406
407 void iwl_trans_tx_queue_set_status(struct iwl_priv *priv,
408 struct iwl_tx_queue *txq,
409 int tx_fifo_id, int scd_retry)
410 {
411 int txq_id = txq->q.id;
412 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
413
414 iwl_write_prph(bus(priv), SCD_QUEUE_STATUS_BITS(txq_id),
415 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
416 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
417 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
418 SCD_QUEUE_STTS_REG_MSK);
419
420 txq->sched_retry = scd_retry;
421
422 IWL_DEBUG_INFO(priv, "%s %s Queue %d on FIFO %d\n",
423 active ? "Activate" : "Deactivate",
424 scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
425 }
426
427 void iwl_trans_pcie_txq_agg_setup(struct iwl_priv *priv, int sta_id, int tid,
428 int frame_limit)
429 {
430 int tx_fifo, txq_id, ssn_idx;
431 u16 ra_tid;
432 unsigned long flags;
433 struct iwl_tid_data *tid_data;
434
435 struct iwl_trans *trans = trans(priv);
436 struct iwl_trans_pcie *trans_pcie =
437 IWL_TRANS_GET_PCIE_TRANS(trans);
438
439 if (WARN_ON(sta_id == IWL_INVALID_STATION))
440 return;
441 if (WARN_ON(tid >= MAX_TID_COUNT))
442 return;
443
444 spin_lock_irqsave(&priv->shrd->sta_lock, flags);
445 tid_data = &priv->stations[sta_id].tid[tid];
446 ssn_idx = SEQ_TO_SN(tid_data->seq_number);
447 txq_id = tid_data->agg.txq_id;
448 tx_fifo = tid_data->agg.tx_fifo;
449 spin_unlock_irqrestore(&priv->shrd->sta_lock, flags);
450
451 ra_tid = BUILD_RAxTID(sta_id, tid);
452
453 spin_lock_irqsave(&priv->shrd->lock, flags);
454
455 /* Stop this Tx queue before configuring it */
456 iwlagn_tx_queue_stop_scheduler(trans, txq_id);
457
458 /* Map receiver-address / traffic-ID to this queue */
459 iwlagn_tx_queue_set_q2ratid(trans, ra_tid, txq_id);
460
461 /* Set this queue as a chain-building queue */
462 iwl_set_bits_prph(bus(priv), SCD_QUEUECHAIN_SEL, (1<<txq_id));
463
464 /* enable aggregations for the queue */
465 iwl_set_bits_prph(bus(priv), SCD_AGGR_SEL, (1<<txq_id));
466
467 /* Place first TFD at index corresponding to start sequence number.
468 * Assumes that ssn_idx is valid (!= 0xFFF) */
469 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
470 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
471 iwl_trans_set_wr_ptrs(trans, txq_id, ssn_idx);
472
473 /* Set up Tx window size and frame limit for this queue */
474 iwl_write_targ_mem(bus(priv), trans_pcie->scd_base_addr +
475 SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
476 sizeof(u32),
477 ((frame_limit <<
478 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
479 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
480 ((frame_limit <<
481 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
482 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
483
484 iwl_set_bits_prph(bus(priv), SCD_INTERRUPT_MASK, (1 << txq_id));
485
486 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
487 iwl_trans_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
488
489 priv->txq[txq_id].sta_id = sta_id;
490 priv->txq[txq_id].tid = tid;
491
492 spin_unlock_irqrestore(&priv->shrd->lock, flags);
493 }
494
495 int iwl_trans_pcie_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
496 u16 ssn_idx, u8 tx_fifo)
497 {
498 struct iwl_trans *trans = trans(priv);
499 if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
500 (IWLAGN_FIRST_AMPDU_QUEUE +
501 priv->cfg->base_params->num_of_ampdu_queues <= txq_id)) {
502 IWL_ERR(priv,
503 "queue number out of range: %d, must be %d to %d\n",
504 txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
505 IWLAGN_FIRST_AMPDU_QUEUE +
506 priv->cfg->base_params->num_of_ampdu_queues - 1);
507 return -EINVAL;
508 }
509
510 iwlagn_tx_queue_stop_scheduler(trans, txq_id);
511
512 iwl_clear_bits_prph(bus(priv), SCD_AGGR_SEL, (1 << txq_id));
513
514 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
515 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
516 /* supposes that ssn_idx is valid (!= 0xFFF) */
517 iwl_trans_set_wr_ptrs(trans, txq_id, ssn_idx);
518
519 iwl_clear_bits_prph(bus(priv), SCD_INTERRUPT_MASK, (1 << txq_id));
520 iwl_txq_ctx_deactivate(priv, txq_id);
521 iwl_trans_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
522
523 return 0;
524 }
525
526 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
527
528 /**
529 * iwl_enqueue_hcmd - enqueue a uCode command
530 * @priv: device private data point
531 * @cmd: a point to the ucode command structure
532 *
533 * The function returns < 0 values to indicate the operation is
534 * failed. On success, it turns the index (> 0) of command in the
535 * command queue.
536 */
537 static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
538 {
539 struct iwl_priv *priv = priv(trans);
540 struct iwl_tx_queue *txq = &priv->txq[priv->shrd->cmd_queue];
541 struct iwl_queue *q = &txq->q;
542 struct iwl_device_cmd *out_cmd;
543 struct iwl_cmd_meta *out_meta;
544 dma_addr_t phys_addr;
545 unsigned long flags;
546 u32 idx;
547 u16 copy_size, cmd_size;
548 bool is_ct_kill = false;
549 bool had_nocopy = false;
550 int i;
551 u8 *cmd_dest;
552 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
553 const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {};
554 int trace_lens[IWL_MAX_CMD_TFDS + 1] = {};
555 int trace_idx;
556 #endif
557
558 if (test_bit(STATUS_FW_ERROR, &trans->shrd->status)) {
559 IWL_WARN(trans, "fw recovery, no hcmd send\n");
560 return -EIO;
561 }
562
563 if ((priv->ucode_owner == IWL_OWNERSHIP_TM) &&
564 !(cmd->flags & CMD_ON_DEMAND)) {
565 IWL_DEBUG_HC(trans, "tm own the uCode, no regular hcmd send\n");
566 return -EIO;
567 }
568
569 copy_size = sizeof(out_cmd->hdr);
570 cmd_size = sizeof(out_cmd->hdr);
571
572 /* need one for the header if the first is NOCOPY */
573 BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1);
574
575 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
576 if (!cmd->len[i])
577 continue;
578 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
579 had_nocopy = true;
580 } else {
581 /* NOCOPY must not be followed by normal! */
582 if (WARN_ON(had_nocopy))
583 return -EINVAL;
584 copy_size += cmd->len[i];
585 }
586 cmd_size += cmd->len[i];
587 }
588
589 /*
590 * If any of the command structures end up being larger than
591 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
592 * allocated into separate TFDs, then we will need to
593 * increase the size of the buffers.
594 */
595 if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE))
596 return -EINVAL;
597
598 if (iwl_is_rfkill(trans->shrd) || iwl_is_ctkill(trans->shrd)) {
599 IWL_WARN(trans, "Not sending command - %s KILL\n",
600 iwl_is_rfkill(trans->shrd) ? "RF" : "CT");
601 return -EIO;
602 }
603
604 spin_lock_irqsave(&trans->hcmd_lock, flags);
605
606 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
607 spin_unlock_irqrestore(&trans->hcmd_lock, flags);
608
609 IWL_ERR(trans, "No space in command queue\n");
610 is_ct_kill = iwl_check_for_ct_kill(priv);
611 if (!is_ct_kill) {
612 IWL_ERR(trans, "Restarting adapter queue is full\n");
613 iwlagn_fw_error(priv, false);
614 }
615 return -ENOSPC;
616 }
617
618 idx = get_cmd_index(q, q->write_ptr);
619 out_cmd = txq->cmd[idx];
620 out_meta = &txq->meta[idx];
621
622 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
623 if (cmd->flags & CMD_WANT_SKB)
624 out_meta->source = cmd;
625 if (cmd->flags & CMD_ASYNC)
626 out_meta->callback = cmd->callback;
627
628 /* set up the header */
629
630 out_cmd->hdr.cmd = cmd->id;
631 out_cmd->hdr.flags = 0;
632 out_cmd->hdr.sequence =
633 cpu_to_le16(QUEUE_TO_SEQ(trans->shrd->cmd_queue) |
634 INDEX_TO_SEQ(q->write_ptr));
635
636 /* and copy the data that needs to be copied */
637
638 cmd_dest = &out_cmd->cmd.payload[0];
639 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
640 if (!cmd->len[i])
641 continue;
642 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)
643 break;
644 memcpy(cmd_dest, cmd->data[i], cmd->len[i]);
645 cmd_dest += cmd->len[i];
646 }
647
648 IWL_DEBUG_HC(trans, "Sending command %s (#%x), seq: 0x%04X, "
649 "%d bytes at %d[%d]:%d\n",
650 get_cmd_string(out_cmd->hdr.cmd),
651 out_cmd->hdr.cmd,
652 le16_to_cpu(out_cmd->hdr.sequence), cmd_size,
653 q->write_ptr, idx, trans->shrd->cmd_queue);
654
655 phys_addr = dma_map_single(bus(trans)->dev, &out_cmd->hdr, copy_size,
656 DMA_BIDIRECTIONAL);
657 if (unlikely(dma_mapping_error(bus(trans)->dev, phys_addr))) {
658 idx = -ENOMEM;
659 goto out;
660 }
661
662 dma_unmap_addr_set(out_meta, mapping, phys_addr);
663 dma_unmap_len_set(out_meta, len, copy_size);
664
665 iwlagn_txq_attach_buf_to_tfd(trans, txq,
666 phys_addr, copy_size, 1);
667 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
668 trace_bufs[0] = &out_cmd->hdr;
669 trace_lens[0] = copy_size;
670 trace_idx = 1;
671 #endif
672
673 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
674 if (!cmd->len[i])
675 continue;
676 if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY))
677 continue;
678 phys_addr = dma_map_single(bus(trans)->dev,
679 (void *)cmd->data[i],
680 cmd->len[i], DMA_BIDIRECTIONAL);
681 if (dma_mapping_error(bus(trans)->dev, phys_addr)) {
682 iwlagn_unmap_tfd(trans, out_meta,
683 &txq->tfds[q->write_ptr],
684 DMA_BIDIRECTIONAL);
685 idx = -ENOMEM;
686 goto out;
687 }
688
689 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
690 cmd->len[i], 0);
691 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
692 trace_bufs[trace_idx] = cmd->data[i];
693 trace_lens[trace_idx] = cmd->len[i];
694 trace_idx++;
695 #endif
696 }
697
698 out_meta->flags = cmd->flags;
699
700 txq->need_update = 1;
701
702 /* check that tracing gets all possible blocks */
703 BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3);
704 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
705 trace_iwlwifi_dev_hcmd(priv, cmd->flags,
706 trace_bufs[0], trace_lens[0],
707 trace_bufs[1], trace_lens[1],
708 trace_bufs[2], trace_lens[2]);
709 #endif
710
711 /* Increment and update queue's write index */
712 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
713 iwl_txq_update_write_ptr(priv, txq);
714
715 out:
716 spin_unlock_irqrestore(&trans->hcmd_lock, flags);
717 return idx;
718 }
719
720 /**
721 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
722 *
723 * When FW advances 'R' index, all entries between old and new 'R' index
724 * need to be reclaimed. As result, some free space forms. If there is
725 * enough free space (> low mark), wake the stack that feeds us.
726 */
727 static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, int idx)
728 {
729 struct iwl_tx_queue *txq = &priv->txq[txq_id];
730 struct iwl_queue *q = &txq->q;
731 int nfreed = 0;
732
733 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
734 IWL_ERR(priv, "%s: Read index for DMA queue txq id (%d), "
735 "index %d is out of range [0-%d] %d %d.\n", __func__,
736 txq_id, idx, q->n_bd, q->write_ptr, q->read_ptr);
737 return;
738 }
739
740 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
741 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
742
743 if (nfreed++ > 0) {
744 IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
745 q->write_ptr, q->read_ptr);
746 iwlagn_fw_error(priv, false);
747 }
748
749 }
750 }
751
752 /**
753 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
754 * @rxb: Rx buffer to reclaim
755 *
756 * If an Rx buffer has an async callback associated with it the callback
757 * will be executed. The attached skb (if present) will only be freed
758 * if the callback returns 1
759 */
760 void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
761 {
762 struct iwl_rx_packet *pkt = rxb_addr(rxb);
763 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
764 int txq_id = SEQ_TO_QUEUE(sequence);
765 int index = SEQ_TO_INDEX(sequence);
766 int cmd_index;
767 struct iwl_device_cmd *cmd;
768 struct iwl_cmd_meta *meta;
769 struct iwl_trans *trans = trans(priv);
770 struct iwl_tx_queue *txq = &priv->txq[trans->shrd->cmd_queue];
771 unsigned long flags;
772
773 /* If a Tx command is being handled and it isn't in the actual
774 * command queue then there a command routing bug has been introduced
775 * in the queue management code. */
776 if (WARN(txq_id != trans->shrd->cmd_queue,
777 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
778 txq_id, trans->shrd->cmd_queue, sequence,
779 priv->txq[trans->shrd->cmd_queue].q.read_ptr,
780 priv->txq[trans->shrd->cmd_queue].q.write_ptr)) {
781 iwl_print_hex_error(priv, pkt, 32);
782 return;
783 }
784
785 cmd_index = get_cmd_index(&txq->q, index);
786 cmd = txq->cmd[cmd_index];
787 meta = &txq->meta[cmd_index];
788
789 iwlagn_unmap_tfd(trans, meta, &txq->tfds[index],
790 DMA_BIDIRECTIONAL);
791
792 /* Input error checking is done when commands are added to queue. */
793 if (meta->flags & CMD_WANT_SKB) {
794 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
795 rxb->page = NULL;
796 } else if (meta->callback)
797 meta->callback(priv, cmd, pkt);
798
799 spin_lock_irqsave(&trans->hcmd_lock, flags);
800
801 iwl_hcmd_queue_reclaim(priv, txq_id, index);
802
803 if (!(meta->flags & CMD_ASYNC)) {
804 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
805 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
806 get_cmd_string(cmd->hdr.cmd));
807 wake_up_interruptible(&priv->wait_command_queue);
808 }
809
810 meta->flags = 0;
811
812 spin_unlock_irqrestore(&trans->hcmd_lock, flags);
813 }
814
815 const char *get_cmd_string(u8 cmd)
816 {
817 switch (cmd) {
818 IWL_CMD(REPLY_ALIVE);
819 IWL_CMD(REPLY_ERROR);
820 IWL_CMD(REPLY_RXON);
821 IWL_CMD(REPLY_RXON_ASSOC);
822 IWL_CMD(REPLY_QOS_PARAM);
823 IWL_CMD(REPLY_RXON_TIMING);
824 IWL_CMD(REPLY_ADD_STA);
825 IWL_CMD(REPLY_REMOVE_STA);
826 IWL_CMD(REPLY_REMOVE_ALL_STA);
827 IWL_CMD(REPLY_TXFIFO_FLUSH);
828 IWL_CMD(REPLY_WEPKEY);
829 IWL_CMD(REPLY_TX);
830 IWL_CMD(REPLY_LEDS_CMD);
831 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
832 IWL_CMD(COEX_PRIORITY_TABLE_CMD);
833 IWL_CMD(COEX_MEDIUM_NOTIFICATION);
834 IWL_CMD(COEX_EVENT_CMD);
835 IWL_CMD(REPLY_QUIET_CMD);
836 IWL_CMD(REPLY_CHANNEL_SWITCH);
837 IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
838 IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
839 IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
840 IWL_CMD(POWER_TABLE_CMD);
841 IWL_CMD(PM_SLEEP_NOTIFICATION);
842 IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
843 IWL_CMD(REPLY_SCAN_CMD);
844 IWL_CMD(REPLY_SCAN_ABORT_CMD);
845 IWL_CMD(SCAN_START_NOTIFICATION);
846 IWL_CMD(SCAN_RESULTS_NOTIFICATION);
847 IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
848 IWL_CMD(BEACON_NOTIFICATION);
849 IWL_CMD(REPLY_TX_BEACON);
850 IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
851 IWL_CMD(QUIET_NOTIFICATION);
852 IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
853 IWL_CMD(MEASURE_ABORT_NOTIFICATION);
854 IWL_CMD(REPLY_BT_CONFIG);
855 IWL_CMD(REPLY_STATISTICS_CMD);
856 IWL_CMD(STATISTICS_NOTIFICATION);
857 IWL_CMD(REPLY_CARD_STATE_CMD);
858 IWL_CMD(CARD_STATE_NOTIFICATION);
859 IWL_CMD(MISSED_BEACONS_NOTIFICATION);
860 IWL_CMD(REPLY_CT_KILL_CONFIG_CMD);
861 IWL_CMD(SENSITIVITY_CMD);
862 IWL_CMD(REPLY_PHY_CALIBRATION_CMD);
863 IWL_CMD(REPLY_RX_PHY_CMD);
864 IWL_CMD(REPLY_RX_MPDU_CMD);
865 IWL_CMD(REPLY_RX);
866 IWL_CMD(REPLY_COMPRESSED_BA);
867 IWL_CMD(CALIBRATION_CFG_CMD);
868 IWL_CMD(CALIBRATION_RES_NOTIFICATION);
869 IWL_CMD(CALIBRATION_COMPLETE_NOTIFICATION);
870 IWL_CMD(REPLY_TX_POWER_DBM_CMD);
871 IWL_CMD(TEMPERATURE_NOTIFICATION);
872 IWL_CMD(TX_ANT_CONFIGURATION_CMD);
873 IWL_CMD(REPLY_BT_COEX_PROFILE_NOTIF);
874 IWL_CMD(REPLY_BT_COEX_PRIO_TABLE);
875 IWL_CMD(REPLY_BT_COEX_PROT_ENV);
876 IWL_CMD(REPLY_WIPAN_PARAMS);
877 IWL_CMD(REPLY_WIPAN_RXON);
878 IWL_CMD(REPLY_WIPAN_RXON_TIMING);
879 IWL_CMD(REPLY_WIPAN_RXON_ASSOC);
880 IWL_CMD(REPLY_WIPAN_QOS_PARAM);
881 IWL_CMD(REPLY_WIPAN_WEPKEY);
882 IWL_CMD(REPLY_WIPAN_P2P_CHANNEL_SWITCH);
883 IWL_CMD(REPLY_WIPAN_NOA_NOTIFICATION);
884 IWL_CMD(REPLY_WIPAN_DEACTIVATION_COMPLETE);
885 IWL_CMD(REPLY_WOWLAN_PATTERNS);
886 IWL_CMD(REPLY_WOWLAN_WAKEUP_FILTER);
887 IWL_CMD(REPLY_WOWLAN_TSC_RSC_PARAMS);
888 IWL_CMD(REPLY_WOWLAN_TKIP_PARAMS);
889 IWL_CMD(REPLY_WOWLAN_KEK_KCK_MATERIAL);
890 IWL_CMD(REPLY_WOWLAN_GET_STATUS);
891 default:
892 return "UNKNOWN";
893
894 }
895 }
896
897 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
898
899 static void iwl_generic_cmd_callback(struct iwl_priv *priv,
900 struct iwl_device_cmd *cmd,
901 struct iwl_rx_packet *pkt)
902 {
903 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
904 IWL_ERR(priv, "Bad return from %s (0x%08X)\n",
905 get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
906 return;
907 }
908
909 #ifdef CONFIG_IWLWIFI_DEBUG
910 switch (cmd->hdr.cmd) {
911 case REPLY_TX_LINK_QUALITY_CMD:
912 case SENSITIVITY_CMD:
913 IWL_DEBUG_HC_DUMP(priv, "back from %s (0x%08X)\n",
914 get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
915 break;
916 default:
917 IWL_DEBUG_HC(priv, "back from %s (0x%08X)\n",
918 get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
919 }
920 #endif
921 }
922
923 static int iwl_send_cmd_async(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
924 {
925 int ret;
926
927 /* An asynchronous command can not expect an SKB to be set. */
928 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
929 return -EINVAL;
930
931 /* Assign a generic callback if one is not provided */
932 if (!cmd->callback)
933 cmd->callback = iwl_generic_cmd_callback;
934
935 if (test_bit(STATUS_EXIT_PENDING, &trans->shrd->status))
936 return -EBUSY;
937
938 ret = iwl_enqueue_hcmd(trans, cmd);
939 if (ret < 0) {
940 IWL_ERR(trans, "Error sending %s: enqueue_hcmd failed: %d\n",
941 get_cmd_string(cmd->id), ret);
942 return ret;
943 }
944 return 0;
945 }
946
947 static int iwl_send_cmd_sync(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
948 {
949 int cmd_idx;
950 int ret;
951
952 lockdep_assert_held(&trans->shrd->mutex);
953
954 /* A synchronous command can not have a callback set. */
955 if (WARN_ON(cmd->callback))
956 return -EINVAL;
957
958 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
959 get_cmd_string(cmd->id));
960
961 set_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
962 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
963 get_cmd_string(cmd->id));
964
965 cmd_idx = iwl_enqueue_hcmd(trans, cmd);
966 if (cmd_idx < 0) {
967 ret = cmd_idx;
968 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
969 IWL_ERR(trans, "Error sending %s: enqueue_hcmd failed: %d\n",
970 get_cmd_string(cmd->id), ret);
971 return ret;
972 }
973
974 ret = wait_event_interruptible_timeout(priv(trans)->wait_command_queue,
975 !test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status),
976 HOST_COMPLETE_TIMEOUT);
977 if (!ret) {
978 if (test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status)) {
979 IWL_ERR(trans,
980 "Error sending %s: time out after %dms.\n",
981 get_cmd_string(cmd->id),
982 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
983
984 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
985 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command"
986 "%s\n", get_cmd_string(cmd->id));
987 ret = -ETIMEDOUT;
988 goto cancel;
989 }
990 }
991
992 if (test_bit(STATUS_RF_KILL_HW, &trans->shrd->status)) {
993 IWL_ERR(trans, "Command %s aborted: RF KILL Switch\n",
994 get_cmd_string(cmd->id));
995 ret = -ECANCELED;
996 goto fail;
997 }
998 if (test_bit(STATUS_FW_ERROR, &trans->shrd->status)) {
999 IWL_ERR(trans, "Command %s failed: FW Error\n",
1000 get_cmd_string(cmd->id));
1001 ret = -EIO;
1002 goto fail;
1003 }
1004 if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) {
1005 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1006 get_cmd_string(cmd->id));
1007 ret = -EIO;
1008 goto cancel;
1009 }
1010
1011 return 0;
1012
1013 cancel:
1014 if (cmd->flags & CMD_WANT_SKB) {
1015 /*
1016 * Cancel the CMD_WANT_SKB flag for the cmd in the
1017 * TX cmd queue. Otherwise in case the cmd comes
1018 * in later, it will possibly set an invalid
1019 * address (cmd->meta.source).
1020 */
1021 priv(trans)->txq[trans->shrd->cmd_queue].meta[cmd_idx].flags &=
1022 ~CMD_WANT_SKB;
1023 }
1024 fail:
1025 if (cmd->reply_page) {
1026 iwl_free_pages(trans->shrd, cmd->reply_page);
1027 cmd->reply_page = 0;
1028 }
1029
1030 return ret;
1031 }
1032
1033 int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1034 {
1035 if (cmd->flags & CMD_ASYNC)
1036 return iwl_send_cmd_async(trans, cmd);
1037
1038 return iwl_send_cmd_sync(trans, cmd);
1039 }
1040
1041 int iwl_trans_pcie_send_cmd_pdu(struct iwl_trans *trans, u8 id, u32 flags,
1042 u16 len, const void *data)
1043 {
1044 struct iwl_host_cmd cmd = {
1045 .id = id,
1046 .len = { len, },
1047 .data = { data, },
1048 .flags = flags,
1049 };
1050
1051 return iwl_trans_pcie_send_cmd(trans, &cmd);
1052 }
1053
1054 /* Frees buffers until index _not_ inclusive */
1055 void iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
1056 struct sk_buff_head *skbs)
1057 {
1058 struct iwl_tx_queue *txq = &priv(trans)->txq[txq_id];
1059 struct iwl_queue *q = &txq->q;
1060 struct iwl_tx_info *tx_info;
1061 struct ieee80211_tx_info *info;
1062 int last_to_free;
1063
1064 /*Since we free until index _not_ inclusive, the one before index is
1065 * the last we will free. This one must be used */
1066 last_to_free = iwl_queue_dec_wrap(index, q->n_bd);
1067
1068 if ((index >= q->n_bd) ||
1069 (iwl_queue_used(q, last_to_free) == 0)) {
1070 IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), "
1071 "last_to_free %d is out of range [0-%d] %d %d.\n",
1072 __func__, txq_id, last_to_free, q->n_bd,
1073 q->write_ptr, q->read_ptr);
1074 return;
1075 }
1076
1077 IWL_DEBUG_TX_REPLY(trans, "reclaim: [%d, %d, %d]\n", txq_id,
1078 q->read_ptr, index);
1079
1080 if (WARN_ON(!skb_queue_empty(skbs)))
1081 return;
1082
1083 for (;
1084 q->read_ptr != index;
1085 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1086
1087 tx_info = &txq->txb[txq->q.read_ptr];
1088
1089 if (WARN_ON_ONCE(tx_info->skb == NULL))
1090 continue;
1091
1092 info = IEEE80211_SKB_CB(tx_info->skb);
1093 info->driver_data[0] = tx_info->ctx;
1094
1095 __skb_queue_tail(skbs, tx_info->skb);
1096
1097 tx_info->skb = NULL;
1098
1099 iwlagn_txq_inval_byte_cnt_tbl(trans, txq);
1100
1101 iwlagn_txq_free_tfd(trans, txq, txq->q.read_ptr);
1102 }
1103 }
Linux kernel - Deliverables
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