1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *****************************************************************************/
63 #include <linux/interrupt.h>
64 #include <linux/debugfs.h>
67 #include "iwl-trans.h"
69 #include "iwl-helpers.h"
70 #include "iwl-trans-int-pcie.h"
71 /*TODO remove uneeded includes when the transport layer tx_free will be here */
74 #include "iwl-shared.h"
76 static int iwl_trans_rx_alloc(struct iwl_trans
*trans
)
78 struct iwl_trans_pcie
*trans_pcie
=
79 IWL_TRANS_GET_PCIE_TRANS(trans
);
80 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
81 struct device
*dev
= bus(trans
)->dev
;
83 memset(&trans_pcie
->rxq
, 0, sizeof(trans_pcie
->rxq
));
85 spin_lock_init(&rxq
->lock
);
86 INIT_LIST_HEAD(&rxq
->rx_free
);
87 INIT_LIST_HEAD(&rxq
->rx_used
);
89 if (WARN_ON(rxq
->bd
|| rxq
->rb_stts
))
92 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
93 rxq
->bd
= dma_alloc_coherent(dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
94 &rxq
->bd_dma
, GFP_KERNEL
);
97 memset(rxq
->bd
, 0, sizeof(__le32
) * RX_QUEUE_SIZE
);
99 /*Allocate the driver's pointer to receive buffer status */
100 rxq
->rb_stts
= dma_alloc_coherent(dev
, sizeof(*rxq
->rb_stts
),
101 &rxq
->rb_stts_dma
, GFP_KERNEL
);
104 memset(rxq
->rb_stts
, 0, sizeof(*rxq
->rb_stts
));
109 dma_free_coherent(dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
110 rxq
->bd
, rxq
->bd_dma
);
111 memset(&rxq
->bd_dma
, 0, sizeof(rxq
->bd_dma
));
117 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans
*trans
)
119 struct iwl_trans_pcie
*trans_pcie
=
120 IWL_TRANS_GET_PCIE_TRANS(trans
);
121 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
124 /* Fill the rx_used queue with _all_ of the Rx buffers */
125 for (i
= 0; i
< RX_FREE_BUFFERS
+ RX_QUEUE_SIZE
; i
++) {
126 /* In the reset function, these buffers may have been allocated
127 * to an SKB, so we need to unmap and free potential storage */
128 if (rxq
->pool
[i
].page
!= NULL
) {
129 dma_unmap_page(bus(trans
)->dev
, rxq
->pool
[i
].page_dma
,
130 PAGE_SIZE
<< hw_params(trans
).rx_page_order
,
132 __iwl_free_pages(priv(trans
), rxq
->pool
[i
].page
);
133 rxq
->pool
[i
].page
= NULL
;
135 list_add_tail(&rxq
->pool
[i
].list
, &rxq
->rx_used
);
139 static void iwl_trans_rx_hw_init(struct iwl_priv
*priv
,
140 struct iwl_rx_queue
*rxq
)
143 const u32 rfdnlog
= RX_QUEUE_SIZE_LOG
; /* 256 RBDs */
144 u32 rb_timeout
= 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
146 rb_timeout
= RX_RB_TIMEOUT
;
148 if (iwlagn_mod_params
.amsdu_size_8K
)
149 rb_size
= FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K
;
151 rb_size
= FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K
;
154 iwl_write_direct32(priv
, FH_MEM_RCSR_CHNL0_CONFIG_REG
, 0);
156 /* Reset driver's Rx queue write index */
157 iwl_write_direct32(priv
, FH_RSCSR_CHNL0_RBDCB_WPTR_REG
, 0);
159 /* Tell device where to find RBD circular buffer in DRAM */
160 iwl_write_direct32(priv
, FH_RSCSR_CHNL0_RBDCB_BASE_REG
,
161 (u32
)(rxq
->bd_dma
>> 8));
163 /* Tell device where in DRAM to update its Rx status */
164 iwl_write_direct32(priv
, FH_RSCSR_CHNL0_STTS_WPTR_REG
,
165 rxq
->rb_stts_dma
>> 4);
168 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
169 * the credit mechanism in 5000 HW RX FIFO
170 * Direct rx interrupts to hosts
171 * Rx buffer size 4 or 8k
175 iwl_write_direct32(priv
, FH_MEM_RCSR_CHNL0_CONFIG_REG
,
176 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL
|
177 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY
|
178 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL
|
179 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK
|
181 (rb_timeout
<< FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS
)|
182 (rfdnlog
<< FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS
));
184 /* Set interrupt coalescing timer to default (2048 usecs) */
185 iwl_write8(priv
, CSR_INT_COALESCING
, IWL_HOST_INT_TIMEOUT_DEF
);
188 static int iwl_rx_init(struct iwl_trans
*trans
)
190 struct iwl_trans_pcie
*trans_pcie
=
191 IWL_TRANS_GET_PCIE_TRANS(trans
);
192 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
198 err
= iwl_trans_rx_alloc(trans
);
203 spin_lock_irqsave(&rxq
->lock
, flags
);
204 INIT_LIST_HEAD(&rxq
->rx_free
);
205 INIT_LIST_HEAD(&rxq
->rx_used
);
207 iwl_trans_rxq_free_rx_bufs(trans
);
209 for (i
= 0; i
< RX_QUEUE_SIZE
; i
++)
210 rxq
->queue
[i
] = NULL
;
212 /* Set us so that we have processed and used all buffers, but have
213 * not restocked the Rx queue with fresh buffers */
214 rxq
->read
= rxq
->write
= 0;
215 rxq
->write_actual
= 0;
217 spin_unlock_irqrestore(&rxq
->lock
, flags
);
219 iwlagn_rx_replenish(trans
);
221 iwl_trans_rx_hw_init(priv(trans
), rxq
);
223 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
224 rxq
->need_update
= 1;
225 iwl_rx_queue_update_write_ptr(trans
, rxq
);
226 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
231 static void iwl_trans_pcie_rx_free(struct iwl_trans
*trans
)
233 struct iwl_trans_pcie
*trans_pcie
=
234 IWL_TRANS_GET_PCIE_TRANS(trans
);
235 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
239 /*if rxq->bd is NULL, it means that nothing has been allocated,
242 IWL_DEBUG_INFO(trans
, "Free NULL rx context\n");
246 spin_lock_irqsave(&rxq
->lock
, flags
);
247 iwl_trans_rxq_free_rx_bufs(trans
);
248 spin_unlock_irqrestore(&rxq
->lock
, flags
);
250 dma_free_coherent(bus(trans
)->dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
251 rxq
->bd
, rxq
->bd_dma
);
252 memset(&rxq
->bd_dma
, 0, sizeof(rxq
->bd_dma
));
256 dma_free_coherent(bus(trans
)->dev
,
257 sizeof(struct iwl_rb_status
),
258 rxq
->rb_stts
, rxq
->rb_stts_dma
);
260 IWL_DEBUG_INFO(trans
, "Free rxq->rb_stts which is NULL\n");
261 memset(&rxq
->rb_stts_dma
, 0, sizeof(rxq
->rb_stts_dma
));
265 static int iwl_trans_rx_stop(struct iwl_priv
*priv
)
269 iwl_write_direct32(priv
, FH_MEM_RCSR_CHNL0_CONFIG_REG
, 0);
270 return iwl_poll_direct_bit(priv
, FH_MEM_RSSR_RX_STATUS_REG
,
271 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE
, 1000);
274 static inline int iwlagn_alloc_dma_ptr(struct iwl_priv
*priv
,
275 struct iwl_dma_ptr
*ptr
, size_t size
)
277 if (WARN_ON(ptr
->addr
))
280 ptr
->addr
= dma_alloc_coherent(priv
->bus
->dev
, size
,
281 &ptr
->dma
, GFP_KERNEL
);
288 static inline void iwlagn_free_dma_ptr(struct iwl_priv
*priv
,
289 struct iwl_dma_ptr
*ptr
)
291 if (unlikely(!ptr
->addr
))
294 dma_free_coherent(priv
->bus
->dev
, ptr
->size
, ptr
->addr
, ptr
->dma
);
295 memset(ptr
, 0, sizeof(*ptr
));
298 static int iwl_trans_txq_alloc(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
,
299 int slots_num
, u32 txq_id
)
301 size_t tfd_sz
= hw_params(priv
).tfd_size
* TFD_QUEUE_SIZE_MAX
;
304 if (WARN_ON(txq
->meta
|| txq
->cmd
|| txq
->txb
|| txq
->tfds
))
307 txq
->q
.n_window
= slots_num
;
309 txq
->meta
= kzalloc(sizeof(txq
->meta
[0]) * slots_num
,
311 txq
->cmd
= kzalloc(sizeof(txq
->cmd
[0]) * slots_num
,
314 if (!txq
->meta
|| !txq
->cmd
)
317 for (i
= 0; i
< slots_num
; i
++) {
318 txq
->cmd
[i
] = kmalloc(sizeof(struct iwl_device_cmd
),
324 /* Alloc driver data array and TFD circular buffer */
325 /* Driver private data, only for Tx (not command) queues,
326 * not shared with device. */
327 if (txq_id
!= priv
->shrd
->cmd_queue
) {
328 txq
->txb
= kzalloc(sizeof(txq
->txb
[0]) *
329 TFD_QUEUE_SIZE_MAX
, GFP_KERNEL
);
331 IWL_ERR(priv
, "kmalloc for auxiliary BD "
332 "structures failed\n");
339 /* Circular buffer of transmit frame descriptors (TFDs),
340 * shared with device */
341 txq
->tfds
= dma_alloc_coherent(priv
->bus
->dev
, tfd_sz
, &txq
->q
.dma_addr
,
344 IWL_ERR(priv
, "dma_alloc_coherent(%zd) failed\n", tfd_sz
);
353 /* since txq->cmd has been zeroed,
354 * all non allocated cmd[i] will be NULL */
356 for (i
= 0; i
< slots_num
; i
++)
367 static int iwl_trans_txq_init(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
,
368 int slots_num
, u32 txq_id
)
372 txq
->need_update
= 0;
373 memset(txq
->meta
, 0, sizeof(txq
->meta
[0]) * slots_num
);
376 * For the default queues 0-3, set up the swq_id
377 * already -- all others need to get one later
378 * (if they need one at all).
381 iwl_set_swq_id(txq
, txq_id
, txq_id
);
383 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
384 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
385 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX
& (TFD_QUEUE_SIZE_MAX
- 1));
387 /* Initialize queue's high/low-water marks, and head/tail indexes */
388 ret
= iwl_queue_init(priv
, &txq
->q
, TFD_QUEUE_SIZE_MAX
, slots_num
,
394 * Tell nic where to find circular buffer of Tx Frame Descriptors for
395 * given Tx queue, and enable the DMA channel used for that queue.
396 * Circular buffer (TFD queue in DRAM) physical base address */
397 iwl_write_direct32(priv
, FH_MEM_CBBC_QUEUE(txq_id
),
398 txq
->q
.dma_addr
>> 8);
404 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
406 static void iwl_tx_queue_unmap(struct iwl_priv
*priv
, int txq_id
)
408 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
409 struct iwl_queue
*q
= &txq
->q
;
414 while (q
->write_ptr
!= q
->read_ptr
) {
415 /* The read_ptr needs to bound by q->n_window */
416 iwlagn_txq_free_tfd(priv
, txq
, get_cmd_index(q
, q
->read_ptr
));
417 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
);
422 * iwl_tx_queue_free - Deallocate DMA queue.
423 * @txq: Transmit queue to deallocate.
425 * Empty queue by removing and destroying all BD's.
427 * 0-fill, but do not free "txq" descriptor structure.
429 static void iwl_tx_queue_free(struct iwl_priv
*priv
, int txq_id
)
431 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
432 struct device
*dev
= priv
->bus
->dev
;
437 iwl_tx_queue_unmap(priv
, txq_id
);
439 /* De-alloc array of command/tx buffers */
440 for (i
= 0; i
< txq
->q
.n_window
; i
++)
443 /* De-alloc circular buffer of TFDs */
445 dma_free_coherent(dev
, hw_params(priv
).tfd_size
*
446 txq
->q
.n_bd
, txq
->tfds
, txq
->q
.dma_addr
);
447 memset(&txq
->q
.dma_addr
, 0, sizeof(txq
->q
.dma_addr
));
450 /* De-alloc array of per-TFD driver data */
454 /* deallocate arrays */
460 /* 0-fill queue descriptor structure */
461 memset(txq
, 0, sizeof(*txq
));
465 * iwl_trans_tx_free - Free TXQ Context
467 * Destroy all TX DMA queues and structures
469 static void iwl_trans_pcie_tx_free(struct iwl_priv
*priv
)
472 struct iwl_trans
*trans
= trans(priv
);
473 struct iwl_trans_pcie
*trans_pcie
=
474 IWL_TRANS_GET_PCIE_TRANS(trans
);
479 txq_id
< hw_params(priv
).max_txq_num
; txq_id
++)
480 iwl_tx_queue_free(priv
, txq_id
);
486 iwlagn_free_dma_ptr(priv
, &priv
->kw
);
488 iwlagn_free_dma_ptr(priv
, &trans_pcie
->scd_bc_tbls
);
492 * iwl_trans_tx_alloc - allocate TX context
493 * Allocate all Tx DMA structures and initialize them
498 static int iwl_trans_tx_alloc(struct iwl_priv
*priv
)
501 int txq_id
, slots_num
;
502 struct iwl_trans
*trans
= trans(priv
);
503 struct iwl_trans_pcie
*trans_pcie
=
504 IWL_TRANS_GET_PCIE_TRANS(trans
);
506 /*It is not allowed to alloc twice, so warn when this happens.
507 * We cannot rely on the previous allocation, so free and fail */
508 if (WARN_ON(priv
->txq
)) {
513 ret
= iwlagn_alloc_dma_ptr(priv
, &trans_pcie
->scd_bc_tbls
,
514 hw_params(priv
).scd_bc_tbls_size
);
516 IWL_ERR(priv
, "Scheduler BC Table allocation failed\n");
520 /* Alloc keep-warm buffer */
521 ret
= iwlagn_alloc_dma_ptr(priv
, &priv
->kw
, IWL_KW_SIZE
);
523 IWL_ERR(priv
, "Keep Warm allocation failed\n");
527 priv
->txq
= kzalloc(sizeof(struct iwl_tx_queue
) *
528 priv
->cfg
->base_params
->num_of_queues
, GFP_KERNEL
);
530 IWL_ERR(priv
, "Not enough memory for txq\n");
535 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
536 for (txq_id
= 0; txq_id
< hw_params(priv
).max_txq_num
; txq_id
++) {
537 slots_num
= (txq_id
== priv
->shrd
->cmd_queue
) ?
538 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
539 ret
= iwl_trans_txq_alloc(priv
, &priv
->txq
[txq_id
], slots_num
,
542 IWL_ERR(priv
, "Tx %d queue alloc failed\n", txq_id
);
550 iwl_trans_tx_free(trans(priv
));
554 static int iwl_tx_init(struct iwl_priv
*priv
)
557 int txq_id
, slots_num
;
562 ret
= iwl_trans_tx_alloc(priv
);
568 spin_lock_irqsave(&priv
->shrd
->lock
, flags
);
570 /* Turn off all Tx DMA fifos */
571 iwl_write_prph(priv
, SCD_TXFACT
, 0);
573 /* Tell NIC where to find the "keep warm" buffer */
574 iwl_write_direct32(priv
, FH_KW_MEM_ADDR_REG
, priv
->kw
.dma
>> 4);
576 spin_unlock_irqrestore(&priv
->shrd
->lock
, flags
);
578 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
579 for (txq_id
= 0; txq_id
< hw_params(priv
).max_txq_num
; txq_id
++) {
580 slots_num
= (txq_id
== priv
->shrd
->cmd_queue
) ?
581 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
582 ret
= iwl_trans_txq_init(priv
, &priv
->txq
[txq_id
], slots_num
,
585 IWL_ERR(priv
, "Tx %d queue init failed\n", txq_id
);
592 /*Upon error, free only if we allocated something */
594 iwl_trans_tx_free(trans(priv
));
598 static void iwl_set_pwr_vmain(struct iwl_priv
*priv
)
601 * (for documentation purposes)
602 * to set power to V_AUX, do:
604 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
605 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
606 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
607 ~APMG_PS_CTRL_MSK_PWR_SRC);
610 iwl_set_bits_mask_prph(priv
, APMG_PS_CTRL_REG
,
611 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN
,
612 ~APMG_PS_CTRL_MSK_PWR_SRC
);
615 static int iwl_nic_init(struct iwl_priv
*priv
)
620 spin_lock_irqsave(&priv
->shrd
->lock
, flags
);
623 /* Set interrupt coalescing calibration timer to default (512 usecs) */
624 iwl_write8(priv
, CSR_INT_COALESCING
, IWL_HOST_INT_CALIB_TIMEOUT_DEF
);
626 spin_unlock_irqrestore(&priv
->shrd
->lock
, flags
);
628 iwl_set_pwr_vmain(priv
);
630 priv
->cfg
->lib
->nic_config(priv
);
632 /* Allocate the RX queue, or reset if it is already allocated */
633 iwl_rx_init(trans(priv
));
635 /* Allocate or reset and init all Tx and Command queues */
636 if (iwl_tx_init(priv
))
639 if (priv
->cfg
->base_params
->shadow_reg_enable
) {
640 /* enable shadow regs in HW */
641 iwl_set_bit(priv
, CSR_MAC_SHADOW_REG_CTRL
,
645 set_bit(STATUS_INIT
, &priv
->shrd
->status
);
650 #define HW_READY_TIMEOUT (50)
652 /* Note: returns poll_bit return value, which is >= 0 if success */
653 static int iwl_set_hw_ready(struct iwl_priv
*priv
)
657 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
658 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
);
660 /* See if we got it */
661 ret
= iwl_poll_bit(priv
, CSR_HW_IF_CONFIG_REG
,
662 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
663 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
666 IWL_DEBUG_INFO(priv
, "hardware%s ready\n", ret
< 0 ? " not" : "");
670 /* Note: returns standard 0/-ERROR code */
671 static int iwl_trans_pcie_prepare_card_hw(struct iwl_priv
*priv
)
675 IWL_DEBUG_INFO(priv
, "iwl_trans_prepare_card_hw enter\n");
677 ret
= iwl_set_hw_ready(priv
);
681 /* If HW is not ready, prepare the conditions to check again */
682 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
683 CSR_HW_IF_CONFIG_REG_PREPARE
);
685 ret
= iwl_poll_bit(priv
, CSR_HW_IF_CONFIG_REG
,
686 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE
,
687 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE
, 150000);
692 /* HW should be ready by now, check again. */
693 ret
= iwl_set_hw_ready(priv
);
699 static int iwl_trans_pcie_start_device(struct iwl_priv
*priv
)
703 priv
->ucode_owner
= IWL_OWNERSHIP_DRIVER
;
705 if ((priv
->cfg
->sku
& EEPROM_SKU_CAP_AMT_ENABLE
) &&
706 iwl_trans_pcie_prepare_card_hw(priv
)) {
707 IWL_WARN(priv
, "Exit HW not ready\n");
711 /* If platform's RF_KILL switch is NOT set to KILL */
712 if (iwl_read32(priv
, CSR_GP_CNTRL
) &
713 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW
)
714 clear_bit(STATUS_RF_KILL_HW
, &priv
->shrd
->status
);
716 set_bit(STATUS_RF_KILL_HW
, &priv
->shrd
->status
);
718 if (iwl_is_rfkill(priv
)) {
719 wiphy_rfkill_set_hw_state(priv
->hw
->wiphy
, true);
720 iwl_enable_interrupts(trans(priv
));
724 iwl_write32(priv
, CSR_INT
, 0xFFFFFFFF);
726 ret
= iwl_nic_init(priv
);
728 IWL_ERR(priv
, "Unable to init nic\n");
732 /* make sure rfkill handshake bits are cleared */
733 iwl_write32(priv
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
734 iwl_write32(priv
, CSR_UCODE_DRV_GP1_CLR
,
735 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED
);
737 /* clear (again), then enable host interrupts */
738 iwl_write32(priv
, CSR_INT
, 0xFFFFFFFF);
739 iwl_enable_interrupts(trans(priv
));
741 /* really make sure rfkill handshake bits are cleared */
742 iwl_write32(priv
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
743 iwl_write32(priv
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
749 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
750 * must be called under priv->shrd->lock and mac access
752 static void iwl_trans_txq_set_sched(struct iwl_priv
*priv
, u32 mask
)
754 iwl_write_prph(priv
, SCD_TXFACT
, mask
);
757 #define IWL_AC_UNSET -1
759 struct queue_to_fifo_ac
{
763 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo
[] = {
764 { IWL_TX_FIFO_VO
, IEEE80211_AC_VO
, },
765 { IWL_TX_FIFO_VI
, IEEE80211_AC_VI
, },
766 { IWL_TX_FIFO_BE
, IEEE80211_AC_BE
, },
767 { IWL_TX_FIFO_BK
, IEEE80211_AC_BK
, },
768 { IWLAGN_CMD_FIFO_NUM
, IWL_AC_UNSET
, },
769 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
770 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
771 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
772 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
773 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
774 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
777 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo
[] = {
778 { IWL_TX_FIFO_VO
, IEEE80211_AC_VO
, },
779 { IWL_TX_FIFO_VI
, IEEE80211_AC_VI
, },
780 { IWL_TX_FIFO_BE
, IEEE80211_AC_BE
, },
781 { IWL_TX_FIFO_BK
, IEEE80211_AC_BK
, },
782 { IWL_TX_FIFO_BK_IPAN
, IEEE80211_AC_BK
, },
783 { IWL_TX_FIFO_BE_IPAN
, IEEE80211_AC_BE
, },
784 { IWL_TX_FIFO_VI_IPAN
, IEEE80211_AC_VI
, },
785 { IWL_TX_FIFO_VO_IPAN
, IEEE80211_AC_VO
, },
786 { IWL_TX_FIFO_BE_IPAN
, 2, },
787 { IWLAGN_CMD_FIFO_NUM
, IWL_AC_UNSET
, },
788 { IWL_TX_FIFO_AUX
, IWL_AC_UNSET
, },
790 static void iwl_trans_pcie_tx_start(struct iwl_priv
*priv
)
792 const struct queue_to_fifo_ac
*queue_to_fifo
;
793 struct iwl_rxon_context
*ctx
;
794 struct iwl_trans
*trans
= trans(priv
);
795 struct iwl_trans_pcie
*trans_pcie
=
796 IWL_TRANS_GET_PCIE_TRANS(trans
);
802 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
804 trans_pcie
->scd_base_addr
= iwl_read_prph(priv
, SCD_SRAM_BASE_ADDR
);
805 a
= trans_pcie
->scd_base_addr
+ SCD_CONTEXT_MEM_LOWER_BOUND
;
806 /* reset conext data memory */
807 for (; a
< trans_pcie
->scd_base_addr
+ SCD_CONTEXT_MEM_UPPER_BOUND
;
809 iwl_write_targ_mem(priv
, a
, 0);
810 /* reset tx status memory */
811 for (; a
< trans_pcie
->scd_base_addr
+ SCD_TX_STTS_MEM_UPPER_BOUND
;
813 iwl_write_targ_mem(priv
, a
, 0);
814 for (; a
< trans_pcie
->scd_base_addr
+
815 SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(priv
).max_txq_num
);
817 iwl_write_targ_mem(priv
, a
, 0);
819 iwl_write_prph(priv
, SCD_DRAM_BASE_ADDR
,
820 trans_pcie
->scd_bc_tbls
.dma
>> 10);
822 /* Enable DMA channel */
823 for (chan
= 0; chan
< FH_TCSR_CHNL_NUM
; chan
++)
824 iwl_write_direct32(priv
, FH_TCSR_CHNL_TX_CONFIG_REG(chan
),
825 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
826 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE
);
828 /* Update FH chicken bits */
829 reg_val
= iwl_read_direct32(priv
, FH_TX_CHICKEN_BITS_REG
);
830 iwl_write_direct32(priv
, FH_TX_CHICKEN_BITS_REG
,
831 reg_val
| FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN
);
833 iwl_write_prph(priv
, SCD_QUEUECHAIN_SEL
,
834 SCD_QUEUECHAIN_SEL_ALL(priv
));
835 iwl_write_prph(priv
, SCD_AGGR_SEL
, 0);
837 /* initiate the queues */
838 for (i
= 0; i
< hw_params(priv
).max_txq_num
; i
++) {
839 iwl_write_prph(priv
, SCD_QUEUE_RDPTR(i
), 0);
840 iwl_write_direct32(priv
, HBUS_TARG_WRPTR
, 0 | (i
<< 8));
841 iwl_write_targ_mem(priv
, trans_pcie
->scd_base_addr
+
842 SCD_CONTEXT_QUEUE_OFFSET(i
), 0);
843 iwl_write_targ_mem(priv
, trans_pcie
->scd_base_addr
+
844 SCD_CONTEXT_QUEUE_OFFSET(i
) +
847 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS
) &
848 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK
) |
850 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS
) &
851 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK
));
854 iwl_write_prph(priv
, SCD_INTERRUPT_MASK
,
855 IWL_MASK(0, hw_params(trans
).max_txq_num
));
857 /* Activate all Tx DMA/FIFO channels */
858 iwl_trans_txq_set_sched(priv
, IWL_MASK(0, 7));
860 /* map queues to FIFOs */
861 if (priv
->valid_contexts
!= BIT(IWL_RXON_CTX_BSS
))
862 queue_to_fifo
= iwlagn_ipan_queue_to_tx_fifo
;
864 queue_to_fifo
= iwlagn_default_queue_to_tx_fifo
;
866 iwl_trans_set_wr_ptrs(priv
, priv
->shrd
->cmd_queue
, 0);
868 /* make sure all queue are not stopped */
869 memset(&priv
->queue_stopped
[0], 0, sizeof(priv
->queue_stopped
));
870 for (i
= 0; i
< 4; i
++)
871 atomic_set(&priv
->queue_stop_count
[i
], 0);
872 for_each_context(priv
, ctx
)
873 ctx
->last_tx_rejected
= false;
875 /* reset to 0 to enable all the queue first */
876 priv
->txq_ctx_active_msk
= 0;
878 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo
) <
879 IWLAGN_FIRST_AMPDU_QUEUE
);
880 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo
) <
881 IWLAGN_FIRST_AMPDU_QUEUE
);
883 for (i
= 0; i
< IWLAGN_FIRST_AMPDU_QUEUE
; i
++) {
884 int fifo
= queue_to_fifo
[i
].fifo
;
885 int ac
= queue_to_fifo
[i
].ac
;
887 iwl_txq_ctx_activate(priv
, i
);
889 if (fifo
== IWL_TX_FIFO_UNUSED
)
892 if (ac
!= IWL_AC_UNSET
)
893 iwl_set_swq_id(&priv
->txq
[i
], ac
, i
);
894 iwl_trans_tx_queue_set_status(priv
, &priv
->txq
[i
], fifo
, 0);
897 spin_unlock_irqrestore(&priv
->shrd
->lock
, flags
);
899 /* Enable L1-Active */
900 iwl_clear_bits_prph(priv
, APMG_PCIDEV_STT_REG
,
901 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
905 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
907 static int iwl_trans_tx_stop(struct iwl_priv
*priv
)
912 /* Turn off all Tx DMA fifos */
913 spin_lock_irqsave(&priv
->shrd
->lock
, flags
);
915 iwl_trans_txq_set_sched(priv
, 0);
917 /* Stop each Tx DMA channel, and wait for it to be idle */
918 for (ch
= 0; ch
< FH_TCSR_CHNL_NUM
; ch
++) {
919 iwl_write_direct32(priv
, FH_TCSR_CHNL_TX_CONFIG_REG(ch
), 0x0);
920 if (iwl_poll_direct_bit(priv
, FH_TSSR_TX_STATUS_REG
,
921 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch
),
923 IWL_ERR(priv
, "Failing on timeout while stopping"
924 " DMA channel %d [0x%08x]", ch
,
925 iwl_read_direct32(priv
, FH_TSSR_TX_STATUS_REG
));
927 spin_unlock_irqrestore(&priv
->shrd
->lock
, flags
);
930 IWL_WARN(priv
, "Stopping tx queues that aren't allocated...");
934 /* Unmap DMA from host system and free skb's */
935 for (txq_id
= 0; txq_id
< hw_params(priv
).max_txq_num
; txq_id
++)
936 iwl_tx_queue_unmap(priv
, txq_id
);
941 static void iwl_trans_pcie_stop_device(struct iwl_priv
*priv
)
943 /* stop and reset the on-board processor */
944 iwl_write32(priv
, CSR_RESET
, CSR_RESET_REG_FLAG_NEVO_RESET
);
946 /* tell the device to stop sending interrupts */
947 iwl_trans_disable_sync_irq(trans(priv
));
949 /* device going down, Stop using ICT table */
950 iwl_disable_ict(trans(priv
));
953 * If a HW restart happens during firmware loading,
954 * then the firmware loading might call this function
955 * and later it might be called again due to the
956 * restart. So don't process again if the device is
959 if (test_bit(STATUS_DEVICE_ENABLED
, &priv
->shrd
->status
)) {
960 iwl_trans_tx_stop(priv
);
961 iwl_trans_rx_stop(priv
);
963 /* Power-down device's busmaster DMA clocks */
964 iwl_write_prph(priv
, APMG_CLK_DIS_REG
,
965 APMG_CLK_VAL_DMA_CLK_RQT
);
969 /* Make sure (redundant) we've released our request to stay awake */
970 iwl_clear_bit(priv
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
972 /* Stop the device, and put it in low power state */
976 static struct iwl_tx_cmd
*iwl_trans_pcie_get_tx_cmd(struct iwl_priv
*priv
,
979 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
980 struct iwl_queue
*q
= &txq
->q
;
981 struct iwl_device_cmd
*dev_cmd
;
983 if (unlikely(iwl_queue_space(q
) < q
->high_mark
))
987 * Set up the Tx-command (not MAC!) header.
988 * Store the chosen Tx queue and TFD index within the sequence field;
989 * after Tx, uCode's Tx response will return this value so driver can
990 * locate the frame within the tx queue and do post-tx processing.
992 dev_cmd
= txq
->cmd
[q
->write_ptr
];
993 memset(dev_cmd
, 0, sizeof(*dev_cmd
));
994 dev_cmd
->hdr
.cmd
= REPLY_TX
;
995 dev_cmd
->hdr
.sequence
= cpu_to_le16((u16
)(QUEUE_TO_SEQ(txq_id
) |
996 INDEX_TO_SEQ(q
->write_ptr
)));
997 return &dev_cmd
->cmd
.tx
;
1000 static int iwl_trans_pcie_tx(struct iwl_priv
*priv
, struct sk_buff
*skb
,
1001 struct iwl_tx_cmd
*tx_cmd
, int txq_id
, __le16 fc
, bool ampdu
,
1002 struct iwl_rxon_context
*ctx
)
1004 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
1005 struct iwl_queue
*q
= &txq
->q
;
1006 struct iwl_device_cmd
*dev_cmd
= txq
->cmd
[q
->write_ptr
];
1007 struct iwl_cmd_meta
*out_meta
;
1009 dma_addr_t phys_addr
= 0;
1010 dma_addr_t txcmd_phys
;
1011 dma_addr_t scratch_phys
;
1012 u16 len
, firstlen
, secondlen
;
1013 u8 wait_write_ptr
= 0;
1014 u8 hdr_len
= ieee80211_hdrlen(fc
);
1016 /* Set up driver data for this TFD */
1017 memset(&(txq
->txb
[q
->write_ptr
]), 0, sizeof(struct iwl_tx_info
));
1018 txq
->txb
[q
->write_ptr
].skb
= skb
;
1019 txq
->txb
[q
->write_ptr
].ctx
= ctx
;
1021 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1022 out_meta
= &txq
->meta
[q
->write_ptr
];
1025 * Use the first empty entry in this queue's command buffer array
1026 * to contain the Tx command and MAC header concatenated together
1027 * (payload data will be in another buffer).
1028 * Size of this varies, due to varying MAC header length.
1029 * If end is not dword aligned, we'll have 2 extra bytes at the end
1030 * of the MAC header (device reads on dword boundaries).
1031 * We'll tell device about this padding later.
1033 len
= sizeof(struct iwl_tx_cmd
) +
1034 sizeof(struct iwl_cmd_header
) + hdr_len
;
1035 firstlen
= (len
+ 3) & ~3;
1037 /* Tell NIC about any 2-byte padding after MAC header */
1038 if (firstlen
!= len
)
1039 tx_cmd
->tx_flags
|= TX_CMD_FLG_MH_PAD_MSK
;
1041 /* Physical address of this Tx command's header (not MAC header!),
1042 * within command buffer array. */
1043 txcmd_phys
= dma_map_single(priv
->bus
->dev
,
1044 &dev_cmd
->hdr
, firstlen
,
1046 if (unlikely(dma_mapping_error(priv
->bus
->dev
, txcmd_phys
)))
1048 dma_unmap_addr_set(out_meta
, mapping
, txcmd_phys
);
1049 dma_unmap_len_set(out_meta
, len
, firstlen
);
1051 if (!ieee80211_has_morefrags(fc
)) {
1052 txq
->need_update
= 1;
1055 txq
->need_update
= 0;
1058 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1059 * if any (802.11 null frames have no payload). */
1060 secondlen
= skb
->len
- hdr_len
;
1061 if (secondlen
> 0) {
1062 phys_addr
= dma_map_single(priv
->bus
->dev
, skb
->data
+ hdr_len
,
1063 secondlen
, DMA_TO_DEVICE
);
1064 if (unlikely(dma_mapping_error(priv
->bus
->dev
, phys_addr
))) {
1065 dma_unmap_single(priv
->bus
->dev
,
1066 dma_unmap_addr(out_meta
, mapping
),
1067 dma_unmap_len(out_meta
, len
),
1073 /* Attach buffers to TFD */
1074 iwlagn_txq_attach_buf_to_tfd(priv
, txq
, txcmd_phys
, firstlen
, 1);
1076 iwlagn_txq_attach_buf_to_tfd(priv
, txq
, phys_addr
,
1079 scratch_phys
= txcmd_phys
+ sizeof(struct iwl_cmd_header
) +
1080 offsetof(struct iwl_tx_cmd
, scratch
);
1082 /* take back ownership of DMA buffer to enable update */
1083 dma_sync_single_for_cpu(priv
->bus
->dev
, txcmd_phys
, firstlen
,
1085 tx_cmd
->dram_lsb_ptr
= cpu_to_le32(scratch_phys
);
1086 tx_cmd
->dram_msb_ptr
= iwl_get_dma_hi_addr(scratch_phys
);
1088 IWL_DEBUG_TX(priv
, "sequence nr = 0X%x\n",
1089 le16_to_cpu(dev_cmd
->hdr
.sequence
));
1090 IWL_DEBUG_TX(priv
, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd
->tx_flags
));
1091 iwl_print_hex_dump(priv
, IWL_DL_TX
, (u8
*)tx_cmd
, sizeof(*tx_cmd
));
1092 iwl_print_hex_dump(priv
, IWL_DL_TX
, (u8
*)tx_cmd
->hdr
, hdr_len
);
1094 /* Set up entry for this TFD in Tx byte-count array */
1096 iwl_trans_txq_update_byte_cnt_tbl(priv
, txq
,
1097 le16_to_cpu(tx_cmd
->len
));
1099 dma_sync_single_for_device(priv
->bus
->dev
, txcmd_phys
, firstlen
,
1102 trace_iwlwifi_dev_tx(priv
,
1103 &((struct iwl_tfd
*)txq
->tfds
)[txq
->q
.write_ptr
],
1104 sizeof(struct iwl_tfd
),
1105 &dev_cmd
->hdr
, firstlen
,
1106 skb
->data
+ hdr_len
, secondlen
);
1108 /* Tell device the write index *just past* this latest filled TFD */
1109 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
1110 iwl_txq_update_write_ptr(priv
, txq
);
1113 * At this point the frame is "transmitted" successfully
1114 * and we will get a TX status notification eventually,
1115 * regardless of the value of ret. "ret" only indicates
1116 * whether or not we should update the write pointer.
1118 if (iwl_queue_space(q
) < q
->high_mark
) {
1119 if (wait_write_ptr
) {
1120 txq
->need_update
= 1;
1121 iwl_txq_update_write_ptr(priv
, txq
);
1123 iwl_stop_queue(priv
, txq
);
1129 static void iwl_trans_pcie_kick_nic(struct iwl_priv
*priv
)
1131 /* Remove all resets to allow NIC to operate */
1132 iwl_write32(priv
, CSR_RESET
, 0);
1135 static int iwl_trans_pcie_request_irq(struct iwl_trans
*trans
)
1137 struct iwl_trans_pcie
*trans_pcie
=
1138 IWL_TRANS_GET_PCIE_TRANS(trans
);
1141 trans_pcie
->inta_mask
= CSR_INI_SET_MASK
;
1143 tasklet_init(&trans_pcie
->irq_tasklet
, (void (*)(unsigned long))
1144 iwl_irq_tasklet
, (unsigned long)trans
);
1146 iwl_alloc_isr_ict(trans
);
1148 err
= request_irq(bus(trans
)->irq
, iwl_isr_ict
, IRQF_SHARED
,
1151 IWL_ERR(trans
, "Error allocating IRQ %d\n", bus(trans
)->irq
);
1152 iwl_free_isr_ict(trans
);
1156 INIT_WORK(&trans_pcie
->rx_replenish
, iwl_bg_rx_replenish
);
1160 static void iwl_trans_pcie_reclaim(struct iwl_trans
*trans
, int txq_id
,
1161 int ssn
, u32 status
, struct sk_buff_head
*skbs
)
1163 struct iwl_priv
*priv
= priv(trans
);
1164 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
1165 /* n_bd is usually 256 => n_bd - 1 = 0xff */
1166 int tfd_num
= ssn
& (txq
->q
.n_bd
- 1);
1170 if (txq
->sched_retry
) {
1172 priv
->stations
[txq
->sta_id
].tid
[txq
->tid
].agg
.state
;
1173 cond
= (agg_state
!= IWL_EMPTYING_HW_QUEUE_DELBA
);
1175 cond
= (status
!= TX_STATUS_FAIL_PASSIVE_NO_RX
);
1178 if (txq
->q
.read_ptr
!= tfd_num
) {
1179 IWL_DEBUG_TX_REPLY(trans
, "Retry scheduler reclaim "
1180 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1181 ssn
, tfd_num
, txq_id
, txq
->swq_id
);
1182 iwl_tx_queue_reclaim(trans
, txq_id
, tfd_num
, skbs
);
1183 if (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
&& cond
)
1184 iwl_wake_queue(priv
, txq
);
1188 static void iwl_trans_pcie_disable_sync_irq(struct iwl_trans
*trans
)
1190 unsigned long flags
;
1191 struct iwl_trans_pcie
*trans_pcie
=
1192 IWL_TRANS_GET_PCIE_TRANS(trans
);
1194 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
1195 iwl_disable_interrupts(trans
);
1196 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
1198 /* wait to make sure we flush pending tasklet*/
1199 synchronize_irq(bus(trans
)->irq
);
1200 tasklet_kill(&trans_pcie
->irq_tasklet
);
1203 static void iwl_trans_pcie_free(struct iwl_priv
*priv
)
1205 free_irq(priv
->bus
->irq
, trans(priv
));
1206 iwl_free_isr_ict(trans(priv
));
1213 static int iwl_trans_pcie_suspend(struct iwl_trans
*trans
)
1216 * This function is called when system goes into suspend state
1217 * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
1218 * first but since iwl_mac_stop() has no knowledge of who the caller is,
1219 * it will not call apm_ops.stop() to stop the DMA operation.
1220 * Calling apm_ops.stop here to make sure we stop the DMA.
1222 * But of course ... if we have configured WoWLAN then we did other
1223 * things already :-)
1225 if (!trans
->shrd
->wowlan
)
1226 iwl_apm_stop(priv(trans
));
1231 static int iwl_trans_pcie_resume(struct iwl_trans
*trans
)
1233 bool hw_rfkill
= false;
1235 iwl_enable_interrupts(trans
);
1237 if (!(iwl_read32(priv(trans
), CSR_GP_CNTRL
) &
1238 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW
))
1242 set_bit(STATUS_RF_KILL_HW
, &trans
->shrd
->status
);
1244 clear_bit(STATUS_RF_KILL_HW
, &trans
->shrd
->status
);
1246 wiphy_rfkill_set_hw_state(priv(trans
)->hw
->wiphy
, hw_rfkill
);
1250 #else /* CONFIG_PM */
1251 static int iwl_trans_pcie_suspend(struct iwl_trans
*trans
)
1254 static int iwl_trans_pcie_resume(struct iwl_trans
*trans
)
1257 #endif /* CONFIG_PM */
1259 const struct iwl_trans_ops trans_ops_pcie
;
1261 static struct iwl_trans
*iwl_trans_pcie_alloc(struct iwl_shared
*shrd
)
1263 struct iwl_trans
*iwl_trans
= kzalloc(sizeof(struct iwl_trans
) +
1264 sizeof(struct iwl_trans_pcie
),
1267 struct iwl_trans_pcie
*trans_pcie
=
1268 IWL_TRANS_GET_PCIE_TRANS(iwl_trans
);
1269 iwl_trans
->ops
= &trans_ops_pcie
;
1270 iwl_trans
->shrd
= shrd
;
1271 trans_pcie
->trans
= iwl_trans
;
1277 #ifdef CONFIG_IWLWIFI_DEBUGFS
1278 /* create and remove of files */
1279 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1280 if (!debugfs_create_file(#name, mode, parent, trans, \
1281 &iwl_dbgfs_##name##_ops)) \
1285 /* file operation */
1286 #define DEBUGFS_READ_FUNC(name) \
1287 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1288 char __user *user_buf, \
1289 size_t count, loff_t *ppos);
1291 #define DEBUGFS_WRITE_FUNC(name) \
1292 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1293 const char __user *user_buf, \
1294 size_t count, loff_t *ppos);
1297 static int iwl_dbgfs_open_file_generic(struct inode
*inode
, struct file
*file
)
1299 file
->private_data
= inode
->i_private
;
1303 #define DEBUGFS_READ_FILE_OPS(name) \
1304 DEBUGFS_READ_FUNC(name); \
1305 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1306 .read = iwl_dbgfs_##name##_read, \
1307 .open = iwl_dbgfs_open_file_generic, \
1308 .llseek = generic_file_llseek, \
1311 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1312 DEBUGFS_READ_FUNC(name); \
1313 DEBUGFS_WRITE_FUNC(name); \
1314 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1315 .write = iwl_dbgfs_##name##_write, \
1316 .read = iwl_dbgfs_##name##_read, \
1317 .open = iwl_dbgfs_open_file_generic, \
1318 .llseek = generic_file_llseek, \
1321 static ssize_t
iwl_dbgfs_traffic_log_read(struct file
*file
,
1322 char __user
*user_buf
,
1323 size_t count
, loff_t
*ppos
)
1325 struct iwl_trans
*trans
= file
->private_data
;
1326 struct iwl_priv
*priv
= priv(trans
);
1327 int pos
= 0, ofs
= 0;
1329 struct iwl_trans_pcie
*trans_pcie
=
1330 IWL_TRANS_GET_PCIE_TRANS(trans
);
1331 struct iwl_tx_queue
*txq
;
1332 struct iwl_queue
*q
;
1333 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
1335 int bufsz
= ((IWL_TRAFFIC_ENTRIES
* IWL_TRAFFIC_ENTRY_SIZE
* 64) * 2) +
1336 (priv
->cfg
->base_params
->num_of_queues
* 32 * 8) + 400;
1341 IWL_ERR(trans
, "txq not ready\n");
1344 buf
= kzalloc(bufsz
, GFP_KERNEL
);
1346 IWL_ERR(trans
, "Can not allocate buffer\n");
1349 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Tx Queue\n");
1350 for (cnt
= 0; cnt
< hw_params(trans
).max_txq_num
; cnt
++) {
1351 txq
= &priv
->txq
[cnt
];
1353 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1354 "q[%d]: read_ptr: %u, write_ptr: %u\n",
1355 cnt
, q
->read_ptr
, q
->write_ptr
);
1357 if (priv
->tx_traffic
&&
1358 (iwl_get_debug_level(trans
->shrd
) & IWL_DL_TX
)) {
1359 ptr
= priv
->tx_traffic
;
1360 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1361 "Tx Traffic idx: %u\n", priv
->tx_traffic_idx
);
1362 for (cnt
= 0, ofs
= 0; cnt
< IWL_TRAFFIC_ENTRIES
; cnt
++) {
1363 for (entry
= 0; entry
< IWL_TRAFFIC_ENTRY_SIZE
/ 16;
1364 entry
++, ofs
+= 16) {
1365 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1367 hex_dump_to_buffer(ptr
+ ofs
, 16, 16, 2,
1368 buf
+ pos
, bufsz
- pos
, 0);
1369 pos
+= strlen(buf
+ pos
);
1370 if (bufsz
- pos
> 0)
1376 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Rx Queue\n");
1377 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1378 "read: %u, write: %u\n",
1379 rxq
->read
, rxq
->write
);
1381 if (priv
->rx_traffic
&&
1382 (iwl_get_debug_level(trans
->shrd
) & IWL_DL_RX
)) {
1383 ptr
= priv
->rx_traffic
;
1384 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1385 "Rx Traffic idx: %u\n", priv
->rx_traffic_idx
);
1386 for (cnt
= 0, ofs
= 0; cnt
< IWL_TRAFFIC_ENTRIES
; cnt
++) {
1387 for (entry
= 0; entry
< IWL_TRAFFIC_ENTRY_SIZE
/ 16;
1388 entry
++, ofs
+= 16) {
1389 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1391 hex_dump_to_buffer(ptr
+ ofs
, 16, 16, 2,
1392 buf
+ pos
, bufsz
- pos
, 0);
1393 pos
+= strlen(buf
+ pos
);
1394 if (bufsz
- pos
> 0)
1400 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1405 static ssize_t
iwl_dbgfs_traffic_log_write(struct file
*file
,
1406 const char __user
*user_buf
,
1407 size_t count
, loff_t
*ppos
)
1409 struct iwl_trans
*trans
= file
->private_data
;
1414 memset(buf
, 0, sizeof(buf
));
1415 buf_size
= min(count
, sizeof(buf
) - 1);
1416 if (copy_from_user(buf
, user_buf
, buf_size
))
1418 if (sscanf(buf
, "%d", &traffic_log
) != 1)
1420 if (traffic_log
== 0)
1421 iwl_reset_traffic_log(priv(trans
));
1426 static ssize_t
iwl_dbgfs_tx_queue_read(struct file
*file
,
1427 char __user
*user_buf
,
1428 size_t count
, loff_t
*ppos
) {
1430 struct iwl_trans
*trans
= file
->private_data
;
1431 struct iwl_priv
*priv
= priv(trans
);
1432 struct iwl_tx_queue
*txq
;
1433 struct iwl_queue
*q
;
1438 const size_t bufsz
= sizeof(char) * 64 *
1439 priv
->cfg
->base_params
->num_of_queues
;
1442 IWL_ERR(priv
, "txq not ready\n");
1445 buf
= kzalloc(bufsz
, GFP_KERNEL
);
1449 for (cnt
= 0; cnt
< hw_params(trans
).max_txq_num
; cnt
++) {
1450 txq
= &priv
->txq
[cnt
];
1452 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1453 "hwq %.2d: read=%u write=%u stop=%d"
1454 " swq_id=%#.2x (ac %d/hwq %d)\n",
1455 cnt
, q
->read_ptr
, q
->write_ptr
,
1456 !!test_bit(cnt
, priv
->queue_stopped
),
1457 txq
->swq_id
, txq
->swq_id
& 3,
1458 (txq
->swq_id
>> 2) & 0x1f);
1461 /* for the ACs, display the stop count too */
1462 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1463 " stop-count: %d\n",
1464 atomic_read(&priv
->queue_stop_count
[cnt
]));
1466 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1471 static ssize_t
iwl_dbgfs_rx_queue_read(struct file
*file
,
1472 char __user
*user_buf
,
1473 size_t count
, loff_t
*ppos
) {
1474 struct iwl_trans
*trans
= file
->private_data
;
1475 struct iwl_trans_pcie
*trans_pcie
=
1476 IWL_TRANS_GET_PCIE_TRANS(trans
);
1477 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
1480 const size_t bufsz
= sizeof(buf
);
1482 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "read: %u\n",
1484 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "write: %u\n",
1486 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "free_count: %u\n",
1489 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "closed_rb_num: %u\n",
1490 le16_to_cpu(rxq
->rb_stts
->closed_rb_num
) & 0x0FFF);
1492 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1493 "closed_rb_num: Not Allocated\n");
1495 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1498 static ssize_t
iwl_dbgfs_log_event_read(struct file
*file
,
1499 char __user
*user_buf
,
1500 size_t count
, loff_t
*ppos
)
1502 struct iwl_trans
*trans
= file
->private_data
;
1505 ssize_t ret
= -ENOMEM
;
1507 ret
= pos
= iwl_dump_nic_event_log(priv(trans
), true, &buf
, true);
1509 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1515 static ssize_t
iwl_dbgfs_log_event_write(struct file
*file
,
1516 const char __user
*user_buf
,
1517 size_t count
, loff_t
*ppos
)
1519 struct iwl_trans
*trans
= file
->private_data
;
1524 memset(buf
, 0, sizeof(buf
));
1525 buf_size
= min(count
, sizeof(buf
) - 1);
1526 if (copy_from_user(buf
, user_buf
, buf_size
))
1528 if (sscanf(buf
, "%d", &event_log_flag
) != 1)
1530 if (event_log_flag
== 1)
1531 iwl_dump_nic_event_log(priv(trans
), true, NULL
, false);
1536 static ssize_t
iwl_dbgfs_interrupt_read(struct file
*file
,
1537 char __user
*user_buf
,
1538 size_t count
, loff_t
*ppos
) {
1540 struct iwl_trans
*trans
= file
->private_data
;
1541 struct iwl_trans_pcie
*trans_pcie
=
1542 IWL_TRANS_GET_PCIE_TRANS(trans
);
1543 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
1547 int bufsz
= 24 * 64; /* 24 items * 64 char per item */
1550 buf
= kzalloc(bufsz
, GFP_KERNEL
);
1552 IWL_ERR(trans
, "Can not allocate Buffer\n");
1556 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1557 "Interrupt Statistics Report:\n");
1559 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "HW Error:\t\t\t %u\n",
1561 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "SW Error:\t\t\t %u\n",
1563 if (isr_stats
->sw
|| isr_stats
->hw
) {
1564 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1565 "\tLast Restarting Code: 0x%X\n",
1566 isr_stats
->err_code
);
1568 #ifdef CONFIG_IWLWIFI_DEBUG
1569 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Frame transmitted:\t\t %u\n",
1571 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Alive interrupt:\t\t %u\n",
1574 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1575 "HW RF KILL switch toggled:\t %u\n", isr_stats
->rfkill
);
1577 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "CT KILL:\t\t\t %u\n",
1580 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Wakeup Interrupt:\t\t %u\n",
1583 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1584 "Rx command responses:\t\t %u\n", isr_stats
->rx
);
1586 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Tx/FH interrupt:\t\t %u\n",
1589 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Unexpected INTA:\t\t %u\n",
1590 isr_stats
->unhandled
);
1592 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1597 static ssize_t
iwl_dbgfs_interrupt_write(struct file
*file
,
1598 const char __user
*user_buf
,
1599 size_t count
, loff_t
*ppos
)
1601 struct iwl_trans
*trans
= file
->private_data
;
1602 struct iwl_trans_pcie
*trans_pcie
=
1603 IWL_TRANS_GET_PCIE_TRANS(trans
);
1604 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
1610 memset(buf
, 0, sizeof(buf
));
1611 buf_size
= min(count
, sizeof(buf
) - 1);
1612 if (copy_from_user(buf
, user_buf
, buf_size
))
1614 if (sscanf(buf
, "%x", &reset_flag
) != 1)
1616 if (reset_flag
== 0)
1617 memset(isr_stats
, 0, sizeof(*isr_stats
));
1622 DEBUGFS_READ_WRITE_FILE_OPS(traffic_log
);
1623 DEBUGFS_READ_WRITE_FILE_OPS(log_event
);
1624 DEBUGFS_READ_WRITE_FILE_OPS(interrupt
);
1625 DEBUGFS_READ_FILE_OPS(rx_queue
);
1626 DEBUGFS_READ_FILE_OPS(tx_queue
);
1629 * Create the debugfs files and directories
1632 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans
*trans
,
1635 DEBUGFS_ADD_FILE(traffic_log
, dir
, S_IWUSR
| S_IRUSR
);
1636 DEBUGFS_ADD_FILE(rx_queue
, dir
, S_IRUSR
);
1637 DEBUGFS_ADD_FILE(tx_queue
, dir
, S_IRUSR
);
1638 DEBUGFS_ADD_FILE(log_event
, dir
, S_IWUSR
| S_IRUSR
);
1639 DEBUGFS_ADD_FILE(interrupt
, dir
, S_IWUSR
| S_IRUSR
);
1643 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans
*trans
,
1647 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1649 const struct iwl_trans_ops trans_ops_pcie
= {
1650 .alloc
= iwl_trans_pcie_alloc
,
1651 .request_irq
= iwl_trans_pcie_request_irq
,
1652 .start_device
= iwl_trans_pcie_start_device
,
1653 .prepare_card_hw
= iwl_trans_pcie_prepare_card_hw
,
1654 .stop_device
= iwl_trans_pcie_stop_device
,
1656 .tx_start
= iwl_trans_pcie_tx_start
,
1658 .rx_free
= iwl_trans_pcie_rx_free
,
1659 .tx_free
= iwl_trans_pcie_tx_free
,
1661 .send_cmd
= iwl_trans_pcie_send_cmd
,
1662 .send_cmd_pdu
= iwl_trans_pcie_send_cmd_pdu
,
1664 .get_tx_cmd
= iwl_trans_pcie_get_tx_cmd
,
1665 .tx
= iwl_trans_pcie_tx
,
1666 .reclaim
= iwl_trans_pcie_reclaim
,
1668 .txq_agg_disable
= iwl_trans_pcie_txq_agg_disable
,
1669 .txq_agg_setup
= iwl_trans_pcie_txq_agg_setup
,
1671 .kick_nic
= iwl_trans_pcie_kick_nic
,
1673 .disable_sync_irq
= iwl_trans_pcie_disable_sync_irq
,
1674 .free
= iwl_trans_pcie_free
,
1676 .dbgfs_register
= iwl_trans_pcie_dbgfs_register
,
1677 .suspend
= iwl_trans_pcie_suspend
,
1678 .resume
= iwl_trans_pcie_resume
,