1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *****************************************************************************/
63 #include <linux/interrupt.h>
64 #include <linux/debugfs.h>
65 #include <linux/bitops.h>
66 #include <linux/gfp.h>
69 #include "iwl-trans.h"
71 #include "iwl-helpers.h"
72 #include "iwl-trans-int-pcie.h"
73 /*TODO remove uneeded includes when the transport layer tx_free will be here */
75 #include "iwl-shared.h"
77 static int iwl_trans_rx_alloc(struct iwl_trans
*trans
)
79 struct iwl_trans_pcie
*trans_pcie
=
80 IWL_TRANS_GET_PCIE_TRANS(trans
);
81 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
82 struct device
*dev
= bus(trans
)->dev
;
84 memset(&trans_pcie
->rxq
, 0, sizeof(trans_pcie
->rxq
));
86 spin_lock_init(&rxq
->lock
);
87 INIT_LIST_HEAD(&rxq
->rx_free
);
88 INIT_LIST_HEAD(&rxq
->rx_used
);
90 if (WARN_ON(rxq
->bd
|| rxq
->rb_stts
))
93 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
94 rxq
->bd
= dma_alloc_coherent(dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
95 &rxq
->bd_dma
, GFP_KERNEL
);
98 memset(rxq
->bd
, 0, sizeof(__le32
) * RX_QUEUE_SIZE
);
100 /*Allocate the driver's pointer to receive buffer status */
101 rxq
->rb_stts
= dma_alloc_coherent(dev
, sizeof(*rxq
->rb_stts
),
102 &rxq
->rb_stts_dma
, GFP_KERNEL
);
105 memset(rxq
->rb_stts
, 0, sizeof(*rxq
->rb_stts
));
110 dma_free_coherent(dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
111 rxq
->bd
, rxq
->bd_dma
);
112 memset(&rxq
->bd_dma
, 0, sizeof(rxq
->bd_dma
));
118 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans
*trans
)
120 struct iwl_trans_pcie
*trans_pcie
=
121 IWL_TRANS_GET_PCIE_TRANS(trans
);
122 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
125 /* Fill the rx_used queue with _all_ of the Rx buffers */
126 for (i
= 0; i
< RX_FREE_BUFFERS
+ RX_QUEUE_SIZE
; i
++) {
127 /* In the reset function, these buffers may have been allocated
128 * to an SKB, so we need to unmap and free potential storage */
129 if (rxq
->pool
[i
].page
!= NULL
) {
130 dma_unmap_page(bus(trans
)->dev
, rxq
->pool
[i
].page_dma
,
131 PAGE_SIZE
<< hw_params(trans
).rx_page_order
,
133 __free_pages(rxq
->pool
[i
].page
,
134 hw_params(trans
).rx_page_order
);
135 rxq
->pool
[i
].page
= NULL
;
137 list_add_tail(&rxq
->pool
[i
].list
, &rxq
->rx_used
);
141 static void iwl_trans_rx_hw_init(struct iwl_trans
*trans
,
142 struct iwl_rx_queue
*rxq
)
145 const u32 rfdnlog
= RX_QUEUE_SIZE_LOG
; /* 256 RBDs */
146 u32 rb_timeout
= 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
148 rb_timeout
= RX_RB_TIMEOUT
;
150 if (iwlagn_mod_params
.amsdu_size_8K
)
151 rb_size
= FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K
;
153 rb_size
= FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K
;
156 iwl_write_direct32(bus(trans
), FH_MEM_RCSR_CHNL0_CONFIG_REG
, 0);
158 /* Reset driver's Rx queue write index */
159 iwl_write_direct32(bus(trans
), FH_RSCSR_CHNL0_RBDCB_WPTR_REG
, 0);
161 /* Tell device where to find RBD circular buffer in DRAM */
162 iwl_write_direct32(bus(trans
), FH_RSCSR_CHNL0_RBDCB_BASE_REG
,
163 (u32
)(rxq
->bd_dma
>> 8));
165 /* Tell device where in DRAM to update its Rx status */
166 iwl_write_direct32(bus(trans
), FH_RSCSR_CHNL0_STTS_WPTR_REG
,
167 rxq
->rb_stts_dma
>> 4);
170 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
171 * the credit mechanism in 5000 HW RX FIFO
172 * Direct rx interrupts to hosts
173 * Rx buffer size 4 or 8k
177 iwl_write_direct32(bus(trans
), FH_MEM_RCSR_CHNL0_CONFIG_REG
,
178 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL
|
179 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY
|
180 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL
|
181 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK
|
183 (rb_timeout
<< FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS
)|
184 (rfdnlog
<< FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS
));
186 /* Set interrupt coalescing timer to default (2048 usecs) */
187 iwl_write8(bus(trans
), CSR_INT_COALESCING
, IWL_HOST_INT_TIMEOUT_DEF
);
190 static int iwl_rx_init(struct iwl_trans
*trans
)
192 struct iwl_trans_pcie
*trans_pcie
=
193 IWL_TRANS_GET_PCIE_TRANS(trans
);
194 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
200 err
= iwl_trans_rx_alloc(trans
);
205 spin_lock_irqsave(&rxq
->lock
, flags
);
206 INIT_LIST_HEAD(&rxq
->rx_free
);
207 INIT_LIST_HEAD(&rxq
->rx_used
);
209 iwl_trans_rxq_free_rx_bufs(trans
);
211 for (i
= 0; i
< RX_QUEUE_SIZE
; i
++)
212 rxq
->queue
[i
] = NULL
;
214 /* Set us so that we have processed and used all buffers, but have
215 * not restocked the Rx queue with fresh buffers */
216 rxq
->read
= rxq
->write
= 0;
217 rxq
->write_actual
= 0;
219 spin_unlock_irqrestore(&rxq
->lock
, flags
);
221 iwlagn_rx_replenish(trans
);
223 iwl_trans_rx_hw_init(trans
, rxq
);
225 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
226 rxq
->need_update
= 1;
227 iwl_rx_queue_update_write_ptr(trans
, rxq
);
228 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
233 static void iwl_trans_pcie_rx_free(struct iwl_trans
*trans
)
235 struct iwl_trans_pcie
*trans_pcie
=
236 IWL_TRANS_GET_PCIE_TRANS(trans
);
237 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
241 /*if rxq->bd is NULL, it means that nothing has been allocated,
244 IWL_DEBUG_INFO(trans
, "Free NULL rx context\n");
248 spin_lock_irqsave(&rxq
->lock
, flags
);
249 iwl_trans_rxq_free_rx_bufs(trans
);
250 spin_unlock_irqrestore(&rxq
->lock
, flags
);
252 dma_free_coherent(bus(trans
)->dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
253 rxq
->bd
, rxq
->bd_dma
);
254 memset(&rxq
->bd_dma
, 0, sizeof(rxq
->bd_dma
));
258 dma_free_coherent(bus(trans
)->dev
,
259 sizeof(struct iwl_rb_status
),
260 rxq
->rb_stts
, rxq
->rb_stts_dma
);
262 IWL_DEBUG_INFO(trans
, "Free rxq->rb_stts which is NULL\n");
263 memset(&rxq
->rb_stts_dma
, 0, sizeof(rxq
->rb_stts_dma
));
267 static int iwl_trans_rx_stop(struct iwl_trans
*trans
)
271 iwl_write_direct32(bus(trans
), FH_MEM_RCSR_CHNL0_CONFIG_REG
, 0);
272 return iwl_poll_direct_bit(bus(trans
), FH_MEM_RSSR_RX_STATUS_REG
,
273 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE
, 1000);
276 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans
*trans
,
277 struct iwl_dma_ptr
*ptr
, size_t size
)
279 if (WARN_ON(ptr
->addr
))
282 ptr
->addr
= dma_alloc_coherent(bus(trans
)->dev
, size
,
283 &ptr
->dma
, GFP_KERNEL
);
290 static inline void iwlagn_free_dma_ptr(struct iwl_trans
*trans
,
291 struct iwl_dma_ptr
*ptr
)
293 if (unlikely(!ptr
->addr
))
296 dma_free_coherent(bus(trans
)->dev
, ptr
->size
, ptr
->addr
, ptr
->dma
);
297 memset(ptr
, 0, sizeof(*ptr
));
300 static int iwl_trans_txq_alloc(struct iwl_trans
*trans
,
301 struct iwl_tx_queue
*txq
, int slots_num
,
304 size_t tfd_sz
= sizeof(struct iwl_tfd
) * TFD_QUEUE_SIZE_MAX
;
307 if (WARN_ON(txq
->meta
|| txq
->cmd
|| txq
->skbs
|| txq
->tfds
))
310 txq
->q
.n_window
= slots_num
;
312 txq
->meta
= kzalloc(sizeof(txq
->meta
[0]) * slots_num
,
314 txq
->cmd
= kzalloc(sizeof(txq
->cmd
[0]) * slots_num
,
317 if (!txq
->meta
|| !txq
->cmd
)
320 if (txq_id
== trans
->shrd
->cmd_queue
)
321 for (i
= 0; i
< slots_num
; i
++) {
322 txq
->cmd
[i
] = kmalloc(sizeof(struct iwl_device_cmd
),
328 /* Alloc driver data array and TFD circular buffer */
329 /* Driver private data, only for Tx (not command) queues,
330 * not shared with device. */
331 if (txq_id
!= trans
->shrd
->cmd_queue
) {
332 txq
->skbs
= kzalloc(sizeof(txq
->skbs
[0]) *
333 TFD_QUEUE_SIZE_MAX
, GFP_KERNEL
);
335 IWL_ERR(trans
, "kmalloc for auxiliary BD "
336 "structures failed\n");
343 /* Circular buffer of transmit frame descriptors (TFDs),
344 * shared with device */
345 txq
->tfds
= dma_alloc_coherent(bus(trans
)->dev
, tfd_sz
,
346 &txq
->q
.dma_addr
, GFP_KERNEL
);
348 IWL_ERR(trans
, "dma_alloc_coherent(%zd) failed\n", tfd_sz
);
357 /* since txq->cmd has been zeroed,
358 * all non allocated cmd[i] will be NULL */
359 if (txq
->cmd
&& txq_id
== trans
->shrd
->cmd_queue
)
360 for (i
= 0; i
< slots_num
; i
++)
371 static int iwl_trans_txq_init(struct iwl_trans
*trans
, struct iwl_tx_queue
*txq
,
372 int slots_num
, u32 txq_id
)
376 txq
->need_update
= 0;
377 memset(txq
->meta
, 0, sizeof(txq
->meta
[0]) * slots_num
);
380 * For the default queues 0-3, set up the swq_id
381 * already -- all others need to get one later
382 * (if they need one at all).
385 iwl_set_swq_id(txq
, txq_id
, txq_id
);
387 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
388 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
389 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX
& (TFD_QUEUE_SIZE_MAX
- 1));
391 /* Initialize queue's high/low-water marks, and head/tail indexes */
392 ret
= iwl_queue_init(&txq
->q
, TFD_QUEUE_SIZE_MAX
, slots_num
,
398 * Tell nic where to find circular buffer of Tx Frame Descriptors for
399 * given Tx queue, and enable the DMA channel used for that queue.
400 * Circular buffer (TFD queue in DRAM) physical base address */
401 iwl_write_direct32(bus(trans
), FH_MEM_CBBC_QUEUE(txq_id
),
402 txq
->q
.dma_addr
>> 8);
408 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
410 static void iwl_tx_queue_unmap(struct iwl_trans
*trans
, int txq_id
)
412 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
413 struct iwl_tx_queue
*txq
= &trans_pcie
->txq
[txq_id
];
414 struct iwl_queue
*q
= &txq
->q
;
419 while (q
->write_ptr
!= q
->read_ptr
) {
420 /* The read_ptr needs to bound by q->n_window */
421 iwlagn_txq_free_tfd(trans
, txq
, get_cmd_index(q
, q
->read_ptr
));
422 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
);
427 * iwl_tx_queue_free - Deallocate DMA queue.
428 * @txq: Transmit queue to deallocate.
430 * Empty queue by removing and destroying all BD's.
432 * 0-fill, but do not free "txq" descriptor structure.
434 static void iwl_tx_queue_free(struct iwl_trans
*trans
, int txq_id
)
436 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
437 struct iwl_tx_queue
*txq
= &trans_pcie
->txq
[txq_id
];
438 struct device
*dev
= bus(trans
)->dev
;
443 iwl_tx_queue_unmap(trans
, txq_id
);
445 /* De-alloc array of command/tx buffers */
447 if (txq_id
== trans
->shrd
->cmd_queue
)
448 for (i
= 0; i
< txq
->q
.n_window
; i
++)
451 /* De-alloc circular buffer of TFDs */
453 dma_free_coherent(dev
, sizeof(struct iwl_tfd
) *
454 txq
->q
.n_bd
, txq
->tfds
, txq
->q
.dma_addr
);
455 memset(&txq
->q
.dma_addr
, 0, sizeof(txq
->q
.dma_addr
));
458 /* De-alloc array of per-TFD driver data */
462 /* deallocate arrays */
468 /* 0-fill queue descriptor structure */
469 memset(txq
, 0, sizeof(*txq
));
473 * iwl_trans_tx_free - Free TXQ Context
475 * Destroy all TX DMA queues and structures
477 static void iwl_trans_pcie_tx_free(struct iwl_trans
*trans
)
480 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
483 if (trans_pcie
->txq
) {
485 txq_id
< hw_params(trans
).max_txq_num
; txq_id
++)
486 iwl_tx_queue_free(trans
, txq_id
);
489 kfree(trans_pcie
->txq
);
490 trans_pcie
->txq
= NULL
;
492 iwlagn_free_dma_ptr(trans
, &trans_pcie
->kw
);
494 iwlagn_free_dma_ptr(trans
, &trans_pcie
->scd_bc_tbls
);
498 * iwl_trans_tx_alloc - allocate TX context
499 * Allocate all Tx DMA structures and initialize them
504 static int iwl_trans_tx_alloc(struct iwl_trans
*trans
)
507 int txq_id
, slots_num
;
508 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
510 u16 scd_bc_tbls_size
= hw_params(trans
).max_txq_num
*
511 sizeof(struct iwlagn_scd_bc_tbl
);
513 /*It is not allowed to alloc twice, so warn when this happens.
514 * We cannot rely on the previous allocation, so free and fail */
515 if (WARN_ON(trans_pcie
->txq
)) {
520 ret
= iwlagn_alloc_dma_ptr(trans
, &trans_pcie
->scd_bc_tbls
,
523 IWL_ERR(trans
, "Scheduler BC Table allocation failed\n");
527 /* Alloc keep-warm buffer */
528 ret
= iwlagn_alloc_dma_ptr(trans
, &trans_pcie
->kw
, IWL_KW_SIZE
);
530 IWL_ERR(trans
, "Keep Warm allocation failed\n");
534 trans_pcie
->txq
= kzalloc(sizeof(struct iwl_tx_queue
) *
535 hw_params(trans
).max_txq_num
, GFP_KERNEL
);
536 if (!trans_pcie
->txq
) {
537 IWL_ERR(trans
, "Not enough memory for txq\n");
542 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
543 for (txq_id
= 0; txq_id
< hw_params(trans
).max_txq_num
; txq_id
++) {
544 slots_num
= (txq_id
== trans
->shrd
->cmd_queue
) ?
545 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
546 ret
= iwl_trans_txq_alloc(trans
, &trans_pcie
->txq
[txq_id
],
549 IWL_ERR(trans
, "Tx %d queue alloc failed\n", txq_id
);
557 iwl_trans_pcie_tx_free(trans
);
561 static int iwl_tx_init(struct iwl_trans
*trans
)
564 int txq_id
, slots_num
;
567 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
569 if (!trans_pcie
->txq
) {
570 ret
= iwl_trans_tx_alloc(trans
);
576 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
578 /* Turn off all Tx DMA fifos */
579 iwl_write_prph(bus(trans
), SCD_TXFACT
, 0);
581 /* Tell NIC where to find the "keep warm" buffer */
582 iwl_write_direct32(bus(trans
), FH_KW_MEM_ADDR_REG
,
583 trans_pcie
->kw
.dma
>> 4);
585 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
587 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
588 for (txq_id
= 0; txq_id
< hw_params(trans
).max_txq_num
; txq_id
++) {
589 slots_num
= (txq_id
== trans
->shrd
->cmd_queue
) ?
590 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
591 ret
= iwl_trans_txq_init(trans
, &trans_pcie
->txq
[txq_id
],
594 IWL_ERR(trans
, "Tx %d queue init failed\n", txq_id
);
601 /*Upon error, free only if we allocated something */
603 iwl_trans_pcie_tx_free(trans
);
607 static void iwl_set_pwr_vmain(struct iwl_priv
*priv
)
609 struct iwl_trans
*trans
= trans(priv
);
611 * (for documentation purposes)
612 * to set power to V_AUX, do:
614 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
615 iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
616 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
617 ~APMG_PS_CTRL_MSK_PWR_SRC);
620 iwl_set_bits_mask_prph(bus(trans
), APMG_PS_CTRL_REG
,
621 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN
,
622 ~APMG_PS_CTRL_MSK_PWR_SRC
);
625 static int iwl_nic_init(struct iwl_trans
*trans
)
628 struct iwl_priv
*priv
= priv(trans
);
631 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
634 /* Set interrupt coalescing calibration timer to default (512 usecs) */
635 iwl_write8(bus(trans
), CSR_INT_COALESCING
,
636 IWL_HOST_INT_CALIB_TIMEOUT_DEF
);
638 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
640 iwl_set_pwr_vmain(priv
);
642 priv
->cfg
->lib
->nic_config(priv
);
644 /* Allocate the RX queue, or reset if it is already allocated */
647 /* Allocate or reset and init all Tx and Command queues */
648 if (iwl_tx_init(trans
))
651 if (hw_params(trans
).shadow_reg_enable
) {
652 /* enable shadow regs in HW */
653 iwl_set_bit(bus(trans
), CSR_MAC_SHADOW_REG_CTRL
,
657 set_bit(STATUS_INIT
, &trans
->shrd
->status
);
662 #define HW_READY_TIMEOUT (50)
664 /* Note: returns poll_bit return value, which is >= 0 if success */
665 static int iwl_set_hw_ready(struct iwl_trans
*trans
)
669 iwl_set_bit(bus(trans
), CSR_HW_IF_CONFIG_REG
,
670 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
);
672 /* See if we got it */
673 ret
= iwl_poll_bit(bus(trans
), CSR_HW_IF_CONFIG_REG
,
674 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
675 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
678 IWL_DEBUG_INFO(trans
, "hardware%s ready\n", ret
< 0 ? " not" : "");
682 /* Note: returns standard 0/-ERROR code */
683 static int iwl_trans_pcie_prepare_card_hw(struct iwl_trans
*trans
)
687 IWL_DEBUG_INFO(trans
, "iwl_trans_prepare_card_hw enter\n");
689 ret
= iwl_set_hw_ready(trans
);
693 /* If HW is not ready, prepare the conditions to check again */
694 iwl_set_bit(bus(trans
), CSR_HW_IF_CONFIG_REG
,
695 CSR_HW_IF_CONFIG_REG_PREPARE
);
697 ret
= iwl_poll_bit(bus(trans
), CSR_HW_IF_CONFIG_REG
,
698 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE
,
699 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE
, 150000);
704 /* HW should be ready by now, check again. */
705 ret
= iwl_set_hw_ready(trans
);
711 #define IWL_AC_UNSET -1
713 struct queue_to_fifo_ac
{
717 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo
[] = {
718 { IWL_TX_FIFO_VO
, IEEE80211_AC_VO
, },
719 { IWL_TX_FIFO_VI
, IEEE80211_AC_VI
, },
720 { IWL_TX_FIFO_BE
, IEEE80211_AC_BE
, },
721 { IWL_TX_FIFO_BK
, IEEE80211_AC_BK
, },
722 { IWLAGN_CMD_FIFO_NUM
, IWL_AC_UNSET
, },
723 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
724 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
725 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
726 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
727 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
728 { IWL_TX_FIFO_UNUSED
, IWL_AC_UNSET
, },
731 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo
[] = {
732 { IWL_TX_FIFO_VO
, IEEE80211_AC_VO
, },
733 { IWL_TX_FIFO_VI
, IEEE80211_AC_VI
, },
734 { IWL_TX_FIFO_BE
, IEEE80211_AC_BE
, },
735 { IWL_TX_FIFO_BK
, IEEE80211_AC_BK
, },
736 { IWL_TX_FIFO_BK_IPAN
, IEEE80211_AC_BK
, },
737 { IWL_TX_FIFO_BE_IPAN
, IEEE80211_AC_BE
, },
738 { IWL_TX_FIFO_VI_IPAN
, IEEE80211_AC_VI
, },
739 { IWL_TX_FIFO_VO_IPAN
, IEEE80211_AC_VO
, },
740 { IWL_TX_FIFO_BE_IPAN
, 2, },
741 { IWLAGN_CMD_FIFO_NUM
, IWL_AC_UNSET
, },
742 { IWL_TX_FIFO_AUX
, IWL_AC_UNSET
, },
745 static const u8 iwlagn_bss_ac_to_fifo
[] = {
751 static const u8 iwlagn_bss_ac_to_queue
[] = {
754 static const u8 iwlagn_pan_ac_to_fifo
[] = {
760 static const u8 iwlagn_pan_ac_to_queue
[] = {
764 static int iwl_trans_pcie_start_device(struct iwl_trans
*trans
)
767 struct iwl_priv
*priv
= priv(trans
);
768 struct iwl_trans_pcie
*trans_pcie
=
769 IWL_TRANS_GET_PCIE_TRANS(trans
);
771 trans
->shrd
->ucode_owner
= IWL_OWNERSHIP_DRIVER
;
772 trans_pcie
->ac_to_queue
[IWL_RXON_CTX_BSS
] = iwlagn_bss_ac_to_queue
;
773 trans_pcie
->ac_to_queue
[IWL_RXON_CTX_PAN
] = iwlagn_pan_ac_to_queue
;
775 trans_pcie
->ac_to_fifo
[IWL_RXON_CTX_BSS
] = iwlagn_bss_ac_to_fifo
;
776 trans_pcie
->ac_to_fifo
[IWL_RXON_CTX_PAN
] = iwlagn_pan_ac_to_fifo
;
778 trans_pcie
->mcast_queue
[IWL_RXON_CTX_BSS
] = 0;
779 trans_pcie
->mcast_queue
[IWL_RXON_CTX_PAN
] = IWL_IPAN_MCAST_QUEUE
;
781 if ((hw_params(trans
).sku
& EEPROM_SKU_CAP_AMT_ENABLE
) &&
782 iwl_trans_pcie_prepare_card_hw(trans
)) {
783 IWL_WARN(trans
, "Exit HW not ready\n");
787 /* If platform's RF_KILL switch is NOT set to KILL */
788 if (iwl_read32(bus(trans
), CSR_GP_CNTRL
) &
789 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW
)
790 clear_bit(STATUS_RF_KILL_HW
, &trans
->shrd
->status
);
792 set_bit(STATUS_RF_KILL_HW
, &trans
->shrd
->status
);
794 if (iwl_is_rfkill(trans
->shrd
)) {
795 wiphy_rfkill_set_hw_state(priv
->hw
->wiphy
, true);
796 iwl_enable_interrupts(trans
);
800 iwl_write32(bus(trans
), CSR_INT
, 0xFFFFFFFF);
802 ret
= iwl_nic_init(trans
);
804 IWL_ERR(trans
, "Unable to init nic\n");
808 /* make sure rfkill handshake bits are cleared */
809 iwl_write32(bus(trans
), CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
810 iwl_write32(bus(trans
), CSR_UCODE_DRV_GP1_CLR
,
811 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED
);
813 /* clear (again), then enable host interrupts */
814 iwl_write32(bus(trans
), CSR_INT
, 0xFFFFFFFF);
815 iwl_enable_interrupts(trans
);
817 /* really make sure rfkill handshake bits are cleared */
818 iwl_write32(bus(trans
), CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
819 iwl_write32(bus(trans
), CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
825 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
826 * must be called under priv->shrd->lock and mac access
828 static void iwl_trans_txq_set_sched(struct iwl_trans
*trans
, u32 mask
)
830 iwl_write_prph(bus(trans
), SCD_TXFACT
, mask
);
833 static void iwl_trans_pcie_tx_start(struct iwl_trans
*trans
)
835 const struct queue_to_fifo_ac
*queue_to_fifo
;
836 struct iwl_rxon_context
*ctx
;
837 struct iwl_priv
*priv
= priv(trans
);
838 struct iwl_trans_pcie
*trans_pcie
=
839 IWL_TRANS_GET_PCIE_TRANS(trans
);
845 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
847 trans_pcie
->scd_base_addr
=
848 iwl_read_prph(bus(trans
), SCD_SRAM_BASE_ADDR
);
849 a
= trans_pcie
->scd_base_addr
+ SCD_CONTEXT_MEM_LOWER_BOUND
;
850 /* reset conext data memory */
851 for (; a
< trans_pcie
->scd_base_addr
+ SCD_CONTEXT_MEM_UPPER_BOUND
;
853 iwl_write_targ_mem(bus(trans
), a
, 0);
854 /* reset tx status memory */
855 for (; a
< trans_pcie
->scd_base_addr
+ SCD_TX_STTS_MEM_UPPER_BOUND
;
857 iwl_write_targ_mem(bus(trans
), a
, 0);
858 for (; a
< trans_pcie
->scd_base_addr
+
859 SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans
).max_txq_num
);
861 iwl_write_targ_mem(bus(trans
), a
, 0);
863 iwl_write_prph(bus(trans
), SCD_DRAM_BASE_ADDR
,
864 trans_pcie
->scd_bc_tbls
.dma
>> 10);
866 /* Enable DMA channel */
867 for (chan
= 0; chan
< FH_TCSR_CHNL_NUM
; chan
++)
868 iwl_write_direct32(bus(trans
), FH_TCSR_CHNL_TX_CONFIG_REG(chan
),
869 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
870 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE
);
872 /* Update FH chicken bits */
873 reg_val
= iwl_read_direct32(bus(trans
), FH_TX_CHICKEN_BITS_REG
);
874 iwl_write_direct32(bus(trans
), FH_TX_CHICKEN_BITS_REG
,
875 reg_val
| FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN
);
877 iwl_write_prph(bus(trans
), SCD_QUEUECHAIN_SEL
,
878 SCD_QUEUECHAIN_SEL_ALL(trans
));
879 iwl_write_prph(bus(trans
), SCD_AGGR_SEL
, 0);
881 /* initiate the queues */
882 for (i
= 0; i
< hw_params(trans
).max_txq_num
; i
++) {
883 iwl_write_prph(bus(trans
), SCD_QUEUE_RDPTR(i
), 0);
884 iwl_write_direct32(bus(trans
), HBUS_TARG_WRPTR
, 0 | (i
<< 8));
885 iwl_write_targ_mem(bus(trans
), trans_pcie
->scd_base_addr
+
886 SCD_CONTEXT_QUEUE_OFFSET(i
), 0);
887 iwl_write_targ_mem(bus(trans
), trans_pcie
->scd_base_addr
+
888 SCD_CONTEXT_QUEUE_OFFSET(i
) +
891 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS
) &
892 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK
) |
894 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS
) &
895 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK
));
898 iwl_write_prph(bus(trans
), SCD_INTERRUPT_MASK
,
899 IWL_MASK(0, hw_params(trans
).max_txq_num
));
901 /* Activate all Tx DMA/FIFO channels */
902 iwl_trans_txq_set_sched(trans
, IWL_MASK(0, 7));
904 /* map queues to FIFOs */
905 if (priv
->valid_contexts
!= BIT(IWL_RXON_CTX_BSS
))
906 queue_to_fifo
= iwlagn_ipan_queue_to_tx_fifo
;
908 queue_to_fifo
= iwlagn_default_queue_to_tx_fifo
;
910 iwl_trans_set_wr_ptrs(trans
, trans
->shrd
->cmd_queue
, 0);
912 /* make sure all queue are not stopped */
913 memset(&trans_pcie
->queue_stopped
[0], 0,
914 sizeof(trans_pcie
->queue_stopped
));
915 for (i
= 0; i
< 4; i
++)
916 atomic_set(&trans_pcie
->queue_stop_count
[i
], 0);
917 for_each_context(priv
, ctx
)
918 ctx
->last_tx_rejected
= false;
920 /* reset to 0 to enable all the queue first */
921 trans_pcie
->txq_ctx_active_msk
= 0;
923 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo
) <
924 IWLAGN_FIRST_AMPDU_QUEUE
);
925 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo
) <
926 IWLAGN_FIRST_AMPDU_QUEUE
);
928 for (i
= 0; i
< IWLAGN_FIRST_AMPDU_QUEUE
; i
++) {
929 int fifo
= queue_to_fifo
[i
].fifo
;
930 int ac
= queue_to_fifo
[i
].ac
;
932 iwl_txq_ctx_activate(trans_pcie
, i
);
934 if (fifo
== IWL_TX_FIFO_UNUSED
)
937 if (ac
!= IWL_AC_UNSET
)
938 iwl_set_swq_id(&trans_pcie
->txq
[i
], ac
, i
);
939 iwl_trans_tx_queue_set_status(trans
, &trans_pcie
->txq
[i
],
943 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
945 /* Enable L1-Active */
946 iwl_clear_bits_prph(bus(trans
), APMG_PCIDEV_STT_REG
,
947 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
951 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
953 static int iwl_trans_tx_stop(struct iwl_trans
*trans
)
957 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
959 /* Turn off all Tx DMA fifos */
960 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
962 iwl_trans_txq_set_sched(trans
, 0);
964 /* Stop each Tx DMA channel, and wait for it to be idle */
965 for (ch
= 0; ch
< FH_TCSR_CHNL_NUM
; ch
++) {
966 iwl_write_direct32(bus(trans
),
967 FH_TCSR_CHNL_TX_CONFIG_REG(ch
), 0x0);
968 if (iwl_poll_direct_bit(bus(trans
), FH_TSSR_TX_STATUS_REG
,
969 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch
),
971 IWL_ERR(trans
, "Failing on timeout while stopping"
972 " DMA channel %d [0x%08x]", ch
,
973 iwl_read_direct32(bus(trans
),
974 FH_TSSR_TX_STATUS_REG
));
976 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
978 if (!trans_pcie
->txq
) {
979 IWL_WARN(trans
, "Stopping tx queues that aren't allocated...");
983 /* Unmap DMA from host system and free skb's */
984 for (txq_id
= 0; txq_id
< hw_params(trans
).max_txq_num
; txq_id
++)
985 iwl_tx_queue_unmap(trans
, txq_id
);
990 static void iwl_trans_pcie_disable_sync_irq(struct iwl_trans
*trans
)
993 struct iwl_trans_pcie
*trans_pcie
=
994 IWL_TRANS_GET_PCIE_TRANS(trans
);
996 spin_lock_irqsave(&trans
->shrd
->lock
, flags
);
997 iwl_disable_interrupts(trans
);
998 spin_unlock_irqrestore(&trans
->shrd
->lock
, flags
);
1000 /* wait to make sure we flush pending tasklet*/
1001 synchronize_irq(bus(trans
)->irq
);
1002 tasklet_kill(&trans_pcie
->irq_tasklet
);
1005 static void iwl_trans_pcie_stop_device(struct iwl_trans
*trans
)
1007 /* stop and reset the on-board processor */
1008 iwl_write32(bus(trans
), CSR_RESET
, CSR_RESET_REG_FLAG_NEVO_RESET
);
1010 /* tell the device to stop sending interrupts */
1011 iwl_trans_pcie_disable_sync_irq(trans
);
1013 /* device going down, Stop using ICT table */
1014 iwl_disable_ict(trans
);
1017 * If a HW restart happens during firmware loading,
1018 * then the firmware loading might call this function
1019 * and later it might be called again due to the
1020 * restart. So don't process again if the device is
1023 if (test_bit(STATUS_DEVICE_ENABLED
, &trans
->shrd
->status
)) {
1024 iwl_trans_tx_stop(trans
);
1025 iwl_trans_rx_stop(trans
);
1027 /* Power-down device's busmaster DMA clocks */
1028 iwl_write_prph(bus(trans
), APMG_CLK_DIS_REG
,
1029 APMG_CLK_VAL_DMA_CLK_RQT
);
1033 /* Make sure (redundant) we've released our request to stay awake */
1034 iwl_clear_bit(bus(trans
), CSR_GP_CNTRL
,
1035 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1037 /* Stop the device, and put it in low power state */
1038 iwl_apm_stop(priv(trans
));
1041 static int iwl_trans_pcie_tx(struct iwl_trans
*trans
, struct sk_buff
*skb
,
1042 struct iwl_device_cmd
*dev_cmd
, u8 ctx
, u8 sta_id
)
1044 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1045 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1046 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1047 struct iwl_tx_cmd
*tx_cmd
= &dev_cmd
->cmd
.tx
;
1048 struct iwl_cmd_meta
*out_meta
;
1049 struct iwl_tx_queue
*txq
;
1050 struct iwl_queue
*q
;
1052 dma_addr_t phys_addr
= 0;
1053 dma_addr_t txcmd_phys
;
1054 dma_addr_t scratch_phys
;
1055 u16 len
, firstlen
, secondlen
;
1057 u8 wait_write_ptr
= 0;
1060 bool is_agg
= false;
1061 __le16 fc
= hdr
->frame_control
;
1062 u8 hdr_len
= ieee80211_hdrlen(fc
);
1065 * Send this frame after DTIM -- there's a special queue
1066 * reserved for this for contexts that support AP mode.
1068 if (info
->flags
& IEEE80211_TX_CTL_SEND_AFTER_DTIM
) {
1069 txq_id
= trans_pcie
->mcast_queue
[ctx
];
1072 * The microcode will clear the more data
1073 * bit in the last frame it transmits.
1075 hdr
->frame_control
|=
1076 cpu_to_le16(IEEE80211_FCTL_MOREDATA
);
1077 } else if (info
->flags
& IEEE80211_TX_CTL_TX_OFFCHAN
)
1078 txq_id
= IWL_AUX_QUEUE
;
1081 trans_pcie
->ac_to_queue
[ctx
][skb_get_queue_mapping(skb
)];
1083 if (ieee80211_is_data_qos(fc
)) {
1085 struct iwl_tid_data
*tid_data
;
1086 qc
= ieee80211_get_qos_ctl(hdr
);
1087 tid
= qc
[0] & IEEE80211_QOS_CTL_TID_MASK
;
1088 tid_data
= &trans
->shrd
->tid_data
[sta_id
][tid
];
1090 if (WARN_ON_ONCE(tid
>= IWL_MAX_TID_COUNT
))
1093 seq_number
= tid_data
->seq_number
;
1094 seq_number
&= IEEE80211_SCTL_SEQ
;
1095 hdr
->seq_ctrl
= hdr
->seq_ctrl
&
1096 cpu_to_le16(IEEE80211_SCTL_FRAG
);
1097 hdr
->seq_ctrl
|= cpu_to_le16(seq_number
);
1099 /* aggregation is on for this <sta,tid> */
1100 if (info
->flags
& IEEE80211_TX_CTL_AMPDU
&&
1101 tid_data
->agg
.state
== IWL_AGG_ON
) {
1102 txq_id
= tid_data
->agg
.txq_id
;
1107 txq
= &trans_pcie
->txq
[txq_id
];
1110 /* Set up driver data for this TFD */
1111 txq
->skbs
[q
->write_ptr
] = skb
;
1112 txq
->cmd
[q
->write_ptr
] = dev_cmd
;
1114 dev_cmd
->hdr
.cmd
= REPLY_TX
;
1115 dev_cmd
->hdr
.sequence
= cpu_to_le16((u16
)(QUEUE_TO_SEQ(txq_id
) |
1116 INDEX_TO_SEQ(q
->write_ptr
)));
1118 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1119 out_meta
= &txq
->meta
[q
->write_ptr
];
1122 * Use the first empty entry in this queue's command buffer array
1123 * to contain the Tx command and MAC header concatenated together
1124 * (payload data will be in another buffer).
1125 * Size of this varies, due to varying MAC header length.
1126 * If end is not dword aligned, we'll have 2 extra bytes at the end
1127 * of the MAC header (device reads on dword boundaries).
1128 * We'll tell device about this padding later.
1130 len
= sizeof(struct iwl_tx_cmd
) +
1131 sizeof(struct iwl_cmd_header
) + hdr_len
;
1132 firstlen
= (len
+ 3) & ~3;
1134 /* Tell NIC about any 2-byte padding after MAC header */
1135 if (firstlen
!= len
)
1136 tx_cmd
->tx_flags
|= TX_CMD_FLG_MH_PAD_MSK
;
1138 /* Physical address of this Tx command's header (not MAC header!),
1139 * within command buffer array. */
1140 txcmd_phys
= dma_map_single(bus(trans
)->dev
,
1141 &dev_cmd
->hdr
, firstlen
,
1143 if (unlikely(dma_mapping_error(bus(trans
)->dev
, txcmd_phys
)))
1145 dma_unmap_addr_set(out_meta
, mapping
, txcmd_phys
);
1146 dma_unmap_len_set(out_meta
, len
, firstlen
);
1148 if (!ieee80211_has_morefrags(fc
)) {
1149 txq
->need_update
= 1;
1152 txq
->need_update
= 0;
1155 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1156 * if any (802.11 null frames have no payload). */
1157 secondlen
= skb
->len
- hdr_len
;
1158 if (secondlen
> 0) {
1159 phys_addr
= dma_map_single(bus(trans
)->dev
, skb
->data
+ hdr_len
,
1160 secondlen
, DMA_TO_DEVICE
);
1161 if (unlikely(dma_mapping_error(bus(trans
)->dev
, phys_addr
))) {
1162 dma_unmap_single(bus(trans
)->dev
,
1163 dma_unmap_addr(out_meta
, mapping
),
1164 dma_unmap_len(out_meta
, len
),
1170 /* Attach buffers to TFD */
1171 iwlagn_txq_attach_buf_to_tfd(trans
, txq
, txcmd_phys
, firstlen
, 1);
1173 iwlagn_txq_attach_buf_to_tfd(trans
, txq
, phys_addr
,
1176 scratch_phys
= txcmd_phys
+ sizeof(struct iwl_cmd_header
) +
1177 offsetof(struct iwl_tx_cmd
, scratch
);
1179 /* take back ownership of DMA buffer to enable update */
1180 dma_sync_single_for_cpu(bus(trans
)->dev
, txcmd_phys
, firstlen
,
1182 tx_cmd
->dram_lsb_ptr
= cpu_to_le32(scratch_phys
);
1183 tx_cmd
->dram_msb_ptr
= iwl_get_dma_hi_addr(scratch_phys
);
1185 IWL_DEBUG_TX(trans
, "sequence nr = 0X%x\n",
1186 le16_to_cpu(dev_cmd
->hdr
.sequence
));
1187 IWL_DEBUG_TX(trans
, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd
->tx_flags
));
1188 iwl_print_hex_dump(trans
, IWL_DL_TX
, (u8
*)tx_cmd
, sizeof(*tx_cmd
));
1189 iwl_print_hex_dump(trans
, IWL_DL_TX
, (u8
*)tx_cmd
->hdr
, hdr_len
);
1191 /* Set up entry for this TFD in Tx byte-count array */
1193 iwl_trans_txq_update_byte_cnt_tbl(trans
, txq
,
1194 le16_to_cpu(tx_cmd
->len
));
1196 dma_sync_single_for_device(bus(trans
)->dev
, txcmd_phys
, firstlen
,
1199 trace_iwlwifi_dev_tx(priv(trans
),
1200 &((struct iwl_tfd
*)txq
->tfds
)[txq
->q
.write_ptr
],
1201 sizeof(struct iwl_tfd
),
1202 &dev_cmd
->hdr
, firstlen
,
1203 skb
->data
+ hdr_len
, secondlen
);
1205 /* Tell device the write index *just past* this latest filled TFD */
1206 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
1207 iwl_txq_update_write_ptr(trans
, txq
);
1209 if (ieee80211_is_data_qos(fc
)) {
1210 trans
->shrd
->tid_data
[sta_id
][tid
].tfds_in_queue
++;
1211 if (!ieee80211_has_morefrags(fc
))
1212 trans
->shrd
->tid_data
[sta_id
][tid
].seq_number
=
1217 * At this point the frame is "transmitted" successfully
1218 * and we will get a TX status notification eventually,
1219 * regardless of the value of ret. "ret" only indicates
1220 * whether or not we should update the write pointer.
1222 if (iwl_queue_space(q
) < q
->high_mark
) {
1223 if (wait_write_ptr
) {
1224 txq
->need_update
= 1;
1225 iwl_txq_update_write_ptr(trans
, txq
);
1227 iwl_stop_queue(trans
, txq
);
1233 static void iwl_trans_pcie_kick_nic(struct iwl_trans
*trans
)
1235 /* Remove all resets to allow NIC to operate */
1236 iwl_write32(bus(trans
), CSR_RESET
, 0);
1239 static int iwl_trans_pcie_request_irq(struct iwl_trans
*trans
)
1241 struct iwl_trans_pcie
*trans_pcie
=
1242 IWL_TRANS_GET_PCIE_TRANS(trans
);
1245 trans_pcie
->inta_mask
= CSR_INI_SET_MASK
;
1247 tasklet_init(&trans_pcie
->irq_tasklet
, (void (*)(unsigned long))
1248 iwl_irq_tasklet
, (unsigned long)trans
);
1250 iwl_alloc_isr_ict(trans
);
1252 err
= request_irq(bus(trans
)->irq
, iwl_isr_ict
, IRQF_SHARED
,
1255 IWL_ERR(trans
, "Error allocating IRQ %d\n", bus(trans
)->irq
);
1256 iwl_free_isr_ict(trans
);
1260 INIT_WORK(&trans_pcie
->rx_replenish
, iwl_bg_rx_replenish
);
1264 static int iwlagn_txq_check_empty(struct iwl_trans
*trans
,
1265 int sta_id
, u8 tid
, int txq_id
)
1267 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1268 struct iwl_queue
*q
= &trans_pcie
->txq
[txq_id
].q
;
1269 struct iwl_tid_data
*tid_data
= &trans
->shrd
->tid_data
[sta_id
][tid
];
1271 lockdep_assert_held(&trans
->shrd
->sta_lock
);
1273 switch (trans
->shrd
->tid_data
[sta_id
][tid
].agg
.state
) {
1274 case IWL_EMPTYING_HW_QUEUE_DELBA
:
1275 /* We are reclaiming the last packet of the */
1276 /* aggregated HW queue */
1277 if ((txq_id
== tid_data
->agg
.txq_id
) &&
1278 (q
->read_ptr
== q
->write_ptr
)) {
1280 "HW queue empty: continue DELBA flow\n");
1281 iwl_trans_pcie_txq_agg_disable(trans
, txq_id
);
1282 tid_data
->agg
.state
= IWL_AGG_OFF
;
1283 iwl_stop_tx_ba_trans_ready(priv(trans
),
1286 iwl_wake_queue(trans
, &trans_pcie
->txq
[txq_id
]);
1289 case IWL_EMPTYING_HW_QUEUE_ADDBA
:
1290 /* We are reclaiming the last packet of the queue */
1291 if (tid_data
->tfds_in_queue
== 0) {
1293 "HW queue empty: continue ADDBA flow\n");
1294 tid_data
->agg
.state
= IWL_AGG_ON
;
1295 iwl_start_tx_ba_trans_ready(priv(trans
),
1305 static void iwl_free_tfds_in_queue(struct iwl_trans
*trans
,
1306 int sta_id
, int tid
, int freed
)
1308 lockdep_assert_held(&trans
->shrd
->sta_lock
);
1310 if (trans
->shrd
->tid_data
[sta_id
][tid
].tfds_in_queue
>= freed
)
1311 trans
->shrd
->tid_data
[sta_id
][tid
].tfds_in_queue
-= freed
;
1313 IWL_DEBUG_TX(trans
, "free more than tfds_in_queue (%u:%d)\n",
1314 trans
->shrd
->tid_data
[sta_id
][tid
].tfds_in_queue
,
1316 trans
->shrd
->tid_data
[sta_id
][tid
].tfds_in_queue
= 0;
1320 static void iwl_trans_pcie_reclaim(struct iwl_trans
*trans
, int sta_id
, int tid
,
1321 int txq_id
, int ssn
, u32 status
,
1322 struct sk_buff_head
*skbs
)
1324 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1325 struct iwl_tx_queue
*txq
= &trans_pcie
->txq
[txq_id
];
1326 /* n_bd is usually 256 => n_bd - 1 = 0xff */
1327 int tfd_num
= ssn
& (txq
->q
.n_bd
- 1);
1332 txq
->time_stamp
= jiffies
;
1334 if (txq
->sched_retry
) {
1336 trans
->shrd
->tid_data
[txq
->sta_id
][txq
->tid
].agg
.state
;
1337 cond
= (agg_state
!= IWL_EMPTYING_HW_QUEUE_DELBA
);
1339 cond
= (status
!= TX_STATUS_FAIL_PASSIVE_NO_RX
);
1342 if (txq
->q
.read_ptr
!= tfd_num
) {
1343 IWL_DEBUG_TX_REPLY(trans
, "Retry scheduler reclaim "
1344 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1345 ssn
, tfd_num
, txq_id
, txq
->swq_id
);
1346 freed
= iwl_tx_queue_reclaim(trans
, txq_id
, tfd_num
, skbs
);
1347 if (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
&& cond
)
1348 iwl_wake_queue(trans
, txq
);
1351 iwl_free_tfds_in_queue(trans
, sta_id
, tid
, freed
);
1352 iwlagn_txq_check_empty(trans
, sta_id
, tid
, txq_id
);
1355 static void iwl_trans_pcie_free(struct iwl_trans
*trans
)
1357 iwl_trans_pcie_tx_free(trans
);
1358 iwl_trans_pcie_rx_free(trans
);
1359 free_irq(bus(trans
)->irq
, trans
);
1360 iwl_free_isr_ict(trans
);
1361 trans
->shrd
->trans
= NULL
;
1367 static int iwl_trans_pcie_suspend(struct iwl_trans
*trans
)
1370 * This function is called when system goes into suspend state
1371 * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
1372 * first but since iwl_mac_stop() has no knowledge of who the caller is,
1373 * it will not call apm_ops.stop() to stop the DMA operation.
1374 * Calling apm_ops.stop here to make sure we stop the DMA.
1376 * But of course ... if we have configured WoWLAN then we did other
1377 * things already :-)
1379 if (!trans
->shrd
->wowlan
)
1380 iwl_apm_stop(priv(trans
));
1385 static int iwl_trans_pcie_resume(struct iwl_trans
*trans
)
1387 bool hw_rfkill
= false;
1389 iwl_enable_interrupts(trans
);
1391 if (!(iwl_read32(bus(trans
), CSR_GP_CNTRL
) &
1392 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW
))
1396 set_bit(STATUS_RF_KILL_HW
, &trans
->shrd
->status
);
1398 clear_bit(STATUS_RF_KILL_HW
, &trans
->shrd
->status
);
1400 wiphy_rfkill_set_hw_state(priv(trans
)->hw
->wiphy
, hw_rfkill
);
1404 #else /* CONFIG_PM */
1405 static int iwl_trans_pcie_suspend(struct iwl_trans
*trans
)
1408 static int iwl_trans_pcie_resume(struct iwl_trans
*trans
)
1411 #endif /* CONFIG_PM */
1413 static void iwl_trans_pcie_wake_any_queue(struct iwl_trans
*trans
,
1417 struct iwl_trans_pcie
*trans_pcie
=
1418 IWL_TRANS_GET_PCIE_TRANS(trans
);
1420 for (ac
= 0; ac
< AC_NUM
; ac
++) {
1421 txq_id
= trans_pcie
->ac_to_queue
[ctx
][ac
];
1422 IWL_DEBUG_INFO(trans
, "Queue Status: Q[%d] %s\n",
1424 (atomic_read(&trans_pcie
->queue_stop_count
[ac
]) > 0)
1425 ? "stopped" : "awake");
1426 iwl_wake_queue(trans
, &trans_pcie
->txq
[txq_id
]);
1430 const struct iwl_trans_ops trans_ops_pcie
;
1432 static struct iwl_trans
*iwl_trans_pcie_alloc(struct iwl_shared
*shrd
)
1434 struct iwl_trans
*iwl_trans
= kzalloc(sizeof(struct iwl_trans
) +
1435 sizeof(struct iwl_trans_pcie
),
1438 struct iwl_trans_pcie
*trans_pcie
=
1439 IWL_TRANS_GET_PCIE_TRANS(iwl_trans
);
1440 iwl_trans
->ops
= &trans_ops_pcie
;
1441 iwl_trans
->shrd
= shrd
;
1442 trans_pcie
->trans
= iwl_trans
;
1443 spin_lock_init(&iwl_trans
->hcmd_lock
);
1449 static void iwl_trans_pcie_stop_queue(struct iwl_trans
*trans
, int txq_id
)
1451 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1453 iwl_stop_queue(trans
, &trans_pcie
->txq
[txq_id
]);
1456 #define IWL_FLUSH_WAIT_MS 2000
1458 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans
*trans
)
1460 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1461 struct iwl_tx_queue
*txq
;
1462 struct iwl_queue
*q
;
1464 unsigned long now
= jiffies
;
1467 /* waiting for all the tx frames complete might take a while */
1468 for (cnt
= 0; cnt
< hw_params(trans
).max_txq_num
; cnt
++) {
1469 if (cnt
== trans
->shrd
->cmd_queue
)
1471 txq
= &trans_pcie
->txq
[cnt
];
1473 while (q
->read_ptr
!= q
->write_ptr
&& !time_after(jiffies
,
1474 now
+ msecs_to_jiffies(IWL_FLUSH_WAIT_MS
)))
1477 if (q
->read_ptr
!= q
->write_ptr
) {
1478 IWL_ERR(trans
, "fail to flush all tx fifo queues\n");
1487 * On every watchdog tick we check (latest) time stamp. If it does not
1488 * change during timeout period and queue is not empty we reset firmware.
1490 static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans
*trans
, int cnt
)
1492 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1493 struct iwl_tx_queue
*txq
= &trans_pcie
->txq
[cnt
];
1494 struct iwl_queue
*q
= &txq
->q
;
1495 unsigned long timeout
;
1497 if (q
->read_ptr
== q
->write_ptr
) {
1498 txq
->time_stamp
= jiffies
;
1502 timeout
= txq
->time_stamp
+
1503 msecs_to_jiffies(hw_params(trans
).wd_timeout
);
1505 if (time_after(jiffies
, timeout
)) {
1506 IWL_ERR(trans
, "Queue %d stuck for %u ms.\n", q
->id
,
1507 hw_params(trans
).wd_timeout
);
1514 #ifdef CONFIG_IWLWIFI_DEBUGFS
1515 /* create and remove of files */
1516 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1517 if (!debugfs_create_file(#name, mode, parent, trans, \
1518 &iwl_dbgfs_##name##_ops)) \
1522 /* file operation */
1523 #define DEBUGFS_READ_FUNC(name) \
1524 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1525 char __user *user_buf, \
1526 size_t count, loff_t *ppos);
1528 #define DEBUGFS_WRITE_FUNC(name) \
1529 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1530 const char __user *user_buf, \
1531 size_t count, loff_t *ppos);
1534 static int iwl_dbgfs_open_file_generic(struct inode
*inode
, struct file
*file
)
1536 file
->private_data
= inode
->i_private
;
1540 #define DEBUGFS_READ_FILE_OPS(name) \
1541 DEBUGFS_READ_FUNC(name); \
1542 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1543 .read = iwl_dbgfs_##name##_read, \
1544 .open = iwl_dbgfs_open_file_generic, \
1545 .llseek = generic_file_llseek, \
1548 #define DEBUGFS_WRITE_FILE_OPS(name) \
1549 DEBUGFS_WRITE_FUNC(name); \
1550 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1551 .write = iwl_dbgfs_##name##_write, \
1552 .open = iwl_dbgfs_open_file_generic, \
1553 .llseek = generic_file_llseek, \
1556 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1557 DEBUGFS_READ_FUNC(name); \
1558 DEBUGFS_WRITE_FUNC(name); \
1559 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1560 .write = iwl_dbgfs_##name##_write, \
1561 .read = iwl_dbgfs_##name##_read, \
1562 .open = iwl_dbgfs_open_file_generic, \
1563 .llseek = generic_file_llseek, \
1566 static ssize_t
iwl_dbgfs_traffic_log_read(struct file
*file
,
1567 char __user
*user_buf
,
1568 size_t count
, loff_t
*ppos
)
1570 struct iwl_trans
*trans
= file
->private_data
;
1571 struct iwl_priv
*priv
= priv(trans
);
1572 int pos
= 0, ofs
= 0;
1574 struct iwl_trans_pcie
*trans_pcie
=
1575 IWL_TRANS_GET_PCIE_TRANS(trans
);
1576 struct iwl_tx_queue
*txq
;
1577 struct iwl_queue
*q
;
1578 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
1580 int bufsz
= ((IWL_TRAFFIC_ENTRIES
* IWL_TRAFFIC_ENTRY_SIZE
* 64) * 2) +
1581 (hw_params(trans
).max_txq_num
* 32 * 8) + 400;
1585 if (!trans_pcie
->txq
) {
1586 IWL_ERR(trans
, "txq not ready\n");
1589 buf
= kzalloc(bufsz
, GFP_KERNEL
);
1591 IWL_ERR(trans
, "Can not allocate buffer\n");
1594 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Tx Queue\n");
1595 for (cnt
= 0; cnt
< hw_params(trans
).max_txq_num
; cnt
++) {
1596 txq
= &trans_pcie
->txq
[cnt
];
1598 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1599 "q[%d]: read_ptr: %u, write_ptr: %u\n",
1600 cnt
, q
->read_ptr
, q
->write_ptr
);
1602 if (priv
->tx_traffic
&&
1603 (iwl_get_debug_level(trans
->shrd
) & IWL_DL_TX
)) {
1604 ptr
= priv
->tx_traffic
;
1605 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1606 "Tx Traffic idx: %u\n", priv
->tx_traffic_idx
);
1607 for (cnt
= 0, ofs
= 0; cnt
< IWL_TRAFFIC_ENTRIES
; cnt
++) {
1608 for (entry
= 0; entry
< IWL_TRAFFIC_ENTRY_SIZE
/ 16;
1609 entry
++, ofs
+= 16) {
1610 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1612 hex_dump_to_buffer(ptr
+ ofs
, 16, 16, 2,
1613 buf
+ pos
, bufsz
- pos
, 0);
1614 pos
+= strlen(buf
+ pos
);
1615 if (bufsz
- pos
> 0)
1621 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Rx Queue\n");
1622 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1623 "read: %u, write: %u\n",
1624 rxq
->read
, rxq
->write
);
1626 if (priv
->rx_traffic
&&
1627 (iwl_get_debug_level(trans
->shrd
) & IWL_DL_RX
)) {
1628 ptr
= priv
->rx_traffic
;
1629 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1630 "Rx Traffic idx: %u\n", priv
->rx_traffic_idx
);
1631 for (cnt
= 0, ofs
= 0; cnt
< IWL_TRAFFIC_ENTRIES
; cnt
++) {
1632 for (entry
= 0; entry
< IWL_TRAFFIC_ENTRY_SIZE
/ 16;
1633 entry
++, ofs
+= 16) {
1634 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1636 hex_dump_to_buffer(ptr
+ ofs
, 16, 16, 2,
1637 buf
+ pos
, bufsz
- pos
, 0);
1638 pos
+= strlen(buf
+ pos
);
1639 if (bufsz
- pos
> 0)
1645 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1650 static ssize_t
iwl_dbgfs_traffic_log_write(struct file
*file
,
1651 const char __user
*user_buf
,
1652 size_t count
, loff_t
*ppos
)
1654 struct iwl_trans
*trans
= file
->private_data
;
1659 memset(buf
, 0, sizeof(buf
));
1660 buf_size
= min(count
, sizeof(buf
) - 1);
1661 if (copy_from_user(buf
, user_buf
, buf_size
))
1663 if (sscanf(buf
, "%d", &traffic_log
) != 1)
1665 if (traffic_log
== 0)
1666 iwl_reset_traffic_log(priv(trans
));
1671 static ssize_t
iwl_dbgfs_tx_queue_read(struct file
*file
,
1672 char __user
*user_buf
,
1673 size_t count
, loff_t
*ppos
)
1675 struct iwl_trans
*trans
= file
->private_data
;
1676 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1677 struct iwl_priv
*priv
= priv(trans
);
1678 struct iwl_tx_queue
*txq
;
1679 struct iwl_queue
*q
;
1684 const size_t bufsz
= sizeof(char) * 64 * hw_params(trans
).max_txq_num
;
1686 if (!trans_pcie
->txq
) {
1687 IWL_ERR(priv
, "txq not ready\n");
1690 buf
= kzalloc(bufsz
, GFP_KERNEL
);
1694 for (cnt
= 0; cnt
< hw_params(trans
).max_txq_num
; cnt
++) {
1695 txq
= &trans_pcie
->txq
[cnt
];
1697 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1698 "hwq %.2d: read=%u write=%u stop=%d"
1699 " swq_id=%#.2x (ac %d/hwq %d)\n",
1700 cnt
, q
->read_ptr
, q
->write_ptr
,
1701 !!test_bit(cnt
, trans_pcie
->queue_stopped
),
1702 txq
->swq_id
, txq
->swq_id
& 3,
1703 (txq
->swq_id
>> 2) & 0x1f);
1706 /* for the ACs, display the stop count too */
1707 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1708 " stop-count: %d\n",
1709 atomic_read(&trans_pcie
->queue_stop_count
[cnt
]));
1711 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1716 static ssize_t
iwl_dbgfs_rx_queue_read(struct file
*file
,
1717 char __user
*user_buf
,
1718 size_t count
, loff_t
*ppos
) {
1719 struct iwl_trans
*trans
= file
->private_data
;
1720 struct iwl_trans_pcie
*trans_pcie
=
1721 IWL_TRANS_GET_PCIE_TRANS(trans
);
1722 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
1725 const size_t bufsz
= sizeof(buf
);
1727 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "read: %u\n",
1729 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "write: %u\n",
1731 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "free_count: %u\n",
1734 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "closed_rb_num: %u\n",
1735 le16_to_cpu(rxq
->rb_stts
->closed_rb_num
) & 0x0FFF);
1737 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1738 "closed_rb_num: Not Allocated\n");
1740 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1743 static ssize_t
iwl_dbgfs_log_event_read(struct file
*file
,
1744 char __user
*user_buf
,
1745 size_t count
, loff_t
*ppos
)
1747 struct iwl_trans
*trans
= file
->private_data
;
1750 ssize_t ret
= -ENOMEM
;
1752 ret
= pos
= iwl_dump_nic_event_log(trans
, true, &buf
, true);
1754 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1760 static ssize_t
iwl_dbgfs_log_event_write(struct file
*file
,
1761 const char __user
*user_buf
,
1762 size_t count
, loff_t
*ppos
)
1764 struct iwl_trans
*trans
= file
->private_data
;
1769 memset(buf
, 0, sizeof(buf
));
1770 buf_size
= min(count
, sizeof(buf
) - 1);
1771 if (copy_from_user(buf
, user_buf
, buf_size
))
1773 if (sscanf(buf
, "%d", &event_log_flag
) != 1)
1775 if (event_log_flag
== 1)
1776 iwl_dump_nic_event_log(trans
, true, NULL
, false);
1781 static ssize_t
iwl_dbgfs_interrupt_read(struct file
*file
,
1782 char __user
*user_buf
,
1783 size_t count
, loff_t
*ppos
) {
1785 struct iwl_trans
*trans
= file
->private_data
;
1786 struct iwl_trans_pcie
*trans_pcie
=
1787 IWL_TRANS_GET_PCIE_TRANS(trans
);
1788 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
1792 int bufsz
= 24 * 64; /* 24 items * 64 char per item */
1795 buf
= kzalloc(bufsz
, GFP_KERNEL
);
1797 IWL_ERR(trans
, "Can not allocate Buffer\n");
1801 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1802 "Interrupt Statistics Report:\n");
1804 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "HW Error:\t\t\t %u\n",
1806 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "SW Error:\t\t\t %u\n",
1808 if (isr_stats
->sw
|| isr_stats
->hw
) {
1809 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1810 "\tLast Restarting Code: 0x%X\n",
1811 isr_stats
->err_code
);
1813 #ifdef CONFIG_IWLWIFI_DEBUG
1814 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Frame transmitted:\t\t %u\n",
1816 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Alive interrupt:\t\t %u\n",
1819 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1820 "HW RF KILL switch toggled:\t %u\n", isr_stats
->rfkill
);
1822 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "CT KILL:\t\t\t %u\n",
1825 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Wakeup Interrupt:\t\t %u\n",
1828 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1829 "Rx command responses:\t\t %u\n", isr_stats
->rx
);
1831 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Tx/FH interrupt:\t\t %u\n",
1834 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Unexpected INTA:\t\t %u\n",
1835 isr_stats
->unhandled
);
1837 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1842 static ssize_t
iwl_dbgfs_interrupt_write(struct file
*file
,
1843 const char __user
*user_buf
,
1844 size_t count
, loff_t
*ppos
)
1846 struct iwl_trans
*trans
= file
->private_data
;
1847 struct iwl_trans_pcie
*trans_pcie
=
1848 IWL_TRANS_GET_PCIE_TRANS(trans
);
1849 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
1855 memset(buf
, 0, sizeof(buf
));
1856 buf_size
= min(count
, sizeof(buf
) - 1);
1857 if (copy_from_user(buf
, user_buf
, buf_size
))
1859 if (sscanf(buf
, "%x", &reset_flag
) != 1)
1861 if (reset_flag
== 0)
1862 memset(isr_stats
, 0, sizeof(*isr_stats
));
1867 static const char *get_csr_string(int cmd
)
1870 IWL_CMD(CSR_HW_IF_CONFIG_REG
);
1871 IWL_CMD(CSR_INT_COALESCING
);
1873 IWL_CMD(CSR_INT_MASK
);
1874 IWL_CMD(CSR_FH_INT_STATUS
);
1875 IWL_CMD(CSR_GPIO_IN
);
1877 IWL_CMD(CSR_GP_CNTRL
);
1878 IWL_CMD(CSR_HW_REV
);
1879 IWL_CMD(CSR_EEPROM_REG
);
1880 IWL_CMD(CSR_EEPROM_GP
);
1881 IWL_CMD(CSR_OTP_GP_REG
);
1882 IWL_CMD(CSR_GIO_REG
);
1883 IWL_CMD(CSR_GP_UCODE_REG
);
1884 IWL_CMD(CSR_GP_DRIVER_REG
);
1885 IWL_CMD(CSR_UCODE_DRV_GP1
);
1886 IWL_CMD(CSR_UCODE_DRV_GP2
);
1887 IWL_CMD(CSR_LED_REG
);
1888 IWL_CMD(CSR_DRAM_INT_TBL_REG
);
1889 IWL_CMD(CSR_GIO_CHICKEN_BITS
);
1890 IWL_CMD(CSR_ANA_PLL_CFG
);
1891 IWL_CMD(CSR_HW_REV_WA_REG
);
1892 IWL_CMD(CSR_DBG_HPET_MEM_REG
);
1898 void iwl_dump_csr(struct iwl_trans
*trans
)
1901 static const u32 csr_tbl
[] = {
1902 CSR_HW_IF_CONFIG_REG
,
1920 CSR_DRAM_INT_TBL_REG
,
1921 CSR_GIO_CHICKEN_BITS
,
1924 CSR_DBG_HPET_MEM_REG
1926 IWL_ERR(trans
, "CSR values:\n");
1927 IWL_ERR(trans
, "(2nd byte of CSR_INT_COALESCING is "
1928 "CSR_INT_PERIODIC_REG)\n");
1929 for (i
= 0; i
< ARRAY_SIZE(csr_tbl
); i
++) {
1930 IWL_ERR(trans
, " %25s: 0X%08x\n",
1931 get_csr_string(csr_tbl
[i
]),
1932 iwl_read32(bus(trans
), csr_tbl
[i
]));
1936 static ssize_t
iwl_dbgfs_csr_write(struct file
*file
,
1937 const char __user
*user_buf
,
1938 size_t count
, loff_t
*ppos
)
1940 struct iwl_trans
*trans
= file
->private_data
;
1945 memset(buf
, 0, sizeof(buf
));
1946 buf_size
= min(count
, sizeof(buf
) - 1);
1947 if (copy_from_user(buf
, user_buf
, buf_size
))
1949 if (sscanf(buf
, "%d", &csr
) != 1)
1952 iwl_dump_csr(trans
);
1957 static const char *get_fh_string(int cmd
)
1960 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG
);
1961 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG
);
1962 IWL_CMD(FH_RSCSR_CHNL0_WPTR
);
1963 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG
);
1964 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG
);
1965 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG
);
1966 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
);
1967 IWL_CMD(FH_TSSR_TX_STATUS_REG
);
1968 IWL_CMD(FH_TSSR_TX_ERROR_REG
);
1974 int iwl_dump_fh(struct iwl_trans
*trans
, char **buf
, bool display
)
1977 #ifdef CONFIG_IWLWIFI_DEBUG
1981 static const u32 fh_tbl
[] = {
1982 FH_RSCSR_CHNL0_STTS_WPTR_REG
,
1983 FH_RSCSR_CHNL0_RBDCB_BASE_REG
,
1984 FH_RSCSR_CHNL0_WPTR
,
1985 FH_MEM_RCSR_CHNL0_CONFIG_REG
,
1986 FH_MEM_RSSR_SHARED_CTRL_REG
,
1987 FH_MEM_RSSR_RX_STATUS_REG
,
1988 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
,
1989 FH_TSSR_TX_STATUS_REG
,
1990 FH_TSSR_TX_ERROR_REG
1992 #ifdef CONFIG_IWLWIFI_DEBUG
1994 bufsz
= ARRAY_SIZE(fh_tbl
) * 48 + 40;
1995 *buf
= kmalloc(bufsz
, GFP_KERNEL
);
1998 pos
+= scnprintf(*buf
+ pos
, bufsz
- pos
,
1999 "FH register values:\n");
2000 for (i
= 0; i
< ARRAY_SIZE(fh_tbl
); i
++) {
2001 pos
+= scnprintf(*buf
+ pos
, bufsz
- pos
,
2003 get_fh_string(fh_tbl
[i
]),
2004 iwl_read_direct32(bus(trans
), fh_tbl
[i
]));
2009 IWL_ERR(trans
, "FH register values:\n");
2010 for (i
= 0; i
< ARRAY_SIZE(fh_tbl
); i
++) {
2011 IWL_ERR(trans
, " %34s: 0X%08x\n",
2012 get_fh_string(fh_tbl
[i
]),
2013 iwl_read_direct32(bus(trans
), fh_tbl
[i
]));
2018 static ssize_t
iwl_dbgfs_fh_reg_read(struct file
*file
,
2019 char __user
*user_buf
,
2020 size_t count
, loff_t
*ppos
)
2022 struct iwl_trans
*trans
= file
->private_data
;
2025 ssize_t ret
= -EFAULT
;
2027 ret
= pos
= iwl_dump_fh(trans
, &buf
, true);
2029 ret
= simple_read_from_buffer(user_buf
,
2030 count
, ppos
, buf
, pos
);
2037 DEBUGFS_READ_WRITE_FILE_OPS(traffic_log
);
2038 DEBUGFS_READ_WRITE_FILE_OPS(log_event
);
2039 DEBUGFS_READ_WRITE_FILE_OPS(interrupt
);
2040 DEBUGFS_READ_FILE_OPS(fh_reg
);
2041 DEBUGFS_READ_FILE_OPS(rx_queue
);
2042 DEBUGFS_READ_FILE_OPS(tx_queue
);
2043 DEBUGFS_WRITE_FILE_OPS(csr
);
2046 * Create the debugfs files and directories
2049 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans
*trans
,
2052 DEBUGFS_ADD_FILE(traffic_log
, dir
, S_IWUSR
| S_IRUSR
);
2053 DEBUGFS_ADD_FILE(rx_queue
, dir
, S_IRUSR
);
2054 DEBUGFS_ADD_FILE(tx_queue
, dir
, S_IRUSR
);
2055 DEBUGFS_ADD_FILE(log_event
, dir
, S_IWUSR
| S_IRUSR
);
2056 DEBUGFS_ADD_FILE(interrupt
, dir
, S_IWUSR
| S_IRUSR
);
2057 DEBUGFS_ADD_FILE(csr
, dir
, S_IWUSR
);
2058 DEBUGFS_ADD_FILE(fh_reg
, dir
, S_IRUSR
);
2062 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans
*trans
,
2066 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2068 const struct iwl_trans_ops trans_ops_pcie
= {
2069 .alloc
= iwl_trans_pcie_alloc
,
2070 .request_irq
= iwl_trans_pcie_request_irq
,
2071 .start_device
= iwl_trans_pcie_start_device
,
2072 .prepare_card_hw
= iwl_trans_pcie_prepare_card_hw
,
2073 .stop_device
= iwl_trans_pcie_stop_device
,
2075 .tx_start
= iwl_trans_pcie_tx_start
,
2076 .wake_any_queue
= iwl_trans_pcie_wake_any_queue
,
2078 .send_cmd
= iwl_trans_pcie_send_cmd
,
2079 .send_cmd_pdu
= iwl_trans_pcie_send_cmd_pdu
,
2081 .tx
= iwl_trans_pcie_tx
,
2082 .reclaim
= iwl_trans_pcie_reclaim
,
2084 .tx_agg_disable
= iwl_trans_pcie_tx_agg_disable
,
2085 .tx_agg_alloc
= iwl_trans_pcie_tx_agg_alloc
,
2086 .tx_agg_setup
= iwl_trans_pcie_tx_agg_setup
,
2088 .kick_nic
= iwl_trans_pcie_kick_nic
,
2090 .free
= iwl_trans_pcie_free
,
2091 .stop_queue
= iwl_trans_pcie_stop_queue
,
2093 .dbgfs_register
= iwl_trans_pcie_dbgfs_register
,
2095 .wait_tx_queue_empty
= iwl_trans_pcie_wait_tx_queue_empty
,
2096 .check_stuck_queue
= iwl_trans_pcie_check_stuck_queue
,
2098 .suspend
= iwl_trans_pcie_suspend
,
2099 .resume
= iwl_trans_pcie_resume
,