1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *****************************************************************************/
64 #include "iwl-trans.h"
66 #include "iwl-helpers.h"
67 /*TODO remove uneeded includes when the transport layer tx_free will be here */
71 static int iwl_trans_rx_alloc(struct iwl_priv
*priv
)
73 struct iwl_rx_queue
*rxq
= &priv
->rxq
;
74 struct device
*dev
= priv
->bus
.dev
;
76 memset(&priv
->rxq
, 0, sizeof(priv
->rxq
));
78 spin_lock_init(&rxq
->lock
);
79 INIT_LIST_HEAD(&rxq
->rx_free
);
80 INIT_LIST_HEAD(&rxq
->rx_used
);
82 if (WARN_ON(rxq
->bd
|| rxq
->rb_stts
))
85 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
86 rxq
->bd
= dma_alloc_coherent(dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
87 &rxq
->bd_dma
, GFP_KERNEL
);
90 memset(rxq
->bd
, 0, sizeof(__le32
) * RX_QUEUE_SIZE
);
92 /*Allocate the driver's pointer to receive buffer status */
93 rxq
->rb_stts
= dma_alloc_coherent(dev
, sizeof(*rxq
->rb_stts
),
94 &rxq
->rb_stts_dma
, GFP_KERNEL
);
97 memset(rxq
->rb_stts
, 0, sizeof(*rxq
->rb_stts
));
102 dma_free_coherent(dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
103 rxq
->bd
, rxq
->bd_dma
);
104 memset(&rxq
->bd_dma
, 0, sizeof(rxq
->bd_dma
));
110 static void iwl_trans_rxq_free_rx_bufs(struct iwl_priv
*priv
)
112 struct iwl_rx_queue
*rxq
= &priv
->rxq
;
115 /* Fill the rx_used queue with _all_ of the Rx buffers */
116 for (i
= 0; i
< RX_FREE_BUFFERS
+ RX_QUEUE_SIZE
; i
++) {
117 /* In the reset function, these buffers may have been allocated
118 * to an SKB, so we need to unmap and free potential storage */
119 if (rxq
->pool
[i
].page
!= NULL
) {
120 dma_unmap_page(priv
->bus
.dev
, rxq
->pool
[i
].page_dma
,
121 PAGE_SIZE
<< priv
->hw_params
.rx_page_order
,
123 __iwl_free_pages(priv
, rxq
->pool
[i
].page
);
124 rxq
->pool
[i
].page
= NULL
;
126 list_add_tail(&rxq
->pool
[i
].list
, &rxq
->rx_used
);
130 static int iwl_trans_rx_init(struct iwl_priv
*priv
)
132 struct iwl_rx_queue
*rxq
= &priv
->rxq
;
137 err
= iwl_trans_rx_alloc(priv
);
142 spin_lock_irqsave(&rxq
->lock
, flags
);
143 INIT_LIST_HEAD(&rxq
->rx_free
);
144 INIT_LIST_HEAD(&rxq
->rx_used
);
146 iwl_trans_rxq_free_rx_bufs(priv
);
148 for (i
= 0; i
< RX_QUEUE_SIZE
; i
++)
149 rxq
->queue
[i
] = NULL
;
151 /* Set us so that we have processed and used all buffers, but have
152 * not restocked the Rx queue with fresh buffers */
153 rxq
->read
= rxq
->write
= 0;
154 rxq
->write_actual
= 0;
156 spin_unlock_irqrestore(&rxq
->lock
, flags
);
161 static void iwl_trans_rx_free(struct iwl_priv
*priv
)
163 struct iwl_rx_queue
*rxq
= &priv
->rxq
;
166 /*if rxq->bd is NULL, it means that nothing has been allocated,
169 IWL_DEBUG_INFO(priv
, "Free NULL rx context\n");
173 spin_lock_irqsave(&rxq
->lock
, flags
);
174 iwl_trans_rxq_free_rx_bufs(priv
);
175 spin_unlock_irqrestore(&rxq
->lock
, flags
);
177 dma_free_coherent(priv
->bus
.dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
178 rxq
->bd
, rxq
->bd_dma
);
179 memset(&rxq
->bd_dma
, 0, sizeof(rxq
->bd_dma
));
183 dma_free_coherent(priv
->bus
.dev
,
184 sizeof(struct iwl_rb_status
),
185 rxq
->rb_stts
, rxq
->rb_stts_dma
);
187 IWL_DEBUG_INFO(priv
, "Free rxq->rb_stts which is NULL\n");
188 memset(&rxq
->rb_stts_dma
, 0, sizeof(rxq
->rb_stts_dma
));
192 static int iwl_trans_rx_stop(struct iwl_priv
*priv
)
196 iwl_write_direct32(priv
, FH_MEM_RCSR_CHNL0_CONFIG_REG
, 0);
197 return iwl_poll_direct_bit(priv
, FH_MEM_RSSR_RX_STATUS_REG
,
198 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE
, 1000);
201 static inline int iwlagn_alloc_dma_ptr(struct iwl_priv
*priv
,
202 struct iwl_dma_ptr
*ptr
, size_t size
)
204 if (WARN_ON(ptr
->addr
))
207 ptr
->addr
= dma_alloc_coherent(priv
->bus
.dev
, size
,
208 &ptr
->dma
, GFP_KERNEL
);
215 static inline void iwlagn_free_dma_ptr(struct iwl_priv
*priv
,
216 struct iwl_dma_ptr
*ptr
)
218 if (unlikely(!ptr
->addr
))
221 dma_free_coherent(priv
->bus
.dev
, ptr
->size
, ptr
->addr
, ptr
->dma
);
222 memset(ptr
, 0, sizeof(*ptr
));
225 static int iwl_trans_txq_alloc(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
,
226 int slots_num
, u32 txq_id
)
228 size_t tfd_sz
= priv
->hw_params
.tfd_size
* TFD_QUEUE_SIZE_MAX
;
231 if (WARN_ON(txq
->meta
|| txq
->cmd
|| txq
->txb
|| txq
->tfds
))
234 txq
->q
.n_window
= slots_num
;
236 txq
->meta
= kzalloc(sizeof(txq
->meta
[0]) * slots_num
,
238 txq
->cmd
= kzalloc(sizeof(txq
->cmd
[0]) * slots_num
,
241 if (!txq
->meta
|| !txq
->cmd
)
244 for (i
= 0; i
< slots_num
; i
++) {
245 txq
->cmd
[i
] = kmalloc(sizeof(struct iwl_device_cmd
),
251 /* Alloc driver data array and TFD circular buffer */
252 /* Driver private data, only for Tx (not command) queues,
253 * not shared with device. */
254 if (txq_id
!= priv
->cmd_queue
) {
255 txq
->txb
= kzalloc(sizeof(txq
->txb
[0]) *
256 TFD_QUEUE_SIZE_MAX
, GFP_KERNEL
);
258 IWL_ERR(priv
, "kmalloc for auxiliary BD "
259 "structures failed\n");
266 /* Circular buffer of transmit frame descriptors (TFDs),
267 * shared with device */
268 txq
->tfds
= dma_alloc_coherent(priv
->bus
.dev
, tfd_sz
, &txq
->q
.dma_addr
,
271 IWL_ERR(priv
, "dma_alloc_coherent(%zd) failed\n", tfd_sz
);
280 /* since txq->cmd has been zeroed,
281 * all non allocated cmd[i] will be NULL */
283 for (i
= 0; i
< slots_num
; i
++)
294 static int iwl_trans_txq_init(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
,
295 int slots_num
, u32 txq_id
)
299 txq
->need_update
= 0;
300 memset(txq
->meta
, 0, sizeof(txq
->meta
[0]) * slots_num
);
303 * For the default queues 0-3, set up the swq_id
304 * already -- all others need to get one later
305 * (if they need one at all).
308 iwl_set_swq_id(txq
, txq_id
, txq_id
);
310 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
311 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
312 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX
& (TFD_QUEUE_SIZE_MAX
- 1));
314 /* Initialize queue's high/low-water marks, and head/tail indexes */
315 ret
= iwl_queue_init(priv
, &txq
->q
, TFD_QUEUE_SIZE_MAX
, slots_num
,
321 * Tell nic where to find circular buffer of Tx Frame Descriptors for
322 * given Tx queue, and enable the DMA channel used for that queue.
323 * Circular buffer (TFD queue in DRAM) physical base address */
324 iwl_write_direct32(priv
, FH_MEM_CBBC_QUEUE(txq_id
),
325 txq
->q
.dma_addr
>> 8);
331 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
333 static void iwl_tx_queue_unmap(struct iwl_priv
*priv
, int txq_id
)
335 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
336 struct iwl_queue
*q
= &txq
->q
;
341 while (q
->write_ptr
!= q
->read_ptr
) {
342 /* The read_ptr needs to bound by q->n_window */
343 iwlagn_txq_free_tfd(priv
, txq
, get_cmd_index(q
, q
->read_ptr
));
344 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
);
349 * iwl_tx_queue_free - Deallocate DMA queue.
350 * @txq: Transmit queue to deallocate.
352 * Empty queue by removing and destroying all BD's.
354 * 0-fill, but do not free "txq" descriptor structure.
356 static void iwl_tx_queue_free(struct iwl_priv
*priv
, int txq_id
)
358 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
359 struct device
*dev
= priv
->bus
.dev
;
364 iwl_tx_queue_unmap(priv
, txq_id
);
366 /* De-alloc array of command/tx buffers */
367 for (i
= 0; i
< txq
->q
.n_window
; i
++)
370 /* De-alloc circular buffer of TFDs */
372 dma_free_coherent(dev
, priv
->hw_params
.tfd_size
*
373 txq
->q
.n_bd
, txq
->tfds
, txq
->q
.dma_addr
);
374 memset(&txq
->q
.dma_addr
, 0, sizeof(txq
->q
.dma_addr
));
377 /* De-alloc array of per-TFD driver data */
381 /* deallocate arrays */
387 /* 0-fill queue descriptor structure */
388 memset(txq
, 0, sizeof(*txq
));
392 * iwl_trans_tx_free - Free TXQ Context
394 * Destroy all TX DMA queues and structures
396 static void iwl_trans_tx_free(struct iwl_priv
*priv
)
402 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++)
403 iwl_tx_queue_free(priv
, txq_id
);
409 iwlagn_free_dma_ptr(priv
, &priv
->kw
);
411 iwlagn_free_dma_ptr(priv
, &priv
->scd_bc_tbls
);
415 * iwl_trans_tx_alloc - allocate TX context
416 * Allocate all Tx DMA structures and initialize them
421 static int iwl_trans_tx_alloc(struct iwl_priv
*priv
)
424 int txq_id
, slots_num
;
426 /*It is not allowed to alloc twice, so warn when this happens.
427 * We cannot rely on the previous allocation, so free and fail */
428 if (WARN_ON(priv
->txq
)) {
433 ret
= iwlagn_alloc_dma_ptr(priv
, &priv
->scd_bc_tbls
,
434 priv
->hw_params
.scd_bc_tbls_size
);
436 IWL_ERR(priv
, "Scheduler BC Table allocation failed\n");
440 /* Alloc keep-warm buffer */
441 ret
= iwlagn_alloc_dma_ptr(priv
, &priv
->kw
, IWL_KW_SIZE
);
443 IWL_ERR(priv
, "Keep Warm allocation failed\n");
447 priv
->txq
= kzalloc(sizeof(struct iwl_tx_queue
) *
448 priv
->cfg
->base_params
->num_of_queues
, GFP_KERNEL
);
450 IWL_ERR(priv
, "Not enough memory for txq\n");
455 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
456 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++) {
457 slots_num
= (txq_id
== priv
->cmd_queue
) ?
458 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
459 ret
= iwl_trans_txq_alloc(priv
, &priv
->txq
[txq_id
], slots_num
,
462 IWL_ERR(priv
, "Tx %d queue alloc failed\n", txq_id
);
474 static int iwl_trans_tx_init(struct iwl_priv
*priv
)
477 int txq_id
, slots_num
;
482 ret
= iwl_trans_tx_alloc(priv
);
488 spin_lock_irqsave(&priv
->lock
, flags
);
490 /* Turn off all Tx DMA fifos */
491 iwl_write_prph(priv
, IWLAGN_SCD_TXFACT
, 0);
493 /* Tell NIC where to find the "keep warm" buffer */
494 iwl_write_direct32(priv
, FH_KW_MEM_ADDR_REG
, priv
->kw
.dma
>> 4);
496 spin_unlock_irqrestore(&priv
->lock
, flags
);
498 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
499 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++) {
500 slots_num
= (txq_id
== priv
->cmd_queue
) ?
501 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
502 ret
= iwl_trans_txq_init(priv
, &priv
->txq
[txq_id
], slots_num
,
505 IWL_ERR(priv
, "Tx %d queue init failed\n", txq_id
);
512 /*Upon error, free only if we allocated something */
519 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
521 static int iwl_trans_tx_stop(struct iwl_priv
*priv
)
526 /* Turn off all Tx DMA fifos */
527 spin_lock_irqsave(&priv
->lock
, flags
);
529 iwlagn_txq_set_sched(priv
, 0);
531 /* Stop each Tx DMA channel, and wait for it to be idle */
532 for (ch
= 0; ch
< FH_TCSR_CHNL_NUM
; ch
++) {
533 iwl_write_direct32(priv
, FH_TCSR_CHNL_TX_CONFIG_REG(ch
), 0x0);
534 if (iwl_poll_direct_bit(priv
, FH_TSSR_TX_STATUS_REG
,
535 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch
),
537 IWL_ERR(priv
, "Failing on timeout while stopping"
538 " DMA channel %d [0x%08x]", ch
,
539 iwl_read_direct32(priv
, FH_TSSR_TX_STATUS_REG
));
541 spin_unlock_irqrestore(&priv
->lock
, flags
);
544 IWL_WARN(priv
, "Stopping tx queues that aren't allocated...");
548 /* Unmap DMA from host system and free skb's */
549 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++)
550 iwl_tx_queue_unmap(priv
, txq_id
);
555 static const struct iwl_trans_ops trans_ops
= {
556 .rx_init
= iwl_trans_rx_init
,
557 .rx_stop
= iwl_trans_rx_stop
,
558 .rx_free
= iwl_trans_rx_free
,
560 .tx_init
= iwl_trans_tx_init
,
561 .tx_stop
= iwl_trans_tx_stop
,
562 .tx_free
= iwl_trans_tx_free
,
564 .send_cmd
= iwl_send_cmd
,
565 .send_cmd_pdu
= iwl_send_cmd_pdu
,
568 void iwl_trans_register(struct iwl_trans
*trans
)
570 trans
->ops
= &trans_ops
;