1 /******************************************************************************
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/etherdevice.h>
31 #include <linux/sched.h>
32 #include <linux/slab.h>
33 #include <net/mac80211.h>
34 #include "iwl-eeprom.h"
40 #include "iwl-helpers.h"
43 * iwl_txq_update_write_ptr - Send new write index to hardware
45 void iwl_txq_update_write_ptr(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
)
48 int txq_id
= txq
->q
.id
;
50 if (txq
->need_update
== 0)
53 if (priv
->cfg
->base_params
->shadow_reg_enable
) {
54 /* shadow register enabled */
55 iwl_write32(priv
, HBUS_TARG_WRPTR
,
56 txq
->q
.write_ptr
| (txq_id
<< 8));
58 /* if we're trying to save power */
59 if (test_bit(STATUS_POWER_PMI
, &priv
->status
)) {
60 /* wake up nic if it's powered down ...
61 * uCode will wake up, and interrupt us again, so next
62 * time we'll skip this part. */
63 reg
= iwl_read32(priv
, CSR_UCODE_DRV_GP1
);
65 if (reg
& CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP
) {
67 "Tx queue %d requesting wakeup,"
68 " GP1 = 0x%x\n", txq_id
, reg
);
69 iwl_set_bit(priv
, CSR_GP_CNTRL
,
70 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
74 iwl_write_direct32(priv
, HBUS_TARG_WRPTR
,
75 txq
->q
.write_ptr
| (txq_id
<< 8));
78 * else not in power-save mode,
79 * uCode will never sleep when we're
80 * trying to tx (during RFKILL, we're not trying to tx).
83 iwl_write32(priv
, HBUS_TARG_WRPTR
,
84 txq
->q
.write_ptr
| (txq_id
<< 8));
89 static inline dma_addr_t
iwl_tfd_tb_get_addr(struct iwl_tfd
*tfd
, u8 idx
)
91 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
93 dma_addr_t addr
= get_unaligned_le32(&tb
->lo
);
94 if (sizeof(dma_addr_t
) > sizeof(u32
))
96 ((dma_addr_t
)(le16_to_cpu(tb
->hi_n_len
) & 0xF) << 16) << 16;
101 static inline u16
iwl_tfd_tb_get_len(struct iwl_tfd
*tfd
, u8 idx
)
103 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
105 return le16_to_cpu(tb
->hi_n_len
) >> 4;
108 static inline void iwl_tfd_set_tb(struct iwl_tfd
*tfd
, u8 idx
,
109 dma_addr_t addr
, u16 len
)
111 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
112 u16 hi_n_len
= len
<< 4;
114 put_unaligned_le32(addr
, &tb
->lo
);
115 if (sizeof(dma_addr_t
) > sizeof(u32
))
116 hi_n_len
|= ((addr
>> 16) >> 16) & 0xF;
118 tb
->hi_n_len
= cpu_to_le16(hi_n_len
);
120 tfd
->num_tbs
= idx
+ 1;
123 static inline u8
iwl_tfd_get_num_tbs(struct iwl_tfd
*tfd
)
125 return tfd
->num_tbs
& 0x1f;
128 static void iwlagn_unmap_tfd(struct iwl_priv
*priv
, struct iwl_cmd_meta
*meta
,
129 struct iwl_tfd
*tfd
, enum dma_data_direction dma_dir
)
134 /* Sanity check on number of chunks */
135 num_tbs
= iwl_tfd_get_num_tbs(tfd
);
137 if (num_tbs
>= IWL_NUM_OF_TBS
) {
138 IWL_ERR(priv
, "Too many chunks: %i\n", num_tbs
);
139 /* @todo issue fatal error, it is quite serious situation */
145 dma_unmap_single(priv
->bus
.dev
,
146 dma_unmap_addr(meta
, mapping
),
147 dma_unmap_len(meta
, len
),
150 /* Unmap chunks, if any. */
151 for (i
= 1; i
< num_tbs
; i
++)
152 dma_unmap_single(priv
->bus
.dev
, iwl_tfd_tb_get_addr(tfd
, i
),
153 iwl_tfd_tb_get_len(tfd
, i
), dma_dir
);
157 * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
158 * @priv - driver private data
161 * Does NOT advance any TFD circular buffer read/write indexes
162 * Does NOT free the TFD itself (which is within circular buffer)
164 void iwlagn_txq_free_tfd(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
)
166 struct iwl_tfd
*tfd_tmp
= txq
->tfds
;
167 int index
= txq
->q
.read_ptr
;
169 iwlagn_unmap_tfd(priv
, &txq
->meta
[index
], &tfd_tmp
[index
],
176 skb
= txq
->txb
[txq
->q
.read_ptr
].skb
;
178 /* can be called from irqs-disabled context */
180 dev_kfree_skb_any(skb
);
181 txq
->txb
[txq
->q
.read_ptr
].skb
= NULL
;
186 int iwlagn_txq_attach_buf_to_tfd(struct iwl_priv
*priv
,
187 struct iwl_tx_queue
*txq
,
188 dma_addr_t addr
, u16 len
,
192 struct iwl_tfd
*tfd
, *tfd_tmp
;
197 tfd
= &tfd_tmp
[q
->write_ptr
];
200 memset(tfd
, 0, sizeof(*tfd
));
202 num_tbs
= iwl_tfd_get_num_tbs(tfd
);
204 /* Each TFD can point to a maximum 20 Tx buffers */
205 if (num_tbs
>= IWL_NUM_OF_TBS
) {
206 IWL_ERR(priv
, "Error can not send more than %d chunks\n",
211 if (WARN_ON(addr
& ~DMA_BIT_MASK(36)))
214 if (unlikely(addr
& ~IWL_TX_DMA_MASK
))
215 IWL_ERR(priv
, "Unaligned address = %llx\n",
216 (unsigned long long)addr
);
218 iwl_tfd_set_tb(tfd
, num_tbs
, addr
, len
);
224 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
226 void iwl_tx_queue_unmap(struct iwl_priv
*priv
, int txq_id
)
228 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
229 struct iwl_queue
*q
= &txq
->q
;
234 while (q
->write_ptr
!= q
->read_ptr
) {
235 iwlagn_txq_free_tfd(priv
, txq
);
236 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
);
241 * iwl_tx_queue_free - Deallocate DMA queue.
242 * @txq: Transmit queue to deallocate.
244 * Empty queue by removing and destroying all BD's.
246 * 0-fill, but do not free "txq" descriptor structure.
248 void iwl_tx_queue_free(struct iwl_priv
*priv
, int txq_id
)
250 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
251 struct device
*dev
= priv
->bus
.dev
;
254 iwl_tx_queue_unmap(priv
, txq_id
);
256 /* De-alloc array of command/tx buffers */
257 for (i
= 0; i
< TFD_TX_CMD_SLOTS
; i
++)
260 /* De-alloc circular buffer of TFDs */
262 dma_free_coherent(dev
, priv
->hw_params
.tfd_size
*
263 txq
->q
.n_bd
, txq
->tfds
, txq
->q
.dma_addr
);
265 /* De-alloc array of per-TFD driver data */
269 /* deallocate arrays */
275 /* 0-fill queue descriptor structure */
276 memset(txq
, 0, sizeof(*txq
));
280 * iwl_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue
282 void iwl_cmd_queue_unmap(struct iwl_priv
*priv
)
284 struct iwl_tx_queue
*txq
= &priv
->txq
[priv
->cmd_queue
];
285 struct iwl_queue
*q
= &txq
->q
;
291 while (q
->read_ptr
!= q
->write_ptr
) {
292 i
= get_cmd_index(q
, q
->read_ptr
);
294 if (txq
->meta
[i
].flags
& CMD_MAPPED
) {
295 iwlagn_unmap_tfd(priv
, &txq
->meta
[i
], &txq
->tfds
[i
],
297 txq
->meta
[i
].flags
= 0;
300 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
);
305 * iwl_cmd_queue_free - Deallocate DMA queue.
306 * @txq: Transmit queue to deallocate.
308 * Empty queue by removing and destroying all BD's.
310 * 0-fill, but do not free "txq" descriptor structure.
312 void iwl_cmd_queue_free(struct iwl_priv
*priv
)
314 struct iwl_tx_queue
*txq
= &priv
->txq
[priv
->cmd_queue
];
315 struct device
*dev
= priv
->bus
.dev
;
318 iwl_cmd_queue_unmap(priv
);
320 /* De-alloc array of command/tx buffers */
321 for (i
= 0; i
< TFD_CMD_SLOTS
; i
++)
324 /* De-alloc circular buffer of TFDs */
326 dma_free_coherent(dev
, priv
->hw_params
.tfd_size
* txq
->q
.n_bd
,
327 txq
->tfds
, txq
->q
.dma_addr
);
329 /* deallocate arrays */
335 /* 0-fill queue descriptor structure */
336 memset(txq
, 0, sizeof(*txq
));
339 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
342 * Theory of operation
344 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
345 * of buffer descriptors, each of which points to one or more data buffers for
346 * the device to read from or fill. Driver and device exchange status of each
347 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
348 * entries in each circular buffer, to protect against confusing empty and full
351 * The device reads or writes the data in the queues via the device's several
352 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
354 * For Tx queue, there are low mark and high mark limits. If, after queuing
355 * the packet for Tx, free space become < low mark, Tx queue stopped. When
356 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
359 ***************************************************/
361 int iwl_queue_space(const struct iwl_queue
*q
)
363 int s
= q
->read_ptr
- q
->write_ptr
;
365 if (q
->read_ptr
> q
->write_ptr
)
370 /* keep some reserve to not confuse empty and full situations */
378 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
380 int iwl_queue_init(struct iwl_priv
*priv
, struct iwl_queue
*q
,
381 int count
, int slots_num
, u32 id
)
384 q
->n_window
= slots_num
;
387 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
388 * and iwl_queue_dec_wrap are broken. */
389 if (WARN_ON(!is_power_of_2(count
)))
392 /* slots_num must be power-of-two size, otherwise
393 * get_cmd_index is broken. */
394 if (WARN_ON(!is_power_of_2(slots_num
)))
397 q
->low_mark
= q
->n_window
/ 4;
401 q
->high_mark
= q
->n_window
/ 8;
402 if (q
->high_mark
< 2)
405 q
->write_ptr
= q
->read_ptr
= 0;
410 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
413 * iwl_enqueue_hcmd - enqueue a uCode command
414 * @priv: device private data point
415 * @cmd: a point to the ucode command structure
417 * The function returns < 0 values to indicate the operation is
418 * failed. On success, it turns the index (> 0) of command in the
421 int iwl_enqueue_hcmd(struct iwl_priv
*priv
, struct iwl_host_cmd
*cmd
)
423 struct iwl_tx_queue
*txq
= &priv
->txq
[priv
->cmd_queue
];
424 struct iwl_queue
*q
= &txq
->q
;
425 struct iwl_device_cmd
*out_cmd
;
426 struct iwl_cmd_meta
*out_meta
;
427 dma_addr_t phys_addr
;
430 u16 copy_size
, cmd_size
;
431 bool is_ct_kill
= false;
432 bool had_nocopy
= false;
435 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
436 const void *trace_bufs
[IWL_MAX_CMD_TFDS
+ 1] = {};
437 int trace_lens
[IWL_MAX_CMD_TFDS
+ 1] = {};
441 if (test_bit(STATUS_FW_ERROR
, &priv
->status
)) {
442 IWL_WARN(priv
, "fw recovery, no hcmd send\n");
446 copy_size
= sizeof(out_cmd
->hdr
);
447 cmd_size
= sizeof(out_cmd
->hdr
);
449 /* need one for the header if the first is NOCOPY */
450 BUILD_BUG_ON(IWL_MAX_CMD_TFDS
> IWL_NUM_OF_TBS
- 1);
452 for (i
= 0; i
< IWL_MAX_CMD_TFDS
; i
++) {
455 if (cmd
->dataflags
[i
] & IWL_HCMD_DFL_NOCOPY
) {
458 /* NOCOPY must not be followed by normal! */
459 if (WARN_ON(had_nocopy
))
461 copy_size
+= cmd
->len
[i
];
463 cmd_size
+= cmd
->len
[i
];
467 * If any of the command structures end up being larger than
468 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
469 * allocated into separate TFDs, then we will need to
470 * increase the size of the buffers.
472 if (WARN_ON(copy_size
> TFD_MAX_PAYLOAD_SIZE
))
475 if (iwl_is_rfkill(priv
) || iwl_is_ctkill(priv
)) {
476 IWL_WARN(priv
, "Not sending command - %s KILL\n",
477 iwl_is_rfkill(priv
) ? "RF" : "CT");
481 spin_lock_irqsave(&priv
->hcmd_lock
, flags
);
483 if (iwl_queue_space(q
) < ((cmd
->flags
& CMD_ASYNC
) ? 2 : 1)) {
484 spin_unlock_irqrestore(&priv
->hcmd_lock
, flags
);
486 IWL_ERR(priv
, "No space in command queue\n");
487 is_ct_kill
= iwl_check_for_ct_kill(priv
);
489 IWL_ERR(priv
, "Restarting adapter due to queue full\n");
490 iwlagn_fw_error(priv
, false);
495 idx
= get_cmd_index(q
, q
->write_ptr
);
496 out_cmd
= txq
->cmd
[idx
];
497 out_meta
= &txq
->meta
[idx
];
499 if (WARN_ON(out_meta
->flags
& CMD_MAPPED
)) {
500 spin_unlock_irqrestore(&priv
->hcmd_lock
, flags
);
504 memset(out_meta
, 0, sizeof(*out_meta
)); /* re-initialize to NULL */
505 if (cmd
->flags
& CMD_WANT_SKB
)
506 out_meta
->source
= cmd
;
507 if (cmd
->flags
& CMD_ASYNC
)
508 out_meta
->callback
= cmd
->callback
;
510 /* set up the header */
512 out_cmd
->hdr
.cmd
= cmd
->id
;
513 out_cmd
->hdr
.flags
= 0;
514 out_cmd
->hdr
.sequence
= cpu_to_le16(QUEUE_TO_SEQ(priv
->cmd_queue
) |
515 INDEX_TO_SEQ(q
->write_ptr
));
517 /* and copy the data that needs to be copied */
519 cmd_dest
= &out_cmd
->cmd
.payload
[0];
520 for (i
= 0; i
< IWL_MAX_CMD_TFDS
; i
++) {
523 if (cmd
->dataflags
[i
] & IWL_HCMD_DFL_NOCOPY
)
525 memcpy(cmd_dest
, cmd
->data
[i
], cmd
->len
[i
]);
526 cmd_dest
+= cmd
->len
[i
];
529 IWL_DEBUG_HC(priv
, "Sending command %s (#%x), seq: 0x%04X, "
530 "%d bytes at %d[%d]:%d\n",
531 get_cmd_string(out_cmd
->hdr
.cmd
),
533 le16_to_cpu(out_cmd
->hdr
.sequence
), cmd_size
,
534 q
->write_ptr
, idx
, priv
->cmd_queue
);
536 phys_addr
= dma_map_single(priv
->bus
.dev
, &out_cmd
->hdr
, copy_size
,
538 if (unlikely(dma_mapping_error(priv
->bus
.dev
, phys_addr
))) {
543 dma_unmap_addr_set(out_meta
, mapping
, phys_addr
);
544 dma_unmap_len_set(out_meta
, len
, copy_size
);
546 iwlagn_txq_attach_buf_to_tfd(priv
, txq
, phys_addr
, copy_size
, 1);
547 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
548 trace_bufs
[0] = &out_cmd
->hdr
;
549 trace_lens
[0] = copy_size
;
553 for (i
= 0; i
< IWL_MAX_CMD_TFDS
; i
++) {
556 if (!(cmd
->dataflags
[i
] & IWL_HCMD_DFL_NOCOPY
))
558 phys_addr
= dma_map_single(priv
->bus
.dev
, (void *)cmd
->data
[i
],
559 cmd
->len
[i
], DMA_BIDIRECTIONAL
);
560 if (dma_mapping_error(priv
->bus
.dev
, phys_addr
)) {
561 iwlagn_unmap_tfd(priv
, out_meta
,
562 &txq
->tfds
[q
->write_ptr
],
568 iwlagn_txq_attach_buf_to_tfd(priv
, txq
, phys_addr
,
570 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
571 trace_bufs
[trace_idx
] = cmd
->data
[i
];
572 trace_lens
[trace_idx
] = cmd
->len
[i
];
577 out_meta
->flags
= cmd
->flags
| CMD_MAPPED
;
579 txq
->need_update
= 1;
581 /* check that tracing gets all possible blocks */
582 BUILD_BUG_ON(IWL_MAX_CMD_TFDS
+ 1 != 3);
583 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
584 trace_iwlwifi_dev_hcmd(priv
, cmd
->flags
,
585 trace_bufs
[0], trace_lens
[0],
586 trace_bufs
[1], trace_lens
[1],
587 trace_bufs
[2], trace_lens
[2]);
590 /* Increment and update queue's write index */
591 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
592 iwl_txq_update_write_ptr(priv
, txq
);
595 spin_unlock_irqrestore(&priv
->hcmd_lock
, flags
);
600 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
602 * When FW advances 'R' index, all entries between old and new 'R' index
603 * need to be reclaimed. As result, some free space forms. If there is
604 * enough free space (> low mark), wake the stack that feeds us.
606 static void iwl_hcmd_queue_reclaim(struct iwl_priv
*priv
, int txq_id
, int idx
)
608 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
609 struct iwl_queue
*q
= &txq
->q
;
612 if ((idx
>= q
->n_bd
) || (iwl_queue_used(q
, idx
) == 0)) {
613 IWL_ERR(priv
, "%s: Read index for DMA queue txq id (%d), "
614 "index %d is out of range [0-%d] %d %d.\n", __func__
,
615 txq_id
, idx
, q
->n_bd
, q
->write_ptr
, q
->read_ptr
);
619 for (idx
= iwl_queue_inc_wrap(idx
, q
->n_bd
); q
->read_ptr
!= idx
;
620 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
623 IWL_ERR(priv
, "HCMD skipped: index (%d) %d %d\n", idx
,
624 q
->write_ptr
, q
->read_ptr
);
625 iwlagn_fw_error(priv
, false);
632 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
633 * @rxb: Rx buffer to reclaim
635 * If an Rx buffer has an async callback associated with it the callback
636 * will be executed. The attached skb (if present) will only be freed
637 * if the callback returns 1
639 void iwl_tx_cmd_complete(struct iwl_priv
*priv
, struct iwl_rx_mem_buffer
*rxb
)
641 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
642 u16 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
643 int txq_id
= SEQ_TO_QUEUE(sequence
);
644 int index
= SEQ_TO_INDEX(sequence
);
646 struct iwl_device_cmd
*cmd
;
647 struct iwl_cmd_meta
*meta
;
648 struct iwl_tx_queue
*txq
= &priv
->txq
[priv
->cmd_queue
];
651 /* If a Tx command is being handled and it isn't in the actual
652 * command queue then there a command routing bug has been introduced
653 * in the queue management code. */
654 if (WARN(txq_id
!= priv
->cmd_queue
,
655 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
656 txq_id
, priv
->cmd_queue
, sequence
,
657 priv
->txq
[priv
->cmd_queue
].q
.read_ptr
,
658 priv
->txq
[priv
->cmd_queue
].q
.write_ptr
)) {
659 iwl_print_hex_error(priv
, pkt
, 32);
663 cmd_index
= get_cmd_index(&txq
->q
, index
);
664 cmd
= txq
->cmd
[cmd_index
];
665 meta
= &txq
->meta
[cmd_index
];
667 iwlagn_unmap_tfd(priv
, meta
, &txq
->tfds
[index
], DMA_BIDIRECTIONAL
);
669 /* Input error checking is done when commands are added to queue. */
670 if (meta
->flags
& CMD_WANT_SKB
) {
671 meta
->source
->reply_page
= (unsigned long)rxb_addr(rxb
);
673 } else if (meta
->callback
)
674 meta
->callback(priv
, cmd
, pkt
);
676 spin_lock_irqsave(&priv
->hcmd_lock
, flags
);
678 iwl_hcmd_queue_reclaim(priv
, txq_id
, index
);
680 if (!(meta
->flags
& CMD_ASYNC
)) {
681 clear_bit(STATUS_HCMD_ACTIVE
, &priv
->status
);
682 IWL_DEBUG_INFO(priv
, "Clearing HCMD_ACTIVE for command %s\n",
683 get_cmd_string(cmd
->hdr
.cmd
));
684 wake_up_interruptible(&priv
->wait_command_queue
);
687 /* Mark as unmapped */
690 spin_unlock_irqrestore(&priv
->hcmd_lock
, flags
);