1 /******************************************************************************
3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/etherdevice.h>
31 #include <net/mac80211.h>
32 #include "iwl-eeprom.h"
37 #include "iwl-helpers.h"
39 static const u16 default_tid_to_tx_fifo
[] = {
61 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
63 * Does NOT advance any TFD circular buffer read/write indexes
64 * Does NOT free the TFD itself (which is within circular buffer)
66 int iwl_hw_txq_free_tfd(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
)
68 struct iwl_tfd_frame
*bd_tmp
= (struct iwl_tfd_frame
*)&txq
->bd
[0];
69 struct iwl_tfd_frame
*bd
= &bd_tmp
[txq
->q
.read_ptr
];
70 struct pci_dev
*dev
= priv
->pci_dev
;
75 /* Host command buffers stay mapped in memory, nothing to clean */
76 if (txq
->q
.id
== IWL_CMD_QUEUE_NUM
)
79 /* Sanity check on number of chunks */
80 counter
= IWL_GET_BITS(*bd
, num_tbs
);
81 if (counter
> MAX_NUM_OF_TBS
) {
82 IWL_ERROR("Too many chunks: %i\n", counter
);
83 /* @todo issue fatal error, it is quite serious situation */
87 /* Unmap chunks, if any.
88 * TFD info for odd chunks is different format than for even chunks. */
89 for (i
= 0; i
< counter
; i
++) {
96 IWL_GET_BITS(bd
->pa
[index
], tb2_addr_lo16
) |
97 (IWL_GET_BITS(bd
->pa
[index
],
98 tb2_addr_hi20
) << 16),
99 IWL_GET_BITS(bd
->pa
[index
], tb2_len
),
103 pci_unmap_single(dev
,
104 le32_to_cpu(bd
->pa
[index
].tb1_addr
),
105 IWL_GET_BITS(bd
->pa
[index
], tb1_len
),
108 /* Free SKB, if any, for this chunk */
109 if (txq
->txb
[txq
->q
.read_ptr
].skb
[i
]) {
110 struct sk_buff
*skb
= txq
->txb
[txq
->q
.read_ptr
].skb
[i
];
113 txq
->txb
[txq
->q
.read_ptr
].skb
[i
] = NULL
;
118 EXPORT_SYMBOL(iwl_hw_txq_free_tfd
);
121 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv
*priv
, void *ptr
,
122 dma_addr_t addr
, u16 len
)
125 struct iwl_tfd_frame
*tfd
= ptr
;
126 u32 num_tbs
= IWL_GET_BITS(*tfd
, num_tbs
);
128 /* Each TFD can point to a maximum 20 Tx buffers */
129 if ((num_tbs
>= MAX_NUM_OF_TBS
) || (num_tbs
< 0)) {
130 IWL_ERROR("Error can not send more than %d chunks\n",
136 is_odd
= num_tbs
& 0x1;
139 tfd
->pa
[index
].tb1_addr
= cpu_to_le32(addr
);
140 IWL_SET_BITS(tfd
->pa
[index
], tb1_addr_hi
,
141 iwl_get_dma_hi_address(addr
));
142 IWL_SET_BITS(tfd
->pa
[index
], tb1_len
, len
);
144 IWL_SET_BITS(tfd
->pa
[index
], tb2_addr_lo16
,
145 (u32
) (addr
& 0xffff));
146 IWL_SET_BITS(tfd
->pa
[index
], tb2_addr_hi20
, addr
>> 16);
147 IWL_SET_BITS(tfd
->pa
[index
], tb2_len
, len
);
150 IWL_SET_BITS(*tfd
, num_tbs
, num_tbs
+ 1);
154 EXPORT_SYMBOL(iwl_hw_txq_attach_buf_to_tfd
);
157 * iwl_txq_update_write_ptr - Send new write index to hardware
159 int iwl_txq_update_write_ptr(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
)
163 int txq_id
= txq
->q
.id
;
165 if (txq
->need_update
== 0)
168 /* if we're trying to save power */
169 if (test_bit(STATUS_POWER_PMI
, &priv
->status
)) {
170 /* wake up nic if it's powered down ...
171 * uCode will wake up, and interrupt us again, so next
172 * time we'll skip this part. */
173 reg
= iwl_read32(priv
, CSR_UCODE_DRV_GP1
);
175 if (reg
& CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP
) {
176 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg
);
177 iwl_set_bit(priv
, CSR_GP_CNTRL
,
178 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
182 /* restore this queue's parameters in nic hardware. */
183 ret
= iwl_grab_nic_access(priv
);
186 iwl_write_direct32(priv
, HBUS_TARG_WRPTR
,
187 txq
->q
.write_ptr
| (txq_id
<< 8));
188 iwl_release_nic_access(priv
);
190 /* else not in power-save mode, uCode will never sleep when we're
191 * trying to tx (during RFKILL, we're not trying to tx). */
193 iwl_write32(priv
, HBUS_TARG_WRPTR
,
194 txq
->q
.write_ptr
| (txq_id
<< 8));
196 txq
->need_update
= 0;
200 EXPORT_SYMBOL(iwl_txq_update_write_ptr
);
204 * iwl_tx_queue_free - Deallocate DMA queue.
205 * @txq: Transmit queue to deallocate.
207 * Empty queue by removing and destroying all BD's.
209 * 0-fill, but do not free "txq" descriptor structure.
211 static void iwl_tx_queue_free(struct iwl_priv
*priv
, int txq_id
)
213 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
214 struct iwl_queue
*q
= &txq
->q
;
215 struct pci_dev
*dev
= priv
->pci_dev
;
216 int i
, slots_num
, len
;
221 /* first, empty all BD's */
222 for (; q
->write_ptr
!= q
->read_ptr
;
223 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
))
224 iwl_hw_txq_free_tfd(priv
, txq
);
226 len
= sizeof(struct iwl_cmd
) * q
->n_window
;
227 if (q
->id
== IWL_CMD_QUEUE_NUM
)
228 len
+= IWL_MAX_SCAN_SIZE
;
230 /* De-alloc array of command/tx buffers */
231 slots_num
= (txq_id
== IWL_CMD_QUEUE_NUM
) ?
232 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
233 for (i
= 0; i
< slots_num
; i
++)
235 if (txq_id
== IWL_CMD_QUEUE_NUM
)
236 kfree(txq
->cmd
[slots_num
]);
238 /* De-alloc circular buffer of TFDs */
240 pci_free_consistent(dev
, sizeof(struct iwl_tfd_frame
) *
241 txq
->q
.n_bd
, txq
->bd
, txq
->q
.dma_addr
);
243 /* De-alloc array of per-TFD driver data */
247 /* 0-fill queue descriptor structure */
248 memset(txq
, 0, sizeof(*txq
));
251 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
254 * Theory of operation
256 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
257 * of buffer descriptors, each of which points to one or more data buffers for
258 * the device to read from or fill. Driver and device exchange status of each
259 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
260 * entries in each circular buffer, to protect against confusing empty and full
263 * The device reads or writes the data in the queues via the device's several
264 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
266 * For Tx queue, there are low mark and high mark limits. If, after queuing
267 * the packet for Tx, free space become < low mark, Tx queue stopped. When
268 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
271 * See more detailed info in iwl-4965-hw.h.
272 ***************************************************/
274 int iwl_queue_space(const struct iwl_queue
*q
)
276 int s
= q
->read_ptr
- q
->write_ptr
;
278 if (q
->read_ptr
> q
->write_ptr
)
283 /* keep some reserve to not confuse empty and full situations */
289 EXPORT_SYMBOL(iwl_queue_space
);
293 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
295 static int iwl_queue_init(struct iwl_priv
*priv
, struct iwl_queue
*q
,
296 int count
, int slots_num
, u32 id
)
299 q
->n_window
= slots_num
;
302 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
303 * and iwl_queue_dec_wrap are broken. */
304 BUG_ON(!is_power_of_2(count
));
306 /* slots_num must be power-of-two size, otherwise
307 * get_cmd_index is broken. */
308 BUG_ON(!is_power_of_2(slots_num
));
310 q
->low_mark
= q
->n_window
/ 4;
314 q
->high_mark
= q
->n_window
/ 8;
315 if (q
->high_mark
< 2)
318 q
->write_ptr
= q
->read_ptr
= 0;
324 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
326 static int iwl_tx_queue_alloc(struct iwl_priv
*priv
,
327 struct iwl_tx_queue
*txq
, u32 id
)
329 struct pci_dev
*dev
= priv
->pci_dev
;
331 /* Driver private data, only for Tx (not command) queues,
332 * not shared with device. */
333 if (id
!= IWL_CMD_QUEUE_NUM
) {
334 txq
->txb
= kmalloc(sizeof(txq
->txb
[0]) *
335 TFD_QUEUE_SIZE_MAX
, GFP_KERNEL
);
337 IWL_ERROR("kmalloc for auxiliary BD "
338 "structures failed\n");
344 /* Circular buffer of transmit frame descriptors (TFDs),
345 * shared with device */
346 txq
->bd
= pci_alloc_consistent(dev
,
347 sizeof(txq
->bd
[0]) * TFD_QUEUE_SIZE_MAX
,
351 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
352 sizeof(txq
->bd
[0]) * TFD_QUEUE_SIZE_MAX
);
367 * Tell nic where to find circular buffer of Tx Frame Descriptors for
368 * given Tx queue, and enable the DMA channel used for that queue.
370 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
371 * channels supported in hardware.
373 static int iwl_hw_tx_queue_init(struct iwl_priv
*priv
,
374 struct iwl_tx_queue
*txq
)
378 int txq_id
= txq
->q
.id
;
380 spin_lock_irqsave(&priv
->lock
, flags
);
381 rc
= iwl_grab_nic_access(priv
);
383 spin_unlock_irqrestore(&priv
->lock
, flags
);
387 /* Circular buffer (TFD queue in DRAM) physical base address */
388 iwl_write_direct32(priv
, FH_MEM_CBBC_QUEUE(txq_id
),
389 txq
->q
.dma_addr
>> 8);
391 /* Enable DMA channel, using same id as for TFD queue */
393 priv
, FH_TCSR_CHNL_TX_CONFIG_REG(txq_id
),
394 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
395 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
);
396 iwl_release_nic_access(priv
);
397 spin_unlock_irqrestore(&priv
->lock
, flags
);
403 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
405 static int iwl_tx_queue_init(struct iwl_priv
*priv
,
406 struct iwl_tx_queue
*txq
,
407 int slots_num
, u32 txq_id
)
413 * Alloc buffer array for commands (Tx or other types of commands).
414 * For the command queue (#4), allocate command space + one big
415 * command for scan, since scan command is very huge; the system will
416 * not have two scans at the same time, so only one is needed.
417 * For normal Tx queues (all other queues), no super-size command
420 len
= sizeof(struct iwl_cmd
);
421 for (i
= 0; i
<= slots_num
; i
++) {
422 if (i
== slots_num
) {
423 if (txq_id
== IWL_CMD_QUEUE_NUM
)
424 len
+= IWL_MAX_SCAN_SIZE
;
429 txq
->cmd
[i
] = kmalloc(len
, GFP_KERNEL
| GFP_DMA
);
434 /* Alloc driver data array and TFD circular buffer */
435 rc
= iwl_tx_queue_alloc(priv
, txq
, txq_id
);
437 for (i
= 0; i
< slots_num
; i
++)
442 txq
->need_update
= 0;
444 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
445 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
446 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX
& (TFD_QUEUE_SIZE_MAX
- 1));
448 /* Initialize queue's high/low-water marks, and head/tail indexes */
449 iwl_queue_init(priv
, &txq
->q
, TFD_QUEUE_SIZE_MAX
, slots_num
, txq_id
);
451 /* Tell device where to find queue */
452 iwl_hw_tx_queue_init(priv
, txq
);
457 * iwl_hw_txq_ctx_free - Free TXQ Context
459 * Destroy all TX DMA queues and structures
461 void iwl_hw_txq_ctx_free(struct iwl_priv
*priv
)
466 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++)
467 iwl_tx_queue_free(priv
, txq_id
);
469 /* Keep-warm buffer */
472 EXPORT_SYMBOL(iwl_hw_txq_ctx_free
);
476 * iwl_txq_ctx_reset - Reset TX queue context
477 * Destroys all DMA structures and initialise them again
482 int iwl_txq_ctx_reset(struct iwl_priv
*priv
)
485 int txq_id
, slots_num
;
490 /* Free all tx/cmd queues and keep-warm buffer */
491 iwl_hw_txq_ctx_free(priv
);
493 /* Alloc keep-warm buffer */
494 ret
= iwl_kw_alloc(priv
);
496 IWL_ERROR("Keep Warm allocation failed\n");
499 spin_lock_irqsave(&priv
->lock
, flags
);
500 ret
= iwl_grab_nic_access(priv
);
502 spin_unlock_irqrestore(&priv
->lock
, flags
);
506 /* Turn off all Tx DMA fifos */
507 priv
->cfg
->ops
->lib
->txq_set_sched(priv
, 0);
509 iwl_release_nic_access(priv
);
510 spin_unlock_irqrestore(&priv
->lock
, flags
);
513 /* Tell nic where to find the keep-warm buffer */
514 ret
= iwl_kw_init(priv
);
516 IWL_ERROR("kw_init failed\n");
520 /* Alloc and init all Tx queues, including the command queue (#4) */
521 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++) {
522 slots_num
= (txq_id
== IWL_CMD_QUEUE_NUM
) ?
523 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
524 ret
= iwl_tx_queue_init(priv
, &priv
->txq
[txq_id
], slots_num
,
527 IWL_ERROR("Tx %d queue init failed\n", txq_id
);
535 iwl_hw_txq_ctx_free(priv
);
542 * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
544 void iwl_txq_ctx_stop(struct iwl_priv
*priv
)
551 /* Turn off all Tx DMA fifos */
552 spin_lock_irqsave(&priv
->lock
, flags
);
553 if (iwl_grab_nic_access(priv
)) {
554 spin_unlock_irqrestore(&priv
->lock
, flags
);
558 priv
->cfg
->ops
->lib
->txq_set_sched(priv
, 0);
560 /* Stop each Tx DMA channel, and wait for it to be idle */
561 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++) {
562 iwl_write_direct32(priv
,
563 FH_TCSR_CHNL_TX_CONFIG_REG(txq_id
), 0x0);
564 iwl_poll_direct_bit(priv
, FH_TSSR_TX_STATUS_REG
,
565 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
568 iwl_release_nic_access(priv
);
569 spin_unlock_irqrestore(&priv
->lock
, flags
);
571 /* Deallocate memory for all Tx queues */
572 iwl_hw_txq_ctx_free(priv
);
574 EXPORT_SYMBOL(iwl_txq_ctx_stop
);
577 * handle build REPLY_TX command notification.
579 static void iwl_tx_cmd_build_basic(struct iwl_priv
*priv
,
580 struct iwl_tx_cmd
*tx_cmd
,
581 struct ieee80211_tx_info
*info
,
582 struct ieee80211_hdr
*hdr
,
583 int is_unicast
, u8 std_id
)
585 __le16 fc
= hdr
->frame_control
;
586 __le32 tx_flags
= tx_cmd
->tx_flags
;
588 tx_cmd
->stop_time
.life_time
= TX_CMD_LIFE_TIME_INFINITE
;
589 if (!(info
->flags
& IEEE80211_TX_CTL_NO_ACK
)) {
590 tx_flags
|= TX_CMD_FLG_ACK_MSK
;
591 if (ieee80211_is_mgmt(fc
))
592 tx_flags
|= TX_CMD_FLG_SEQ_CTL_MSK
;
593 if (ieee80211_is_probe_resp(fc
) &&
594 !(le16_to_cpu(hdr
->seq_ctrl
) & 0xf))
595 tx_flags
|= TX_CMD_FLG_TSF_MSK
;
597 tx_flags
&= (~TX_CMD_FLG_ACK_MSK
);
598 tx_flags
|= TX_CMD_FLG_SEQ_CTL_MSK
;
601 if (ieee80211_is_back_req(fc
))
602 tx_flags
|= TX_CMD_FLG_ACK_MSK
| TX_CMD_FLG_IMM_BA_RSP_MASK
;
605 tx_cmd
->sta_id
= std_id
;
606 if (ieee80211_has_morefrags(fc
))
607 tx_flags
|= TX_CMD_FLG_MORE_FRAG_MSK
;
609 if (ieee80211_is_data_qos(fc
)) {
610 u8
*qc
= ieee80211_get_qos_ctl(hdr
);
611 tx_cmd
->tid_tspec
= qc
[0] & 0xf;
612 tx_flags
&= ~TX_CMD_FLG_SEQ_CTL_MSK
;
614 tx_flags
|= TX_CMD_FLG_SEQ_CTL_MSK
;
617 priv
->cfg
->ops
->utils
->rts_tx_cmd_flag(info
, &tx_flags
);
619 if ((tx_flags
& TX_CMD_FLG_RTS_MSK
) || (tx_flags
& TX_CMD_FLG_CTS_MSK
))
620 tx_flags
|= TX_CMD_FLG_FULL_TXOP_PROT_MSK
;
622 tx_flags
&= ~(TX_CMD_FLG_ANT_SEL_MSK
);
623 if (ieee80211_is_mgmt(fc
)) {
624 if (ieee80211_is_assoc_req(fc
) || ieee80211_is_reassoc_req(fc
))
625 tx_cmd
->timeout
.pm_frame_timeout
= cpu_to_le16(3);
627 tx_cmd
->timeout
.pm_frame_timeout
= cpu_to_le16(2);
629 tx_cmd
->timeout
.pm_frame_timeout
= 0;
632 tx_cmd
->driver_txop
= 0;
633 tx_cmd
->tx_flags
= tx_flags
;
634 tx_cmd
->next_frame_len
= 0;
637 #define RTS_HCCA_RETRY_LIMIT 3
638 #define RTS_DFAULT_RETRY_LIMIT 60
640 static void iwl_tx_cmd_build_rate(struct iwl_priv
*priv
,
641 struct iwl_tx_cmd
*tx_cmd
,
642 struct ieee80211_tx_info
*info
,
643 __le16 fc
, int sta_id
,
646 u8 rts_retry_limit
= 0;
647 u8 data_retry_limit
= 0;
652 rate_idx
= min(ieee80211_get_tx_rate(priv
->hw
, info
)->hw_value
& 0xffff,
655 rate_plcp
= iwl_rates
[rate_idx
].plcp
;
657 rts_retry_limit
= (is_hcca
) ?
658 RTS_HCCA_RETRY_LIMIT
: RTS_DFAULT_RETRY_LIMIT
;
660 if ((rate_idx
>= IWL_FIRST_CCK_RATE
) && (rate_idx
<= IWL_LAST_CCK_RATE
))
661 rate_flags
|= RATE_MCS_CCK_MSK
;
664 if (ieee80211_is_probe_resp(fc
)) {
665 data_retry_limit
= 3;
666 if (data_retry_limit
< rts_retry_limit
)
667 rts_retry_limit
= data_retry_limit
;
669 data_retry_limit
= IWL_DEFAULT_TX_RETRY
;
671 if (priv
->data_retry_limit
!= -1)
672 data_retry_limit
= priv
->data_retry_limit
;
675 if (ieee80211_is_data(fc
)) {
676 tx_cmd
->initial_rate_index
= 0;
677 tx_cmd
->tx_flags
|= TX_CMD_FLG_STA_RATE_MSK
;
679 switch (fc
& cpu_to_le16(IEEE80211_FCTL_STYPE
)) {
680 case cpu_to_le16(IEEE80211_STYPE_AUTH
):
681 case cpu_to_le16(IEEE80211_STYPE_DEAUTH
):
682 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ
):
683 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ
):
684 if (tx_cmd
->tx_flags
& TX_CMD_FLG_RTS_MSK
) {
685 tx_cmd
->tx_flags
&= ~TX_CMD_FLG_RTS_MSK
;
686 tx_cmd
->tx_flags
|= TX_CMD_FLG_CTS_MSK
;
693 /* Alternate between antenna A and B for successive frames */
694 if (priv
->use_ant_b_for_management_frame
) {
695 priv
->use_ant_b_for_management_frame
= 0;
696 rate_flags
|= RATE_MCS_ANT_B_MSK
;
698 priv
->use_ant_b_for_management_frame
= 1;
699 rate_flags
|= RATE_MCS_ANT_A_MSK
;
703 tx_cmd
->rts_retry_limit
= rts_retry_limit
;
704 tx_cmd
->data_retry_limit
= data_retry_limit
;
705 tx_cmd
->rate_n_flags
= iwl_hw_set_rate_n_flags(rate_plcp
, rate_flags
);
708 static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv
*priv
,
709 struct ieee80211_tx_info
*info
,
710 struct iwl_tx_cmd
*tx_cmd
,
711 struct sk_buff
*skb_frag
,
714 struct ieee80211_key_conf
*keyconf
= info
->control
.hw_key
;
716 switch (keyconf
->alg
) {
718 tx_cmd
->sec_ctl
= TX_CMD_SEC_CCM
;
719 memcpy(tx_cmd
->key
, keyconf
->key
, keyconf
->keylen
);
720 if (info
->flags
& IEEE80211_TX_CTL_AMPDU
)
721 tx_cmd
->tx_flags
|= TX_CMD_FLG_AGG_CCMP_MSK
;
722 IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
726 tx_cmd
->sec_ctl
= TX_CMD_SEC_TKIP
;
727 ieee80211_get_tkip_key(keyconf
, skb_frag
,
728 IEEE80211_TKIP_P2_KEY
, tx_cmd
->key
);
729 IWL_DEBUG_TX("tx_cmd with tkip hwcrypto\n");
733 tx_cmd
->sec_ctl
|= (TX_CMD_SEC_WEP
|
734 (keyconf
->keyidx
& TX_CMD_SEC_MSK
) << TX_CMD_SEC_SHIFT
);
736 if (keyconf
->keylen
== WEP_KEY_LEN_128
)
737 tx_cmd
->sec_ctl
|= TX_CMD_SEC_KEY128
;
739 memcpy(&tx_cmd
->key
[3], keyconf
->key
, keyconf
->keylen
);
741 IWL_DEBUG_TX("Configuring packet for WEP encryption "
742 "with key %d\n", keyconf
->keyidx
);
746 printk(KERN_ERR
"Unknown encode alg %d\n", keyconf
->alg
);
751 static void iwl_update_tx_stats(struct iwl_priv
*priv
, u16 fc
, u16 len
)
753 /* 0 - mgmt, 1 - cnt, 2 - data */
754 int idx
= (fc
& IEEE80211_FCTL_FTYPE
) >> 2;
755 priv
->tx_stats
[idx
].cnt
++;
756 priv
->tx_stats
[idx
].bytes
+= len
;
760 * start REPLY_TX command process
762 int iwl_tx_skb(struct iwl_priv
*priv
, struct sk_buff
*skb
)
764 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
765 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
766 struct iwl_tfd_frame
*tfd
;
767 struct iwl_tx_queue
*txq
;
769 struct iwl_cmd
*out_cmd
;
770 struct iwl_tx_cmd
*tx_cmd
;
772 dma_addr_t phys_addr
;
773 dma_addr_t txcmd_phys
;
774 dma_addr_t scratch_phys
;
775 u16 len
, idx
, len_org
;
780 u8 wait_write_ptr
= 0;
786 spin_lock_irqsave(&priv
->lock
, flags
);
787 if (iwl_is_rfkill(priv
)) {
788 IWL_DEBUG_DROP("Dropping - RF KILL\n");
793 IWL_DEBUG_DROP("Dropping - !priv->vif\n");
797 if ((ieee80211_get_tx_rate(priv
->hw
, info
)->hw_value
& 0xFF) ==
799 IWL_ERROR("ERROR: No TX rate available.\n");
803 unicast
= !is_multicast_ether_addr(hdr
->addr1
);
805 fc
= hdr
->frame_control
;
807 #ifdef CONFIG_IWLWIFI_DEBUG
808 if (ieee80211_is_auth(fc
))
809 IWL_DEBUG_TX("Sending AUTH frame\n");
810 else if (ieee80211_is_assoc_req(fc
))
811 IWL_DEBUG_TX("Sending ASSOC frame\n");
812 else if (ieee80211_is_reassoc_req(fc
))
813 IWL_DEBUG_TX("Sending REASSOC frame\n");
816 /* drop all data frame if we are not associated */
817 if (ieee80211_is_data(fc
) &&
818 (!iwl_is_associated(priv
) ||
819 ((priv
->iw_mode
== IEEE80211_IF_TYPE_STA
) && !priv
->assoc_id
) ||
820 !priv
->assoc_station_added
)) {
821 IWL_DEBUG_DROP("Dropping - !iwl_is_associated\n");
825 spin_unlock_irqrestore(&priv
->lock
, flags
);
827 hdr_len
= ieee80211_get_hdrlen(le16_to_cpu(fc
));
829 /* Find (or create) index into station table for destination station */
830 sta_id
= iwl_get_sta_id(priv
, hdr
);
831 if (sta_id
== IWL_INVALID_STATION
) {
832 DECLARE_MAC_BUF(mac
);
834 IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
835 print_mac(mac
, hdr
->addr1
));
839 IWL_DEBUG_TX("station Id %d\n", sta_id
);
841 swq_id
= skb_get_queue_mapping(skb
);
843 if (ieee80211_is_data_qos(fc
)) {
844 qc
= ieee80211_get_qos_ctl(hdr
);
846 seq_number
= priv
->stations
[sta_id
].tid
[tid
].seq_number
;
847 seq_number
&= IEEE80211_SCTL_SEQ
;
848 hdr
->seq_ctrl
= hdr
->seq_ctrl
&
849 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG
);
850 hdr
->seq_ctrl
|= cpu_to_le16(seq_number
);
852 /* aggregation is on for this <sta,tid> */
853 if (info
->flags
& IEEE80211_TX_CTL_AMPDU
)
854 txq_id
= priv
->stations
[sta_id
].tid
[tid
].agg
.txq_id
;
855 priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
++;
858 /* Descriptor for chosen Tx queue */
859 txq
= &priv
->txq
[txq_id
];
862 spin_lock_irqsave(&priv
->lock
, flags
);
864 /* Set up first empty TFD within this queue's circular TFD buffer */
865 tfd
= &txq
->bd
[q
->write_ptr
];
866 memset(tfd
, 0, sizeof(*tfd
));
867 idx
= get_cmd_index(q
, q
->write_ptr
, 0);
869 /* Set up driver data for this TFD */
870 memset(&(txq
->txb
[q
->write_ptr
]), 0, sizeof(struct iwl_tx_info
));
871 txq
->txb
[q
->write_ptr
].skb
[0] = skb
;
873 /* Set up first empty entry in queue's array of Tx/cmd buffers */
874 out_cmd
= txq
->cmd
[idx
];
875 tx_cmd
= &out_cmd
->cmd
.tx
;
876 memset(&out_cmd
->hdr
, 0, sizeof(out_cmd
->hdr
));
877 memset(tx_cmd
, 0, sizeof(struct iwl_tx_cmd
));
880 * Set up the Tx-command (not MAC!) header.
881 * Store the chosen Tx queue and TFD index within the sequence field;
882 * after Tx, uCode's Tx response will return this value so driver can
883 * locate the frame within the tx queue and do post-tx processing.
885 out_cmd
->hdr
.cmd
= REPLY_TX
;
886 out_cmd
->hdr
.sequence
= cpu_to_le16((u16
)(QUEUE_TO_SEQ(txq_id
) |
887 INDEX_TO_SEQ(q
->write_ptr
)));
889 /* Copy MAC header from skb into command buffer */
890 memcpy(tx_cmd
->hdr
, hdr
, hdr_len
);
893 * Use the first empty entry in this queue's command buffer array
894 * to contain the Tx command and MAC header concatenated together
895 * (payload data will be in another buffer).
896 * Size of this varies, due to varying MAC header length.
897 * If end is not dword aligned, we'll have 2 extra bytes at the end
898 * of the MAC header (device reads on dword boundaries).
899 * We'll tell device about this padding later.
901 len
= sizeof(struct iwl_tx_cmd
) +
902 sizeof(struct iwl_cmd_header
) + hdr_len
;
905 len
= (len
+ 3) & ~3;
912 /* Physical address of this Tx command's header (not MAC header!),
913 * within command buffer array. */
914 txcmd_phys
= pci_map_single(priv
->pci_dev
, out_cmd
,
915 sizeof(struct iwl_cmd
), PCI_DMA_TODEVICE
);
916 txcmd_phys
+= offsetof(struct iwl_cmd
, hdr
);
918 /* Add buffer containing Tx command and MAC(!) header to TFD's
920 iwl_hw_txq_attach_buf_to_tfd(priv
, tfd
, txcmd_phys
, len
);
922 if (info
->control
.hw_key
)
923 iwl_tx_cmd_build_hwcrypto(priv
, info
, tx_cmd
, skb
, sta_id
);
925 /* Set up TFD's 2nd entry to point directly to remainder of skb,
926 * if any (802.11 null frames have no payload). */
927 len
= skb
->len
- hdr_len
;
929 phys_addr
= pci_map_single(priv
->pci_dev
, skb
->data
+ hdr_len
,
930 len
, PCI_DMA_TODEVICE
);
931 iwl_hw_txq_attach_buf_to_tfd(priv
, tfd
, phys_addr
, len
);
934 /* Tell NIC about any 2-byte padding after MAC header */
936 tx_cmd
->tx_flags
|= TX_CMD_FLG_MH_PAD_MSK
;
938 /* Total # bytes to be transmitted */
940 tx_cmd
->len
= cpu_to_le16(len
);
941 /* TODO need this for burst mode later on */
942 iwl_tx_cmd_build_basic(priv
, tx_cmd
, info
, hdr
, unicast
, sta_id
);
944 /* set is_hcca to 0; it probably will never be implemented */
945 iwl_tx_cmd_build_rate(priv
, tx_cmd
, info
, fc
, sta_id
, 0);
947 iwl_update_tx_stats(priv
, le16_to_cpu(fc
), len
);
949 scratch_phys
= txcmd_phys
+ sizeof(struct iwl_cmd_header
) +
950 offsetof(struct iwl_tx_cmd
, scratch
);
951 tx_cmd
->dram_lsb_ptr
= cpu_to_le32(scratch_phys
);
952 tx_cmd
->dram_msb_ptr
= iwl_get_dma_hi_address(scratch_phys
);
954 if (!ieee80211_has_morefrags(hdr
->frame_control
)) {
955 txq
->need_update
= 1;
957 priv
->stations
[sta_id
].tid
[tid
].seq_number
= seq_number
;
960 txq
->need_update
= 0;
963 iwl_print_hex_dump(priv
, IWL_DL_TX
, (u8
*)tx_cmd
, sizeof(*tx_cmd
));
965 iwl_print_hex_dump(priv
, IWL_DL_TX
, (u8
*)tx_cmd
->hdr
, hdr_len
);
967 /* Set up entry for this TFD in Tx byte-count array */
968 priv
->cfg
->ops
->lib
->txq_update_byte_cnt_tbl(priv
, txq
, len
);
970 /* Tell device the write index *just past* this latest filled TFD */
971 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
972 ret
= iwl_txq_update_write_ptr(priv
, txq
);
973 spin_unlock_irqrestore(&priv
->lock
, flags
);
978 if ((iwl_queue_space(q
) < q
->high_mark
) && priv
->mac80211_registered
) {
979 if (wait_write_ptr
) {
980 spin_lock_irqsave(&priv
->lock
, flags
);
981 txq
->need_update
= 1;
982 iwl_txq_update_write_ptr(priv
, txq
);
983 spin_unlock_irqrestore(&priv
->lock
, flags
);
985 ieee80211_stop_queue(priv
->hw
, swq_id
);
992 spin_unlock_irqrestore(&priv
->lock
, flags
);
996 EXPORT_SYMBOL(iwl_tx_skb
);
998 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1001 * iwl_enqueue_hcmd - enqueue a uCode command
1002 * @priv: device private data point
1003 * @cmd: a point to the ucode command structure
1005 * The function returns < 0 values to indicate the operation is
1006 * failed. On success, it turns the index (> 0) of command in the
1009 int iwl_enqueue_hcmd(struct iwl_priv
*priv
, struct iwl_host_cmd
*cmd
)
1011 struct iwl_tx_queue
*txq
= &priv
->txq
[IWL_CMD_QUEUE_NUM
];
1012 struct iwl_queue
*q
= &txq
->q
;
1013 struct iwl_tfd_frame
*tfd
;
1014 struct iwl_cmd
*out_cmd
;
1015 dma_addr_t phys_addr
;
1016 unsigned long flags
;
1021 cmd
->len
= priv
->cfg
->ops
->utils
->get_hcmd_size(cmd
->id
, cmd
->len
);
1022 fix_size
= (u16
)(cmd
->len
+ sizeof(out_cmd
->hdr
));
1024 /* If any of the command structures end up being larger than
1025 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
1026 * we will need to increase the size of the TFD entries */
1027 BUG_ON((fix_size
> TFD_MAX_PAYLOAD_SIZE
) &&
1028 !(cmd
->meta
.flags
& CMD_SIZE_HUGE
));
1030 if (iwl_is_rfkill(priv
)) {
1031 IWL_DEBUG_INFO("Not sending command - RF KILL");
1035 if (iwl_queue_space(q
) < ((cmd
->meta
.flags
& CMD_ASYNC
) ? 2 : 1)) {
1036 IWL_ERROR("No space for Tx\n");
1040 spin_lock_irqsave(&priv
->hcmd_lock
, flags
);
1042 tfd
= &txq
->bd
[q
->write_ptr
];
1043 memset(tfd
, 0, sizeof(*tfd
));
1046 idx
= get_cmd_index(q
, q
->write_ptr
, cmd
->meta
.flags
& CMD_SIZE_HUGE
);
1047 out_cmd
= txq
->cmd
[idx
];
1049 out_cmd
->hdr
.cmd
= cmd
->id
;
1050 memcpy(&out_cmd
->meta
, &cmd
->meta
, sizeof(cmd
->meta
));
1051 memcpy(&out_cmd
->cmd
.payload
, cmd
->data
, cmd
->len
);
1053 /* At this point, the out_cmd now has all of the incoming cmd
1056 out_cmd
->hdr
.flags
= 0;
1057 out_cmd
->hdr
.sequence
= cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM
) |
1058 INDEX_TO_SEQ(q
->write_ptr
));
1059 if (out_cmd
->meta
.flags
& CMD_SIZE_HUGE
)
1060 out_cmd
->hdr
.sequence
|= cpu_to_le16(SEQ_HUGE_FRAME
);
1061 len
= (idx
== TFD_CMD_SLOTS
) ?
1062 IWL_MAX_SCAN_SIZE
: sizeof(struct iwl_cmd
);
1063 phys_addr
= pci_map_single(priv
->pci_dev
, out_cmd
, len
,
1065 phys_addr
+= offsetof(struct iwl_cmd
, hdr
);
1066 iwl_hw_txq_attach_buf_to_tfd(priv
, tfd
, phys_addr
, fix_size
);
1068 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
1069 "%d bytes at %d[%d]:%d\n",
1070 get_cmd_string(out_cmd
->hdr
.cmd
),
1071 out_cmd
->hdr
.cmd
, le16_to_cpu(out_cmd
->hdr
.sequence
),
1072 fix_size
, q
->write_ptr
, idx
, IWL_CMD_QUEUE_NUM
);
1074 txq
->need_update
= 1;
1076 /* Set up entry in queue's byte count circular buffer */
1077 priv
->cfg
->ops
->lib
->txq_update_byte_cnt_tbl(priv
, txq
, 0);
1079 /* Increment and update queue's write index */
1080 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
1081 ret
= iwl_txq_update_write_ptr(priv
, txq
);
1083 spin_unlock_irqrestore(&priv
->hcmd_lock
, flags
);
1084 return ret
? ret
: idx
;
1087 int iwl_tx_queue_reclaim(struct iwl_priv
*priv
, int txq_id
, int index
)
1089 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
1090 struct iwl_queue
*q
= &txq
->q
;
1091 struct iwl_tx_info
*tx_info
;
1094 if ((index
>= q
->n_bd
) || (iwl_queue_used(q
, index
) == 0)) {
1095 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
1096 "is out of range [0-%d] %d %d.\n", txq_id
,
1097 index
, q
->n_bd
, q
->write_ptr
, q
->read_ptr
);
1101 for (index
= iwl_queue_inc_wrap(index
, q
->n_bd
); q
->read_ptr
!= index
;
1102 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
1104 tx_info
= &txq
->txb
[txq
->q
.read_ptr
];
1105 ieee80211_tx_status_irqsafe(priv
->hw
, tx_info
->skb
[0]);
1106 tx_info
->skb
[0] = NULL
;
1108 if (priv
->cfg
->ops
->lib
->txq_inval_byte_cnt_tbl
)
1109 priv
->cfg
->ops
->lib
->txq_inval_byte_cnt_tbl(priv
, txq
);
1111 iwl_hw_txq_free_tfd(priv
, txq
);
1116 EXPORT_SYMBOL(iwl_tx_queue_reclaim
);
1120 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
1122 * When FW advances 'R' index, all entries between old and new 'R' index
1123 * need to be reclaimed. As result, some free space forms. If there is
1124 * enough free space (> low mark), wake the stack that feeds us.
1126 static void iwl_hcmd_queue_reclaim(struct iwl_priv
*priv
, int txq_id
, int index
)
1128 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
1129 struct iwl_queue
*q
= &txq
->q
;
1130 struct iwl_tfd_frame
*bd
= &txq
->bd
[index
];
1131 dma_addr_t dma_addr
;
1132 int is_odd
, buf_len
;
1135 if ((index
>= q
->n_bd
) || (iwl_queue_used(q
, index
) == 0)) {
1136 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
1137 "is out of range [0-%d] %d %d.\n", txq_id
,
1138 index
, q
->n_bd
, q
->write_ptr
, q
->read_ptr
);
1142 for (index
= iwl_queue_inc_wrap(index
, q
->n_bd
); q
->read_ptr
!= index
;
1143 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
1146 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index
,
1147 q
->write_ptr
, q
->read_ptr
);
1148 queue_work(priv
->workqueue
, &priv
->restart
);
1150 is_odd
= (index
/2) & 0x1;
1152 dma_addr
= IWL_GET_BITS(bd
->pa
[index
], tb2_addr_lo16
) |
1153 (IWL_GET_BITS(bd
->pa
[index
],
1154 tb2_addr_hi20
) << 16);
1155 buf_len
= IWL_GET_BITS(bd
->pa
[index
], tb2_len
);
1157 dma_addr
= le32_to_cpu(bd
->pa
[index
].tb1_addr
);
1158 buf_len
= IWL_GET_BITS(bd
->pa
[index
], tb1_len
);
1161 pci_unmap_single(priv
->pci_dev
, dma_addr
, buf_len
,
1168 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
1169 * @rxb: Rx buffer to reclaim
1171 * If an Rx buffer has an async callback associated with it the callback
1172 * will be executed. The attached skb (if present) will only be freed
1173 * if the callback returns 1
1175 void iwl_tx_cmd_complete(struct iwl_priv
*priv
, struct iwl_rx_mem_buffer
*rxb
)
1177 struct iwl_rx_packet
*pkt
= (struct iwl_rx_packet
*)rxb
->skb
->data
;
1178 u16 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
1179 int txq_id
= SEQ_TO_QUEUE(sequence
);
1180 int index
= SEQ_TO_INDEX(sequence
);
1181 int huge
= sequence
& SEQ_HUGE_FRAME
;
1183 struct iwl_cmd
*cmd
;
1185 /* If a Tx command is being handled and it isn't in the actual
1186 * command queue then there a command routing bug has been introduced
1187 * in the queue management code. */
1188 if (txq_id
!= IWL_CMD_QUEUE_NUM
)
1189 IWL_ERROR("Error wrong command queue %d command id 0x%X\n",
1190 txq_id
, pkt
->hdr
.cmd
);
1191 BUG_ON(txq_id
!= IWL_CMD_QUEUE_NUM
);
1193 cmd_index
= get_cmd_index(&priv
->txq
[IWL_CMD_QUEUE_NUM
].q
, index
, huge
);
1194 cmd
= priv
->txq
[IWL_CMD_QUEUE_NUM
].cmd
[cmd_index
];
1196 /* Input error checking is done when commands are added to queue. */
1197 if (cmd
->meta
.flags
& CMD_WANT_SKB
) {
1198 cmd
->meta
.source
->u
.skb
= rxb
->skb
;
1200 } else if (cmd
->meta
.u
.callback
&&
1201 !cmd
->meta
.u
.callback(priv
, cmd
, rxb
->skb
))
1204 iwl_hcmd_queue_reclaim(priv
, txq_id
, index
);
1206 if (!(cmd
->meta
.flags
& CMD_ASYNC
)) {
1207 clear_bit(STATUS_HCMD_ACTIVE
, &priv
->status
);
1208 wake_up_interruptible(&priv
->wait_command_queue
);
1211 EXPORT_SYMBOL(iwl_tx_cmd_complete
);
1214 * Find first available (lowest unused) Tx Queue, mark it "active".
1215 * Called only when finding queue for aggregation.
1216 * Should never return anything < 7, because they should already
1217 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
1219 static int iwl_txq_ctx_activate_free(struct iwl_priv
*priv
)
1223 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++)
1224 if (!test_and_set_bit(txq_id
, &priv
->txq_ctx_active_msk
))
1229 int iwl_tx_agg_start(struct iwl_priv
*priv
, const u8
*ra
, u16 tid
, u16
*ssn
)
1235 unsigned long flags
;
1236 struct iwl_tid_data
*tid_data
;
1237 DECLARE_MAC_BUF(mac
);
1239 if (likely(tid
< ARRAY_SIZE(default_tid_to_tx_fifo
)))
1240 tx_fifo
= default_tid_to_tx_fifo
[tid
];
1244 IWL_WARNING("%s on ra = %s tid = %d\n",
1245 __func__
, print_mac(mac
, ra
), tid
);
1247 sta_id
= iwl_find_station(priv
, ra
);
1248 if (sta_id
== IWL_INVALID_STATION
)
1251 if (priv
->stations
[sta_id
].tid
[tid
].agg
.state
!= IWL_AGG_OFF
) {
1252 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
1256 txq_id
= iwl_txq_ctx_activate_free(priv
);
1260 spin_lock_irqsave(&priv
->sta_lock
, flags
);
1261 tid_data
= &priv
->stations
[sta_id
].tid
[tid
];
1262 *ssn
= SEQ_TO_SN(tid_data
->seq_number
);
1263 tid_data
->agg
.txq_id
= txq_id
;
1264 spin_unlock_irqrestore(&priv
->sta_lock
, flags
);
1266 ret
= priv
->cfg
->ops
->lib
->txq_agg_enable(priv
, txq_id
, tx_fifo
,
1271 if (tid_data
->tfds_in_queue
== 0) {
1272 printk(KERN_ERR
"HW queue is empty\n");
1273 tid_data
->agg
.state
= IWL_AGG_ON
;
1274 ieee80211_start_tx_ba_cb_irqsafe(priv
->hw
, ra
, tid
);
1276 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
1277 tid_data
->tfds_in_queue
);
1278 tid_data
->agg
.state
= IWL_EMPTYING_HW_QUEUE_ADDBA
;
1282 EXPORT_SYMBOL(iwl_tx_agg_start
);
1284 int iwl_tx_agg_stop(struct iwl_priv
*priv
, const u8
*ra
, u16 tid
)
1286 int tx_fifo_id
, txq_id
, sta_id
, ssn
= -1;
1287 struct iwl_tid_data
*tid_data
;
1288 int ret
, write_ptr
, read_ptr
;
1289 unsigned long flags
;
1290 DECLARE_MAC_BUF(mac
);
1293 IWL_ERROR("ra = NULL\n");
1297 if (likely(tid
< ARRAY_SIZE(default_tid_to_tx_fifo
)))
1298 tx_fifo_id
= default_tid_to_tx_fifo
[tid
];
1302 sta_id
= iwl_find_station(priv
, ra
);
1304 if (sta_id
== IWL_INVALID_STATION
)
1307 if (priv
->stations
[sta_id
].tid
[tid
].agg
.state
!= IWL_AGG_ON
)
1308 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
1310 tid_data
= &priv
->stations
[sta_id
].tid
[tid
];
1311 ssn
= (tid_data
->seq_number
& IEEE80211_SCTL_SEQ
) >> 4;
1312 txq_id
= tid_data
->agg
.txq_id
;
1313 write_ptr
= priv
->txq
[txq_id
].q
.write_ptr
;
1314 read_ptr
= priv
->txq
[txq_id
].q
.read_ptr
;
1316 /* The queue is not empty */
1317 if (write_ptr
!= read_ptr
) {
1318 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
1319 priv
->stations
[sta_id
].tid
[tid
].agg
.state
=
1320 IWL_EMPTYING_HW_QUEUE_DELBA
;
1324 IWL_DEBUG_HT("HW queue is empty\n");
1325 priv
->stations
[sta_id
].tid
[tid
].agg
.state
= IWL_AGG_OFF
;
1327 spin_lock_irqsave(&priv
->lock
, flags
);
1328 ret
= priv
->cfg
->ops
->lib
->txq_agg_disable(priv
, txq_id
, ssn
,
1330 spin_unlock_irqrestore(&priv
->lock
, flags
);
1335 ieee80211_stop_tx_ba_cb_irqsafe(priv
->hw
, ra
, tid
);
1339 EXPORT_SYMBOL(iwl_tx_agg_stop
);
1341 int iwl_txq_check_empty(struct iwl_priv
*priv
, int sta_id
, u8 tid
, int txq_id
)
1343 struct iwl_queue
*q
= &priv
->txq
[txq_id
].q
;
1344 u8
*addr
= priv
->stations
[sta_id
].sta
.sta
.addr
;
1345 struct iwl_tid_data
*tid_data
= &priv
->stations
[sta_id
].tid
[tid
];
1347 switch (priv
->stations
[sta_id
].tid
[tid
].agg
.state
) {
1348 case IWL_EMPTYING_HW_QUEUE_DELBA
:
1349 /* We are reclaiming the last packet of the */
1350 /* aggregated HW queue */
1351 if (txq_id
== tid_data
->agg
.txq_id
&&
1352 q
->read_ptr
== q
->write_ptr
) {
1353 u16 ssn
= SEQ_TO_SN(tid_data
->seq_number
);
1354 int tx_fifo
= default_tid_to_tx_fifo
[tid
];
1355 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
1356 priv
->cfg
->ops
->lib
->txq_agg_disable(priv
, txq_id
,
1358 tid_data
->agg
.state
= IWL_AGG_OFF
;
1359 ieee80211_stop_tx_ba_cb_irqsafe(priv
->hw
, addr
, tid
);
1362 case IWL_EMPTYING_HW_QUEUE_ADDBA
:
1363 /* We are reclaiming the last packet of the queue */
1364 if (tid_data
->tfds_in_queue
== 0) {
1365 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
1366 tid_data
->agg
.state
= IWL_AGG_ON
;
1367 ieee80211_start_tx_ba_cb_irqsafe(priv
->hw
, addr
, tid
);
1373 EXPORT_SYMBOL(iwl_txq_check_empty
);
1376 * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack
1378 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1379 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1381 static int iwl_tx_status_reply_compressed_ba(struct iwl_priv
*priv
,
1382 struct iwl_ht_agg
*agg
,
1383 struct iwl_compressed_ba_resp
*ba_resp
)
1387 u16 seq_ctl
= le16_to_cpu(ba_resp
->seq_ctl
);
1388 u16 scd_flow
= le16_to_cpu(ba_resp
->scd_flow
);
1391 struct ieee80211_tx_info
*info
;
1393 if (unlikely(!agg
->wait_for_ba
)) {
1394 IWL_ERROR("Received BA when not expected\n");
1398 /* Mark that the expected block-ack response arrived */
1399 agg
->wait_for_ba
= 0;
1400 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg
->start_idx
, ba_resp
->seq_ctl
);
1402 /* Calculate shift to align block-ack bits with our Tx window bits */
1403 sh
= agg
->start_idx
- SEQ_TO_INDEX(seq_ctl
>>4);
1404 if (sh
< 0) /* tbw something is wrong with indices */
1407 /* don't use 64-bit values for now */
1408 bitmap
= le64_to_cpu(ba_resp
->bitmap
) >> sh
;
1410 if (agg
->frame_count
> (64 - sh
)) {
1411 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
1415 /* check for success or failure according to the
1416 * transmitted bitmap and block-ack bitmap */
1417 bitmap
&= agg
->bitmap
;
1419 /* For each frame attempted in aggregation,
1420 * update driver's record of tx frame's status. */
1421 for (i
= 0; i
< agg
->frame_count
; i
++) {
1422 ack
= bitmap
& (1ULL << i
);
1424 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
1425 ack
? "ACK":"NACK", i
, (agg
->start_idx
+ i
) & 0xff,
1426 agg
->start_idx
+ i
);
1429 info
= IEEE80211_SKB_CB(priv
->txq
[scd_flow
].txb
[agg
->start_idx
].skb
[0]);
1430 memset(&info
->status
, 0, sizeof(info
->status
));
1431 info
->flags
= IEEE80211_TX_STAT_ACK
;
1432 info
->flags
|= IEEE80211_TX_STAT_AMPDU
;
1433 info
->status
.ampdu_ack_map
= successes
;
1434 info
->status
.ampdu_ack_len
= agg
->frame_count
;
1435 iwl_hwrate_to_tx_control(priv
, agg
->rate_n_flags
, info
);
1437 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap
);
1443 * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1445 * Handles block-acknowledge notification from device, which reports success
1446 * of frames sent via aggregation.
1448 void iwl_rx_reply_compressed_ba(struct iwl_priv
*priv
,
1449 struct iwl_rx_mem_buffer
*rxb
)
1451 struct iwl_rx_packet
*pkt
= (struct iwl_rx_packet
*)rxb
->skb
->data
;
1452 struct iwl_compressed_ba_resp
*ba_resp
= &pkt
->u
.compressed_ba
;
1454 struct iwl_tx_queue
*txq
= NULL
;
1455 struct iwl_ht_agg
*agg
;
1456 DECLARE_MAC_BUF(mac
);
1458 /* "flow" corresponds to Tx queue */
1459 u16 scd_flow
= le16_to_cpu(ba_resp
->scd_flow
);
1461 /* "ssn" is start of block-ack Tx window, corresponds to index
1462 * (in Tx queue's circular buffer) of first TFD/frame in window */
1463 u16 ba_resp_scd_ssn
= le16_to_cpu(ba_resp
->scd_ssn
);
1465 if (scd_flow
>= priv
->hw_params
.max_txq_num
) {
1466 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues\n");
1470 txq
= &priv
->txq
[scd_flow
];
1471 agg
= &priv
->stations
[ba_resp
->sta_id
].tid
[ba_resp
->tid
].agg
;
1473 /* Find index just before block-ack window */
1474 index
= iwl_queue_dec_wrap(ba_resp_scd_ssn
& 0xff, txq
->q
.n_bd
);
1476 /* TODO: Need to get this copy more safely - now good for debug */
1478 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
1481 print_mac(mac
, (u8
*) &ba_resp
->sta_addr_lo32
),
1483 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1484 "%d, scd_ssn = %d\n",
1487 (unsigned long long)le64_to_cpu(ba_resp
->bitmap
),
1490 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
1492 (unsigned long long)agg
->bitmap
);
1494 /* Update driver's record of ACK vs. not for each frame in window */
1495 iwl_tx_status_reply_compressed_ba(priv
, agg
, ba_resp
);
1497 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1498 * block-ack window (we assume that they've been successfully
1499 * transmitted ... if not, it's too late anyway). */
1500 if (txq
->q
.read_ptr
!= (ba_resp_scd_ssn
& 0xff)) {
1501 /* calculate mac80211 ampdu sw queue to wake */
1503 scd_flow
- priv
->hw_params
.first_ampdu_q
+ priv
->hw
->queues
;
1504 int freed
= iwl_tx_queue_reclaim(priv
, scd_flow
, index
);
1505 priv
->stations
[ba_resp
->sta_id
].
1506 tid
[ba_resp
->tid
].tfds_in_queue
-= freed
;
1507 if (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
&&
1508 priv
->mac80211_registered
&&
1509 agg
->state
!= IWL_EMPTYING_HW_QUEUE_DELBA
)
1510 ieee80211_wake_queue(priv
->hw
, ampdu_q
);
1512 iwl_txq_check_empty(priv
, ba_resp
->sta_id
,
1513 ba_resp
->tid
, scd_flow
);
1516 EXPORT_SYMBOL(iwl_rx_reply_compressed_ba
);
1518 #ifdef CONFIG_IWLWIFI_DEBUG
1519 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
1521 const char *iwl_get_tx_fail_reason(u32 status
)
1523 switch (status
& TX_STATUS_MSK
) {
1524 case TX_STATUS_SUCCESS
:
1526 TX_STATUS_ENTRY(SHORT_LIMIT
);
1527 TX_STATUS_ENTRY(LONG_LIMIT
);
1528 TX_STATUS_ENTRY(FIFO_UNDERRUN
);
1529 TX_STATUS_ENTRY(MGMNT_ABORT
);
1530 TX_STATUS_ENTRY(NEXT_FRAG
);
1531 TX_STATUS_ENTRY(LIFE_EXPIRE
);
1532 TX_STATUS_ENTRY(DEST_PS
);
1533 TX_STATUS_ENTRY(ABORTED
);
1534 TX_STATUS_ENTRY(BT_RETRY
);
1535 TX_STATUS_ENTRY(STA_INVALID
);
1536 TX_STATUS_ENTRY(FRAG_DROPPED
);
1537 TX_STATUS_ENTRY(TID_DISABLE
);
1538 TX_STATUS_ENTRY(FRAME_FLUSHED
);
1539 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL
);
1540 TX_STATUS_ENTRY(TX_LOCKED
);
1541 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR
);
1546 EXPORT_SYMBOL(iwl_get_tx_fail_reason
);
1547 #endif /* CONFIG_IWLWIFI_DEBUG */