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iwlwifi: check the SCD conf from ALIVE response
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / pcie / trans.c
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63 #include <linux/pci.h>
64 #include <linux/pci-aspm.h>
65 #include <linux/interrupt.h>
66 #include <linux/debugfs.h>
67 #include <linux/sched.h>
68 #include <linux/bitops.h>
69 #include <linux/gfp.h>
70
71 #include "iwl-drv.h"
72 #include "iwl-trans.h"
73 #include "iwl-csr.h"
74 #include "iwl-prph.h"
75 #include "iwl-agn-hw.h"
76 #include "internal.h"
77 /* FIXME: need to abstract out TX command (once we know what it looks like) */
78 #include "dvm/commands.h"
79
80 #define SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie) \
81 (((1<<trans->cfg->base_params->num_of_queues) - 1) &\
82 (~(1<<(trans_pcie)->cmd_queue)))
83
84 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
85 {
86 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
87 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
88 struct device *dev = trans->dev;
89
90 memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
91
92 spin_lock_init(&rxq->lock);
93
94 if (WARN_ON(rxq->bd || rxq->rb_stts))
95 return -EINVAL;
96
97 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
98 rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
99 &rxq->bd_dma, GFP_KERNEL);
100 if (!rxq->bd)
101 goto err_bd;
102
103 /*Allocate the driver's pointer to receive buffer status */
104 rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
105 &rxq->rb_stts_dma, GFP_KERNEL);
106 if (!rxq->rb_stts)
107 goto err_rb_stts;
108
109 return 0;
110
111 err_rb_stts:
112 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
113 rxq->bd, rxq->bd_dma);
114 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
115 rxq->bd = NULL;
116 err_bd:
117 return -ENOMEM;
118 }
119
120 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
121 {
122 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
123 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
124 int i;
125
126 /* Fill the rx_used queue with _all_ of the Rx buffers */
127 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
128 /* In the reset function, these buffers may have been allocated
129 * to an SKB, so we need to unmap and free potential storage */
130 if (rxq->pool[i].page != NULL) {
131 dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
132 PAGE_SIZE << trans_pcie->rx_page_order,
133 DMA_FROM_DEVICE);
134 __free_pages(rxq->pool[i].page,
135 trans_pcie->rx_page_order);
136 rxq->pool[i].page = NULL;
137 }
138 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
139 }
140 }
141
142 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
143 struct iwl_rx_queue *rxq)
144 {
145 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
146 u32 rb_size;
147 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
148 u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
149
150 if (trans_pcie->rx_buf_size_8k)
151 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
152 else
153 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
154
155 /* Stop Rx DMA */
156 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
157
158 /* Reset driver's Rx queue write index */
159 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
160
161 /* Tell device where to find RBD circular buffer in DRAM */
162 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
163 (u32)(rxq->bd_dma >> 8));
164
165 /* Tell device where in DRAM to update its Rx status */
166 iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
167 rxq->rb_stts_dma >> 4);
168
169 /* Enable Rx DMA
170 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
171 * the credit mechanism in 5000 HW RX FIFO
172 * Direct rx interrupts to hosts
173 * Rx buffer size 4 or 8k
174 * RB timeout 0x10
175 * 256 RBDs
176 */
177 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
178 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
179 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
180 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
181 rb_size|
182 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
183 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
184
185 /* Set interrupt coalescing timer to default (2048 usecs) */
186 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
187 }
188
189 static int iwl_rx_init(struct iwl_trans *trans)
190 {
191 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
192 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
193
194 int i, err;
195 unsigned long flags;
196
197 if (!rxq->bd) {
198 err = iwl_trans_rx_alloc(trans);
199 if (err)
200 return err;
201 }
202
203 spin_lock_irqsave(&rxq->lock, flags);
204 INIT_LIST_HEAD(&rxq->rx_free);
205 INIT_LIST_HEAD(&rxq->rx_used);
206
207 iwl_trans_rxq_free_rx_bufs(trans);
208
209 for (i = 0; i < RX_QUEUE_SIZE; i++)
210 rxq->queue[i] = NULL;
211
212 /* Set us so that we have processed and used all buffers, but have
213 * not restocked the Rx queue with fresh buffers */
214 rxq->read = rxq->write = 0;
215 rxq->write_actual = 0;
216 rxq->free_count = 0;
217 spin_unlock_irqrestore(&rxq->lock, flags);
218
219 iwl_rx_replenish(trans);
220
221 iwl_trans_rx_hw_init(trans, rxq);
222
223 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
224 rxq->need_update = 1;
225 iwl_rx_queue_update_write_ptr(trans, rxq);
226 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
227
228 return 0;
229 }
230
231 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
232 {
233 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
234 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
235 unsigned long flags;
236
237 /*if rxq->bd is NULL, it means that nothing has been allocated,
238 * exit now */
239 if (!rxq->bd) {
240 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
241 return;
242 }
243
244 spin_lock_irqsave(&rxq->lock, flags);
245 iwl_trans_rxq_free_rx_bufs(trans);
246 spin_unlock_irqrestore(&rxq->lock, flags);
247
248 dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
249 rxq->bd, rxq->bd_dma);
250 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
251 rxq->bd = NULL;
252
253 if (rxq->rb_stts)
254 dma_free_coherent(trans->dev,
255 sizeof(struct iwl_rb_status),
256 rxq->rb_stts, rxq->rb_stts_dma);
257 else
258 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
259 memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
260 rxq->rb_stts = NULL;
261 }
262
263 static int iwl_trans_rx_stop(struct iwl_trans *trans)
264 {
265
266 /* stop Rx DMA */
267 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
268 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
269 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
270 }
271
272 static int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
273 struct iwl_dma_ptr *ptr, size_t size)
274 {
275 if (WARN_ON(ptr->addr))
276 return -EINVAL;
277
278 ptr->addr = dma_alloc_coherent(trans->dev, size,
279 &ptr->dma, GFP_KERNEL);
280 if (!ptr->addr)
281 return -ENOMEM;
282 ptr->size = size;
283 return 0;
284 }
285
286 static void iwlagn_free_dma_ptr(struct iwl_trans *trans,
287 struct iwl_dma_ptr *ptr)
288 {
289 if (unlikely(!ptr->addr))
290 return;
291
292 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
293 memset(ptr, 0, sizeof(*ptr));
294 }
295
296 static void iwl_trans_pcie_queue_stuck_timer(unsigned long data)
297 {
298 struct iwl_tx_queue *txq = (void *)data;
299 struct iwl_queue *q = &txq->q;
300 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
301 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
302 u32 scd_sram_addr = trans_pcie->scd_base_addr +
303 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
304 u8 buf[16];
305 int i;
306
307 spin_lock(&txq->lock);
308 /* check if triggered erroneously */
309 if (txq->q.read_ptr == txq->q.write_ptr) {
310 spin_unlock(&txq->lock);
311 return;
312 }
313 spin_unlock(&txq->lock);
314
315 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
316 jiffies_to_msecs(trans_pcie->wd_timeout));
317 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
318 txq->q.read_ptr, txq->q.write_ptr);
319
320 iwl_read_targ_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
321
322 iwl_print_hex_error(trans, buf, sizeof(buf));
323
324 for (i = 0; i < FH_TCSR_CHNL_NUM; i++)
325 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i,
326 iwl_read_direct32(trans, FH_TX_TRB_REG(i)));
327
328 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
329 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i));
330 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
331 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
332 u32 tbl_dw =
333 iwl_read_targ_mem(trans,
334 trans_pcie->scd_base_addr +
335 SCD_TRANS_TBL_OFFSET_QUEUE(i));
336
337 if (i & 0x1)
338 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
339 else
340 tbl_dw = tbl_dw & 0x0000FFFF;
341
342 IWL_ERR(trans,
343 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
344 i, active ? "" : "in", fifo, tbl_dw,
345 iwl_read_prph(trans,
346 SCD_QUEUE_RDPTR(i)) & (txq->q.n_bd - 1),
347 iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
348 }
349
350 for (i = q->read_ptr; i != q->write_ptr;
351 i = iwl_queue_inc_wrap(i, q->n_bd)) {
352 struct iwl_tx_cmd *tx_cmd =
353 (struct iwl_tx_cmd *)txq->entries[i].cmd->payload;
354 IWL_ERR(trans, "scratch %d = 0x%08x\n", i,
355 get_unaligned_le32(&tx_cmd->scratch));
356 }
357
358 iwl_op_mode_nic_error(trans->op_mode);
359 }
360
361 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
362 struct iwl_tx_queue *txq, int slots_num,
363 u32 txq_id)
364 {
365 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
366 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
367 int i;
368
369 if (WARN_ON(txq->entries || txq->tfds))
370 return -EINVAL;
371
372 setup_timer(&txq->stuck_timer, iwl_trans_pcie_queue_stuck_timer,
373 (unsigned long)txq);
374 txq->trans_pcie = trans_pcie;
375
376 txq->q.n_window = slots_num;
377
378 txq->entries = kcalloc(slots_num,
379 sizeof(struct iwl_pcie_tx_queue_entry),
380 GFP_KERNEL);
381
382 if (!txq->entries)
383 goto error;
384
385 if (txq_id == trans_pcie->cmd_queue)
386 for (i = 0; i < slots_num; i++) {
387 txq->entries[i].cmd =
388 kmalloc(sizeof(struct iwl_device_cmd),
389 GFP_KERNEL);
390 if (!txq->entries[i].cmd)
391 goto error;
392 }
393
394 /* Circular buffer of transmit frame descriptors (TFDs),
395 * shared with device */
396 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
397 &txq->q.dma_addr, GFP_KERNEL);
398 if (!txq->tfds) {
399 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
400 goto error;
401 }
402 txq->q.id = txq_id;
403
404 return 0;
405 error:
406 if (txq->entries && txq_id == trans_pcie->cmd_queue)
407 for (i = 0; i < slots_num; i++)
408 kfree(txq->entries[i].cmd);
409 kfree(txq->entries);
410 txq->entries = NULL;
411
412 return -ENOMEM;
413
414 }
415
416 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
417 int slots_num, u32 txq_id)
418 {
419 int ret;
420
421 txq->need_update = 0;
422
423 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
424 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
425 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
426
427 /* Initialize queue's high/low-water marks, and head/tail indexes */
428 ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
429 txq_id);
430 if (ret)
431 return ret;
432
433 spin_lock_init(&txq->lock);
434
435 /*
436 * Tell nic where to find circular buffer of Tx Frame Descriptors for
437 * given Tx queue, and enable the DMA channel used for that queue.
438 * Circular buffer (TFD queue in DRAM) physical base address */
439 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
440 txq->q.dma_addr >> 8);
441
442 return 0;
443 }
444
445 /*
446 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
447 */
448 void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
449 {
450 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
451 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
452 struct iwl_queue *q = &txq->q;
453 enum dma_data_direction dma_dir;
454
455 if (!q->n_bd)
456 return;
457
458 /* In the command queue, all the TBs are mapped as BIDI
459 * so unmap them as such.
460 */
461 if (txq_id == trans_pcie->cmd_queue)
462 dma_dir = DMA_BIDIRECTIONAL;
463 else
464 dma_dir = DMA_TO_DEVICE;
465
466 spin_lock_bh(&txq->lock);
467 while (q->write_ptr != q->read_ptr) {
468 iwl_txq_free_tfd(trans, txq, dma_dir);
469 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
470 }
471 spin_unlock_bh(&txq->lock);
472 }
473
474 /**
475 * iwl_tx_queue_free - Deallocate DMA queue.
476 * @txq: Transmit queue to deallocate.
477 *
478 * Empty queue by removing and destroying all BD's.
479 * Free all buffers.
480 * 0-fill, but do not free "txq" descriptor structure.
481 */
482 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
483 {
484 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
485 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
486 struct device *dev = trans->dev;
487 int i;
488
489 if (WARN_ON(!txq))
490 return;
491
492 iwl_tx_queue_unmap(trans, txq_id);
493
494 /* De-alloc array of command/tx buffers */
495 if (txq_id == trans_pcie->cmd_queue)
496 for (i = 0; i < txq->q.n_window; i++) {
497 kfree(txq->entries[i].cmd);
498 kfree(txq->entries[i].copy_cmd);
499 kfree(txq->entries[i].free_buf);
500 }
501
502 /* De-alloc circular buffer of TFDs */
503 if (txq->q.n_bd) {
504 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
505 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
506 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
507 }
508
509 kfree(txq->entries);
510 txq->entries = NULL;
511
512 del_timer_sync(&txq->stuck_timer);
513
514 /* 0-fill queue descriptor structure */
515 memset(txq, 0, sizeof(*txq));
516 }
517
518 /**
519 * iwl_trans_tx_free - Free TXQ Context
520 *
521 * Destroy all TX DMA queues and structures
522 */
523 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
524 {
525 int txq_id;
526 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
527
528 /* Tx queues */
529 if (trans_pcie->txq) {
530 for (txq_id = 0;
531 txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
532 iwl_tx_queue_free(trans, txq_id);
533 }
534
535 kfree(trans_pcie->txq);
536 trans_pcie->txq = NULL;
537
538 iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
539
540 iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
541 }
542
543 /**
544 * iwl_trans_tx_alloc - allocate TX context
545 * Allocate all Tx DMA structures and initialize them
546 *
547 * @param priv
548 * @return error code
549 */
550 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
551 {
552 int ret;
553 int txq_id, slots_num;
554 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
555
556 u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
557 sizeof(struct iwlagn_scd_bc_tbl);
558
559 /*It is not allowed to alloc twice, so warn when this happens.
560 * We cannot rely on the previous allocation, so free and fail */
561 if (WARN_ON(trans_pcie->txq)) {
562 ret = -EINVAL;
563 goto error;
564 }
565
566 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
567 scd_bc_tbls_size);
568 if (ret) {
569 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
570 goto error;
571 }
572
573 /* Alloc keep-warm buffer */
574 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
575 if (ret) {
576 IWL_ERR(trans, "Keep Warm allocation failed\n");
577 goto error;
578 }
579
580 trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
581 sizeof(struct iwl_tx_queue), GFP_KERNEL);
582 if (!trans_pcie->txq) {
583 IWL_ERR(trans, "Not enough memory for txq\n");
584 ret = ENOMEM;
585 goto error;
586 }
587
588 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
589 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
590 txq_id++) {
591 slots_num = (txq_id == trans_pcie->cmd_queue) ?
592 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
593 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
594 slots_num, txq_id);
595 if (ret) {
596 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
597 goto error;
598 }
599 }
600
601 return 0;
602
603 error:
604 iwl_trans_pcie_tx_free(trans);
605
606 return ret;
607 }
608 static int iwl_tx_init(struct iwl_trans *trans)
609 {
610 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
611 int ret;
612 int txq_id, slots_num;
613 unsigned long flags;
614 bool alloc = false;
615
616 if (!trans_pcie->txq) {
617 ret = iwl_trans_tx_alloc(trans);
618 if (ret)
619 goto error;
620 alloc = true;
621 }
622
623 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
624
625 /* Turn off all Tx DMA fifos */
626 iwl_write_prph(trans, SCD_TXFACT, 0);
627
628 /* Tell NIC where to find the "keep warm" buffer */
629 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
630 trans_pcie->kw.dma >> 4);
631
632 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
633
634 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
635 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
636 txq_id++) {
637 slots_num = (txq_id == trans_pcie->cmd_queue) ?
638 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
639 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
640 slots_num, txq_id);
641 if (ret) {
642 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
643 goto error;
644 }
645 }
646
647 return 0;
648 error:
649 /*Upon error, free only if we allocated something */
650 if (alloc)
651 iwl_trans_pcie_tx_free(trans);
652 return ret;
653 }
654
655 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
656 {
657 /*
658 * (for documentation purposes)
659 * to set power to V_AUX, do:
660
661 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
662 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
663 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
664 ~APMG_PS_CTRL_MSK_PWR_SRC);
665 */
666
667 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
668 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
669 ~APMG_PS_CTRL_MSK_PWR_SRC);
670 }
671
672 /* PCI registers */
673 #define PCI_CFG_RETRY_TIMEOUT 0x041
674 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
675 #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
676
677 static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
678 {
679 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
680 u16 pci_lnk_ctl;
681
682 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL,
683 &pci_lnk_ctl);
684 return pci_lnk_ctl;
685 }
686
687 static void iwl_apm_config(struct iwl_trans *trans)
688 {
689 /*
690 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
691 * Check if BIOS (or OS) enabled L1-ASPM on this device.
692 * If so (likely), disable L0S, so device moves directly L0->L1;
693 * costs negligible amount of power savings.
694 * If not (unlikely), enable L0S, so there is at least some
695 * power savings, even without L1.
696 */
697 u16 lctl = iwl_pciexp_link_ctrl(trans);
698
699 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
700 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
701 /* L1-ASPM enabled; disable(!) L0S */
702 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
703 dev_printk(KERN_INFO, trans->dev,
704 "L1 Enabled; Disabling L0S\n");
705 } else {
706 /* L1-ASPM disabled; enable(!) L0S */
707 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
708 dev_printk(KERN_INFO, trans->dev,
709 "L1 Disabled; Enabling L0S\n");
710 }
711 trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
712 }
713
714 /*
715 * Start up NIC's basic functionality after it has been reset
716 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
717 * NOTE: This does not load uCode nor start the embedded processor
718 */
719 static int iwl_apm_init(struct iwl_trans *trans)
720 {
721 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
722 int ret = 0;
723 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
724
725 /*
726 * Use "set_bit" below rather than "write", to preserve any hardware
727 * bits already set by default after reset.
728 */
729
730 /* Disable L0S exit timer (platform NMI Work/Around) */
731 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
732 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
733
734 /*
735 * Disable L0s without affecting L1;
736 * don't wait for ICH L0s (ICH bug W/A)
737 */
738 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
739 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
740
741 /* Set FH wait threshold to maximum (HW error during stress W/A) */
742 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
743
744 /*
745 * Enable HAP INTA (interrupt from management bus) to
746 * wake device's PCI Express link L1a -> L0s
747 */
748 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
749 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
750
751 iwl_apm_config(trans);
752
753 /* Configure analog phase-lock-loop before activating to D0A */
754 if (trans->cfg->base_params->pll_cfg_val)
755 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
756 trans->cfg->base_params->pll_cfg_val);
757
758 /*
759 * Set "initialization complete" bit to move adapter from
760 * D0U* --> D0A* (powered-up active) state.
761 */
762 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
763
764 /*
765 * Wait for clock stabilization; once stabilized, access to
766 * device-internal resources is supported, e.g. iwl_write_prph()
767 * and accesses to uCode SRAM.
768 */
769 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
770 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
771 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
772 if (ret < 0) {
773 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
774 goto out;
775 }
776
777 /*
778 * Enable DMA clock and wait for it to stabilize.
779 *
780 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
781 * do not disable clocks. This preserves any hardware bits already
782 * set by default in "CLK_CTRL_REG" after reset.
783 */
784 iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
785 udelay(20);
786
787 /* Disable L1-Active */
788 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
789 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
790
791 set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
792
793 out:
794 return ret;
795 }
796
797 static int iwl_apm_stop_master(struct iwl_trans *trans)
798 {
799 int ret = 0;
800
801 /* stop device's busmaster DMA activity */
802 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
803
804 ret = iwl_poll_bit(trans, CSR_RESET,
805 CSR_RESET_REG_FLAG_MASTER_DISABLED,
806 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
807 if (ret)
808 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
809
810 IWL_DEBUG_INFO(trans, "stop master\n");
811
812 return ret;
813 }
814
815 static void iwl_apm_stop(struct iwl_trans *trans)
816 {
817 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
818 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
819
820 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
821
822 /* Stop device's DMA activity */
823 iwl_apm_stop_master(trans);
824
825 /* Reset the entire device */
826 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
827
828 udelay(10);
829
830 /*
831 * Clear "initialization complete" bit to move adapter from
832 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
833 */
834 iwl_clear_bit(trans, CSR_GP_CNTRL,
835 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
836 }
837
838 static int iwl_nic_init(struct iwl_trans *trans)
839 {
840 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
841 unsigned long flags;
842
843 /* nic_init */
844 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
845 iwl_apm_init(trans);
846
847 /* Set interrupt coalescing calibration timer to default (512 usecs) */
848 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
849
850 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
851
852 iwl_set_pwr_vmain(trans);
853
854 iwl_op_mode_nic_config(trans->op_mode);
855
856 /* Allocate the RX queue, or reset if it is already allocated */
857 iwl_rx_init(trans);
858
859 /* Allocate or reset and init all Tx and Command queues */
860 if (iwl_tx_init(trans))
861 return -ENOMEM;
862
863 if (trans->cfg->base_params->shadow_reg_enable) {
864 /* enable shadow regs in HW */
865 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
866 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
867 }
868
869 return 0;
870 }
871
872 #define HW_READY_TIMEOUT (50)
873
874 /* Note: returns poll_bit return value, which is >= 0 if success */
875 static int iwl_set_hw_ready(struct iwl_trans *trans)
876 {
877 int ret;
878
879 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
880 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
881
882 /* See if we got it */
883 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
884 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
885 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
886 HW_READY_TIMEOUT);
887
888 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
889 return ret;
890 }
891
892 /* Note: returns standard 0/-ERROR code */
893 static int iwl_prepare_card_hw(struct iwl_trans *trans)
894 {
895 int ret;
896 int t = 0;
897
898 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
899
900 ret = iwl_set_hw_ready(trans);
901 /* If the card is ready, exit 0 */
902 if (ret >= 0)
903 return 0;
904
905 /* If HW is not ready, prepare the conditions to check again */
906 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
907 CSR_HW_IF_CONFIG_REG_PREPARE);
908
909 do {
910 ret = iwl_set_hw_ready(trans);
911 if (ret >= 0)
912 return 0;
913
914 usleep_range(200, 1000);
915 t += 200;
916 } while (t < 150000);
917
918 return ret;
919 }
920
921 /*
922 * ucode
923 */
924 static int iwl_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
925 dma_addr_t phy_addr, u32 byte_cnt)
926 {
927 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
928 int ret;
929
930 trans_pcie->ucode_write_complete = false;
931
932 iwl_write_direct32(trans,
933 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
934 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
935
936 iwl_write_direct32(trans,
937 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
938 dst_addr);
939
940 iwl_write_direct32(trans,
941 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
942 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
943
944 iwl_write_direct32(trans,
945 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
946 (iwl_get_dma_hi_addr(phy_addr)
947 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
948
949 iwl_write_direct32(trans,
950 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
951 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
952 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
953 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
954
955 iwl_write_direct32(trans,
956 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
957 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
958 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
959 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
960
961 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
962 trans_pcie->ucode_write_complete, 5 * HZ);
963 if (!ret) {
964 IWL_ERR(trans, "Failed to load firmware chunk!\n");
965 return -ETIMEDOUT;
966 }
967
968 return 0;
969 }
970
971 static int iwl_load_section(struct iwl_trans *trans, u8 section_num,
972 const struct fw_desc *section)
973 {
974 u8 *v_addr;
975 dma_addr_t p_addr;
976 u32 offset;
977 int ret = 0;
978
979 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
980 section_num);
981
982 v_addr = dma_alloc_coherent(trans->dev, PAGE_SIZE, &p_addr, GFP_KERNEL);
983 if (!v_addr)
984 return -ENOMEM;
985
986 for (offset = 0; offset < section->len; offset += PAGE_SIZE) {
987 u32 copy_size;
988
989 copy_size = min_t(u32, PAGE_SIZE, section->len - offset);
990
991 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
992 ret = iwl_load_firmware_chunk(trans, section->offset + offset,
993 p_addr, copy_size);
994 if (ret) {
995 IWL_ERR(trans,
996 "Could not load the [%d] uCode section\n",
997 section_num);
998 break;
999 }
1000 }
1001
1002 dma_free_coherent(trans->dev, PAGE_SIZE, v_addr, p_addr);
1003 return ret;
1004 }
1005
1006 static int iwl_load_given_ucode(struct iwl_trans *trans,
1007 const struct fw_img *image)
1008 {
1009 int i, ret = 0;
1010
1011 for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
1012 if (!image->sec[i].data)
1013 break;
1014
1015 ret = iwl_load_section(trans, i, &image->sec[i]);
1016 if (ret)
1017 return ret;
1018 }
1019
1020 /* Remove all resets to allow NIC to operate */
1021 iwl_write32(trans, CSR_RESET, 0);
1022
1023 return 0;
1024 }
1025
1026 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1027 const struct fw_img *fw)
1028 {
1029 int ret;
1030 bool hw_rfkill;
1031
1032 /* This may fail if AMT took ownership of the device */
1033 if (iwl_prepare_card_hw(trans)) {
1034 IWL_WARN(trans, "Exit HW not ready\n");
1035 return -EIO;
1036 }
1037
1038 iwl_enable_rfkill_int(trans);
1039
1040 /* If platform's RF_KILL switch is NOT set to KILL */
1041 hw_rfkill = iwl_is_rfkill_set(trans);
1042 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1043 if (hw_rfkill)
1044 return -ERFKILL;
1045
1046 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1047
1048 ret = iwl_nic_init(trans);
1049 if (ret) {
1050 IWL_ERR(trans, "Unable to init nic\n");
1051 return ret;
1052 }
1053
1054 /* make sure rfkill handshake bits are cleared */
1055 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1056 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1057 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1058
1059 /* clear (again), then enable host interrupts */
1060 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1061 iwl_enable_interrupts(trans);
1062
1063 /* really make sure rfkill handshake bits are cleared */
1064 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1065 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1066
1067 /* Load the given image to the HW */
1068 return iwl_load_given_ucode(trans, fw);
1069 }
1070
1071 /*
1072 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1073 */
1074 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
1075 {
1076 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1077 IWL_TRANS_GET_PCIE_TRANS(trans);
1078
1079 iwl_write_prph(trans, SCD_TXFACT, mask);
1080 }
1081
1082 static void iwl_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
1083 {
1084 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1085 u32 a;
1086 int chan;
1087 u32 reg_val;
1088
1089 /* make sure all queue are not stopped/used */
1090 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
1091 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
1092
1093 trans_pcie->scd_base_addr =
1094 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
1095
1096 WARN_ON(scd_base_addr != 0 &&
1097 scd_base_addr != trans_pcie->scd_base_addr);
1098
1099 a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
1100 /* reset conext data memory */
1101 for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
1102 a += 4)
1103 iwl_write_targ_mem(trans, a, 0);
1104 /* reset tx status memory */
1105 for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
1106 a += 4)
1107 iwl_write_targ_mem(trans, a, 0);
1108 for (; a < trans_pcie->scd_base_addr +
1109 SCD_TRANS_TBL_OFFSET_QUEUE(
1110 trans->cfg->base_params->num_of_queues);
1111 a += 4)
1112 iwl_write_targ_mem(trans, a, 0);
1113
1114 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
1115 trans_pcie->scd_bc_tbls.dma >> 10);
1116
1117 /* The chain extension of the SCD doesn't work well. This feature is
1118 * enabled by default by the HW, so we need to disable it manually.
1119 */
1120 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
1121
1122 iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
1123 trans_pcie->cmd_fifo);
1124
1125 /* Activate all Tx DMA/FIFO channels */
1126 iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
1127
1128 /* Enable DMA channel */
1129 for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
1130 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1131 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1132 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1133
1134 /* Update FH chicken bits */
1135 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
1136 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1137 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1138
1139 /* Enable L1-Active */
1140 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1141 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1142 }
1143
1144 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1145 {
1146 iwl_reset_ict(trans);
1147 iwl_tx_start(trans, scd_addr);
1148 }
1149
1150 /**
1151 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1152 */
1153 static int iwl_trans_tx_stop(struct iwl_trans *trans)
1154 {
1155 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1156 int ch, txq_id, ret;
1157 unsigned long flags;
1158
1159 /* Turn off all Tx DMA fifos */
1160 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1161
1162 iwl_trans_txq_set_sched(trans, 0);
1163
1164 /* Stop each Tx DMA channel, and wait for it to be idle */
1165 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
1166 iwl_write_direct32(trans,
1167 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
1168 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
1169 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000);
1170 if (ret < 0)
1171 IWL_ERR(trans,
1172 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
1173 ch,
1174 iwl_read_direct32(trans,
1175 FH_TSSR_TX_STATUS_REG));
1176 }
1177 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1178
1179 if (!trans_pcie->txq) {
1180 IWL_WARN(trans,
1181 "Stopping tx queues that aren't allocated...\n");
1182 return 0;
1183 }
1184
1185 /* Unmap DMA from host system and free skb's */
1186 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
1187 txq_id++)
1188 iwl_tx_queue_unmap(trans, txq_id);
1189
1190 return 0;
1191 }
1192
1193 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1194 {
1195 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1196 unsigned long flags;
1197
1198 /* tell the device to stop sending interrupts */
1199 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1200 iwl_disable_interrupts(trans);
1201 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1202
1203 /* device going down, Stop using ICT table */
1204 iwl_disable_ict(trans);
1205
1206 /*
1207 * If a HW restart happens during firmware loading,
1208 * then the firmware loading might call this function
1209 * and later it might be called again due to the
1210 * restart. So don't process again if the device is
1211 * already dead.
1212 */
1213 if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
1214 iwl_trans_tx_stop(trans);
1215 iwl_trans_rx_stop(trans);
1216
1217 /* Power-down device's busmaster DMA clocks */
1218 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1219 APMG_CLK_VAL_DMA_CLK_RQT);
1220 udelay(5);
1221 }
1222
1223 /* Make sure (redundant) we've released our request to stay awake */
1224 iwl_clear_bit(trans, CSR_GP_CNTRL,
1225 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1226
1227 /* Stop the device, and put it in low power state */
1228 iwl_apm_stop(trans);
1229
1230 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1231 * Clean again the interrupt here
1232 */
1233 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1234 iwl_disable_interrupts(trans);
1235 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1236
1237 iwl_enable_rfkill_int(trans);
1238
1239 /* wait to make sure we flush pending tasklet*/
1240 synchronize_irq(trans_pcie->irq);
1241 tasklet_kill(&trans_pcie->irq_tasklet);
1242
1243 cancel_work_sync(&trans_pcie->rx_replenish);
1244
1245 /* stop and reset the on-board processor */
1246 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1247
1248 /* clear all status bits */
1249 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
1250 clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
1251 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
1252 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1253 clear_bit(STATUS_RFKILL, &trans_pcie->status);
1254 }
1255
1256 static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
1257 {
1258 /* let the ucode operate on its own */
1259 iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
1260 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
1261
1262 iwl_disable_interrupts(trans);
1263 iwl_clear_bit(trans, CSR_GP_CNTRL,
1264 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1265 }
1266
1267 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1268 struct iwl_device_cmd *dev_cmd, int txq_id)
1269 {
1270 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1271 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1272 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1273 struct iwl_cmd_meta *out_meta;
1274 struct iwl_tx_queue *txq;
1275 struct iwl_queue *q;
1276 dma_addr_t phys_addr = 0;
1277 dma_addr_t txcmd_phys;
1278 dma_addr_t scratch_phys;
1279 u16 len, firstlen, secondlen;
1280 u8 wait_write_ptr = 0;
1281 __le16 fc = hdr->frame_control;
1282 u8 hdr_len = ieee80211_hdrlen(fc);
1283 u16 __maybe_unused wifi_seq;
1284
1285 txq = &trans_pcie->txq[txq_id];
1286 q = &txq->q;
1287
1288 if (unlikely(!test_bit(txq_id, trans_pcie->queue_used))) {
1289 WARN_ON_ONCE(1);
1290 return -EINVAL;
1291 }
1292
1293 spin_lock(&txq->lock);
1294
1295 /* In AGG mode, the index in the ring must correspond to the WiFi
1296 * sequence number. This is a HW requirements to help the SCD to parse
1297 * the BA.
1298 * Check here that the packets are in the right place on the ring.
1299 */
1300 #ifdef CONFIG_IWLWIFI_DEBUG
1301 wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1302 WARN_ONCE((iwl_read_prph(trans, SCD_AGGR_SEL) & BIT(txq_id)) &&
1303 ((wifi_seq & 0xff) != q->write_ptr),
1304 "Q: %d WiFi Seq %d tfdNum %d",
1305 txq_id, wifi_seq, q->write_ptr);
1306 #endif
1307
1308 /* Set up driver data for this TFD */
1309 txq->entries[q->write_ptr].skb = skb;
1310 txq->entries[q->write_ptr].cmd = dev_cmd;
1311
1312 dev_cmd->hdr.cmd = REPLY_TX;
1313 dev_cmd->hdr.sequence =
1314 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1315 INDEX_TO_SEQ(q->write_ptr)));
1316
1317 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1318 out_meta = &txq->entries[q->write_ptr].meta;
1319
1320 /*
1321 * Use the first empty entry in this queue's command buffer array
1322 * to contain the Tx command and MAC header concatenated together
1323 * (payload data will be in another buffer).
1324 * Size of this varies, due to varying MAC header length.
1325 * If end is not dword aligned, we'll have 2 extra bytes at the end
1326 * of the MAC header (device reads on dword boundaries).
1327 * We'll tell device about this padding later.
1328 */
1329 len = sizeof(struct iwl_tx_cmd) +
1330 sizeof(struct iwl_cmd_header) + hdr_len;
1331 firstlen = (len + 3) & ~3;
1332
1333 /* Tell NIC about any 2-byte padding after MAC header */
1334 if (firstlen != len)
1335 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1336
1337 /* Physical address of this Tx command's header (not MAC header!),
1338 * within command buffer array. */
1339 txcmd_phys = dma_map_single(trans->dev,
1340 &dev_cmd->hdr, firstlen,
1341 DMA_BIDIRECTIONAL);
1342 if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1343 goto out_err;
1344 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1345 dma_unmap_len_set(out_meta, len, firstlen);
1346
1347 if (!ieee80211_has_morefrags(fc)) {
1348 txq->need_update = 1;
1349 } else {
1350 wait_write_ptr = 1;
1351 txq->need_update = 0;
1352 }
1353
1354 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1355 * if any (802.11 null frames have no payload). */
1356 secondlen = skb->len - hdr_len;
1357 if (secondlen > 0) {
1358 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1359 secondlen, DMA_TO_DEVICE);
1360 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1361 dma_unmap_single(trans->dev,
1362 dma_unmap_addr(out_meta, mapping),
1363 dma_unmap_len(out_meta, len),
1364 DMA_BIDIRECTIONAL);
1365 goto out_err;
1366 }
1367 }
1368
1369 /* Attach buffers to TFD */
1370 iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1371 if (secondlen > 0)
1372 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1373 secondlen, 0);
1374
1375 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1376 offsetof(struct iwl_tx_cmd, scratch);
1377
1378 /* take back ownership of DMA buffer to enable update */
1379 dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1380 DMA_BIDIRECTIONAL);
1381 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1382 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1383
1384 IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1385 le16_to_cpu(dev_cmd->hdr.sequence));
1386 IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1387
1388 /* Set up entry for this TFD in Tx byte-count array */
1389 iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1390
1391 dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1392 DMA_BIDIRECTIONAL);
1393
1394 trace_iwlwifi_dev_tx(trans->dev, skb,
1395 &txq->tfds[txq->q.write_ptr],
1396 sizeof(struct iwl_tfd),
1397 &dev_cmd->hdr, firstlen,
1398 skb->data + hdr_len, secondlen);
1399 trace_iwlwifi_dev_tx_data(trans->dev, skb,
1400 skb->data + hdr_len, secondlen);
1401
1402 /* start timer if queue currently empty */
1403 if (txq->need_update && q->read_ptr == q->write_ptr &&
1404 trans_pcie->wd_timeout)
1405 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1406
1407 /* Tell device the write index *just past* this latest filled TFD */
1408 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1409 iwl_txq_update_write_ptr(trans, txq);
1410
1411 /*
1412 * At this point the frame is "transmitted" successfully
1413 * and we will get a TX status notification eventually,
1414 * regardless of the value of ret. "ret" only indicates
1415 * whether or not we should update the write pointer.
1416 */
1417 if (iwl_queue_space(q) < q->high_mark) {
1418 if (wait_write_ptr) {
1419 txq->need_update = 1;
1420 iwl_txq_update_write_ptr(trans, txq);
1421 } else {
1422 iwl_stop_queue(trans, txq);
1423 }
1424 }
1425 spin_unlock(&txq->lock);
1426 return 0;
1427 out_err:
1428 spin_unlock(&txq->lock);
1429 return -1;
1430 }
1431
1432 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1433 {
1434 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1435 int err;
1436 bool hw_rfkill;
1437
1438 trans_pcie->inta_mask = CSR_INI_SET_MASK;
1439
1440 if (!trans_pcie->irq_requested) {
1441 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1442 iwl_irq_tasklet, (unsigned long)trans);
1443
1444 iwl_alloc_isr_ict(trans);
1445
1446 err = request_irq(trans_pcie->irq, iwl_isr_ict, IRQF_SHARED,
1447 DRV_NAME, trans);
1448 if (err) {
1449 IWL_ERR(trans, "Error allocating IRQ %d\n",
1450 trans_pcie->irq);
1451 goto error;
1452 }
1453
1454 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1455 trans_pcie->irq_requested = true;
1456 }
1457
1458 err = iwl_prepare_card_hw(trans);
1459 if (err) {
1460 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1461 goto err_free_irq;
1462 }
1463
1464 iwl_apm_init(trans);
1465
1466 /* From now on, the op_mode will be kept updated about RF kill state */
1467 iwl_enable_rfkill_int(trans);
1468
1469 hw_rfkill = iwl_is_rfkill_set(trans);
1470 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1471
1472 return err;
1473
1474 err_free_irq:
1475 trans_pcie->irq_requested = false;
1476 free_irq(trans_pcie->irq, trans);
1477 error:
1478 iwl_free_isr_ict(trans);
1479 tasklet_kill(&trans_pcie->irq_tasklet);
1480 return err;
1481 }
1482
1483 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
1484 bool op_mode_leaving)
1485 {
1486 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1487 bool hw_rfkill;
1488 unsigned long flags;
1489
1490 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1491 iwl_disable_interrupts(trans);
1492 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1493
1494 iwl_apm_stop(trans);
1495
1496 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1497 iwl_disable_interrupts(trans);
1498 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1499
1500 if (!op_mode_leaving) {
1501 /*
1502 * Even if we stop the HW, we still want the RF kill
1503 * interrupt
1504 */
1505 iwl_enable_rfkill_int(trans);
1506
1507 /*
1508 * Check again since the RF kill state may have changed while
1509 * all the interrupts were disabled, in this case we couldn't
1510 * receive the RF kill interrupt and update the state in the
1511 * op_mode.
1512 */
1513 hw_rfkill = iwl_is_rfkill_set(trans);
1514 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1515 }
1516 }
1517
1518 static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
1519 struct sk_buff_head *skbs)
1520 {
1521 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1522 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1523 /* n_bd is usually 256 => n_bd - 1 = 0xff */
1524 int tfd_num = ssn & (txq->q.n_bd - 1);
1525
1526 spin_lock(&txq->lock);
1527
1528 if (txq->q.read_ptr != tfd_num) {
1529 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
1530 txq_id, txq->q.read_ptr, tfd_num, ssn);
1531 iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1532 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1533 iwl_wake_queue(trans, txq);
1534 }
1535
1536 spin_unlock(&txq->lock);
1537 }
1538
1539 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1540 {
1541 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1542 }
1543
1544 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1545 {
1546 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1547 }
1548
1549 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1550 {
1551 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1552 }
1553
1554 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1555 const struct iwl_trans_config *trans_cfg)
1556 {
1557 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1558
1559 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1560 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1561 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1562 trans_pcie->n_no_reclaim_cmds = 0;
1563 else
1564 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1565 if (trans_pcie->n_no_reclaim_cmds)
1566 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1567 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1568
1569 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1570 if (trans_pcie->rx_buf_size_8k)
1571 trans_pcie->rx_page_order = get_order(8 * 1024);
1572 else
1573 trans_pcie->rx_page_order = get_order(4 * 1024);
1574
1575 trans_pcie->wd_timeout =
1576 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
1577
1578 trans_pcie->command_names = trans_cfg->command_names;
1579 }
1580
1581 void iwl_trans_pcie_free(struct iwl_trans *trans)
1582 {
1583 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1584
1585 iwl_trans_pcie_tx_free(trans);
1586 iwl_trans_pcie_rx_free(trans);
1587
1588 if (trans_pcie->irq_requested == true) {
1589 free_irq(trans_pcie->irq, trans);
1590 iwl_free_isr_ict(trans);
1591 }
1592
1593 pci_disable_msi(trans_pcie->pci_dev);
1594 iounmap(trans_pcie->hw_base);
1595 pci_release_regions(trans_pcie->pci_dev);
1596 pci_disable_device(trans_pcie->pci_dev);
1597 kmem_cache_destroy(trans->dev_cmd_pool);
1598
1599 kfree(trans);
1600 }
1601
1602 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1603 {
1604 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1605
1606 if (state)
1607 set_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1608 else
1609 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1610 }
1611
1612 #ifdef CONFIG_PM_SLEEP
1613 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1614 {
1615 return 0;
1616 }
1617
1618 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1619 {
1620 bool hw_rfkill;
1621
1622 iwl_enable_rfkill_int(trans);
1623
1624 hw_rfkill = iwl_is_rfkill_set(trans);
1625 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1626
1627 if (!hw_rfkill)
1628 iwl_enable_interrupts(trans);
1629
1630 return 0;
1631 }
1632 #endif /* CONFIG_PM_SLEEP */
1633
1634 #define IWL_FLUSH_WAIT_MS 2000
1635
1636 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1637 {
1638 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1639 struct iwl_tx_queue *txq;
1640 struct iwl_queue *q;
1641 int cnt;
1642 unsigned long now = jiffies;
1643 int ret = 0;
1644
1645 /* waiting for all the tx frames complete might take a while */
1646 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1647 if (cnt == trans_pcie->cmd_queue)
1648 continue;
1649 txq = &trans_pcie->txq[cnt];
1650 q = &txq->q;
1651 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1652 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1653 msleep(1);
1654
1655 if (q->read_ptr != q->write_ptr) {
1656 IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1657 ret = -ETIMEDOUT;
1658 break;
1659 }
1660 }
1661 return ret;
1662 }
1663
1664 static const char *get_fh_string(int cmd)
1665 {
1666 #define IWL_CMD(x) case x: return #x
1667 switch (cmd) {
1668 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1669 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1670 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1671 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1672 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1673 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1674 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1675 IWL_CMD(FH_TSSR_TX_STATUS_REG);
1676 IWL_CMD(FH_TSSR_TX_ERROR_REG);
1677 default:
1678 return "UNKNOWN";
1679 }
1680 #undef IWL_CMD
1681 }
1682
1683 int iwl_dump_fh(struct iwl_trans *trans, char **buf)
1684 {
1685 int i;
1686 static const u32 fh_tbl[] = {
1687 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1688 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1689 FH_RSCSR_CHNL0_WPTR,
1690 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1691 FH_MEM_RSSR_SHARED_CTRL_REG,
1692 FH_MEM_RSSR_RX_STATUS_REG,
1693 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1694 FH_TSSR_TX_STATUS_REG,
1695 FH_TSSR_TX_ERROR_REG
1696 };
1697
1698 #ifdef CONFIG_IWLWIFI_DEBUGFS
1699 if (buf) {
1700 int pos = 0;
1701 size_t bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1702
1703 *buf = kmalloc(bufsz, GFP_KERNEL);
1704 if (!*buf)
1705 return -ENOMEM;
1706
1707 pos += scnprintf(*buf + pos, bufsz - pos,
1708 "FH register values:\n");
1709
1710 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
1711 pos += scnprintf(*buf + pos, bufsz - pos,
1712 " %34s: 0X%08x\n",
1713 get_fh_string(fh_tbl[i]),
1714 iwl_read_direct32(trans, fh_tbl[i]));
1715
1716 return pos;
1717 }
1718 #endif
1719
1720 IWL_ERR(trans, "FH register values:\n");
1721 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
1722 IWL_ERR(trans, " %34s: 0X%08x\n",
1723 get_fh_string(fh_tbl[i]),
1724 iwl_read_direct32(trans, fh_tbl[i]));
1725
1726 return 0;
1727 }
1728
1729 static const char *get_csr_string(int cmd)
1730 {
1731 #define IWL_CMD(x) case x: return #x
1732 switch (cmd) {
1733 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1734 IWL_CMD(CSR_INT_COALESCING);
1735 IWL_CMD(CSR_INT);
1736 IWL_CMD(CSR_INT_MASK);
1737 IWL_CMD(CSR_FH_INT_STATUS);
1738 IWL_CMD(CSR_GPIO_IN);
1739 IWL_CMD(CSR_RESET);
1740 IWL_CMD(CSR_GP_CNTRL);
1741 IWL_CMD(CSR_HW_REV);
1742 IWL_CMD(CSR_EEPROM_REG);
1743 IWL_CMD(CSR_EEPROM_GP);
1744 IWL_CMD(CSR_OTP_GP_REG);
1745 IWL_CMD(CSR_GIO_REG);
1746 IWL_CMD(CSR_GP_UCODE_REG);
1747 IWL_CMD(CSR_GP_DRIVER_REG);
1748 IWL_CMD(CSR_UCODE_DRV_GP1);
1749 IWL_CMD(CSR_UCODE_DRV_GP2);
1750 IWL_CMD(CSR_LED_REG);
1751 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1752 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1753 IWL_CMD(CSR_ANA_PLL_CFG);
1754 IWL_CMD(CSR_HW_REV_WA_REG);
1755 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1756 default:
1757 return "UNKNOWN";
1758 }
1759 #undef IWL_CMD
1760 }
1761
1762 void iwl_dump_csr(struct iwl_trans *trans)
1763 {
1764 int i;
1765 static const u32 csr_tbl[] = {
1766 CSR_HW_IF_CONFIG_REG,
1767 CSR_INT_COALESCING,
1768 CSR_INT,
1769 CSR_INT_MASK,
1770 CSR_FH_INT_STATUS,
1771 CSR_GPIO_IN,
1772 CSR_RESET,
1773 CSR_GP_CNTRL,
1774 CSR_HW_REV,
1775 CSR_EEPROM_REG,
1776 CSR_EEPROM_GP,
1777 CSR_OTP_GP_REG,
1778 CSR_GIO_REG,
1779 CSR_GP_UCODE_REG,
1780 CSR_GP_DRIVER_REG,
1781 CSR_UCODE_DRV_GP1,
1782 CSR_UCODE_DRV_GP2,
1783 CSR_LED_REG,
1784 CSR_DRAM_INT_TBL_REG,
1785 CSR_GIO_CHICKEN_BITS,
1786 CSR_ANA_PLL_CFG,
1787 CSR_HW_REV_WA_REG,
1788 CSR_DBG_HPET_MEM_REG
1789 };
1790 IWL_ERR(trans, "CSR values:\n");
1791 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1792 "CSR_INT_PERIODIC_REG)\n");
1793 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1794 IWL_ERR(trans, " %25s: 0X%08x\n",
1795 get_csr_string(csr_tbl[i]),
1796 iwl_read32(trans, csr_tbl[i]));
1797 }
1798 }
1799
1800 #ifdef CONFIG_IWLWIFI_DEBUGFS
1801 /* create and remove of files */
1802 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1803 if (!debugfs_create_file(#name, mode, parent, trans, \
1804 &iwl_dbgfs_##name##_ops)) \
1805 goto err; \
1806 } while (0)
1807
1808 /* file operation */
1809 #define DEBUGFS_READ_FUNC(name) \
1810 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1811 char __user *user_buf, \
1812 size_t count, loff_t *ppos);
1813
1814 #define DEBUGFS_WRITE_FUNC(name) \
1815 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1816 const char __user *user_buf, \
1817 size_t count, loff_t *ppos);
1818
1819
1820 #define DEBUGFS_READ_FILE_OPS(name) \
1821 DEBUGFS_READ_FUNC(name); \
1822 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1823 .read = iwl_dbgfs_##name##_read, \
1824 .open = simple_open, \
1825 .llseek = generic_file_llseek, \
1826 };
1827
1828 #define DEBUGFS_WRITE_FILE_OPS(name) \
1829 DEBUGFS_WRITE_FUNC(name); \
1830 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1831 .write = iwl_dbgfs_##name##_write, \
1832 .open = simple_open, \
1833 .llseek = generic_file_llseek, \
1834 };
1835
1836 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1837 DEBUGFS_READ_FUNC(name); \
1838 DEBUGFS_WRITE_FUNC(name); \
1839 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1840 .write = iwl_dbgfs_##name##_write, \
1841 .read = iwl_dbgfs_##name##_read, \
1842 .open = simple_open, \
1843 .llseek = generic_file_llseek, \
1844 };
1845
1846 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1847 char __user *user_buf,
1848 size_t count, loff_t *ppos)
1849 {
1850 struct iwl_trans *trans = file->private_data;
1851 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1852 struct iwl_tx_queue *txq;
1853 struct iwl_queue *q;
1854 char *buf;
1855 int pos = 0;
1856 int cnt;
1857 int ret;
1858 size_t bufsz;
1859
1860 bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1861
1862 if (!trans_pcie->txq)
1863 return -EAGAIN;
1864
1865 buf = kzalloc(bufsz, GFP_KERNEL);
1866 if (!buf)
1867 return -ENOMEM;
1868
1869 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1870 txq = &trans_pcie->txq[cnt];
1871 q = &txq->q;
1872 pos += scnprintf(buf + pos, bufsz - pos,
1873 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1874 cnt, q->read_ptr, q->write_ptr,
1875 !!test_bit(cnt, trans_pcie->queue_used),
1876 !!test_bit(cnt, trans_pcie->queue_stopped));
1877 }
1878 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1879 kfree(buf);
1880 return ret;
1881 }
1882
1883 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1884 char __user *user_buf,
1885 size_t count, loff_t *ppos)
1886 {
1887 struct iwl_trans *trans = file->private_data;
1888 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1889 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1890 char buf[256];
1891 int pos = 0;
1892 const size_t bufsz = sizeof(buf);
1893
1894 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1895 rxq->read);
1896 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1897 rxq->write);
1898 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1899 rxq->free_count);
1900 if (rxq->rb_stts) {
1901 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1902 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1903 } else {
1904 pos += scnprintf(buf + pos, bufsz - pos,
1905 "closed_rb_num: Not Allocated\n");
1906 }
1907 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1908 }
1909
1910 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1911 char __user *user_buf,
1912 size_t count, loff_t *ppos)
1913 {
1914 struct iwl_trans *trans = file->private_data;
1915 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1916 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1917
1918 int pos = 0;
1919 char *buf;
1920 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1921 ssize_t ret;
1922
1923 buf = kzalloc(bufsz, GFP_KERNEL);
1924 if (!buf)
1925 return -ENOMEM;
1926
1927 pos += scnprintf(buf + pos, bufsz - pos,
1928 "Interrupt Statistics Report:\n");
1929
1930 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1931 isr_stats->hw);
1932 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1933 isr_stats->sw);
1934 if (isr_stats->sw || isr_stats->hw) {
1935 pos += scnprintf(buf + pos, bufsz - pos,
1936 "\tLast Restarting Code: 0x%X\n",
1937 isr_stats->err_code);
1938 }
1939 #ifdef CONFIG_IWLWIFI_DEBUG
1940 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1941 isr_stats->sch);
1942 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1943 isr_stats->alive);
1944 #endif
1945 pos += scnprintf(buf + pos, bufsz - pos,
1946 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1947
1948 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1949 isr_stats->ctkill);
1950
1951 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1952 isr_stats->wakeup);
1953
1954 pos += scnprintf(buf + pos, bufsz - pos,
1955 "Rx command responses:\t\t %u\n", isr_stats->rx);
1956
1957 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1958 isr_stats->tx);
1959
1960 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1961 isr_stats->unhandled);
1962
1963 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1964 kfree(buf);
1965 return ret;
1966 }
1967
1968 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1969 const char __user *user_buf,
1970 size_t count, loff_t *ppos)
1971 {
1972 struct iwl_trans *trans = file->private_data;
1973 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1974 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1975
1976 char buf[8];
1977 int buf_size;
1978 u32 reset_flag;
1979
1980 memset(buf, 0, sizeof(buf));
1981 buf_size = min(count, sizeof(buf) - 1);
1982 if (copy_from_user(buf, user_buf, buf_size))
1983 return -EFAULT;
1984 if (sscanf(buf, "%x", &reset_flag) != 1)
1985 return -EFAULT;
1986 if (reset_flag == 0)
1987 memset(isr_stats, 0, sizeof(*isr_stats));
1988
1989 return count;
1990 }
1991
1992 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1993 const char __user *user_buf,
1994 size_t count, loff_t *ppos)
1995 {
1996 struct iwl_trans *trans = file->private_data;
1997 char buf[8];
1998 int buf_size;
1999 int csr;
2000
2001 memset(buf, 0, sizeof(buf));
2002 buf_size = min(count, sizeof(buf) - 1);
2003 if (copy_from_user(buf, user_buf, buf_size))
2004 return -EFAULT;
2005 if (sscanf(buf, "%d", &csr) != 1)
2006 return -EFAULT;
2007
2008 iwl_dump_csr(trans);
2009
2010 return count;
2011 }
2012
2013 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2014 char __user *user_buf,
2015 size_t count, loff_t *ppos)
2016 {
2017 struct iwl_trans *trans = file->private_data;
2018 char *buf = NULL;
2019 int pos = 0;
2020 ssize_t ret = -EFAULT;
2021
2022 ret = pos = iwl_dump_fh(trans, &buf);
2023 if (buf) {
2024 ret = simple_read_from_buffer(user_buf,
2025 count, ppos, buf, pos);
2026 kfree(buf);
2027 }
2028
2029 return ret;
2030 }
2031
2032 static ssize_t iwl_dbgfs_fw_restart_write(struct file *file,
2033 const char __user *user_buf,
2034 size_t count, loff_t *ppos)
2035 {
2036 struct iwl_trans *trans = file->private_data;
2037
2038 if (!trans->op_mode)
2039 return -EAGAIN;
2040
2041 local_bh_disable();
2042 iwl_op_mode_nic_error(trans->op_mode);
2043 local_bh_enable();
2044
2045 return count;
2046 }
2047
2048 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2049 DEBUGFS_READ_FILE_OPS(fh_reg);
2050 DEBUGFS_READ_FILE_OPS(rx_queue);
2051 DEBUGFS_READ_FILE_OPS(tx_queue);
2052 DEBUGFS_WRITE_FILE_OPS(csr);
2053 DEBUGFS_WRITE_FILE_OPS(fw_restart);
2054
2055 /*
2056 * Create the debugfs files and directories
2057 *
2058 */
2059 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2060 struct dentry *dir)
2061 {
2062 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2063 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2064 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2065 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2066 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2067 DEBUGFS_ADD_FILE(fw_restart, dir, S_IWUSR);
2068 return 0;
2069
2070 err:
2071 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2072 return -ENOMEM;
2073 }
2074 #else
2075 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2076 struct dentry *dir)
2077 {
2078 return 0;
2079 }
2080 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2081
2082 static const struct iwl_trans_ops trans_ops_pcie = {
2083 .start_hw = iwl_trans_pcie_start_hw,
2084 .stop_hw = iwl_trans_pcie_stop_hw,
2085 .fw_alive = iwl_trans_pcie_fw_alive,
2086 .start_fw = iwl_trans_pcie_start_fw,
2087 .stop_device = iwl_trans_pcie_stop_device,
2088
2089 .wowlan_suspend = iwl_trans_pcie_wowlan_suspend,
2090
2091 .send_cmd = iwl_trans_pcie_send_cmd,
2092
2093 .tx = iwl_trans_pcie_tx,
2094 .reclaim = iwl_trans_pcie_reclaim,
2095
2096 .txq_disable = iwl_trans_pcie_txq_disable,
2097 .txq_enable = iwl_trans_pcie_txq_enable,
2098
2099 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2100
2101 .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2102
2103 #ifdef CONFIG_PM_SLEEP
2104 .suspend = iwl_trans_pcie_suspend,
2105 .resume = iwl_trans_pcie_resume,
2106 #endif
2107 .write8 = iwl_trans_pcie_write8,
2108 .write32 = iwl_trans_pcie_write32,
2109 .read32 = iwl_trans_pcie_read32,
2110 .configure = iwl_trans_pcie_configure,
2111 .set_pmi = iwl_trans_pcie_set_pmi,
2112 };
2113
2114 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2115 const struct pci_device_id *ent,
2116 const struct iwl_cfg *cfg)
2117 {
2118 struct iwl_trans_pcie *trans_pcie;
2119 struct iwl_trans *trans;
2120 u16 pci_cmd;
2121 int err;
2122
2123 trans = kzalloc(sizeof(struct iwl_trans) +
2124 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2125
2126 if (WARN_ON(!trans))
2127 return NULL;
2128
2129 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2130
2131 trans->ops = &trans_ops_pcie;
2132 trans->cfg = cfg;
2133 trans_pcie->trans = trans;
2134 spin_lock_init(&trans_pcie->irq_lock);
2135 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2136
2137 /* W/A - seems to solve weird behavior. We need to remove this if we
2138 * don't want to stay in L1 all the time. This wastes a lot of power */
2139 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2140 PCIE_LINK_STATE_CLKPM);
2141
2142 if (pci_enable_device(pdev)) {
2143 err = -ENODEV;
2144 goto out_no_pci;
2145 }
2146
2147 pci_set_master(pdev);
2148
2149 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2150 if (!err)
2151 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2152 if (err) {
2153 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2154 if (!err)
2155 err = pci_set_consistent_dma_mask(pdev,
2156 DMA_BIT_MASK(32));
2157 /* both attempts failed: */
2158 if (err) {
2159 dev_printk(KERN_ERR, &pdev->dev,
2160 "No suitable DMA available.\n");
2161 goto out_pci_disable_device;
2162 }
2163 }
2164
2165 err = pci_request_regions(pdev, DRV_NAME);
2166 if (err) {
2167 dev_printk(KERN_ERR, &pdev->dev,
2168 "pci_request_regions failed\n");
2169 goto out_pci_disable_device;
2170 }
2171
2172 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2173 if (!trans_pcie->hw_base) {
2174 dev_printk(KERN_ERR, &pdev->dev, "pci_ioremap_bar failed\n");
2175 err = -ENODEV;
2176 goto out_pci_release_regions;
2177 }
2178
2179 dev_printk(KERN_INFO, &pdev->dev,
2180 "pci_resource_len = 0x%08llx\n",
2181 (unsigned long long) pci_resource_len(pdev, 0));
2182 dev_printk(KERN_INFO, &pdev->dev,
2183 "pci_resource_base = %p\n", trans_pcie->hw_base);
2184
2185 dev_printk(KERN_INFO, &pdev->dev,
2186 "HW Revision ID = 0x%X\n", pdev->revision);
2187
2188 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2189 * PCI Tx retries from interfering with C3 CPU state */
2190 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2191
2192 err = pci_enable_msi(pdev);
2193 if (err)
2194 dev_printk(KERN_ERR, &pdev->dev,
2195 "pci_enable_msi failed(0X%x)\n", err);
2196
2197 trans->dev = &pdev->dev;
2198 trans_pcie->irq = pdev->irq;
2199 trans_pcie->pci_dev = pdev;
2200 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2201 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2202 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2203 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2204
2205 /* TODO: Move this away, not needed if not MSI */
2206 /* enable rfkill interrupt: hw bug w/a */
2207 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2208 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2209 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2210 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2211 }
2212
2213 /* Initialize the wait queue for commands */
2214 init_waitqueue_head(&trans_pcie->wait_command_queue);
2215 spin_lock_init(&trans->reg_lock);
2216
2217 snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
2218 "iwl_cmd_pool:%s", dev_name(trans->dev));
2219
2220 trans->dev_cmd_headroom = 0;
2221 trans->dev_cmd_pool =
2222 kmem_cache_create(trans->dev_cmd_pool_name,
2223 sizeof(struct iwl_device_cmd)
2224 + trans->dev_cmd_headroom,
2225 sizeof(void *),
2226 SLAB_HWCACHE_ALIGN,
2227 NULL);
2228
2229 if (!trans->dev_cmd_pool)
2230 goto out_pci_disable_msi;
2231
2232 return trans;
2233
2234 out_pci_disable_msi:
2235 pci_disable_msi(pdev);
2236 out_pci_release_regions:
2237 pci_release_regions(pdev);
2238 out_pci_disable_device:
2239 pci_disable_device(pdev);
2240 out_no_pci:
2241 kfree(trans);
2242 return NULL;
2243 }
Linux kernel - Deliverables
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