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[deliverable/linux.git] / drivers / net / wireless / iwlwifi / pcie / trans.c
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
23 * USA
24 *
25 * The full GNU General Public License is included in this distribution
26 * in the file called COPYING.
27 *
28 * Contact Information:
29 * Intel Linux Wireless <ilw@linux.intel.com>
30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 *
32 * BSD LICENSE
33 *
34 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
35 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
36 * All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 *
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
47 * distribution.
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *
64 *****************************************************************************/
65 #include <linux/pci.h>
66 #include <linux/pci-aspm.h>
67 #include <linux/interrupt.h>
68 #include <linux/debugfs.h>
69 #include <linux/sched.h>
70 #include <linux/bitops.h>
71 #include <linux/gfp.h>
72 #include <linux/vmalloc.h>
73
74 #include "iwl-drv.h"
75 #include "iwl-trans.h"
76 #include "iwl-csr.h"
77 #include "iwl-prph.h"
78 #include "iwl-agn-hw.h"
79 #include "iwl-fw-error-dump.h"
80 #include "internal.h"
81
82 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
83 {
84 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
85
86 if (!trans_pcie->fw_mon_page)
87 return;
88
89 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
90 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
91 __free_pages(trans_pcie->fw_mon_page,
92 get_order(trans_pcie->fw_mon_size));
93 trans_pcie->fw_mon_page = NULL;
94 trans_pcie->fw_mon_phys = 0;
95 trans_pcie->fw_mon_size = 0;
96 }
97
98 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans)
99 {
100 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
101 struct page *page;
102 dma_addr_t phys;
103 u32 size;
104 u8 power;
105
106 if (trans_pcie->fw_mon_page) {
107 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
108 trans_pcie->fw_mon_size,
109 DMA_FROM_DEVICE);
110 return;
111 }
112
113 phys = 0;
114 for (power = 26; power >= 11; power--) {
115 int order;
116
117 size = BIT(power);
118 order = get_order(size);
119 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
120 order);
121 if (!page)
122 continue;
123
124 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
125 DMA_FROM_DEVICE);
126 if (dma_mapping_error(trans->dev, phys)) {
127 __free_pages(page, order);
128 continue;
129 }
130 IWL_INFO(trans,
131 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
132 size, order);
133 break;
134 }
135
136 if (WARN_ON_ONCE(!page))
137 return;
138
139 trans_pcie->fw_mon_page = page;
140 trans_pcie->fw_mon_phys = phys;
141 trans_pcie->fw_mon_size = size;
142 }
143
144 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
145 {
146 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
147 ((reg & 0x0000ffff) | (2 << 28)));
148 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
149 }
150
151 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
152 {
153 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
154 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
155 ((reg & 0x0000ffff) | (3 << 28)));
156 }
157
158 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
159 {
160 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
161 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
162 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
163 ~APMG_PS_CTRL_MSK_PWR_SRC);
164 else
165 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
166 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
167 ~APMG_PS_CTRL_MSK_PWR_SRC);
168 }
169
170 /* PCI registers */
171 #define PCI_CFG_RETRY_TIMEOUT 0x041
172
173 static void iwl_pcie_apm_config(struct iwl_trans *trans)
174 {
175 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
176 u16 lctl;
177 u16 cap;
178
179 /*
180 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
181 * Check if BIOS (or OS) enabled L1-ASPM on this device.
182 * If so (likely), disable L0S, so device moves directly L0->L1;
183 * costs negligible amount of power savings.
184 * If not (unlikely), enable L0S, so there is at least some
185 * power savings, even without L1.
186 */
187 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
188 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
189 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
190 else
191 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
192 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
193
194 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
195 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
196 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
197 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
198 trans->ltr_enabled ? "En" : "Dis");
199 }
200
201 /*
202 * Start up NIC's basic functionality after it has been reset
203 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
204 * NOTE: This does not load uCode nor start the embedded processor
205 */
206 static int iwl_pcie_apm_init(struct iwl_trans *trans)
207 {
208 int ret = 0;
209 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
210
211 /*
212 * Use "set_bit" below rather than "write", to preserve any hardware
213 * bits already set by default after reset.
214 */
215
216 /* Disable L0S exit timer (platform NMI Work/Around) */
217 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
218 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
219 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
220
221 /*
222 * Disable L0s without affecting L1;
223 * don't wait for ICH L0s (ICH bug W/A)
224 */
225 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
226 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
227
228 /* Set FH wait threshold to maximum (HW error during stress W/A) */
229 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
230
231 /*
232 * Enable HAP INTA (interrupt from management bus) to
233 * wake device's PCI Express link L1a -> L0s
234 */
235 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
236 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
237
238 iwl_pcie_apm_config(trans);
239
240 /* Configure analog phase-lock-loop before activating to D0A */
241 if (trans->cfg->base_params->pll_cfg_val)
242 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
243 trans->cfg->base_params->pll_cfg_val);
244
245 /*
246 * Set "initialization complete" bit to move adapter from
247 * D0U* --> D0A* (powered-up active) state.
248 */
249 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
250
251 /*
252 * Wait for clock stabilization; once stabilized, access to
253 * device-internal resources is supported, e.g. iwl_write_prph()
254 * and accesses to uCode SRAM.
255 */
256 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
257 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
258 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
259 if (ret < 0) {
260 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
261 goto out;
262 }
263
264 if (trans->cfg->host_interrupt_operation_mode) {
265 /*
266 * This is a bit of an abuse - This is needed for 7260 / 3160
267 * only check host_interrupt_operation_mode even if this is
268 * not related to host_interrupt_operation_mode.
269 *
270 * Enable the oscillator to count wake up time for L1 exit. This
271 * consumes slightly more power (100uA) - but allows to be sure
272 * that we wake up from L1 on time.
273 *
274 * This looks weird: read twice the same register, discard the
275 * value, set a bit, and yet again, read that same register
276 * just to discard the value. But that's the way the hardware
277 * seems to like it.
278 */
279 iwl_read_prph(trans, OSC_CLK);
280 iwl_read_prph(trans, OSC_CLK);
281 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
282 iwl_read_prph(trans, OSC_CLK);
283 iwl_read_prph(trans, OSC_CLK);
284 }
285
286 /*
287 * Enable DMA clock and wait for it to stabilize.
288 *
289 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
290 * bits do not disable clocks. This preserves any hardware
291 * bits already set by default in "CLK_CTRL_REG" after reset.
292 */
293 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
294 iwl_write_prph(trans, APMG_CLK_EN_REG,
295 APMG_CLK_VAL_DMA_CLK_RQT);
296 udelay(20);
297
298 /* Disable L1-Active */
299 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
300 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
301
302 /* Clear the interrupt in APMG if the NIC is in RFKILL */
303 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
304 APMG_RTC_INT_STT_RFKILL);
305 }
306
307 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
308
309 out:
310 return ret;
311 }
312
313 /*
314 * Enable LP XTAL to avoid HW bug where device may consume much power if
315 * FW is not loaded after device reset. LP XTAL is disabled by default
316 * after device HW reset. Do it only if XTAL is fed by internal source.
317 * Configure device's "persistence" mode to avoid resetting XTAL again when
318 * SHRD_HW_RST occurs in S3.
319 */
320 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
321 {
322 int ret;
323 u32 apmg_gp1_reg;
324 u32 apmg_xtal_cfg_reg;
325 u32 dl_cfg_reg;
326
327 /* Force XTAL ON */
328 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
329 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
330
331 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
332 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
333
334 udelay(10);
335
336 /*
337 * Set "initialization complete" bit to move adapter from
338 * D0U* --> D0A* (powered-up active) state.
339 */
340 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
341
342 /*
343 * Wait for clock stabilization; once stabilized, access to
344 * device-internal resources is possible.
345 */
346 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
347 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
348 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
349 25000);
350 if (WARN_ON(ret < 0)) {
351 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
352 /* Release XTAL ON request */
353 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
354 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
355 return;
356 }
357
358 /*
359 * Clear "disable persistence" to avoid LP XTAL resetting when
360 * SHRD_HW_RST is applied in S3.
361 */
362 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
363 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
364
365 /*
366 * Force APMG XTAL to be active to prevent its disabling by HW
367 * caused by APMG idle state.
368 */
369 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
370 SHR_APMG_XTAL_CFG_REG);
371 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
372 apmg_xtal_cfg_reg |
373 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
374
375 /*
376 * Reset entire device again - do controller reset (results in
377 * SHRD_HW_RST). Turn MAC off before proceeding.
378 */
379 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
380
381 udelay(10);
382
383 /* Enable LP XTAL by indirect access through CSR */
384 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
385 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
386 SHR_APMG_GP1_WF_XTAL_LP_EN |
387 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
388
389 /* Clear delay line clock power up */
390 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
391 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
392 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
393
394 /*
395 * Enable persistence mode to avoid LP XTAL resetting when
396 * SHRD_HW_RST is applied in S3.
397 */
398 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
399 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
400
401 /*
402 * Clear "initialization complete" bit to move adapter from
403 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
404 */
405 iwl_clear_bit(trans, CSR_GP_CNTRL,
406 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
407
408 /* Activates XTAL resources monitor */
409 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
410 CSR_MONITOR_XTAL_RESOURCES);
411
412 /* Release XTAL ON request */
413 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
414 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
415 udelay(10);
416
417 /* Release APMG XTAL */
418 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
419 apmg_xtal_cfg_reg &
420 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
421 }
422
423 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
424 {
425 int ret = 0;
426
427 /* stop device's busmaster DMA activity */
428 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
429
430 ret = iwl_poll_bit(trans, CSR_RESET,
431 CSR_RESET_REG_FLAG_MASTER_DISABLED,
432 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
433 if (ret < 0)
434 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
435
436 IWL_DEBUG_INFO(trans, "stop master\n");
437
438 return ret;
439 }
440
441 static void iwl_pcie_apm_stop(struct iwl_trans *trans)
442 {
443 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
444
445 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
446
447 /* Stop device's DMA activity */
448 iwl_pcie_apm_stop_master(trans);
449
450 if (trans->cfg->lp_xtal_workaround) {
451 iwl_pcie_apm_lp_xtal_enable(trans);
452 return;
453 }
454
455 /* Reset the entire device */
456 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
457
458 udelay(10);
459
460 /*
461 * Clear "initialization complete" bit to move adapter from
462 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
463 */
464 iwl_clear_bit(trans, CSR_GP_CNTRL,
465 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
466 }
467
468 static int iwl_pcie_nic_init(struct iwl_trans *trans)
469 {
470 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
471
472 /* nic_init */
473 spin_lock(&trans_pcie->irq_lock);
474 iwl_pcie_apm_init(trans);
475
476 spin_unlock(&trans_pcie->irq_lock);
477
478 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
479 iwl_pcie_set_pwr(trans, false);
480
481 iwl_op_mode_nic_config(trans->op_mode);
482
483 /* Allocate the RX queue, or reset if it is already allocated */
484 iwl_pcie_rx_init(trans);
485
486 /* Allocate or reset and init all Tx and Command queues */
487 if (iwl_pcie_tx_init(trans))
488 return -ENOMEM;
489
490 if (trans->cfg->base_params->shadow_reg_enable) {
491 /* enable shadow regs in HW */
492 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
493 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
494 }
495
496 return 0;
497 }
498
499 #define HW_READY_TIMEOUT (50)
500
501 /* Note: returns poll_bit return value, which is >= 0 if success */
502 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
503 {
504 int ret;
505
506 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
507 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
508
509 /* See if we got it */
510 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
511 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
512 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
513 HW_READY_TIMEOUT);
514
515 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
516 return ret;
517 }
518
519 /* Note: returns standard 0/-ERROR code */
520 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
521 {
522 int ret;
523 int t = 0;
524 int iter;
525
526 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
527
528 ret = iwl_pcie_set_hw_ready(trans);
529 /* If the card is ready, exit 0 */
530 if (ret >= 0)
531 return 0;
532
533 for (iter = 0; iter < 10; iter++) {
534 /* If HW is not ready, prepare the conditions to check again */
535 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
536 CSR_HW_IF_CONFIG_REG_PREPARE);
537
538 do {
539 ret = iwl_pcie_set_hw_ready(trans);
540 if (ret >= 0)
541 return 0;
542
543 usleep_range(200, 1000);
544 t += 200;
545 } while (t < 150000);
546 msleep(25);
547 }
548
549 IWL_ERR(trans, "Couldn't prepare the card\n");
550
551 return ret;
552 }
553
554 /*
555 * ucode
556 */
557 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
558 dma_addr_t phy_addr, u32 byte_cnt)
559 {
560 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
561 int ret;
562
563 trans_pcie->ucode_write_complete = false;
564
565 iwl_write_direct32(trans,
566 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
567 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
568
569 iwl_write_direct32(trans,
570 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
571 dst_addr);
572
573 iwl_write_direct32(trans,
574 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
575 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
576
577 iwl_write_direct32(trans,
578 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
579 (iwl_get_dma_hi_addr(phy_addr)
580 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
581
582 iwl_write_direct32(trans,
583 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
584 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
585 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
586 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
587
588 iwl_write_direct32(trans,
589 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
590 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
591 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
592 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
593
594 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
595 trans_pcie->ucode_write_complete, 5 * HZ);
596 if (!ret) {
597 IWL_ERR(trans, "Failed to load firmware chunk!\n");
598 return -ETIMEDOUT;
599 }
600
601 return 0;
602 }
603
604 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
605 const struct fw_desc *section)
606 {
607 u8 *v_addr;
608 dma_addr_t p_addr;
609 u32 offset, chunk_sz = section->len;
610 int ret = 0;
611
612 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
613 section_num);
614
615 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
616 GFP_KERNEL | __GFP_NOWARN);
617 if (!v_addr) {
618 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
619 chunk_sz = PAGE_SIZE;
620 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
621 &p_addr, GFP_KERNEL);
622 if (!v_addr)
623 return -ENOMEM;
624 }
625
626 for (offset = 0; offset < section->len; offset += chunk_sz) {
627 u32 copy_size;
628
629 copy_size = min_t(u32, chunk_sz, section->len - offset);
630
631 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
632 ret = iwl_pcie_load_firmware_chunk(trans,
633 section->offset + offset,
634 p_addr, copy_size);
635 if (ret) {
636 IWL_ERR(trans,
637 "Could not load the [%d] uCode section\n",
638 section_num);
639 break;
640 }
641 }
642
643 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
644 return ret;
645 }
646
647 static int iwl_pcie_load_cpu_secured_sections(struct iwl_trans *trans,
648 const struct fw_img *image,
649 int cpu,
650 int *first_ucode_section)
651 {
652 int shift_param;
653 int i, ret = 0;
654 u32 last_read_idx = 0;
655
656 if (cpu == 1) {
657 shift_param = 0;
658 *first_ucode_section = 0;
659 } else {
660 shift_param = 16;
661 (*first_ucode_section)++;
662 }
663
664 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
665 last_read_idx = i;
666
667 if (!image->sec[i].data ||
668 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
669 IWL_DEBUG_FW(trans,
670 "Break since Data not valid or Empty section, sec = %d\n",
671 i);
672 break;
673 }
674
675 if (i == (*first_ucode_section) + 1)
676 /* set CPU to started */
677 iwl_set_bits_prph(trans,
678 CSR_UCODE_LOAD_STATUS_ADDR,
679 LMPM_CPU_HDRS_LOADING_COMPLETED
680 << shift_param);
681
682 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
683 if (ret)
684 return ret;
685 }
686 /* image loading complete */
687 iwl_set_bits_prph(trans,
688 CSR_UCODE_LOAD_STATUS_ADDR,
689 LMPM_CPU_UCODE_LOADING_COMPLETED << shift_param);
690
691 *first_ucode_section = last_read_idx;
692
693 return 0;
694 }
695
696 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
697 const struct fw_img *image,
698 int cpu,
699 int *first_ucode_section)
700 {
701 int shift_param;
702 int i, ret = 0;
703 u32 last_read_idx = 0;
704
705 if (cpu == 1) {
706 shift_param = 0;
707 *first_ucode_section = 0;
708 } else {
709 shift_param = 16;
710 (*first_ucode_section)++;
711 }
712
713 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
714 last_read_idx = i;
715
716 if (!image->sec[i].data ||
717 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
718 IWL_DEBUG_FW(trans,
719 "Break since Data not valid or Empty section, sec = %d\n",
720 i);
721 break;
722 }
723
724 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
725 if (ret)
726 return ret;
727 }
728
729 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
730 iwl_set_bits_prph(trans,
731 CSR_UCODE_LOAD_STATUS_ADDR,
732 (LMPM_CPU_UCODE_LOADING_COMPLETED |
733 LMPM_CPU_HDRS_LOADING_COMPLETED |
734 LMPM_CPU_UCODE_LOADING_STARTED) <<
735 shift_param);
736
737 *first_ucode_section = last_read_idx;
738
739 return 0;
740 }
741
742 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
743 const struct fw_img *image)
744 {
745 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
746 int ret = 0;
747 int first_ucode_section;
748
749 IWL_DEBUG_FW(trans,
750 "working with %s CPU\n",
751 image->is_dual_cpus ? "Dual" : "Single");
752
753 /* configure the ucode to be ready to get the secured image */
754 if (iwl_has_secure_boot(trans->hw_rev, trans->cfg->device_family)) {
755 /* set secure boot inspector addresses */
756 iwl_write_prph(trans,
757 LMPM_SECURE_INSPECTOR_CODE_ADDR,
758 LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE);
759
760 iwl_write_prph(trans,
761 LMPM_SECURE_INSPECTOR_DATA_ADDR,
762 LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE);
763
764 /* set CPU1 header address */
765 iwl_write_prph(trans,
766 LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR,
767 LMPM_SECURE_CPU1_HDR_MEM_SPACE);
768
769 /* load to FW the binary Secured sections of CPU1 */
770 ret = iwl_pcie_load_cpu_secured_sections(trans, image, 1,
771 &first_ucode_section);
772 if (ret)
773 return ret;
774
775 } else {
776 /* load to FW the binary Non secured sections of CPU1 */
777 ret = iwl_pcie_load_cpu_sections(trans, image, 1,
778 &first_ucode_section);
779 if (ret)
780 return ret;
781 }
782
783 if (image->is_dual_cpus) {
784 /* set CPU2 header address */
785 iwl_write_prph(trans,
786 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
787 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
788
789 /* load to FW the binary sections of CPU2 */
790 if (iwl_has_secure_boot(trans->hw_rev,
791 trans->cfg->device_family))
792 ret = iwl_pcie_load_cpu_secured_sections(
793 trans, image, 2,
794 &first_ucode_section);
795 else
796 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
797 &first_ucode_section);
798 if (ret)
799 return ret;
800 }
801
802 /* supported for 7000 only for the moment */
803 if (iwlwifi_mod_params.fw_monitor &&
804 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
805 iwl_pcie_alloc_fw_monitor(trans);
806
807 if (trans_pcie->fw_mon_size) {
808 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
809 trans_pcie->fw_mon_phys >> 4);
810 iwl_write_prph(trans, MON_BUFF_END_ADDR,
811 (trans_pcie->fw_mon_phys +
812 trans_pcie->fw_mon_size) >> 4);
813 }
814 }
815
816 /* release CPU reset */
817 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
818 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
819 else
820 iwl_write32(trans, CSR_RESET, 0);
821
822 if (iwl_has_secure_boot(trans->hw_rev, trans->cfg->device_family)) {
823 /* wait for image verification to complete */
824 ret = iwl_poll_prph_bit(trans,
825 LMPM_SECURE_BOOT_CPU1_STATUS_ADDR,
826 LMPM_SECURE_BOOT_STATUS_SUCCESS,
827 LMPM_SECURE_BOOT_STATUS_SUCCESS,
828 LMPM_SECURE_TIME_OUT);
829
830 if (ret < 0) {
831 IWL_ERR(trans, "Time out on secure boot process\n");
832 return ret;
833 }
834 }
835
836 return 0;
837 }
838
839 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
840 const struct fw_img *fw, bool run_in_rfkill)
841 {
842 int ret;
843 bool hw_rfkill;
844
845 /* This may fail if AMT took ownership of the device */
846 if (iwl_pcie_prepare_card_hw(trans)) {
847 IWL_WARN(trans, "Exit HW not ready\n");
848 return -EIO;
849 }
850
851 iwl_enable_rfkill_int(trans);
852
853 /* If platform's RF_KILL switch is NOT set to KILL */
854 hw_rfkill = iwl_is_rfkill_set(trans);
855 if (hw_rfkill)
856 set_bit(STATUS_RFKILL, &trans->status);
857 else
858 clear_bit(STATUS_RFKILL, &trans->status);
859 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
860 if (hw_rfkill && !run_in_rfkill)
861 return -ERFKILL;
862
863 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
864
865 ret = iwl_pcie_nic_init(trans);
866 if (ret) {
867 IWL_ERR(trans, "Unable to init nic\n");
868 return ret;
869 }
870
871 /* make sure rfkill handshake bits are cleared */
872 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
873 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
874 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
875
876 /* clear (again), then enable host interrupts */
877 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
878 iwl_enable_interrupts(trans);
879
880 /* really make sure rfkill handshake bits are cleared */
881 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
882 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
883
884 /* Load the given image to the HW */
885 return iwl_pcie_load_given_ucode(trans, fw);
886 }
887
888 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
889 {
890 iwl_pcie_reset_ict(trans);
891 iwl_pcie_tx_start(trans, scd_addr);
892 }
893
894 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
895 {
896 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
897 bool hw_rfkill, was_hw_rfkill;
898
899 was_hw_rfkill = iwl_is_rfkill_set(trans);
900
901 /* tell the device to stop sending interrupts */
902 spin_lock(&trans_pcie->irq_lock);
903 iwl_disable_interrupts(trans);
904 spin_unlock(&trans_pcie->irq_lock);
905
906 /* device going down, Stop using ICT table */
907 iwl_pcie_disable_ict(trans);
908
909 /*
910 * If a HW restart happens during firmware loading,
911 * then the firmware loading might call this function
912 * and later it might be called again due to the
913 * restart. So don't process again if the device is
914 * already dead.
915 */
916 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
917 iwl_pcie_tx_stop(trans);
918 iwl_pcie_rx_stop(trans);
919
920 /* Power-down device's busmaster DMA clocks */
921 iwl_write_prph(trans, APMG_CLK_DIS_REG,
922 APMG_CLK_VAL_DMA_CLK_RQT);
923 udelay(5);
924 }
925
926 /* Make sure (redundant) we've released our request to stay awake */
927 iwl_clear_bit(trans, CSR_GP_CNTRL,
928 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
929
930 /* Stop the device, and put it in low power state */
931 iwl_pcie_apm_stop(trans);
932
933 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
934 * Clean again the interrupt here
935 */
936 spin_lock(&trans_pcie->irq_lock);
937 iwl_disable_interrupts(trans);
938 spin_unlock(&trans_pcie->irq_lock);
939
940 /* stop and reset the on-board processor */
941 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
942
943 /* clear all status bits */
944 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
945 clear_bit(STATUS_INT_ENABLED, &trans->status);
946 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
947 clear_bit(STATUS_TPOWER_PMI, &trans->status);
948 clear_bit(STATUS_RFKILL, &trans->status);
949
950 /*
951 * Even if we stop the HW, we still want the RF kill
952 * interrupt
953 */
954 iwl_enable_rfkill_int(trans);
955
956 /*
957 * Check again since the RF kill state may have changed while
958 * all the interrupts were disabled, in this case we couldn't
959 * receive the RF kill interrupt and update the state in the
960 * op_mode.
961 * Don't call the op_mode if the rkfill state hasn't changed.
962 * This allows the op_mode to call stop_device from the rfkill
963 * notification without endless recursion. Under very rare
964 * circumstances, we might have a small recursion if the rfkill
965 * state changed exactly now while we were called from stop_device.
966 * This is very unlikely but can happen and is supported.
967 */
968 hw_rfkill = iwl_is_rfkill_set(trans);
969 if (hw_rfkill)
970 set_bit(STATUS_RFKILL, &trans->status);
971 else
972 clear_bit(STATUS_RFKILL, &trans->status);
973 if (hw_rfkill != was_hw_rfkill)
974 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
975 }
976
977 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
978 {
979 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
980 iwl_trans_pcie_stop_device(trans);
981 }
982
983 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
984 {
985 iwl_disable_interrupts(trans);
986
987 /*
988 * in testing mode, the host stays awake and the
989 * hardware won't be reset (not even partially)
990 */
991 if (test)
992 return;
993
994 iwl_pcie_disable_ict(trans);
995
996 iwl_clear_bit(trans, CSR_GP_CNTRL,
997 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
998 iwl_clear_bit(trans, CSR_GP_CNTRL,
999 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1000
1001 /*
1002 * reset TX queues -- some of their registers reset during S3
1003 * so if we don't reset everything here the D3 image would try
1004 * to execute some invalid memory upon resume
1005 */
1006 iwl_trans_pcie_tx_reset(trans);
1007
1008 iwl_pcie_set_pwr(trans, true);
1009 }
1010
1011 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1012 enum iwl_d3_status *status,
1013 bool test)
1014 {
1015 u32 val;
1016 int ret;
1017
1018 if (test) {
1019 iwl_enable_interrupts(trans);
1020 *status = IWL_D3_STATUS_ALIVE;
1021 return 0;
1022 }
1023
1024 /*
1025 * Also enables interrupts - none will happen as the device doesn't
1026 * know we're waking it up, only when the opmode actually tells it
1027 * after this call.
1028 */
1029 iwl_pcie_reset_ict(trans);
1030
1031 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1032 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1033
1034 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1035 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1036 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1037 25000);
1038 if (ret < 0) {
1039 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1040 return ret;
1041 }
1042
1043 iwl_pcie_set_pwr(trans, false);
1044
1045 iwl_trans_pcie_tx_reset(trans);
1046
1047 ret = iwl_pcie_rx_init(trans);
1048 if (ret) {
1049 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
1050 return ret;
1051 }
1052
1053 val = iwl_read32(trans, CSR_RESET);
1054 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1055 *status = IWL_D3_STATUS_RESET;
1056 else
1057 *status = IWL_D3_STATUS_ALIVE;
1058
1059 return 0;
1060 }
1061
1062 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1063 {
1064 bool hw_rfkill;
1065 int err;
1066
1067 err = iwl_pcie_prepare_card_hw(trans);
1068 if (err) {
1069 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1070 return err;
1071 }
1072
1073 /* Reset the entire device */
1074 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1075
1076 usleep_range(10, 15);
1077
1078 iwl_pcie_apm_init(trans);
1079
1080 /* From now on, the op_mode will be kept updated about RF kill state */
1081 iwl_enable_rfkill_int(trans);
1082
1083 hw_rfkill = iwl_is_rfkill_set(trans);
1084 if (hw_rfkill)
1085 set_bit(STATUS_RFKILL, &trans->status);
1086 else
1087 clear_bit(STATUS_RFKILL, &trans->status);
1088 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1089
1090 return 0;
1091 }
1092
1093 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1094 {
1095 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1096
1097 /* disable interrupts - don't enable HW RF kill interrupt */
1098 spin_lock(&trans_pcie->irq_lock);
1099 iwl_disable_interrupts(trans);
1100 spin_unlock(&trans_pcie->irq_lock);
1101
1102 iwl_pcie_apm_stop(trans);
1103
1104 spin_lock(&trans_pcie->irq_lock);
1105 iwl_disable_interrupts(trans);
1106 spin_unlock(&trans_pcie->irq_lock);
1107
1108 iwl_pcie_disable_ict(trans);
1109 }
1110
1111 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1112 {
1113 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1114 }
1115
1116 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1117 {
1118 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1119 }
1120
1121 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1122 {
1123 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1124 }
1125
1126 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1127 {
1128 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1129 ((reg & 0x000FFFFF) | (3 << 24)));
1130 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1131 }
1132
1133 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1134 u32 val)
1135 {
1136 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1137 ((addr & 0x000FFFFF) | (3 << 24)));
1138 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1139 }
1140
1141 static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1142 {
1143 WARN_ON(1);
1144 return 0;
1145 }
1146
1147 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1148 const struct iwl_trans_config *trans_cfg)
1149 {
1150 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1151
1152 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1153 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1154 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1155 trans_pcie->n_no_reclaim_cmds = 0;
1156 else
1157 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1158 if (trans_pcie->n_no_reclaim_cmds)
1159 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1160 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1161
1162 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1163 if (trans_pcie->rx_buf_size_8k)
1164 trans_pcie->rx_page_order = get_order(8 * 1024);
1165 else
1166 trans_pcie->rx_page_order = get_order(4 * 1024);
1167
1168 trans_pcie->wd_timeout =
1169 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
1170
1171 trans_pcie->command_names = trans_cfg->command_names;
1172 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1173 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1174
1175 /* Initialize NAPI here - it should be before registering to mac80211
1176 * in the opmode but after the HW struct is allocated.
1177 * As this function may be called again in some corner cases don't
1178 * do anything if NAPI was already initialized.
1179 */
1180 if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1181 init_dummy_netdev(&trans_pcie->napi_dev);
1182 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1183 &trans_pcie->napi_dev,
1184 iwl_pcie_dummy_napi_poll, 64);
1185 }
1186 }
1187
1188 void iwl_trans_pcie_free(struct iwl_trans *trans)
1189 {
1190 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1191
1192 synchronize_irq(trans_pcie->pci_dev->irq);
1193
1194 iwl_pcie_tx_free(trans);
1195 iwl_pcie_rx_free(trans);
1196
1197 free_irq(trans_pcie->pci_dev->irq, trans);
1198 iwl_pcie_free_ict(trans);
1199
1200 pci_disable_msi(trans_pcie->pci_dev);
1201 iounmap(trans_pcie->hw_base);
1202 pci_release_regions(trans_pcie->pci_dev);
1203 pci_disable_device(trans_pcie->pci_dev);
1204 kmem_cache_destroy(trans->dev_cmd_pool);
1205
1206 if (trans_pcie->napi.poll)
1207 netif_napi_del(&trans_pcie->napi);
1208
1209 iwl_pcie_free_fw_monitor(trans);
1210
1211 kfree(trans);
1212 }
1213
1214 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1215 {
1216 if (state)
1217 set_bit(STATUS_TPOWER_PMI, &trans->status);
1218 else
1219 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1220 }
1221
1222 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1223 unsigned long *flags)
1224 {
1225 int ret;
1226 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1227
1228 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1229
1230 if (trans_pcie->cmd_in_flight)
1231 goto out;
1232
1233 /* this bit wakes up the NIC */
1234 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1235 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1236
1237 /*
1238 * These bits say the device is running, and should keep running for
1239 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1240 * but they do not indicate that embedded SRAM is restored yet;
1241 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1242 * to/from host DRAM when sleeping/waking for power-saving.
1243 * Each direction takes approximately 1/4 millisecond; with this
1244 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1245 * series of register accesses are expected (e.g. reading Event Log),
1246 * to keep device from sleeping.
1247 *
1248 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1249 * SRAM is okay/restored. We don't check that here because this call
1250 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1251 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1252 *
1253 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1254 * and do not save/restore SRAM when power cycling.
1255 */
1256 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1257 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1258 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1259 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1260 if (unlikely(ret < 0)) {
1261 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1262 if (!silent) {
1263 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1264 WARN_ONCE(1,
1265 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1266 val);
1267 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1268 return false;
1269 }
1270 }
1271
1272 out:
1273 /*
1274 * Fool sparse by faking we release the lock - sparse will
1275 * track nic_access anyway.
1276 */
1277 __release(&trans_pcie->reg_lock);
1278 return true;
1279 }
1280
1281 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1282 unsigned long *flags)
1283 {
1284 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1285
1286 lockdep_assert_held(&trans_pcie->reg_lock);
1287
1288 /*
1289 * Fool sparse by faking we acquiring the lock - sparse will
1290 * track nic_access anyway.
1291 */
1292 __acquire(&trans_pcie->reg_lock);
1293
1294 if (trans_pcie->cmd_in_flight)
1295 goto out;
1296
1297 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1298 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1299 /*
1300 * Above we read the CSR_GP_CNTRL register, which will flush
1301 * any previous writes, but we need the write that clears the
1302 * MAC_ACCESS_REQ bit to be performed before any other writes
1303 * scheduled on different CPUs (after we drop reg_lock).
1304 */
1305 mmiowb();
1306 out:
1307 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1308 }
1309
1310 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1311 void *buf, int dwords)
1312 {
1313 unsigned long flags;
1314 int offs, ret = 0;
1315 u32 *vals = buf;
1316
1317 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1318 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1319 for (offs = 0; offs < dwords; offs++)
1320 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1321 iwl_trans_release_nic_access(trans, &flags);
1322 } else {
1323 ret = -EBUSY;
1324 }
1325 return ret;
1326 }
1327
1328 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1329 const void *buf, int dwords)
1330 {
1331 unsigned long flags;
1332 int offs, ret = 0;
1333 const u32 *vals = buf;
1334
1335 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1336 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1337 for (offs = 0; offs < dwords; offs++)
1338 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1339 vals ? vals[offs] : 0);
1340 iwl_trans_release_nic_access(trans, &flags);
1341 } else {
1342 ret = -EBUSY;
1343 }
1344 return ret;
1345 }
1346
1347 #define IWL_FLUSH_WAIT_MS 2000
1348
1349 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1350 {
1351 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1352 struct iwl_txq *txq;
1353 struct iwl_queue *q;
1354 int cnt;
1355 unsigned long now = jiffies;
1356 u32 scd_sram_addr;
1357 u8 buf[16];
1358 int ret = 0;
1359
1360 /* waiting for all the tx frames complete might take a while */
1361 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1362 u8 wr_ptr;
1363
1364 if (cnt == trans_pcie->cmd_queue)
1365 continue;
1366 if (!test_bit(cnt, trans_pcie->queue_used))
1367 continue;
1368 if (!(BIT(cnt) & txq_bm))
1369 continue;
1370
1371 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1372 txq = &trans_pcie->txq[cnt];
1373 q = &txq->q;
1374 wr_ptr = ACCESS_ONCE(q->write_ptr);
1375
1376 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1377 !time_after(jiffies,
1378 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1379 u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1380
1381 if (WARN_ONCE(wr_ptr != write_ptr,
1382 "WR pointer moved while flushing %d -> %d\n",
1383 wr_ptr, write_ptr))
1384 return -ETIMEDOUT;
1385 msleep(1);
1386 }
1387
1388 if (q->read_ptr != q->write_ptr) {
1389 IWL_ERR(trans,
1390 "fail to flush all tx fifo queues Q %d\n", cnt);
1391 ret = -ETIMEDOUT;
1392 break;
1393 }
1394 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1395 }
1396
1397 if (!ret)
1398 return 0;
1399
1400 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1401 txq->q.read_ptr, txq->q.write_ptr);
1402
1403 scd_sram_addr = trans_pcie->scd_base_addr +
1404 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1405 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1406
1407 iwl_print_hex_error(trans, buf, sizeof(buf));
1408
1409 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1410 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1411 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1412
1413 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1414 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1415 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1416 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1417 u32 tbl_dw =
1418 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1419 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1420
1421 if (cnt & 0x1)
1422 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1423 else
1424 tbl_dw = tbl_dw & 0x0000FFFF;
1425
1426 IWL_ERR(trans,
1427 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1428 cnt, active ? "" : "in", fifo, tbl_dw,
1429 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1430 (TFD_QUEUE_SIZE_MAX - 1),
1431 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1432 }
1433
1434 return ret;
1435 }
1436
1437 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1438 u32 mask, u32 value)
1439 {
1440 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1441 unsigned long flags;
1442
1443 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1444 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1445 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1446 }
1447
1448 static const char *get_csr_string(int cmd)
1449 {
1450 #define IWL_CMD(x) case x: return #x
1451 switch (cmd) {
1452 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1453 IWL_CMD(CSR_INT_COALESCING);
1454 IWL_CMD(CSR_INT);
1455 IWL_CMD(CSR_INT_MASK);
1456 IWL_CMD(CSR_FH_INT_STATUS);
1457 IWL_CMD(CSR_GPIO_IN);
1458 IWL_CMD(CSR_RESET);
1459 IWL_CMD(CSR_GP_CNTRL);
1460 IWL_CMD(CSR_HW_REV);
1461 IWL_CMD(CSR_EEPROM_REG);
1462 IWL_CMD(CSR_EEPROM_GP);
1463 IWL_CMD(CSR_OTP_GP_REG);
1464 IWL_CMD(CSR_GIO_REG);
1465 IWL_CMD(CSR_GP_UCODE_REG);
1466 IWL_CMD(CSR_GP_DRIVER_REG);
1467 IWL_CMD(CSR_UCODE_DRV_GP1);
1468 IWL_CMD(CSR_UCODE_DRV_GP2);
1469 IWL_CMD(CSR_LED_REG);
1470 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1471 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1472 IWL_CMD(CSR_ANA_PLL_CFG);
1473 IWL_CMD(CSR_HW_REV_WA_REG);
1474 IWL_CMD(CSR_MONITOR_STATUS_REG);
1475 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1476 default:
1477 return "UNKNOWN";
1478 }
1479 #undef IWL_CMD
1480 }
1481
1482 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1483 {
1484 int i;
1485 static const u32 csr_tbl[] = {
1486 CSR_HW_IF_CONFIG_REG,
1487 CSR_INT_COALESCING,
1488 CSR_INT,
1489 CSR_INT_MASK,
1490 CSR_FH_INT_STATUS,
1491 CSR_GPIO_IN,
1492 CSR_RESET,
1493 CSR_GP_CNTRL,
1494 CSR_HW_REV,
1495 CSR_EEPROM_REG,
1496 CSR_EEPROM_GP,
1497 CSR_OTP_GP_REG,
1498 CSR_GIO_REG,
1499 CSR_GP_UCODE_REG,
1500 CSR_GP_DRIVER_REG,
1501 CSR_UCODE_DRV_GP1,
1502 CSR_UCODE_DRV_GP2,
1503 CSR_LED_REG,
1504 CSR_DRAM_INT_TBL_REG,
1505 CSR_GIO_CHICKEN_BITS,
1506 CSR_ANA_PLL_CFG,
1507 CSR_MONITOR_STATUS_REG,
1508 CSR_HW_REV_WA_REG,
1509 CSR_DBG_HPET_MEM_REG
1510 };
1511 IWL_ERR(trans, "CSR values:\n");
1512 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1513 "CSR_INT_PERIODIC_REG)\n");
1514 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1515 IWL_ERR(trans, " %25s: 0X%08x\n",
1516 get_csr_string(csr_tbl[i]),
1517 iwl_read32(trans, csr_tbl[i]));
1518 }
1519 }
1520
1521 #ifdef CONFIG_IWLWIFI_DEBUGFS
1522 /* create and remove of files */
1523 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1524 if (!debugfs_create_file(#name, mode, parent, trans, \
1525 &iwl_dbgfs_##name##_ops)) \
1526 goto err; \
1527 } while (0)
1528
1529 /* file operation */
1530 #define DEBUGFS_READ_FILE_OPS(name) \
1531 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1532 .read = iwl_dbgfs_##name##_read, \
1533 .open = simple_open, \
1534 .llseek = generic_file_llseek, \
1535 };
1536
1537 #define DEBUGFS_WRITE_FILE_OPS(name) \
1538 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1539 .write = iwl_dbgfs_##name##_write, \
1540 .open = simple_open, \
1541 .llseek = generic_file_llseek, \
1542 };
1543
1544 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1545 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1546 .write = iwl_dbgfs_##name##_write, \
1547 .read = iwl_dbgfs_##name##_read, \
1548 .open = simple_open, \
1549 .llseek = generic_file_llseek, \
1550 };
1551
1552 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1553 char __user *user_buf,
1554 size_t count, loff_t *ppos)
1555 {
1556 struct iwl_trans *trans = file->private_data;
1557 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1558 struct iwl_txq *txq;
1559 struct iwl_queue *q;
1560 char *buf;
1561 int pos = 0;
1562 int cnt;
1563 int ret;
1564 size_t bufsz;
1565
1566 bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1567
1568 if (!trans_pcie->txq)
1569 return -EAGAIN;
1570
1571 buf = kzalloc(bufsz, GFP_KERNEL);
1572 if (!buf)
1573 return -ENOMEM;
1574
1575 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1576 txq = &trans_pcie->txq[cnt];
1577 q = &txq->q;
1578 pos += scnprintf(buf + pos, bufsz - pos,
1579 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d%s\n",
1580 cnt, q->read_ptr, q->write_ptr,
1581 !!test_bit(cnt, trans_pcie->queue_used),
1582 !!test_bit(cnt, trans_pcie->queue_stopped),
1583 txq->need_update,
1584 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
1585 }
1586 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1587 kfree(buf);
1588 return ret;
1589 }
1590
1591 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1592 char __user *user_buf,
1593 size_t count, loff_t *ppos)
1594 {
1595 struct iwl_trans *trans = file->private_data;
1596 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1597 struct iwl_rxq *rxq = &trans_pcie->rxq;
1598 char buf[256];
1599 int pos = 0;
1600 const size_t bufsz = sizeof(buf);
1601
1602 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1603 rxq->read);
1604 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1605 rxq->write);
1606 pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
1607 rxq->write_actual);
1608 pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
1609 rxq->need_update);
1610 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1611 rxq->free_count);
1612 if (rxq->rb_stts) {
1613 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1614 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1615 } else {
1616 pos += scnprintf(buf + pos, bufsz - pos,
1617 "closed_rb_num: Not Allocated\n");
1618 }
1619 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1620 }
1621
1622 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1623 char __user *user_buf,
1624 size_t count, loff_t *ppos)
1625 {
1626 struct iwl_trans *trans = file->private_data;
1627 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1628 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1629
1630 int pos = 0;
1631 char *buf;
1632 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1633 ssize_t ret;
1634
1635 buf = kzalloc(bufsz, GFP_KERNEL);
1636 if (!buf)
1637 return -ENOMEM;
1638
1639 pos += scnprintf(buf + pos, bufsz - pos,
1640 "Interrupt Statistics Report:\n");
1641
1642 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1643 isr_stats->hw);
1644 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1645 isr_stats->sw);
1646 if (isr_stats->sw || isr_stats->hw) {
1647 pos += scnprintf(buf + pos, bufsz - pos,
1648 "\tLast Restarting Code: 0x%X\n",
1649 isr_stats->err_code);
1650 }
1651 #ifdef CONFIG_IWLWIFI_DEBUG
1652 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1653 isr_stats->sch);
1654 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1655 isr_stats->alive);
1656 #endif
1657 pos += scnprintf(buf + pos, bufsz - pos,
1658 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1659
1660 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1661 isr_stats->ctkill);
1662
1663 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1664 isr_stats->wakeup);
1665
1666 pos += scnprintf(buf + pos, bufsz - pos,
1667 "Rx command responses:\t\t %u\n", isr_stats->rx);
1668
1669 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1670 isr_stats->tx);
1671
1672 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1673 isr_stats->unhandled);
1674
1675 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1676 kfree(buf);
1677 return ret;
1678 }
1679
1680 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1681 const char __user *user_buf,
1682 size_t count, loff_t *ppos)
1683 {
1684 struct iwl_trans *trans = file->private_data;
1685 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1686 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1687
1688 char buf[8];
1689 int buf_size;
1690 u32 reset_flag;
1691
1692 memset(buf, 0, sizeof(buf));
1693 buf_size = min(count, sizeof(buf) - 1);
1694 if (copy_from_user(buf, user_buf, buf_size))
1695 return -EFAULT;
1696 if (sscanf(buf, "%x", &reset_flag) != 1)
1697 return -EFAULT;
1698 if (reset_flag == 0)
1699 memset(isr_stats, 0, sizeof(*isr_stats));
1700
1701 return count;
1702 }
1703
1704 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1705 const char __user *user_buf,
1706 size_t count, loff_t *ppos)
1707 {
1708 struct iwl_trans *trans = file->private_data;
1709 char buf[8];
1710 int buf_size;
1711 int csr;
1712
1713 memset(buf, 0, sizeof(buf));
1714 buf_size = min(count, sizeof(buf) - 1);
1715 if (copy_from_user(buf, user_buf, buf_size))
1716 return -EFAULT;
1717 if (sscanf(buf, "%d", &csr) != 1)
1718 return -EFAULT;
1719
1720 iwl_pcie_dump_csr(trans);
1721
1722 return count;
1723 }
1724
1725 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1726 char __user *user_buf,
1727 size_t count, loff_t *ppos)
1728 {
1729 struct iwl_trans *trans = file->private_data;
1730 char *buf = NULL;
1731 ssize_t ret;
1732
1733 ret = iwl_dump_fh(trans, &buf);
1734 if (ret < 0)
1735 return ret;
1736 if (!buf)
1737 return -EINVAL;
1738 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
1739 kfree(buf);
1740 return ret;
1741 }
1742
1743 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1744 DEBUGFS_READ_FILE_OPS(fh_reg);
1745 DEBUGFS_READ_FILE_OPS(rx_queue);
1746 DEBUGFS_READ_FILE_OPS(tx_queue);
1747 DEBUGFS_WRITE_FILE_OPS(csr);
1748
1749 /*
1750 * Create the debugfs files and directories
1751 *
1752 */
1753 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1754 struct dentry *dir)
1755 {
1756 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1757 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1758 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1759 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1760 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1761 return 0;
1762
1763 err:
1764 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1765 return -ENOMEM;
1766 }
1767 #else
1768 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1769 struct dentry *dir)
1770 {
1771 return 0;
1772 }
1773 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1774
1775 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
1776 {
1777 u32 cmdlen = 0;
1778 int i;
1779
1780 for (i = 0; i < IWL_NUM_OF_TBS; i++)
1781 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
1782
1783 return cmdlen;
1784 }
1785
1786 static const struct {
1787 u32 start, end;
1788 } iwl_prph_dump_addr[] = {
1789 { .start = 0x00a00000, .end = 0x00a00000 },
1790 { .start = 0x00a0000c, .end = 0x00a00024 },
1791 { .start = 0x00a0002c, .end = 0x00a0003c },
1792 { .start = 0x00a00410, .end = 0x00a00418 },
1793 { .start = 0x00a00420, .end = 0x00a00420 },
1794 { .start = 0x00a00428, .end = 0x00a00428 },
1795 { .start = 0x00a00430, .end = 0x00a0043c },
1796 { .start = 0x00a00444, .end = 0x00a00444 },
1797 { .start = 0x00a004c0, .end = 0x00a004cc },
1798 { .start = 0x00a004d8, .end = 0x00a004d8 },
1799 { .start = 0x00a004e0, .end = 0x00a004f0 },
1800 { .start = 0x00a00840, .end = 0x00a00840 },
1801 { .start = 0x00a00850, .end = 0x00a00858 },
1802 { .start = 0x00a01004, .end = 0x00a01008 },
1803 { .start = 0x00a01010, .end = 0x00a01010 },
1804 { .start = 0x00a01018, .end = 0x00a01018 },
1805 { .start = 0x00a01024, .end = 0x00a01024 },
1806 { .start = 0x00a0102c, .end = 0x00a01034 },
1807 { .start = 0x00a0103c, .end = 0x00a01040 },
1808 { .start = 0x00a01048, .end = 0x00a01094 },
1809 { .start = 0x00a01c00, .end = 0x00a01c20 },
1810 { .start = 0x00a01c58, .end = 0x00a01c58 },
1811 { .start = 0x00a01c7c, .end = 0x00a01c7c },
1812 { .start = 0x00a01c28, .end = 0x00a01c54 },
1813 { .start = 0x00a01c5c, .end = 0x00a01c5c },
1814 { .start = 0x00a01c84, .end = 0x00a01c84 },
1815 { .start = 0x00a01ce0, .end = 0x00a01d0c },
1816 { .start = 0x00a01d18, .end = 0x00a01d20 },
1817 { .start = 0x00a01d2c, .end = 0x00a01d30 },
1818 { .start = 0x00a01d40, .end = 0x00a01d5c },
1819 { .start = 0x00a01d80, .end = 0x00a01d80 },
1820 { .start = 0x00a01d98, .end = 0x00a01d98 },
1821 { .start = 0x00a01dc0, .end = 0x00a01dfc },
1822 { .start = 0x00a01e00, .end = 0x00a01e2c },
1823 { .start = 0x00a01e40, .end = 0x00a01e60 },
1824 { .start = 0x00a01e84, .end = 0x00a01e90 },
1825 { .start = 0x00a01e9c, .end = 0x00a01ec4 },
1826 { .start = 0x00a01ed0, .end = 0x00a01ed0 },
1827 { .start = 0x00a01f00, .end = 0x00a01f14 },
1828 { .start = 0x00a01f44, .end = 0x00a01f58 },
1829 { .start = 0x00a01f80, .end = 0x00a01fa8 },
1830 { .start = 0x00a01fb0, .end = 0x00a01fbc },
1831 { .start = 0x00a01ff8, .end = 0x00a01ffc },
1832 { .start = 0x00a02000, .end = 0x00a02048 },
1833 { .start = 0x00a02068, .end = 0x00a020f0 },
1834 { .start = 0x00a02100, .end = 0x00a02118 },
1835 { .start = 0x00a02140, .end = 0x00a0214c },
1836 { .start = 0x00a02168, .end = 0x00a0218c },
1837 { .start = 0x00a021c0, .end = 0x00a021c0 },
1838 { .start = 0x00a02400, .end = 0x00a02410 },
1839 { .start = 0x00a02418, .end = 0x00a02420 },
1840 { .start = 0x00a02428, .end = 0x00a0242c },
1841 { .start = 0x00a02434, .end = 0x00a02434 },
1842 { .start = 0x00a02440, .end = 0x00a02460 },
1843 { .start = 0x00a02468, .end = 0x00a024b0 },
1844 { .start = 0x00a024c8, .end = 0x00a024cc },
1845 { .start = 0x00a02500, .end = 0x00a02504 },
1846 { .start = 0x00a0250c, .end = 0x00a02510 },
1847 { .start = 0x00a02540, .end = 0x00a02554 },
1848 { .start = 0x00a02580, .end = 0x00a025f4 },
1849 { .start = 0x00a02600, .end = 0x00a0260c },
1850 { .start = 0x00a02648, .end = 0x00a02650 },
1851 { .start = 0x00a02680, .end = 0x00a02680 },
1852 { .start = 0x00a026c0, .end = 0x00a026d0 },
1853 { .start = 0x00a02700, .end = 0x00a0270c },
1854 { .start = 0x00a02804, .end = 0x00a02804 },
1855 { .start = 0x00a02818, .end = 0x00a0281c },
1856 { .start = 0x00a02c00, .end = 0x00a02db4 },
1857 { .start = 0x00a02df4, .end = 0x00a02fb0 },
1858 { .start = 0x00a03000, .end = 0x00a03014 },
1859 { .start = 0x00a0301c, .end = 0x00a0302c },
1860 { .start = 0x00a03034, .end = 0x00a03038 },
1861 { .start = 0x00a03040, .end = 0x00a03048 },
1862 { .start = 0x00a03060, .end = 0x00a03068 },
1863 { .start = 0x00a03070, .end = 0x00a03074 },
1864 { .start = 0x00a0307c, .end = 0x00a0307c },
1865 { .start = 0x00a03080, .end = 0x00a03084 },
1866 { .start = 0x00a0308c, .end = 0x00a03090 },
1867 { .start = 0x00a03098, .end = 0x00a03098 },
1868 { .start = 0x00a030a0, .end = 0x00a030a0 },
1869 { .start = 0x00a030a8, .end = 0x00a030b4 },
1870 { .start = 0x00a030bc, .end = 0x00a030bc },
1871 { .start = 0x00a030c0, .end = 0x00a0312c },
1872 { .start = 0x00a03c00, .end = 0x00a03c5c },
1873 { .start = 0x00a04400, .end = 0x00a04454 },
1874 { .start = 0x00a04460, .end = 0x00a04474 },
1875 { .start = 0x00a044c0, .end = 0x00a044ec },
1876 { .start = 0x00a04500, .end = 0x00a04504 },
1877 { .start = 0x00a04510, .end = 0x00a04538 },
1878 { .start = 0x00a04540, .end = 0x00a04548 },
1879 { .start = 0x00a04560, .end = 0x00a0457c },
1880 { .start = 0x00a04590, .end = 0x00a04598 },
1881 { .start = 0x00a045c0, .end = 0x00a045f4 },
1882 };
1883
1884 static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
1885 struct iwl_fw_error_dump_data **data)
1886 {
1887 struct iwl_fw_error_dump_prph *prph;
1888 unsigned long flags;
1889 u32 prph_len = 0, i;
1890
1891 if (!iwl_trans_grab_nic_access(trans, false, &flags))
1892 return 0;
1893
1894 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
1895 /* The range includes both boundaries */
1896 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
1897 iwl_prph_dump_addr[i].start + 4;
1898 int reg;
1899 __le32 *val;
1900
1901 prph_len += sizeof(*data) + sizeof(*prph) +
1902 num_bytes_in_chunk;
1903
1904 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
1905 (*data)->len = cpu_to_le32(sizeof(*prph) +
1906 num_bytes_in_chunk);
1907 prph = (void *)(*data)->data;
1908 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
1909 val = (void *)prph->data;
1910
1911 for (reg = iwl_prph_dump_addr[i].start;
1912 reg <= iwl_prph_dump_addr[i].end;
1913 reg += 4)
1914 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
1915 reg));
1916 *data = iwl_fw_error_next_data(*data);
1917 }
1918
1919 iwl_trans_release_nic_access(trans, &flags);
1920
1921 return prph_len;
1922 }
1923
1924 #define IWL_CSR_TO_DUMP (0x250)
1925
1926 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
1927 struct iwl_fw_error_dump_data **data)
1928 {
1929 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
1930 __le32 *val;
1931 int i;
1932
1933 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
1934 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
1935 val = (void *)(*data)->data;
1936
1937 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
1938 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
1939
1940 *data = iwl_fw_error_next_data(*data);
1941
1942 return csr_len;
1943 }
1944
1945 static
1946 struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans)
1947 {
1948 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1949 struct iwl_fw_error_dump_data *data;
1950 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
1951 struct iwl_fw_error_dump_txcmd *txcmd;
1952 struct iwl_trans_dump_data *dump_data;
1953 u32 len;
1954 int i, ptr;
1955
1956 /* transport dump header */
1957 len = sizeof(*dump_data);
1958
1959 /* host commands */
1960 len += sizeof(*data) +
1961 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
1962
1963 /* CSR registers */
1964 len += sizeof(*data) + IWL_CSR_TO_DUMP;
1965
1966 /* PRPH registers */
1967 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
1968 /* The range includes both boundaries */
1969 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
1970 iwl_prph_dump_addr[i].start + 4;
1971
1972 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
1973 num_bytes_in_chunk;
1974 }
1975
1976 /* FW monitor */
1977 if (trans_pcie->fw_mon_page)
1978 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
1979 trans_pcie->fw_mon_size;
1980
1981 dump_data = vzalloc(len);
1982 if (!dump_data)
1983 return NULL;
1984
1985 len = 0;
1986 data = (void *)dump_data->data;
1987 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
1988 txcmd = (void *)data->data;
1989 spin_lock_bh(&cmdq->lock);
1990 ptr = cmdq->q.write_ptr;
1991 for (i = 0; i < cmdq->q.n_window; i++) {
1992 u8 idx = get_cmd_index(&cmdq->q, ptr);
1993 u32 caplen, cmdlen;
1994
1995 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
1996 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
1997
1998 if (cmdlen) {
1999 len += sizeof(*txcmd) + caplen;
2000 txcmd->cmdlen = cpu_to_le32(cmdlen);
2001 txcmd->caplen = cpu_to_le32(caplen);
2002 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2003 txcmd = (void *)((u8 *)txcmd->data + caplen);
2004 }
2005
2006 ptr = iwl_queue_dec_wrap(ptr);
2007 }
2008 spin_unlock_bh(&cmdq->lock);
2009
2010 data->len = cpu_to_le32(len);
2011 len += sizeof(*data);
2012 data = iwl_fw_error_next_data(data);
2013
2014 len += iwl_trans_pcie_dump_prph(trans, &data);
2015 len += iwl_trans_pcie_dump_csr(trans, &data);
2016 /* data is already pointing to the next section */
2017
2018 if (trans_pcie->fw_mon_page) {
2019 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2020
2021 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2022 data->len = cpu_to_le32(trans_pcie->fw_mon_size +
2023 sizeof(*fw_mon_data));
2024 fw_mon_data = (void *)data->data;
2025 fw_mon_data->fw_mon_wr_ptr =
2026 cpu_to_le32(iwl_read_prph(trans, MON_BUFF_WRPTR));
2027 fw_mon_data->fw_mon_cycle_cnt =
2028 cpu_to_le32(iwl_read_prph(trans, MON_BUFF_CYCLE_CNT));
2029 fw_mon_data->fw_mon_base_ptr =
2030 cpu_to_le32(iwl_read_prph(trans, MON_BUFF_BASE_ADDR));
2031
2032 /*
2033 * The firmware is now asserted, it won't write anything to
2034 * the buffer. CPU can take ownership to fetch the data.
2035 * The buffer will be handed back to the device before the
2036 * firmware will be restarted.
2037 */
2038 dma_sync_single_for_cpu(trans->dev, trans_pcie->fw_mon_phys,
2039 trans_pcie->fw_mon_size,
2040 DMA_FROM_DEVICE);
2041 memcpy(fw_mon_data->data, page_address(trans_pcie->fw_mon_page),
2042 trans_pcie->fw_mon_size);
2043
2044 len += sizeof(*data) + sizeof(*fw_mon_data) +
2045 trans_pcie->fw_mon_size;
2046 }
2047
2048 dump_data->len = len;
2049
2050 return dump_data;
2051 }
2052
2053 static const struct iwl_trans_ops trans_ops_pcie = {
2054 .start_hw = iwl_trans_pcie_start_hw,
2055 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
2056 .fw_alive = iwl_trans_pcie_fw_alive,
2057 .start_fw = iwl_trans_pcie_start_fw,
2058 .stop_device = iwl_trans_pcie_stop_device,
2059
2060 .d3_suspend = iwl_trans_pcie_d3_suspend,
2061 .d3_resume = iwl_trans_pcie_d3_resume,
2062
2063 .send_cmd = iwl_trans_pcie_send_hcmd,
2064
2065 .tx = iwl_trans_pcie_tx,
2066 .reclaim = iwl_trans_pcie_reclaim,
2067
2068 .txq_disable = iwl_trans_pcie_txq_disable,
2069 .txq_enable = iwl_trans_pcie_txq_enable,
2070
2071 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2072
2073 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2074
2075 .write8 = iwl_trans_pcie_write8,
2076 .write32 = iwl_trans_pcie_write32,
2077 .read32 = iwl_trans_pcie_read32,
2078 .read_prph = iwl_trans_pcie_read_prph,
2079 .write_prph = iwl_trans_pcie_write_prph,
2080 .read_mem = iwl_trans_pcie_read_mem,
2081 .write_mem = iwl_trans_pcie_write_mem,
2082 .configure = iwl_trans_pcie_configure,
2083 .set_pmi = iwl_trans_pcie_set_pmi,
2084 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
2085 .release_nic_access = iwl_trans_pcie_release_nic_access,
2086 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
2087
2088 .dump_data = iwl_trans_pcie_dump_data,
2089 };
2090
2091 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2092 const struct pci_device_id *ent,
2093 const struct iwl_cfg *cfg)
2094 {
2095 struct iwl_trans_pcie *trans_pcie;
2096 struct iwl_trans *trans;
2097 u16 pci_cmd;
2098 int err;
2099
2100 trans = kzalloc(sizeof(struct iwl_trans) +
2101 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2102 if (!trans) {
2103 err = -ENOMEM;
2104 goto out;
2105 }
2106
2107 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2108
2109 trans->ops = &trans_ops_pcie;
2110 trans->cfg = cfg;
2111 trans_lockdep_init(trans);
2112 trans_pcie->trans = trans;
2113 spin_lock_init(&trans_pcie->irq_lock);
2114 spin_lock_init(&trans_pcie->reg_lock);
2115 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2116
2117 err = pci_enable_device(pdev);
2118 if (err)
2119 goto out_no_pci;
2120
2121 if (!cfg->base_params->pcie_l1_allowed) {
2122 /*
2123 * W/A - seems to solve weird behavior. We need to remove this
2124 * if we don't want to stay in L1 all the time. This wastes a
2125 * lot of power.
2126 */
2127 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2128 PCIE_LINK_STATE_L1 |
2129 PCIE_LINK_STATE_CLKPM);
2130 }
2131
2132 pci_set_master(pdev);
2133
2134 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2135 if (!err)
2136 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2137 if (err) {
2138 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2139 if (!err)
2140 err = pci_set_consistent_dma_mask(pdev,
2141 DMA_BIT_MASK(32));
2142 /* both attempts failed: */
2143 if (err) {
2144 dev_err(&pdev->dev, "No suitable DMA available\n");
2145 goto out_pci_disable_device;
2146 }
2147 }
2148
2149 err = pci_request_regions(pdev, DRV_NAME);
2150 if (err) {
2151 dev_err(&pdev->dev, "pci_request_regions failed\n");
2152 goto out_pci_disable_device;
2153 }
2154
2155 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2156 if (!trans_pcie->hw_base) {
2157 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
2158 err = -ENODEV;
2159 goto out_pci_release_regions;
2160 }
2161
2162 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2163 * PCI Tx retries from interfering with C3 CPU state */
2164 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2165
2166 trans->dev = &pdev->dev;
2167 trans_pcie->pci_dev = pdev;
2168 iwl_disable_interrupts(trans);
2169
2170 err = pci_enable_msi(pdev);
2171 if (err) {
2172 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
2173 /* enable rfkill interrupt: hw bug w/a */
2174 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2175 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2176 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2177 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2178 }
2179 }
2180
2181 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2182 /*
2183 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2184 * changed, and now the revision step also includes bit 0-1 (no more
2185 * "dash" value). To keep hw_rev backwards compatible - we'll store it
2186 * in the old format.
2187 */
2188 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
2189 trans->hw_rev = (trans->hw_rev & 0xfff0) |
2190 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
2191
2192 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2193 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2194 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2195
2196 /* Initialize the wait queue for commands */
2197 init_waitqueue_head(&trans_pcie->wait_command_queue);
2198
2199 snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
2200 "iwl_cmd_pool:%s", dev_name(trans->dev));
2201
2202 trans->dev_cmd_headroom = 0;
2203 trans->dev_cmd_pool =
2204 kmem_cache_create(trans->dev_cmd_pool_name,
2205 sizeof(struct iwl_device_cmd)
2206 + trans->dev_cmd_headroom,
2207 sizeof(void *),
2208 SLAB_HWCACHE_ALIGN,
2209 NULL);
2210
2211 if (!trans->dev_cmd_pool) {
2212 err = -ENOMEM;
2213 goto out_pci_disable_msi;
2214 }
2215
2216 if (iwl_pcie_alloc_ict(trans))
2217 goto out_free_cmd_pool;
2218
2219 err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
2220 iwl_pcie_irq_handler,
2221 IRQF_SHARED, DRV_NAME, trans);
2222 if (err) {
2223 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2224 goto out_free_ict;
2225 }
2226
2227 trans_pcie->inta_mask = CSR_INI_SET_MASK;
2228
2229 return trans;
2230
2231 out_free_ict:
2232 iwl_pcie_free_ict(trans);
2233 out_free_cmd_pool:
2234 kmem_cache_destroy(trans->dev_cmd_pool);
2235 out_pci_disable_msi:
2236 pci_disable_msi(pdev);
2237 out_pci_release_regions:
2238 pci_release_regions(pdev);
2239 out_pci_disable_device:
2240 pci_disable_device(pdev);
2241 out_no_pci:
2242 kfree(trans);
2243 out:
2244 return ERR_PTR(err);
2245 }
Linux kernel - Deliverables
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