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iwlwifi: pcie: provide a way to stop configuration if it is forbidden
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / pcie / trans.c
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
23 * USA
24 *
25 * The full GNU General Public License is included in this distribution
26 * in the file called COPYING.
27 *
28 * Contact Information:
29 * Intel Linux Wireless <ilw@linux.intel.com>
30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 *
32 * BSD LICENSE
33 *
34 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
35 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
36 * All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 *
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
47 * distribution.
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *
64 *****************************************************************************/
65 #include <linux/pci.h>
66 #include <linux/pci-aspm.h>
67 #include <linux/interrupt.h>
68 #include <linux/debugfs.h>
69 #include <linux/sched.h>
70 #include <linux/bitops.h>
71 #include <linux/gfp.h>
72 #include <linux/vmalloc.h>
73
74 #include "iwl-drv.h"
75 #include "iwl-trans.h"
76 #include "iwl-csr.h"
77 #include "iwl-prph.h"
78 #include "iwl-scd.h"
79 #include "iwl-agn-hw.h"
80 #include "iwl-fw-error-dump.h"
81 #include "internal.h"
82 #include "iwl-fh.h"
83
84 /* extended range in FW SRAM */
85 #define IWL_FW_MEM_EXTENDED_START 0x40000
86 #define IWL_FW_MEM_EXTENDED_END 0x57FFF
87
88 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
89 {
90 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
91
92 if (!trans_pcie->fw_mon_page)
93 return;
94
95 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
96 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
97 __free_pages(trans_pcie->fw_mon_page,
98 get_order(trans_pcie->fw_mon_size));
99 trans_pcie->fw_mon_page = NULL;
100 trans_pcie->fw_mon_phys = 0;
101 trans_pcie->fw_mon_size = 0;
102 }
103
104 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
105 {
106 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
107 struct page *page = NULL;
108 dma_addr_t phys;
109 u32 size = 0;
110 u8 power;
111
112 if (!max_power) {
113 /* default max_power is maximum */
114 max_power = 26;
115 } else {
116 max_power += 11;
117 }
118
119 if (WARN(max_power > 26,
120 "External buffer size for monitor is too big %d, check the FW TLV\n",
121 max_power))
122 return;
123
124 if (trans_pcie->fw_mon_page) {
125 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
126 trans_pcie->fw_mon_size,
127 DMA_FROM_DEVICE);
128 return;
129 }
130
131 phys = 0;
132 for (power = max_power; power >= 11; power--) {
133 int order;
134
135 size = BIT(power);
136 order = get_order(size);
137 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
138 order);
139 if (!page)
140 continue;
141
142 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
143 DMA_FROM_DEVICE);
144 if (dma_mapping_error(trans->dev, phys)) {
145 __free_pages(page, order);
146 page = NULL;
147 continue;
148 }
149 IWL_INFO(trans,
150 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
151 size, order);
152 break;
153 }
154
155 if (WARN_ON_ONCE(!page))
156 return;
157
158 if (power != max_power)
159 IWL_ERR(trans,
160 "Sorry - debug buffer is only %luK while you requested %luK\n",
161 (unsigned long)BIT(power - 10),
162 (unsigned long)BIT(max_power - 10));
163
164 trans_pcie->fw_mon_page = page;
165 trans_pcie->fw_mon_phys = phys;
166 trans_pcie->fw_mon_size = size;
167 }
168
169 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
170 {
171 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
172 ((reg & 0x0000ffff) | (2 << 28)));
173 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
174 }
175
176 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
177 {
178 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
179 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
180 ((reg & 0x0000ffff) | (3 << 28)));
181 }
182
183 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
184 {
185 if (!trans->cfg->apmg_not_supported)
186 return;
187
188 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
189 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
190 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
191 ~APMG_PS_CTRL_MSK_PWR_SRC);
192 else
193 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
194 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
195 ~APMG_PS_CTRL_MSK_PWR_SRC);
196 }
197
198 /* PCI registers */
199 #define PCI_CFG_RETRY_TIMEOUT 0x041
200
201 static void iwl_pcie_apm_config(struct iwl_trans *trans)
202 {
203 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
204 u16 lctl;
205 u16 cap;
206
207 /*
208 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
209 * Check if BIOS (or OS) enabled L1-ASPM on this device.
210 * If so (likely), disable L0S, so device moves directly L0->L1;
211 * costs negligible amount of power savings.
212 * If not (unlikely), enable L0S, so there is at least some
213 * power savings, even without L1.
214 */
215 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
216 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
217 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
218 else
219 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
220 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
221
222 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
223 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
224 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
225 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
226 trans->ltr_enabled ? "En" : "Dis");
227 }
228
229 /*
230 * Start up NIC's basic functionality after it has been reset
231 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
232 * NOTE: This does not load uCode nor start the embedded processor
233 */
234 static int iwl_pcie_apm_init(struct iwl_trans *trans)
235 {
236 int ret = 0;
237 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
238
239 /*
240 * Use "set_bit" below rather than "write", to preserve any hardware
241 * bits already set by default after reset.
242 */
243
244 /* Disable L0S exit timer (platform NMI Work/Around) */
245 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
246 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
247 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
248
249 /*
250 * Disable L0s without affecting L1;
251 * don't wait for ICH L0s (ICH bug W/A)
252 */
253 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
254 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
255
256 /* Set FH wait threshold to maximum (HW error during stress W/A) */
257 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
258
259 /*
260 * Enable HAP INTA (interrupt from management bus) to
261 * wake device's PCI Express link L1a -> L0s
262 */
263 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
264 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
265
266 iwl_pcie_apm_config(trans);
267
268 /* Configure analog phase-lock-loop before activating to D0A */
269 if (trans->cfg->base_params->pll_cfg_val)
270 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
271 trans->cfg->base_params->pll_cfg_val);
272
273 /*
274 * Set "initialization complete" bit to move adapter from
275 * D0U* --> D0A* (powered-up active) state.
276 */
277 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
278
279 /*
280 * Wait for clock stabilization; once stabilized, access to
281 * device-internal resources is supported, e.g. iwl_write_prph()
282 * and accesses to uCode SRAM.
283 */
284 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
285 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
286 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
287 if (ret < 0) {
288 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
289 goto out;
290 }
291
292 if (trans->cfg->host_interrupt_operation_mode) {
293 /*
294 * This is a bit of an abuse - This is needed for 7260 / 3160
295 * only check host_interrupt_operation_mode even if this is
296 * not related to host_interrupt_operation_mode.
297 *
298 * Enable the oscillator to count wake up time for L1 exit. This
299 * consumes slightly more power (100uA) - but allows to be sure
300 * that we wake up from L1 on time.
301 *
302 * This looks weird: read twice the same register, discard the
303 * value, set a bit, and yet again, read that same register
304 * just to discard the value. But that's the way the hardware
305 * seems to like it.
306 */
307 iwl_read_prph(trans, OSC_CLK);
308 iwl_read_prph(trans, OSC_CLK);
309 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
310 iwl_read_prph(trans, OSC_CLK);
311 iwl_read_prph(trans, OSC_CLK);
312 }
313
314 /*
315 * Enable DMA clock and wait for it to stabilize.
316 *
317 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
318 * bits do not disable clocks. This preserves any hardware
319 * bits already set by default in "CLK_CTRL_REG" after reset.
320 */
321 if (!trans->cfg->apmg_not_supported) {
322 iwl_write_prph(trans, APMG_CLK_EN_REG,
323 APMG_CLK_VAL_DMA_CLK_RQT);
324 udelay(20);
325
326 /* Disable L1-Active */
327 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
328 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
329
330 /* Clear the interrupt in APMG if the NIC is in RFKILL */
331 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
332 APMG_RTC_INT_STT_RFKILL);
333 }
334
335 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
336
337 out:
338 return ret;
339 }
340
341 /*
342 * Enable LP XTAL to avoid HW bug where device may consume much power if
343 * FW is not loaded after device reset. LP XTAL is disabled by default
344 * after device HW reset. Do it only if XTAL is fed by internal source.
345 * Configure device's "persistence" mode to avoid resetting XTAL again when
346 * SHRD_HW_RST occurs in S3.
347 */
348 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
349 {
350 int ret;
351 u32 apmg_gp1_reg;
352 u32 apmg_xtal_cfg_reg;
353 u32 dl_cfg_reg;
354
355 /* Force XTAL ON */
356 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
357 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
358
359 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
360 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
361
362 udelay(10);
363
364 /*
365 * Set "initialization complete" bit to move adapter from
366 * D0U* --> D0A* (powered-up active) state.
367 */
368 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
369
370 /*
371 * Wait for clock stabilization; once stabilized, access to
372 * device-internal resources is possible.
373 */
374 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
375 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
376 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
377 25000);
378 if (WARN_ON(ret < 0)) {
379 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
380 /* Release XTAL ON request */
381 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
382 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
383 return;
384 }
385
386 /*
387 * Clear "disable persistence" to avoid LP XTAL resetting when
388 * SHRD_HW_RST is applied in S3.
389 */
390 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
391 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
392
393 /*
394 * Force APMG XTAL to be active to prevent its disabling by HW
395 * caused by APMG idle state.
396 */
397 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
398 SHR_APMG_XTAL_CFG_REG);
399 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
400 apmg_xtal_cfg_reg |
401 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
402
403 /*
404 * Reset entire device again - do controller reset (results in
405 * SHRD_HW_RST). Turn MAC off before proceeding.
406 */
407 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
408
409 udelay(10);
410
411 /* Enable LP XTAL by indirect access through CSR */
412 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
413 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
414 SHR_APMG_GP1_WF_XTAL_LP_EN |
415 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
416
417 /* Clear delay line clock power up */
418 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
419 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
420 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
421
422 /*
423 * Enable persistence mode to avoid LP XTAL resetting when
424 * SHRD_HW_RST is applied in S3.
425 */
426 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
427 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
428
429 /*
430 * Clear "initialization complete" bit to move adapter from
431 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
432 */
433 iwl_clear_bit(trans, CSR_GP_CNTRL,
434 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
435
436 /* Activates XTAL resources monitor */
437 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
438 CSR_MONITOR_XTAL_RESOURCES);
439
440 /* Release XTAL ON request */
441 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
442 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
443 udelay(10);
444
445 /* Release APMG XTAL */
446 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
447 apmg_xtal_cfg_reg &
448 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
449 }
450
451 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
452 {
453 int ret = 0;
454
455 /* stop device's busmaster DMA activity */
456 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
457
458 ret = iwl_poll_bit(trans, CSR_RESET,
459 CSR_RESET_REG_FLAG_MASTER_DISABLED,
460 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
461 if (ret < 0)
462 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
463
464 IWL_DEBUG_INFO(trans, "stop master\n");
465
466 return ret;
467 }
468
469 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
470 {
471 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
472
473 if (op_mode_leave) {
474 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
475 iwl_pcie_apm_init(trans);
476
477 /* inform ME that we are leaving */
478 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
479 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
480 APMG_PCIDEV_STT_VAL_WAKE_ME);
481 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
482 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
483 CSR_HW_IF_CONFIG_REG_PREPARE |
484 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
485 mdelay(5);
486 }
487
488 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
489
490 /* Stop device's DMA activity */
491 iwl_pcie_apm_stop_master(trans);
492
493 if (trans->cfg->lp_xtal_workaround) {
494 iwl_pcie_apm_lp_xtal_enable(trans);
495 return;
496 }
497
498 /* Reset the entire device */
499 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
500
501 udelay(10);
502
503 /*
504 * Clear "initialization complete" bit to move adapter from
505 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
506 */
507 iwl_clear_bit(trans, CSR_GP_CNTRL,
508 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
509 }
510
511 static int iwl_pcie_nic_init(struct iwl_trans *trans)
512 {
513 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
514
515 /* nic_init */
516 spin_lock(&trans_pcie->irq_lock);
517 iwl_pcie_apm_init(trans);
518
519 spin_unlock(&trans_pcie->irq_lock);
520
521 iwl_pcie_set_pwr(trans, false);
522
523 iwl_op_mode_nic_config(trans->op_mode);
524
525 /* Allocate the RX queue, or reset if it is already allocated */
526 iwl_pcie_rx_init(trans);
527
528 /* Allocate or reset and init all Tx and Command queues */
529 if (iwl_pcie_tx_init(trans))
530 return -ENOMEM;
531
532 if (trans->cfg->base_params->shadow_reg_enable) {
533 /* enable shadow regs in HW */
534 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
535 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
536 }
537
538 return 0;
539 }
540
541 #define HW_READY_TIMEOUT (50)
542
543 /* Note: returns poll_bit return value, which is >= 0 if success */
544 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
545 {
546 int ret;
547
548 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
549 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
550
551 /* See if we got it */
552 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
553 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
554 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
555 HW_READY_TIMEOUT);
556
557 if (ret >= 0)
558 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
559
560 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
561 return ret;
562 }
563
564 /* Note: returns standard 0/-ERROR code */
565 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
566 {
567 int ret;
568 int t = 0;
569 int iter;
570
571 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
572
573 ret = iwl_pcie_set_hw_ready(trans);
574 /* If the card is ready, exit 0 */
575 if (ret >= 0)
576 return 0;
577
578 for (iter = 0; iter < 10; iter++) {
579 /* If HW is not ready, prepare the conditions to check again */
580 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
581 CSR_HW_IF_CONFIG_REG_PREPARE);
582
583 do {
584 ret = iwl_pcie_set_hw_ready(trans);
585 if (ret >= 0)
586 return 0;
587
588 usleep_range(200, 1000);
589 t += 200;
590 } while (t < 150000);
591 msleep(25);
592 }
593
594 IWL_ERR(trans, "Couldn't prepare the card\n");
595
596 return ret;
597 }
598
599 /*
600 * ucode
601 */
602 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
603 dma_addr_t phy_addr, u32 byte_cnt)
604 {
605 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
606 int ret;
607
608 trans_pcie->ucode_write_complete = false;
609
610 iwl_write_direct32(trans,
611 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
612 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
613
614 iwl_write_direct32(trans,
615 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
616 dst_addr);
617
618 iwl_write_direct32(trans,
619 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
620 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
621
622 iwl_write_direct32(trans,
623 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
624 (iwl_get_dma_hi_addr(phy_addr)
625 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
626
627 iwl_write_direct32(trans,
628 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
629 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
630 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
631 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
632
633 iwl_write_direct32(trans,
634 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
635 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
636 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
637 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
638
639 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
640 trans_pcie->ucode_write_complete, 5 * HZ);
641 if (!ret) {
642 IWL_ERR(trans, "Failed to load firmware chunk!\n");
643 return -ETIMEDOUT;
644 }
645
646 return 0;
647 }
648
649 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
650 const struct fw_desc *section)
651 {
652 u8 *v_addr;
653 dma_addr_t p_addr;
654 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
655 int ret = 0;
656
657 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
658 section_num);
659
660 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
661 GFP_KERNEL | __GFP_NOWARN);
662 if (!v_addr) {
663 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
664 chunk_sz = PAGE_SIZE;
665 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
666 &p_addr, GFP_KERNEL);
667 if (!v_addr)
668 return -ENOMEM;
669 }
670
671 for (offset = 0; offset < section->len; offset += chunk_sz) {
672 u32 copy_size, dst_addr;
673 bool extended_addr = false;
674
675 copy_size = min_t(u32, chunk_sz, section->len - offset);
676 dst_addr = section->offset + offset;
677
678 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
679 dst_addr <= IWL_FW_MEM_EXTENDED_END)
680 extended_addr = true;
681
682 if (extended_addr)
683 iwl_set_bits_prph(trans, LMPM_CHICK,
684 LMPM_CHICK_EXTENDED_ADDR_SPACE);
685
686 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
687 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
688 copy_size);
689
690 if (extended_addr)
691 iwl_clear_bits_prph(trans, LMPM_CHICK,
692 LMPM_CHICK_EXTENDED_ADDR_SPACE);
693
694 if (ret) {
695 IWL_ERR(trans,
696 "Could not load the [%d] uCode section\n",
697 section_num);
698 break;
699 }
700 }
701
702 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
703 return ret;
704 }
705
706 /*
707 * Driver Takes the ownership on secure machine before FW load
708 * and prevent race with the BT load.
709 * W/A for ROM bug. (should be remove in the next Si step)
710 */
711 static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
712 {
713 u32 val, loop = 1000;
714
715 /*
716 * Check the RSA semaphore is accessible.
717 * If the HW isn't locked and the rsa semaphore isn't accessible,
718 * we are in trouble.
719 */
720 val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
721 if (val & (BIT(1) | BIT(17))) {
722 IWL_INFO(trans,
723 "can't access the RSA semaphore it is write protected\n");
724 return 0;
725 }
726
727 /* take ownership on the AUX IF */
728 iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
729 iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
730
731 do {
732 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
733 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
734 if (val == 0x1) {
735 iwl_write_prph(trans, RSA_ENABLE, 0);
736 return 0;
737 }
738
739 udelay(10);
740 loop--;
741 } while (loop > 0);
742
743 IWL_ERR(trans, "Failed to take ownership on secure machine\n");
744 return -EIO;
745 }
746
747 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
748 const struct fw_img *image,
749 int cpu,
750 int *first_ucode_section)
751 {
752 int shift_param;
753 int i, ret = 0, sec_num = 0x1;
754 u32 val, last_read_idx = 0;
755
756 if (cpu == 1) {
757 shift_param = 0;
758 *first_ucode_section = 0;
759 } else {
760 shift_param = 16;
761 (*first_ucode_section)++;
762 }
763
764 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
765 last_read_idx = i;
766
767 if (!image->sec[i].data ||
768 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
769 IWL_DEBUG_FW(trans,
770 "Break since Data not valid or Empty section, sec = %d\n",
771 i);
772 break;
773 }
774
775 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
776 if (ret)
777 return ret;
778
779 /* Notify the ucode of the loaded section number and status */
780 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
781 val = val | (sec_num << shift_param);
782 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
783 sec_num = (sec_num << 1) | 0x1;
784 }
785
786 *first_ucode_section = last_read_idx;
787
788 if (cpu == 1)
789 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
790 else
791 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
792
793 return 0;
794 }
795
796 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
797 const struct fw_img *image,
798 int cpu,
799 int *first_ucode_section)
800 {
801 int shift_param;
802 int i, ret = 0;
803 u32 last_read_idx = 0;
804
805 if (cpu == 1) {
806 shift_param = 0;
807 *first_ucode_section = 0;
808 } else {
809 shift_param = 16;
810 (*first_ucode_section)++;
811 }
812
813 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
814 last_read_idx = i;
815
816 if (!image->sec[i].data ||
817 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
818 IWL_DEBUG_FW(trans,
819 "Break since Data not valid or Empty section, sec = %d\n",
820 i);
821 break;
822 }
823
824 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
825 if (ret)
826 return ret;
827 }
828
829 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
830 iwl_set_bits_prph(trans,
831 CSR_UCODE_LOAD_STATUS_ADDR,
832 (LMPM_CPU_UCODE_LOADING_COMPLETED |
833 LMPM_CPU_HDRS_LOADING_COMPLETED |
834 LMPM_CPU_UCODE_LOADING_STARTED) <<
835 shift_param);
836
837 *first_ucode_section = last_read_idx;
838
839 return 0;
840 }
841
842 static void iwl_pcie_apply_destination(struct iwl_trans *trans)
843 {
844 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
845 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
846 int i;
847
848 if (dest->version)
849 IWL_ERR(trans,
850 "DBG DEST version is %d - expect issues\n",
851 dest->version);
852
853 IWL_INFO(trans, "Applying debug destination %s\n",
854 get_fw_dbg_mode_string(dest->monitor_mode));
855
856 if (dest->monitor_mode == EXTERNAL_MODE)
857 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
858 else
859 IWL_WARN(trans, "PCI should have external buffer debug\n");
860
861 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
862 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
863 u32 val = le32_to_cpu(dest->reg_ops[i].val);
864
865 switch (dest->reg_ops[i].op) {
866 case CSR_ASSIGN:
867 iwl_write32(trans, addr, val);
868 break;
869 case CSR_SETBIT:
870 iwl_set_bit(trans, addr, BIT(val));
871 break;
872 case CSR_CLEARBIT:
873 iwl_clear_bit(trans, addr, BIT(val));
874 break;
875 case PRPH_ASSIGN:
876 iwl_write_prph(trans, addr, val);
877 break;
878 case PRPH_SETBIT:
879 iwl_set_bits_prph(trans, addr, BIT(val));
880 break;
881 case PRPH_CLEARBIT:
882 iwl_clear_bits_prph(trans, addr, BIT(val));
883 break;
884 case PRPH_BLOCKBIT:
885 if (iwl_read_prph(trans, addr) & BIT(val)) {
886 IWL_ERR(trans,
887 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
888 val, addr);
889 goto monitor;
890 }
891 break;
892 default:
893 IWL_ERR(trans, "FW debug - unknown OP %d\n",
894 dest->reg_ops[i].op);
895 break;
896 }
897 }
898
899 monitor:
900 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
901 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
902 trans_pcie->fw_mon_phys >> dest->base_shift);
903 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
904 (trans_pcie->fw_mon_phys +
905 trans_pcie->fw_mon_size) >> dest->end_shift);
906 }
907 }
908
909 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
910 const struct fw_img *image)
911 {
912 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
913 int ret = 0;
914 int first_ucode_section;
915
916 IWL_DEBUG_FW(trans, "working with %s CPU\n",
917 image->is_dual_cpus ? "Dual" : "Single");
918
919 /* load to FW the binary non secured sections of CPU1 */
920 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
921 if (ret)
922 return ret;
923
924 if (image->is_dual_cpus) {
925 /* set CPU2 header address */
926 iwl_write_prph(trans,
927 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
928 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
929
930 /* load to FW the binary sections of CPU2 */
931 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
932 &first_ucode_section);
933 if (ret)
934 return ret;
935 }
936
937 /* supported for 7000 only for the moment */
938 if (iwlwifi_mod_params.fw_monitor &&
939 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
940 iwl_pcie_alloc_fw_monitor(trans, 0);
941
942 if (trans_pcie->fw_mon_size) {
943 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
944 trans_pcie->fw_mon_phys >> 4);
945 iwl_write_prph(trans, MON_BUFF_END_ADDR,
946 (trans_pcie->fw_mon_phys +
947 trans_pcie->fw_mon_size) >> 4);
948 }
949 } else if (trans->dbg_dest_tlv) {
950 iwl_pcie_apply_destination(trans);
951 }
952
953 /* release CPU reset */
954 iwl_write32(trans, CSR_RESET, 0);
955
956 return 0;
957 }
958
959 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
960 const struct fw_img *image)
961 {
962 int ret = 0;
963 int first_ucode_section;
964
965 IWL_DEBUG_FW(trans, "working with %s CPU\n",
966 image->is_dual_cpus ? "Dual" : "Single");
967
968 if (trans->dbg_dest_tlv)
969 iwl_pcie_apply_destination(trans);
970
971 /* TODO: remove in the next Si step */
972 ret = iwl_pcie_rsa_race_bug_wa(trans);
973 if (ret)
974 return ret;
975
976 /* configure the ucode to be ready to get the secured image */
977 /* release CPU reset */
978 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
979
980 /* load to FW the binary Secured sections of CPU1 */
981 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
982 &first_ucode_section);
983 if (ret)
984 return ret;
985
986 /* load to FW the binary sections of CPU2 */
987 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
988 &first_ucode_section);
989 }
990
991 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
992 const struct fw_img *fw, bool run_in_rfkill)
993 {
994 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
995 bool hw_rfkill;
996 int ret;
997
998 mutex_lock(&trans_pcie->mutex);
999
1000 /* Someone called stop_device, don't try to start_fw */
1001 if (trans_pcie->is_down) {
1002 IWL_WARN(trans,
1003 "Can't start_fw since the HW hasn't been started\n");
1004 ret = EIO;
1005 goto out;
1006 }
1007
1008 /* This may fail if AMT took ownership of the device */
1009 if (iwl_pcie_prepare_card_hw(trans)) {
1010 IWL_WARN(trans, "Exit HW not ready\n");
1011 ret = -EIO;
1012 goto out;
1013 }
1014
1015 iwl_enable_rfkill_int(trans);
1016
1017 /* If platform's RF_KILL switch is NOT set to KILL */
1018 hw_rfkill = iwl_is_rfkill_set(trans);
1019 if (hw_rfkill)
1020 set_bit(STATUS_RFKILL, &trans->status);
1021 else
1022 clear_bit(STATUS_RFKILL, &trans->status);
1023 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1024 if (hw_rfkill && !run_in_rfkill) {
1025 ret = -ERFKILL;
1026 goto out;
1027 }
1028
1029 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1030
1031 ret = iwl_pcie_nic_init(trans);
1032 if (ret) {
1033 IWL_ERR(trans, "Unable to init nic\n");
1034 goto out;
1035 }
1036
1037 /* make sure rfkill handshake bits are cleared */
1038 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1039 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1040 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1041
1042 /* clear (again), then enable host interrupts */
1043 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1044 iwl_enable_interrupts(trans);
1045
1046 /* really make sure rfkill handshake bits are cleared */
1047 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1048 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1049
1050 /* Load the given image to the HW */
1051 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1052 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1053 else
1054 ret = iwl_pcie_load_given_ucode(trans, fw);
1055
1056 out:
1057 mutex_unlock(&trans_pcie->mutex);
1058 return ret;
1059 }
1060
1061 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1062 {
1063 iwl_pcie_reset_ict(trans);
1064 iwl_pcie_tx_start(trans, scd_addr);
1065 }
1066
1067 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1068 {
1069 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1070 bool hw_rfkill, was_hw_rfkill;
1071
1072 lockdep_assert_held(&trans_pcie->mutex);
1073
1074 if (trans_pcie->is_down)
1075 return;
1076
1077 trans_pcie->is_down = true;
1078
1079 was_hw_rfkill = iwl_is_rfkill_set(trans);
1080
1081 /* tell the device to stop sending interrupts */
1082 spin_lock(&trans_pcie->irq_lock);
1083 iwl_disable_interrupts(trans);
1084 spin_unlock(&trans_pcie->irq_lock);
1085
1086 /* device going down, Stop using ICT table */
1087 iwl_pcie_disable_ict(trans);
1088
1089 /*
1090 * If a HW restart happens during firmware loading,
1091 * then the firmware loading might call this function
1092 * and later it might be called again due to the
1093 * restart. So don't process again if the device is
1094 * already dead.
1095 */
1096 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1097 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
1098 iwl_pcie_tx_stop(trans);
1099 iwl_pcie_rx_stop(trans);
1100
1101 /* Power-down device's busmaster DMA clocks */
1102 if (!trans->cfg->apmg_not_supported) {
1103 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1104 APMG_CLK_VAL_DMA_CLK_RQT);
1105 udelay(5);
1106 }
1107 }
1108
1109 /* Make sure (redundant) we've released our request to stay awake */
1110 iwl_clear_bit(trans, CSR_GP_CNTRL,
1111 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1112
1113 /* Stop the device, and put it in low power state */
1114 iwl_pcie_apm_stop(trans, false);
1115
1116 /* stop and reset the on-board processor */
1117 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1118 udelay(20);
1119
1120 /*
1121 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1122 * This is a bug in certain verions of the hardware.
1123 * Certain devices also keep sending HW RF kill interrupt all
1124 * the time, unless the interrupt is ACKed even if the interrupt
1125 * should be masked. Re-ACK all the interrupts here.
1126 */
1127 spin_lock(&trans_pcie->irq_lock);
1128 iwl_disable_interrupts(trans);
1129 spin_unlock(&trans_pcie->irq_lock);
1130
1131
1132 /* clear all status bits */
1133 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1134 clear_bit(STATUS_INT_ENABLED, &trans->status);
1135 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1136 clear_bit(STATUS_RFKILL, &trans->status);
1137
1138 /*
1139 * Even if we stop the HW, we still want the RF kill
1140 * interrupt
1141 */
1142 iwl_enable_rfkill_int(trans);
1143
1144 /*
1145 * Check again since the RF kill state may have changed while
1146 * all the interrupts were disabled, in this case we couldn't
1147 * receive the RF kill interrupt and update the state in the
1148 * op_mode.
1149 * Don't call the op_mode if the rkfill state hasn't changed.
1150 * This allows the op_mode to call stop_device from the rfkill
1151 * notification without endless recursion. Under very rare
1152 * circumstances, we might have a small recursion if the rfkill
1153 * state changed exactly now while we were called from stop_device.
1154 * This is very unlikely but can happen and is supported.
1155 */
1156 hw_rfkill = iwl_is_rfkill_set(trans);
1157 if (hw_rfkill)
1158 set_bit(STATUS_RFKILL, &trans->status);
1159 else
1160 clear_bit(STATUS_RFKILL, &trans->status);
1161 if (hw_rfkill != was_hw_rfkill)
1162 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1163
1164 /* re-take ownership to prevent other users from stealing the deivce */
1165 iwl_pcie_prepare_card_hw(trans);
1166 }
1167
1168 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1169 {
1170 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1171
1172 mutex_lock(&trans_pcie->mutex);
1173 _iwl_trans_pcie_stop_device(trans, low_power);
1174 mutex_unlock(&trans_pcie->mutex);
1175 }
1176
1177 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1178 {
1179 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1180 IWL_TRANS_GET_PCIE_TRANS(trans);
1181
1182 lockdep_assert_held(&trans_pcie->mutex);
1183
1184 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1185 _iwl_trans_pcie_stop_device(trans, true);
1186 }
1187
1188 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
1189 {
1190 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1191
1192 iwl_disable_interrupts(trans);
1193
1194 /*
1195 * in testing mode, the host stays awake and the
1196 * hardware won't be reset (not even partially)
1197 */
1198 if (test)
1199 return;
1200
1201 iwl_pcie_disable_ict(trans);
1202
1203 synchronize_irq(trans_pcie->pci_dev->irq);
1204
1205 iwl_clear_bit(trans, CSR_GP_CNTRL,
1206 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1207 iwl_clear_bit(trans, CSR_GP_CNTRL,
1208 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1209
1210 /*
1211 * reset TX queues -- some of their registers reset during S3
1212 * so if we don't reset everything here the D3 image would try
1213 * to execute some invalid memory upon resume
1214 */
1215 iwl_trans_pcie_tx_reset(trans);
1216
1217 iwl_pcie_set_pwr(trans, true);
1218 }
1219
1220 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1221 enum iwl_d3_status *status,
1222 bool test)
1223 {
1224 u32 val;
1225 int ret;
1226
1227 if (test) {
1228 iwl_enable_interrupts(trans);
1229 *status = IWL_D3_STATUS_ALIVE;
1230 return 0;
1231 }
1232
1233 /*
1234 * Also enables interrupts - none will happen as the device doesn't
1235 * know we're waking it up, only when the opmode actually tells it
1236 * after this call.
1237 */
1238 iwl_pcie_reset_ict(trans);
1239
1240 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1241 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1242
1243 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1244 udelay(2);
1245
1246 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1247 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1248 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1249 25000);
1250 if (ret < 0) {
1251 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1252 return ret;
1253 }
1254
1255 iwl_pcie_set_pwr(trans, false);
1256
1257 iwl_trans_pcie_tx_reset(trans);
1258
1259 ret = iwl_pcie_rx_init(trans);
1260 if (ret) {
1261 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
1262 return ret;
1263 }
1264
1265 val = iwl_read32(trans, CSR_RESET);
1266 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1267 *status = IWL_D3_STATUS_RESET;
1268 else
1269 *status = IWL_D3_STATUS_ALIVE;
1270
1271 return 0;
1272 }
1273
1274 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1275 {
1276 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1277 bool hw_rfkill;
1278 int err;
1279
1280 lockdep_assert_held(&trans_pcie->mutex);
1281
1282 err = iwl_pcie_prepare_card_hw(trans);
1283 if (err) {
1284 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1285 return err;
1286 }
1287
1288 /* Reset the entire device */
1289 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1290
1291 usleep_range(10, 15);
1292
1293 iwl_pcie_apm_init(trans);
1294
1295 /* From now on, the op_mode will be kept updated about RF kill state */
1296 iwl_enable_rfkill_int(trans);
1297
1298 /* Set is_down to false here so that...*/
1299 trans_pcie->is_down = false;
1300
1301 hw_rfkill = iwl_is_rfkill_set(trans);
1302 if (hw_rfkill)
1303 set_bit(STATUS_RFKILL, &trans->status);
1304 else
1305 clear_bit(STATUS_RFKILL, &trans->status);
1306 /* ... rfkill can call stop_device and set it false if needed */
1307 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1308
1309 return 0;
1310 }
1311
1312 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1313 {
1314 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1315 int ret;
1316
1317 mutex_lock(&trans_pcie->mutex);
1318 ret = _iwl_trans_pcie_start_hw(trans, low_power);
1319 mutex_unlock(&trans_pcie->mutex);
1320
1321 return ret;
1322 }
1323
1324 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1325 {
1326 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1327
1328 mutex_lock(&trans_pcie->mutex);
1329
1330 /* disable interrupts - don't enable HW RF kill interrupt */
1331 spin_lock(&trans_pcie->irq_lock);
1332 iwl_disable_interrupts(trans);
1333 spin_unlock(&trans_pcie->irq_lock);
1334
1335 iwl_pcie_apm_stop(trans, true);
1336
1337 spin_lock(&trans_pcie->irq_lock);
1338 iwl_disable_interrupts(trans);
1339 spin_unlock(&trans_pcie->irq_lock);
1340
1341 iwl_pcie_disable_ict(trans);
1342
1343 mutex_unlock(&trans_pcie->mutex);
1344
1345 synchronize_irq(trans_pcie->pci_dev->irq);
1346 }
1347
1348 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1349 {
1350 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1351 }
1352
1353 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1354 {
1355 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1356 }
1357
1358 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1359 {
1360 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1361 }
1362
1363 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1364 {
1365 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1366 ((reg & 0x000FFFFF) | (3 << 24)));
1367 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1368 }
1369
1370 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1371 u32 val)
1372 {
1373 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1374 ((addr & 0x000FFFFF) | (3 << 24)));
1375 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1376 }
1377
1378 static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1379 {
1380 WARN_ON(1);
1381 return 0;
1382 }
1383
1384 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1385 const struct iwl_trans_config *trans_cfg)
1386 {
1387 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1388
1389 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1390 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1391 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1392 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1393 trans_pcie->n_no_reclaim_cmds = 0;
1394 else
1395 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1396 if (trans_pcie->n_no_reclaim_cmds)
1397 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1398 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1399
1400 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1401 if (trans_pcie->rx_buf_size_8k)
1402 trans_pcie->rx_page_order = get_order(8 * 1024);
1403 else
1404 trans_pcie->rx_page_order = get_order(4 * 1024);
1405
1406 trans_pcie->wide_cmd_header = trans_cfg->wide_cmd_header;
1407 trans_pcie->command_names = trans_cfg->command_names;
1408 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1409 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1410
1411 /* init ref_count to 1 (should be cleared when ucode is loaded) */
1412 trans_pcie->ref_count = 1;
1413
1414 /* Initialize NAPI here - it should be before registering to mac80211
1415 * in the opmode but after the HW struct is allocated.
1416 * As this function may be called again in some corner cases don't
1417 * do anything if NAPI was already initialized.
1418 */
1419 if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1420 init_dummy_netdev(&trans_pcie->napi_dev);
1421 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1422 &trans_pcie->napi_dev,
1423 iwl_pcie_dummy_napi_poll, 64);
1424 }
1425 }
1426
1427 void iwl_trans_pcie_free(struct iwl_trans *trans)
1428 {
1429 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1430
1431 synchronize_irq(trans_pcie->pci_dev->irq);
1432
1433 iwl_pcie_tx_free(trans);
1434 iwl_pcie_rx_free(trans);
1435
1436 free_irq(trans_pcie->pci_dev->irq, trans);
1437 iwl_pcie_free_ict(trans);
1438
1439 pci_disable_msi(trans_pcie->pci_dev);
1440 iounmap(trans_pcie->hw_base);
1441 pci_release_regions(trans_pcie->pci_dev);
1442 pci_disable_device(trans_pcie->pci_dev);
1443
1444 if (trans_pcie->napi.poll)
1445 netif_napi_del(&trans_pcie->napi);
1446
1447 iwl_pcie_free_fw_monitor(trans);
1448
1449 iwl_trans_free(trans);
1450 }
1451
1452 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1453 {
1454 if (state)
1455 set_bit(STATUS_TPOWER_PMI, &trans->status);
1456 else
1457 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1458 }
1459
1460 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1461 unsigned long *flags)
1462 {
1463 int ret;
1464 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1465
1466 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1467
1468 if (trans_pcie->cmd_hold_nic_awake)
1469 goto out;
1470
1471 /* this bit wakes up the NIC */
1472 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1473 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1474 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1475 udelay(2);
1476
1477 /*
1478 * These bits say the device is running, and should keep running for
1479 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1480 * but they do not indicate that embedded SRAM is restored yet;
1481 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1482 * to/from host DRAM when sleeping/waking for power-saving.
1483 * Each direction takes approximately 1/4 millisecond; with this
1484 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1485 * series of register accesses are expected (e.g. reading Event Log),
1486 * to keep device from sleeping.
1487 *
1488 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1489 * SRAM is okay/restored. We don't check that here because this call
1490 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1491 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1492 *
1493 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1494 * and do not save/restore SRAM when power cycling.
1495 */
1496 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1497 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1498 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1499 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1500 if (unlikely(ret < 0)) {
1501 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1502 if (!silent) {
1503 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1504 WARN_ONCE(1,
1505 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1506 val);
1507 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1508 return false;
1509 }
1510 }
1511
1512 out:
1513 /*
1514 * Fool sparse by faking we release the lock - sparse will
1515 * track nic_access anyway.
1516 */
1517 __release(&trans_pcie->reg_lock);
1518 return true;
1519 }
1520
1521 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1522 unsigned long *flags)
1523 {
1524 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1525
1526 lockdep_assert_held(&trans_pcie->reg_lock);
1527
1528 /*
1529 * Fool sparse by faking we acquiring the lock - sparse will
1530 * track nic_access anyway.
1531 */
1532 __acquire(&trans_pcie->reg_lock);
1533
1534 if (trans_pcie->cmd_hold_nic_awake)
1535 goto out;
1536
1537 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1538 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1539 /*
1540 * Above we read the CSR_GP_CNTRL register, which will flush
1541 * any previous writes, but we need the write that clears the
1542 * MAC_ACCESS_REQ bit to be performed before any other writes
1543 * scheduled on different CPUs (after we drop reg_lock).
1544 */
1545 mmiowb();
1546 out:
1547 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1548 }
1549
1550 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1551 void *buf, int dwords)
1552 {
1553 unsigned long flags;
1554 int offs, ret = 0;
1555 u32 *vals = buf;
1556
1557 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1558 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1559 for (offs = 0; offs < dwords; offs++)
1560 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1561 iwl_trans_release_nic_access(trans, &flags);
1562 } else {
1563 ret = -EBUSY;
1564 }
1565 return ret;
1566 }
1567
1568 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1569 const void *buf, int dwords)
1570 {
1571 unsigned long flags;
1572 int offs, ret = 0;
1573 const u32 *vals = buf;
1574
1575 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1576 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1577 for (offs = 0; offs < dwords; offs++)
1578 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1579 vals ? vals[offs] : 0);
1580 iwl_trans_release_nic_access(trans, &flags);
1581 } else {
1582 ret = -EBUSY;
1583 }
1584 return ret;
1585 }
1586
1587 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1588 unsigned long txqs,
1589 bool freeze)
1590 {
1591 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1592 int queue;
1593
1594 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1595 struct iwl_txq *txq = &trans_pcie->txq[queue];
1596 unsigned long now;
1597
1598 spin_lock_bh(&txq->lock);
1599
1600 now = jiffies;
1601
1602 if (txq->frozen == freeze)
1603 goto next_queue;
1604
1605 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1606 freeze ? "Freezing" : "Waking", queue);
1607
1608 txq->frozen = freeze;
1609
1610 if (txq->q.read_ptr == txq->q.write_ptr)
1611 goto next_queue;
1612
1613 if (freeze) {
1614 if (unlikely(time_after(now,
1615 txq->stuck_timer.expires))) {
1616 /*
1617 * The timer should have fired, maybe it is
1618 * spinning right now on the lock.
1619 */
1620 goto next_queue;
1621 }
1622 /* remember how long until the timer fires */
1623 txq->frozen_expiry_remainder =
1624 txq->stuck_timer.expires - now;
1625 del_timer(&txq->stuck_timer);
1626 goto next_queue;
1627 }
1628
1629 /*
1630 * Wake a non-empty queue -> arm timer with the
1631 * remainder before it froze
1632 */
1633 mod_timer(&txq->stuck_timer,
1634 now + txq->frozen_expiry_remainder);
1635
1636 next_queue:
1637 spin_unlock_bh(&txq->lock);
1638 }
1639 }
1640
1641 #define IWL_FLUSH_WAIT_MS 2000
1642
1643 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1644 {
1645 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1646 struct iwl_txq *txq;
1647 struct iwl_queue *q;
1648 int cnt;
1649 unsigned long now = jiffies;
1650 u32 scd_sram_addr;
1651 u8 buf[16];
1652 int ret = 0;
1653
1654 /* waiting for all the tx frames complete might take a while */
1655 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1656 u8 wr_ptr;
1657
1658 if (cnt == trans_pcie->cmd_queue)
1659 continue;
1660 if (!test_bit(cnt, trans_pcie->queue_used))
1661 continue;
1662 if (!(BIT(cnt) & txq_bm))
1663 continue;
1664
1665 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1666 txq = &trans_pcie->txq[cnt];
1667 q = &txq->q;
1668 wr_ptr = ACCESS_ONCE(q->write_ptr);
1669
1670 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1671 !time_after(jiffies,
1672 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1673 u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1674
1675 if (WARN_ONCE(wr_ptr != write_ptr,
1676 "WR pointer moved while flushing %d -> %d\n",
1677 wr_ptr, write_ptr))
1678 return -ETIMEDOUT;
1679 msleep(1);
1680 }
1681
1682 if (q->read_ptr != q->write_ptr) {
1683 IWL_ERR(trans,
1684 "fail to flush all tx fifo queues Q %d\n", cnt);
1685 ret = -ETIMEDOUT;
1686 break;
1687 }
1688 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1689 }
1690
1691 if (!ret)
1692 return 0;
1693
1694 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1695 txq->q.read_ptr, txq->q.write_ptr);
1696
1697 scd_sram_addr = trans_pcie->scd_base_addr +
1698 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1699 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1700
1701 iwl_print_hex_error(trans, buf, sizeof(buf));
1702
1703 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1704 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1705 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1706
1707 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1708 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1709 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1710 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1711 u32 tbl_dw =
1712 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1713 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1714
1715 if (cnt & 0x1)
1716 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1717 else
1718 tbl_dw = tbl_dw & 0x0000FFFF;
1719
1720 IWL_ERR(trans,
1721 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1722 cnt, active ? "" : "in", fifo, tbl_dw,
1723 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1724 (TFD_QUEUE_SIZE_MAX - 1),
1725 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1726 }
1727
1728 return ret;
1729 }
1730
1731 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1732 u32 mask, u32 value)
1733 {
1734 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1735 unsigned long flags;
1736
1737 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1738 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1739 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1740 }
1741
1742 void iwl_trans_pcie_ref(struct iwl_trans *trans)
1743 {
1744 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1745 unsigned long flags;
1746
1747 if (iwlwifi_mod_params.d0i3_disable)
1748 return;
1749
1750 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1751 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1752 trans_pcie->ref_count++;
1753 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1754 }
1755
1756 void iwl_trans_pcie_unref(struct iwl_trans *trans)
1757 {
1758 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1759 unsigned long flags;
1760
1761 if (iwlwifi_mod_params.d0i3_disable)
1762 return;
1763
1764 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1765 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1766 if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) {
1767 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1768 return;
1769 }
1770 trans_pcie->ref_count--;
1771 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1772 }
1773
1774 static const char *get_csr_string(int cmd)
1775 {
1776 #define IWL_CMD(x) case x: return #x
1777 switch (cmd) {
1778 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1779 IWL_CMD(CSR_INT_COALESCING);
1780 IWL_CMD(CSR_INT);
1781 IWL_CMD(CSR_INT_MASK);
1782 IWL_CMD(CSR_FH_INT_STATUS);
1783 IWL_CMD(CSR_GPIO_IN);
1784 IWL_CMD(CSR_RESET);
1785 IWL_CMD(CSR_GP_CNTRL);
1786 IWL_CMD(CSR_HW_REV);
1787 IWL_CMD(CSR_EEPROM_REG);
1788 IWL_CMD(CSR_EEPROM_GP);
1789 IWL_CMD(CSR_OTP_GP_REG);
1790 IWL_CMD(CSR_GIO_REG);
1791 IWL_CMD(CSR_GP_UCODE_REG);
1792 IWL_CMD(CSR_GP_DRIVER_REG);
1793 IWL_CMD(CSR_UCODE_DRV_GP1);
1794 IWL_CMD(CSR_UCODE_DRV_GP2);
1795 IWL_CMD(CSR_LED_REG);
1796 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1797 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1798 IWL_CMD(CSR_ANA_PLL_CFG);
1799 IWL_CMD(CSR_HW_REV_WA_REG);
1800 IWL_CMD(CSR_MONITOR_STATUS_REG);
1801 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1802 default:
1803 return "UNKNOWN";
1804 }
1805 #undef IWL_CMD
1806 }
1807
1808 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1809 {
1810 int i;
1811 static const u32 csr_tbl[] = {
1812 CSR_HW_IF_CONFIG_REG,
1813 CSR_INT_COALESCING,
1814 CSR_INT,
1815 CSR_INT_MASK,
1816 CSR_FH_INT_STATUS,
1817 CSR_GPIO_IN,
1818 CSR_RESET,
1819 CSR_GP_CNTRL,
1820 CSR_HW_REV,
1821 CSR_EEPROM_REG,
1822 CSR_EEPROM_GP,
1823 CSR_OTP_GP_REG,
1824 CSR_GIO_REG,
1825 CSR_GP_UCODE_REG,
1826 CSR_GP_DRIVER_REG,
1827 CSR_UCODE_DRV_GP1,
1828 CSR_UCODE_DRV_GP2,
1829 CSR_LED_REG,
1830 CSR_DRAM_INT_TBL_REG,
1831 CSR_GIO_CHICKEN_BITS,
1832 CSR_ANA_PLL_CFG,
1833 CSR_MONITOR_STATUS_REG,
1834 CSR_HW_REV_WA_REG,
1835 CSR_DBG_HPET_MEM_REG
1836 };
1837 IWL_ERR(trans, "CSR values:\n");
1838 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1839 "CSR_INT_PERIODIC_REG)\n");
1840 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1841 IWL_ERR(trans, " %25s: 0X%08x\n",
1842 get_csr_string(csr_tbl[i]),
1843 iwl_read32(trans, csr_tbl[i]));
1844 }
1845 }
1846
1847 #ifdef CONFIG_IWLWIFI_DEBUGFS
1848 /* create and remove of files */
1849 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1850 if (!debugfs_create_file(#name, mode, parent, trans, \
1851 &iwl_dbgfs_##name##_ops)) \
1852 goto err; \
1853 } while (0)
1854
1855 /* file operation */
1856 #define DEBUGFS_READ_FILE_OPS(name) \
1857 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1858 .read = iwl_dbgfs_##name##_read, \
1859 .open = simple_open, \
1860 .llseek = generic_file_llseek, \
1861 };
1862
1863 #define DEBUGFS_WRITE_FILE_OPS(name) \
1864 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1865 .write = iwl_dbgfs_##name##_write, \
1866 .open = simple_open, \
1867 .llseek = generic_file_llseek, \
1868 };
1869
1870 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1871 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1872 .write = iwl_dbgfs_##name##_write, \
1873 .read = iwl_dbgfs_##name##_read, \
1874 .open = simple_open, \
1875 .llseek = generic_file_llseek, \
1876 };
1877
1878 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1879 char __user *user_buf,
1880 size_t count, loff_t *ppos)
1881 {
1882 struct iwl_trans *trans = file->private_data;
1883 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1884 struct iwl_txq *txq;
1885 struct iwl_queue *q;
1886 char *buf;
1887 int pos = 0;
1888 int cnt;
1889 int ret;
1890 size_t bufsz;
1891
1892 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
1893
1894 if (!trans_pcie->txq)
1895 return -EAGAIN;
1896
1897 buf = kzalloc(bufsz, GFP_KERNEL);
1898 if (!buf)
1899 return -ENOMEM;
1900
1901 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1902 txq = &trans_pcie->txq[cnt];
1903 q = &txq->q;
1904 pos += scnprintf(buf + pos, bufsz - pos,
1905 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
1906 cnt, q->read_ptr, q->write_ptr,
1907 !!test_bit(cnt, trans_pcie->queue_used),
1908 !!test_bit(cnt, trans_pcie->queue_stopped),
1909 txq->need_update, txq->frozen,
1910 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
1911 }
1912 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1913 kfree(buf);
1914 return ret;
1915 }
1916
1917 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1918 char __user *user_buf,
1919 size_t count, loff_t *ppos)
1920 {
1921 struct iwl_trans *trans = file->private_data;
1922 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1923 struct iwl_rxq *rxq = &trans_pcie->rxq;
1924 char buf[256];
1925 int pos = 0;
1926 const size_t bufsz = sizeof(buf);
1927
1928 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1929 rxq->read);
1930 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1931 rxq->write);
1932 pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
1933 rxq->write_actual);
1934 pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
1935 rxq->need_update);
1936 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1937 rxq->free_count);
1938 if (rxq->rb_stts) {
1939 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1940 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1941 } else {
1942 pos += scnprintf(buf + pos, bufsz - pos,
1943 "closed_rb_num: Not Allocated\n");
1944 }
1945 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1946 }
1947
1948 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1949 char __user *user_buf,
1950 size_t count, loff_t *ppos)
1951 {
1952 struct iwl_trans *trans = file->private_data;
1953 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1954 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1955
1956 int pos = 0;
1957 char *buf;
1958 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1959 ssize_t ret;
1960
1961 buf = kzalloc(bufsz, GFP_KERNEL);
1962 if (!buf)
1963 return -ENOMEM;
1964
1965 pos += scnprintf(buf + pos, bufsz - pos,
1966 "Interrupt Statistics Report:\n");
1967
1968 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1969 isr_stats->hw);
1970 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1971 isr_stats->sw);
1972 if (isr_stats->sw || isr_stats->hw) {
1973 pos += scnprintf(buf + pos, bufsz - pos,
1974 "\tLast Restarting Code: 0x%X\n",
1975 isr_stats->err_code);
1976 }
1977 #ifdef CONFIG_IWLWIFI_DEBUG
1978 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1979 isr_stats->sch);
1980 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1981 isr_stats->alive);
1982 #endif
1983 pos += scnprintf(buf + pos, bufsz - pos,
1984 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1985
1986 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1987 isr_stats->ctkill);
1988
1989 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1990 isr_stats->wakeup);
1991
1992 pos += scnprintf(buf + pos, bufsz - pos,
1993 "Rx command responses:\t\t %u\n", isr_stats->rx);
1994
1995 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1996 isr_stats->tx);
1997
1998 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1999 isr_stats->unhandled);
2000
2001 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2002 kfree(buf);
2003 return ret;
2004 }
2005
2006 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2007 const char __user *user_buf,
2008 size_t count, loff_t *ppos)
2009 {
2010 struct iwl_trans *trans = file->private_data;
2011 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2012 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2013
2014 char buf[8];
2015 int buf_size;
2016 u32 reset_flag;
2017
2018 memset(buf, 0, sizeof(buf));
2019 buf_size = min(count, sizeof(buf) - 1);
2020 if (copy_from_user(buf, user_buf, buf_size))
2021 return -EFAULT;
2022 if (sscanf(buf, "%x", &reset_flag) != 1)
2023 return -EFAULT;
2024 if (reset_flag == 0)
2025 memset(isr_stats, 0, sizeof(*isr_stats));
2026
2027 return count;
2028 }
2029
2030 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2031 const char __user *user_buf,
2032 size_t count, loff_t *ppos)
2033 {
2034 struct iwl_trans *trans = file->private_data;
2035 char buf[8];
2036 int buf_size;
2037 int csr;
2038
2039 memset(buf, 0, sizeof(buf));
2040 buf_size = min(count, sizeof(buf) - 1);
2041 if (copy_from_user(buf, user_buf, buf_size))
2042 return -EFAULT;
2043 if (sscanf(buf, "%d", &csr) != 1)
2044 return -EFAULT;
2045
2046 iwl_pcie_dump_csr(trans);
2047
2048 return count;
2049 }
2050
2051 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2052 char __user *user_buf,
2053 size_t count, loff_t *ppos)
2054 {
2055 struct iwl_trans *trans = file->private_data;
2056 char *buf = NULL;
2057 ssize_t ret;
2058
2059 ret = iwl_dump_fh(trans, &buf);
2060 if (ret < 0)
2061 return ret;
2062 if (!buf)
2063 return -EINVAL;
2064 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2065 kfree(buf);
2066 return ret;
2067 }
2068
2069 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2070 DEBUGFS_READ_FILE_OPS(fh_reg);
2071 DEBUGFS_READ_FILE_OPS(rx_queue);
2072 DEBUGFS_READ_FILE_OPS(tx_queue);
2073 DEBUGFS_WRITE_FILE_OPS(csr);
2074
2075 /*
2076 * Create the debugfs files and directories
2077 *
2078 */
2079 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2080 struct dentry *dir)
2081 {
2082 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2083 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2084 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2085 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2086 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2087 return 0;
2088
2089 err:
2090 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2091 return -ENOMEM;
2092 }
2093 #else
2094 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2095 struct dentry *dir)
2096 {
2097 return 0;
2098 }
2099 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2100
2101 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
2102 {
2103 u32 cmdlen = 0;
2104 int i;
2105
2106 for (i = 0; i < IWL_NUM_OF_TBS; i++)
2107 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
2108
2109 return cmdlen;
2110 }
2111
2112 static const struct {
2113 u32 start, end;
2114 } iwl_prph_dump_addr[] = {
2115 { .start = 0x00a00000, .end = 0x00a00000 },
2116 { .start = 0x00a0000c, .end = 0x00a00024 },
2117 { .start = 0x00a0002c, .end = 0x00a0003c },
2118 { .start = 0x00a00410, .end = 0x00a00418 },
2119 { .start = 0x00a00420, .end = 0x00a00420 },
2120 { .start = 0x00a00428, .end = 0x00a00428 },
2121 { .start = 0x00a00430, .end = 0x00a0043c },
2122 { .start = 0x00a00444, .end = 0x00a00444 },
2123 { .start = 0x00a004c0, .end = 0x00a004cc },
2124 { .start = 0x00a004d8, .end = 0x00a004d8 },
2125 { .start = 0x00a004e0, .end = 0x00a004f0 },
2126 { .start = 0x00a00840, .end = 0x00a00840 },
2127 { .start = 0x00a00850, .end = 0x00a00858 },
2128 { .start = 0x00a01004, .end = 0x00a01008 },
2129 { .start = 0x00a01010, .end = 0x00a01010 },
2130 { .start = 0x00a01018, .end = 0x00a01018 },
2131 { .start = 0x00a01024, .end = 0x00a01024 },
2132 { .start = 0x00a0102c, .end = 0x00a01034 },
2133 { .start = 0x00a0103c, .end = 0x00a01040 },
2134 { .start = 0x00a01048, .end = 0x00a01094 },
2135 { .start = 0x00a01c00, .end = 0x00a01c20 },
2136 { .start = 0x00a01c58, .end = 0x00a01c58 },
2137 { .start = 0x00a01c7c, .end = 0x00a01c7c },
2138 { .start = 0x00a01c28, .end = 0x00a01c54 },
2139 { .start = 0x00a01c5c, .end = 0x00a01c5c },
2140 { .start = 0x00a01c60, .end = 0x00a01cdc },
2141 { .start = 0x00a01ce0, .end = 0x00a01d0c },
2142 { .start = 0x00a01d18, .end = 0x00a01d20 },
2143 { .start = 0x00a01d2c, .end = 0x00a01d30 },
2144 { .start = 0x00a01d40, .end = 0x00a01d5c },
2145 { .start = 0x00a01d80, .end = 0x00a01d80 },
2146 { .start = 0x00a01d98, .end = 0x00a01d9c },
2147 { .start = 0x00a01da8, .end = 0x00a01da8 },
2148 { .start = 0x00a01db8, .end = 0x00a01df4 },
2149 { .start = 0x00a01dc0, .end = 0x00a01dfc },
2150 { .start = 0x00a01e00, .end = 0x00a01e2c },
2151 { .start = 0x00a01e40, .end = 0x00a01e60 },
2152 { .start = 0x00a01e68, .end = 0x00a01e6c },
2153 { .start = 0x00a01e74, .end = 0x00a01e74 },
2154 { .start = 0x00a01e84, .end = 0x00a01e90 },
2155 { .start = 0x00a01e9c, .end = 0x00a01ec4 },
2156 { .start = 0x00a01ed0, .end = 0x00a01ee0 },
2157 { .start = 0x00a01f00, .end = 0x00a01f1c },
2158 { .start = 0x00a01f44, .end = 0x00a01ffc },
2159 { .start = 0x00a02000, .end = 0x00a02048 },
2160 { .start = 0x00a02068, .end = 0x00a020f0 },
2161 { .start = 0x00a02100, .end = 0x00a02118 },
2162 { .start = 0x00a02140, .end = 0x00a0214c },
2163 { .start = 0x00a02168, .end = 0x00a0218c },
2164 { .start = 0x00a021c0, .end = 0x00a021c0 },
2165 { .start = 0x00a02400, .end = 0x00a02410 },
2166 { .start = 0x00a02418, .end = 0x00a02420 },
2167 { .start = 0x00a02428, .end = 0x00a0242c },
2168 { .start = 0x00a02434, .end = 0x00a02434 },
2169 { .start = 0x00a02440, .end = 0x00a02460 },
2170 { .start = 0x00a02468, .end = 0x00a024b0 },
2171 { .start = 0x00a024c8, .end = 0x00a024cc },
2172 { .start = 0x00a02500, .end = 0x00a02504 },
2173 { .start = 0x00a0250c, .end = 0x00a02510 },
2174 { .start = 0x00a02540, .end = 0x00a02554 },
2175 { .start = 0x00a02580, .end = 0x00a025f4 },
2176 { .start = 0x00a02600, .end = 0x00a0260c },
2177 { .start = 0x00a02648, .end = 0x00a02650 },
2178 { .start = 0x00a02680, .end = 0x00a02680 },
2179 { .start = 0x00a026c0, .end = 0x00a026d0 },
2180 { .start = 0x00a02700, .end = 0x00a0270c },
2181 { .start = 0x00a02804, .end = 0x00a02804 },
2182 { .start = 0x00a02818, .end = 0x00a0281c },
2183 { .start = 0x00a02c00, .end = 0x00a02db4 },
2184 { .start = 0x00a02df4, .end = 0x00a02fb0 },
2185 { .start = 0x00a03000, .end = 0x00a03014 },
2186 { .start = 0x00a0301c, .end = 0x00a0302c },
2187 { .start = 0x00a03034, .end = 0x00a03038 },
2188 { .start = 0x00a03040, .end = 0x00a03048 },
2189 { .start = 0x00a03060, .end = 0x00a03068 },
2190 { .start = 0x00a03070, .end = 0x00a03074 },
2191 { .start = 0x00a0307c, .end = 0x00a0307c },
2192 { .start = 0x00a03080, .end = 0x00a03084 },
2193 { .start = 0x00a0308c, .end = 0x00a03090 },
2194 { .start = 0x00a03098, .end = 0x00a03098 },
2195 { .start = 0x00a030a0, .end = 0x00a030a0 },
2196 { .start = 0x00a030a8, .end = 0x00a030b4 },
2197 { .start = 0x00a030bc, .end = 0x00a030bc },
2198 { .start = 0x00a030c0, .end = 0x00a0312c },
2199 { .start = 0x00a03c00, .end = 0x00a03c5c },
2200 { .start = 0x00a04400, .end = 0x00a04454 },
2201 { .start = 0x00a04460, .end = 0x00a04474 },
2202 { .start = 0x00a044c0, .end = 0x00a044ec },
2203 { .start = 0x00a04500, .end = 0x00a04504 },
2204 { .start = 0x00a04510, .end = 0x00a04538 },
2205 { .start = 0x00a04540, .end = 0x00a04548 },
2206 { .start = 0x00a04560, .end = 0x00a0457c },
2207 { .start = 0x00a04590, .end = 0x00a04598 },
2208 { .start = 0x00a045c0, .end = 0x00a045f4 },
2209 };
2210
2211 static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
2212 struct iwl_fw_error_dump_data **data)
2213 {
2214 struct iwl_fw_error_dump_prph *prph;
2215 unsigned long flags;
2216 u32 prph_len = 0, i;
2217
2218 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2219 return 0;
2220
2221 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2222 /* The range includes both boundaries */
2223 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2224 iwl_prph_dump_addr[i].start + 4;
2225 int reg;
2226 __le32 *val;
2227
2228 prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
2229
2230 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
2231 (*data)->len = cpu_to_le32(sizeof(*prph) +
2232 num_bytes_in_chunk);
2233 prph = (void *)(*data)->data;
2234 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
2235 val = (void *)prph->data;
2236
2237 for (reg = iwl_prph_dump_addr[i].start;
2238 reg <= iwl_prph_dump_addr[i].end;
2239 reg += 4)
2240 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2241 reg));
2242 *data = iwl_fw_error_next_data(*data);
2243 }
2244
2245 iwl_trans_release_nic_access(trans, &flags);
2246
2247 return prph_len;
2248 }
2249
2250 #define IWL_CSR_TO_DUMP (0x250)
2251
2252 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2253 struct iwl_fw_error_dump_data **data)
2254 {
2255 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2256 __le32 *val;
2257 int i;
2258
2259 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2260 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2261 val = (void *)(*data)->data;
2262
2263 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2264 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2265
2266 *data = iwl_fw_error_next_data(*data);
2267
2268 return csr_len;
2269 }
2270
2271 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2272 struct iwl_fw_error_dump_data **data)
2273 {
2274 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2275 unsigned long flags;
2276 __le32 *val;
2277 int i;
2278
2279 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2280 return 0;
2281
2282 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2283 (*data)->len = cpu_to_le32(fh_regs_len);
2284 val = (void *)(*data)->data;
2285
2286 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2287 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2288
2289 iwl_trans_release_nic_access(trans, &flags);
2290
2291 *data = iwl_fw_error_next_data(*data);
2292
2293 return sizeof(**data) + fh_regs_len;
2294 }
2295
2296 static u32
2297 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2298 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2299 u32 monitor_len)
2300 {
2301 u32 buf_size_in_dwords = (monitor_len >> 2);
2302 u32 *buffer = (u32 *)fw_mon_data->data;
2303 unsigned long flags;
2304 u32 i;
2305
2306 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2307 return 0;
2308
2309 __iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2310 for (i = 0; i < buf_size_in_dwords; i++)
2311 buffer[i] = __iwl_read_prph(trans, MON_DMARB_RD_DATA_ADDR);
2312 __iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2313
2314 iwl_trans_release_nic_access(trans, &flags);
2315
2316 return monitor_len;
2317 }
2318
2319 static
2320 struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans)
2321 {
2322 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2323 struct iwl_fw_error_dump_data *data;
2324 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2325 struct iwl_fw_error_dump_txcmd *txcmd;
2326 struct iwl_trans_dump_data *dump_data;
2327 u32 len;
2328 u32 monitor_len;
2329 int i, ptr;
2330
2331 /* transport dump header */
2332 len = sizeof(*dump_data);
2333
2334 /* host commands */
2335 len += sizeof(*data) +
2336 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2337
2338 /* CSR registers */
2339 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2340
2341 /* PRPH registers */
2342 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2343 /* The range includes both boundaries */
2344 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2345 iwl_prph_dump_addr[i].start + 4;
2346
2347 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
2348 num_bytes_in_chunk;
2349 }
2350
2351 /* FH registers */
2352 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2353
2354 /* FW monitor */
2355 if (trans_pcie->fw_mon_page) {
2356 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2357 trans_pcie->fw_mon_size;
2358 monitor_len = trans_pcie->fw_mon_size;
2359 } else if (trans->dbg_dest_tlv) {
2360 u32 base, end;
2361
2362 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2363 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2364
2365 base = iwl_read_prph(trans, base) <<
2366 trans->dbg_dest_tlv->base_shift;
2367 end = iwl_read_prph(trans, end) <<
2368 trans->dbg_dest_tlv->end_shift;
2369
2370 /* Make "end" point to the actual end */
2371 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2372 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
2373 end += (1 << trans->dbg_dest_tlv->end_shift);
2374 monitor_len = end - base;
2375 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2376 monitor_len;
2377 } else {
2378 monitor_len = 0;
2379 }
2380
2381 dump_data = vzalloc(len);
2382 if (!dump_data)
2383 return NULL;
2384
2385 len = 0;
2386 data = (void *)dump_data->data;
2387 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2388 txcmd = (void *)data->data;
2389 spin_lock_bh(&cmdq->lock);
2390 ptr = cmdq->q.write_ptr;
2391 for (i = 0; i < cmdq->q.n_window; i++) {
2392 u8 idx = get_cmd_index(&cmdq->q, ptr);
2393 u32 caplen, cmdlen;
2394
2395 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2396 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2397
2398 if (cmdlen) {
2399 len += sizeof(*txcmd) + caplen;
2400 txcmd->cmdlen = cpu_to_le32(cmdlen);
2401 txcmd->caplen = cpu_to_le32(caplen);
2402 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2403 txcmd = (void *)((u8 *)txcmd->data + caplen);
2404 }
2405
2406 ptr = iwl_queue_dec_wrap(ptr);
2407 }
2408 spin_unlock_bh(&cmdq->lock);
2409
2410 data->len = cpu_to_le32(len);
2411 len += sizeof(*data);
2412 data = iwl_fw_error_next_data(data);
2413
2414 len += iwl_trans_pcie_dump_prph(trans, &data);
2415 len += iwl_trans_pcie_dump_csr(trans, &data);
2416 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2417 /* data is already pointing to the next section */
2418
2419 if ((trans_pcie->fw_mon_page &&
2420 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2421 trans->dbg_dest_tlv) {
2422 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2423 u32 base, write_ptr, wrap_cnt;
2424
2425 /* If there was a dest TLV - use the values from there */
2426 if (trans->dbg_dest_tlv) {
2427 write_ptr =
2428 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2429 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2430 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2431 } else {
2432 base = MON_BUFF_BASE_ADDR;
2433 write_ptr = MON_BUFF_WRPTR;
2434 wrap_cnt = MON_BUFF_CYCLE_CNT;
2435 }
2436
2437 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2438 fw_mon_data = (void *)data->data;
2439 fw_mon_data->fw_mon_wr_ptr =
2440 cpu_to_le32(iwl_read_prph(trans, write_ptr));
2441 fw_mon_data->fw_mon_cycle_cnt =
2442 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2443 fw_mon_data->fw_mon_base_ptr =
2444 cpu_to_le32(iwl_read_prph(trans, base));
2445
2446 len += sizeof(*data) + sizeof(*fw_mon_data);
2447 if (trans_pcie->fw_mon_page) {
2448 /*
2449 * The firmware is now asserted, it won't write anything
2450 * to the buffer. CPU can take ownership to fetch the
2451 * data. The buffer will be handed back to the device
2452 * before the firmware will be restarted.
2453 */
2454 dma_sync_single_for_cpu(trans->dev,
2455 trans_pcie->fw_mon_phys,
2456 trans_pcie->fw_mon_size,
2457 DMA_FROM_DEVICE);
2458 memcpy(fw_mon_data->data,
2459 page_address(trans_pcie->fw_mon_page),
2460 trans_pcie->fw_mon_size);
2461
2462 monitor_len = trans_pcie->fw_mon_size;
2463 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2464 /*
2465 * Update pointers to reflect actual values after
2466 * shifting
2467 */
2468 base = iwl_read_prph(trans, base) <<
2469 trans->dbg_dest_tlv->base_shift;
2470 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2471 monitor_len / sizeof(u32));
2472 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2473 monitor_len =
2474 iwl_trans_pci_dump_marbh_monitor(trans,
2475 fw_mon_data,
2476 monitor_len);
2477 } else {
2478 /* Didn't match anything - output no monitor data */
2479 monitor_len = 0;
2480 }
2481
2482 len += monitor_len;
2483 data->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2484 }
2485
2486 dump_data->len = len;
2487
2488 return dump_data;
2489 }
2490
2491 static const struct iwl_trans_ops trans_ops_pcie = {
2492 .start_hw = iwl_trans_pcie_start_hw,
2493 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
2494 .fw_alive = iwl_trans_pcie_fw_alive,
2495 .start_fw = iwl_trans_pcie_start_fw,
2496 .stop_device = iwl_trans_pcie_stop_device,
2497
2498 .d3_suspend = iwl_trans_pcie_d3_suspend,
2499 .d3_resume = iwl_trans_pcie_d3_resume,
2500
2501 .send_cmd = iwl_trans_pcie_send_hcmd,
2502
2503 .tx = iwl_trans_pcie_tx,
2504 .reclaim = iwl_trans_pcie_reclaim,
2505
2506 .txq_disable = iwl_trans_pcie_txq_disable,
2507 .txq_enable = iwl_trans_pcie_txq_enable,
2508
2509 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2510
2511 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2512 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
2513
2514 .write8 = iwl_trans_pcie_write8,
2515 .write32 = iwl_trans_pcie_write32,
2516 .read32 = iwl_trans_pcie_read32,
2517 .read_prph = iwl_trans_pcie_read_prph,
2518 .write_prph = iwl_trans_pcie_write_prph,
2519 .read_mem = iwl_trans_pcie_read_mem,
2520 .write_mem = iwl_trans_pcie_write_mem,
2521 .configure = iwl_trans_pcie_configure,
2522 .set_pmi = iwl_trans_pcie_set_pmi,
2523 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
2524 .release_nic_access = iwl_trans_pcie_release_nic_access,
2525 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
2526
2527 .ref = iwl_trans_pcie_ref,
2528 .unref = iwl_trans_pcie_unref,
2529
2530 .dump_data = iwl_trans_pcie_dump_data,
2531 };
2532
2533 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2534 const struct pci_device_id *ent,
2535 const struct iwl_cfg *cfg)
2536 {
2537 struct iwl_trans_pcie *trans_pcie;
2538 struct iwl_trans *trans;
2539 u16 pci_cmd;
2540 int err;
2541
2542 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2543 &pdev->dev, cfg, &trans_ops_pcie, 0);
2544 if (!trans)
2545 return ERR_PTR(-ENOMEM);
2546
2547 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2548
2549 trans_pcie->trans = trans;
2550 spin_lock_init(&trans_pcie->irq_lock);
2551 spin_lock_init(&trans_pcie->reg_lock);
2552 spin_lock_init(&trans_pcie->ref_lock);
2553 mutex_init(&trans_pcie->mutex);
2554 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2555
2556 err = pci_enable_device(pdev);
2557 if (err)
2558 goto out_no_pci;
2559
2560 if (!cfg->base_params->pcie_l1_allowed) {
2561 /*
2562 * W/A - seems to solve weird behavior. We need to remove this
2563 * if we don't want to stay in L1 all the time. This wastes a
2564 * lot of power.
2565 */
2566 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2567 PCIE_LINK_STATE_L1 |
2568 PCIE_LINK_STATE_CLKPM);
2569 }
2570
2571 pci_set_master(pdev);
2572
2573 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2574 if (!err)
2575 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2576 if (err) {
2577 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2578 if (!err)
2579 err = pci_set_consistent_dma_mask(pdev,
2580 DMA_BIT_MASK(32));
2581 /* both attempts failed: */
2582 if (err) {
2583 dev_err(&pdev->dev, "No suitable DMA available\n");
2584 goto out_pci_disable_device;
2585 }
2586 }
2587
2588 err = pci_request_regions(pdev, DRV_NAME);
2589 if (err) {
2590 dev_err(&pdev->dev, "pci_request_regions failed\n");
2591 goto out_pci_disable_device;
2592 }
2593
2594 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2595 if (!trans_pcie->hw_base) {
2596 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
2597 err = -ENODEV;
2598 goto out_pci_release_regions;
2599 }
2600
2601 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2602 * PCI Tx retries from interfering with C3 CPU state */
2603 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2604
2605 trans->dev = &pdev->dev;
2606 trans_pcie->pci_dev = pdev;
2607 iwl_disable_interrupts(trans);
2608
2609 err = pci_enable_msi(pdev);
2610 if (err) {
2611 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
2612 /* enable rfkill interrupt: hw bug w/a */
2613 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2614 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2615 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2616 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2617 }
2618 }
2619
2620 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2621 /*
2622 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2623 * changed, and now the revision step also includes bit 0-1 (no more
2624 * "dash" value). To keep hw_rev backwards compatible - we'll store it
2625 * in the old format.
2626 */
2627 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
2628 unsigned long flags;
2629 int ret;
2630
2631 trans->hw_rev = (trans->hw_rev & 0xfff0) |
2632 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
2633
2634 /*
2635 * in-order to recognize C step driver should read chip version
2636 * id located at the AUX bus MISC address space.
2637 */
2638 iwl_set_bit(trans, CSR_GP_CNTRL,
2639 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
2640 udelay(2);
2641
2642 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2643 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2644 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2645 25000);
2646 if (ret < 0) {
2647 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
2648 goto out_pci_disable_msi;
2649 }
2650
2651 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
2652 u32 hw_step;
2653
2654 hw_step = __iwl_read_prph(trans, WFPM_CTRL_REG);
2655 hw_step |= ENABLE_WFPM;
2656 __iwl_write_prph(trans, WFPM_CTRL_REG, hw_step);
2657 hw_step = __iwl_read_prph(trans, AUX_MISC_REG);
2658 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
2659 if (hw_step == 0x3)
2660 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
2661 (SILICON_C_STEP << 2);
2662 iwl_trans_release_nic_access(trans, &flags);
2663 }
2664 }
2665
2666 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2667 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2668 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2669
2670 /* Initialize the wait queue for commands */
2671 init_waitqueue_head(&trans_pcie->wait_command_queue);
2672
2673 if (iwl_pcie_alloc_ict(trans))
2674 goto out_pci_disable_msi;
2675
2676 err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
2677 iwl_pcie_irq_handler,
2678 IRQF_SHARED, DRV_NAME, trans);
2679 if (err) {
2680 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2681 goto out_free_ict;
2682 }
2683
2684 trans_pcie->inta_mask = CSR_INI_SET_MASK;
2685 trans->d0i3_mode = IWL_D0I3_MODE_ON_SUSPEND;
2686
2687 return trans;
2688
2689 out_free_ict:
2690 iwl_pcie_free_ict(trans);
2691 out_pci_disable_msi:
2692 pci_disable_msi(pdev);
2693 out_pci_release_regions:
2694 pci_release_regions(pdev);
2695 out_pci_disable_device:
2696 pci_disable_device(pdev);
2697 out_no_pci:
2698 iwl_trans_free(trans);
2699 return ERR_PTR(err);
2700 }
Linux kernel - Deliverables
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