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Merge branch 'for-john' of git://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi...
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / pcie / trans.c
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63 #include <linux/pci.h>
64 #include <linux/pci-aspm.h>
65 #include <linux/interrupt.h>
66 #include <linux/debugfs.h>
67 #include <linux/sched.h>
68 #include <linux/bitops.h>
69 #include <linux/gfp.h>
70
71 #include "iwl-drv.h"
72 #include "iwl-trans.h"
73 #include "iwl-csr.h"
74 #include "iwl-prph.h"
75 #include "iwl-agn-hw.h"
76 #include "internal.h"
77
78 static void iwl_pcie_set_pwr_vmain(struct iwl_trans *trans)
79 {
80 /*
81 * (for documentation purposes)
82 * to set power to V_AUX, do:
83
84 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
85 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
86 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
87 ~APMG_PS_CTRL_MSK_PWR_SRC);
88 */
89
90 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
91 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
92 ~APMG_PS_CTRL_MSK_PWR_SRC);
93 }
94
95 /* PCI registers */
96 #define PCI_CFG_RETRY_TIMEOUT 0x041
97 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
98 #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
99
100 static void iwl_pcie_apm_config(struct iwl_trans *trans)
101 {
102 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
103 u16 lctl;
104
105 /*
106 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
107 * Check if BIOS (or OS) enabled L1-ASPM on this device.
108 * If so (likely), disable L0S, so device moves directly L0->L1;
109 * costs negligible amount of power savings.
110 * If not (unlikely), enable L0S, so there is at least some
111 * power savings, even without L1.
112 */
113 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
114
115 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
116 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
117 /* L1-ASPM enabled; disable(!) L0S */
118 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
119 dev_info(trans->dev, "L1 Enabled; Disabling L0S\n");
120 } else {
121 /* L1-ASPM disabled; enable(!) L0S */
122 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
123 dev_info(trans->dev, "L1 Disabled; Enabling L0S\n");
124 }
125 trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
126 }
127
128 /*
129 * Start up NIC's basic functionality after it has been reset
130 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
131 * NOTE: This does not load uCode nor start the embedded processor
132 */
133 static int iwl_pcie_apm_init(struct iwl_trans *trans)
134 {
135 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
136 int ret = 0;
137 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
138
139 /*
140 * Use "set_bit" below rather than "write", to preserve any hardware
141 * bits already set by default after reset.
142 */
143
144 /* Disable L0S exit timer (platform NMI Work/Around) */
145 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
146 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
147
148 /*
149 * Disable L0s without affecting L1;
150 * don't wait for ICH L0s (ICH bug W/A)
151 */
152 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
153 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
154
155 /* Set FH wait threshold to maximum (HW error during stress W/A) */
156 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
157
158 /*
159 * Enable HAP INTA (interrupt from management bus) to
160 * wake device's PCI Express link L1a -> L0s
161 */
162 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
163 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
164
165 iwl_pcie_apm_config(trans);
166
167 /* Configure analog phase-lock-loop before activating to D0A */
168 if (trans->cfg->base_params->pll_cfg_val)
169 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
170 trans->cfg->base_params->pll_cfg_val);
171
172 /*
173 * Set "initialization complete" bit to move adapter from
174 * D0U* --> D0A* (powered-up active) state.
175 */
176 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
177
178 /*
179 * Wait for clock stabilization; once stabilized, access to
180 * device-internal resources is supported, e.g. iwl_write_prph()
181 * and accesses to uCode SRAM.
182 */
183 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
184 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
185 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
186 if (ret < 0) {
187 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
188 goto out;
189 }
190
191 /*
192 * Enable DMA clock and wait for it to stabilize.
193 *
194 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
195 * do not disable clocks. This preserves any hardware bits already
196 * set by default in "CLK_CTRL_REG" after reset.
197 */
198 iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
199 udelay(20);
200
201 /* Disable L1-Active */
202 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
203 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
204
205 set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
206
207 out:
208 return ret;
209 }
210
211 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
212 {
213 int ret = 0;
214
215 /* stop device's busmaster DMA activity */
216 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
217
218 ret = iwl_poll_bit(trans, CSR_RESET,
219 CSR_RESET_REG_FLAG_MASTER_DISABLED,
220 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
221 if (ret)
222 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
223
224 IWL_DEBUG_INFO(trans, "stop master\n");
225
226 return ret;
227 }
228
229 static void iwl_pcie_apm_stop(struct iwl_trans *trans)
230 {
231 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
232 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
233
234 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
235
236 /* Stop device's DMA activity */
237 iwl_pcie_apm_stop_master(trans);
238
239 /* Reset the entire device */
240 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
241
242 udelay(10);
243
244 /*
245 * Clear "initialization complete" bit to move adapter from
246 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
247 */
248 iwl_clear_bit(trans, CSR_GP_CNTRL,
249 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
250 }
251
252 static int iwl_pcie_nic_init(struct iwl_trans *trans)
253 {
254 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
255 unsigned long flags;
256
257 /* nic_init */
258 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
259 iwl_pcie_apm_init(trans);
260
261 /* Set interrupt coalescing calibration timer to default (512 usecs) */
262 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
263
264 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
265
266 iwl_pcie_set_pwr_vmain(trans);
267
268 iwl_op_mode_nic_config(trans->op_mode);
269
270 /* Allocate the RX queue, or reset if it is already allocated */
271 iwl_pcie_rx_init(trans);
272
273 /* Allocate or reset and init all Tx and Command queues */
274 if (iwl_pcie_tx_init(trans))
275 return -ENOMEM;
276
277 if (trans->cfg->base_params->shadow_reg_enable) {
278 /* enable shadow regs in HW */
279 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
280 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
281 }
282
283 return 0;
284 }
285
286 #define HW_READY_TIMEOUT (50)
287
288 /* Note: returns poll_bit return value, which is >= 0 if success */
289 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
290 {
291 int ret;
292
293 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
294 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
295
296 /* See if we got it */
297 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
298 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
299 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
300 HW_READY_TIMEOUT);
301
302 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
303 return ret;
304 }
305
306 /* Note: returns standard 0/-ERROR code */
307 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
308 {
309 int ret;
310 int t = 0;
311
312 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
313
314 ret = iwl_pcie_set_hw_ready(trans);
315 /* If the card is ready, exit 0 */
316 if (ret >= 0)
317 return 0;
318
319 /* If HW is not ready, prepare the conditions to check again */
320 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
321 CSR_HW_IF_CONFIG_REG_PREPARE);
322
323 do {
324 ret = iwl_pcie_set_hw_ready(trans);
325 if (ret >= 0)
326 return 0;
327
328 usleep_range(200, 1000);
329 t += 200;
330 } while (t < 150000);
331
332 return ret;
333 }
334
335 /*
336 * ucode
337 */
338 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
339 dma_addr_t phy_addr, u32 byte_cnt)
340 {
341 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
342 int ret;
343
344 trans_pcie->ucode_write_complete = false;
345
346 iwl_write_direct32(trans,
347 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
348 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
349
350 iwl_write_direct32(trans,
351 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
352 dst_addr);
353
354 iwl_write_direct32(trans,
355 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
356 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
357
358 iwl_write_direct32(trans,
359 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
360 (iwl_get_dma_hi_addr(phy_addr)
361 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
362
363 iwl_write_direct32(trans,
364 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
365 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
366 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
367 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
368
369 iwl_write_direct32(trans,
370 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
371 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
372 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
373 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
374
375 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
376 trans_pcie->ucode_write_complete, 5 * HZ);
377 if (!ret) {
378 IWL_ERR(trans, "Failed to load firmware chunk!\n");
379 return -ETIMEDOUT;
380 }
381
382 return 0;
383 }
384
385 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
386 const struct fw_desc *section)
387 {
388 u8 *v_addr;
389 dma_addr_t p_addr;
390 u32 offset;
391 int ret = 0;
392
393 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
394 section_num);
395
396 v_addr = dma_alloc_coherent(trans->dev, PAGE_SIZE, &p_addr, GFP_KERNEL);
397 if (!v_addr)
398 return -ENOMEM;
399
400 for (offset = 0; offset < section->len; offset += PAGE_SIZE) {
401 u32 copy_size;
402
403 copy_size = min_t(u32, PAGE_SIZE, section->len - offset);
404
405 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
406 ret = iwl_pcie_load_firmware_chunk(trans,
407 section->offset + offset,
408 p_addr, copy_size);
409 if (ret) {
410 IWL_ERR(trans,
411 "Could not load the [%d] uCode section\n",
412 section_num);
413 break;
414 }
415 }
416
417 dma_free_coherent(trans->dev, PAGE_SIZE, v_addr, p_addr);
418 return ret;
419 }
420
421 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
422 const struct fw_img *image)
423 {
424 int i, ret = 0;
425
426 for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
427 if (!image->sec[i].data)
428 break;
429
430 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
431 if (ret)
432 return ret;
433 }
434
435 /* Remove all resets to allow NIC to operate */
436 iwl_write32(trans, CSR_RESET, 0);
437
438 return 0;
439 }
440
441 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
442 const struct fw_img *fw)
443 {
444 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
445 int ret;
446 bool hw_rfkill;
447
448 /* This may fail if AMT took ownership of the device */
449 if (iwl_pcie_prepare_card_hw(trans)) {
450 IWL_WARN(trans, "Exit HW not ready\n");
451 return -EIO;
452 }
453
454 clear_bit(STATUS_FW_ERROR, &trans_pcie->status);
455
456 iwl_enable_rfkill_int(trans);
457
458 /* If platform's RF_KILL switch is NOT set to KILL */
459 hw_rfkill = iwl_is_rfkill_set(trans);
460 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
461 if (hw_rfkill)
462 return -ERFKILL;
463
464 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
465
466 ret = iwl_pcie_nic_init(trans);
467 if (ret) {
468 IWL_ERR(trans, "Unable to init nic\n");
469 return ret;
470 }
471
472 /* make sure rfkill handshake bits are cleared */
473 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
474 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
475 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
476
477 /* clear (again), then enable host interrupts */
478 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
479 iwl_enable_interrupts(trans);
480
481 /* really make sure rfkill handshake bits are cleared */
482 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
483 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
484
485 /* Load the given image to the HW */
486 return iwl_pcie_load_given_ucode(trans, fw);
487 }
488
489 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
490 {
491 iwl_pcie_reset_ict(trans);
492 iwl_pcie_tx_start(trans, scd_addr);
493 }
494
495 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
496 {
497 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
498 unsigned long flags;
499
500 /* tell the device to stop sending interrupts */
501 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
502 iwl_disable_interrupts(trans);
503 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
504
505 /* device going down, Stop using ICT table */
506 iwl_pcie_disable_ict(trans);
507
508 /*
509 * If a HW restart happens during firmware loading,
510 * then the firmware loading might call this function
511 * and later it might be called again due to the
512 * restart. So don't process again if the device is
513 * already dead.
514 */
515 if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
516 iwl_pcie_tx_stop(trans);
517 iwl_pcie_rx_stop(trans);
518
519 /* Power-down device's busmaster DMA clocks */
520 iwl_write_prph(trans, APMG_CLK_DIS_REG,
521 APMG_CLK_VAL_DMA_CLK_RQT);
522 udelay(5);
523 }
524
525 /* Make sure (redundant) we've released our request to stay awake */
526 iwl_clear_bit(trans, CSR_GP_CNTRL,
527 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
528
529 /* Stop the device, and put it in low power state */
530 iwl_pcie_apm_stop(trans);
531
532 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
533 * Clean again the interrupt here
534 */
535 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
536 iwl_disable_interrupts(trans);
537 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
538
539 iwl_enable_rfkill_int(trans);
540
541 /* wait to make sure we flush pending tasklet*/
542 synchronize_irq(trans_pcie->irq);
543 tasklet_kill(&trans_pcie->irq_tasklet);
544
545 cancel_work_sync(&trans_pcie->rx_replenish);
546
547 /* stop and reset the on-board processor */
548 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
549
550 /* clear all status bits */
551 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
552 clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
553 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
554 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
555 clear_bit(STATUS_RFKILL, &trans_pcie->status);
556 }
557
558 static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
559 {
560 /* let the ucode operate on its own */
561 iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
562 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
563
564 iwl_disable_interrupts(trans);
565 iwl_clear_bit(trans, CSR_GP_CNTRL,
566 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
567 }
568
569 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
570 {
571 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
572 int err;
573 bool hw_rfkill;
574
575 trans_pcie->inta_mask = CSR_INI_SET_MASK;
576
577 if (!trans_pcie->irq_requested) {
578 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
579 iwl_pcie_tasklet, (unsigned long)trans);
580
581 iwl_pcie_alloc_ict(trans);
582
583 err = request_irq(trans_pcie->irq, iwl_pcie_isr_ict,
584 IRQF_SHARED, DRV_NAME, trans);
585 if (err) {
586 IWL_ERR(trans, "Error allocating IRQ %d\n",
587 trans_pcie->irq);
588 goto error;
589 }
590
591 trans_pcie->irq_requested = true;
592 }
593
594 err = iwl_pcie_prepare_card_hw(trans);
595 if (err) {
596 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
597 goto err_free_irq;
598 }
599
600 iwl_pcie_apm_init(trans);
601
602 /* From now on, the op_mode will be kept updated about RF kill state */
603 iwl_enable_rfkill_int(trans);
604
605 hw_rfkill = iwl_is_rfkill_set(trans);
606 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
607
608 return err;
609
610 err_free_irq:
611 trans_pcie->irq_requested = false;
612 free_irq(trans_pcie->irq, trans);
613 error:
614 iwl_pcie_free_ict(trans);
615 tasklet_kill(&trans_pcie->irq_tasklet);
616 return err;
617 }
618
619 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
620 bool op_mode_leaving)
621 {
622 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
623 bool hw_rfkill;
624 unsigned long flags;
625
626 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
627 iwl_disable_interrupts(trans);
628 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
629
630 iwl_pcie_apm_stop(trans);
631
632 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
633 iwl_disable_interrupts(trans);
634 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
635
636 iwl_pcie_disable_ict(trans);
637
638 if (!op_mode_leaving) {
639 /*
640 * Even if we stop the HW, we still want the RF kill
641 * interrupt
642 */
643 iwl_enable_rfkill_int(trans);
644
645 /*
646 * Check again since the RF kill state may have changed while
647 * all the interrupts were disabled, in this case we couldn't
648 * receive the RF kill interrupt and update the state in the
649 * op_mode.
650 */
651 hw_rfkill = iwl_is_rfkill_set(trans);
652 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
653 }
654 }
655
656 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
657 {
658 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
659 }
660
661 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
662 {
663 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
664 }
665
666 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
667 {
668 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
669 }
670
671 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
672 {
673 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
674 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
675 }
676
677 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
678 u32 val)
679 {
680 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
681 ((addr & 0x0000FFFF) | (3 << 24)));
682 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
683 }
684
685 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
686 const struct iwl_trans_config *trans_cfg)
687 {
688 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
689
690 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
691 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
692 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
693 trans_pcie->n_no_reclaim_cmds = 0;
694 else
695 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
696 if (trans_pcie->n_no_reclaim_cmds)
697 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
698 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
699
700 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
701 if (trans_pcie->rx_buf_size_8k)
702 trans_pcie->rx_page_order = get_order(8 * 1024);
703 else
704 trans_pcie->rx_page_order = get_order(4 * 1024);
705
706 trans_pcie->wd_timeout =
707 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
708
709 trans_pcie->command_names = trans_cfg->command_names;
710 }
711
712 void iwl_trans_pcie_free(struct iwl_trans *trans)
713 {
714 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
715
716 iwl_pcie_tx_free(trans);
717 iwl_pcie_rx_free(trans);
718
719 if (trans_pcie->irq_requested == true) {
720 free_irq(trans_pcie->irq, trans);
721 iwl_pcie_free_ict(trans);
722 }
723
724 pci_disable_msi(trans_pcie->pci_dev);
725 iounmap(trans_pcie->hw_base);
726 pci_release_regions(trans_pcie->pci_dev);
727 pci_disable_device(trans_pcie->pci_dev);
728 kmem_cache_destroy(trans->dev_cmd_pool);
729
730 kfree(trans);
731 }
732
733 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
734 {
735 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
736
737 if (state)
738 set_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
739 else
740 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
741 }
742
743 #ifdef CONFIG_PM_SLEEP
744 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
745 {
746 return 0;
747 }
748
749 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
750 {
751 bool hw_rfkill;
752
753 iwl_enable_rfkill_int(trans);
754
755 hw_rfkill = iwl_is_rfkill_set(trans);
756 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
757
758 if (!hw_rfkill)
759 iwl_enable_interrupts(trans);
760
761 return 0;
762 }
763 #endif /* CONFIG_PM_SLEEP */
764
765 #define IWL_FLUSH_WAIT_MS 2000
766
767 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
768 {
769 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
770 struct iwl_txq *txq;
771 struct iwl_queue *q;
772 int cnt;
773 unsigned long now = jiffies;
774 int ret = 0;
775
776 /* waiting for all the tx frames complete might take a while */
777 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
778 if (cnt == trans_pcie->cmd_queue)
779 continue;
780 txq = &trans_pcie->txq[cnt];
781 q = &txq->q;
782 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
783 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
784 msleep(1);
785
786 if (q->read_ptr != q->write_ptr) {
787 IWL_ERR(trans, "fail to flush all tx fifo queues\n");
788 ret = -ETIMEDOUT;
789 break;
790 }
791 }
792 return ret;
793 }
794
795 static const char *get_fh_string(int cmd)
796 {
797 #define IWL_CMD(x) case x: return #x
798 switch (cmd) {
799 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
800 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
801 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
802 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
803 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
804 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
805 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
806 IWL_CMD(FH_TSSR_TX_STATUS_REG);
807 IWL_CMD(FH_TSSR_TX_ERROR_REG);
808 default:
809 return "UNKNOWN";
810 }
811 #undef IWL_CMD
812 }
813
814 int iwl_pcie_dump_fh(struct iwl_trans *trans, char **buf)
815 {
816 int i;
817 static const u32 fh_tbl[] = {
818 FH_RSCSR_CHNL0_STTS_WPTR_REG,
819 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
820 FH_RSCSR_CHNL0_WPTR,
821 FH_MEM_RCSR_CHNL0_CONFIG_REG,
822 FH_MEM_RSSR_SHARED_CTRL_REG,
823 FH_MEM_RSSR_RX_STATUS_REG,
824 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
825 FH_TSSR_TX_STATUS_REG,
826 FH_TSSR_TX_ERROR_REG
827 };
828
829 #ifdef CONFIG_IWLWIFI_DEBUGFS
830 if (buf) {
831 int pos = 0;
832 size_t bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
833
834 *buf = kmalloc(bufsz, GFP_KERNEL);
835 if (!*buf)
836 return -ENOMEM;
837
838 pos += scnprintf(*buf + pos, bufsz - pos,
839 "FH register values:\n");
840
841 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
842 pos += scnprintf(*buf + pos, bufsz - pos,
843 " %34s: 0X%08x\n",
844 get_fh_string(fh_tbl[i]),
845 iwl_read_direct32(trans, fh_tbl[i]));
846
847 return pos;
848 }
849 #endif
850
851 IWL_ERR(trans, "FH register values:\n");
852 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
853 IWL_ERR(trans, " %34s: 0X%08x\n",
854 get_fh_string(fh_tbl[i]),
855 iwl_read_direct32(trans, fh_tbl[i]));
856
857 return 0;
858 }
859
860 static const char *get_csr_string(int cmd)
861 {
862 #define IWL_CMD(x) case x: return #x
863 switch (cmd) {
864 IWL_CMD(CSR_HW_IF_CONFIG_REG);
865 IWL_CMD(CSR_INT_COALESCING);
866 IWL_CMD(CSR_INT);
867 IWL_CMD(CSR_INT_MASK);
868 IWL_CMD(CSR_FH_INT_STATUS);
869 IWL_CMD(CSR_GPIO_IN);
870 IWL_CMD(CSR_RESET);
871 IWL_CMD(CSR_GP_CNTRL);
872 IWL_CMD(CSR_HW_REV);
873 IWL_CMD(CSR_EEPROM_REG);
874 IWL_CMD(CSR_EEPROM_GP);
875 IWL_CMD(CSR_OTP_GP_REG);
876 IWL_CMD(CSR_GIO_REG);
877 IWL_CMD(CSR_GP_UCODE_REG);
878 IWL_CMD(CSR_GP_DRIVER_REG);
879 IWL_CMD(CSR_UCODE_DRV_GP1);
880 IWL_CMD(CSR_UCODE_DRV_GP2);
881 IWL_CMD(CSR_LED_REG);
882 IWL_CMD(CSR_DRAM_INT_TBL_REG);
883 IWL_CMD(CSR_GIO_CHICKEN_BITS);
884 IWL_CMD(CSR_ANA_PLL_CFG);
885 IWL_CMD(CSR_HW_REV_WA_REG);
886 IWL_CMD(CSR_DBG_HPET_MEM_REG);
887 default:
888 return "UNKNOWN";
889 }
890 #undef IWL_CMD
891 }
892
893 void iwl_pcie_dump_csr(struct iwl_trans *trans)
894 {
895 int i;
896 static const u32 csr_tbl[] = {
897 CSR_HW_IF_CONFIG_REG,
898 CSR_INT_COALESCING,
899 CSR_INT,
900 CSR_INT_MASK,
901 CSR_FH_INT_STATUS,
902 CSR_GPIO_IN,
903 CSR_RESET,
904 CSR_GP_CNTRL,
905 CSR_HW_REV,
906 CSR_EEPROM_REG,
907 CSR_EEPROM_GP,
908 CSR_OTP_GP_REG,
909 CSR_GIO_REG,
910 CSR_GP_UCODE_REG,
911 CSR_GP_DRIVER_REG,
912 CSR_UCODE_DRV_GP1,
913 CSR_UCODE_DRV_GP2,
914 CSR_LED_REG,
915 CSR_DRAM_INT_TBL_REG,
916 CSR_GIO_CHICKEN_BITS,
917 CSR_ANA_PLL_CFG,
918 CSR_HW_REV_WA_REG,
919 CSR_DBG_HPET_MEM_REG
920 };
921 IWL_ERR(trans, "CSR values:\n");
922 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
923 "CSR_INT_PERIODIC_REG)\n");
924 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
925 IWL_ERR(trans, " %25s: 0X%08x\n",
926 get_csr_string(csr_tbl[i]),
927 iwl_read32(trans, csr_tbl[i]));
928 }
929 }
930
931 #ifdef CONFIG_IWLWIFI_DEBUGFS
932 /* create and remove of files */
933 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
934 if (!debugfs_create_file(#name, mode, parent, trans, \
935 &iwl_dbgfs_##name##_ops)) \
936 goto err; \
937 } while (0)
938
939 /* file operation */
940 #define DEBUGFS_READ_FUNC(name) \
941 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
942 char __user *user_buf, \
943 size_t count, loff_t *ppos);
944
945 #define DEBUGFS_WRITE_FUNC(name) \
946 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
947 const char __user *user_buf, \
948 size_t count, loff_t *ppos);
949
950 #define DEBUGFS_READ_FILE_OPS(name) \
951 DEBUGFS_READ_FUNC(name); \
952 static const struct file_operations iwl_dbgfs_##name##_ops = { \
953 .read = iwl_dbgfs_##name##_read, \
954 .open = simple_open, \
955 .llseek = generic_file_llseek, \
956 };
957
958 #define DEBUGFS_WRITE_FILE_OPS(name) \
959 DEBUGFS_WRITE_FUNC(name); \
960 static const struct file_operations iwl_dbgfs_##name##_ops = { \
961 .write = iwl_dbgfs_##name##_write, \
962 .open = simple_open, \
963 .llseek = generic_file_llseek, \
964 };
965
966 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
967 DEBUGFS_READ_FUNC(name); \
968 DEBUGFS_WRITE_FUNC(name); \
969 static const struct file_operations iwl_dbgfs_##name##_ops = { \
970 .write = iwl_dbgfs_##name##_write, \
971 .read = iwl_dbgfs_##name##_read, \
972 .open = simple_open, \
973 .llseek = generic_file_llseek, \
974 };
975
976 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
977 char __user *user_buf,
978 size_t count, loff_t *ppos)
979 {
980 struct iwl_trans *trans = file->private_data;
981 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
982 struct iwl_txq *txq;
983 struct iwl_queue *q;
984 char *buf;
985 int pos = 0;
986 int cnt;
987 int ret;
988 size_t bufsz;
989
990 bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
991
992 if (!trans_pcie->txq)
993 return -EAGAIN;
994
995 buf = kzalloc(bufsz, GFP_KERNEL);
996 if (!buf)
997 return -ENOMEM;
998
999 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1000 txq = &trans_pcie->txq[cnt];
1001 q = &txq->q;
1002 pos += scnprintf(buf + pos, bufsz - pos,
1003 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1004 cnt, q->read_ptr, q->write_ptr,
1005 !!test_bit(cnt, trans_pcie->queue_used),
1006 !!test_bit(cnt, trans_pcie->queue_stopped));
1007 }
1008 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1009 kfree(buf);
1010 return ret;
1011 }
1012
1013 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1014 char __user *user_buf,
1015 size_t count, loff_t *ppos)
1016 {
1017 struct iwl_trans *trans = file->private_data;
1018 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1019 struct iwl_rxq *rxq = &trans_pcie->rxq;
1020 char buf[256];
1021 int pos = 0;
1022 const size_t bufsz = sizeof(buf);
1023
1024 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1025 rxq->read);
1026 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1027 rxq->write);
1028 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1029 rxq->free_count);
1030 if (rxq->rb_stts) {
1031 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1032 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1033 } else {
1034 pos += scnprintf(buf + pos, bufsz - pos,
1035 "closed_rb_num: Not Allocated\n");
1036 }
1037 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1038 }
1039
1040 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1041 char __user *user_buf,
1042 size_t count, loff_t *ppos)
1043 {
1044 struct iwl_trans *trans = file->private_data;
1045 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1046 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1047
1048 int pos = 0;
1049 char *buf;
1050 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1051 ssize_t ret;
1052
1053 buf = kzalloc(bufsz, GFP_KERNEL);
1054 if (!buf)
1055 return -ENOMEM;
1056
1057 pos += scnprintf(buf + pos, bufsz - pos,
1058 "Interrupt Statistics Report:\n");
1059
1060 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1061 isr_stats->hw);
1062 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1063 isr_stats->sw);
1064 if (isr_stats->sw || isr_stats->hw) {
1065 pos += scnprintf(buf + pos, bufsz - pos,
1066 "\tLast Restarting Code: 0x%X\n",
1067 isr_stats->err_code);
1068 }
1069 #ifdef CONFIG_IWLWIFI_DEBUG
1070 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1071 isr_stats->sch);
1072 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1073 isr_stats->alive);
1074 #endif
1075 pos += scnprintf(buf + pos, bufsz - pos,
1076 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1077
1078 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1079 isr_stats->ctkill);
1080
1081 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1082 isr_stats->wakeup);
1083
1084 pos += scnprintf(buf + pos, bufsz - pos,
1085 "Rx command responses:\t\t %u\n", isr_stats->rx);
1086
1087 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1088 isr_stats->tx);
1089
1090 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1091 isr_stats->unhandled);
1092
1093 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1094 kfree(buf);
1095 return ret;
1096 }
1097
1098 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1099 const char __user *user_buf,
1100 size_t count, loff_t *ppos)
1101 {
1102 struct iwl_trans *trans = file->private_data;
1103 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1104 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1105
1106 char buf[8];
1107 int buf_size;
1108 u32 reset_flag;
1109
1110 memset(buf, 0, sizeof(buf));
1111 buf_size = min(count, sizeof(buf) - 1);
1112 if (copy_from_user(buf, user_buf, buf_size))
1113 return -EFAULT;
1114 if (sscanf(buf, "%x", &reset_flag) != 1)
1115 return -EFAULT;
1116 if (reset_flag == 0)
1117 memset(isr_stats, 0, sizeof(*isr_stats));
1118
1119 return count;
1120 }
1121
1122 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1123 const char __user *user_buf,
1124 size_t count, loff_t *ppos)
1125 {
1126 struct iwl_trans *trans = file->private_data;
1127 char buf[8];
1128 int buf_size;
1129 int csr;
1130
1131 memset(buf, 0, sizeof(buf));
1132 buf_size = min(count, sizeof(buf) - 1);
1133 if (copy_from_user(buf, user_buf, buf_size))
1134 return -EFAULT;
1135 if (sscanf(buf, "%d", &csr) != 1)
1136 return -EFAULT;
1137
1138 iwl_pcie_dump_csr(trans);
1139
1140 return count;
1141 }
1142
1143 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1144 char __user *user_buf,
1145 size_t count, loff_t *ppos)
1146 {
1147 struct iwl_trans *trans = file->private_data;
1148 char *buf = NULL;
1149 int pos = 0;
1150 ssize_t ret = -EFAULT;
1151
1152 ret = pos = iwl_pcie_dump_fh(trans, &buf);
1153 if (buf) {
1154 ret = simple_read_from_buffer(user_buf,
1155 count, ppos, buf, pos);
1156 kfree(buf);
1157 }
1158
1159 return ret;
1160 }
1161
1162 static ssize_t iwl_dbgfs_fw_restart_write(struct file *file,
1163 const char __user *user_buf,
1164 size_t count, loff_t *ppos)
1165 {
1166 struct iwl_trans *trans = file->private_data;
1167
1168 if (!trans->op_mode)
1169 return -EAGAIN;
1170
1171 local_bh_disable();
1172 iwl_op_mode_nic_error(trans->op_mode);
1173 local_bh_enable();
1174
1175 return count;
1176 }
1177
1178 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1179 DEBUGFS_READ_FILE_OPS(fh_reg);
1180 DEBUGFS_READ_FILE_OPS(rx_queue);
1181 DEBUGFS_READ_FILE_OPS(tx_queue);
1182 DEBUGFS_WRITE_FILE_OPS(csr);
1183 DEBUGFS_WRITE_FILE_OPS(fw_restart);
1184
1185 /*
1186 * Create the debugfs files and directories
1187 *
1188 */
1189 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1190 struct dentry *dir)
1191 {
1192 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1193 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1194 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1195 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1196 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1197 DEBUGFS_ADD_FILE(fw_restart, dir, S_IWUSR);
1198 return 0;
1199
1200 err:
1201 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1202 return -ENOMEM;
1203 }
1204 #else
1205 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1206 struct dentry *dir)
1207 {
1208 return 0;
1209 }
1210 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1211
1212 static const struct iwl_trans_ops trans_ops_pcie = {
1213 .start_hw = iwl_trans_pcie_start_hw,
1214 .stop_hw = iwl_trans_pcie_stop_hw,
1215 .fw_alive = iwl_trans_pcie_fw_alive,
1216 .start_fw = iwl_trans_pcie_start_fw,
1217 .stop_device = iwl_trans_pcie_stop_device,
1218
1219 .wowlan_suspend = iwl_trans_pcie_wowlan_suspend,
1220
1221 .send_cmd = iwl_trans_pcie_send_hcmd,
1222
1223 .tx = iwl_trans_pcie_tx,
1224 .reclaim = iwl_trans_pcie_reclaim,
1225
1226 .txq_disable = iwl_trans_pcie_txq_disable,
1227 .txq_enable = iwl_trans_pcie_txq_enable,
1228
1229 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1230
1231 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
1232
1233 #ifdef CONFIG_PM_SLEEP
1234 .suspend = iwl_trans_pcie_suspend,
1235 .resume = iwl_trans_pcie_resume,
1236 #endif
1237 .write8 = iwl_trans_pcie_write8,
1238 .write32 = iwl_trans_pcie_write32,
1239 .read32 = iwl_trans_pcie_read32,
1240 .read_prph = iwl_trans_pcie_read_prph,
1241 .write_prph = iwl_trans_pcie_write_prph,
1242 .configure = iwl_trans_pcie_configure,
1243 .set_pmi = iwl_trans_pcie_set_pmi,
1244 };
1245
1246 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
1247 const struct pci_device_id *ent,
1248 const struct iwl_cfg *cfg)
1249 {
1250 struct iwl_trans_pcie *trans_pcie;
1251 struct iwl_trans *trans;
1252 u16 pci_cmd;
1253 int err;
1254
1255 trans = kzalloc(sizeof(struct iwl_trans) +
1256 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
1257
1258 if (!trans)
1259 return NULL;
1260
1261 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1262
1263 trans->ops = &trans_ops_pcie;
1264 trans->cfg = cfg;
1265 trans_pcie->trans = trans;
1266 spin_lock_init(&trans_pcie->irq_lock);
1267 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
1268
1269 /* W/A - seems to solve weird behavior. We need to remove this if we
1270 * don't want to stay in L1 all the time. This wastes a lot of power */
1271 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
1272 PCIE_LINK_STATE_CLKPM);
1273
1274 if (pci_enable_device(pdev)) {
1275 err = -ENODEV;
1276 goto out_no_pci;
1277 }
1278
1279 pci_set_master(pdev);
1280
1281 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
1282 if (!err)
1283 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
1284 if (err) {
1285 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1286 if (!err)
1287 err = pci_set_consistent_dma_mask(pdev,
1288 DMA_BIT_MASK(32));
1289 /* both attempts failed: */
1290 if (err) {
1291 dev_err(&pdev->dev, "No suitable DMA available\n");
1292 goto out_pci_disable_device;
1293 }
1294 }
1295
1296 err = pci_request_regions(pdev, DRV_NAME);
1297 if (err) {
1298 dev_err(&pdev->dev, "pci_request_regions failed\n");
1299 goto out_pci_disable_device;
1300 }
1301
1302 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
1303 if (!trans_pcie->hw_base) {
1304 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
1305 err = -ENODEV;
1306 goto out_pci_release_regions;
1307 }
1308
1309 /* We disable the RETRY_TIMEOUT register (0x41) to keep
1310 * PCI Tx retries from interfering with C3 CPU state */
1311 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
1312
1313 err = pci_enable_msi(pdev);
1314 if (err) {
1315 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
1316 /* enable rfkill interrupt: hw bug w/a */
1317 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1318 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1319 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1320 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1321 }
1322 }
1323
1324 trans->dev = &pdev->dev;
1325 trans_pcie->irq = pdev->irq;
1326 trans_pcie->pci_dev = pdev;
1327 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
1328 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
1329 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
1330 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
1331
1332 /* Initialize the wait queue for commands */
1333 init_waitqueue_head(&trans_pcie->wait_command_queue);
1334 spin_lock_init(&trans->reg_lock);
1335
1336 snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
1337 "iwl_cmd_pool:%s", dev_name(trans->dev));
1338
1339 trans->dev_cmd_headroom = 0;
1340 trans->dev_cmd_pool =
1341 kmem_cache_create(trans->dev_cmd_pool_name,
1342 sizeof(struct iwl_device_cmd)
1343 + trans->dev_cmd_headroom,
1344 sizeof(void *),
1345 SLAB_HWCACHE_ALIGN,
1346 NULL);
1347
1348 if (!trans->dev_cmd_pool)
1349 goto out_pci_disable_msi;
1350
1351 return trans;
1352
1353 out_pci_disable_msi:
1354 pci_disable_msi(pdev);
1355 out_pci_release_regions:
1356 pci_release_regions(pdev);
1357 out_pci_disable_device:
1358 pci_disable_device(pdev);
1359 out_no_pci:
1360 kfree(trans);
1361 return NULL;
1362 }
Linux kernel - Deliverables
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