projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
iwlwifi: virtualize iwl_{grab,release}_nic_access
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / pcie / trans.c
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63 #include <linux/pci.h>
64 #include <linux/pci-aspm.h>
65 #include <linux/interrupt.h>
66 #include <linux/debugfs.h>
67 #include <linux/sched.h>
68 #include <linux/bitops.h>
69 #include <linux/gfp.h>
70
71 #include "iwl-drv.h"
72 #include "iwl-trans.h"
73 #include "iwl-csr.h"
74 #include "iwl-prph.h"
75 #include "iwl-agn-hw.h"
76 #include "internal.h"
77
78 static void iwl_pcie_set_pwr_vmain(struct iwl_trans *trans)
79 {
80 /*
81 * (for documentation purposes)
82 * to set power to V_AUX, do:
83
84 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
85 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
86 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
87 ~APMG_PS_CTRL_MSK_PWR_SRC);
88 */
89
90 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
91 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
92 ~APMG_PS_CTRL_MSK_PWR_SRC);
93 }
94
95 /* PCI registers */
96 #define PCI_CFG_RETRY_TIMEOUT 0x041
97
98 static void iwl_pcie_apm_config(struct iwl_trans *trans)
99 {
100 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
101 u16 lctl;
102
103 /*
104 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
105 * Check if BIOS (or OS) enabled L1-ASPM on this device.
106 * If so (likely), disable L0S, so device moves directly L0->L1;
107 * costs negligible amount of power savings.
108 * If not (unlikely), enable L0S, so there is at least some
109 * power savings, even without L1.
110 */
111 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
112 if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
113 /* L1-ASPM enabled; disable(!) L0S */
114 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
115 dev_info(trans->dev, "L1 Enabled; Disabling L0S\n");
116 } else {
117 /* L1-ASPM disabled; enable(!) L0S */
118 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
119 dev_info(trans->dev, "L1 Disabled; Enabling L0S\n");
120 }
121 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
122 }
123
124 /*
125 * Start up NIC's basic functionality after it has been reset
126 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
127 * NOTE: This does not load uCode nor start the embedded processor
128 */
129 static int iwl_pcie_apm_init(struct iwl_trans *trans)
130 {
131 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
132 int ret = 0;
133 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
134
135 /*
136 * Use "set_bit" below rather than "write", to preserve any hardware
137 * bits already set by default after reset.
138 */
139
140 /* Disable L0S exit timer (platform NMI Work/Around) */
141 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
142 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
143
144 /*
145 * Disable L0s without affecting L1;
146 * don't wait for ICH L0s (ICH bug W/A)
147 */
148 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
149 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
150
151 /* Set FH wait threshold to maximum (HW error during stress W/A) */
152 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
153
154 /*
155 * Enable HAP INTA (interrupt from management bus) to
156 * wake device's PCI Express link L1a -> L0s
157 */
158 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
159 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
160
161 iwl_pcie_apm_config(trans);
162
163 /* Configure analog phase-lock-loop before activating to D0A */
164 if (trans->cfg->base_params->pll_cfg_val)
165 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
166 trans->cfg->base_params->pll_cfg_val);
167
168 /*
169 * Set "initialization complete" bit to move adapter from
170 * D0U* --> D0A* (powered-up active) state.
171 */
172 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
173
174 /*
175 * Wait for clock stabilization; once stabilized, access to
176 * device-internal resources is supported, e.g. iwl_write_prph()
177 * and accesses to uCode SRAM.
178 */
179 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
180 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
181 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
182 if (ret < 0) {
183 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
184 goto out;
185 }
186
187 /*
188 * Enable DMA clock and wait for it to stabilize.
189 *
190 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
191 * do not disable clocks. This preserves any hardware bits already
192 * set by default in "CLK_CTRL_REG" after reset.
193 */
194 iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
195 udelay(20);
196
197 /* Disable L1-Active */
198 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
199 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
200
201 set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
202
203 out:
204 return ret;
205 }
206
207 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
208 {
209 int ret = 0;
210
211 /* stop device's busmaster DMA activity */
212 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
213
214 ret = iwl_poll_bit(trans, CSR_RESET,
215 CSR_RESET_REG_FLAG_MASTER_DISABLED,
216 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
217 if (ret)
218 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
219
220 IWL_DEBUG_INFO(trans, "stop master\n");
221
222 return ret;
223 }
224
225 static void iwl_pcie_apm_stop(struct iwl_trans *trans)
226 {
227 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
228 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
229
230 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
231
232 /* Stop device's DMA activity */
233 iwl_pcie_apm_stop_master(trans);
234
235 /* Reset the entire device */
236 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
237
238 udelay(10);
239
240 /*
241 * Clear "initialization complete" bit to move adapter from
242 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
243 */
244 iwl_clear_bit(trans, CSR_GP_CNTRL,
245 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
246 }
247
248 static int iwl_pcie_nic_init(struct iwl_trans *trans)
249 {
250 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
251 unsigned long flags;
252
253 /* nic_init */
254 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
255 iwl_pcie_apm_init(trans);
256
257 /* Set interrupt coalescing calibration timer to default (512 usecs) */
258 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
259
260 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
261
262 iwl_pcie_set_pwr_vmain(trans);
263
264 iwl_op_mode_nic_config(trans->op_mode);
265
266 /* Allocate the RX queue, or reset if it is already allocated */
267 iwl_pcie_rx_init(trans);
268
269 /* Allocate or reset and init all Tx and Command queues */
270 if (iwl_pcie_tx_init(trans))
271 return -ENOMEM;
272
273 if (trans->cfg->base_params->shadow_reg_enable) {
274 /* enable shadow regs in HW */
275 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
276 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
277 }
278
279 return 0;
280 }
281
282 #define HW_READY_TIMEOUT (50)
283
284 /* Note: returns poll_bit return value, which is >= 0 if success */
285 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
286 {
287 int ret;
288
289 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
290 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
291
292 /* See if we got it */
293 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
294 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
295 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
296 HW_READY_TIMEOUT);
297
298 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
299 return ret;
300 }
301
302 /* Note: returns standard 0/-ERROR code */
303 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
304 {
305 int ret;
306 int t = 0;
307
308 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
309
310 ret = iwl_pcie_set_hw_ready(trans);
311 /* If the card is ready, exit 0 */
312 if (ret >= 0)
313 return 0;
314
315 /* If HW is not ready, prepare the conditions to check again */
316 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
317 CSR_HW_IF_CONFIG_REG_PREPARE);
318
319 do {
320 ret = iwl_pcie_set_hw_ready(trans);
321 if (ret >= 0)
322 return 0;
323
324 usleep_range(200, 1000);
325 t += 200;
326 } while (t < 150000);
327
328 return ret;
329 }
330
331 /*
332 * ucode
333 */
334 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
335 dma_addr_t phy_addr, u32 byte_cnt)
336 {
337 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
338 int ret;
339
340 trans_pcie->ucode_write_complete = false;
341
342 iwl_write_direct32(trans,
343 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
344 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
345
346 iwl_write_direct32(trans,
347 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
348 dst_addr);
349
350 iwl_write_direct32(trans,
351 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
352 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
353
354 iwl_write_direct32(trans,
355 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
356 (iwl_get_dma_hi_addr(phy_addr)
357 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
358
359 iwl_write_direct32(trans,
360 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
361 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
362 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
363 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
364
365 iwl_write_direct32(trans,
366 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
367 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
368 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
369 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
370
371 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
372 trans_pcie->ucode_write_complete, 5 * HZ);
373 if (!ret) {
374 IWL_ERR(trans, "Failed to load firmware chunk!\n");
375 return -ETIMEDOUT;
376 }
377
378 return 0;
379 }
380
381 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
382 const struct fw_desc *section)
383 {
384 u8 *v_addr;
385 dma_addr_t p_addr;
386 u32 offset;
387 int ret = 0;
388
389 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
390 section_num);
391
392 v_addr = dma_alloc_coherent(trans->dev, PAGE_SIZE, &p_addr, GFP_KERNEL);
393 if (!v_addr)
394 return -ENOMEM;
395
396 for (offset = 0; offset < section->len; offset += PAGE_SIZE) {
397 u32 copy_size;
398
399 copy_size = min_t(u32, PAGE_SIZE, section->len - offset);
400
401 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
402 ret = iwl_pcie_load_firmware_chunk(trans,
403 section->offset + offset,
404 p_addr, copy_size);
405 if (ret) {
406 IWL_ERR(trans,
407 "Could not load the [%d] uCode section\n",
408 section_num);
409 break;
410 }
411 }
412
413 dma_free_coherent(trans->dev, PAGE_SIZE, v_addr, p_addr);
414 return ret;
415 }
416
417 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
418 const struct fw_img *image)
419 {
420 int i, ret = 0;
421
422 for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
423 if (!image->sec[i].data)
424 break;
425
426 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
427 if (ret)
428 return ret;
429 }
430
431 /* Remove all resets to allow NIC to operate */
432 iwl_write32(trans, CSR_RESET, 0);
433
434 return 0;
435 }
436
437 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
438 const struct fw_img *fw, bool run_in_rfkill)
439 {
440 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
441 int ret;
442 bool hw_rfkill;
443
444 /* This may fail if AMT took ownership of the device */
445 if (iwl_pcie_prepare_card_hw(trans)) {
446 IWL_WARN(trans, "Exit HW not ready\n");
447 return -EIO;
448 }
449
450 clear_bit(STATUS_FW_ERROR, &trans_pcie->status);
451
452 iwl_enable_rfkill_int(trans);
453
454 /* If platform's RF_KILL switch is NOT set to KILL */
455 hw_rfkill = iwl_is_rfkill_set(trans);
456 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
457 if (hw_rfkill && !run_in_rfkill)
458 return -ERFKILL;
459
460 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
461
462 ret = iwl_pcie_nic_init(trans);
463 if (ret) {
464 IWL_ERR(trans, "Unable to init nic\n");
465 return ret;
466 }
467
468 /* make sure rfkill handshake bits are cleared */
469 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
470 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
471 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
472
473 /* clear (again), then enable host interrupts */
474 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
475 iwl_enable_interrupts(trans);
476
477 /* really make sure rfkill handshake bits are cleared */
478 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
479 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
480
481 /* Load the given image to the HW */
482 return iwl_pcie_load_given_ucode(trans, fw);
483 }
484
485 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
486 {
487 iwl_pcie_reset_ict(trans);
488 iwl_pcie_tx_start(trans, scd_addr);
489 }
490
491 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
492 {
493 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
494 unsigned long flags;
495
496 /* tell the device to stop sending interrupts */
497 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
498 iwl_disable_interrupts(trans);
499 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
500
501 /* device going down, Stop using ICT table */
502 iwl_pcie_disable_ict(trans);
503
504 /*
505 * If a HW restart happens during firmware loading,
506 * then the firmware loading might call this function
507 * and later it might be called again due to the
508 * restart. So don't process again if the device is
509 * already dead.
510 */
511 if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
512 iwl_pcie_tx_stop(trans);
513 iwl_pcie_rx_stop(trans);
514
515 /* Power-down device's busmaster DMA clocks */
516 iwl_write_prph(trans, APMG_CLK_DIS_REG,
517 APMG_CLK_VAL_DMA_CLK_RQT);
518 udelay(5);
519 }
520
521 /* Make sure (redundant) we've released our request to stay awake */
522 iwl_clear_bit(trans, CSR_GP_CNTRL,
523 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
524
525 /* Stop the device, and put it in low power state */
526 iwl_pcie_apm_stop(trans);
527
528 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
529 * Clean again the interrupt here
530 */
531 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
532 iwl_disable_interrupts(trans);
533 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
534
535 iwl_enable_rfkill_int(trans);
536
537 /* wait to make sure we flush pending tasklet*/
538 synchronize_irq(trans_pcie->irq);
539 tasklet_kill(&trans_pcie->irq_tasklet);
540
541 cancel_work_sync(&trans_pcie->rx_replenish);
542
543 /* stop and reset the on-board processor */
544 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
545
546 /* clear all status bits */
547 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
548 clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
549 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
550 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
551 clear_bit(STATUS_RFKILL, &trans_pcie->status);
552 }
553
554 static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
555 {
556 /* let the ucode operate on its own */
557 iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
558 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
559
560 iwl_disable_interrupts(trans);
561 iwl_clear_bit(trans, CSR_GP_CNTRL,
562 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
563 }
564
565 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
566 {
567 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
568 int err;
569 bool hw_rfkill;
570
571 trans_pcie->inta_mask = CSR_INI_SET_MASK;
572
573 if (!trans_pcie->irq_requested) {
574 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
575 iwl_pcie_tasklet, (unsigned long)trans);
576
577 iwl_pcie_alloc_ict(trans);
578
579 err = request_irq(trans_pcie->irq, iwl_pcie_isr_ict,
580 IRQF_SHARED, DRV_NAME, trans);
581 if (err) {
582 IWL_ERR(trans, "Error allocating IRQ %d\n",
583 trans_pcie->irq);
584 goto error;
585 }
586
587 trans_pcie->irq_requested = true;
588 }
589
590 err = iwl_pcie_prepare_card_hw(trans);
591 if (err) {
592 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
593 goto err_free_irq;
594 }
595
596 iwl_pcie_apm_init(trans);
597
598 /* From now on, the op_mode will be kept updated about RF kill state */
599 iwl_enable_rfkill_int(trans);
600
601 hw_rfkill = iwl_is_rfkill_set(trans);
602 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
603
604 return err;
605
606 err_free_irq:
607 trans_pcie->irq_requested = false;
608 free_irq(trans_pcie->irq, trans);
609 error:
610 iwl_pcie_free_ict(trans);
611 tasklet_kill(&trans_pcie->irq_tasklet);
612 return err;
613 }
614
615 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
616 bool op_mode_leaving)
617 {
618 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
619 bool hw_rfkill;
620 unsigned long flags;
621
622 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
623 iwl_disable_interrupts(trans);
624 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
625
626 iwl_pcie_apm_stop(trans);
627
628 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
629 iwl_disable_interrupts(trans);
630 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
631
632 iwl_pcie_disable_ict(trans);
633
634 if (!op_mode_leaving) {
635 /*
636 * Even if we stop the HW, we still want the RF kill
637 * interrupt
638 */
639 iwl_enable_rfkill_int(trans);
640
641 /*
642 * Check again since the RF kill state may have changed while
643 * all the interrupts were disabled, in this case we couldn't
644 * receive the RF kill interrupt and update the state in the
645 * op_mode.
646 */
647 hw_rfkill = iwl_is_rfkill_set(trans);
648 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
649 }
650 }
651
652 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
653 {
654 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
655 }
656
657 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
658 {
659 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
660 }
661
662 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
663 {
664 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
665 }
666
667 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
668 {
669 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
670 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
671 }
672
673 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
674 u32 val)
675 {
676 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
677 ((addr & 0x0000FFFF) | (3 << 24)));
678 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
679 }
680
681 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
682 const struct iwl_trans_config *trans_cfg)
683 {
684 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
685
686 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
687 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
688 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
689 trans_pcie->n_no_reclaim_cmds = 0;
690 else
691 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
692 if (trans_pcie->n_no_reclaim_cmds)
693 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
694 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
695
696 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
697 if (trans_pcie->rx_buf_size_8k)
698 trans_pcie->rx_page_order = get_order(8 * 1024);
699 else
700 trans_pcie->rx_page_order = get_order(4 * 1024);
701
702 trans_pcie->wd_timeout =
703 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
704
705 trans_pcie->command_names = trans_cfg->command_names;
706 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
707 }
708
709 void iwl_trans_pcie_free(struct iwl_trans *trans)
710 {
711 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
712
713 iwl_pcie_tx_free(trans);
714 iwl_pcie_rx_free(trans);
715
716 if (trans_pcie->irq_requested == true) {
717 free_irq(trans_pcie->irq, trans);
718 iwl_pcie_free_ict(trans);
719 }
720
721 pci_disable_msi(trans_pcie->pci_dev);
722 iounmap(trans_pcie->hw_base);
723 pci_release_regions(trans_pcie->pci_dev);
724 pci_disable_device(trans_pcie->pci_dev);
725 kmem_cache_destroy(trans->dev_cmd_pool);
726
727 kfree(trans);
728 }
729
730 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
731 {
732 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
733
734 if (state)
735 set_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
736 else
737 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
738 }
739
740 #ifdef CONFIG_PM_SLEEP
741 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
742 {
743 return 0;
744 }
745
746 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
747 {
748 bool hw_rfkill;
749
750 iwl_enable_rfkill_int(trans);
751
752 hw_rfkill = iwl_is_rfkill_set(trans);
753 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
754
755 if (!hw_rfkill)
756 iwl_enable_interrupts(trans);
757
758 return 0;
759 }
760 #endif /* CONFIG_PM_SLEEP */
761
762 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent)
763 {
764 int ret;
765
766 lockdep_assert_held(&trans->reg_lock);
767
768 /* this bit wakes up the NIC */
769 __iwl_set_bit(trans, CSR_GP_CNTRL,
770 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
771
772 /*
773 * These bits say the device is running, and should keep running for
774 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
775 * but they do not indicate that embedded SRAM is restored yet;
776 * 3945 and 4965 have volatile SRAM, and must save/restore contents
777 * to/from host DRAM when sleeping/waking for power-saving.
778 * Each direction takes approximately 1/4 millisecond; with this
779 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
780 * series of register accesses are expected (e.g. reading Event Log),
781 * to keep device from sleeping.
782 *
783 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
784 * SRAM is okay/restored. We don't check that here because this call
785 * is just for hardware register access; but GP1 MAC_SLEEP check is a
786 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
787 *
788 * 5000 series and later (including 1000 series) have non-volatile SRAM,
789 * and do not save/restore SRAM when power cycling.
790 */
791 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
792 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
793 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
794 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
795 if (unlikely(ret < 0)) {
796 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
797 if (!silent) {
798 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
799 WARN_ONCE(1,
800 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
801 val);
802 return false;
803 }
804 }
805
806 return true;
807 }
808
809 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans)
810 {
811 lockdep_assert_held(&trans->reg_lock);
812 __iwl_clear_bit(trans, CSR_GP_CNTRL,
813 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
814 /*
815 * Above we read the CSR_GP_CNTRL register, which will flush
816 * any previous writes, but we need the write that clears the
817 * MAC_ACCESS_REQ bit to be performed before any other writes
818 * scheduled on different CPUs (after we drop reg_lock).
819 */
820 mmiowb();
821 }
822
823
824 #define IWL_FLUSH_WAIT_MS 2000
825
826 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
827 {
828 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
829 struct iwl_txq *txq;
830 struct iwl_queue *q;
831 int cnt;
832 unsigned long now = jiffies;
833 int ret = 0;
834
835 /* waiting for all the tx frames complete might take a while */
836 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
837 if (cnt == trans_pcie->cmd_queue)
838 continue;
839 txq = &trans_pcie->txq[cnt];
840 q = &txq->q;
841 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
842 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
843 msleep(1);
844
845 if (q->read_ptr != q->write_ptr) {
846 IWL_ERR(trans, "fail to flush all tx fifo queues\n");
847 ret = -ETIMEDOUT;
848 break;
849 }
850 }
851 return ret;
852 }
853
854 static const char *get_fh_string(int cmd)
855 {
856 #define IWL_CMD(x) case x: return #x
857 switch (cmd) {
858 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
859 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
860 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
861 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
862 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
863 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
864 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
865 IWL_CMD(FH_TSSR_TX_STATUS_REG);
866 IWL_CMD(FH_TSSR_TX_ERROR_REG);
867 default:
868 return "UNKNOWN";
869 }
870 #undef IWL_CMD
871 }
872
873 int iwl_pcie_dump_fh(struct iwl_trans *trans, char **buf)
874 {
875 int i;
876 static const u32 fh_tbl[] = {
877 FH_RSCSR_CHNL0_STTS_WPTR_REG,
878 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
879 FH_RSCSR_CHNL0_WPTR,
880 FH_MEM_RCSR_CHNL0_CONFIG_REG,
881 FH_MEM_RSSR_SHARED_CTRL_REG,
882 FH_MEM_RSSR_RX_STATUS_REG,
883 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
884 FH_TSSR_TX_STATUS_REG,
885 FH_TSSR_TX_ERROR_REG
886 };
887
888 #ifdef CONFIG_IWLWIFI_DEBUGFS
889 if (buf) {
890 int pos = 0;
891 size_t bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
892
893 *buf = kmalloc(bufsz, GFP_KERNEL);
894 if (!*buf)
895 return -ENOMEM;
896
897 pos += scnprintf(*buf + pos, bufsz - pos,
898 "FH register values:\n");
899
900 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
901 pos += scnprintf(*buf + pos, bufsz - pos,
902 " %34s: 0X%08x\n",
903 get_fh_string(fh_tbl[i]),
904 iwl_read_direct32(trans, fh_tbl[i]));
905
906 return pos;
907 }
908 #endif
909
910 IWL_ERR(trans, "FH register values:\n");
911 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
912 IWL_ERR(trans, " %34s: 0X%08x\n",
913 get_fh_string(fh_tbl[i]),
914 iwl_read_direct32(trans, fh_tbl[i]));
915
916 return 0;
917 }
918
919 static const char *get_csr_string(int cmd)
920 {
921 #define IWL_CMD(x) case x: return #x
922 switch (cmd) {
923 IWL_CMD(CSR_HW_IF_CONFIG_REG);
924 IWL_CMD(CSR_INT_COALESCING);
925 IWL_CMD(CSR_INT);
926 IWL_CMD(CSR_INT_MASK);
927 IWL_CMD(CSR_FH_INT_STATUS);
928 IWL_CMD(CSR_GPIO_IN);
929 IWL_CMD(CSR_RESET);
930 IWL_CMD(CSR_GP_CNTRL);
931 IWL_CMD(CSR_HW_REV);
932 IWL_CMD(CSR_EEPROM_REG);
933 IWL_CMD(CSR_EEPROM_GP);
934 IWL_CMD(CSR_OTP_GP_REG);
935 IWL_CMD(CSR_GIO_REG);
936 IWL_CMD(CSR_GP_UCODE_REG);
937 IWL_CMD(CSR_GP_DRIVER_REG);
938 IWL_CMD(CSR_UCODE_DRV_GP1);
939 IWL_CMD(CSR_UCODE_DRV_GP2);
940 IWL_CMD(CSR_LED_REG);
941 IWL_CMD(CSR_DRAM_INT_TBL_REG);
942 IWL_CMD(CSR_GIO_CHICKEN_BITS);
943 IWL_CMD(CSR_ANA_PLL_CFG);
944 IWL_CMD(CSR_HW_REV_WA_REG);
945 IWL_CMD(CSR_DBG_HPET_MEM_REG);
946 default:
947 return "UNKNOWN";
948 }
949 #undef IWL_CMD
950 }
951
952 void iwl_pcie_dump_csr(struct iwl_trans *trans)
953 {
954 int i;
955 static const u32 csr_tbl[] = {
956 CSR_HW_IF_CONFIG_REG,
957 CSR_INT_COALESCING,
958 CSR_INT,
959 CSR_INT_MASK,
960 CSR_FH_INT_STATUS,
961 CSR_GPIO_IN,
962 CSR_RESET,
963 CSR_GP_CNTRL,
964 CSR_HW_REV,
965 CSR_EEPROM_REG,
966 CSR_EEPROM_GP,
967 CSR_OTP_GP_REG,
968 CSR_GIO_REG,
969 CSR_GP_UCODE_REG,
970 CSR_GP_DRIVER_REG,
971 CSR_UCODE_DRV_GP1,
972 CSR_UCODE_DRV_GP2,
973 CSR_LED_REG,
974 CSR_DRAM_INT_TBL_REG,
975 CSR_GIO_CHICKEN_BITS,
976 CSR_ANA_PLL_CFG,
977 CSR_HW_REV_WA_REG,
978 CSR_DBG_HPET_MEM_REG
979 };
980 IWL_ERR(trans, "CSR values:\n");
981 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
982 "CSR_INT_PERIODIC_REG)\n");
983 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
984 IWL_ERR(trans, " %25s: 0X%08x\n",
985 get_csr_string(csr_tbl[i]),
986 iwl_read32(trans, csr_tbl[i]));
987 }
988 }
989
990 #ifdef CONFIG_IWLWIFI_DEBUGFS
991 /* create and remove of files */
992 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
993 if (!debugfs_create_file(#name, mode, parent, trans, \
994 &iwl_dbgfs_##name##_ops)) \
995 goto err; \
996 } while (0)
997
998 /* file operation */
999 #define DEBUGFS_READ_FUNC(name) \
1000 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1001 char __user *user_buf, \
1002 size_t count, loff_t *ppos);
1003
1004 #define DEBUGFS_WRITE_FUNC(name) \
1005 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1006 const char __user *user_buf, \
1007 size_t count, loff_t *ppos);
1008
1009 #define DEBUGFS_READ_FILE_OPS(name) \
1010 DEBUGFS_READ_FUNC(name); \
1011 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1012 .read = iwl_dbgfs_##name##_read, \
1013 .open = simple_open, \
1014 .llseek = generic_file_llseek, \
1015 };
1016
1017 #define DEBUGFS_WRITE_FILE_OPS(name) \
1018 DEBUGFS_WRITE_FUNC(name); \
1019 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1020 .write = iwl_dbgfs_##name##_write, \
1021 .open = simple_open, \
1022 .llseek = generic_file_llseek, \
1023 };
1024
1025 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1026 DEBUGFS_READ_FUNC(name); \
1027 DEBUGFS_WRITE_FUNC(name); \
1028 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1029 .write = iwl_dbgfs_##name##_write, \
1030 .read = iwl_dbgfs_##name##_read, \
1031 .open = simple_open, \
1032 .llseek = generic_file_llseek, \
1033 };
1034
1035 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1036 char __user *user_buf,
1037 size_t count, loff_t *ppos)
1038 {
1039 struct iwl_trans *trans = file->private_data;
1040 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1041 struct iwl_txq *txq;
1042 struct iwl_queue *q;
1043 char *buf;
1044 int pos = 0;
1045 int cnt;
1046 int ret;
1047 size_t bufsz;
1048
1049 bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1050
1051 if (!trans_pcie->txq)
1052 return -EAGAIN;
1053
1054 buf = kzalloc(bufsz, GFP_KERNEL);
1055 if (!buf)
1056 return -ENOMEM;
1057
1058 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1059 txq = &trans_pcie->txq[cnt];
1060 q = &txq->q;
1061 pos += scnprintf(buf + pos, bufsz - pos,
1062 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1063 cnt, q->read_ptr, q->write_ptr,
1064 !!test_bit(cnt, trans_pcie->queue_used),
1065 !!test_bit(cnt, trans_pcie->queue_stopped));
1066 }
1067 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1068 kfree(buf);
1069 return ret;
1070 }
1071
1072 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1073 char __user *user_buf,
1074 size_t count, loff_t *ppos)
1075 {
1076 struct iwl_trans *trans = file->private_data;
1077 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1078 struct iwl_rxq *rxq = &trans_pcie->rxq;
1079 char buf[256];
1080 int pos = 0;
1081 const size_t bufsz = sizeof(buf);
1082
1083 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1084 rxq->read);
1085 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1086 rxq->write);
1087 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1088 rxq->free_count);
1089 if (rxq->rb_stts) {
1090 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1091 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1092 } else {
1093 pos += scnprintf(buf + pos, bufsz - pos,
1094 "closed_rb_num: Not Allocated\n");
1095 }
1096 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1097 }
1098
1099 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1100 char __user *user_buf,
1101 size_t count, loff_t *ppos)
1102 {
1103 struct iwl_trans *trans = file->private_data;
1104 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1105 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1106
1107 int pos = 0;
1108 char *buf;
1109 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1110 ssize_t ret;
1111
1112 buf = kzalloc(bufsz, GFP_KERNEL);
1113 if (!buf)
1114 return -ENOMEM;
1115
1116 pos += scnprintf(buf + pos, bufsz - pos,
1117 "Interrupt Statistics Report:\n");
1118
1119 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1120 isr_stats->hw);
1121 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1122 isr_stats->sw);
1123 if (isr_stats->sw || isr_stats->hw) {
1124 pos += scnprintf(buf + pos, bufsz - pos,
1125 "\tLast Restarting Code: 0x%X\n",
1126 isr_stats->err_code);
1127 }
1128 #ifdef CONFIG_IWLWIFI_DEBUG
1129 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1130 isr_stats->sch);
1131 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1132 isr_stats->alive);
1133 #endif
1134 pos += scnprintf(buf + pos, bufsz - pos,
1135 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1136
1137 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1138 isr_stats->ctkill);
1139
1140 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1141 isr_stats->wakeup);
1142
1143 pos += scnprintf(buf + pos, bufsz - pos,
1144 "Rx command responses:\t\t %u\n", isr_stats->rx);
1145
1146 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1147 isr_stats->tx);
1148
1149 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1150 isr_stats->unhandled);
1151
1152 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1153 kfree(buf);
1154 return ret;
1155 }
1156
1157 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1158 const char __user *user_buf,
1159 size_t count, loff_t *ppos)
1160 {
1161 struct iwl_trans *trans = file->private_data;
1162 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1163 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1164
1165 char buf[8];
1166 int buf_size;
1167 u32 reset_flag;
1168
1169 memset(buf, 0, sizeof(buf));
1170 buf_size = min(count, sizeof(buf) - 1);
1171 if (copy_from_user(buf, user_buf, buf_size))
1172 return -EFAULT;
1173 if (sscanf(buf, "%x", &reset_flag) != 1)
1174 return -EFAULT;
1175 if (reset_flag == 0)
1176 memset(isr_stats, 0, sizeof(*isr_stats));
1177
1178 return count;
1179 }
1180
1181 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1182 const char __user *user_buf,
1183 size_t count, loff_t *ppos)
1184 {
1185 struct iwl_trans *trans = file->private_data;
1186 char buf[8];
1187 int buf_size;
1188 int csr;
1189
1190 memset(buf, 0, sizeof(buf));
1191 buf_size = min(count, sizeof(buf) - 1);
1192 if (copy_from_user(buf, user_buf, buf_size))
1193 return -EFAULT;
1194 if (sscanf(buf, "%d", &csr) != 1)
1195 return -EFAULT;
1196
1197 iwl_pcie_dump_csr(trans);
1198
1199 return count;
1200 }
1201
1202 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1203 char __user *user_buf,
1204 size_t count, loff_t *ppos)
1205 {
1206 struct iwl_trans *trans = file->private_data;
1207 char *buf = NULL;
1208 int pos = 0;
1209 ssize_t ret = -EFAULT;
1210
1211 ret = pos = iwl_pcie_dump_fh(trans, &buf);
1212 if (buf) {
1213 ret = simple_read_from_buffer(user_buf,
1214 count, ppos, buf, pos);
1215 kfree(buf);
1216 }
1217
1218 return ret;
1219 }
1220
1221 static ssize_t iwl_dbgfs_fw_restart_write(struct file *file,
1222 const char __user *user_buf,
1223 size_t count, loff_t *ppos)
1224 {
1225 struct iwl_trans *trans = file->private_data;
1226
1227 if (!trans->op_mode)
1228 return -EAGAIN;
1229
1230 local_bh_disable();
1231 iwl_op_mode_nic_error(trans->op_mode);
1232 local_bh_enable();
1233
1234 return count;
1235 }
1236
1237 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1238 DEBUGFS_READ_FILE_OPS(fh_reg);
1239 DEBUGFS_READ_FILE_OPS(rx_queue);
1240 DEBUGFS_READ_FILE_OPS(tx_queue);
1241 DEBUGFS_WRITE_FILE_OPS(csr);
1242 DEBUGFS_WRITE_FILE_OPS(fw_restart);
1243
1244 /*
1245 * Create the debugfs files and directories
1246 *
1247 */
1248 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1249 struct dentry *dir)
1250 {
1251 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1252 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1253 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1254 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1255 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1256 DEBUGFS_ADD_FILE(fw_restart, dir, S_IWUSR);
1257 return 0;
1258
1259 err:
1260 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1261 return -ENOMEM;
1262 }
1263 #else
1264 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1265 struct dentry *dir)
1266 {
1267 return 0;
1268 }
1269 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1270
1271 static const struct iwl_trans_ops trans_ops_pcie = {
1272 .start_hw = iwl_trans_pcie_start_hw,
1273 .stop_hw = iwl_trans_pcie_stop_hw,
1274 .fw_alive = iwl_trans_pcie_fw_alive,
1275 .start_fw = iwl_trans_pcie_start_fw,
1276 .stop_device = iwl_trans_pcie_stop_device,
1277
1278 .wowlan_suspend = iwl_trans_pcie_wowlan_suspend,
1279
1280 .send_cmd = iwl_trans_pcie_send_hcmd,
1281
1282 .tx = iwl_trans_pcie_tx,
1283 .reclaim = iwl_trans_pcie_reclaim,
1284
1285 .txq_disable = iwl_trans_pcie_txq_disable,
1286 .txq_enable = iwl_trans_pcie_txq_enable,
1287
1288 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1289
1290 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
1291
1292 #ifdef CONFIG_PM_SLEEP
1293 .suspend = iwl_trans_pcie_suspend,
1294 .resume = iwl_trans_pcie_resume,
1295 #endif
1296 .write8 = iwl_trans_pcie_write8,
1297 .write32 = iwl_trans_pcie_write32,
1298 .read32 = iwl_trans_pcie_read32,
1299 .read_prph = iwl_trans_pcie_read_prph,
1300 .write_prph = iwl_trans_pcie_write_prph,
1301 .configure = iwl_trans_pcie_configure,
1302 .set_pmi = iwl_trans_pcie_set_pmi,
1303 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
1304 .release_nic_access = iwl_trans_pcie_release_nic_access
1305 };
1306
1307 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
1308 const struct pci_device_id *ent,
1309 const struct iwl_cfg *cfg)
1310 {
1311 struct iwl_trans_pcie *trans_pcie;
1312 struct iwl_trans *trans;
1313 u16 pci_cmd;
1314 int err;
1315
1316 trans = kzalloc(sizeof(struct iwl_trans) +
1317 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
1318
1319 if (!trans)
1320 return NULL;
1321
1322 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1323
1324 trans->ops = &trans_ops_pcie;
1325 trans->cfg = cfg;
1326 trans_pcie->trans = trans;
1327 spin_lock_init(&trans_pcie->irq_lock);
1328 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
1329
1330 /* W/A - seems to solve weird behavior. We need to remove this if we
1331 * don't want to stay in L1 all the time. This wastes a lot of power */
1332 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
1333 PCIE_LINK_STATE_CLKPM);
1334
1335 if (pci_enable_device(pdev)) {
1336 err = -ENODEV;
1337 goto out_no_pci;
1338 }
1339
1340 pci_set_master(pdev);
1341
1342 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
1343 if (!err)
1344 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
1345 if (err) {
1346 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1347 if (!err)
1348 err = pci_set_consistent_dma_mask(pdev,
1349 DMA_BIT_MASK(32));
1350 /* both attempts failed: */
1351 if (err) {
1352 dev_err(&pdev->dev, "No suitable DMA available\n");
1353 goto out_pci_disable_device;
1354 }
1355 }
1356
1357 err = pci_request_regions(pdev, DRV_NAME);
1358 if (err) {
1359 dev_err(&pdev->dev, "pci_request_regions failed\n");
1360 goto out_pci_disable_device;
1361 }
1362
1363 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
1364 if (!trans_pcie->hw_base) {
1365 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
1366 err = -ENODEV;
1367 goto out_pci_release_regions;
1368 }
1369
1370 /* We disable the RETRY_TIMEOUT register (0x41) to keep
1371 * PCI Tx retries from interfering with C3 CPU state */
1372 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
1373
1374 err = pci_enable_msi(pdev);
1375 if (err) {
1376 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
1377 /* enable rfkill interrupt: hw bug w/a */
1378 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1379 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1380 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1381 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1382 }
1383 }
1384
1385 trans->dev = &pdev->dev;
1386 trans_pcie->irq = pdev->irq;
1387 trans_pcie->pci_dev = pdev;
1388 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
1389 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
1390 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
1391 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
1392
1393 /* Initialize the wait queue for commands */
1394 init_waitqueue_head(&trans_pcie->wait_command_queue);
1395 spin_lock_init(&trans->reg_lock);
1396
1397 snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
1398 "iwl_cmd_pool:%s", dev_name(trans->dev));
1399
1400 trans->dev_cmd_headroom = 0;
1401 trans->dev_cmd_pool =
1402 kmem_cache_create(trans->dev_cmd_pool_name,
1403 sizeof(struct iwl_device_cmd)
1404 + trans->dev_cmd_headroom,
1405 sizeof(void *),
1406 SLAB_HWCACHE_ALIGN,
1407 NULL);
1408
1409 if (!trans->dev_cmd_pool)
1410 goto out_pci_disable_msi;
1411
1412 return trans;
1413
1414 out_pci_disable_msi:
1415 pci_disable_msi(pdev);
1416 out_pci_release_regions:
1417 pci_release_regions(pdev);
1418 out_pci_disable_device:
1419 pci_disable_device(pdev);
1420 out_no_pci:
1421 kfree(trans);
1422 return NULL;
1423 }
Linux kernel - Deliverables
This page took 0.060385 seconds and 6 git commands to generate.