1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
25 * The full GNU General Public License is included in this distribution
26 * in the file called COPYING.
28 * Contact Information:
29 * Intel Linux Wireless <ilw@linux.intel.com>
30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
34 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
35 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
36 * All rights reserved.
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
64 *****************************************************************************/
65 #include <linux/pci.h>
66 #include <linux/pci-aspm.h>
67 #include <linux/interrupt.h>
68 #include <linux/debugfs.h>
69 #include <linux/sched.h>
70 #include <linux/bitops.h>
71 #include <linux/gfp.h>
72 #include <linux/vmalloc.h>
75 #include "iwl-trans.h"
78 #include "iwl-agn-hw.h"
79 #include "iwl-fw-error-dump.h"
82 static void iwl_pcie_free_fw_monitor(struct iwl_trans
*trans
)
84 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
86 if (!trans_pcie
->fw_mon_page
)
89 dma_unmap_page(trans
->dev
, trans_pcie
->fw_mon_phys
,
90 trans_pcie
->fw_mon_size
, DMA_FROM_DEVICE
);
91 __free_pages(trans_pcie
->fw_mon_page
,
92 get_order(trans_pcie
->fw_mon_size
));
93 trans_pcie
->fw_mon_page
= NULL
;
94 trans_pcie
->fw_mon_phys
= 0;
95 trans_pcie
->fw_mon_size
= 0;
98 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans
*trans
)
100 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
106 if (trans_pcie
->fw_mon_page
) {
107 dma_sync_single_for_device(trans
->dev
, trans_pcie
->fw_mon_phys
,
108 trans_pcie
->fw_mon_size
,
114 for (power
= 26; power
>= 11; power
--) {
118 order
= get_order(size
);
119 page
= alloc_pages(__GFP_COMP
| __GFP_NOWARN
| __GFP_ZERO
,
124 phys
= dma_map_page(trans
->dev
, page
, 0, PAGE_SIZE
<< order
,
126 if (dma_mapping_error(trans
->dev
, phys
)) {
127 __free_pages(page
, order
);
131 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
139 trans_pcie
->fw_mon_page
= page
;
140 trans_pcie
->fw_mon_phys
= phys
;
141 trans_pcie
->fw_mon_size
= size
;
144 static u32
iwl_trans_pcie_read_shr(struct iwl_trans
*trans
, u32 reg
)
146 iwl_write32(trans
, HEEP_CTRL_WRD_PCIEX_CTRL_REG
,
147 ((reg
& 0x0000ffff) | (2 << 28)));
148 return iwl_read32(trans
, HEEP_CTRL_WRD_PCIEX_DATA_REG
);
151 static void iwl_trans_pcie_write_shr(struct iwl_trans
*trans
, u32 reg
, u32 val
)
153 iwl_write32(trans
, HEEP_CTRL_WRD_PCIEX_DATA_REG
, val
);
154 iwl_write32(trans
, HEEP_CTRL_WRD_PCIEX_CTRL_REG
,
155 ((reg
& 0x0000ffff) | (3 << 28)));
158 static void iwl_pcie_set_pwr(struct iwl_trans
*trans
, bool vaux
)
160 if (vaux
&& pci_pme_capable(to_pci_dev(trans
->dev
), PCI_D3cold
))
161 iwl_set_bits_mask_prph(trans
, APMG_PS_CTRL_REG
,
162 APMG_PS_CTRL_VAL_PWR_SRC_VAUX
,
163 ~APMG_PS_CTRL_MSK_PWR_SRC
);
165 iwl_set_bits_mask_prph(trans
, APMG_PS_CTRL_REG
,
166 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN
,
167 ~APMG_PS_CTRL_MSK_PWR_SRC
);
171 #define PCI_CFG_RETRY_TIMEOUT 0x041
173 static void iwl_pcie_apm_config(struct iwl_trans
*trans
)
175 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
180 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
181 * Check if BIOS (or OS) enabled L1-ASPM on this device.
182 * If so (likely), disable L0S, so device moves directly L0->L1;
183 * costs negligible amount of power savings.
184 * If not (unlikely), enable L0S, so there is at least some
185 * power savings, even without L1.
187 pcie_capability_read_word(trans_pcie
->pci_dev
, PCI_EXP_LNKCTL
, &lctl
);
188 if (lctl
& PCI_EXP_LNKCTL_ASPM_L1
)
189 iwl_set_bit(trans
, CSR_GIO_REG
, CSR_GIO_REG_VAL_L0S_ENABLED
);
191 iwl_clear_bit(trans
, CSR_GIO_REG
, CSR_GIO_REG_VAL_L0S_ENABLED
);
192 trans
->pm_support
= !(lctl
& PCI_EXP_LNKCTL_ASPM_L0S
);
194 pcie_capability_read_word(trans_pcie
->pci_dev
, PCI_EXP_DEVCTL2
, &cap
);
195 trans
->ltr_enabled
= cap
& PCI_EXP_DEVCTL2_LTR_EN
;
196 dev_info(trans
->dev
, "L1 %sabled - LTR %sabled\n",
197 (lctl
& PCI_EXP_LNKCTL_ASPM_L1
) ? "En" : "Dis",
198 trans
->ltr_enabled
? "En" : "Dis");
202 * Start up NIC's basic functionality after it has been reset
203 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
204 * NOTE: This does not load uCode nor start the embedded processor
206 static int iwl_pcie_apm_init(struct iwl_trans
*trans
)
209 IWL_DEBUG_INFO(trans
, "Init card's basic functions\n");
212 * Use "set_bit" below rather than "write", to preserve any hardware
213 * bits already set by default after reset.
216 /* Disable L0S exit timer (platform NMI Work/Around) */
217 if (trans
->cfg
->device_family
!= IWL_DEVICE_FAMILY_8000
)
218 iwl_set_bit(trans
, CSR_GIO_CHICKEN_BITS
,
219 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER
);
222 * Disable L0s without affecting L1;
223 * don't wait for ICH L0s (ICH bug W/A)
225 iwl_set_bit(trans
, CSR_GIO_CHICKEN_BITS
,
226 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX
);
228 /* Set FH wait threshold to maximum (HW error during stress W/A) */
229 iwl_set_bit(trans
, CSR_DBG_HPET_MEM_REG
, CSR_DBG_HPET_MEM_REG_VAL
);
232 * Enable HAP INTA (interrupt from management bus) to
233 * wake device's PCI Express link L1a -> L0s
235 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
236 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A
);
238 iwl_pcie_apm_config(trans
);
240 /* Configure analog phase-lock-loop before activating to D0A */
241 if (trans
->cfg
->base_params
->pll_cfg_val
)
242 iwl_set_bit(trans
, CSR_ANA_PLL_CFG
,
243 trans
->cfg
->base_params
->pll_cfg_val
);
246 * Set "initialization complete" bit to move adapter from
247 * D0U* --> D0A* (powered-up active) state.
249 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
252 * Wait for clock stabilization; once stabilized, access to
253 * device-internal resources is supported, e.g. iwl_write_prph()
254 * and accesses to uCode SRAM.
256 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
257 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
258 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
, 25000);
260 IWL_DEBUG_INFO(trans
, "Failed to init the card\n");
264 if (trans
->cfg
->host_interrupt_operation_mode
) {
266 * This is a bit of an abuse - This is needed for 7260 / 3160
267 * only check host_interrupt_operation_mode even if this is
268 * not related to host_interrupt_operation_mode.
270 * Enable the oscillator to count wake up time for L1 exit. This
271 * consumes slightly more power (100uA) - but allows to be sure
272 * that we wake up from L1 on time.
274 * This looks weird: read twice the same register, discard the
275 * value, set a bit, and yet again, read that same register
276 * just to discard the value. But that's the way the hardware
279 iwl_read_prph(trans
, OSC_CLK
);
280 iwl_read_prph(trans
, OSC_CLK
);
281 iwl_set_bits_prph(trans
, OSC_CLK
, OSC_CLK_FORCE_CONTROL
);
282 iwl_read_prph(trans
, OSC_CLK
);
283 iwl_read_prph(trans
, OSC_CLK
);
287 * Enable DMA clock and wait for it to stabilize.
289 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
290 * bits do not disable clocks. This preserves any hardware
291 * bits already set by default in "CLK_CTRL_REG" after reset.
293 if (trans
->cfg
->device_family
!= IWL_DEVICE_FAMILY_8000
) {
294 iwl_write_prph(trans
, APMG_CLK_EN_REG
,
295 APMG_CLK_VAL_DMA_CLK_RQT
);
298 /* Disable L1-Active */
299 iwl_set_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
300 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
302 /* Clear the interrupt in APMG if the NIC is in RFKILL */
303 iwl_write_prph(trans
, APMG_RTC_INT_STT_REG
,
304 APMG_RTC_INT_STT_RFKILL
);
307 set_bit(STATUS_DEVICE_ENABLED
, &trans
->status
);
314 * Enable LP XTAL to avoid HW bug where device may consume much power if
315 * FW is not loaded after device reset. LP XTAL is disabled by default
316 * after device HW reset. Do it only if XTAL is fed by internal source.
317 * Configure device's "persistence" mode to avoid resetting XTAL again when
318 * SHRD_HW_RST occurs in S3.
320 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans
*trans
)
324 u32 apmg_xtal_cfg_reg
;
328 __iwl_trans_pcie_set_bit(trans
, CSR_GP_CNTRL
,
329 CSR_GP_CNTRL_REG_FLAG_XTAL_ON
);
331 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
332 iwl_set_bit(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
337 * Set "initialization complete" bit to move adapter from
338 * D0U* --> D0A* (powered-up active) state.
340 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
343 * Wait for clock stabilization; once stabilized, access to
344 * device-internal resources is possible.
346 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
347 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
348 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
350 if (WARN_ON(ret
< 0)) {
351 IWL_ERR(trans
, "Access time out - failed to enable LP XTAL\n");
352 /* Release XTAL ON request */
353 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
354 CSR_GP_CNTRL_REG_FLAG_XTAL_ON
);
359 * Clear "disable persistence" to avoid LP XTAL resetting when
360 * SHRD_HW_RST is applied in S3.
362 iwl_clear_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
363 APMG_PCIDEV_STT_VAL_PERSIST_DIS
);
366 * Force APMG XTAL to be active to prevent its disabling by HW
367 * caused by APMG idle state.
369 apmg_xtal_cfg_reg
= iwl_trans_pcie_read_shr(trans
,
370 SHR_APMG_XTAL_CFG_REG
);
371 iwl_trans_pcie_write_shr(trans
, SHR_APMG_XTAL_CFG_REG
,
373 SHR_APMG_XTAL_CFG_XTAL_ON_REQ
);
376 * Reset entire device again - do controller reset (results in
377 * SHRD_HW_RST). Turn MAC off before proceeding.
379 iwl_set_bit(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
383 /* Enable LP XTAL by indirect access through CSR */
384 apmg_gp1_reg
= iwl_trans_pcie_read_shr(trans
, SHR_APMG_GP1_REG
);
385 iwl_trans_pcie_write_shr(trans
, SHR_APMG_GP1_REG
, apmg_gp1_reg
|
386 SHR_APMG_GP1_WF_XTAL_LP_EN
|
387 SHR_APMG_GP1_CHICKEN_BIT_SELECT
);
389 /* Clear delay line clock power up */
390 dl_cfg_reg
= iwl_trans_pcie_read_shr(trans
, SHR_APMG_DL_CFG_REG
);
391 iwl_trans_pcie_write_shr(trans
, SHR_APMG_DL_CFG_REG
, dl_cfg_reg
&
392 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP
);
395 * Enable persistence mode to avoid LP XTAL resetting when
396 * SHRD_HW_RST is applied in S3.
398 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
399 CSR_HW_IF_CONFIG_REG_PERSIST_MODE
);
402 * Clear "initialization complete" bit to move adapter from
403 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
405 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
406 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
408 /* Activates XTAL resources monitor */
409 __iwl_trans_pcie_set_bit(trans
, CSR_MONITOR_CFG_REG
,
410 CSR_MONITOR_XTAL_RESOURCES
);
412 /* Release XTAL ON request */
413 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
414 CSR_GP_CNTRL_REG_FLAG_XTAL_ON
);
417 /* Release APMG XTAL */
418 iwl_trans_pcie_write_shr(trans
, SHR_APMG_XTAL_CFG_REG
,
420 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ
);
423 static int iwl_pcie_apm_stop_master(struct iwl_trans
*trans
)
427 /* stop device's busmaster DMA activity */
428 iwl_set_bit(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_STOP_MASTER
);
430 ret
= iwl_poll_bit(trans
, CSR_RESET
,
431 CSR_RESET_REG_FLAG_MASTER_DISABLED
,
432 CSR_RESET_REG_FLAG_MASTER_DISABLED
, 100);
434 IWL_WARN(trans
, "Master Disable Timed Out, 100 usec\n");
436 IWL_DEBUG_INFO(trans
, "stop master\n");
441 static void iwl_pcie_apm_stop(struct iwl_trans
*trans
)
443 IWL_DEBUG_INFO(trans
, "Stop card, put in low power state\n");
445 clear_bit(STATUS_DEVICE_ENABLED
, &trans
->status
);
447 /* Stop device's DMA activity */
448 iwl_pcie_apm_stop_master(trans
);
450 if (trans
->cfg
->lp_xtal_workaround
) {
451 iwl_pcie_apm_lp_xtal_enable(trans
);
455 /* Reset the entire device */
456 iwl_set_bit(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
461 * Clear "initialization complete" bit to move adapter from
462 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
464 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
465 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
468 static int iwl_pcie_nic_init(struct iwl_trans
*trans
)
470 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
473 spin_lock(&trans_pcie
->irq_lock
);
474 iwl_pcie_apm_init(trans
);
476 spin_unlock(&trans_pcie
->irq_lock
);
478 if (trans
->cfg
->device_family
!= IWL_DEVICE_FAMILY_8000
)
479 iwl_pcie_set_pwr(trans
, false);
481 iwl_op_mode_nic_config(trans
->op_mode
);
483 /* Allocate the RX queue, or reset if it is already allocated */
484 iwl_pcie_rx_init(trans
);
486 /* Allocate or reset and init all Tx and Command queues */
487 if (iwl_pcie_tx_init(trans
))
490 if (trans
->cfg
->base_params
->shadow_reg_enable
) {
491 /* enable shadow regs in HW */
492 iwl_set_bit(trans
, CSR_MAC_SHADOW_REG_CTRL
, 0x800FFFFF);
493 IWL_DEBUG_INFO(trans
, "Enabling shadow registers in device\n");
499 #define HW_READY_TIMEOUT (50)
501 /* Note: returns poll_bit return value, which is >= 0 if success */
502 static int iwl_pcie_set_hw_ready(struct iwl_trans
*trans
)
506 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
507 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
);
509 /* See if we got it */
510 ret
= iwl_poll_bit(trans
, CSR_HW_IF_CONFIG_REG
,
511 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
512 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
515 IWL_DEBUG_INFO(trans
, "hardware%s ready\n", ret
< 0 ? " not" : "");
519 /* Note: returns standard 0/-ERROR code */
520 static int iwl_pcie_prepare_card_hw(struct iwl_trans
*trans
)
526 IWL_DEBUG_INFO(trans
, "iwl_trans_prepare_card_hw enter\n");
528 ret
= iwl_pcie_set_hw_ready(trans
);
529 /* If the card is ready, exit 0 */
533 for (iter
= 0; iter
< 10; iter
++) {
534 /* If HW is not ready, prepare the conditions to check again */
535 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
536 CSR_HW_IF_CONFIG_REG_PREPARE
);
539 ret
= iwl_pcie_set_hw_ready(trans
);
543 usleep_range(200, 1000);
545 } while (t
< 150000);
549 IWL_ERR(trans
, "Couldn't prepare the card\n");
557 static int iwl_pcie_load_firmware_chunk(struct iwl_trans
*trans
, u32 dst_addr
,
558 dma_addr_t phy_addr
, u32 byte_cnt
)
560 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
563 trans_pcie
->ucode_write_complete
= false;
565 iwl_write_direct32(trans
,
566 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
567 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE
);
569 iwl_write_direct32(trans
,
570 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL
),
573 iwl_write_direct32(trans
,
574 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL
),
575 phy_addr
& FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK
);
577 iwl_write_direct32(trans
,
578 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL
),
579 (iwl_get_dma_hi_addr(phy_addr
)
580 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT
) | byte_cnt
);
582 iwl_write_direct32(trans
,
583 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL
),
584 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM
|
585 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX
|
586 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID
);
588 iwl_write_direct32(trans
,
589 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
590 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
591 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE
|
592 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD
);
594 ret
= wait_event_timeout(trans_pcie
->ucode_write_waitq
,
595 trans_pcie
->ucode_write_complete
, 5 * HZ
);
597 IWL_ERR(trans
, "Failed to load firmware chunk!\n");
604 static int iwl_pcie_load_section(struct iwl_trans
*trans
, u8 section_num
,
605 const struct fw_desc
*section
)
609 u32 offset
, chunk_sz
= section
->len
;
612 IWL_DEBUG_FW(trans
, "[%d] uCode section being loaded...\n",
615 v_addr
= dma_alloc_coherent(trans
->dev
, chunk_sz
, &p_addr
,
616 GFP_KERNEL
| __GFP_NOWARN
);
618 IWL_DEBUG_INFO(trans
, "Falling back to small chunks of DMA\n");
619 chunk_sz
= PAGE_SIZE
;
620 v_addr
= dma_alloc_coherent(trans
->dev
, chunk_sz
,
621 &p_addr
, GFP_KERNEL
);
626 for (offset
= 0; offset
< section
->len
; offset
+= chunk_sz
) {
629 copy_size
= min_t(u32
, chunk_sz
, section
->len
- offset
);
631 memcpy(v_addr
, (u8
*)section
->data
+ offset
, copy_size
);
632 ret
= iwl_pcie_load_firmware_chunk(trans
,
633 section
->offset
+ offset
,
637 "Could not load the [%d] uCode section\n",
643 dma_free_coherent(trans
->dev
, chunk_sz
, v_addr
, p_addr
);
647 static int iwl_pcie_load_cpu_secured_sections(struct iwl_trans
*trans
,
648 const struct fw_img
*image
,
650 int *first_ucode_section
)
654 u32 last_read_idx
= 0;
658 *first_ucode_section
= 0;
661 (*first_ucode_section
)++;
664 for (i
= *first_ucode_section
; i
< IWL_UCODE_SECTION_MAX
; i
++) {
667 if (!image
->sec
[i
].data
||
668 image
->sec
[i
].offset
== CPU1_CPU2_SEPARATOR_SECTION
) {
670 "Break since Data not valid or Empty section, sec = %d\n",
675 if (i
== (*first_ucode_section
) + 1)
676 /* set CPU to started */
677 iwl_set_bits_prph(trans
,
678 CSR_UCODE_LOAD_STATUS_ADDR
,
679 LMPM_CPU_HDRS_LOADING_COMPLETED
682 ret
= iwl_pcie_load_section(trans
, i
, &image
->sec
[i
]);
686 /* image loading complete */
687 iwl_set_bits_prph(trans
,
688 CSR_UCODE_LOAD_STATUS_ADDR
,
689 LMPM_CPU_UCODE_LOADING_COMPLETED
<< shift_param
);
691 *first_ucode_section
= last_read_idx
;
696 static int iwl_pcie_load_cpu_sections(struct iwl_trans
*trans
,
697 const struct fw_img
*image
,
699 int *first_ucode_section
)
703 u32 last_read_idx
= 0;
707 *first_ucode_section
= 0;
710 (*first_ucode_section
)++;
713 for (i
= *first_ucode_section
; i
< IWL_UCODE_SECTION_MAX
; i
++) {
716 if (!image
->sec
[i
].data
||
717 image
->sec
[i
].offset
== CPU1_CPU2_SEPARATOR_SECTION
) {
719 "Break since Data not valid or Empty section, sec = %d\n",
724 ret
= iwl_pcie_load_section(trans
, i
, &image
->sec
[i
]);
729 if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_8000
)
730 iwl_set_bits_prph(trans
,
731 CSR_UCODE_LOAD_STATUS_ADDR
,
732 (LMPM_CPU_UCODE_LOADING_COMPLETED
|
733 LMPM_CPU_HDRS_LOADING_COMPLETED
|
734 LMPM_CPU_UCODE_LOADING_STARTED
) <<
737 *first_ucode_section
= last_read_idx
;
742 static int iwl_pcie_load_given_ucode(struct iwl_trans
*trans
,
743 const struct fw_img
*image
)
745 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
747 int first_ucode_section
;
750 "working with %s image\n",
751 image
->is_secure
? "Secured" : "Non Secured");
753 "working with %s CPU\n",
754 image
->is_dual_cpus
? "Dual" : "Single");
756 /* configure the ucode to be ready to get the secured image */
757 if (image
->is_secure
) {
758 /* set secure boot inspector addresses */
759 iwl_write_prph(trans
,
760 LMPM_SECURE_INSPECTOR_CODE_ADDR
,
761 LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE
);
763 iwl_write_prph(trans
,
764 LMPM_SECURE_INSPECTOR_DATA_ADDR
,
765 LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE
);
767 /* set CPU1 header address */
768 iwl_write_prph(trans
,
769 LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR
,
770 LMPM_SECURE_CPU1_HDR_MEM_SPACE
);
772 /* load to FW the binary Secured sections of CPU1 */
773 ret
= iwl_pcie_load_cpu_secured_sections(trans
, image
, 1,
774 &first_ucode_section
);
779 /* load to FW the binary Non secured sections of CPU1 */
780 ret
= iwl_pcie_load_cpu_sections(trans
, image
, 1,
781 &first_ucode_section
);
786 if (image
->is_dual_cpus
) {
787 /* set CPU2 header address */
788 iwl_write_prph(trans
,
789 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR
,
790 LMPM_SECURE_CPU2_HDR_MEM_SPACE
);
792 /* load to FW the binary sections of CPU2 */
793 if (image
->is_secure
)
794 ret
= iwl_pcie_load_cpu_secured_sections(
796 &first_ucode_section
);
798 ret
= iwl_pcie_load_cpu_sections(trans
, image
, 2,
799 &first_ucode_section
);
804 /* supported for 7000 only for the moment */
805 if (iwlwifi_mod_params
.fw_monitor
&&
806 trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_7000
) {
807 iwl_pcie_alloc_fw_monitor(trans
);
809 if (trans_pcie
->fw_mon_size
) {
810 iwl_write_prph(trans
, MON_BUFF_BASE_ADDR
,
811 trans_pcie
->fw_mon_phys
>> 4);
812 iwl_write_prph(trans
, MON_BUFF_END_ADDR
,
813 (trans_pcie
->fw_mon_phys
+
814 trans_pcie
->fw_mon_size
) >> 4);
818 /* release CPU reset */
819 if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_8000
)
820 iwl_write_prph(trans
, RELEASE_CPU_RESET
, RELEASE_CPU_RESET_BIT
);
822 iwl_write32(trans
, CSR_RESET
, 0);
824 if (image
->is_secure
) {
825 /* wait for image verification to complete */
826 ret
= iwl_poll_prph_bit(trans
,
827 LMPM_SECURE_BOOT_CPU1_STATUS_ADDR
,
828 LMPM_SECURE_BOOT_STATUS_SUCCESS
,
829 LMPM_SECURE_BOOT_STATUS_SUCCESS
,
830 LMPM_SECURE_TIME_OUT
);
833 IWL_ERR(trans
, "Time out on secure boot process\n");
841 static int iwl_trans_pcie_start_fw(struct iwl_trans
*trans
,
842 const struct fw_img
*fw
, bool run_in_rfkill
)
847 /* This may fail if AMT took ownership of the device */
848 if (iwl_pcie_prepare_card_hw(trans
)) {
849 IWL_WARN(trans
, "Exit HW not ready\n");
853 iwl_enable_rfkill_int(trans
);
855 /* If platform's RF_KILL switch is NOT set to KILL */
856 hw_rfkill
= iwl_is_rfkill_set(trans
);
858 set_bit(STATUS_RFKILL
, &trans
->status
);
860 clear_bit(STATUS_RFKILL
, &trans
->status
);
861 iwl_trans_pcie_rf_kill(trans
, hw_rfkill
);
862 if (hw_rfkill
&& !run_in_rfkill
)
865 iwl_write32(trans
, CSR_INT
, 0xFFFFFFFF);
867 ret
= iwl_pcie_nic_init(trans
);
869 IWL_ERR(trans
, "Unable to init nic\n");
873 /* make sure rfkill handshake bits are cleared */
874 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
875 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
,
876 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED
);
878 /* clear (again), then enable host interrupts */
879 iwl_write32(trans
, CSR_INT
, 0xFFFFFFFF);
880 iwl_enable_interrupts(trans
);
882 /* really make sure rfkill handshake bits are cleared */
883 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
884 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
886 /* Load the given image to the HW */
887 return iwl_pcie_load_given_ucode(trans
, fw
);
890 static void iwl_trans_pcie_fw_alive(struct iwl_trans
*trans
, u32 scd_addr
)
892 iwl_pcie_reset_ict(trans
);
893 iwl_pcie_tx_start(trans
, scd_addr
);
896 static void iwl_trans_pcie_stop_device(struct iwl_trans
*trans
)
898 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
899 bool hw_rfkill
, was_hw_rfkill
;
901 was_hw_rfkill
= iwl_is_rfkill_set(trans
);
903 /* tell the device to stop sending interrupts */
904 spin_lock(&trans_pcie
->irq_lock
);
905 iwl_disable_interrupts(trans
);
906 spin_unlock(&trans_pcie
->irq_lock
);
908 /* device going down, Stop using ICT table */
909 iwl_pcie_disable_ict(trans
);
912 * If a HW restart happens during firmware loading,
913 * then the firmware loading might call this function
914 * and later it might be called again due to the
915 * restart. So don't process again if the device is
918 if (test_bit(STATUS_DEVICE_ENABLED
, &trans
->status
)) {
919 iwl_pcie_tx_stop(trans
);
920 iwl_pcie_rx_stop(trans
);
922 /* Power-down device's busmaster DMA clocks */
923 iwl_write_prph(trans
, APMG_CLK_DIS_REG
,
924 APMG_CLK_VAL_DMA_CLK_RQT
);
928 /* Make sure (redundant) we've released our request to stay awake */
929 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
930 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
932 /* Stop the device, and put it in low power state */
933 iwl_pcie_apm_stop(trans
);
935 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
936 * Clean again the interrupt here
938 spin_lock(&trans_pcie
->irq_lock
);
939 iwl_disable_interrupts(trans
);
940 spin_unlock(&trans_pcie
->irq_lock
);
942 /* stop and reset the on-board processor */
943 iwl_write32(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_NEVO_RESET
);
945 /* clear all status bits */
946 clear_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
);
947 clear_bit(STATUS_INT_ENABLED
, &trans
->status
);
948 clear_bit(STATUS_DEVICE_ENABLED
, &trans
->status
);
949 clear_bit(STATUS_TPOWER_PMI
, &trans
->status
);
950 clear_bit(STATUS_RFKILL
, &trans
->status
);
953 * Even if we stop the HW, we still want the RF kill
956 iwl_enable_rfkill_int(trans
);
959 * Check again since the RF kill state may have changed while
960 * all the interrupts were disabled, in this case we couldn't
961 * receive the RF kill interrupt and update the state in the
963 * Don't call the op_mode if the rkfill state hasn't changed.
964 * This allows the op_mode to call stop_device from the rfkill
965 * notification without endless recursion. Under very rare
966 * circumstances, we might have a small recursion if the rfkill
967 * state changed exactly now while we were called from stop_device.
968 * This is very unlikely but can happen and is supported.
970 hw_rfkill
= iwl_is_rfkill_set(trans
);
972 set_bit(STATUS_RFKILL
, &trans
->status
);
974 clear_bit(STATUS_RFKILL
, &trans
->status
);
975 if (hw_rfkill
!= was_hw_rfkill
)
976 iwl_trans_pcie_rf_kill(trans
, hw_rfkill
);
979 void iwl_trans_pcie_rf_kill(struct iwl_trans
*trans
, bool state
)
981 if (iwl_op_mode_hw_rf_kill(trans
->op_mode
, state
))
982 iwl_trans_pcie_stop_device(trans
);
985 static void iwl_trans_pcie_d3_suspend(struct iwl_trans
*trans
, bool test
)
987 iwl_disable_interrupts(trans
);
990 * in testing mode, the host stays awake and the
991 * hardware won't be reset (not even partially)
996 iwl_pcie_disable_ict(trans
);
998 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
999 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1000 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
1001 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
1004 * reset TX queues -- some of their registers reset during S3
1005 * so if we don't reset everything here the D3 image would try
1006 * to execute some invalid memory upon resume
1008 iwl_trans_pcie_tx_reset(trans
);
1010 iwl_pcie_set_pwr(trans
, true);
1013 static int iwl_trans_pcie_d3_resume(struct iwl_trans
*trans
,
1014 enum iwl_d3_status
*status
,
1021 iwl_enable_interrupts(trans
);
1022 *status
= IWL_D3_STATUS_ALIVE
;
1026 iwl_pcie_set_pwr(trans
, false);
1028 val
= iwl_read32(trans
, CSR_RESET
);
1029 if (val
& CSR_RESET_REG_FLAG_NEVO_RESET
) {
1030 *status
= IWL_D3_STATUS_RESET
;
1035 * Also enables interrupts - none will happen as the device doesn't
1036 * know we're waking it up, only when the opmode actually tells it
1039 iwl_pcie_reset_ict(trans
);
1041 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1042 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
1044 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
1045 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
1046 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
1049 IWL_ERR(trans
, "Failed to resume the device (mac ready)\n");
1053 iwl_trans_pcie_tx_reset(trans
);
1055 ret
= iwl_pcie_rx_init(trans
);
1057 IWL_ERR(trans
, "Failed to resume the device (RX reset)\n");
1061 *status
= IWL_D3_STATUS_ALIVE
;
1065 static int iwl_trans_pcie_start_hw(struct iwl_trans
*trans
)
1070 err
= iwl_pcie_prepare_card_hw(trans
);
1072 IWL_ERR(trans
, "Error while preparing HW: %d\n", err
);
1076 /* Reset the entire device */
1077 iwl_write32(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
1079 usleep_range(10, 15);
1081 iwl_pcie_apm_init(trans
);
1083 /* From now on, the op_mode will be kept updated about RF kill state */
1084 iwl_enable_rfkill_int(trans
);
1086 hw_rfkill
= iwl_is_rfkill_set(trans
);
1088 set_bit(STATUS_RFKILL
, &trans
->status
);
1090 clear_bit(STATUS_RFKILL
, &trans
->status
);
1091 iwl_trans_pcie_rf_kill(trans
, hw_rfkill
);
1096 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans
*trans
)
1098 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1100 /* disable interrupts - don't enable HW RF kill interrupt */
1101 spin_lock(&trans_pcie
->irq_lock
);
1102 iwl_disable_interrupts(trans
);
1103 spin_unlock(&trans_pcie
->irq_lock
);
1105 iwl_pcie_apm_stop(trans
);
1107 spin_lock(&trans_pcie
->irq_lock
);
1108 iwl_disable_interrupts(trans
);
1109 spin_unlock(&trans_pcie
->irq_lock
);
1111 iwl_pcie_disable_ict(trans
);
1114 static void iwl_trans_pcie_write8(struct iwl_trans
*trans
, u32 ofs
, u8 val
)
1116 writeb(val
, IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1119 static void iwl_trans_pcie_write32(struct iwl_trans
*trans
, u32 ofs
, u32 val
)
1121 writel(val
, IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1124 static u32
iwl_trans_pcie_read32(struct iwl_trans
*trans
, u32 ofs
)
1126 return readl(IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1129 static u32
iwl_trans_pcie_read_prph(struct iwl_trans
*trans
, u32 reg
)
1131 iwl_trans_pcie_write32(trans
, HBUS_TARG_PRPH_RADDR
,
1132 ((reg
& 0x000FFFFF) | (3 << 24)));
1133 return iwl_trans_pcie_read32(trans
, HBUS_TARG_PRPH_RDAT
);
1136 static void iwl_trans_pcie_write_prph(struct iwl_trans
*trans
, u32 addr
,
1139 iwl_trans_pcie_write32(trans
, HBUS_TARG_PRPH_WADDR
,
1140 ((addr
& 0x000FFFFF) | (3 << 24)));
1141 iwl_trans_pcie_write32(trans
, HBUS_TARG_PRPH_WDAT
, val
);
1144 static int iwl_pcie_dummy_napi_poll(struct napi_struct
*napi
, int budget
)
1150 static void iwl_trans_pcie_configure(struct iwl_trans
*trans
,
1151 const struct iwl_trans_config
*trans_cfg
)
1153 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1155 trans_pcie
->cmd_queue
= trans_cfg
->cmd_queue
;
1156 trans_pcie
->cmd_fifo
= trans_cfg
->cmd_fifo
;
1157 if (WARN_ON(trans_cfg
->n_no_reclaim_cmds
> MAX_NO_RECLAIM_CMDS
))
1158 trans_pcie
->n_no_reclaim_cmds
= 0;
1160 trans_pcie
->n_no_reclaim_cmds
= trans_cfg
->n_no_reclaim_cmds
;
1161 if (trans_pcie
->n_no_reclaim_cmds
)
1162 memcpy(trans_pcie
->no_reclaim_cmds
, trans_cfg
->no_reclaim_cmds
,
1163 trans_pcie
->n_no_reclaim_cmds
* sizeof(u8
));
1165 trans_pcie
->rx_buf_size_8k
= trans_cfg
->rx_buf_size_8k
;
1166 if (trans_pcie
->rx_buf_size_8k
)
1167 trans_pcie
->rx_page_order
= get_order(8 * 1024);
1169 trans_pcie
->rx_page_order
= get_order(4 * 1024);
1171 trans_pcie
->wd_timeout
=
1172 msecs_to_jiffies(trans_cfg
->queue_watchdog_timeout
);
1174 trans_pcie
->command_names
= trans_cfg
->command_names
;
1175 trans_pcie
->bc_table_dword
= trans_cfg
->bc_table_dword
;
1176 trans_pcie
->scd_set_active
= trans_cfg
->scd_set_active
;
1178 /* Initialize NAPI here - it should be before registering to mac80211
1179 * in the opmode but after the HW struct is allocated.
1180 * As this function may be called again in some corner cases don't
1181 * do anything if NAPI was already initialized.
1183 if (!trans_pcie
->napi
.poll
&& trans
->op_mode
->ops
->napi_add
) {
1184 init_dummy_netdev(&trans_pcie
->napi_dev
);
1185 iwl_op_mode_napi_add(trans
->op_mode
, &trans_pcie
->napi
,
1186 &trans_pcie
->napi_dev
,
1187 iwl_pcie_dummy_napi_poll
, 64);
1191 void iwl_trans_pcie_free(struct iwl_trans
*trans
)
1193 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1195 synchronize_irq(trans_pcie
->pci_dev
->irq
);
1197 iwl_pcie_tx_free(trans
);
1198 iwl_pcie_rx_free(trans
);
1200 free_irq(trans_pcie
->pci_dev
->irq
, trans
);
1201 iwl_pcie_free_ict(trans
);
1203 pci_disable_msi(trans_pcie
->pci_dev
);
1204 iounmap(trans_pcie
->hw_base
);
1205 pci_release_regions(trans_pcie
->pci_dev
);
1206 pci_disable_device(trans_pcie
->pci_dev
);
1207 kmem_cache_destroy(trans
->dev_cmd_pool
);
1209 if (trans_pcie
->napi
.poll
)
1210 netif_napi_del(&trans_pcie
->napi
);
1212 iwl_pcie_free_fw_monitor(trans
);
1217 static void iwl_trans_pcie_set_pmi(struct iwl_trans
*trans
, bool state
)
1220 set_bit(STATUS_TPOWER_PMI
, &trans
->status
);
1222 clear_bit(STATUS_TPOWER_PMI
, &trans
->status
);
1225 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans
*trans
, bool silent
,
1226 unsigned long *flags
)
1229 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1231 spin_lock_irqsave(&trans_pcie
->reg_lock
, *flags
);
1233 if (trans_pcie
->cmd_in_flight
)
1236 /* this bit wakes up the NIC */
1237 __iwl_trans_pcie_set_bit(trans
, CSR_GP_CNTRL
,
1238 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1241 * These bits say the device is running, and should keep running for
1242 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1243 * but they do not indicate that embedded SRAM is restored yet;
1244 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1245 * to/from host DRAM when sleeping/waking for power-saving.
1246 * Each direction takes approximately 1/4 millisecond; with this
1247 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1248 * series of register accesses are expected (e.g. reading Event Log),
1249 * to keep device from sleeping.
1251 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1252 * SRAM is okay/restored. We don't check that here because this call
1253 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1254 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1256 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1257 * and do not save/restore SRAM when power cycling.
1259 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
1260 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN
,
1261 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
|
1262 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP
), 15000);
1263 if (unlikely(ret
< 0)) {
1264 iwl_write32(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_FORCE_NMI
);
1266 u32 val
= iwl_read32(trans
, CSR_GP_CNTRL
);
1268 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1270 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, *flags
);
1277 * Fool sparse by faking we release the lock - sparse will
1278 * track nic_access anyway.
1280 __release(&trans_pcie
->reg_lock
);
1284 static void iwl_trans_pcie_release_nic_access(struct iwl_trans
*trans
,
1285 unsigned long *flags
)
1287 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1289 lockdep_assert_held(&trans_pcie
->reg_lock
);
1292 * Fool sparse by faking we acquiring the lock - sparse will
1293 * track nic_access anyway.
1295 __acquire(&trans_pcie
->reg_lock
);
1297 if (trans_pcie
->cmd_in_flight
)
1300 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
1301 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1303 * Above we read the CSR_GP_CNTRL register, which will flush
1304 * any previous writes, but we need the write that clears the
1305 * MAC_ACCESS_REQ bit to be performed before any other writes
1306 * scheduled on different CPUs (after we drop reg_lock).
1310 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, *flags
);
1313 static int iwl_trans_pcie_read_mem(struct iwl_trans
*trans
, u32 addr
,
1314 void *buf
, int dwords
)
1316 unsigned long flags
;
1320 if (iwl_trans_grab_nic_access(trans
, false, &flags
)) {
1321 iwl_write32(trans
, HBUS_TARG_MEM_RADDR
, addr
);
1322 for (offs
= 0; offs
< dwords
; offs
++)
1323 vals
[offs
] = iwl_read32(trans
, HBUS_TARG_MEM_RDAT
);
1324 iwl_trans_release_nic_access(trans
, &flags
);
1331 static int iwl_trans_pcie_write_mem(struct iwl_trans
*trans
, u32 addr
,
1332 const void *buf
, int dwords
)
1334 unsigned long flags
;
1336 const u32
*vals
= buf
;
1338 if (iwl_trans_grab_nic_access(trans
, false, &flags
)) {
1339 iwl_write32(trans
, HBUS_TARG_MEM_WADDR
, addr
);
1340 for (offs
= 0; offs
< dwords
; offs
++)
1341 iwl_write32(trans
, HBUS_TARG_MEM_WDAT
,
1342 vals
? vals
[offs
] : 0);
1343 iwl_trans_release_nic_access(trans
, &flags
);
1350 #define IWL_FLUSH_WAIT_MS 2000
1352 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans
*trans
, u32 txq_bm
)
1354 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1355 struct iwl_txq
*txq
;
1356 struct iwl_queue
*q
;
1358 unsigned long now
= jiffies
;
1363 /* waiting for all the tx frames complete might take a while */
1364 for (cnt
= 0; cnt
< trans
->cfg
->base_params
->num_of_queues
; cnt
++) {
1367 if (cnt
== trans_pcie
->cmd_queue
)
1369 if (!test_bit(cnt
, trans_pcie
->queue_used
))
1371 if (!(BIT(cnt
) & txq_bm
))
1374 IWL_DEBUG_TX_QUEUES(trans
, "Emptying queue %d...\n", cnt
);
1375 txq
= &trans_pcie
->txq
[cnt
];
1377 wr_ptr
= ACCESS_ONCE(q
->write_ptr
);
1379 while (q
->read_ptr
!= ACCESS_ONCE(q
->write_ptr
) &&
1380 !time_after(jiffies
,
1381 now
+ msecs_to_jiffies(IWL_FLUSH_WAIT_MS
))) {
1382 u8 write_ptr
= ACCESS_ONCE(q
->write_ptr
);
1384 if (WARN_ONCE(wr_ptr
!= write_ptr
,
1385 "WR pointer moved while flushing %d -> %d\n",
1391 if (q
->read_ptr
!= q
->write_ptr
) {
1393 "fail to flush all tx fifo queues Q %d\n", cnt
);
1397 IWL_DEBUG_TX_QUEUES(trans
, "Queue %d is now empty.\n", cnt
);
1403 IWL_ERR(trans
, "Current SW read_ptr %d write_ptr %d\n",
1404 txq
->q
.read_ptr
, txq
->q
.write_ptr
);
1406 scd_sram_addr
= trans_pcie
->scd_base_addr
+
1407 SCD_TX_STTS_QUEUE_OFFSET(txq
->q
.id
);
1408 iwl_trans_read_mem_bytes(trans
, scd_sram_addr
, buf
, sizeof(buf
));
1410 iwl_print_hex_error(trans
, buf
, sizeof(buf
));
1412 for (cnt
= 0; cnt
< FH_TCSR_CHNL_NUM
; cnt
++)
1413 IWL_ERR(trans
, "FH TRBs(%d) = 0x%08x\n", cnt
,
1414 iwl_read_direct32(trans
, FH_TX_TRB_REG(cnt
)));
1416 for (cnt
= 0; cnt
< trans
->cfg
->base_params
->num_of_queues
; cnt
++) {
1417 u32 status
= iwl_read_prph(trans
, SCD_QUEUE_STATUS_BITS(cnt
));
1418 u8 fifo
= (status
>> SCD_QUEUE_STTS_REG_POS_TXF
) & 0x7;
1419 bool active
= !!(status
& BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE
));
1421 iwl_trans_read_mem32(trans
, trans_pcie
->scd_base_addr
+
1422 SCD_TRANS_TBL_OFFSET_QUEUE(cnt
));
1425 tbl_dw
= (tbl_dw
& 0xFFFF0000) >> 16;
1427 tbl_dw
= tbl_dw
& 0x0000FFFF;
1430 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1431 cnt
, active
? "" : "in", fifo
, tbl_dw
,
1432 iwl_read_prph(trans
, SCD_QUEUE_RDPTR(cnt
)) &
1433 (TFD_QUEUE_SIZE_MAX
- 1),
1434 iwl_read_prph(trans
, SCD_QUEUE_WRPTR(cnt
)));
1440 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans
*trans
, u32 reg
,
1441 u32 mask
, u32 value
)
1443 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1444 unsigned long flags
;
1446 spin_lock_irqsave(&trans_pcie
->reg_lock
, flags
);
1447 __iwl_trans_pcie_set_bits_mask(trans
, reg
, mask
, value
);
1448 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, flags
);
1451 static const char *get_csr_string(int cmd
)
1453 #define IWL_CMD(x) case x: return #x
1455 IWL_CMD(CSR_HW_IF_CONFIG_REG
);
1456 IWL_CMD(CSR_INT_COALESCING
);
1458 IWL_CMD(CSR_INT_MASK
);
1459 IWL_CMD(CSR_FH_INT_STATUS
);
1460 IWL_CMD(CSR_GPIO_IN
);
1462 IWL_CMD(CSR_GP_CNTRL
);
1463 IWL_CMD(CSR_HW_REV
);
1464 IWL_CMD(CSR_EEPROM_REG
);
1465 IWL_CMD(CSR_EEPROM_GP
);
1466 IWL_CMD(CSR_OTP_GP_REG
);
1467 IWL_CMD(CSR_GIO_REG
);
1468 IWL_CMD(CSR_GP_UCODE_REG
);
1469 IWL_CMD(CSR_GP_DRIVER_REG
);
1470 IWL_CMD(CSR_UCODE_DRV_GP1
);
1471 IWL_CMD(CSR_UCODE_DRV_GP2
);
1472 IWL_CMD(CSR_LED_REG
);
1473 IWL_CMD(CSR_DRAM_INT_TBL_REG
);
1474 IWL_CMD(CSR_GIO_CHICKEN_BITS
);
1475 IWL_CMD(CSR_ANA_PLL_CFG
);
1476 IWL_CMD(CSR_HW_REV_WA_REG
);
1477 IWL_CMD(CSR_MONITOR_STATUS_REG
);
1478 IWL_CMD(CSR_DBG_HPET_MEM_REG
);
1485 void iwl_pcie_dump_csr(struct iwl_trans
*trans
)
1488 static const u32 csr_tbl
[] = {
1489 CSR_HW_IF_CONFIG_REG
,
1507 CSR_DRAM_INT_TBL_REG
,
1508 CSR_GIO_CHICKEN_BITS
,
1510 CSR_MONITOR_STATUS_REG
,
1512 CSR_DBG_HPET_MEM_REG
1514 IWL_ERR(trans
, "CSR values:\n");
1515 IWL_ERR(trans
, "(2nd byte of CSR_INT_COALESCING is "
1516 "CSR_INT_PERIODIC_REG)\n");
1517 for (i
= 0; i
< ARRAY_SIZE(csr_tbl
); i
++) {
1518 IWL_ERR(trans
, " %25s: 0X%08x\n",
1519 get_csr_string(csr_tbl
[i
]),
1520 iwl_read32(trans
, csr_tbl
[i
]));
1524 #ifdef CONFIG_IWLWIFI_DEBUGFS
1525 /* create and remove of files */
1526 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1527 if (!debugfs_create_file(#name, mode, parent, trans, \
1528 &iwl_dbgfs_##name##_ops)) \
1532 /* file operation */
1533 #define DEBUGFS_READ_FILE_OPS(name) \
1534 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1535 .read = iwl_dbgfs_##name##_read, \
1536 .open = simple_open, \
1537 .llseek = generic_file_llseek, \
1540 #define DEBUGFS_WRITE_FILE_OPS(name) \
1541 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1542 .write = iwl_dbgfs_##name##_write, \
1543 .open = simple_open, \
1544 .llseek = generic_file_llseek, \
1547 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1548 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1549 .write = iwl_dbgfs_##name##_write, \
1550 .read = iwl_dbgfs_##name##_read, \
1551 .open = simple_open, \
1552 .llseek = generic_file_llseek, \
1555 static ssize_t
iwl_dbgfs_tx_queue_read(struct file
*file
,
1556 char __user
*user_buf
,
1557 size_t count
, loff_t
*ppos
)
1559 struct iwl_trans
*trans
= file
->private_data
;
1560 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1561 struct iwl_txq
*txq
;
1562 struct iwl_queue
*q
;
1569 bufsz
= sizeof(char) * 64 * trans
->cfg
->base_params
->num_of_queues
;
1571 if (!trans_pcie
->txq
)
1574 buf
= kzalloc(bufsz
, GFP_KERNEL
);
1578 for (cnt
= 0; cnt
< trans
->cfg
->base_params
->num_of_queues
; cnt
++) {
1579 txq
= &trans_pcie
->txq
[cnt
];
1581 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1582 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d%s\n",
1583 cnt
, q
->read_ptr
, q
->write_ptr
,
1584 !!test_bit(cnt
, trans_pcie
->queue_used
),
1585 !!test_bit(cnt
, trans_pcie
->queue_stopped
),
1587 (cnt
== trans_pcie
->cmd_queue
? " HCMD" : ""));
1589 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1594 static ssize_t
iwl_dbgfs_rx_queue_read(struct file
*file
,
1595 char __user
*user_buf
,
1596 size_t count
, loff_t
*ppos
)
1598 struct iwl_trans
*trans
= file
->private_data
;
1599 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1600 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
;
1603 const size_t bufsz
= sizeof(buf
);
1605 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "read: %u\n",
1607 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "write: %u\n",
1609 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "write_actual: %u\n",
1611 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "need_update: %d\n",
1613 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "free_count: %u\n",
1616 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "closed_rb_num: %u\n",
1617 le16_to_cpu(rxq
->rb_stts
->closed_rb_num
) & 0x0FFF);
1619 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1620 "closed_rb_num: Not Allocated\n");
1622 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1625 static ssize_t
iwl_dbgfs_interrupt_read(struct file
*file
,
1626 char __user
*user_buf
,
1627 size_t count
, loff_t
*ppos
)
1629 struct iwl_trans
*trans
= file
->private_data
;
1630 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1631 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
1635 int bufsz
= 24 * 64; /* 24 items * 64 char per item */
1638 buf
= kzalloc(bufsz
, GFP_KERNEL
);
1642 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1643 "Interrupt Statistics Report:\n");
1645 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "HW Error:\t\t\t %u\n",
1647 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "SW Error:\t\t\t %u\n",
1649 if (isr_stats
->sw
|| isr_stats
->hw
) {
1650 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1651 "\tLast Restarting Code: 0x%X\n",
1652 isr_stats
->err_code
);
1654 #ifdef CONFIG_IWLWIFI_DEBUG
1655 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Frame transmitted:\t\t %u\n",
1657 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Alive interrupt:\t\t %u\n",
1660 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1661 "HW RF KILL switch toggled:\t %u\n", isr_stats
->rfkill
);
1663 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "CT KILL:\t\t\t %u\n",
1666 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Wakeup Interrupt:\t\t %u\n",
1669 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1670 "Rx command responses:\t\t %u\n", isr_stats
->rx
);
1672 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Tx/FH interrupt:\t\t %u\n",
1675 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Unexpected INTA:\t\t %u\n",
1676 isr_stats
->unhandled
);
1678 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1683 static ssize_t
iwl_dbgfs_interrupt_write(struct file
*file
,
1684 const char __user
*user_buf
,
1685 size_t count
, loff_t
*ppos
)
1687 struct iwl_trans
*trans
= file
->private_data
;
1688 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1689 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
1695 memset(buf
, 0, sizeof(buf
));
1696 buf_size
= min(count
, sizeof(buf
) - 1);
1697 if (copy_from_user(buf
, user_buf
, buf_size
))
1699 if (sscanf(buf
, "%x", &reset_flag
) != 1)
1701 if (reset_flag
== 0)
1702 memset(isr_stats
, 0, sizeof(*isr_stats
));
1707 static ssize_t
iwl_dbgfs_csr_write(struct file
*file
,
1708 const char __user
*user_buf
,
1709 size_t count
, loff_t
*ppos
)
1711 struct iwl_trans
*trans
= file
->private_data
;
1716 memset(buf
, 0, sizeof(buf
));
1717 buf_size
= min(count
, sizeof(buf
) - 1);
1718 if (copy_from_user(buf
, user_buf
, buf_size
))
1720 if (sscanf(buf
, "%d", &csr
) != 1)
1723 iwl_pcie_dump_csr(trans
);
1728 static ssize_t
iwl_dbgfs_fh_reg_read(struct file
*file
,
1729 char __user
*user_buf
,
1730 size_t count
, loff_t
*ppos
)
1732 struct iwl_trans
*trans
= file
->private_data
;
1736 ret
= iwl_dump_fh(trans
, &buf
);
1741 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, ret
);
1746 DEBUGFS_READ_WRITE_FILE_OPS(interrupt
);
1747 DEBUGFS_READ_FILE_OPS(fh_reg
);
1748 DEBUGFS_READ_FILE_OPS(rx_queue
);
1749 DEBUGFS_READ_FILE_OPS(tx_queue
);
1750 DEBUGFS_WRITE_FILE_OPS(csr
);
1753 * Create the debugfs files and directories
1756 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans
*trans
,
1759 DEBUGFS_ADD_FILE(rx_queue
, dir
, S_IRUSR
);
1760 DEBUGFS_ADD_FILE(tx_queue
, dir
, S_IRUSR
);
1761 DEBUGFS_ADD_FILE(interrupt
, dir
, S_IWUSR
| S_IRUSR
);
1762 DEBUGFS_ADD_FILE(csr
, dir
, S_IWUSR
);
1763 DEBUGFS_ADD_FILE(fh_reg
, dir
, S_IRUSR
);
1767 IWL_ERR(trans
, "failed to create the trans debugfs entry\n");
1771 static u32
iwl_trans_pcie_get_cmdlen(struct iwl_tfd
*tfd
)
1776 for (i
= 0; i
< IWL_NUM_OF_TBS
; i
++)
1777 cmdlen
+= iwl_pcie_tfd_tb_get_len(tfd
, i
);
1782 static const struct {
1784 } iwl_prph_dump_addr
[] = {
1785 { .start
= 0x00a00000, .end
= 0x00a00000 },
1786 { .start
= 0x00a0000c, .end
= 0x00a00024 },
1787 { .start
= 0x00a0002c, .end
= 0x00a0003c },
1788 { .start
= 0x00a00410, .end
= 0x00a00418 },
1789 { .start
= 0x00a00420, .end
= 0x00a00420 },
1790 { .start
= 0x00a00428, .end
= 0x00a00428 },
1791 { .start
= 0x00a00430, .end
= 0x00a0043c },
1792 { .start
= 0x00a00444, .end
= 0x00a00444 },
1793 { .start
= 0x00a004c0, .end
= 0x00a004cc },
1794 { .start
= 0x00a004d8, .end
= 0x00a004d8 },
1795 { .start
= 0x00a004e0, .end
= 0x00a004f0 },
1796 { .start
= 0x00a00840, .end
= 0x00a00840 },
1797 { .start
= 0x00a00850, .end
= 0x00a00858 },
1798 { .start
= 0x00a01004, .end
= 0x00a01008 },
1799 { .start
= 0x00a01010, .end
= 0x00a01010 },
1800 { .start
= 0x00a01018, .end
= 0x00a01018 },
1801 { .start
= 0x00a01024, .end
= 0x00a01024 },
1802 { .start
= 0x00a0102c, .end
= 0x00a01034 },
1803 { .start
= 0x00a0103c, .end
= 0x00a01040 },
1804 { .start
= 0x00a01048, .end
= 0x00a01094 },
1805 { .start
= 0x00a01c00, .end
= 0x00a01c20 },
1806 { .start
= 0x00a01c58, .end
= 0x00a01c58 },
1807 { .start
= 0x00a01c7c, .end
= 0x00a01c7c },
1808 { .start
= 0x00a01c28, .end
= 0x00a01c54 },
1809 { .start
= 0x00a01c5c, .end
= 0x00a01c5c },
1810 { .start
= 0x00a01c84, .end
= 0x00a01c84 },
1811 { .start
= 0x00a01ce0, .end
= 0x00a01d0c },
1812 { .start
= 0x00a01d18, .end
= 0x00a01d20 },
1813 { .start
= 0x00a01d2c, .end
= 0x00a01d30 },
1814 { .start
= 0x00a01d40, .end
= 0x00a01d5c },
1815 { .start
= 0x00a01d80, .end
= 0x00a01d80 },
1816 { .start
= 0x00a01d98, .end
= 0x00a01d98 },
1817 { .start
= 0x00a01dc0, .end
= 0x00a01dfc },
1818 { .start
= 0x00a01e00, .end
= 0x00a01e2c },
1819 { .start
= 0x00a01e40, .end
= 0x00a01e60 },
1820 { .start
= 0x00a01e84, .end
= 0x00a01e90 },
1821 { .start
= 0x00a01e9c, .end
= 0x00a01ec4 },
1822 { .start
= 0x00a01ed0, .end
= 0x00a01ed0 },
1823 { .start
= 0x00a01f00, .end
= 0x00a01f14 },
1824 { .start
= 0x00a01f44, .end
= 0x00a01f58 },
1825 { .start
= 0x00a01f80, .end
= 0x00a01fa8 },
1826 { .start
= 0x00a01fb0, .end
= 0x00a01fbc },
1827 { .start
= 0x00a01ff8, .end
= 0x00a01ffc },
1828 { .start
= 0x00a02000, .end
= 0x00a02048 },
1829 { .start
= 0x00a02068, .end
= 0x00a020f0 },
1830 { .start
= 0x00a02100, .end
= 0x00a02118 },
1831 { .start
= 0x00a02140, .end
= 0x00a0214c },
1832 { .start
= 0x00a02168, .end
= 0x00a0218c },
1833 { .start
= 0x00a021c0, .end
= 0x00a021c0 },
1834 { .start
= 0x00a02400, .end
= 0x00a02410 },
1835 { .start
= 0x00a02418, .end
= 0x00a02420 },
1836 { .start
= 0x00a02428, .end
= 0x00a0242c },
1837 { .start
= 0x00a02434, .end
= 0x00a02434 },
1838 { .start
= 0x00a02440, .end
= 0x00a02460 },
1839 { .start
= 0x00a02468, .end
= 0x00a024b0 },
1840 { .start
= 0x00a024c8, .end
= 0x00a024cc },
1841 { .start
= 0x00a02500, .end
= 0x00a02504 },
1842 { .start
= 0x00a0250c, .end
= 0x00a02510 },
1843 { .start
= 0x00a02540, .end
= 0x00a02554 },
1844 { .start
= 0x00a02580, .end
= 0x00a025f4 },
1845 { .start
= 0x00a02600, .end
= 0x00a0260c },
1846 { .start
= 0x00a02648, .end
= 0x00a02650 },
1847 { .start
= 0x00a02680, .end
= 0x00a02680 },
1848 { .start
= 0x00a026c0, .end
= 0x00a026d0 },
1849 { .start
= 0x00a02700, .end
= 0x00a0270c },
1850 { .start
= 0x00a02804, .end
= 0x00a02804 },
1851 { .start
= 0x00a02818, .end
= 0x00a0281c },
1852 { .start
= 0x00a02c00, .end
= 0x00a02db4 },
1853 { .start
= 0x00a02df4, .end
= 0x00a02fb0 },
1854 { .start
= 0x00a03000, .end
= 0x00a03014 },
1855 { .start
= 0x00a0301c, .end
= 0x00a0302c },
1856 { .start
= 0x00a03034, .end
= 0x00a03038 },
1857 { .start
= 0x00a03040, .end
= 0x00a03048 },
1858 { .start
= 0x00a03060, .end
= 0x00a03068 },
1859 { .start
= 0x00a03070, .end
= 0x00a03074 },
1860 { .start
= 0x00a0307c, .end
= 0x00a0307c },
1861 { .start
= 0x00a03080, .end
= 0x00a03084 },
1862 { .start
= 0x00a0308c, .end
= 0x00a03090 },
1863 { .start
= 0x00a03098, .end
= 0x00a03098 },
1864 { .start
= 0x00a030a0, .end
= 0x00a030a0 },
1865 { .start
= 0x00a030a8, .end
= 0x00a030b4 },
1866 { .start
= 0x00a030bc, .end
= 0x00a030bc },
1867 { .start
= 0x00a030c0, .end
= 0x00a0312c },
1868 { .start
= 0x00a03c00, .end
= 0x00a03c5c },
1869 { .start
= 0x00a04400, .end
= 0x00a04454 },
1870 { .start
= 0x00a04460, .end
= 0x00a04474 },
1871 { .start
= 0x00a044c0, .end
= 0x00a044ec },
1872 { .start
= 0x00a04500, .end
= 0x00a04504 },
1873 { .start
= 0x00a04510, .end
= 0x00a04538 },
1874 { .start
= 0x00a04540, .end
= 0x00a04548 },
1875 { .start
= 0x00a04560, .end
= 0x00a0457c },
1876 { .start
= 0x00a04590, .end
= 0x00a04598 },
1877 { .start
= 0x00a045c0, .end
= 0x00a045f4 },
1880 static u32
iwl_trans_pcie_dump_prph(struct iwl_trans
*trans
,
1881 struct iwl_fw_error_dump_data
**data
)
1883 struct iwl_fw_error_dump_prph
*prph
;
1884 unsigned long flags
;
1885 u32 prph_len
= 0, i
;
1887 if (!iwl_trans_grab_nic_access(trans
, false, &flags
))
1890 for (i
= 0; i
< ARRAY_SIZE(iwl_prph_dump_addr
); i
++) {
1891 /* The range includes both boundaries */
1892 int num_bytes_in_chunk
= iwl_prph_dump_addr
[i
].end
-
1893 iwl_prph_dump_addr
[i
].start
+ 4;
1897 prph_len
+= sizeof(*data
) + sizeof(*prph
) +
1900 (*data
)->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH
);
1901 (*data
)->len
= cpu_to_le32(sizeof(*prph
) +
1902 num_bytes_in_chunk
);
1903 prph
= (void *)(*data
)->data
;
1904 prph
->prph_start
= cpu_to_le32(iwl_prph_dump_addr
[i
].start
);
1905 val
= (void *)prph
->data
;
1907 for (reg
= iwl_prph_dump_addr
[i
].start
;
1908 reg
<= iwl_prph_dump_addr
[i
].end
;
1910 *val
++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans
,
1912 *data
= iwl_fw_error_next_data(*data
);
1915 iwl_trans_release_nic_access(trans
, &flags
);
1920 #define IWL_CSR_TO_DUMP (0x250)
1922 static u32
iwl_trans_pcie_dump_csr(struct iwl_trans
*trans
,
1923 struct iwl_fw_error_dump_data
**data
)
1925 u32 csr_len
= sizeof(**data
) + IWL_CSR_TO_DUMP
;
1929 (*data
)->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_CSR
);
1930 (*data
)->len
= cpu_to_le32(IWL_CSR_TO_DUMP
);
1931 val
= (void *)(*data
)->data
;
1933 for (i
= 0; i
< IWL_CSR_TO_DUMP
; i
+= 4)
1934 *val
++ = cpu_to_le32(iwl_trans_pcie_read32(trans
, i
));
1936 *data
= iwl_fw_error_next_data(*data
);
1942 struct iwl_trans_dump_data
*iwl_trans_pcie_dump_data(struct iwl_trans
*trans
)
1944 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1945 struct iwl_fw_error_dump_data
*data
;
1946 struct iwl_txq
*cmdq
= &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
1947 struct iwl_fw_error_dump_txcmd
*txcmd
;
1948 struct iwl_trans_dump_data
*dump_data
;
1952 /* transport dump header */
1953 len
= sizeof(*dump_data
);
1956 len
+= sizeof(*data
) +
1957 cmdq
->q
.n_window
* (sizeof(*txcmd
) + TFD_MAX_PAYLOAD_SIZE
);
1960 len
+= sizeof(*data
) + IWL_CSR_TO_DUMP
;
1962 /* PRPH registers */
1963 for (i
= 0; i
< ARRAY_SIZE(iwl_prph_dump_addr
); i
++) {
1964 /* The range includes both boundaries */
1965 int num_bytes_in_chunk
= iwl_prph_dump_addr
[i
].end
-
1966 iwl_prph_dump_addr
[i
].start
+ 4;
1968 len
+= sizeof(*data
) + sizeof(struct iwl_fw_error_dump_prph
) +
1973 if (trans_pcie
->fw_mon_page
)
1974 len
+= sizeof(*data
) + sizeof(struct iwl_fw_error_dump_fw_mon
) +
1975 trans_pcie
->fw_mon_size
;
1977 dump_data
= vzalloc(len
);
1982 data
= (void *)dump_data
->data
;
1983 data
->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD
);
1984 txcmd
= (void *)data
->data
;
1985 spin_lock_bh(&cmdq
->lock
);
1986 ptr
= cmdq
->q
.write_ptr
;
1987 for (i
= 0; i
< cmdq
->q
.n_window
; i
++) {
1988 u8 idx
= get_cmd_index(&cmdq
->q
, ptr
);
1991 cmdlen
= iwl_trans_pcie_get_cmdlen(&cmdq
->tfds
[ptr
]);
1992 caplen
= min_t(u32
, TFD_MAX_PAYLOAD_SIZE
, cmdlen
);
1995 len
+= sizeof(*txcmd
) + caplen
;
1996 txcmd
->cmdlen
= cpu_to_le32(cmdlen
);
1997 txcmd
->caplen
= cpu_to_le32(caplen
);
1998 memcpy(txcmd
->data
, cmdq
->entries
[idx
].cmd
, caplen
);
1999 txcmd
= (void *)((u8
*)txcmd
->data
+ caplen
);
2002 ptr
= iwl_queue_dec_wrap(ptr
);
2004 spin_unlock_bh(&cmdq
->lock
);
2006 data
->len
= cpu_to_le32(len
);
2007 len
+= sizeof(*data
);
2008 data
= iwl_fw_error_next_data(data
);
2010 len
+= iwl_trans_pcie_dump_prph(trans
, &data
);
2011 len
+= iwl_trans_pcie_dump_csr(trans
, &data
);
2012 /* data is already pointing to the next section */
2014 if (trans_pcie
->fw_mon_page
) {
2015 struct iwl_fw_error_dump_fw_mon
*fw_mon_data
;
2017 data
->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR
);
2018 data
->len
= cpu_to_le32(trans_pcie
->fw_mon_size
+
2019 sizeof(*fw_mon_data
));
2020 fw_mon_data
= (void *)data
->data
;
2021 fw_mon_data
->fw_mon_wr_ptr
=
2022 cpu_to_le32(iwl_read_prph(trans
, MON_BUFF_WRPTR
));
2023 fw_mon_data
->fw_mon_cycle_cnt
=
2024 cpu_to_le32(iwl_read_prph(trans
, MON_BUFF_CYCLE_CNT
));
2025 fw_mon_data
->fw_mon_base_ptr
=
2026 cpu_to_le32(iwl_read_prph(trans
, MON_BUFF_BASE_ADDR
));
2029 * The firmware is now asserted, it won't write anything to
2030 * the buffer. CPU can take ownership to fetch the data.
2031 * The buffer will be handed back to the device before the
2032 * firmware will be restarted.
2034 dma_sync_single_for_cpu(trans
->dev
, trans_pcie
->fw_mon_phys
,
2035 trans_pcie
->fw_mon_size
,
2037 memcpy(fw_mon_data
->data
, page_address(trans_pcie
->fw_mon_page
),
2038 trans_pcie
->fw_mon_size
);
2040 len
+= sizeof(*data
) + sizeof(*fw_mon_data
) +
2041 trans_pcie
->fw_mon_size
;
2044 dump_data
->len
= len
;
2049 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans
*trans
,
2054 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2056 static const struct iwl_trans_ops trans_ops_pcie
= {
2057 .start_hw
= iwl_trans_pcie_start_hw
,
2058 .op_mode_leave
= iwl_trans_pcie_op_mode_leave
,
2059 .fw_alive
= iwl_trans_pcie_fw_alive
,
2060 .start_fw
= iwl_trans_pcie_start_fw
,
2061 .stop_device
= iwl_trans_pcie_stop_device
,
2063 .d3_suspend
= iwl_trans_pcie_d3_suspend
,
2064 .d3_resume
= iwl_trans_pcie_d3_resume
,
2066 .send_cmd
= iwl_trans_pcie_send_hcmd
,
2068 .tx
= iwl_trans_pcie_tx
,
2069 .reclaim
= iwl_trans_pcie_reclaim
,
2071 .txq_disable
= iwl_trans_pcie_txq_disable
,
2072 .txq_enable
= iwl_trans_pcie_txq_enable
,
2074 .dbgfs_register
= iwl_trans_pcie_dbgfs_register
,
2076 .wait_tx_queue_empty
= iwl_trans_pcie_wait_txq_empty
,
2078 .write8
= iwl_trans_pcie_write8
,
2079 .write32
= iwl_trans_pcie_write32
,
2080 .read32
= iwl_trans_pcie_read32
,
2081 .read_prph
= iwl_trans_pcie_read_prph
,
2082 .write_prph
= iwl_trans_pcie_write_prph
,
2083 .read_mem
= iwl_trans_pcie_read_mem
,
2084 .write_mem
= iwl_trans_pcie_write_mem
,
2085 .configure
= iwl_trans_pcie_configure
,
2086 .set_pmi
= iwl_trans_pcie_set_pmi
,
2087 .grab_nic_access
= iwl_trans_pcie_grab_nic_access
,
2088 .release_nic_access
= iwl_trans_pcie_release_nic_access
,
2089 .set_bits_mask
= iwl_trans_pcie_set_bits_mask
,
2091 #ifdef CONFIG_IWLWIFI_DEBUGFS
2092 .dump_data
= iwl_trans_pcie_dump_data
,
2096 struct iwl_trans
*iwl_trans_pcie_alloc(struct pci_dev
*pdev
,
2097 const struct pci_device_id
*ent
,
2098 const struct iwl_cfg
*cfg
)
2100 struct iwl_trans_pcie
*trans_pcie
;
2101 struct iwl_trans
*trans
;
2105 trans
= kzalloc(sizeof(struct iwl_trans
) +
2106 sizeof(struct iwl_trans_pcie
), GFP_KERNEL
);
2112 trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2114 trans
->ops
= &trans_ops_pcie
;
2116 trans_lockdep_init(trans
);
2117 trans_pcie
->trans
= trans
;
2118 spin_lock_init(&trans_pcie
->irq_lock
);
2119 spin_lock_init(&trans_pcie
->reg_lock
);
2120 init_waitqueue_head(&trans_pcie
->ucode_write_waitq
);
2122 err
= pci_enable_device(pdev
);
2126 if (!cfg
->base_params
->pcie_l1_allowed
) {
2128 * W/A - seems to solve weird behavior. We need to remove this
2129 * if we don't want to stay in L1 all the time. This wastes a
2132 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
|
2133 PCIE_LINK_STATE_L1
|
2134 PCIE_LINK_STATE_CLKPM
);
2137 pci_set_master(pdev
);
2139 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(36));
2141 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(36));
2143 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
2145 err
= pci_set_consistent_dma_mask(pdev
,
2147 /* both attempts failed: */
2149 dev_err(&pdev
->dev
, "No suitable DMA available\n");
2150 goto out_pci_disable_device
;
2154 err
= pci_request_regions(pdev
, DRV_NAME
);
2156 dev_err(&pdev
->dev
, "pci_request_regions failed\n");
2157 goto out_pci_disable_device
;
2160 trans_pcie
->hw_base
= pci_ioremap_bar(pdev
, 0);
2161 if (!trans_pcie
->hw_base
) {
2162 dev_err(&pdev
->dev
, "pci_ioremap_bar failed\n");
2164 goto out_pci_release_regions
;
2167 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2168 * PCI Tx retries from interfering with C3 CPU state */
2169 pci_write_config_byte(pdev
, PCI_CFG_RETRY_TIMEOUT
, 0x00);
2171 trans
->dev
= &pdev
->dev
;
2172 trans_pcie
->pci_dev
= pdev
;
2173 iwl_disable_interrupts(trans
);
2175 err
= pci_enable_msi(pdev
);
2177 dev_err(&pdev
->dev
, "pci_enable_msi failed(0X%x)\n", err
);
2178 /* enable rfkill interrupt: hw bug w/a */
2179 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
2180 if (pci_cmd
& PCI_COMMAND_INTX_DISABLE
) {
2181 pci_cmd
&= ~PCI_COMMAND_INTX_DISABLE
;
2182 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
2186 trans
->hw_rev
= iwl_read32(trans
, CSR_HW_REV
);
2188 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2189 * changed, and now the revision step also includes bit 0-1 (no more
2190 * "dash" value). To keep hw_rev backwards compatible - we'll store it
2191 * in the old format.
2193 if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_8000
)
2194 trans
->hw_rev
= (trans
->hw_rev
& 0xfff0) |
2195 (CSR_HW_REV_STEP(trans
->hw_rev
<< 2) << 2);
2197 trans
->hw_id
= (pdev
->device
<< 16) + pdev
->subsystem_device
;
2198 snprintf(trans
->hw_id_str
, sizeof(trans
->hw_id_str
),
2199 "PCI ID: 0x%04X:0x%04X", pdev
->device
, pdev
->subsystem_device
);
2201 /* Initialize the wait queue for commands */
2202 init_waitqueue_head(&trans_pcie
->wait_command_queue
);
2204 snprintf(trans
->dev_cmd_pool_name
, sizeof(trans
->dev_cmd_pool_name
),
2205 "iwl_cmd_pool:%s", dev_name(trans
->dev
));
2207 trans
->dev_cmd_headroom
= 0;
2208 trans
->dev_cmd_pool
=
2209 kmem_cache_create(trans
->dev_cmd_pool_name
,
2210 sizeof(struct iwl_device_cmd
)
2211 + trans
->dev_cmd_headroom
,
2216 if (!trans
->dev_cmd_pool
) {
2218 goto out_pci_disable_msi
;
2221 if (iwl_pcie_alloc_ict(trans
))
2222 goto out_free_cmd_pool
;
2224 err
= request_threaded_irq(pdev
->irq
, iwl_pcie_isr
,
2225 iwl_pcie_irq_handler
,
2226 IRQF_SHARED
, DRV_NAME
, trans
);
2228 IWL_ERR(trans
, "Error allocating IRQ %d\n", pdev
->irq
);
2232 trans_pcie
->inta_mask
= CSR_INI_SET_MASK
;
2237 iwl_pcie_free_ict(trans
);
2239 kmem_cache_destroy(trans
->dev_cmd_pool
);
2240 out_pci_disable_msi
:
2241 pci_disable_msi(pdev
);
2242 out_pci_release_regions
:
2243 pci_release_regions(pdev
);
2244 out_pci_disable_device
:
2245 pci_disable_device(pdev
);
2249 return ERR_PTR(err
);