1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
25 * The full GNU General Public License is included in this distribution
26 * in the file called COPYING.
28 * Contact Information:
29 * Intel Linux Wireless <ilw@linux.intel.com>
30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
34 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
35 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
36 * All rights reserved.
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
64 *****************************************************************************/
65 #include <linux/pci.h>
66 #include <linux/pci-aspm.h>
67 #include <linux/interrupt.h>
68 #include <linux/debugfs.h>
69 #include <linux/sched.h>
70 #include <linux/bitops.h>
71 #include <linux/gfp.h>
72 #include <linux/vmalloc.h>
75 #include "iwl-trans.h"
79 #include "iwl-agn-hw.h"
80 #include "iwl-fw-error-dump.h"
84 /* extended range in FW SRAM */
85 #define IWL_FW_MEM_EXTENDED_START 0x40000
86 #define IWL_FW_MEM_EXTENDED_END 0x57FFF
88 static void iwl_pcie_free_fw_monitor(struct iwl_trans
*trans
)
90 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
92 if (!trans_pcie
->fw_mon_page
)
95 dma_unmap_page(trans
->dev
, trans_pcie
->fw_mon_phys
,
96 trans_pcie
->fw_mon_size
, DMA_FROM_DEVICE
);
97 __free_pages(trans_pcie
->fw_mon_page
,
98 get_order(trans_pcie
->fw_mon_size
));
99 trans_pcie
->fw_mon_page
= NULL
;
100 trans_pcie
->fw_mon_phys
= 0;
101 trans_pcie
->fw_mon_size
= 0;
104 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans
*trans
, u8 max_power
)
106 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
107 struct page
*page
= NULL
;
113 /* default max_power is maximum */
119 if (WARN(max_power
> 26,
120 "External buffer size for monitor is too big %d, check the FW TLV\n",
124 if (trans_pcie
->fw_mon_page
) {
125 dma_sync_single_for_device(trans
->dev
, trans_pcie
->fw_mon_phys
,
126 trans_pcie
->fw_mon_size
,
132 for (power
= max_power
; power
>= 11; power
--) {
136 order
= get_order(size
);
137 page
= alloc_pages(__GFP_COMP
| __GFP_NOWARN
| __GFP_ZERO
,
142 phys
= dma_map_page(trans
->dev
, page
, 0, PAGE_SIZE
<< order
,
144 if (dma_mapping_error(trans
->dev
, phys
)) {
145 __free_pages(page
, order
);
150 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
155 if (WARN_ON_ONCE(!page
))
158 if (power
!= max_power
)
160 "Sorry - debug buffer is only %luK while you requested %luK\n",
161 (unsigned long)BIT(power
- 10),
162 (unsigned long)BIT(max_power
- 10));
164 trans_pcie
->fw_mon_page
= page
;
165 trans_pcie
->fw_mon_phys
= phys
;
166 trans_pcie
->fw_mon_size
= size
;
169 static u32
iwl_trans_pcie_read_shr(struct iwl_trans
*trans
, u32 reg
)
171 iwl_write32(trans
, HEEP_CTRL_WRD_PCIEX_CTRL_REG
,
172 ((reg
& 0x0000ffff) | (2 << 28)));
173 return iwl_read32(trans
, HEEP_CTRL_WRD_PCIEX_DATA_REG
);
176 static void iwl_trans_pcie_write_shr(struct iwl_trans
*trans
, u32 reg
, u32 val
)
178 iwl_write32(trans
, HEEP_CTRL_WRD_PCIEX_DATA_REG
, val
);
179 iwl_write32(trans
, HEEP_CTRL_WRD_PCIEX_CTRL_REG
,
180 ((reg
& 0x0000ffff) | (3 << 28)));
183 static void iwl_pcie_set_pwr(struct iwl_trans
*trans
, bool vaux
)
185 if (!trans
->cfg
->apmg_not_supported
)
188 if (vaux
&& pci_pme_capable(to_pci_dev(trans
->dev
), PCI_D3cold
))
189 iwl_set_bits_mask_prph(trans
, APMG_PS_CTRL_REG
,
190 APMG_PS_CTRL_VAL_PWR_SRC_VAUX
,
191 ~APMG_PS_CTRL_MSK_PWR_SRC
);
193 iwl_set_bits_mask_prph(trans
, APMG_PS_CTRL_REG
,
194 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN
,
195 ~APMG_PS_CTRL_MSK_PWR_SRC
);
199 #define PCI_CFG_RETRY_TIMEOUT 0x041
201 static void iwl_pcie_apm_config(struct iwl_trans
*trans
)
203 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
208 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
209 * Check if BIOS (or OS) enabled L1-ASPM on this device.
210 * If so (likely), disable L0S, so device moves directly L0->L1;
211 * costs negligible amount of power savings.
212 * If not (unlikely), enable L0S, so there is at least some
213 * power savings, even without L1.
215 pcie_capability_read_word(trans_pcie
->pci_dev
, PCI_EXP_LNKCTL
, &lctl
);
216 if (lctl
& PCI_EXP_LNKCTL_ASPM_L1
)
217 iwl_set_bit(trans
, CSR_GIO_REG
, CSR_GIO_REG_VAL_L0S_ENABLED
);
219 iwl_clear_bit(trans
, CSR_GIO_REG
, CSR_GIO_REG_VAL_L0S_ENABLED
);
220 trans
->pm_support
= !(lctl
& PCI_EXP_LNKCTL_ASPM_L0S
);
222 pcie_capability_read_word(trans_pcie
->pci_dev
, PCI_EXP_DEVCTL2
, &cap
);
223 trans
->ltr_enabled
= cap
& PCI_EXP_DEVCTL2_LTR_EN
;
224 dev_info(trans
->dev
, "L1 %sabled - LTR %sabled\n",
225 (lctl
& PCI_EXP_LNKCTL_ASPM_L1
) ? "En" : "Dis",
226 trans
->ltr_enabled
? "En" : "Dis");
230 * Start up NIC's basic functionality after it has been reset
231 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
232 * NOTE: This does not load uCode nor start the embedded processor
234 static int iwl_pcie_apm_init(struct iwl_trans
*trans
)
237 IWL_DEBUG_INFO(trans
, "Init card's basic functions\n");
240 * Use "set_bit" below rather than "write", to preserve any hardware
241 * bits already set by default after reset.
244 /* Disable L0S exit timer (platform NMI Work/Around) */
245 if (trans
->cfg
->device_family
!= IWL_DEVICE_FAMILY_8000
)
246 iwl_set_bit(trans
, CSR_GIO_CHICKEN_BITS
,
247 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER
);
250 * Disable L0s without affecting L1;
251 * don't wait for ICH L0s (ICH bug W/A)
253 iwl_set_bit(trans
, CSR_GIO_CHICKEN_BITS
,
254 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX
);
256 /* Set FH wait threshold to maximum (HW error during stress W/A) */
257 iwl_set_bit(trans
, CSR_DBG_HPET_MEM_REG
, CSR_DBG_HPET_MEM_REG_VAL
);
260 * Enable HAP INTA (interrupt from management bus) to
261 * wake device's PCI Express link L1a -> L0s
263 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
264 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A
);
266 iwl_pcie_apm_config(trans
);
268 /* Configure analog phase-lock-loop before activating to D0A */
269 if (trans
->cfg
->base_params
->pll_cfg_val
)
270 iwl_set_bit(trans
, CSR_ANA_PLL_CFG
,
271 trans
->cfg
->base_params
->pll_cfg_val
);
274 * Set "initialization complete" bit to move adapter from
275 * D0U* --> D0A* (powered-up active) state.
277 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
280 * Wait for clock stabilization; once stabilized, access to
281 * device-internal resources is supported, e.g. iwl_write_prph()
282 * and accesses to uCode SRAM.
284 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
285 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
286 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
, 25000);
288 IWL_DEBUG_INFO(trans
, "Failed to init the card\n");
292 if (trans
->cfg
->host_interrupt_operation_mode
) {
294 * This is a bit of an abuse - This is needed for 7260 / 3160
295 * only check host_interrupt_operation_mode even if this is
296 * not related to host_interrupt_operation_mode.
298 * Enable the oscillator to count wake up time for L1 exit. This
299 * consumes slightly more power (100uA) - but allows to be sure
300 * that we wake up from L1 on time.
302 * This looks weird: read twice the same register, discard the
303 * value, set a bit, and yet again, read that same register
304 * just to discard the value. But that's the way the hardware
307 iwl_read_prph(trans
, OSC_CLK
);
308 iwl_read_prph(trans
, OSC_CLK
);
309 iwl_set_bits_prph(trans
, OSC_CLK
, OSC_CLK_FORCE_CONTROL
);
310 iwl_read_prph(trans
, OSC_CLK
);
311 iwl_read_prph(trans
, OSC_CLK
);
315 * Enable DMA clock and wait for it to stabilize.
317 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
318 * bits do not disable clocks. This preserves any hardware
319 * bits already set by default in "CLK_CTRL_REG" after reset.
321 if (!trans
->cfg
->apmg_not_supported
) {
322 iwl_write_prph(trans
, APMG_CLK_EN_REG
,
323 APMG_CLK_VAL_DMA_CLK_RQT
);
326 /* Disable L1-Active */
327 iwl_set_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
328 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
330 /* Clear the interrupt in APMG if the NIC is in RFKILL */
331 iwl_write_prph(trans
, APMG_RTC_INT_STT_REG
,
332 APMG_RTC_INT_STT_RFKILL
);
335 set_bit(STATUS_DEVICE_ENABLED
, &trans
->status
);
342 * Enable LP XTAL to avoid HW bug where device may consume much power if
343 * FW is not loaded after device reset. LP XTAL is disabled by default
344 * after device HW reset. Do it only if XTAL is fed by internal source.
345 * Configure device's "persistence" mode to avoid resetting XTAL again when
346 * SHRD_HW_RST occurs in S3.
348 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans
*trans
)
352 u32 apmg_xtal_cfg_reg
;
356 __iwl_trans_pcie_set_bit(trans
, CSR_GP_CNTRL
,
357 CSR_GP_CNTRL_REG_FLAG_XTAL_ON
);
359 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
360 iwl_set_bit(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
365 * Set "initialization complete" bit to move adapter from
366 * D0U* --> D0A* (powered-up active) state.
368 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
371 * Wait for clock stabilization; once stabilized, access to
372 * device-internal resources is possible.
374 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
375 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
376 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
378 if (WARN_ON(ret
< 0)) {
379 IWL_ERR(trans
, "Access time out - failed to enable LP XTAL\n");
380 /* Release XTAL ON request */
381 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
382 CSR_GP_CNTRL_REG_FLAG_XTAL_ON
);
387 * Clear "disable persistence" to avoid LP XTAL resetting when
388 * SHRD_HW_RST is applied in S3.
390 iwl_clear_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
391 APMG_PCIDEV_STT_VAL_PERSIST_DIS
);
394 * Force APMG XTAL to be active to prevent its disabling by HW
395 * caused by APMG idle state.
397 apmg_xtal_cfg_reg
= iwl_trans_pcie_read_shr(trans
,
398 SHR_APMG_XTAL_CFG_REG
);
399 iwl_trans_pcie_write_shr(trans
, SHR_APMG_XTAL_CFG_REG
,
401 SHR_APMG_XTAL_CFG_XTAL_ON_REQ
);
404 * Reset entire device again - do controller reset (results in
405 * SHRD_HW_RST). Turn MAC off before proceeding.
407 iwl_set_bit(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
411 /* Enable LP XTAL by indirect access through CSR */
412 apmg_gp1_reg
= iwl_trans_pcie_read_shr(trans
, SHR_APMG_GP1_REG
);
413 iwl_trans_pcie_write_shr(trans
, SHR_APMG_GP1_REG
, apmg_gp1_reg
|
414 SHR_APMG_GP1_WF_XTAL_LP_EN
|
415 SHR_APMG_GP1_CHICKEN_BIT_SELECT
);
417 /* Clear delay line clock power up */
418 dl_cfg_reg
= iwl_trans_pcie_read_shr(trans
, SHR_APMG_DL_CFG_REG
);
419 iwl_trans_pcie_write_shr(trans
, SHR_APMG_DL_CFG_REG
, dl_cfg_reg
&
420 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP
);
423 * Enable persistence mode to avoid LP XTAL resetting when
424 * SHRD_HW_RST is applied in S3.
426 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
427 CSR_HW_IF_CONFIG_REG_PERSIST_MODE
);
430 * Clear "initialization complete" bit to move adapter from
431 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
433 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
434 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
436 /* Activates XTAL resources monitor */
437 __iwl_trans_pcie_set_bit(trans
, CSR_MONITOR_CFG_REG
,
438 CSR_MONITOR_XTAL_RESOURCES
);
440 /* Release XTAL ON request */
441 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
442 CSR_GP_CNTRL_REG_FLAG_XTAL_ON
);
445 /* Release APMG XTAL */
446 iwl_trans_pcie_write_shr(trans
, SHR_APMG_XTAL_CFG_REG
,
448 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ
);
451 static int iwl_pcie_apm_stop_master(struct iwl_trans
*trans
)
455 /* stop device's busmaster DMA activity */
456 iwl_set_bit(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_STOP_MASTER
);
458 ret
= iwl_poll_bit(trans
, CSR_RESET
,
459 CSR_RESET_REG_FLAG_MASTER_DISABLED
,
460 CSR_RESET_REG_FLAG_MASTER_DISABLED
, 100);
462 IWL_WARN(trans
, "Master Disable Timed Out, 100 usec\n");
464 IWL_DEBUG_INFO(trans
, "stop master\n");
469 static void iwl_pcie_apm_stop(struct iwl_trans
*trans
, bool op_mode_leave
)
471 IWL_DEBUG_INFO(trans
, "Stop card, put in low power state\n");
474 if (!test_bit(STATUS_DEVICE_ENABLED
, &trans
->status
))
475 iwl_pcie_apm_init(trans
);
477 /* inform ME that we are leaving */
478 if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_7000
)
479 iwl_set_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
480 APMG_PCIDEV_STT_VAL_WAKE_ME
);
481 else if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_8000
)
482 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
483 CSR_HW_IF_CONFIG_REG_PREPARE
|
484 CSR_HW_IF_CONFIG_REG_ENABLE_PME
);
488 clear_bit(STATUS_DEVICE_ENABLED
, &trans
->status
);
490 /* Stop device's DMA activity */
491 iwl_pcie_apm_stop_master(trans
);
493 if (trans
->cfg
->lp_xtal_workaround
) {
494 iwl_pcie_apm_lp_xtal_enable(trans
);
498 /* Reset the entire device */
499 iwl_set_bit(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
504 * Clear "initialization complete" bit to move adapter from
505 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
507 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
508 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
511 static int iwl_pcie_nic_init(struct iwl_trans
*trans
)
513 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
516 spin_lock(&trans_pcie
->irq_lock
);
517 iwl_pcie_apm_init(trans
);
519 spin_unlock(&trans_pcie
->irq_lock
);
521 iwl_pcie_set_pwr(trans
, false);
523 iwl_op_mode_nic_config(trans
->op_mode
);
525 /* Allocate the RX queue, or reset if it is already allocated */
526 iwl_pcie_rx_init(trans
);
528 /* Allocate or reset and init all Tx and Command queues */
529 if (iwl_pcie_tx_init(trans
))
532 if (trans
->cfg
->base_params
->shadow_reg_enable
) {
533 /* enable shadow regs in HW */
534 iwl_set_bit(trans
, CSR_MAC_SHADOW_REG_CTRL
, 0x800FFFFF);
535 IWL_DEBUG_INFO(trans
, "Enabling shadow registers in device\n");
541 #define HW_READY_TIMEOUT (50)
543 /* Note: returns poll_bit return value, which is >= 0 if success */
544 static int iwl_pcie_set_hw_ready(struct iwl_trans
*trans
)
548 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
549 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
);
551 /* See if we got it */
552 ret
= iwl_poll_bit(trans
, CSR_HW_IF_CONFIG_REG
,
553 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
554 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
558 iwl_set_bit(trans
, CSR_MBOX_SET_REG
, CSR_MBOX_SET_REG_OS_ALIVE
);
560 IWL_DEBUG_INFO(trans
, "hardware%s ready\n", ret
< 0 ? " not" : "");
564 /* Note: returns standard 0/-ERROR code */
565 static int iwl_pcie_prepare_card_hw(struct iwl_trans
*trans
)
571 IWL_DEBUG_INFO(trans
, "iwl_trans_prepare_card_hw enter\n");
573 ret
= iwl_pcie_set_hw_ready(trans
);
574 /* If the card is ready, exit 0 */
578 for (iter
= 0; iter
< 10; iter
++) {
579 /* If HW is not ready, prepare the conditions to check again */
580 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
581 CSR_HW_IF_CONFIG_REG_PREPARE
);
584 ret
= iwl_pcie_set_hw_ready(trans
);
588 usleep_range(200, 1000);
590 } while (t
< 150000);
594 IWL_ERR(trans
, "Couldn't prepare the card\n");
602 static int iwl_pcie_load_firmware_chunk(struct iwl_trans
*trans
, u32 dst_addr
,
603 dma_addr_t phy_addr
, u32 byte_cnt
)
605 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
608 trans_pcie
->ucode_write_complete
= false;
610 iwl_write_direct32(trans
,
611 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
612 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE
);
614 iwl_write_direct32(trans
,
615 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL
),
618 iwl_write_direct32(trans
,
619 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL
),
620 phy_addr
& FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK
);
622 iwl_write_direct32(trans
,
623 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL
),
624 (iwl_get_dma_hi_addr(phy_addr
)
625 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT
) | byte_cnt
);
627 iwl_write_direct32(trans
,
628 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL
),
629 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM
|
630 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX
|
631 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID
);
633 iwl_write_direct32(trans
,
634 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
635 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
636 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE
|
637 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD
);
639 ret
= wait_event_timeout(trans_pcie
->ucode_write_waitq
,
640 trans_pcie
->ucode_write_complete
, 5 * HZ
);
642 IWL_ERR(trans
, "Failed to load firmware chunk!\n");
649 static int iwl_pcie_load_section(struct iwl_trans
*trans
, u8 section_num
,
650 const struct fw_desc
*section
)
654 u32 offset
, chunk_sz
= min_t(u32
, FH_MEM_TB_MAX_LENGTH
, section
->len
);
657 IWL_DEBUG_FW(trans
, "[%d] uCode section being loaded...\n",
660 v_addr
= dma_alloc_coherent(trans
->dev
, chunk_sz
, &p_addr
,
661 GFP_KERNEL
| __GFP_NOWARN
);
663 IWL_DEBUG_INFO(trans
, "Falling back to small chunks of DMA\n");
664 chunk_sz
= PAGE_SIZE
;
665 v_addr
= dma_alloc_coherent(trans
->dev
, chunk_sz
,
666 &p_addr
, GFP_KERNEL
);
671 for (offset
= 0; offset
< section
->len
; offset
+= chunk_sz
) {
672 u32 copy_size
, dst_addr
;
673 bool extended_addr
= false;
675 copy_size
= min_t(u32
, chunk_sz
, section
->len
- offset
);
676 dst_addr
= section
->offset
+ offset
;
678 if (dst_addr
>= IWL_FW_MEM_EXTENDED_START
&&
679 dst_addr
<= IWL_FW_MEM_EXTENDED_END
)
680 extended_addr
= true;
683 iwl_set_bits_prph(trans
, LMPM_CHICK
,
684 LMPM_CHICK_EXTENDED_ADDR_SPACE
);
686 memcpy(v_addr
, (u8
*)section
->data
+ offset
, copy_size
);
687 ret
= iwl_pcie_load_firmware_chunk(trans
, dst_addr
, p_addr
,
691 iwl_clear_bits_prph(trans
, LMPM_CHICK
,
692 LMPM_CHICK_EXTENDED_ADDR_SPACE
);
696 "Could not load the [%d] uCode section\n",
702 dma_free_coherent(trans
->dev
, chunk_sz
, v_addr
, p_addr
);
707 * Driver Takes the ownership on secure machine before FW load
708 * and prevent race with the BT load.
709 * W/A for ROM bug. (should be remove in the next Si step)
711 static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans
*trans
)
713 u32 val
, loop
= 1000;
716 * Check the RSA semaphore is accessible.
717 * If the HW isn't locked and the rsa semaphore isn't accessible,
720 val
= iwl_read_prph(trans
, PREG_AUX_BUS_WPROT_0
);
721 if (val
& (BIT(1) | BIT(17))) {
723 "can't access the RSA semaphore it is write protected\n");
727 /* take ownership on the AUX IF */
728 iwl_write_prph(trans
, WFPM_CTRL_REG
, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK
);
729 iwl_write_prph(trans
, AUX_MISC_MASTER1_EN
, AUX_MISC_MASTER1_EN_SBE_MSK
);
732 iwl_write_prph(trans
, AUX_MISC_MASTER1_SMPHR_STATUS
, 0x1);
733 val
= iwl_read_prph(trans
, AUX_MISC_MASTER1_SMPHR_STATUS
);
735 iwl_write_prph(trans
, RSA_ENABLE
, 0);
743 IWL_ERR(trans
, "Failed to take ownership on secure machine\n");
747 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans
*trans
,
748 const struct fw_img
*image
,
750 int *first_ucode_section
)
753 int i
, ret
= 0, sec_num
= 0x1;
754 u32 val
, last_read_idx
= 0;
758 *first_ucode_section
= 0;
761 (*first_ucode_section
)++;
764 for (i
= *first_ucode_section
; i
< IWL_UCODE_SECTION_MAX
; i
++) {
767 if (!image
->sec
[i
].data
||
768 image
->sec
[i
].offset
== CPU1_CPU2_SEPARATOR_SECTION
) {
770 "Break since Data not valid or Empty section, sec = %d\n",
775 ret
= iwl_pcie_load_section(trans
, i
, &image
->sec
[i
]);
779 /* Notify the ucode of the loaded section number and status */
780 val
= iwl_read_direct32(trans
, FH_UCODE_LOAD_STATUS
);
781 val
= val
| (sec_num
<< shift_param
);
782 iwl_write_direct32(trans
, FH_UCODE_LOAD_STATUS
, val
);
783 sec_num
= (sec_num
<< 1) | 0x1;
786 *first_ucode_section
= last_read_idx
;
789 iwl_write_direct32(trans
, FH_UCODE_LOAD_STATUS
, 0xFFFF);
791 iwl_write_direct32(trans
, FH_UCODE_LOAD_STATUS
, 0xFFFFFFFF);
796 static int iwl_pcie_load_cpu_sections(struct iwl_trans
*trans
,
797 const struct fw_img
*image
,
799 int *first_ucode_section
)
803 u32 last_read_idx
= 0;
807 *first_ucode_section
= 0;
810 (*first_ucode_section
)++;
813 for (i
= *first_ucode_section
; i
< IWL_UCODE_SECTION_MAX
; i
++) {
816 if (!image
->sec
[i
].data
||
817 image
->sec
[i
].offset
== CPU1_CPU2_SEPARATOR_SECTION
) {
819 "Break since Data not valid or Empty section, sec = %d\n",
824 ret
= iwl_pcie_load_section(trans
, i
, &image
->sec
[i
]);
829 if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_8000
)
830 iwl_set_bits_prph(trans
,
831 CSR_UCODE_LOAD_STATUS_ADDR
,
832 (LMPM_CPU_UCODE_LOADING_COMPLETED
|
833 LMPM_CPU_HDRS_LOADING_COMPLETED
|
834 LMPM_CPU_UCODE_LOADING_STARTED
) <<
837 *first_ucode_section
= last_read_idx
;
842 static void iwl_pcie_apply_destination(struct iwl_trans
*trans
)
844 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
845 const struct iwl_fw_dbg_dest_tlv
*dest
= trans
->dbg_dest_tlv
;
850 "DBG DEST version is %d - expect issues\n",
853 IWL_INFO(trans
, "Applying debug destination %s\n",
854 get_fw_dbg_mode_string(dest
->monitor_mode
));
856 if (dest
->monitor_mode
== EXTERNAL_MODE
)
857 iwl_pcie_alloc_fw_monitor(trans
, dest
->size_power
);
859 IWL_WARN(trans
, "PCI should have external buffer debug\n");
861 for (i
= 0; i
< trans
->dbg_dest_reg_num
; i
++) {
862 u32 addr
= le32_to_cpu(dest
->reg_ops
[i
].addr
);
863 u32 val
= le32_to_cpu(dest
->reg_ops
[i
].val
);
865 switch (dest
->reg_ops
[i
].op
) {
867 iwl_write32(trans
, addr
, val
);
870 iwl_set_bit(trans
, addr
, BIT(val
));
873 iwl_clear_bit(trans
, addr
, BIT(val
));
876 iwl_write_prph(trans
, addr
, val
);
879 iwl_set_bits_prph(trans
, addr
, BIT(val
));
882 iwl_clear_bits_prph(trans
, addr
, BIT(val
));
885 IWL_ERR(trans
, "FW debug - unknown OP %d\n",
886 dest
->reg_ops
[i
].op
);
891 if (dest
->monitor_mode
== EXTERNAL_MODE
&& trans_pcie
->fw_mon_size
) {
892 iwl_write_prph(trans
, le32_to_cpu(dest
->base_reg
),
893 trans_pcie
->fw_mon_phys
>> dest
->base_shift
);
894 iwl_write_prph(trans
, le32_to_cpu(dest
->end_reg
),
895 (trans_pcie
->fw_mon_phys
+
896 trans_pcie
->fw_mon_size
) >> dest
->end_shift
);
900 static int iwl_pcie_load_given_ucode(struct iwl_trans
*trans
,
901 const struct fw_img
*image
)
903 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
905 int first_ucode_section
;
907 IWL_DEBUG_FW(trans
, "working with %s CPU\n",
908 image
->is_dual_cpus
? "Dual" : "Single");
910 /* load to FW the binary non secured sections of CPU1 */
911 ret
= iwl_pcie_load_cpu_sections(trans
, image
, 1, &first_ucode_section
);
915 if (image
->is_dual_cpus
) {
916 /* set CPU2 header address */
917 iwl_write_prph(trans
,
918 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR
,
919 LMPM_SECURE_CPU2_HDR_MEM_SPACE
);
921 /* load to FW the binary sections of CPU2 */
922 ret
= iwl_pcie_load_cpu_sections(trans
, image
, 2,
923 &first_ucode_section
);
928 /* supported for 7000 only for the moment */
929 if (iwlwifi_mod_params
.fw_monitor
&&
930 trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_7000
) {
931 iwl_pcie_alloc_fw_monitor(trans
, 0);
933 if (trans_pcie
->fw_mon_size
) {
934 iwl_write_prph(trans
, MON_BUFF_BASE_ADDR
,
935 trans_pcie
->fw_mon_phys
>> 4);
936 iwl_write_prph(trans
, MON_BUFF_END_ADDR
,
937 (trans_pcie
->fw_mon_phys
+
938 trans_pcie
->fw_mon_size
) >> 4);
940 } else if (trans
->dbg_dest_tlv
) {
941 iwl_pcie_apply_destination(trans
);
944 /* release CPU reset */
945 iwl_write32(trans
, CSR_RESET
, 0);
950 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans
*trans
,
951 const struct fw_img
*image
)
954 int first_ucode_section
;
956 IWL_DEBUG_FW(trans
, "working with %s CPU\n",
957 image
->is_dual_cpus
? "Dual" : "Single");
959 if (trans
->dbg_dest_tlv
)
960 iwl_pcie_apply_destination(trans
);
962 /* TODO: remove in the next Si step */
963 ret
= iwl_pcie_rsa_race_bug_wa(trans
);
967 /* configure the ucode to be ready to get the secured image */
968 /* release CPU reset */
969 iwl_write_prph(trans
, RELEASE_CPU_RESET
, RELEASE_CPU_RESET_BIT
);
971 /* load to FW the binary Secured sections of CPU1 */
972 ret
= iwl_pcie_load_cpu_sections_8000(trans
, image
, 1,
973 &first_ucode_section
);
977 /* load to FW the binary sections of CPU2 */
978 return iwl_pcie_load_cpu_sections_8000(trans
, image
, 2,
979 &first_ucode_section
);
982 static int iwl_trans_pcie_start_fw(struct iwl_trans
*trans
,
983 const struct fw_img
*fw
, bool run_in_rfkill
)
988 /* This may fail if AMT took ownership of the device */
989 if (iwl_pcie_prepare_card_hw(trans
)) {
990 IWL_WARN(trans
, "Exit HW not ready\n");
994 iwl_enable_rfkill_int(trans
);
996 /* If platform's RF_KILL switch is NOT set to KILL */
997 hw_rfkill
= iwl_is_rfkill_set(trans
);
999 set_bit(STATUS_RFKILL
, &trans
->status
);
1001 clear_bit(STATUS_RFKILL
, &trans
->status
);
1002 iwl_trans_pcie_rf_kill(trans
, hw_rfkill
);
1003 if (hw_rfkill
&& !run_in_rfkill
)
1006 iwl_write32(trans
, CSR_INT
, 0xFFFFFFFF);
1008 ret
= iwl_pcie_nic_init(trans
);
1010 IWL_ERR(trans
, "Unable to init nic\n");
1014 /* make sure rfkill handshake bits are cleared */
1015 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
1016 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
,
1017 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED
);
1019 /* clear (again), then enable host interrupts */
1020 iwl_write32(trans
, CSR_INT
, 0xFFFFFFFF);
1021 iwl_enable_interrupts(trans
);
1023 /* really make sure rfkill handshake bits are cleared */
1024 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
1025 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
1027 /* Load the given image to the HW */
1028 if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_8000
)
1029 return iwl_pcie_load_given_ucode_8000(trans
, fw
);
1031 return iwl_pcie_load_given_ucode(trans
, fw
);
1034 static void iwl_trans_pcie_fw_alive(struct iwl_trans
*trans
, u32 scd_addr
)
1036 iwl_pcie_reset_ict(trans
);
1037 iwl_pcie_tx_start(trans
, scd_addr
);
1040 static void iwl_trans_pcie_stop_device(struct iwl_trans
*trans
, bool low_power
)
1042 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1043 bool hw_rfkill
, was_hw_rfkill
;
1045 was_hw_rfkill
= iwl_is_rfkill_set(trans
);
1047 /* tell the device to stop sending interrupts */
1048 spin_lock(&trans_pcie
->irq_lock
);
1049 iwl_disable_interrupts(trans
);
1050 spin_unlock(&trans_pcie
->irq_lock
);
1052 /* device going down, Stop using ICT table */
1053 iwl_pcie_disable_ict(trans
);
1056 * If a HW restart happens during firmware loading,
1057 * then the firmware loading might call this function
1058 * and later it might be called again due to the
1059 * restart. So don't process again if the device is
1062 if (test_and_clear_bit(STATUS_DEVICE_ENABLED
, &trans
->status
)) {
1063 IWL_DEBUG_INFO(trans
, "DEVICE_ENABLED bit was set and is now cleared\n");
1064 iwl_pcie_tx_stop(trans
);
1065 iwl_pcie_rx_stop(trans
);
1067 /* Power-down device's busmaster DMA clocks */
1068 if (!trans
->cfg
->apmg_not_supported
) {
1069 iwl_write_prph(trans
, APMG_CLK_DIS_REG
,
1070 APMG_CLK_VAL_DMA_CLK_RQT
);
1075 /* Make sure (redundant) we've released our request to stay awake */
1076 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
1077 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1079 /* Stop the device, and put it in low power state */
1080 iwl_pcie_apm_stop(trans
, false);
1082 /* stop and reset the on-board processor */
1083 iwl_write32(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
1087 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1088 * This is a bug in certain verions of the hardware.
1089 * Certain devices also keep sending HW RF kill interrupt all
1090 * the time, unless the interrupt is ACKed even if the interrupt
1091 * should be masked. Re-ACK all the interrupts here.
1093 spin_lock(&trans_pcie
->irq_lock
);
1094 iwl_disable_interrupts(trans
);
1095 spin_unlock(&trans_pcie
->irq_lock
);
1098 /* clear all status bits */
1099 clear_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
);
1100 clear_bit(STATUS_INT_ENABLED
, &trans
->status
);
1101 clear_bit(STATUS_TPOWER_PMI
, &trans
->status
);
1102 clear_bit(STATUS_RFKILL
, &trans
->status
);
1105 * Even if we stop the HW, we still want the RF kill
1108 iwl_enable_rfkill_int(trans
);
1111 * Check again since the RF kill state may have changed while
1112 * all the interrupts were disabled, in this case we couldn't
1113 * receive the RF kill interrupt and update the state in the
1115 * Don't call the op_mode if the rkfill state hasn't changed.
1116 * This allows the op_mode to call stop_device from the rfkill
1117 * notification without endless recursion. Under very rare
1118 * circumstances, we might have a small recursion if the rfkill
1119 * state changed exactly now while we were called from stop_device.
1120 * This is very unlikely but can happen and is supported.
1122 hw_rfkill
= iwl_is_rfkill_set(trans
);
1124 set_bit(STATUS_RFKILL
, &trans
->status
);
1126 clear_bit(STATUS_RFKILL
, &trans
->status
);
1127 if (hw_rfkill
!= was_hw_rfkill
)
1128 iwl_trans_pcie_rf_kill(trans
, hw_rfkill
);
1130 /* re-take ownership to prevent other users from stealing the deivce */
1131 iwl_pcie_prepare_card_hw(trans
);
1134 void iwl_trans_pcie_rf_kill(struct iwl_trans
*trans
, bool state
)
1136 if (iwl_op_mode_hw_rf_kill(trans
->op_mode
, state
))
1137 iwl_trans_pcie_stop_device(trans
, true);
1140 static void iwl_trans_pcie_d3_suspend(struct iwl_trans
*trans
, bool test
)
1142 iwl_disable_interrupts(trans
);
1145 * in testing mode, the host stays awake and the
1146 * hardware won't be reset (not even partially)
1151 iwl_pcie_disable_ict(trans
);
1153 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
1154 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1155 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
1156 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
1159 * reset TX queues -- some of their registers reset during S3
1160 * so if we don't reset everything here the D3 image would try
1161 * to execute some invalid memory upon resume
1163 iwl_trans_pcie_tx_reset(trans
);
1165 iwl_pcie_set_pwr(trans
, true);
1168 static int iwl_trans_pcie_d3_resume(struct iwl_trans
*trans
,
1169 enum iwl_d3_status
*status
,
1176 iwl_enable_interrupts(trans
);
1177 *status
= IWL_D3_STATUS_ALIVE
;
1182 * Also enables interrupts - none will happen as the device doesn't
1183 * know we're waking it up, only when the opmode actually tells it
1186 iwl_pcie_reset_ict(trans
);
1188 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1189 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
1191 if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_8000
)
1194 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
1195 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
1196 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
1199 IWL_ERR(trans
, "Failed to resume the device (mac ready)\n");
1203 iwl_pcie_set_pwr(trans
, false);
1205 iwl_trans_pcie_tx_reset(trans
);
1207 ret
= iwl_pcie_rx_init(trans
);
1209 IWL_ERR(trans
, "Failed to resume the device (RX reset)\n");
1213 val
= iwl_read32(trans
, CSR_RESET
);
1214 if (val
& CSR_RESET_REG_FLAG_NEVO_RESET
)
1215 *status
= IWL_D3_STATUS_RESET
;
1217 *status
= IWL_D3_STATUS_ALIVE
;
1222 static int iwl_trans_pcie_start_hw(struct iwl_trans
*trans
, bool low_power
)
1227 err
= iwl_pcie_prepare_card_hw(trans
);
1229 IWL_ERR(trans
, "Error while preparing HW: %d\n", err
);
1233 /* Reset the entire device */
1234 iwl_write32(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
1236 usleep_range(10, 15);
1238 iwl_pcie_apm_init(trans
);
1240 /* From now on, the op_mode will be kept updated about RF kill state */
1241 iwl_enable_rfkill_int(trans
);
1243 hw_rfkill
= iwl_is_rfkill_set(trans
);
1245 set_bit(STATUS_RFKILL
, &trans
->status
);
1247 clear_bit(STATUS_RFKILL
, &trans
->status
);
1248 iwl_trans_pcie_rf_kill(trans
, hw_rfkill
);
1253 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans
*trans
)
1255 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1257 /* disable interrupts - don't enable HW RF kill interrupt */
1258 spin_lock(&trans_pcie
->irq_lock
);
1259 iwl_disable_interrupts(trans
);
1260 spin_unlock(&trans_pcie
->irq_lock
);
1262 iwl_pcie_apm_stop(trans
, true);
1264 spin_lock(&trans_pcie
->irq_lock
);
1265 iwl_disable_interrupts(trans
);
1266 spin_unlock(&trans_pcie
->irq_lock
);
1268 iwl_pcie_disable_ict(trans
);
1271 static void iwl_trans_pcie_write8(struct iwl_trans
*trans
, u32 ofs
, u8 val
)
1273 writeb(val
, IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1276 static void iwl_trans_pcie_write32(struct iwl_trans
*trans
, u32 ofs
, u32 val
)
1278 writel(val
, IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1281 static u32
iwl_trans_pcie_read32(struct iwl_trans
*trans
, u32 ofs
)
1283 return readl(IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1286 static u32
iwl_trans_pcie_read_prph(struct iwl_trans
*trans
, u32 reg
)
1288 iwl_trans_pcie_write32(trans
, HBUS_TARG_PRPH_RADDR
,
1289 ((reg
& 0x000FFFFF) | (3 << 24)));
1290 return iwl_trans_pcie_read32(trans
, HBUS_TARG_PRPH_RDAT
);
1293 static void iwl_trans_pcie_write_prph(struct iwl_trans
*trans
, u32 addr
,
1296 iwl_trans_pcie_write32(trans
, HBUS_TARG_PRPH_WADDR
,
1297 ((addr
& 0x000FFFFF) | (3 << 24)));
1298 iwl_trans_pcie_write32(trans
, HBUS_TARG_PRPH_WDAT
, val
);
1301 static int iwl_pcie_dummy_napi_poll(struct napi_struct
*napi
, int budget
)
1307 static void iwl_trans_pcie_configure(struct iwl_trans
*trans
,
1308 const struct iwl_trans_config
*trans_cfg
)
1310 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1312 trans_pcie
->cmd_queue
= trans_cfg
->cmd_queue
;
1313 trans_pcie
->cmd_fifo
= trans_cfg
->cmd_fifo
;
1314 trans_pcie
->cmd_q_wdg_timeout
= trans_cfg
->cmd_q_wdg_timeout
;
1315 if (WARN_ON(trans_cfg
->n_no_reclaim_cmds
> MAX_NO_RECLAIM_CMDS
))
1316 trans_pcie
->n_no_reclaim_cmds
= 0;
1318 trans_pcie
->n_no_reclaim_cmds
= trans_cfg
->n_no_reclaim_cmds
;
1319 if (trans_pcie
->n_no_reclaim_cmds
)
1320 memcpy(trans_pcie
->no_reclaim_cmds
, trans_cfg
->no_reclaim_cmds
,
1321 trans_pcie
->n_no_reclaim_cmds
* sizeof(u8
));
1323 trans_pcie
->rx_buf_size_8k
= trans_cfg
->rx_buf_size_8k
;
1324 if (trans_pcie
->rx_buf_size_8k
)
1325 trans_pcie
->rx_page_order
= get_order(8 * 1024);
1327 trans_pcie
->rx_page_order
= get_order(4 * 1024);
1329 trans_pcie
->command_names
= trans_cfg
->command_names
;
1330 trans_pcie
->bc_table_dword
= trans_cfg
->bc_table_dword
;
1331 trans_pcie
->scd_set_active
= trans_cfg
->scd_set_active
;
1333 /* init ref_count to 1 (should be cleared when ucode is loaded) */
1334 trans_pcie
->ref_count
= 1;
1336 /* Initialize NAPI here - it should be before registering to mac80211
1337 * in the opmode but after the HW struct is allocated.
1338 * As this function may be called again in some corner cases don't
1339 * do anything if NAPI was already initialized.
1341 if (!trans_pcie
->napi
.poll
&& trans
->op_mode
->ops
->napi_add
) {
1342 init_dummy_netdev(&trans_pcie
->napi_dev
);
1343 iwl_op_mode_napi_add(trans
->op_mode
, &trans_pcie
->napi
,
1344 &trans_pcie
->napi_dev
,
1345 iwl_pcie_dummy_napi_poll
, 64);
1349 void iwl_trans_pcie_free(struct iwl_trans
*trans
)
1351 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1353 synchronize_irq(trans_pcie
->pci_dev
->irq
);
1355 iwl_pcie_tx_free(trans
);
1356 iwl_pcie_rx_free(trans
);
1358 free_irq(trans_pcie
->pci_dev
->irq
, trans
);
1359 iwl_pcie_free_ict(trans
);
1361 pci_disable_msi(trans_pcie
->pci_dev
);
1362 iounmap(trans_pcie
->hw_base
);
1363 pci_release_regions(trans_pcie
->pci_dev
);
1364 pci_disable_device(trans_pcie
->pci_dev
);
1366 if (trans_pcie
->napi
.poll
)
1367 netif_napi_del(&trans_pcie
->napi
);
1369 iwl_pcie_free_fw_monitor(trans
);
1371 iwl_trans_free(trans
);
1374 static void iwl_trans_pcie_set_pmi(struct iwl_trans
*trans
, bool state
)
1377 set_bit(STATUS_TPOWER_PMI
, &trans
->status
);
1379 clear_bit(STATUS_TPOWER_PMI
, &trans
->status
);
1382 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans
*trans
, bool silent
,
1383 unsigned long *flags
)
1386 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1388 spin_lock_irqsave(&trans_pcie
->reg_lock
, *flags
);
1390 if (trans_pcie
->cmd_hold_nic_awake
)
1393 /* this bit wakes up the NIC */
1394 __iwl_trans_pcie_set_bit(trans
, CSR_GP_CNTRL
,
1395 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1396 if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_8000
)
1400 * These bits say the device is running, and should keep running for
1401 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1402 * but they do not indicate that embedded SRAM is restored yet;
1403 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1404 * to/from host DRAM when sleeping/waking for power-saving.
1405 * Each direction takes approximately 1/4 millisecond; with this
1406 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1407 * series of register accesses are expected (e.g. reading Event Log),
1408 * to keep device from sleeping.
1410 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1411 * SRAM is okay/restored. We don't check that here because this call
1412 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1413 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1415 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1416 * and do not save/restore SRAM when power cycling.
1418 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
1419 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN
,
1420 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
|
1421 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP
), 15000);
1422 if (unlikely(ret
< 0)) {
1423 iwl_write32(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_FORCE_NMI
);
1425 u32 val
= iwl_read32(trans
, CSR_GP_CNTRL
);
1427 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1429 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, *flags
);
1436 * Fool sparse by faking we release the lock - sparse will
1437 * track nic_access anyway.
1439 __release(&trans_pcie
->reg_lock
);
1443 static void iwl_trans_pcie_release_nic_access(struct iwl_trans
*trans
,
1444 unsigned long *flags
)
1446 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1448 lockdep_assert_held(&trans_pcie
->reg_lock
);
1451 * Fool sparse by faking we acquiring the lock - sparse will
1452 * track nic_access anyway.
1454 __acquire(&trans_pcie
->reg_lock
);
1456 if (trans_pcie
->cmd_hold_nic_awake
)
1459 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
1460 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1462 * Above we read the CSR_GP_CNTRL register, which will flush
1463 * any previous writes, but we need the write that clears the
1464 * MAC_ACCESS_REQ bit to be performed before any other writes
1465 * scheduled on different CPUs (after we drop reg_lock).
1469 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, *flags
);
1472 static int iwl_trans_pcie_read_mem(struct iwl_trans
*trans
, u32 addr
,
1473 void *buf
, int dwords
)
1475 unsigned long flags
;
1479 if (iwl_trans_grab_nic_access(trans
, false, &flags
)) {
1480 iwl_write32(trans
, HBUS_TARG_MEM_RADDR
, addr
);
1481 for (offs
= 0; offs
< dwords
; offs
++)
1482 vals
[offs
] = iwl_read32(trans
, HBUS_TARG_MEM_RDAT
);
1483 iwl_trans_release_nic_access(trans
, &flags
);
1490 static int iwl_trans_pcie_write_mem(struct iwl_trans
*trans
, u32 addr
,
1491 const void *buf
, int dwords
)
1493 unsigned long flags
;
1495 const u32
*vals
= buf
;
1497 if (iwl_trans_grab_nic_access(trans
, false, &flags
)) {
1498 iwl_write32(trans
, HBUS_TARG_MEM_WADDR
, addr
);
1499 for (offs
= 0; offs
< dwords
; offs
++)
1500 iwl_write32(trans
, HBUS_TARG_MEM_WDAT
,
1501 vals
? vals
[offs
] : 0);
1502 iwl_trans_release_nic_access(trans
, &flags
);
1509 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans
*trans
,
1513 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1516 for_each_set_bit(queue
, &txqs
, BITS_PER_LONG
) {
1517 struct iwl_txq
*txq
= &trans_pcie
->txq
[queue
];
1520 spin_lock_bh(&txq
->lock
);
1524 if (txq
->frozen
== freeze
)
1527 IWL_DEBUG_TX_QUEUES(trans
, "%s TXQ %d\n",
1528 freeze
? "Freezing" : "Waking", queue
);
1530 txq
->frozen
= freeze
;
1532 if (txq
->q
.read_ptr
== txq
->q
.write_ptr
)
1536 if (unlikely(time_after(now
,
1537 txq
->stuck_timer
.expires
))) {
1539 * The timer should have fired, maybe it is
1540 * spinning right now on the lock.
1544 /* remember how long until the timer fires */
1545 txq
->frozen_expiry_remainder
=
1546 txq
->stuck_timer
.expires
- now
;
1547 del_timer(&txq
->stuck_timer
);
1552 * Wake a non-empty queue -> arm timer with the
1553 * remainder before it froze
1555 mod_timer(&txq
->stuck_timer
,
1556 now
+ txq
->frozen_expiry_remainder
);
1559 spin_unlock_bh(&txq
->lock
);
1563 #define IWL_FLUSH_WAIT_MS 2000
1565 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans
*trans
, u32 txq_bm
)
1567 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1568 struct iwl_txq
*txq
;
1569 struct iwl_queue
*q
;
1571 unsigned long now
= jiffies
;
1576 /* waiting for all the tx frames complete might take a while */
1577 for (cnt
= 0; cnt
< trans
->cfg
->base_params
->num_of_queues
; cnt
++) {
1580 if (cnt
== trans_pcie
->cmd_queue
)
1582 if (!test_bit(cnt
, trans_pcie
->queue_used
))
1584 if (!(BIT(cnt
) & txq_bm
))
1587 IWL_DEBUG_TX_QUEUES(trans
, "Emptying queue %d...\n", cnt
);
1588 txq
= &trans_pcie
->txq
[cnt
];
1590 wr_ptr
= ACCESS_ONCE(q
->write_ptr
);
1592 while (q
->read_ptr
!= ACCESS_ONCE(q
->write_ptr
) &&
1593 !time_after(jiffies
,
1594 now
+ msecs_to_jiffies(IWL_FLUSH_WAIT_MS
))) {
1595 u8 write_ptr
= ACCESS_ONCE(q
->write_ptr
);
1597 if (WARN_ONCE(wr_ptr
!= write_ptr
,
1598 "WR pointer moved while flushing %d -> %d\n",
1604 if (q
->read_ptr
!= q
->write_ptr
) {
1606 "fail to flush all tx fifo queues Q %d\n", cnt
);
1610 IWL_DEBUG_TX_QUEUES(trans
, "Queue %d is now empty.\n", cnt
);
1616 IWL_ERR(trans
, "Current SW read_ptr %d write_ptr %d\n",
1617 txq
->q
.read_ptr
, txq
->q
.write_ptr
);
1619 scd_sram_addr
= trans_pcie
->scd_base_addr
+
1620 SCD_TX_STTS_QUEUE_OFFSET(txq
->q
.id
);
1621 iwl_trans_read_mem_bytes(trans
, scd_sram_addr
, buf
, sizeof(buf
));
1623 iwl_print_hex_error(trans
, buf
, sizeof(buf
));
1625 for (cnt
= 0; cnt
< FH_TCSR_CHNL_NUM
; cnt
++)
1626 IWL_ERR(trans
, "FH TRBs(%d) = 0x%08x\n", cnt
,
1627 iwl_read_direct32(trans
, FH_TX_TRB_REG(cnt
)));
1629 for (cnt
= 0; cnt
< trans
->cfg
->base_params
->num_of_queues
; cnt
++) {
1630 u32 status
= iwl_read_prph(trans
, SCD_QUEUE_STATUS_BITS(cnt
));
1631 u8 fifo
= (status
>> SCD_QUEUE_STTS_REG_POS_TXF
) & 0x7;
1632 bool active
= !!(status
& BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE
));
1634 iwl_trans_read_mem32(trans
, trans_pcie
->scd_base_addr
+
1635 SCD_TRANS_TBL_OFFSET_QUEUE(cnt
));
1638 tbl_dw
= (tbl_dw
& 0xFFFF0000) >> 16;
1640 tbl_dw
= tbl_dw
& 0x0000FFFF;
1643 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1644 cnt
, active
? "" : "in", fifo
, tbl_dw
,
1645 iwl_read_prph(trans
, SCD_QUEUE_RDPTR(cnt
)) &
1646 (TFD_QUEUE_SIZE_MAX
- 1),
1647 iwl_read_prph(trans
, SCD_QUEUE_WRPTR(cnt
)));
1653 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans
*trans
, u32 reg
,
1654 u32 mask
, u32 value
)
1656 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1657 unsigned long flags
;
1659 spin_lock_irqsave(&trans_pcie
->reg_lock
, flags
);
1660 __iwl_trans_pcie_set_bits_mask(trans
, reg
, mask
, value
);
1661 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, flags
);
1664 void iwl_trans_pcie_ref(struct iwl_trans
*trans
)
1666 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1667 unsigned long flags
;
1669 if (iwlwifi_mod_params
.d0i3_disable
)
1672 spin_lock_irqsave(&trans_pcie
->ref_lock
, flags
);
1673 IWL_DEBUG_RPM(trans
, "ref_counter: %d\n", trans_pcie
->ref_count
);
1674 trans_pcie
->ref_count
++;
1675 spin_unlock_irqrestore(&trans_pcie
->ref_lock
, flags
);
1678 void iwl_trans_pcie_unref(struct iwl_trans
*trans
)
1680 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1681 unsigned long flags
;
1683 if (iwlwifi_mod_params
.d0i3_disable
)
1686 spin_lock_irqsave(&trans_pcie
->ref_lock
, flags
);
1687 IWL_DEBUG_RPM(trans
, "ref_counter: %d\n", trans_pcie
->ref_count
);
1688 if (WARN_ON_ONCE(trans_pcie
->ref_count
== 0)) {
1689 spin_unlock_irqrestore(&trans_pcie
->ref_lock
, flags
);
1692 trans_pcie
->ref_count
--;
1693 spin_unlock_irqrestore(&trans_pcie
->ref_lock
, flags
);
1696 static const char *get_csr_string(int cmd
)
1698 #define IWL_CMD(x) case x: return #x
1700 IWL_CMD(CSR_HW_IF_CONFIG_REG
);
1701 IWL_CMD(CSR_INT_COALESCING
);
1703 IWL_CMD(CSR_INT_MASK
);
1704 IWL_CMD(CSR_FH_INT_STATUS
);
1705 IWL_CMD(CSR_GPIO_IN
);
1707 IWL_CMD(CSR_GP_CNTRL
);
1708 IWL_CMD(CSR_HW_REV
);
1709 IWL_CMD(CSR_EEPROM_REG
);
1710 IWL_CMD(CSR_EEPROM_GP
);
1711 IWL_CMD(CSR_OTP_GP_REG
);
1712 IWL_CMD(CSR_GIO_REG
);
1713 IWL_CMD(CSR_GP_UCODE_REG
);
1714 IWL_CMD(CSR_GP_DRIVER_REG
);
1715 IWL_CMD(CSR_UCODE_DRV_GP1
);
1716 IWL_CMD(CSR_UCODE_DRV_GP2
);
1717 IWL_CMD(CSR_LED_REG
);
1718 IWL_CMD(CSR_DRAM_INT_TBL_REG
);
1719 IWL_CMD(CSR_GIO_CHICKEN_BITS
);
1720 IWL_CMD(CSR_ANA_PLL_CFG
);
1721 IWL_CMD(CSR_HW_REV_WA_REG
);
1722 IWL_CMD(CSR_MONITOR_STATUS_REG
);
1723 IWL_CMD(CSR_DBG_HPET_MEM_REG
);
1730 void iwl_pcie_dump_csr(struct iwl_trans
*trans
)
1733 static const u32 csr_tbl
[] = {
1734 CSR_HW_IF_CONFIG_REG
,
1752 CSR_DRAM_INT_TBL_REG
,
1753 CSR_GIO_CHICKEN_BITS
,
1755 CSR_MONITOR_STATUS_REG
,
1757 CSR_DBG_HPET_MEM_REG
1759 IWL_ERR(trans
, "CSR values:\n");
1760 IWL_ERR(trans
, "(2nd byte of CSR_INT_COALESCING is "
1761 "CSR_INT_PERIODIC_REG)\n");
1762 for (i
= 0; i
< ARRAY_SIZE(csr_tbl
); i
++) {
1763 IWL_ERR(trans
, " %25s: 0X%08x\n",
1764 get_csr_string(csr_tbl
[i
]),
1765 iwl_read32(trans
, csr_tbl
[i
]));
1769 #ifdef CONFIG_IWLWIFI_DEBUGFS
1770 /* create and remove of files */
1771 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1772 if (!debugfs_create_file(#name, mode, parent, trans, \
1773 &iwl_dbgfs_##name##_ops)) \
1777 /* file operation */
1778 #define DEBUGFS_READ_FILE_OPS(name) \
1779 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1780 .read = iwl_dbgfs_##name##_read, \
1781 .open = simple_open, \
1782 .llseek = generic_file_llseek, \
1785 #define DEBUGFS_WRITE_FILE_OPS(name) \
1786 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1787 .write = iwl_dbgfs_##name##_write, \
1788 .open = simple_open, \
1789 .llseek = generic_file_llseek, \
1792 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1793 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1794 .write = iwl_dbgfs_##name##_write, \
1795 .read = iwl_dbgfs_##name##_read, \
1796 .open = simple_open, \
1797 .llseek = generic_file_llseek, \
1800 static ssize_t
iwl_dbgfs_tx_queue_read(struct file
*file
,
1801 char __user
*user_buf
,
1802 size_t count
, loff_t
*ppos
)
1804 struct iwl_trans
*trans
= file
->private_data
;
1805 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1806 struct iwl_txq
*txq
;
1807 struct iwl_queue
*q
;
1814 bufsz
= sizeof(char) * 75 * trans
->cfg
->base_params
->num_of_queues
;
1816 if (!trans_pcie
->txq
)
1819 buf
= kzalloc(bufsz
, GFP_KERNEL
);
1823 for (cnt
= 0; cnt
< trans
->cfg
->base_params
->num_of_queues
; cnt
++) {
1824 txq
= &trans_pcie
->txq
[cnt
];
1826 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1827 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
1828 cnt
, q
->read_ptr
, q
->write_ptr
,
1829 !!test_bit(cnt
, trans_pcie
->queue_used
),
1830 !!test_bit(cnt
, trans_pcie
->queue_stopped
),
1831 txq
->need_update
, txq
->frozen
,
1832 (cnt
== trans_pcie
->cmd_queue
? " HCMD" : ""));
1834 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1839 static ssize_t
iwl_dbgfs_rx_queue_read(struct file
*file
,
1840 char __user
*user_buf
,
1841 size_t count
, loff_t
*ppos
)
1843 struct iwl_trans
*trans
= file
->private_data
;
1844 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1845 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
;
1848 const size_t bufsz
= sizeof(buf
);
1850 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "read: %u\n",
1852 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "write: %u\n",
1854 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "write_actual: %u\n",
1856 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "need_update: %d\n",
1858 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "free_count: %u\n",
1861 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "closed_rb_num: %u\n",
1862 le16_to_cpu(rxq
->rb_stts
->closed_rb_num
) & 0x0FFF);
1864 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1865 "closed_rb_num: Not Allocated\n");
1867 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1870 static ssize_t
iwl_dbgfs_interrupt_read(struct file
*file
,
1871 char __user
*user_buf
,
1872 size_t count
, loff_t
*ppos
)
1874 struct iwl_trans
*trans
= file
->private_data
;
1875 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1876 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
1880 int bufsz
= 24 * 64; /* 24 items * 64 char per item */
1883 buf
= kzalloc(bufsz
, GFP_KERNEL
);
1887 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1888 "Interrupt Statistics Report:\n");
1890 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "HW Error:\t\t\t %u\n",
1892 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "SW Error:\t\t\t %u\n",
1894 if (isr_stats
->sw
|| isr_stats
->hw
) {
1895 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1896 "\tLast Restarting Code: 0x%X\n",
1897 isr_stats
->err_code
);
1899 #ifdef CONFIG_IWLWIFI_DEBUG
1900 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Frame transmitted:\t\t %u\n",
1902 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Alive interrupt:\t\t %u\n",
1905 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1906 "HW RF KILL switch toggled:\t %u\n", isr_stats
->rfkill
);
1908 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "CT KILL:\t\t\t %u\n",
1911 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Wakeup Interrupt:\t\t %u\n",
1914 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1915 "Rx command responses:\t\t %u\n", isr_stats
->rx
);
1917 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Tx/FH interrupt:\t\t %u\n",
1920 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Unexpected INTA:\t\t %u\n",
1921 isr_stats
->unhandled
);
1923 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1928 static ssize_t
iwl_dbgfs_interrupt_write(struct file
*file
,
1929 const char __user
*user_buf
,
1930 size_t count
, loff_t
*ppos
)
1932 struct iwl_trans
*trans
= file
->private_data
;
1933 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1934 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
1940 memset(buf
, 0, sizeof(buf
));
1941 buf_size
= min(count
, sizeof(buf
) - 1);
1942 if (copy_from_user(buf
, user_buf
, buf_size
))
1944 if (sscanf(buf
, "%x", &reset_flag
) != 1)
1946 if (reset_flag
== 0)
1947 memset(isr_stats
, 0, sizeof(*isr_stats
));
1952 static ssize_t
iwl_dbgfs_csr_write(struct file
*file
,
1953 const char __user
*user_buf
,
1954 size_t count
, loff_t
*ppos
)
1956 struct iwl_trans
*trans
= file
->private_data
;
1961 memset(buf
, 0, sizeof(buf
));
1962 buf_size
= min(count
, sizeof(buf
) - 1);
1963 if (copy_from_user(buf
, user_buf
, buf_size
))
1965 if (sscanf(buf
, "%d", &csr
) != 1)
1968 iwl_pcie_dump_csr(trans
);
1973 static ssize_t
iwl_dbgfs_fh_reg_read(struct file
*file
,
1974 char __user
*user_buf
,
1975 size_t count
, loff_t
*ppos
)
1977 struct iwl_trans
*trans
= file
->private_data
;
1981 ret
= iwl_dump_fh(trans
, &buf
);
1986 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, ret
);
1991 DEBUGFS_READ_WRITE_FILE_OPS(interrupt
);
1992 DEBUGFS_READ_FILE_OPS(fh_reg
);
1993 DEBUGFS_READ_FILE_OPS(rx_queue
);
1994 DEBUGFS_READ_FILE_OPS(tx_queue
);
1995 DEBUGFS_WRITE_FILE_OPS(csr
);
1998 * Create the debugfs files and directories
2001 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans
*trans
,
2004 DEBUGFS_ADD_FILE(rx_queue
, dir
, S_IRUSR
);
2005 DEBUGFS_ADD_FILE(tx_queue
, dir
, S_IRUSR
);
2006 DEBUGFS_ADD_FILE(interrupt
, dir
, S_IWUSR
| S_IRUSR
);
2007 DEBUGFS_ADD_FILE(csr
, dir
, S_IWUSR
);
2008 DEBUGFS_ADD_FILE(fh_reg
, dir
, S_IRUSR
);
2012 IWL_ERR(trans
, "failed to create the trans debugfs entry\n");
2016 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans
*trans
,
2021 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2023 static u32
iwl_trans_pcie_get_cmdlen(struct iwl_tfd
*tfd
)
2028 for (i
= 0; i
< IWL_NUM_OF_TBS
; i
++)
2029 cmdlen
+= iwl_pcie_tfd_tb_get_len(tfd
, i
);
2034 static const struct {
2036 } iwl_prph_dump_addr
[] = {
2037 { .start
= 0x00a00000, .end
= 0x00a00000 },
2038 { .start
= 0x00a0000c, .end
= 0x00a00024 },
2039 { .start
= 0x00a0002c, .end
= 0x00a0003c },
2040 { .start
= 0x00a00410, .end
= 0x00a00418 },
2041 { .start
= 0x00a00420, .end
= 0x00a00420 },
2042 { .start
= 0x00a00428, .end
= 0x00a00428 },
2043 { .start
= 0x00a00430, .end
= 0x00a0043c },
2044 { .start
= 0x00a00444, .end
= 0x00a00444 },
2045 { .start
= 0x00a004c0, .end
= 0x00a004cc },
2046 { .start
= 0x00a004d8, .end
= 0x00a004d8 },
2047 { .start
= 0x00a004e0, .end
= 0x00a004f0 },
2048 { .start
= 0x00a00840, .end
= 0x00a00840 },
2049 { .start
= 0x00a00850, .end
= 0x00a00858 },
2050 { .start
= 0x00a01004, .end
= 0x00a01008 },
2051 { .start
= 0x00a01010, .end
= 0x00a01010 },
2052 { .start
= 0x00a01018, .end
= 0x00a01018 },
2053 { .start
= 0x00a01024, .end
= 0x00a01024 },
2054 { .start
= 0x00a0102c, .end
= 0x00a01034 },
2055 { .start
= 0x00a0103c, .end
= 0x00a01040 },
2056 { .start
= 0x00a01048, .end
= 0x00a01094 },
2057 { .start
= 0x00a01c00, .end
= 0x00a01c20 },
2058 { .start
= 0x00a01c58, .end
= 0x00a01c58 },
2059 { .start
= 0x00a01c7c, .end
= 0x00a01c7c },
2060 { .start
= 0x00a01c28, .end
= 0x00a01c54 },
2061 { .start
= 0x00a01c5c, .end
= 0x00a01c5c },
2062 { .start
= 0x00a01c60, .end
= 0x00a01cdc },
2063 { .start
= 0x00a01ce0, .end
= 0x00a01d0c },
2064 { .start
= 0x00a01d18, .end
= 0x00a01d20 },
2065 { .start
= 0x00a01d2c, .end
= 0x00a01d30 },
2066 { .start
= 0x00a01d40, .end
= 0x00a01d5c },
2067 { .start
= 0x00a01d80, .end
= 0x00a01d80 },
2068 { .start
= 0x00a01d98, .end
= 0x00a01d9c },
2069 { .start
= 0x00a01da8, .end
= 0x00a01da8 },
2070 { .start
= 0x00a01db8, .end
= 0x00a01df4 },
2071 { .start
= 0x00a01dc0, .end
= 0x00a01dfc },
2072 { .start
= 0x00a01e00, .end
= 0x00a01e2c },
2073 { .start
= 0x00a01e40, .end
= 0x00a01e60 },
2074 { .start
= 0x00a01e68, .end
= 0x00a01e6c },
2075 { .start
= 0x00a01e74, .end
= 0x00a01e74 },
2076 { .start
= 0x00a01e84, .end
= 0x00a01e90 },
2077 { .start
= 0x00a01e9c, .end
= 0x00a01ec4 },
2078 { .start
= 0x00a01ed0, .end
= 0x00a01ee0 },
2079 { .start
= 0x00a01f00, .end
= 0x00a01f1c },
2080 { .start
= 0x00a01f44, .end
= 0x00a01ffc },
2081 { .start
= 0x00a02000, .end
= 0x00a02048 },
2082 { .start
= 0x00a02068, .end
= 0x00a020f0 },
2083 { .start
= 0x00a02100, .end
= 0x00a02118 },
2084 { .start
= 0x00a02140, .end
= 0x00a0214c },
2085 { .start
= 0x00a02168, .end
= 0x00a0218c },
2086 { .start
= 0x00a021c0, .end
= 0x00a021c0 },
2087 { .start
= 0x00a02400, .end
= 0x00a02410 },
2088 { .start
= 0x00a02418, .end
= 0x00a02420 },
2089 { .start
= 0x00a02428, .end
= 0x00a0242c },
2090 { .start
= 0x00a02434, .end
= 0x00a02434 },
2091 { .start
= 0x00a02440, .end
= 0x00a02460 },
2092 { .start
= 0x00a02468, .end
= 0x00a024b0 },
2093 { .start
= 0x00a024c8, .end
= 0x00a024cc },
2094 { .start
= 0x00a02500, .end
= 0x00a02504 },
2095 { .start
= 0x00a0250c, .end
= 0x00a02510 },
2096 { .start
= 0x00a02540, .end
= 0x00a02554 },
2097 { .start
= 0x00a02580, .end
= 0x00a025f4 },
2098 { .start
= 0x00a02600, .end
= 0x00a0260c },
2099 { .start
= 0x00a02648, .end
= 0x00a02650 },
2100 { .start
= 0x00a02680, .end
= 0x00a02680 },
2101 { .start
= 0x00a026c0, .end
= 0x00a026d0 },
2102 { .start
= 0x00a02700, .end
= 0x00a0270c },
2103 { .start
= 0x00a02804, .end
= 0x00a02804 },
2104 { .start
= 0x00a02818, .end
= 0x00a0281c },
2105 { .start
= 0x00a02c00, .end
= 0x00a02db4 },
2106 { .start
= 0x00a02df4, .end
= 0x00a02fb0 },
2107 { .start
= 0x00a03000, .end
= 0x00a03014 },
2108 { .start
= 0x00a0301c, .end
= 0x00a0302c },
2109 { .start
= 0x00a03034, .end
= 0x00a03038 },
2110 { .start
= 0x00a03040, .end
= 0x00a03048 },
2111 { .start
= 0x00a03060, .end
= 0x00a03068 },
2112 { .start
= 0x00a03070, .end
= 0x00a03074 },
2113 { .start
= 0x00a0307c, .end
= 0x00a0307c },
2114 { .start
= 0x00a03080, .end
= 0x00a03084 },
2115 { .start
= 0x00a0308c, .end
= 0x00a03090 },
2116 { .start
= 0x00a03098, .end
= 0x00a03098 },
2117 { .start
= 0x00a030a0, .end
= 0x00a030a0 },
2118 { .start
= 0x00a030a8, .end
= 0x00a030b4 },
2119 { .start
= 0x00a030bc, .end
= 0x00a030bc },
2120 { .start
= 0x00a030c0, .end
= 0x00a0312c },
2121 { .start
= 0x00a03c00, .end
= 0x00a03c5c },
2122 { .start
= 0x00a04400, .end
= 0x00a04454 },
2123 { .start
= 0x00a04460, .end
= 0x00a04474 },
2124 { .start
= 0x00a044c0, .end
= 0x00a044ec },
2125 { .start
= 0x00a04500, .end
= 0x00a04504 },
2126 { .start
= 0x00a04510, .end
= 0x00a04538 },
2127 { .start
= 0x00a04540, .end
= 0x00a04548 },
2128 { .start
= 0x00a04560, .end
= 0x00a0457c },
2129 { .start
= 0x00a04590, .end
= 0x00a04598 },
2130 { .start
= 0x00a045c0, .end
= 0x00a045f4 },
2133 static u32
iwl_trans_pcie_dump_prph(struct iwl_trans
*trans
,
2134 struct iwl_fw_error_dump_data
**data
)
2136 struct iwl_fw_error_dump_prph
*prph
;
2137 unsigned long flags
;
2138 u32 prph_len
= 0, i
;
2140 if (!iwl_trans_grab_nic_access(trans
, false, &flags
))
2143 for (i
= 0; i
< ARRAY_SIZE(iwl_prph_dump_addr
); i
++) {
2144 /* The range includes both boundaries */
2145 int num_bytes_in_chunk
= iwl_prph_dump_addr
[i
].end
-
2146 iwl_prph_dump_addr
[i
].start
+ 4;
2150 prph_len
+= sizeof(**data
) + sizeof(*prph
) + num_bytes_in_chunk
;
2152 (*data
)->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH
);
2153 (*data
)->len
= cpu_to_le32(sizeof(*prph
) +
2154 num_bytes_in_chunk
);
2155 prph
= (void *)(*data
)->data
;
2156 prph
->prph_start
= cpu_to_le32(iwl_prph_dump_addr
[i
].start
);
2157 val
= (void *)prph
->data
;
2159 for (reg
= iwl_prph_dump_addr
[i
].start
;
2160 reg
<= iwl_prph_dump_addr
[i
].end
;
2162 *val
++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans
,
2164 *data
= iwl_fw_error_next_data(*data
);
2167 iwl_trans_release_nic_access(trans
, &flags
);
2172 #define IWL_CSR_TO_DUMP (0x250)
2174 static u32
iwl_trans_pcie_dump_csr(struct iwl_trans
*trans
,
2175 struct iwl_fw_error_dump_data
**data
)
2177 u32 csr_len
= sizeof(**data
) + IWL_CSR_TO_DUMP
;
2181 (*data
)->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_CSR
);
2182 (*data
)->len
= cpu_to_le32(IWL_CSR_TO_DUMP
);
2183 val
= (void *)(*data
)->data
;
2185 for (i
= 0; i
< IWL_CSR_TO_DUMP
; i
+= 4)
2186 *val
++ = cpu_to_le32(iwl_trans_pcie_read32(trans
, i
));
2188 *data
= iwl_fw_error_next_data(*data
);
2193 static u32
iwl_trans_pcie_fh_regs_dump(struct iwl_trans
*trans
,
2194 struct iwl_fw_error_dump_data
**data
)
2196 u32 fh_regs_len
= FH_MEM_UPPER_BOUND
- FH_MEM_LOWER_BOUND
;
2197 unsigned long flags
;
2201 if (!iwl_trans_grab_nic_access(trans
, false, &flags
))
2204 (*data
)->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS
);
2205 (*data
)->len
= cpu_to_le32(fh_regs_len
);
2206 val
= (void *)(*data
)->data
;
2208 for (i
= FH_MEM_LOWER_BOUND
; i
< FH_MEM_UPPER_BOUND
; i
+= sizeof(u32
))
2209 *val
++ = cpu_to_le32(iwl_trans_pcie_read32(trans
, i
));
2211 iwl_trans_release_nic_access(trans
, &flags
);
2213 *data
= iwl_fw_error_next_data(*data
);
2215 return sizeof(**data
) + fh_regs_len
;
2219 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans
*trans
,
2220 struct iwl_fw_error_dump_fw_mon
*fw_mon_data
,
2223 u32 buf_size_in_dwords
= (monitor_len
>> 2);
2224 u32
*buffer
= (u32
*)fw_mon_data
->data
;
2225 unsigned long flags
;
2228 if (!iwl_trans_grab_nic_access(trans
, false, &flags
))
2231 __iwl_write_prph(trans
, MON_DMARB_RD_CTL_ADDR
, 0x1);
2232 for (i
= 0; i
< buf_size_in_dwords
; i
++)
2233 buffer
[i
] = __iwl_read_prph(trans
, MON_DMARB_RD_DATA_ADDR
);
2234 __iwl_write_prph(trans
, MON_DMARB_RD_CTL_ADDR
, 0x0);
2236 iwl_trans_release_nic_access(trans
, &flags
);
2242 struct iwl_trans_dump_data
*iwl_trans_pcie_dump_data(struct iwl_trans
*trans
)
2244 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2245 struct iwl_fw_error_dump_data
*data
;
2246 struct iwl_txq
*cmdq
= &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
2247 struct iwl_fw_error_dump_txcmd
*txcmd
;
2248 struct iwl_trans_dump_data
*dump_data
;
2253 /* transport dump header */
2254 len
= sizeof(*dump_data
);
2257 len
+= sizeof(*data
) +
2258 cmdq
->q
.n_window
* (sizeof(*txcmd
) + TFD_MAX_PAYLOAD_SIZE
);
2261 len
+= sizeof(*data
) + IWL_CSR_TO_DUMP
;
2263 /* PRPH registers */
2264 for (i
= 0; i
< ARRAY_SIZE(iwl_prph_dump_addr
); i
++) {
2265 /* The range includes both boundaries */
2266 int num_bytes_in_chunk
= iwl_prph_dump_addr
[i
].end
-
2267 iwl_prph_dump_addr
[i
].start
+ 4;
2269 len
+= sizeof(*data
) + sizeof(struct iwl_fw_error_dump_prph
) +
2274 len
+= sizeof(*data
) + (FH_MEM_UPPER_BOUND
- FH_MEM_LOWER_BOUND
);
2277 if (trans_pcie
->fw_mon_page
) {
2278 len
+= sizeof(*data
) + sizeof(struct iwl_fw_error_dump_fw_mon
) +
2279 trans_pcie
->fw_mon_size
;
2280 monitor_len
= trans_pcie
->fw_mon_size
;
2281 } else if (trans
->dbg_dest_tlv
) {
2284 base
= le32_to_cpu(trans
->dbg_dest_tlv
->base_reg
);
2285 end
= le32_to_cpu(trans
->dbg_dest_tlv
->end_reg
);
2287 base
= iwl_read_prph(trans
, base
) <<
2288 trans
->dbg_dest_tlv
->base_shift
;
2289 end
= iwl_read_prph(trans
, end
) <<
2290 trans
->dbg_dest_tlv
->end_shift
;
2292 /* Make "end" point to the actual end */
2293 if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_8000
||
2294 trans
->dbg_dest_tlv
->monitor_mode
== MARBH_MODE
)
2295 end
+= (1 << trans
->dbg_dest_tlv
->end_shift
);
2296 monitor_len
= end
- base
;
2297 len
+= sizeof(*data
) + sizeof(struct iwl_fw_error_dump_fw_mon
) +
2303 dump_data
= vzalloc(len
);
2308 data
= (void *)dump_data
->data
;
2309 data
->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD
);
2310 txcmd
= (void *)data
->data
;
2311 spin_lock_bh(&cmdq
->lock
);
2312 ptr
= cmdq
->q
.write_ptr
;
2313 for (i
= 0; i
< cmdq
->q
.n_window
; i
++) {
2314 u8 idx
= get_cmd_index(&cmdq
->q
, ptr
);
2317 cmdlen
= iwl_trans_pcie_get_cmdlen(&cmdq
->tfds
[ptr
]);
2318 caplen
= min_t(u32
, TFD_MAX_PAYLOAD_SIZE
, cmdlen
);
2321 len
+= sizeof(*txcmd
) + caplen
;
2322 txcmd
->cmdlen
= cpu_to_le32(cmdlen
);
2323 txcmd
->caplen
= cpu_to_le32(caplen
);
2324 memcpy(txcmd
->data
, cmdq
->entries
[idx
].cmd
, caplen
);
2325 txcmd
= (void *)((u8
*)txcmd
->data
+ caplen
);
2328 ptr
= iwl_queue_dec_wrap(ptr
);
2330 spin_unlock_bh(&cmdq
->lock
);
2332 data
->len
= cpu_to_le32(len
);
2333 len
+= sizeof(*data
);
2334 data
= iwl_fw_error_next_data(data
);
2336 len
+= iwl_trans_pcie_dump_prph(trans
, &data
);
2337 len
+= iwl_trans_pcie_dump_csr(trans
, &data
);
2338 len
+= iwl_trans_pcie_fh_regs_dump(trans
, &data
);
2339 /* data is already pointing to the next section */
2341 if ((trans_pcie
->fw_mon_page
&&
2342 trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_7000
) ||
2343 trans
->dbg_dest_tlv
) {
2344 struct iwl_fw_error_dump_fw_mon
*fw_mon_data
;
2345 u32 base
, write_ptr
, wrap_cnt
;
2347 /* If there was a dest TLV - use the values from there */
2348 if (trans
->dbg_dest_tlv
) {
2350 le32_to_cpu(trans
->dbg_dest_tlv
->write_ptr_reg
);
2351 wrap_cnt
= le32_to_cpu(trans
->dbg_dest_tlv
->wrap_count
);
2352 base
= le32_to_cpu(trans
->dbg_dest_tlv
->base_reg
);
2354 base
= MON_BUFF_BASE_ADDR
;
2355 write_ptr
= MON_BUFF_WRPTR
;
2356 wrap_cnt
= MON_BUFF_CYCLE_CNT
;
2359 data
->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR
);
2360 fw_mon_data
= (void *)data
->data
;
2361 fw_mon_data
->fw_mon_wr_ptr
=
2362 cpu_to_le32(iwl_read_prph(trans
, write_ptr
));
2363 fw_mon_data
->fw_mon_cycle_cnt
=
2364 cpu_to_le32(iwl_read_prph(trans
, wrap_cnt
));
2365 fw_mon_data
->fw_mon_base_ptr
=
2366 cpu_to_le32(iwl_read_prph(trans
, base
));
2368 len
+= sizeof(*data
) + sizeof(*fw_mon_data
);
2369 if (trans_pcie
->fw_mon_page
) {
2371 * The firmware is now asserted, it won't write anything
2372 * to the buffer. CPU can take ownership to fetch the
2373 * data. The buffer will be handed back to the device
2374 * before the firmware will be restarted.
2376 dma_sync_single_for_cpu(trans
->dev
,
2377 trans_pcie
->fw_mon_phys
,
2378 trans_pcie
->fw_mon_size
,
2380 memcpy(fw_mon_data
->data
,
2381 page_address(trans_pcie
->fw_mon_page
),
2382 trans_pcie
->fw_mon_size
);
2384 monitor_len
= trans_pcie
->fw_mon_size
;
2385 } else if (trans
->dbg_dest_tlv
->monitor_mode
== SMEM_MODE
) {
2387 * Update pointers to reflect actual values after
2390 base
= iwl_read_prph(trans
, base
) <<
2391 trans
->dbg_dest_tlv
->base_shift
;
2392 iwl_trans_read_mem(trans
, base
, fw_mon_data
->data
,
2393 monitor_len
/ sizeof(u32
));
2394 } else if (trans
->dbg_dest_tlv
->monitor_mode
== MARBH_MODE
) {
2396 iwl_trans_pci_dump_marbh_monitor(trans
,
2400 /* Didn't match anything - output no monitor data */
2405 data
->len
= cpu_to_le32(monitor_len
+ sizeof(*fw_mon_data
));
2408 dump_data
->len
= len
;
2413 static const struct iwl_trans_ops trans_ops_pcie
= {
2414 .start_hw
= iwl_trans_pcie_start_hw
,
2415 .op_mode_leave
= iwl_trans_pcie_op_mode_leave
,
2416 .fw_alive
= iwl_trans_pcie_fw_alive
,
2417 .start_fw
= iwl_trans_pcie_start_fw
,
2418 .stop_device
= iwl_trans_pcie_stop_device
,
2420 .d3_suspend
= iwl_trans_pcie_d3_suspend
,
2421 .d3_resume
= iwl_trans_pcie_d3_resume
,
2423 .send_cmd
= iwl_trans_pcie_send_hcmd
,
2425 .tx
= iwl_trans_pcie_tx
,
2426 .reclaim
= iwl_trans_pcie_reclaim
,
2428 .txq_disable
= iwl_trans_pcie_txq_disable
,
2429 .txq_enable
= iwl_trans_pcie_txq_enable
,
2431 .dbgfs_register
= iwl_trans_pcie_dbgfs_register
,
2433 .wait_tx_queue_empty
= iwl_trans_pcie_wait_txq_empty
,
2434 .freeze_txq_timer
= iwl_trans_pcie_freeze_txq_timer
,
2436 .write8
= iwl_trans_pcie_write8
,
2437 .write32
= iwl_trans_pcie_write32
,
2438 .read32
= iwl_trans_pcie_read32
,
2439 .read_prph
= iwl_trans_pcie_read_prph
,
2440 .write_prph
= iwl_trans_pcie_write_prph
,
2441 .read_mem
= iwl_trans_pcie_read_mem
,
2442 .write_mem
= iwl_trans_pcie_write_mem
,
2443 .configure
= iwl_trans_pcie_configure
,
2444 .set_pmi
= iwl_trans_pcie_set_pmi
,
2445 .grab_nic_access
= iwl_trans_pcie_grab_nic_access
,
2446 .release_nic_access
= iwl_trans_pcie_release_nic_access
,
2447 .set_bits_mask
= iwl_trans_pcie_set_bits_mask
,
2449 .ref
= iwl_trans_pcie_ref
,
2450 .unref
= iwl_trans_pcie_unref
,
2452 .dump_data
= iwl_trans_pcie_dump_data
,
2455 struct iwl_trans
*iwl_trans_pcie_alloc(struct pci_dev
*pdev
,
2456 const struct pci_device_id
*ent
,
2457 const struct iwl_cfg
*cfg
)
2459 struct iwl_trans_pcie
*trans_pcie
;
2460 struct iwl_trans
*trans
;
2464 trans
= iwl_trans_alloc(sizeof(struct iwl_trans_pcie
),
2465 &pdev
->dev
, cfg
, &trans_ops_pcie
, 0);
2467 return ERR_PTR(-ENOMEM
);
2469 trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2471 trans_pcie
->trans
= trans
;
2472 spin_lock_init(&trans_pcie
->irq_lock
);
2473 spin_lock_init(&trans_pcie
->reg_lock
);
2474 spin_lock_init(&trans_pcie
->ref_lock
);
2475 init_waitqueue_head(&trans_pcie
->ucode_write_waitq
);
2477 err
= pci_enable_device(pdev
);
2481 if (!cfg
->base_params
->pcie_l1_allowed
) {
2483 * W/A - seems to solve weird behavior. We need to remove this
2484 * if we don't want to stay in L1 all the time. This wastes a
2487 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
|
2488 PCIE_LINK_STATE_L1
|
2489 PCIE_LINK_STATE_CLKPM
);
2492 pci_set_master(pdev
);
2494 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(36));
2496 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(36));
2498 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
2500 err
= pci_set_consistent_dma_mask(pdev
,
2502 /* both attempts failed: */
2504 dev_err(&pdev
->dev
, "No suitable DMA available\n");
2505 goto out_pci_disable_device
;
2509 err
= pci_request_regions(pdev
, DRV_NAME
);
2511 dev_err(&pdev
->dev
, "pci_request_regions failed\n");
2512 goto out_pci_disable_device
;
2515 trans_pcie
->hw_base
= pci_ioremap_bar(pdev
, 0);
2516 if (!trans_pcie
->hw_base
) {
2517 dev_err(&pdev
->dev
, "pci_ioremap_bar failed\n");
2519 goto out_pci_release_regions
;
2522 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2523 * PCI Tx retries from interfering with C3 CPU state */
2524 pci_write_config_byte(pdev
, PCI_CFG_RETRY_TIMEOUT
, 0x00);
2526 trans
->dev
= &pdev
->dev
;
2527 trans_pcie
->pci_dev
= pdev
;
2528 iwl_disable_interrupts(trans
);
2530 err
= pci_enable_msi(pdev
);
2532 dev_err(&pdev
->dev
, "pci_enable_msi failed(0X%x)\n", err
);
2533 /* enable rfkill interrupt: hw bug w/a */
2534 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
2535 if (pci_cmd
& PCI_COMMAND_INTX_DISABLE
) {
2536 pci_cmd
&= ~PCI_COMMAND_INTX_DISABLE
;
2537 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
2541 trans
->hw_rev
= iwl_read32(trans
, CSR_HW_REV
);
2543 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2544 * changed, and now the revision step also includes bit 0-1 (no more
2545 * "dash" value). To keep hw_rev backwards compatible - we'll store it
2546 * in the old format.
2548 if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_8000
) {
2549 unsigned long flags
;
2552 trans
->hw_rev
= (trans
->hw_rev
& 0xfff0) |
2553 (CSR_HW_REV_STEP(trans
->hw_rev
<< 2) << 2);
2556 * in-order to recognize C step driver should read chip version
2557 * id located at the AUX bus MISC address space.
2559 iwl_set_bit(trans
, CSR_GP_CNTRL
,
2560 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
2563 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
2564 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
2565 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
2568 IWL_DEBUG_INFO(trans
, "Failed to wake up the nic\n");
2569 goto out_pci_disable_msi
;
2572 if (iwl_trans_grab_nic_access(trans
, false, &flags
)) {
2575 hw_step
= __iwl_read_prph(trans
, WFPM_CTRL_REG
);
2576 hw_step
|= ENABLE_WFPM
;
2577 __iwl_write_prph(trans
, WFPM_CTRL_REG
, hw_step
);
2578 hw_step
= __iwl_read_prph(trans
, AUX_MISC_REG
);
2579 hw_step
= (hw_step
>> HW_STEP_LOCATION_BITS
) & 0xF;
2581 trans
->hw_rev
= (trans
->hw_rev
& 0xFFFFFFF3) |
2582 (SILICON_C_STEP
<< 2);
2583 iwl_trans_release_nic_access(trans
, &flags
);
2587 trans
->hw_id
= (pdev
->device
<< 16) + pdev
->subsystem_device
;
2588 snprintf(trans
->hw_id_str
, sizeof(trans
->hw_id_str
),
2589 "PCI ID: 0x%04X:0x%04X", pdev
->device
, pdev
->subsystem_device
);
2591 /* Initialize the wait queue for commands */
2592 init_waitqueue_head(&trans_pcie
->wait_command_queue
);
2594 if (iwl_pcie_alloc_ict(trans
))
2595 goto out_pci_disable_msi
;
2597 err
= request_threaded_irq(pdev
->irq
, iwl_pcie_isr
,
2598 iwl_pcie_irq_handler
,
2599 IRQF_SHARED
, DRV_NAME
, trans
);
2601 IWL_ERR(trans
, "Error allocating IRQ %d\n", pdev
->irq
);
2605 trans_pcie
->inta_mask
= CSR_INI_SET_MASK
;
2606 trans
->d0i3_mode
= IWL_D0I3_MODE_ON_SUSPEND
;
2611 iwl_pcie_free_ict(trans
);
2612 out_pci_disable_msi
:
2613 pci_disable_msi(pdev
);
2614 out_pci_release_regions
:
2615 pci_release_regions(pdev
);
2616 out_pci_disable_device
:
2617 pci_disable_device(pdev
);
2619 iwl_trans_free(trans
);
2620 return ERR_PTR(err
);