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Merge branch 'for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/wq
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / pcie / trans.c
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called COPYING.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63 #include <linux/pci.h>
64 #include <linux/pci-aspm.h>
65 #include <linux/interrupt.h>
66 #include <linux/debugfs.h>
67 #include <linux/sched.h>
68 #include <linux/bitops.h>
69 #include <linux/gfp.h>
70
71 #include "iwl-drv.h"
72 #include "iwl-trans.h"
73 #include "iwl-csr.h"
74 #include "iwl-prph.h"
75 #include "iwl-agn-hw.h"
76 #include "internal.h"
77
78 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
79 {
80 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
81 ((reg & 0x0000ffff) | (2 << 28)));
82 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
83 }
84
85 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
86 {
87 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
88 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
89 ((reg & 0x0000ffff) | (3 << 28)));
90 }
91
92 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
93 {
94 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
95 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
96 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
97 ~APMG_PS_CTRL_MSK_PWR_SRC);
98 else
99 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
100 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
101 ~APMG_PS_CTRL_MSK_PWR_SRC);
102 }
103
104 /* PCI registers */
105 #define PCI_CFG_RETRY_TIMEOUT 0x041
106 #define CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC
107
108 static void iwl_pcie_apm_config(struct iwl_trans *trans)
109 {
110 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
111 u16 lctl;
112
113 /*
114 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
115 * Check if BIOS (or OS) enabled L1-ASPM on this device.
116 * If so (likely), disable L0S, so device moves directly L0->L1;
117 * costs negligible amount of power savings.
118 * If not (unlikely), enable L0S, so there is at least some
119 * power savings, even without L1.
120 */
121 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
122 if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
123 /* L1-ASPM enabled; disable(!) L0S */
124 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
125 dev_info(trans->dev, "L1 Enabled; Disabling L0S\n");
126 } else {
127 /* L1-ASPM disabled; enable(!) L0S */
128 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
129 dev_info(trans->dev, "L1 Disabled; Enabling L0S\n");
130 }
131 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
132 }
133
134 /*
135 * Start up NIC's basic functionality after it has been reset
136 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
137 * NOTE: This does not load uCode nor start the embedded processor
138 */
139 static int iwl_pcie_apm_init(struct iwl_trans *trans)
140 {
141 int ret = 0;
142 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
143
144 /*
145 * Use "set_bit" below rather than "write", to preserve any hardware
146 * bits already set by default after reset.
147 */
148
149 /* Disable L0S exit timer (platform NMI Work/Around) */
150 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
151 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
152 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
153
154 /*
155 * Disable L0s without affecting L1;
156 * don't wait for ICH L0s (ICH bug W/A)
157 */
158 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
159 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
160
161 /* Set FH wait threshold to maximum (HW error during stress W/A) */
162 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
163
164 /*
165 * Enable HAP INTA (interrupt from management bus) to
166 * wake device's PCI Express link L1a -> L0s
167 */
168 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
169 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
170
171 iwl_pcie_apm_config(trans);
172
173 /* Configure analog phase-lock-loop before activating to D0A */
174 if (trans->cfg->base_params->pll_cfg_val)
175 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
176 trans->cfg->base_params->pll_cfg_val);
177
178 /*
179 * Set "initialization complete" bit to move adapter from
180 * D0U* --> D0A* (powered-up active) state.
181 */
182 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
183
184 /*
185 * Wait for clock stabilization; once stabilized, access to
186 * device-internal resources is supported, e.g. iwl_write_prph()
187 * and accesses to uCode SRAM.
188 */
189 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
190 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
191 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
192 if (ret < 0) {
193 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
194 goto out;
195 }
196
197 if (trans->cfg->host_interrupt_operation_mode) {
198 /*
199 * This is a bit of an abuse - This is needed for 7260 / 3160
200 * only check host_interrupt_operation_mode even if this is
201 * not related to host_interrupt_operation_mode.
202 *
203 * Enable the oscillator to count wake up time for L1 exit. This
204 * consumes slightly more power (100uA) - but allows to be sure
205 * that we wake up from L1 on time.
206 *
207 * This looks weird: read twice the same register, discard the
208 * value, set a bit, and yet again, read that same register
209 * just to discard the value. But that's the way the hardware
210 * seems to like it.
211 */
212 iwl_read_prph(trans, OSC_CLK);
213 iwl_read_prph(trans, OSC_CLK);
214 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
215 iwl_read_prph(trans, OSC_CLK);
216 iwl_read_prph(trans, OSC_CLK);
217 }
218
219 /*
220 * Enable DMA clock and wait for it to stabilize.
221 *
222 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
223 * bits do not disable clocks. This preserves any hardware
224 * bits already set by default in "CLK_CTRL_REG" after reset.
225 */
226 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
227 iwl_write_prph(trans, APMG_CLK_EN_REG,
228 APMG_CLK_VAL_DMA_CLK_RQT);
229 udelay(20);
230
231 /* Disable L1-Active */
232 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
233 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
234
235 /* Clear the interrupt in APMG if the NIC is in RFKILL */
236 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
237 APMG_RTC_INT_STT_RFKILL);
238 }
239
240 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
241
242 out:
243 return ret;
244 }
245
246 /*
247 * Enable LP XTAL to avoid HW bug where device may consume much power if
248 * FW is not loaded after device reset. LP XTAL is disabled by default
249 * after device HW reset. Do it only if XTAL is fed by internal source.
250 * Configure device's "persistence" mode to avoid resetting XTAL again when
251 * SHRD_HW_RST occurs in S3.
252 */
253 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
254 {
255 int ret;
256 u32 apmg_gp1_reg;
257 u32 apmg_xtal_cfg_reg;
258 u32 dl_cfg_reg;
259
260 /* Force XTAL ON */
261 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
262 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
263
264 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
265 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
266
267 udelay(10);
268
269 /*
270 * Set "initialization complete" bit to move adapter from
271 * D0U* --> D0A* (powered-up active) state.
272 */
273 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
274
275 /*
276 * Wait for clock stabilization; once stabilized, access to
277 * device-internal resources is possible.
278 */
279 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
280 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
281 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
282 25000);
283 if (WARN_ON(ret < 0)) {
284 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
285 /* Release XTAL ON request */
286 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
287 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
288 return;
289 }
290
291 /*
292 * Clear "disable persistence" to avoid LP XTAL resetting when
293 * SHRD_HW_RST is applied in S3.
294 */
295 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
296 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
297
298 /*
299 * Force APMG XTAL to be active to prevent its disabling by HW
300 * caused by APMG idle state.
301 */
302 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
303 SHR_APMG_XTAL_CFG_REG);
304 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
305 apmg_xtal_cfg_reg |
306 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
307
308 /*
309 * Reset entire device again - do controller reset (results in
310 * SHRD_HW_RST). Turn MAC off before proceeding.
311 */
312 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
313
314 udelay(10);
315
316 /* Enable LP XTAL by indirect access through CSR */
317 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
318 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
319 SHR_APMG_GP1_WF_XTAL_LP_EN |
320 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
321
322 /* Clear delay line clock power up */
323 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
324 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
325 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
326
327 /*
328 * Enable persistence mode to avoid LP XTAL resetting when
329 * SHRD_HW_RST is applied in S3.
330 */
331 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
332 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
333
334 /*
335 * Clear "initialization complete" bit to move adapter from
336 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
337 */
338 iwl_clear_bit(trans, CSR_GP_CNTRL,
339 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
340
341 /* Activates XTAL resources monitor */
342 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
343 CSR_MONITOR_XTAL_RESOURCES);
344
345 /* Release XTAL ON request */
346 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
347 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
348 udelay(10);
349
350 /* Release APMG XTAL */
351 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
352 apmg_xtal_cfg_reg &
353 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
354 }
355
356 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
357 {
358 int ret = 0;
359
360 /* stop device's busmaster DMA activity */
361 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
362
363 ret = iwl_poll_bit(trans, CSR_RESET,
364 CSR_RESET_REG_FLAG_MASTER_DISABLED,
365 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
366 if (ret)
367 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
368
369 IWL_DEBUG_INFO(trans, "stop master\n");
370
371 return ret;
372 }
373
374 static void iwl_pcie_apm_stop(struct iwl_trans *trans)
375 {
376 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
377
378 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
379
380 /* Stop device's DMA activity */
381 iwl_pcie_apm_stop_master(trans);
382
383 if (trans->cfg->lp_xtal_workaround) {
384 iwl_pcie_apm_lp_xtal_enable(trans);
385 return;
386 }
387
388 /* Reset the entire device */
389 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
390
391 udelay(10);
392
393 /*
394 * Clear "initialization complete" bit to move adapter from
395 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
396 */
397 iwl_clear_bit(trans, CSR_GP_CNTRL,
398 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
399 }
400
401 static int iwl_pcie_nic_init(struct iwl_trans *trans)
402 {
403 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
404
405 /* nic_init */
406 spin_lock(&trans_pcie->irq_lock);
407 iwl_pcie_apm_init(trans);
408
409 spin_unlock(&trans_pcie->irq_lock);
410
411 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
412 iwl_pcie_set_pwr(trans, false);
413
414 iwl_op_mode_nic_config(trans->op_mode);
415
416 /* Allocate the RX queue, or reset if it is already allocated */
417 iwl_pcie_rx_init(trans);
418
419 /* Allocate or reset and init all Tx and Command queues */
420 if (iwl_pcie_tx_init(trans))
421 return -ENOMEM;
422
423 if (trans->cfg->base_params->shadow_reg_enable) {
424 /* enable shadow regs in HW */
425 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
426 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
427 }
428
429 return 0;
430 }
431
432 #define HW_READY_TIMEOUT (50)
433
434 /* Note: returns poll_bit return value, which is >= 0 if success */
435 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
436 {
437 int ret;
438
439 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
440 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
441
442 /* See if we got it */
443 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
444 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
445 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
446 HW_READY_TIMEOUT);
447
448 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
449 return ret;
450 }
451
452 /* Note: returns standard 0/-ERROR code */
453 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
454 {
455 int ret;
456 int t = 0;
457
458 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
459
460 ret = iwl_pcie_set_hw_ready(trans);
461 /* If the card is ready, exit 0 */
462 if (ret >= 0)
463 return 0;
464
465 /* If HW is not ready, prepare the conditions to check again */
466 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
467 CSR_HW_IF_CONFIG_REG_PREPARE);
468
469 do {
470 ret = iwl_pcie_set_hw_ready(trans);
471 if (ret >= 0)
472 return 0;
473
474 usleep_range(200, 1000);
475 t += 200;
476 } while (t < 150000);
477
478 return ret;
479 }
480
481 /*
482 * ucode
483 */
484 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
485 dma_addr_t phy_addr, u32 byte_cnt)
486 {
487 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
488 int ret;
489
490 trans_pcie->ucode_write_complete = false;
491
492 iwl_write_direct32(trans,
493 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
494 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
495
496 iwl_write_direct32(trans,
497 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
498 dst_addr);
499
500 iwl_write_direct32(trans,
501 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
502 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
503
504 iwl_write_direct32(trans,
505 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
506 (iwl_get_dma_hi_addr(phy_addr)
507 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
508
509 iwl_write_direct32(trans,
510 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
511 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
512 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
513 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
514
515 iwl_write_direct32(trans,
516 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
517 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
518 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
519 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
520
521 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
522 trans_pcie->ucode_write_complete, 5 * HZ);
523 if (!ret) {
524 IWL_ERR(trans, "Failed to load firmware chunk!\n");
525 return -ETIMEDOUT;
526 }
527
528 return 0;
529 }
530
531 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
532 const struct fw_desc *section)
533 {
534 u8 *v_addr;
535 dma_addr_t p_addr;
536 u32 offset, chunk_sz = section->len;
537 int ret = 0;
538
539 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
540 section_num);
541
542 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
543 GFP_KERNEL | __GFP_NOWARN);
544 if (!v_addr) {
545 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
546 chunk_sz = PAGE_SIZE;
547 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
548 &p_addr, GFP_KERNEL);
549 if (!v_addr)
550 return -ENOMEM;
551 }
552
553 for (offset = 0; offset < section->len; offset += chunk_sz) {
554 u32 copy_size;
555
556 copy_size = min_t(u32, chunk_sz, section->len - offset);
557
558 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
559 ret = iwl_pcie_load_firmware_chunk(trans,
560 section->offset + offset,
561 p_addr, copy_size);
562 if (ret) {
563 IWL_ERR(trans,
564 "Could not load the [%d] uCode section\n",
565 section_num);
566 break;
567 }
568 }
569
570 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
571 return ret;
572 }
573
574 static int iwl_pcie_load_cpu_secured_sections(struct iwl_trans *trans,
575 const struct fw_img *image,
576 int cpu,
577 int *first_ucode_section)
578 {
579 int shift_param;
580 int i, ret = 0;
581 u32 last_read_idx = 0;
582
583 if (cpu == 1) {
584 shift_param = 0;
585 *first_ucode_section = 0;
586 } else {
587 shift_param = 16;
588 (*first_ucode_section)++;
589 }
590
591 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
592 last_read_idx = i;
593
594 if (!image->sec[i].data ||
595 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
596 IWL_DEBUG_FW(trans,
597 "Break since Data not valid or Empty section, sec = %d\n",
598 i);
599 break;
600 }
601
602 if (i == (*first_ucode_section) + 1)
603 /* set CPU to started */
604 iwl_set_bits_prph(trans,
605 CSR_UCODE_LOAD_STATUS_ADDR,
606 LMPM_CPU_HDRS_LOADING_COMPLETED
607 << shift_param);
608
609 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
610 if (ret)
611 return ret;
612 }
613 /* image loading complete */
614 iwl_set_bits_prph(trans,
615 CSR_UCODE_LOAD_STATUS_ADDR,
616 LMPM_CPU_UCODE_LOADING_COMPLETED << shift_param);
617
618 *first_ucode_section = last_read_idx;
619
620 return 0;
621 }
622
623 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
624 const struct fw_img *image,
625 int cpu,
626 int *first_ucode_section)
627 {
628 int shift_param;
629 int i, ret = 0;
630 u32 last_read_idx = 0;
631
632 if (cpu == 1) {
633 shift_param = 0;
634 *first_ucode_section = 0;
635 } else {
636 shift_param = 16;
637 (*first_ucode_section)++;
638 }
639
640 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
641 last_read_idx = i;
642
643 if (!image->sec[i].data ||
644 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
645 IWL_DEBUG_FW(trans,
646 "Break since Data not valid or Empty section, sec = %d\n",
647 i);
648 break;
649 }
650
651 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
652 if (ret)
653 return ret;
654 }
655
656 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
657 iwl_set_bits_prph(trans,
658 CSR_UCODE_LOAD_STATUS_ADDR,
659 (LMPM_CPU_UCODE_LOADING_COMPLETED |
660 LMPM_CPU_HDRS_LOADING_COMPLETED |
661 LMPM_CPU_UCODE_LOADING_STARTED) <<
662 shift_param);
663
664 *first_ucode_section = last_read_idx;
665
666 return 0;
667 }
668
669 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
670 const struct fw_img *image)
671 {
672 int ret = 0;
673 int first_ucode_section;
674
675 IWL_DEBUG_FW(trans,
676 "working with %s image\n",
677 image->is_secure ? "Secured" : "Non Secured");
678 IWL_DEBUG_FW(trans,
679 "working with %s CPU\n",
680 image->is_dual_cpus ? "Dual" : "Single");
681
682 /* configure the ucode to be ready to get the secured image */
683 if (image->is_secure) {
684 /* set secure boot inspector addresses */
685 iwl_write_prph(trans,
686 LMPM_SECURE_INSPECTOR_CODE_ADDR,
687 LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE);
688
689 iwl_write_prph(trans,
690 LMPM_SECURE_INSPECTOR_DATA_ADDR,
691 LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE);
692
693 /* set CPU1 header address */
694 iwl_write_prph(trans,
695 LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR,
696 LMPM_SECURE_CPU1_HDR_MEM_SPACE);
697
698 /* load to FW the binary Secured sections of CPU1 */
699 ret = iwl_pcie_load_cpu_secured_sections(trans, image, 1,
700 &first_ucode_section);
701 if (ret)
702 return ret;
703
704 } else {
705 /* load to FW the binary Non secured sections of CPU1 */
706 ret = iwl_pcie_load_cpu_sections(trans, image, 1,
707 &first_ucode_section);
708 if (ret)
709 return ret;
710 }
711
712 if (image->is_dual_cpus) {
713 /* set CPU2 header address */
714 iwl_write_prph(trans,
715 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
716 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
717
718 /* load to FW the binary sections of CPU2 */
719 if (image->is_secure)
720 ret = iwl_pcie_load_cpu_secured_sections(
721 trans, image, 2,
722 &first_ucode_section);
723 else
724 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
725 &first_ucode_section);
726 if (ret)
727 return ret;
728 }
729
730 /* release CPU reset */
731 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
732 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
733 else
734 iwl_write32(trans, CSR_RESET, 0);
735
736 if (image->is_secure) {
737 /* wait for image verification to complete */
738 ret = iwl_poll_prph_bit(trans,
739 LMPM_SECURE_BOOT_CPU1_STATUS_ADDR,
740 LMPM_SECURE_BOOT_STATUS_SUCCESS,
741 LMPM_SECURE_BOOT_STATUS_SUCCESS,
742 LMPM_SECURE_TIME_OUT);
743
744 if (ret < 0) {
745 IWL_ERR(trans, "Time out on secure boot process\n");
746 return ret;
747 }
748 }
749
750 return 0;
751 }
752
753 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
754 const struct fw_img *fw, bool run_in_rfkill)
755 {
756 int ret;
757 bool hw_rfkill;
758
759 /* This may fail if AMT took ownership of the device */
760 if (iwl_pcie_prepare_card_hw(trans)) {
761 IWL_WARN(trans, "Exit HW not ready\n");
762 return -EIO;
763 }
764
765 iwl_enable_rfkill_int(trans);
766
767 /* If platform's RF_KILL switch is NOT set to KILL */
768 hw_rfkill = iwl_is_rfkill_set(trans);
769 if (hw_rfkill)
770 set_bit(STATUS_RFKILL, &trans->status);
771 else
772 clear_bit(STATUS_RFKILL, &trans->status);
773 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
774 if (hw_rfkill && !run_in_rfkill)
775 return -ERFKILL;
776
777 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
778
779 ret = iwl_pcie_nic_init(trans);
780 if (ret) {
781 IWL_ERR(trans, "Unable to init nic\n");
782 return ret;
783 }
784
785 /* make sure rfkill handshake bits are cleared */
786 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
787 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
788 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
789
790 /* clear (again), then enable host interrupts */
791 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
792 iwl_enable_interrupts(trans);
793
794 /* really make sure rfkill handshake bits are cleared */
795 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
796 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
797
798 /* Load the given image to the HW */
799 return iwl_pcie_load_given_ucode(trans, fw);
800 }
801
802 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
803 {
804 iwl_pcie_reset_ict(trans);
805 iwl_pcie_tx_start(trans, scd_addr);
806 }
807
808 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
809 {
810 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
811 bool hw_rfkill, was_hw_rfkill;
812
813 was_hw_rfkill = iwl_is_rfkill_set(trans);
814
815 /* tell the device to stop sending interrupts */
816 spin_lock(&trans_pcie->irq_lock);
817 iwl_disable_interrupts(trans);
818 spin_unlock(&trans_pcie->irq_lock);
819
820 /* device going down, Stop using ICT table */
821 iwl_pcie_disable_ict(trans);
822
823 /*
824 * If a HW restart happens during firmware loading,
825 * then the firmware loading might call this function
826 * and later it might be called again due to the
827 * restart. So don't process again if the device is
828 * already dead.
829 */
830 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
831 iwl_pcie_tx_stop(trans);
832 iwl_pcie_rx_stop(trans);
833
834 /* Power-down device's busmaster DMA clocks */
835 iwl_write_prph(trans, APMG_CLK_DIS_REG,
836 APMG_CLK_VAL_DMA_CLK_RQT);
837 udelay(5);
838 }
839
840 /* Make sure (redundant) we've released our request to stay awake */
841 iwl_clear_bit(trans, CSR_GP_CNTRL,
842 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
843
844 /* Stop the device, and put it in low power state */
845 iwl_pcie_apm_stop(trans);
846
847 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
848 * Clean again the interrupt here
849 */
850 spin_lock(&trans_pcie->irq_lock);
851 iwl_disable_interrupts(trans);
852 spin_unlock(&trans_pcie->irq_lock);
853
854 /* stop and reset the on-board processor */
855 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
856
857 /* clear all status bits */
858 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
859 clear_bit(STATUS_INT_ENABLED, &trans->status);
860 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
861 clear_bit(STATUS_TPOWER_PMI, &trans->status);
862 clear_bit(STATUS_RFKILL, &trans->status);
863
864 /*
865 * Even if we stop the HW, we still want the RF kill
866 * interrupt
867 */
868 iwl_enable_rfkill_int(trans);
869
870 /*
871 * Check again since the RF kill state may have changed while
872 * all the interrupts were disabled, in this case we couldn't
873 * receive the RF kill interrupt and update the state in the
874 * op_mode.
875 * Don't call the op_mode if the rkfill state hasn't changed.
876 * This allows the op_mode to call stop_device from the rfkill
877 * notification without endless recursion. Under very rare
878 * circumstances, we might have a small recursion if the rfkill
879 * state changed exactly now while we were called from stop_device.
880 * This is very unlikely but can happen and is supported.
881 */
882 hw_rfkill = iwl_is_rfkill_set(trans);
883 if (hw_rfkill)
884 set_bit(STATUS_RFKILL, &trans->status);
885 else
886 clear_bit(STATUS_RFKILL, &trans->status);
887 if (hw_rfkill != was_hw_rfkill)
888 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
889 }
890
891 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
892 {
893 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
894 iwl_trans_pcie_stop_device(trans);
895 }
896
897 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
898 {
899 iwl_disable_interrupts(trans);
900
901 /*
902 * in testing mode, the host stays awake and the
903 * hardware won't be reset (not even partially)
904 */
905 if (test)
906 return;
907
908 iwl_pcie_disable_ict(trans);
909
910 iwl_clear_bit(trans, CSR_GP_CNTRL,
911 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
912 iwl_clear_bit(trans, CSR_GP_CNTRL,
913 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
914
915 /*
916 * reset TX queues -- some of their registers reset during S3
917 * so if we don't reset everything here the D3 image would try
918 * to execute some invalid memory upon resume
919 */
920 iwl_trans_pcie_tx_reset(trans);
921
922 iwl_pcie_set_pwr(trans, true);
923 }
924
925 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
926 enum iwl_d3_status *status,
927 bool test)
928 {
929 u32 val;
930 int ret;
931
932 if (test) {
933 iwl_enable_interrupts(trans);
934 *status = IWL_D3_STATUS_ALIVE;
935 return 0;
936 }
937
938 iwl_pcie_set_pwr(trans, false);
939
940 val = iwl_read32(trans, CSR_RESET);
941 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) {
942 *status = IWL_D3_STATUS_RESET;
943 return 0;
944 }
945
946 /*
947 * Also enables interrupts - none will happen as the device doesn't
948 * know we're waking it up, only when the opmode actually tells it
949 * after this call.
950 */
951 iwl_pcie_reset_ict(trans);
952
953 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
954 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
955
956 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
957 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
958 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
959 25000);
960 if (ret) {
961 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
962 return ret;
963 }
964
965 iwl_trans_pcie_tx_reset(trans);
966
967 ret = iwl_pcie_rx_init(trans);
968 if (ret) {
969 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
970 return ret;
971 }
972
973 *status = IWL_D3_STATUS_ALIVE;
974 return 0;
975 }
976
977 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
978 {
979 bool hw_rfkill;
980 int err;
981
982 err = iwl_pcie_prepare_card_hw(trans);
983 if (err) {
984 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
985 return err;
986 }
987
988 /* Reset the entire device */
989 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
990
991 usleep_range(10, 15);
992
993 iwl_pcie_apm_init(trans);
994
995 /* From now on, the op_mode will be kept updated about RF kill state */
996 iwl_enable_rfkill_int(trans);
997
998 hw_rfkill = iwl_is_rfkill_set(trans);
999 if (hw_rfkill)
1000 set_bit(STATUS_RFKILL, &trans->status);
1001 else
1002 clear_bit(STATUS_RFKILL, &trans->status);
1003 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1004
1005 return 0;
1006 }
1007
1008 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1009 {
1010 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1011
1012 /* disable interrupts - don't enable HW RF kill interrupt */
1013 spin_lock(&trans_pcie->irq_lock);
1014 iwl_disable_interrupts(trans);
1015 spin_unlock(&trans_pcie->irq_lock);
1016
1017 iwl_pcie_apm_stop(trans);
1018
1019 spin_lock(&trans_pcie->irq_lock);
1020 iwl_disable_interrupts(trans);
1021 spin_unlock(&trans_pcie->irq_lock);
1022
1023 iwl_pcie_disable_ict(trans);
1024 }
1025
1026 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1027 {
1028 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1029 }
1030
1031 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1032 {
1033 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1034 }
1035
1036 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1037 {
1038 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1039 }
1040
1041 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1042 {
1043 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1044 ((reg & 0x000FFFFF) | (3 << 24)));
1045 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1046 }
1047
1048 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1049 u32 val)
1050 {
1051 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1052 ((addr & 0x000FFFFF) | (3 << 24)));
1053 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1054 }
1055
1056 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1057 const struct iwl_trans_config *trans_cfg)
1058 {
1059 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1060
1061 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1062 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1063 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1064 trans_pcie->n_no_reclaim_cmds = 0;
1065 else
1066 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1067 if (trans_pcie->n_no_reclaim_cmds)
1068 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1069 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1070
1071 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1072 if (trans_pcie->rx_buf_size_8k)
1073 trans_pcie->rx_page_order = get_order(8 * 1024);
1074 else
1075 trans_pcie->rx_page_order = get_order(4 * 1024);
1076
1077 trans_pcie->wd_timeout =
1078 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
1079
1080 trans_pcie->command_names = trans_cfg->command_names;
1081 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1082 }
1083
1084 void iwl_trans_pcie_free(struct iwl_trans *trans)
1085 {
1086 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1087
1088 synchronize_irq(trans_pcie->pci_dev->irq);
1089
1090 iwl_pcie_tx_free(trans);
1091 iwl_pcie_rx_free(trans);
1092
1093 free_irq(trans_pcie->pci_dev->irq, trans);
1094 iwl_pcie_free_ict(trans);
1095
1096 pci_disable_msi(trans_pcie->pci_dev);
1097 iounmap(trans_pcie->hw_base);
1098 pci_release_regions(trans_pcie->pci_dev);
1099 pci_disable_device(trans_pcie->pci_dev);
1100 kmem_cache_destroy(trans->dev_cmd_pool);
1101
1102 kfree(trans);
1103 }
1104
1105 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1106 {
1107 if (state)
1108 set_bit(STATUS_TPOWER_PMI, &trans->status);
1109 else
1110 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1111 }
1112
1113 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1114 unsigned long *flags)
1115 {
1116 int ret;
1117 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1118
1119 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1120
1121 if (trans_pcie->cmd_in_flight)
1122 goto out;
1123
1124 /* this bit wakes up the NIC */
1125 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1126 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1127
1128 /*
1129 * These bits say the device is running, and should keep running for
1130 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1131 * but they do not indicate that embedded SRAM is restored yet;
1132 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1133 * to/from host DRAM when sleeping/waking for power-saving.
1134 * Each direction takes approximately 1/4 millisecond; with this
1135 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1136 * series of register accesses are expected (e.g. reading Event Log),
1137 * to keep device from sleeping.
1138 *
1139 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1140 * SRAM is okay/restored. We don't check that here because this call
1141 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1142 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1143 *
1144 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1145 * and do not save/restore SRAM when power cycling.
1146 */
1147 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1148 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1149 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1150 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1151 if (unlikely(ret < 0)) {
1152 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1153 if (!silent) {
1154 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1155 WARN_ONCE(1,
1156 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1157 val);
1158 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1159 return false;
1160 }
1161 }
1162
1163 out:
1164 /*
1165 * Fool sparse by faking we release the lock - sparse will
1166 * track nic_access anyway.
1167 */
1168 __release(&trans_pcie->reg_lock);
1169 return true;
1170 }
1171
1172 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1173 unsigned long *flags)
1174 {
1175 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1176
1177 lockdep_assert_held(&trans_pcie->reg_lock);
1178
1179 /*
1180 * Fool sparse by faking we acquiring the lock - sparse will
1181 * track nic_access anyway.
1182 */
1183 __acquire(&trans_pcie->reg_lock);
1184
1185 if (trans_pcie->cmd_in_flight)
1186 goto out;
1187
1188 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1189 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1190 /*
1191 * Above we read the CSR_GP_CNTRL register, which will flush
1192 * any previous writes, but we need the write that clears the
1193 * MAC_ACCESS_REQ bit to be performed before any other writes
1194 * scheduled on different CPUs (after we drop reg_lock).
1195 */
1196 mmiowb();
1197 out:
1198 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1199 }
1200
1201 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1202 void *buf, int dwords)
1203 {
1204 unsigned long flags;
1205 int offs, ret = 0;
1206 u32 *vals = buf;
1207
1208 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1209 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1210 for (offs = 0; offs < dwords; offs++)
1211 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1212 iwl_trans_release_nic_access(trans, &flags);
1213 } else {
1214 ret = -EBUSY;
1215 }
1216 return ret;
1217 }
1218
1219 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1220 const void *buf, int dwords)
1221 {
1222 unsigned long flags;
1223 int offs, ret = 0;
1224 const u32 *vals = buf;
1225
1226 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1227 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1228 for (offs = 0; offs < dwords; offs++)
1229 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1230 vals ? vals[offs] : 0);
1231 iwl_trans_release_nic_access(trans, &flags);
1232 } else {
1233 ret = -EBUSY;
1234 }
1235 return ret;
1236 }
1237
1238 #define IWL_FLUSH_WAIT_MS 2000
1239
1240 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
1241 {
1242 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1243 struct iwl_txq *txq;
1244 struct iwl_queue *q;
1245 int cnt;
1246 unsigned long now = jiffies;
1247 u32 scd_sram_addr;
1248 u8 buf[16];
1249 int ret = 0;
1250
1251 /* waiting for all the tx frames complete might take a while */
1252 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1253 if (cnt == trans_pcie->cmd_queue)
1254 continue;
1255 txq = &trans_pcie->txq[cnt];
1256 q = &txq->q;
1257 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1258 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1259 msleep(1);
1260
1261 if (q->read_ptr != q->write_ptr) {
1262 IWL_ERR(trans,
1263 "fail to flush all tx fifo queues Q %d\n", cnt);
1264 ret = -ETIMEDOUT;
1265 break;
1266 }
1267 }
1268
1269 if (!ret)
1270 return 0;
1271
1272 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1273 txq->q.read_ptr, txq->q.write_ptr);
1274
1275 scd_sram_addr = trans_pcie->scd_base_addr +
1276 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1277 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1278
1279 iwl_print_hex_error(trans, buf, sizeof(buf));
1280
1281 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1282 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1283 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1284
1285 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1286 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1287 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1288 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1289 u32 tbl_dw =
1290 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1291 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1292
1293 if (cnt & 0x1)
1294 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1295 else
1296 tbl_dw = tbl_dw & 0x0000FFFF;
1297
1298 IWL_ERR(trans,
1299 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1300 cnt, active ? "" : "in", fifo, tbl_dw,
1301 iwl_read_prph(trans,
1302 SCD_QUEUE_RDPTR(cnt)) & (txq->q.n_bd - 1),
1303 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1304 }
1305
1306 return ret;
1307 }
1308
1309 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1310 u32 mask, u32 value)
1311 {
1312 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1313 unsigned long flags;
1314
1315 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1316 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1317 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1318 }
1319
1320 static const char *get_csr_string(int cmd)
1321 {
1322 #define IWL_CMD(x) case x: return #x
1323 switch (cmd) {
1324 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1325 IWL_CMD(CSR_INT_COALESCING);
1326 IWL_CMD(CSR_INT);
1327 IWL_CMD(CSR_INT_MASK);
1328 IWL_CMD(CSR_FH_INT_STATUS);
1329 IWL_CMD(CSR_GPIO_IN);
1330 IWL_CMD(CSR_RESET);
1331 IWL_CMD(CSR_GP_CNTRL);
1332 IWL_CMD(CSR_HW_REV);
1333 IWL_CMD(CSR_EEPROM_REG);
1334 IWL_CMD(CSR_EEPROM_GP);
1335 IWL_CMD(CSR_OTP_GP_REG);
1336 IWL_CMD(CSR_GIO_REG);
1337 IWL_CMD(CSR_GP_UCODE_REG);
1338 IWL_CMD(CSR_GP_DRIVER_REG);
1339 IWL_CMD(CSR_UCODE_DRV_GP1);
1340 IWL_CMD(CSR_UCODE_DRV_GP2);
1341 IWL_CMD(CSR_LED_REG);
1342 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1343 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1344 IWL_CMD(CSR_ANA_PLL_CFG);
1345 IWL_CMD(CSR_HW_REV_WA_REG);
1346 IWL_CMD(CSR_MONITOR_STATUS_REG);
1347 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1348 default:
1349 return "UNKNOWN";
1350 }
1351 #undef IWL_CMD
1352 }
1353
1354 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1355 {
1356 int i;
1357 static const u32 csr_tbl[] = {
1358 CSR_HW_IF_CONFIG_REG,
1359 CSR_INT_COALESCING,
1360 CSR_INT,
1361 CSR_INT_MASK,
1362 CSR_FH_INT_STATUS,
1363 CSR_GPIO_IN,
1364 CSR_RESET,
1365 CSR_GP_CNTRL,
1366 CSR_HW_REV,
1367 CSR_EEPROM_REG,
1368 CSR_EEPROM_GP,
1369 CSR_OTP_GP_REG,
1370 CSR_GIO_REG,
1371 CSR_GP_UCODE_REG,
1372 CSR_GP_DRIVER_REG,
1373 CSR_UCODE_DRV_GP1,
1374 CSR_UCODE_DRV_GP2,
1375 CSR_LED_REG,
1376 CSR_DRAM_INT_TBL_REG,
1377 CSR_GIO_CHICKEN_BITS,
1378 CSR_ANA_PLL_CFG,
1379 CSR_MONITOR_STATUS_REG,
1380 CSR_HW_REV_WA_REG,
1381 CSR_DBG_HPET_MEM_REG
1382 };
1383 IWL_ERR(trans, "CSR values:\n");
1384 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1385 "CSR_INT_PERIODIC_REG)\n");
1386 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1387 IWL_ERR(trans, " %25s: 0X%08x\n",
1388 get_csr_string(csr_tbl[i]),
1389 iwl_read32(trans, csr_tbl[i]));
1390 }
1391 }
1392
1393 #ifdef CONFIG_IWLWIFI_DEBUGFS
1394 /* create and remove of files */
1395 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1396 if (!debugfs_create_file(#name, mode, parent, trans, \
1397 &iwl_dbgfs_##name##_ops)) \
1398 goto err; \
1399 } while (0)
1400
1401 /* file operation */
1402 #define DEBUGFS_READ_FILE_OPS(name) \
1403 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1404 .read = iwl_dbgfs_##name##_read, \
1405 .open = simple_open, \
1406 .llseek = generic_file_llseek, \
1407 };
1408
1409 #define DEBUGFS_WRITE_FILE_OPS(name) \
1410 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1411 .write = iwl_dbgfs_##name##_write, \
1412 .open = simple_open, \
1413 .llseek = generic_file_llseek, \
1414 };
1415
1416 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1417 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1418 .write = iwl_dbgfs_##name##_write, \
1419 .read = iwl_dbgfs_##name##_read, \
1420 .open = simple_open, \
1421 .llseek = generic_file_llseek, \
1422 };
1423
1424 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1425 char __user *user_buf,
1426 size_t count, loff_t *ppos)
1427 {
1428 struct iwl_trans *trans = file->private_data;
1429 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1430 struct iwl_txq *txq;
1431 struct iwl_queue *q;
1432 char *buf;
1433 int pos = 0;
1434 int cnt;
1435 int ret;
1436 size_t bufsz;
1437
1438 bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1439
1440 if (!trans_pcie->txq)
1441 return -EAGAIN;
1442
1443 buf = kzalloc(bufsz, GFP_KERNEL);
1444 if (!buf)
1445 return -ENOMEM;
1446
1447 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1448 txq = &trans_pcie->txq[cnt];
1449 q = &txq->q;
1450 pos += scnprintf(buf + pos, bufsz - pos,
1451 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1452 cnt, q->read_ptr, q->write_ptr,
1453 !!test_bit(cnt, trans_pcie->queue_used),
1454 !!test_bit(cnt, trans_pcie->queue_stopped));
1455 }
1456 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1457 kfree(buf);
1458 return ret;
1459 }
1460
1461 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1462 char __user *user_buf,
1463 size_t count, loff_t *ppos)
1464 {
1465 struct iwl_trans *trans = file->private_data;
1466 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1467 struct iwl_rxq *rxq = &trans_pcie->rxq;
1468 char buf[256];
1469 int pos = 0;
1470 const size_t bufsz = sizeof(buf);
1471
1472 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1473 rxq->read);
1474 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1475 rxq->write);
1476 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1477 rxq->free_count);
1478 if (rxq->rb_stts) {
1479 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1480 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1481 } else {
1482 pos += scnprintf(buf + pos, bufsz - pos,
1483 "closed_rb_num: Not Allocated\n");
1484 }
1485 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1486 }
1487
1488 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1489 char __user *user_buf,
1490 size_t count, loff_t *ppos)
1491 {
1492 struct iwl_trans *trans = file->private_data;
1493 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1494 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1495
1496 int pos = 0;
1497 char *buf;
1498 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1499 ssize_t ret;
1500
1501 buf = kzalloc(bufsz, GFP_KERNEL);
1502 if (!buf)
1503 return -ENOMEM;
1504
1505 pos += scnprintf(buf + pos, bufsz - pos,
1506 "Interrupt Statistics Report:\n");
1507
1508 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1509 isr_stats->hw);
1510 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1511 isr_stats->sw);
1512 if (isr_stats->sw || isr_stats->hw) {
1513 pos += scnprintf(buf + pos, bufsz - pos,
1514 "\tLast Restarting Code: 0x%X\n",
1515 isr_stats->err_code);
1516 }
1517 #ifdef CONFIG_IWLWIFI_DEBUG
1518 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1519 isr_stats->sch);
1520 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1521 isr_stats->alive);
1522 #endif
1523 pos += scnprintf(buf + pos, bufsz - pos,
1524 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1525
1526 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1527 isr_stats->ctkill);
1528
1529 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1530 isr_stats->wakeup);
1531
1532 pos += scnprintf(buf + pos, bufsz - pos,
1533 "Rx command responses:\t\t %u\n", isr_stats->rx);
1534
1535 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1536 isr_stats->tx);
1537
1538 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1539 isr_stats->unhandled);
1540
1541 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1542 kfree(buf);
1543 return ret;
1544 }
1545
1546 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1547 const char __user *user_buf,
1548 size_t count, loff_t *ppos)
1549 {
1550 struct iwl_trans *trans = file->private_data;
1551 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1552 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1553
1554 char buf[8];
1555 int buf_size;
1556 u32 reset_flag;
1557
1558 memset(buf, 0, sizeof(buf));
1559 buf_size = min(count, sizeof(buf) - 1);
1560 if (copy_from_user(buf, user_buf, buf_size))
1561 return -EFAULT;
1562 if (sscanf(buf, "%x", &reset_flag) != 1)
1563 return -EFAULT;
1564 if (reset_flag == 0)
1565 memset(isr_stats, 0, sizeof(*isr_stats));
1566
1567 return count;
1568 }
1569
1570 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1571 const char __user *user_buf,
1572 size_t count, loff_t *ppos)
1573 {
1574 struct iwl_trans *trans = file->private_data;
1575 char buf[8];
1576 int buf_size;
1577 int csr;
1578
1579 memset(buf, 0, sizeof(buf));
1580 buf_size = min(count, sizeof(buf) - 1);
1581 if (copy_from_user(buf, user_buf, buf_size))
1582 return -EFAULT;
1583 if (sscanf(buf, "%d", &csr) != 1)
1584 return -EFAULT;
1585
1586 iwl_pcie_dump_csr(trans);
1587
1588 return count;
1589 }
1590
1591 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1592 char __user *user_buf,
1593 size_t count, loff_t *ppos)
1594 {
1595 struct iwl_trans *trans = file->private_data;
1596 char *buf = NULL;
1597 ssize_t ret;
1598
1599 ret = iwl_dump_fh(trans, &buf);
1600 if (ret < 0)
1601 return ret;
1602 if (!buf)
1603 return -EINVAL;
1604 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
1605 kfree(buf);
1606 return ret;
1607 }
1608
1609 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1610 DEBUGFS_READ_FILE_OPS(fh_reg);
1611 DEBUGFS_READ_FILE_OPS(rx_queue);
1612 DEBUGFS_READ_FILE_OPS(tx_queue);
1613 DEBUGFS_WRITE_FILE_OPS(csr);
1614
1615 /*
1616 * Create the debugfs files and directories
1617 *
1618 */
1619 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1620 struct dentry *dir)
1621 {
1622 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1623 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1624 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1625 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1626 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1627 return 0;
1628
1629 err:
1630 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1631 return -ENOMEM;
1632 }
1633 #else
1634 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1635 struct dentry *dir)
1636 {
1637 return 0;
1638 }
1639 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1640
1641 static const struct iwl_trans_ops trans_ops_pcie = {
1642 .start_hw = iwl_trans_pcie_start_hw,
1643 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
1644 .fw_alive = iwl_trans_pcie_fw_alive,
1645 .start_fw = iwl_trans_pcie_start_fw,
1646 .stop_device = iwl_trans_pcie_stop_device,
1647
1648 .d3_suspend = iwl_trans_pcie_d3_suspend,
1649 .d3_resume = iwl_trans_pcie_d3_resume,
1650
1651 .send_cmd = iwl_trans_pcie_send_hcmd,
1652
1653 .tx = iwl_trans_pcie_tx,
1654 .reclaim = iwl_trans_pcie_reclaim,
1655
1656 .txq_disable = iwl_trans_pcie_txq_disable,
1657 .txq_enable = iwl_trans_pcie_txq_enable,
1658
1659 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1660
1661 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
1662
1663 .write8 = iwl_trans_pcie_write8,
1664 .write32 = iwl_trans_pcie_write32,
1665 .read32 = iwl_trans_pcie_read32,
1666 .read_prph = iwl_trans_pcie_read_prph,
1667 .write_prph = iwl_trans_pcie_write_prph,
1668 .read_mem = iwl_trans_pcie_read_mem,
1669 .write_mem = iwl_trans_pcie_write_mem,
1670 .configure = iwl_trans_pcie_configure,
1671 .set_pmi = iwl_trans_pcie_set_pmi,
1672 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
1673 .release_nic_access = iwl_trans_pcie_release_nic_access,
1674 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
1675 };
1676
1677 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
1678 const struct pci_device_id *ent,
1679 const struct iwl_cfg *cfg)
1680 {
1681 struct iwl_trans_pcie *trans_pcie;
1682 struct iwl_trans *trans;
1683 u16 pci_cmd;
1684 int err;
1685
1686 trans = kzalloc(sizeof(struct iwl_trans) +
1687 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
1688 if (!trans) {
1689 err = -ENOMEM;
1690 goto out;
1691 }
1692
1693 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1694
1695 trans->ops = &trans_ops_pcie;
1696 trans->cfg = cfg;
1697 trans_lockdep_init(trans);
1698 trans_pcie->trans = trans;
1699 spin_lock_init(&trans_pcie->irq_lock);
1700 spin_lock_init(&trans_pcie->reg_lock);
1701 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
1702
1703 err = pci_enable_device(pdev);
1704 if (err)
1705 goto out_no_pci;
1706
1707 if (!cfg->base_params->pcie_l1_allowed) {
1708 /*
1709 * W/A - seems to solve weird behavior. We need to remove this
1710 * if we don't want to stay in L1 all the time. This wastes a
1711 * lot of power.
1712 */
1713 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
1714 PCIE_LINK_STATE_L1 |
1715 PCIE_LINK_STATE_CLKPM);
1716 }
1717
1718 pci_set_master(pdev);
1719
1720 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
1721 if (!err)
1722 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
1723 if (err) {
1724 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1725 if (!err)
1726 err = pci_set_consistent_dma_mask(pdev,
1727 DMA_BIT_MASK(32));
1728 /* both attempts failed: */
1729 if (err) {
1730 dev_err(&pdev->dev, "No suitable DMA available\n");
1731 goto out_pci_disable_device;
1732 }
1733 }
1734
1735 err = pci_request_regions(pdev, DRV_NAME);
1736 if (err) {
1737 dev_err(&pdev->dev, "pci_request_regions failed\n");
1738 goto out_pci_disable_device;
1739 }
1740
1741 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
1742 if (!trans_pcie->hw_base) {
1743 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
1744 err = -ENODEV;
1745 goto out_pci_release_regions;
1746 }
1747
1748 /* We disable the RETRY_TIMEOUT register (0x41) to keep
1749 * PCI Tx retries from interfering with C3 CPU state */
1750 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
1751
1752 trans->dev = &pdev->dev;
1753 trans_pcie->pci_dev = pdev;
1754 iwl_disable_interrupts(trans);
1755
1756 err = pci_enable_msi(pdev);
1757 if (err) {
1758 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
1759 /* enable rfkill interrupt: hw bug w/a */
1760 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1761 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1762 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1763 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1764 }
1765 }
1766
1767 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
1768 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
1769 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
1770 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
1771
1772 /* Initialize the wait queue for commands */
1773 init_waitqueue_head(&trans_pcie->wait_command_queue);
1774
1775 snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
1776 "iwl_cmd_pool:%s", dev_name(trans->dev));
1777
1778 trans->dev_cmd_headroom = 0;
1779 trans->dev_cmd_pool =
1780 kmem_cache_create(trans->dev_cmd_pool_name,
1781 sizeof(struct iwl_device_cmd)
1782 + trans->dev_cmd_headroom,
1783 sizeof(void *),
1784 SLAB_HWCACHE_ALIGN,
1785 NULL);
1786
1787 if (!trans->dev_cmd_pool) {
1788 err = -ENOMEM;
1789 goto out_pci_disable_msi;
1790 }
1791
1792 if (iwl_pcie_alloc_ict(trans))
1793 goto out_free_cmd_pool;
1794
1795 err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
1796 iwl_pcie_irq_handler,
1797 IRQF_SHARED, DRV_NAME, trans);
1798 if (err) {
1799 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
1800 goto out_free_ict;
1801 }
1802
1803 trans_pcie->inta_mask = CSR_INI_SET_MASK;
1804
1805 return trans;
1806
1807 out_free_ict:
1808 iwl_pcie_free_ict(trans);
1809 out_free_cmd_pool:
1810 kmem_cache_destroy(trans->dev_cmd_pool);
1811 out_pci_disable_msi:
1812 pci_disable_msi(pdev);
1813 out_pci_release_regions:
1814 pci_release_regions(pdev);
1815 out_pci_disable_device:
1816 pci_disable_device(pdev);
1817 out_no_pci:
1818 kfree(trans);
1819 out:
1820 return ERR_PTR(err);
1821 }
Linux kernel - Deliverables
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