1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *****************************************************************************/
63 #include <linux/pci.h>
64 #include <linux/pci-aspm.h>
65 #include <linux/interrupt.h>
66 #include <linux/debugfs.h>
67 #include <linux/sched.h>
68 #include <linux/bitops.h>
69 #include <linux/gfp.h>
72 #include "iwl-trans.h"
75 #include "iwl-agn-hw.h"
77 /* FIXME: need to abstract out TX command (once we know what it looks like) */
78 #include "dvm/commands.h"
80 #define SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie) \
81 (((1<<trans->cfg->base_params->num_of_queues) - 1) &\
82 (~(1<<(trans_pcie)->cmd_queue)))
84 static int iwl_trans_rx_alloc(struct iwl_trans
*trans
)
86 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
87 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
88 struct device
*dev
= trans
->dev
;
90 memset(&trans_pcie
->rxq
, 0, sizeof(trans_pcie
->rxq
));
92 spin_lock_init(&rxq
->lock
);
94 if (WARN_ON(rxq
->bd
|| rxq
->rb_stts
))
97 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
98 rxq
->bd
= dma_zalloc_coherent(dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
99 &rxq
->bd_dma
, GFP_KERNEL
);
103 /*Allocate the driver's pointer to receive buffer status */
104 rxq
->rb_stts
= dma_zalloc_coherent(dev
, sizeof(*rxq
->rb_stts
),
105 &rxq
->rb_stts_dma
, GFP_KERNEL
);
112 dma_free_coherent(dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
113 rxq
->bd
, rxq
->bd_dma
);
114 memset(&rxq
->bd_dma
, 0, sizeof(rxq
->bd_dma
));
120 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans
*trans
)
122 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
123 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
126 /* Fill the rx_used queue with _all_ of the Rx buffers */
127 for (i
= 0; i
< RX_FREE_BUFFERS
+ RX_QUEUE_SIZE
; i
++) {
128 /* In the reset function, these buffers may have been allocated
129 * to an SKB, so we need to unmap and free potential storage */
130 if (rxq
->pool
[i
].page
!= NULL
) {
131 dma_unmap_page(trans
->dev
, rxq
->pool
[i
].page_dma
,
132 PAGE_SIZE
<< trans_pcie
->rx_page_order
,
134 __free_pages(rxq
->pool
[i
].page
,
135 trans_pcie
->rx_page_order
);
136 rxq
->pool
[i
].page
= NULL
;
138 list_add_tail(&rxq
->pool
[i
].list
, &rxq
->rx_used
);
142 static void iwl_trans_rx_hw_init(struct iwl_trans
*trans
,
143 struct iwl_rx_queue
*rxq
)
145 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
147 const u32 rfdnlog
= RX_QUEUE_SIZE_LOG
; /* 256 RBDs */
148 u32 rb_timeout
= RX_RB_TIMEOUT
; /* FIXME: RX_RB_TIMEOUT for all devices? */
150 if (trans_pcie
->rx_buf_size_8k
)
151 rb_size
= FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K
;
153 rb_size
= FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K
;
156 iwl_write_direct32(trans
, FH_MEM_RCSR_CHNL0_CONFIG_REG
, 0);
158 /* Reset driver's Rx queue write index */
159 iwl_write_direct32(trans
, FH_RSCSR_CHNL0_RBDCB_WPTR_REG
, 0);
161 /* Tell device where to find RBD circular buffer in DRAM */
162 iwl_write_direct32(trans
, FH_RSCSR_CHNL0_RBDCB_BASE_REG
,
163 (u32
)(rxq
->bd_dma
>> 8));
165 /* Tell device where in DRAM to update its Rx status */
166 iwl_write_direct32(trans
, FH_RSCSR_CHNL0_STTS_WPTR_REG
,
167 rxq
->rb_stts_dma
>> 4);
170 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
171 * the credit mechanism in 5000 HW RX FIFO
172 * Direct rx interrupts to hosts
173 * Rx buffer size 4 or 8k
177 iwl_write_direct32(trans
, FH_MEM_RCSR_CHNL0_CONFIG_REG
,
178 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL
|
179 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY
|
180 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL
|
182 (rb_timeout
<< FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS
)|
183 (rfdnlog
<< FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS
));
185 /* Set interrupt coalescing timer to default (2048 usecs) */
186 iwl_write8(trans
, CSR_INT_COALESCING
, IWL_HOST_INT_TIMEOUT_DEF
);
189 static int iwl_rx_init(struct iwl_trans
*trans
)
191 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
192 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
198 err
= iwl_trans_rx_alloc(trans
);
203 spin_lock_irqsave(&rxq
->lock
, flags
);
204 INIT_LIST_HEAD(&rxq
->rx_free
);
205 INIT_LIST_HEAD(&rxq
->rx_used
);
207 iwl_trans_rxq_free_rx_bufs(trans
);
209 for (i
= 0; i
< RX_QUEUE_SIZE
; i
++)
210 rxq
->queue
[i
] = NULL
;
212 /* Set us so that we have processed and used all buffers, but have
213 * not restocked the Rx queue with fresh buffers */
214 rxq
->read
= rxq
->write
= 0;
215 rxq
->write_actual
= 0;
217 spin_unlock_irqrestore(&rxq
->lock
, flags
);
219 iwl_rx_replenish(trans
);
221 iwl_trans_rx_hw_init(trans
, rxq
);
223 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
224 rxq
->need_update
= 1;
225 iwl_rx_queue_update_write_ptr(trans
, rxq
);
226 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
231 static void iwl_trans_pcie_rx_free(struct iwl_trans
*trans
)
233 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
234 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
237 /*if rxq->bd is NULL, it means that nothing has been allocated,
240 IWL_DEBUG_INFO(trans
, "Free NULL rx context\n");
244 spin_lock_irqsave(&rxq
->lock
, flags
);
245 iwl_trans_rxq_free_rx_bufs(trans
);
246 spin_unlock_irqrestore(&rxq
->lock
, flags
);
248 dma_free_coherent(trans
->dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
249 rxq
->bd
, rxq
->bd_dma
);
250 memset(&rxq
->bd_dma
, 0, sizeof(rxq
->bd_dma
));
254 dma_free_coherent(trans
->dev
,
255 sizeof(struct iwl_rb_status
),
256 rxq
->rb_stts
, rxq
->rb_stts_dma
);
258 IWL_DEBUG_INFO(trans
, "Free rxq->rb_stts which is NULL\n");
259 memset(&rxq
->rb_stts_dma
, 0, sizeof(rxq
->rb_stts_dma
));
263 static int iwl_trans_rx_stop(struct iwl_trans
*trans
)
267 iwl_write_direct32(trans
, FH_MEM_RCSR_CHNL0_CONFIG_REG
, 0);
268 return iwl_poll_direct_bit(trans
, FH_MEM_RSSR_RX_STATUS_REG
,
269 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE
, 1000);
272 static int iwlagn_alloc_dma_ptr(struct iwl_trans
*trans
,
273 struct iwl_dma_ptr
*ptr
, size_t size
)
275 if (WARN_ON(ptr
->addr
))
278 ptr
->addr
= dma_alloc_coherent(trans
->dev
, size
,
279 &ptr
->dma
, GFP_KERNEL
);
286 static void iwlagn_free_dma_ptr(struct iwl_trans
*trans
,
287 struct iwl_dma_ptr
*ptr
)
289 if (unlikely(!ptr
->addr
))
292 dma_free_coherent(trans
->dev
, ptr
->size
, ptr
->addr
, ptr
->dma
);
293 memset(ptr
, 0, sizeof(*ptr
));
296 static void iwl_trans_pcie_queue_stuck_timer(unsigned long data
)
298 struct iwl_tx_queue
*txq
= (void *)data
;
299 struct iwl_queue
*q
= &txq
->q
;
300 struct iwl_trans_pcie
*trans_pcie
= txq
->trans_pcie
;
301 struct iwl_trans
*trans
= iwl_trans_pcie_get_trans(trans_pcie
);
302 u32 scd_sram_addr
= trans_pcie
->scd_base_addr
+
303 SCD_TX_STTS_QUEUE_OFFSET(txq
->q
.id
);
307 spin_lock(&txq
->lock
);
308 /* check if triggered erroneously */
309 if (txq
->q
.read_ptr
== txq
->q
.write_ptr
) {
310 spin_unlock(&txq
->lock
);
313 spin_unlock(&txq
->lock
);
315 IWL_ERR(trans
, "Queue %d stuck for %u ms.\n", txq
->q
.id
,
316 jiffies_to_msecs(trans_pcie
->wd_timeout
));
317 IWL_ERR(trans
, "Current SW read_ptr %d write_ptr %d\n",
318 txq
->q
.read_ptr
, txq
->q
.write_ptr
);
320 iwl_read_targ_mem_bytes(trans
, scd_sram_addr
, buf
, sizeof(buf
));
322 iwl_print_hex_error(trans
, buf
, sizeof(buf
));
324 for (i
= 0; i
< FH_TCSR_CHNL_NUM
; i
++)
325 IWL_ERR(trans
, "FH TRBs(%d) = 0x%08x\n", i
,
326 iwl_read_direct32(trans
, FH_TX_TRB_REG(i
)));
328 for (i
= 0; i
< trans
->cfg
->base_params
->num_of_queues
; i
++) {
329 u32 status
= iwl_read_prph(trans
, SCD_QUEUE_STATUS_BITS(i
));
330 u8 fifo
= (status
>> SCD_QUEUE_STTS_REG_POS_TXF
) & 0x7;
331 bool active
= !!(status
& BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE
));
333 iwl_read_targ_mem(trans
,
334 trans_pcie
->scd_base_addr
+
335 SCD_TRANS_TBL_OFFSET_QUEUE(i
));
338 tbl_dw
= (tbl_dw
& 0xFFFF0000) >> 16;
340 tbl_dw
= tbl_dw
& 0x0000FFFF;
343 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
344 i
, active
? "" : "in", fifo
, tbl_dw
,
346 SCD_QUEUE_RDPTR(i
)) & (txq
->q
.n_bd
- 1),
347 iwl_read_prph(trans
, SCD_QUEUE_WRPTR(i
)));
350 for (i
= q
->read_ptr
; i
!= q
->write_ptr
;
351 i
= iwl_queue_inc_wrap(i
, q
->n_bd
)) {
352 struct iwl_tx_cmd
*tx_cmd
=
353 (struct iwl_tx_cmd
*)txq
->entries
[i
].cmd
->payload
;
354 IWL_ERR(trans
, "scratch %d = 0x%08x\n", i
,
355 get_unaligned_le32(&tx_cmd
->scratch
));
358 iwl_op_mode_nic_error(trans
->op_mode
);
361 static int iwl_trans_txq_alloc(struct iwl_trans
*trans
,
362 struct iwl_tx_queue
*txq
, int slots_num
,
365 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
366 size_t tfd_sz
= sizeof(struct iwl_tfd
) * TFD_QUEUE_SIZE_MAX
;
369 if (WARN_ON(txq
->entries
|| txq
->tfds
))
372 setup_timer(&txq
->stuck_timer
, iwl_trans_pcie_queue_stuck_timer
,
374 txq
->trans_pcie
= trans_pcie
;
376 txq
->q
.n_window
= slots_num
;
378 txq
->entries
= kcalloc(slots_num
,
379 sizeof(struct iwl_pcie_tx_queue_entry
),
385 if (txq_id
== trans_pcie
->cmd_queue
)
386 for (i
= 0; i
< slots_num
; i
++) {
387 txq
->entries
[i
].cmd
=
388 kmalloc(sizeof(struct iwl_device_cmd
),
390 if (!txq
->entries
[i
].cmd
)
394 /* Circular buffer of transmit frame descriptors (TFDs),
395 * shared with device */
396 txq
->tfds
= dma_alloc_coherent(trans
->dev
, tfd_sz
,
397 &txq
->q
.dma_addr
, GFP_KERNEL
);
399 IWL_ERR(trans
, "dma_alloc_coherent(%zd) failed\n", tfd_sz
);
406 if (txq
->entries
&& txq_id
== trans_pcie
->cmd_queue
)
407 for (i
= 0; i
< slots_num
; i
++)
408 kfree(txq
->entries
[i
].cmd
);
416 static int iwl_trans_txq_init(struct iwl_trans
*trans
, struct iwl_tx_queue
*txq
,
417 int slots_num
, u32 txq_id
)
421 txq
->need_update
= 0;
423 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
424 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
425 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX
& (TFD_QUEUE_SIZE_MAX
- 1));
427 /* Initialize queue's high/low-water marks, and head/tail indexes */
428 ret
= iwl_queue_init(&txq
->q
, TFD_QUEUE_SIZE_MAX
, slots_num
,
433 spin_lock_init(&txq
->lock
);
436 * Tell nic where to find circular buffer of Tx Frame Descriptors for
437 * given Tx queue, and enable the DMA channel used for that queue.
438 * Circular buffer (TFD queue in DRAM) physical base address */
439 iwl_write_direct32(trans
, FH_MEM_CBBC_QUEUE(txq_id
),
440 txq
->q
.dma_addr
>> 8);
446 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
448 void iwl_tx_queue_unmap(struct iwl_trans
*trans
, int txq_id
)
450 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
451 struct iwl_tx_queue
*txq
= &trans_pcie
->txq
[txq_id
];
452 struct iwl_queue
*q
= &txq
->q
;
453 enum dma_data_direction dma_dir
;
458 /* In the command queue, all the TBs are mapped as BIDI
459 * so unmap them as such.
461 if (txq_id
== trans_pcie
->cmd_queue
)
462 dma_dir
= DMA_BIDIRECTIONAL
;
464 dma_dir
= DMA_TO_DEVICE
;
466 spin_lock_bh(&txq
->lock
);
467 while (q
->write_ptr
!= q
->read_ptr
) {
468 iwl_txq_free_tfd(trans
, txq
, dma_dir
);
469 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
);
471 spin_unlock_bh(&txq
->lock
);
475 * iwl_tx_queue_free - Deallocate DMA queue.
476 * @txq: Transmit queue to deallocate.
478 * Empty queue by removing and destroying all BD's.
480 * 0-fill, but do not free "txq" descriptor structure.
482 static void iwl_tx_queue_free(struct iwl_trans
*trans
, int txq_id
)
484 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
485 struct iwl_tx_queue
*txq
= &trans_pcie
->txq
[txq_id
];
486 struct device
*dev
= trans
->dev
;
492 iwl_tx_queue_unmap(trans
, txq_id
);
494 /* De-alloc array of command/tx buffers */
495 if (txq_id
== trans_pcie
->cmd_queue
)
496 for (i
= 0; i
< txq
->q
.n_window
; i
++) {
497 kfree(txq
->entries
[i
].cmd
);
498 kfree(txq
->entries
[i
].copy_cmd
);
499 kfree(txq
->entries
[i
].free_buf
);
502 /* De-alloc circular buffer of TFDs */
504 dma_free_coherent(dev
, sizeof(struct iwl_tfd
) *
505 txq
->q
.n_bd
, txq
->tfds
, txq
->q
.dma_addr
);
506 memset(&txq
->q
.dma_addr
, 0, sizeof(txq
->q
.dma_addr
));
512 del_timer_sync(&txq
->stuck_timer
);
514 /* 0-fill queue descriptor structure */
515 memset(txq
, 0, sizeof(*txq
));
519 * iwl_trans_tx_free - Free TXQ Context
521 * Destroy all TX DMA queues and structures
523 static void iwl_trans_pcie_tx_free(struct iwl_trans
*trans
)
526 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
529 if (trans_pcie
->txq
) {
531 txq_id
< trans
->cfg
->base_params
->num_of_queues
; txq_id
++)
532 iwl_tx_queue_free(trans
, txq_id
);
535 kfree(trans_pcie
->txq
);
536 trans_pcie
->txq
= NULL
;
538 iwlagn_free_dma_ptr(trans
, &trans_pcie
->kw
);
540 iwlagn_free_dma_ptr(trans
, &trans_pcie
->scd_bc_tbls
);
544 * iwl_trans_tx_alloc - allocate TX context
545 * Allocate all Tx DMA structures and initialize them
550 static int iwl_trans_tx_alloc(struct iwl_trans
*trans
)
553 int txq_id
, slots_num
;
554 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
556 u16 scd_bc_tbls_size
= trans
->cfg
->base_params
->num_of_queues
*
557 sizeof(struct iwlagn_scd_bc_tbl
);
559 /*It is not allowed to alloc twice, so warn when this happens.
560 * We cannot rely on the previous allocation, so free and fail */
561 if (WARN_ON(trans_pcie
->txq
)) {
566 ret
= iwlagn_alloc_dma_ptr(trans
, &trans_pcie
->scd_bc_tbls
,
569 IWL_ERR(trans
, "Scheduler BC Table allocation failed\n");
573 /* Alloc keep-warm buffer */
574 ret
= iwlagn_alloc_dma_ptr(trans
, &trans_pcie
->kw
, IWL_KW_SIZE
);
576 IWL_ERR(trans
, "Keep Warm allocation failed\n");
580 trans_pcie
->txq
= kcalloc(trans
->cfg
->base_params
->num_of_queues
,
581 sizeof(struct iwl_tx_queue
), GFP_KERNEL
);
582 if (!trans_pcie
->txq
) {
583 IWL_ERR(trans
, "Not enough memory for txq\n");
588 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
589 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
591 slots_num
= (txq_id
== trans_pcie
->cmd_queue
) ?
592 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
593 ret
= iwl_trans_txq_alloc(trans
, &trans_pcie
->txq
[txq_id
],
596 IWL_ERR(trans
, "Tx %d queue alloc failed\n", txq_id
);
604 iwl_trans_pcie_tx_free(trans
);
608 static int iwl_tx_init(struct iwl_trans
*trans
)
610 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
612 int txq_id
, slots_num
;
616 if (!trans_pcie
->txq
) {
617 ret
= iwl_trans_tx_alloc(trans
);
623 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
625 /* Turn off all Tx DMA fifos */
626 iwl_write_prph(trans
, SCD_TXFACT
, 0);
628 /* Tell NIC where to find the "keep warm" buffer */
629 iwl_write_direct32(trans
, FH_KW_MEM_ADDR_REG
,
630 trans_pcie
->kw
.dma
>> 4);
632 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
634 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
635 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
637 slots_num
= (txq_id
== trans_pcie
->cmd_queue
) ?
638 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
639 ret
= iwl_trans_txq_init(trans
, &trans_pcie
->txq
[txq_id
],
642 IWL_ERR(trans
, "Tx %d queue init failed\n", txq_id
);
649 /*Upon error, free only if we allocated something */
651 iwl_trans_pcie_tx_free(trans
);
655 static void iwl_set_pwr_vmain(struct iwl_trans
*trans
)
658 * (for documentation purposes)
659 * to set power to V_AUX, do:
661 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
662 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
663 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
664 ~APMG_PS_CTRL_MSK_PWR_SRC);
667 iwl_set_bits_mask_prph(trans
, APMG_PS_CTRL_REG
,
668 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN
,
669 ~APMG_PS_CTRL_MSK_PWR_SRC
);
673 #define PCI_CFG_RETRY_TIMEOUT 0x041
674 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
675 #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
677 static u16
iwl_pciexp_link_ctrl(struct iwl_trans
*trans
)
679 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
682 pcie_capability_read_word(trans_pcie
->pci_dev
, PCI_EXP_LNKCTL
,
687 static void iwl_apm_config(struct iwl_trans
*trans
)
690 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
691 * Check if BIOS (or OS) enabled L1-ASPM on this device.
692 * If so (likely), disable L0S, so device moves directly L0->L1;
693 * costs negligible amount of power savings.
694 * If not (unlikely), enable L0S, so there is at least some
695 * power savings, even without L1.
697 u16 lctl
= iwl_pciexp_link_ctrl(trans
);
699 if ((lctl
& PCI_CFG_LINK_CTRL_VAL_L1_EN
) ==
700 PCI_CFG_LINK_CTRL_VAL_L1_EN
) {
701 /* L1-ASPM enabled; disable(!) L0S */
702 iwl_set_bit(trans
, CSR_GIO_REG
, CSR_GIO_REG_VAL_L0S_ENABLED
);
703 dev_printk(KERN_INFO
, trans
->dev
,
704 "L1 Enabled; Disabling L0S\n");
706 /* L1-ASPM disabled; enable(!) L0S */
707 iwl_clear_bit(trans
, CSR_GIO_REG
, CSR_GIO_REG_VAL_L0S_ENABLED
);
708 dev_printk(KERN_INFO
, trans
->dev
,
709 "L1 Disabled; Enabling L0S\n");
711 trans
->pm_support
= !(lctl
& PCI_CFG_LINK_CTRL_VAL_L0S_EN
);
715 * Start up NIC's basic functionality after it has been reset
716 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
717 * NOTE: This does not load uCode nor start the embedded processor
719 static int iwl_apm_init(struct iwl_trans
*trans
)
721 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
723 IWL_DEBUG_INFO(trans
, "Init card's basic functions\n");
726 * Use "set_bit" below rather than "write", to preserve any hardware
727 * bits already set by default after reset.
730 /* Disable L0S exit timer (platform NMI Work/Around) */
731 iwl_set_bit(trans
, CSR_GIO_CHICKEN_BITS
,
732 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER
);
735 * Disable L0s without affecting L1;
736 * don't wait for ICH L0s (ICH bug W/A)
738 iwl_set_bit(trans
, CSR_GIO_CHICKEN_BITS
,
739 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX
);
741 /* Set FH wait threshold to maximum (HW error during stress W/A) */
742 iwl_set_bit(trans
, CSR_DBG_HPET_MEM_REG
, CSR_DBG_HPET_MEM_REG_VAL
);
745 * Enable HAP INTA (interrupt from management bus) to
746 * wake device's PCI Express link L1a -> L0s
748 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
749 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A
);
751 iwl_apm_config(trans
);
753 /* Configure analog phase-lock-loop before activating to D0A */
754 if (trans
->cfg
->base_params
->pll_cfg_val
)
755 iwl_set_bit(trans
, CSR_ANA_PLL_CFG
,
756 trans
->cfg
->base_params
->pll_cfg_val
);
759 * Set "initialization complete" bit to move adapter from
760 * D0U* --> D0A* (powered-up active) state.
762 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
765 * Wait for clock stabilization; once stabilized, access to
766 * device-internal resources is supported, e.g. iwl_write_prph()
767 * and accesses to uCode SRAM.
769 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
770 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
771 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
, 25000);
773 IWL_DEBUG_INFO(trans
, "Failed to init the card\n");
778 * Enable DMA clock and wait for it to stabilize.
780 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
781 * do not disable clocks. This preserves any hardware bits already
782 * set by default in "CLK_CTRL_REG" after reset.
784 iwl_write_prph(trans
, APMG_CLK_EN_REG
, APMG_CLK_VAL_DMA_CLK_RQT
);
787 /* Disable L1-Active */
788 iwl_set_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
789 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
791 set_bit(STATUS_DEVICE_ENABLED
, &trans_pcie
->status
);
797 static int iwl_apm_stop_master(struct iwl_trans
*trans
)
801 /* stop device's busmaster DMA activity */
802 iwl_set_bit(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_STOP_MASTER
);
804 ret
= iwl_poll_bit(trans
, CSR_RESET
,
805 CSR_RESET_REG_FLAG_MASTER_DISABLED
,
806 CSR_RESET_REG_FLAG_MASTER_DISABLED
, 100);
808 IWL_WARN(trans
, "Master Disable Timed Out, 100 usec\n");
810 IWL_DEBUG_INFO(trans
, "stop master\n");
815 static void iwl_apm_stop(struct iwl_trans
*trans
)
817 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
818 IWL_DEBUG_INFO(trans
, "Stop card, put in low power state\n");
820 clear_bit(STATUS_DEVICE_ENABLED
, &trans_pcie
->status
);
822 /* Stop device's DMA activity */
823 iwl_apm_stop_master(trans
);
825 /* Reset the entire device */
826 iwl_set_bit(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
831 * Clear "initialization complete" bit to move adapter from
832 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
834 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
835 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
838 static int iwl_nic_init(struct iwl_trans
*trans
)
840 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
844 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
847 /* Set interrupt coalescing calibration timer to default (512 usecs) */
848 iwl_write8(trans
, CSR_INT_COALESCING
, IWL_HOST_INT_CALIB_TIMEOUT_DEF
);
850 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
852 iwl_set_pwr_vmain(trans
);
854 iwl_op_mode_nic_config(trans
->op_mode
);
856 /* Allocate the RX queue, or reset if it is already allocated */
859 /* Allocate or reset and init all Tx and Command queues */
860 if (iwl_tx_init(trans
))
863 if (trans
->cfg
->base_params
->shadow_reg_enable
) {
864 /* enable shadow regs in HW */
865 iwl_set_bit(trans
, CSR_MAC_SHADOW_REG_CTRL
, 0x800FFFFF);
866 IWL_DEBUG_INFO(trans
, "Enabling shadow registers in device\n");
872 #define HW_READY_TIMEOUT (50)
874 /* Note: returns poll_bit return value, which is >= 0 if success */
875 static int iwl_set_hw_ready(struct iwl_trans
*trans
)
879 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
880 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
);
882 /* See if we got it */
883 ret
= iwl_poll_bit(trans
, CSR_HW_IF_CONFIG_REG
,
884 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
885 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
888 IWL_DEBUG_INFO(trans
, "hardware%s ready\n", ret
< 0 ? " not" : "");
892 /* Note: returns standard 0/-ERROR code */
893 static int iwl_prepare_card_hw(struct iwl_trans
*trans
)
898 IWL_DEBUG_INFO(trans
, "iwl_trans_prepare_card_hw enter\n");
900 ret
= iwl_set_hw_ready(trans
);
901 /* If the card is ready, exit 0 */
905 /* If HW is not ready, prepare the conditions to check again */
906 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
907 CSR_HW_IF_CONFIG_REG_PREPARE
);
910 ret
= iwl_set_hw_ready(trans
);
914 usleep_range(200, 1000);
916 } while (t
< 150000);
924 static int iwl_load_firmware_chunk(struct iwl_trans
*trans
, u32 dst_addr
,
925 dma_addr_t phy_addr
, u32 byte_cnt
)
927 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
930 trans_pcie
->ucode_write_complete
= false;
932 iwl_write_direct32(trans
,
933 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
934 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE
);
936 iwl_write_direct32(trans
,
937 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL
),
940 iwl_write_direct32(trans
,
941 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL
),
942 phy_addr
& FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK
);
944 iwl_write_direct32(trans
,
945 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL
),
946 (iwl_get_dma_hi_addr(phy_addr
)
947 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT
) | byte_cnt
);
949 iwl_write_direct32(trans
,
950 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL
),
951 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM
|
952 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX
|
953 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID
);
955 iwl_write_direct32(trans
,
956 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
957 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
958 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE
|
959 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD
);
961 ret
= wait_event_timeout(trans_pcie
->ucode_write_waitq
,
962 trans_pcie
->ucode_write_complete
, 5 * HZ
);
964 IWL_ERR(trans
, "Failed to load firmware chunk!\n");
971 static int iwl_load_section(struct iwl_trans
*trans
, u8 section_num
,
972 const struct fw_desc
*section
)
979 IWL_DEBUG_FW(trans
, "[%d] uCode section being loaded...\n",
982 v_addr
= dma_alloc_coherent(trans
->dev
, PAGE_SIZE
, &p_addr
, GFP_KERNEL
);
986 for (offset
= 0; offset
< section
->len
; offset
+= PAGE_SIZE
) {
989 copy_size
= min_t(u32
, PAGE_SIZE
, section
->len
- offset
);
991 memcpy(v_addr
, (u8
*)section
->data
+ offset
, copy_size
);
992 ret
= iwl_load_firmware_chunk(trans
, section
->offset
+ offset
,
996 "Could not load the [%d] uCode section\n",
1002 dma_free_coherent(trans
->dev
, PAGE_SIZE
, v_addr
, p_addr
);
1006 static int iwl_load_given_ucode(struct iwl_trans
*trans
,
1007 const struct fw_img
*image
)
1011 for (i
= 0; i
< IWL_UCODE_SECTION_MAX
; i
++) {
1012 if (!image
->sec
[i
].data
)
1015 ret
= iwl_load_section(trans
, i
, &image
->sec
[i
]);
1020 /* Remove all resets to allow NIC to operate */
1021 iwl_write32(trans
, CSR_RESET
, 0);
1026 static int iwl_trans_pcie_start_fw(struct iwl_trans
*trans
,
1027 const struct fw_img
*fw
)
1032 /* This may fail if AMT took ownership of the device */
1033 if (iwl_prepare_card_hw(trans
)) {
1034 IWL_WARN(trans
, "Exit HW not ready\n");
1038 iwl_enable_rfkill_int(trans
);
1040 /* If platform's RF_KILL switch is NOT set to KILL */
1041 hw_rfkill
= iwl_is_rfkill_set(trans
);
1042 iwl_op_mode_hw_rf_kill(trans
->op_mode
, hw_rfkill
);
1046 iwl_write32(trans
, CSR_INT
, 0xFFFFFFFF);
1048 ret
= iwl_nic_init(trans
);
1050 IWL_ERR(trans
, "Unable to init nic\n");
1054 /* make sure rfkill handshake bits are cleared */
1055 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
1056 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
,
1057 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED
);
1059 /* clear (again), then enable host interrupts */
1060 iwl_write32(trans
, CSR_INT
, 0xFFFFFFFF);
1061 iwl_enable_interrupts(trans
);
1063 /* really make sure rfkill handshake bits are cleared */
1064 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
1065 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
1067 /* Load the given image to the HW */
1068 return iwl_load_given_ucode(trans
, fw
);
1072 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1074 static void iwl_trans_txq_set_sched(struct iwl_trans
*trans
, u32 mask
)
1076 struct iwl_trans_pcie __maybe_unused
*trans_pcie
=
1077 IWL_TRANS_GET_PCIE_TRANS(trans
);
1079 iwl_write_prph(trans
, SCD_TXFACT
, mask
);
1082 static void iwl_tx_start(struct iwl_trans
*trans
)
1084 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1089 /* make sure all queue are not stopped/used */
1090 memset(trans_pcie
->queue_stopped
, 0, sizeof(trans_pcie
->queue_stopped
));
1091 memset(trans_pcie
->queue_used
, 0, sizeof(trans_pcie
->queue_used
));
1093 trans_pcie
->scd_base_addr
=
1094 iwl_read_prph(trans
, SCD_SRAM_BASE_ADDR
);
1095 a
= trans_pcie
->scd_base_addr
+ SCD_CONTEXT_MEM_LOWER_BOUND
;
1096 /* reset conext data memory */
1097 for (; a
< trans_pcie
->scd_base_addr
+ SCD_CONTEXT_MEM_UPPER_BOUND
;
1099 iwl_write_targ_mem(trans
, a
, 0);
1100 /* reset tx status memory */
1101 for (; a
< trans_pcie
->scd_base_addr
+ SCD_TX_STTS_MEM_UPPER_BOUND
;
1103 iwl_write_targ_mem(trans
, a
, 0);
1104 for (; a
< trans_pcie
->scd_base_addr
+
1105 SCD_TRANS_TBL_OFFSET_QUEUE(
1106 trans
->cfg
->base_params
->num_of_queues
);
1108 iwl_write_targ_mem(trans
, a
, 0);
1110 iwl_write_prph(trans
, SCD_DRAM_BASE_ADDR
,
1111 trans_pcie
->scd_bc_tbls
.dma
>> 10);
1113 /* The chain extension of the SCD doesn't work well. This feature is
1114 * enabled by default by the HW, so we need to disable it manually.
1116 iwl_write_prph(trans
, SCD_CHAINEXT_EN
, 0);
1118 iwl_trans_ac_txq_enable(trans
, trans_pcie
->cmd_queue
,
1119 trans_pcie
->cmd_fifo
);
1121 /* Activate all Tx DMA/FIFO channels */
1122 iwl_trans_txq_set_sched(trans
, IWL_MASK(0, 7));
1124 /* Enable DMA channel */
1125 for (chan
= 0; chan
< FH_TCSR_CHNL_NUM
; chan
++)
1126 iwl_write_direct32(trans
, FH_TCSR_CHNL_TX_CONFIG_REG(chan
),
1127 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
1128 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE
);
1130 /* Update FH chicken bits */
1131 reg_val
= iwl_read_direct32(trans
, FH_TX_CHICKEN_BITS_REG
);
1132 iwl_write_direct32(trans
, FH_TX_CHICKEN_BITS_REG
,
1133 reg_val
| FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN
);
1135 /* Enable L1-Active */
1136 iwl_clear_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
1137 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
1140 static void iwl_trans_pcie_fw_alive(struct iwl_trans
*trans
)
1142 iwl_reset_ict(trans
);
1143 iwl_tx_start(trans
);
1147 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1149 static int iwl_trans_tx_stop(struct iwl_trans
*trans
)
1151 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1152 int ch
, txq_id
, ret
;
1153 unsigned long flags
;
1155 /* Turn off all Tx DMA fifos */
1156 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
1158 iwl_trans_txq_set_sched(trans
, 0);
1160 /* Stop each Tx DMA channel, and wait for it to be idle */
1161 for (ch
= 0; ch
< FH_TCSR_CHNL_NUM
; ch
++) {
1162 iwl_write_direct32(trans
,
1163 FH_TCSR_CHNL_TX_CONFIG_REG(ch
), 0x0);
1164 ret
= iwl_poll_direct_bit(trans
, FH_TSSR_TX_STATUS_REG
,
1165 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch
), 1000);
1168 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
1170 iwl_read_direct32(trans
,
1171 FH_TSSR_TX_STATUS_REG
));
1173 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
1175 if (!trans_pcie
->txq
) {
1177 "Stopping tx queues that aren't allocated...\n");
1181 /* Unmap DMA from host system and free skb's */
1182 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
1184 iwl_tx_queue_unmap(trans
, txq_id
);
1189 static void iwl_trans_pcie_stop_device(struct iwl_trans
*trans
)
1191 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1192 unsigned long flags
;
1194 /* tell the device to stop sending interrupts */
1195 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
1196 iwl_disable_interrupts(trans
);
1197 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
1199 /* device going down, Stop using ICT table */
1200 iwl_disable_ict(trans
);
1203 * If a HW restart happens during firmware loading,
1204 * then the firmware loading might call this function
1205 * and later it might be called again due to the
1206 * restart. So don't process again if the device is
1209 if (test_bit(STATUS_DEVICE_ENABLED
, &trans_pcie
->status
)) {
1210 iwl_trans_tx_stop(trans
);
1211 iwl_trans_rx_stop(trans
);
1213 /* Power-down device's busmaster DMA clocks */
1214 iwl_write_prph(trans
, APMG_CLK_DIS_REG
,
1215 APMG_CLK_VAL_DMA_CLK_RQT
);
1219 /* Make sure (redundant) we've released our request to stay awake */
1220 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
1221 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1223 /* Stop the device, and put it in low power state */
1224 iwl_apm_stop(trans
);
1226 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1227 * Clean again the interrupt here
1229 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
1230 iwl_disable_interrupts(trans
);
1231 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
1233 iwl_enable_rfkill_int(trans
);
1235 /* wait to make sure we flush pending tasklet*/
1236 synchronize_irq(trans_pcie
->irq
);
1237 tasklet_kill(&trans_pcie
->irq_tasklet
);
1239 cancel_work_sync(&trans_pcie
->rx_replenish
);
1241 /* stop and reset the on-board processor */
1242 iwl_write32(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_NEVO_RESET
);
1244 /* clear all status bits */
1245 clear_bit(STATUS_HCMD_ACTIVE
, &trans_pcie
->status
);
1246 clear_bit(STATUS_INT_ENABLED
, &trans_pcie
->status
);
1247 clear_bit(STATUS_DEVICE_ENABLED
, &trans_pcie
->status
);
1248 clear_bit(STATUS_TPOWER_PMI
, &trans_pcie
->status
);
1249 clear_bit(STATUS_RFKILL
, &trans_pcie
->status
);
1252 static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans
*trans
)
1254 /* let the ucode operate on its own */
1255 iwl_write32(trans
, CSR_UCODE_DRV_GP1_SET
,
1256 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE
);
1258 iwl_disable_interrupts(trans
);
1259 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
1260 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1263 static int iwl_trans_pcie_tx(struct iwl_trans
*trans
, struct sk_buff
*skb
,
1264 struct iwl_device_cmd
*dev_cmd
, int txq_id
)
1266 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1267 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1268 struct iwl_tx_cmd
*tx_cmd
= (struct iwl_tx_cmd
*) dev_cmd
->payload
;
1269 struct iwl_cmd_meta
*out_meta
;
1270 struct iwl_tx_queue
*txq
;
1271 struct iwl_queue
*q
;
1272 dma_addr_t phys_addr
= 0;
1273 dma_addr_t txcmd_phys
;
1274 dma_addr_t scratch_phys
;
1275 u16 len
, firstlen
, secondlen
;
1276 u8 wait_write_ptr
= 0;
1277 __le16 fc
= hdr
->frame_control
;
1278 u8 hdr_len
= ieee80211_hdrlen(fc
);
1279 u16 __maybe_unused wifi_seq
;
1281 txq
= &trans_pcie
->txq
[txq_id
];
1284 if (unlikely(!test_bit(txq_id
, trans_pcie
->queue_used
))) {
1289 spin_lock(&txq
->lock
);
1291 /* In AGG mode, the index in the ring must correspond to the WiFi
1292 * sequence number. This is a HW requirements to help the SCD to parse
1294 * Check here that the packets are in the right place on the ring.
1296 #ifdef CONFIG_IWLWIFI_DEBUG
1297 wifi_seq
= SEQ_TO_SN(le16_to_cpu(hdr
->seq_ctrl
));
1298 WARN_ONCE((iwl_read_prph(trans
, SCD_AGGR_SEL
) & BIT(txq_id
)) &&
1299 ((wifi_seq
& 0xff) != q
->write_ptr
),
1300 "Q: %d WiFi Seq %d tfdNum %d",
1301 txq_id
, wifi_seq
, q
->write_ptr
);
1304 /* Set up driver data for this TFD */
1305 txq
->entries
[q
->write_ptr
].skb
= skb
;
1306 txq
->entries
[q
->write_ptr
].cmd
= dev_cmd
;
1308 dev_cmd
->hdr
.cmd
= REPLY_TX
;
1309 dev_cmd
->hdr
.sequence
=
1310 cpu_to_le16((u16
)(QUEUE_TO_SEQ(txq_id
) |
1311 INDEX_TO_SEQ(q
->write_ptr
)));
1313 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1314 out_meta
= &txq
->entries
[q
->write_ptr
].meta
;
1317 * Use the first empty entry in this queue's command buffer array
1318 * to contain the Tx command and MAC header concatenated together
1319 * (payload data will be in another buffer).
1320 * Size of this varies, due to varying MAC header length.
1321 * If end is not dword aligned, we'll have 2 extra bytes at the end
1322 * of the MAC header (device reads on dword boundaries).
1323 * We'll tell device about this padding later.
1325 len
= sizeof(struct iwl_tx_cmd
) +
1326 sizeof(struct iwl_cmd_header
) + hdr_len
;
1327 firstlen
= (len
+ 3) & ~3;
1329 /* Tell NIC about any 2-byte padding after MAC header */
1330 if (firstlen
!= len
)
1331 tx_cmd
->tx_flags
|= TX_CMD_FLG_MH_PAD_MSK
;
1333 /* Physical address of this Tx command's header (not MAC header!),
1334 * within command buffer array. */
1335 txcmd_phys
= dma_map_single(trans
->dev
,
1336 &dev_cmd
->hdr
, firstlen
,
1338 if (unlikely(dma_mapping_error(trans
->dev
, txcmd_phys
)))
1340 dma_unmap_addr_set(out_meta
, mapping
, txcmd_phys
);
1341 dma_unmap_len_set(out_meta
, len
, firstlen
);
1343 if (!ieee80211_has_morefrags(fc
)) {
1344 txq
->need_update
= 1;
1347 txq
->need_update
= 0;
1350 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1351 * if any (802.11 null frames have no payload). */
1352 secondlen
= skb
->len
- hdr_len
;
1353 if (secondlen
> 0) {
1354 phys_addr
= dma_map_single(trans
->dev
, skb
->data
+ hdr_len
,
1355 secondlen
, DMA_TO_DEVICE
);
1356 if (unlikely(dma_mapping_error(trans
->dev
, phys_addr
))) {
1357 dma_unmap_single(trans
->dev
,
1358 dma_unmap_addr(out_meta
, mapping
),
1359 dma_unmap_len(out_meta
, len
),
1365 /* Attach buffers to TFD */
1366 iwlagn_txq_attach_buf_to_tfd(trans
, txq
, txcmd_phys
, firstlen
, 1);
1368 iwlagn_txq_attach_buf_to_tfd(trans
, txq
, phys_addr
,
1371 scratch_phys
= txcmd_phys
+ sizeof(struct iwl_cmd_header
) +
1372 offsetof(struct iwl_tx_cmd
, scratch
);
1374 /* take back ownership of DMA buffer to enable update */
1375 dma_sync_single_for_cpu(trans
->dev
, txcmd_phys
, firstlen
,
1377 tx_cmd
->dram_lsb_ptr
= cpu_to_le32(scratch_phys
);
1378 tx_cmd
->dram_msb_ptr
= iwl_get_dma_hi_addr(scratch_phys
);
1380 IWL_DEBUG_TX(trans
, "sequence nr = 0X%x\n",
1381 le16_to_cpu(dev_cmd
->hdr
.sequence
));
1382 IWL_DEBUG_TX(trans
, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd
->tx_flags
));
1384 /* Set up entry for this TFD in Tx byte-count array */
1385 iwl_trans_txq_update_byte_cnt_tbl(trans
, txq
, le16_to_cpu(tx_cmd
->len
));
1387 dma_sync_single_for_device(trans
->dev
, txcmd_phys
, firstlen
,
1390 trace_iwlwifi_dev_tx(trans
->dev
, skb
,
1391 &txq
->tfds
[txq
->q
.write_ptr
],
1392 sizeof(struct iwl_tfd
),
1393 &dev_cmd
->hdr
, firstlen
,
1394 skb
->data
+ hdr_len
, secondlen
);
1395 trace_iwlwifi_dev_tx_data(trans
->dev
, skb
,
1396 skb
->data
+ hdr_len
, secondlen
);
1398 /* start timer if queue currently empty */
1399 if (txq
->need_update
&& q
->read_ptr
== q
->write_ptr
&&
1400 trans_pcie
->wd_timeout
)
1401 mod_timer(&txq
->stuck_timer
, jiffies
+ trans_pcie
->wd_timeout
);
1403 /* Tell device the write index *just past* this latest filled TFD */
1404 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
1405 iwl_txq_update_write_ptr(trans
, txq
);
1408 * At this point the frame is "transmitted" successfully
1409 * and we will get a TX status notification eventually,
1410 * regardless of the value of ret. "ret" only indicates
1411 * whether or not we should update the write pointer.
1413 if (iwl_queue_space(q
) < q
->high_mark
) {
1414 if (wait_write_ptr
) {
1415 txq
->need_update
= 1;
1416 iwl_txq_update_write_ptr(trans
, txq
);
1418 iwl_stop_queue(trans
, txq
);
1421 spin_unlock(&txq
->lock
);
1424 spin_unlock(&txq
->lock
);
1428 static int iwl_trans_pcie_start_hw(struct iwl_trans
*trans
)
1430 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1434 trans_pcie
->inta_mask
= CSR_INI_SET_MASK
;
1436 if (!trans_pcie
->irq_requested
) {
1437 tasklet_init(&trans_pcie
->irq_tasklet
, (void (*)(unsigned long))
1438 iwl_irq_tasklet
, (unsigned long)trans
);
1440 iwl_alloc_isr_ict(trans
);
1442 err
= request_irq(trans_pcie
->irq
, iwl_isr_ict
, IRQF_SHARED
,
1445 IWL_ERR(trans
, "Error allocating IRQ %d\n",
1450 INIT_WORK(&trans_pcie
->rx_replenish
, iwl_bg_rx_replenish
);
1451 trans_pcie
->irq_requested
= true;
1454 err
= iwl_prepare_card_hw(trans
);
1456 IWL_ERR(trans
, "Error while preparing HW: %d\n", err
);
1460 iwl_apm_init(trans
);
1462 /* From now on, the op_mode will be kept updated about RF kill state */
1463 iwl_enable_rfkill_int(trans
);
1465 hw_rfkill
= iwl_is_rfkill_set(trans
);
1466 iwl_op_mode_hw_rf_kill(trans
->op_mode
, hw_rfkill
);
1471 trans_pcie
->irq_requested
= false;
1472 free_irq(trans_pcie
->irq
, trans
);
1474 iwl_free_isr_ict(trans
);
1475 tasklet_kill(&trans_pcie
->irq_tasklet
);
1479 static void iwl_trans_pcie_stop_hw(struct iwl_trans
*trans
,
1480 bool op_mode_leaving
)
1482 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1484 unsigned long flags
;
1486 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
1487 iwl_disable_interrupts(trans
);
1488 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
1490 iwl_apm_stop(trans
);
1492 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
1493 iwl_disable_interrupts(trans
);
1494 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
1496 if (!op_mode_leaving
) {
1498 * Even if we stop the HW, we still want the RF kill
1501 iwl_enable_rfkill_int(trans
);
1504 * Check again since the RF kill state may have changed while
1505 * all the interrupts were disabled, in this case we couldn't
1506 * receive the RF kill interrupt and update the state in the
1509 hw_rfkill
= iwl_is_rfkill_set(trans
);
1510 iwl_op_mode_hw_rf_kill(trans
->op_mode
, hw_rfkill
);
1514 static void iwl_trans_pcie_reclaim(struct iwl_trans
*trans
, int txq_id
, int ssn
,
1515 struct sk_buff_head
*skbs
)
1517 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1518 struct iwl_tx_queue
*txq
= &trans_pcie
->txq
[txq_id
];
1519 /* n_bd is usually 256 => n_bd - 1 = 0xff */
1520 int tfd_num
= ssn
& (txq
->q
.n_bd
- 1);
1522 spin_lock(&txq
->lock
);
1524 if (txq
->q
.read_ptr
!= tfd_num
) {
1525 IWL_DEBUG_TX_REPLY(trans
, "[Q %d] %d -> %d (%d)\n",
1526 txq_id
, txq
->q
.read_ptr
, tfd_num
, ssn
);
1527 iwl_tx_queue_reclaim(trans
, txq_id
, tfd_num
, skbs
);
1528 if (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
)
1529 iwl_wake_queue(trans
, txq
);
1532 spin_unlock(&txq
->lock
);
1535 static void iwl_trans_pcie_write8(struct iwl_trans
*trans
, u32 ofs
, u8 val
)
1537 writeb(val
, IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1540 static void iwl_trans_pcie_write32(struct iwl_trans
*trans
, u32 ofs
, u32 val
)
1542 writel(val
, IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1545 static u32
iwl_trans_pcie_read32(struct iwl_trans
*trans
, u32 ofs
)
1547 return readl(IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1550 static void iwl_trans_pcie_configure(struct iwl_trans
*trans
,
1551 const struct iwl_trans_config
*trans_cfg
)
1553 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1555 trans_pcie
->cmd_queue
= trans_cfg
->cmd_queue
;
1556 trans_pcie
->cmd_fifo
= trans_cfg
->cmd_fifo
;
1557 if (WARN_ON(trans_cfg
->n_no_reclaim_cmds
> MAX_NO_RECLAIM_CMDS
))
1558 trans_pcie
->n_no_reclaim_cmds
= 0;
1560 trans_pcie
->n_no_reclaim_cmds
= trans_cfg
->n_no_reclaim_cmds
;
1561 if (trans_pcie
->n_no_reclaim_cmds
)
1562 memcpy(trans_pcie
->no_reclaim_cmds
, trans_cfg
->no_reclaim_cmds
,
1563 trans_pcie
->n_no_reclaim_cmds
* sizeof(u8
));
1565 trans_pcie
->rx_buf_size_8k
= trans_cfg
->rx_buf_size_8k
;
1566 if (trans_pcie
->rx_buf_size_8k
)
1567 trans_pcie
->rx_page_order
= get_order(8 * 1024);
1569 trans_pcie
->rx_page_order
= get_order(4 * 1024);
1571 trans_pcie
->wd_timeout
=
1572 msecs_to_jiffies(trans_cfg
->queue_watchdog_timeout
);
1574 trans_pcie
->command_names
= trans_cfg
->command_names
;
1577 void iwl_trans_pcie_free(struct iwl_trans
*trans
)
1579 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1581 iwl_trans_pcie_tx_free(trans
);
1582 iwl_trans_pcie_rx_free(trans
);
1584 if (trans_pcie
->irq_requested
== true) {
1585 free_irq(trans_pcie
->irq
, trans
);
1586 iwl_free_isr_ict(trans
);
1589 pci_disable_msi(trans_pcie
->pci_dev
);
1590 iounmap(trans_pcie
->hw_base
);
1591 pci_release_regions(trans_pcie
->pci_dev
);
1592 pci_disable_device(trans_pcie
->pci_dev
);
1593 kmem_cache_destroy(trans
->dev_cmd_pool
);
1598 static void iwl_trans_pcie_set_pmi(struct iwl_trans
*trans
, bool state
)
1600 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1603 set_bit(STATUS_TPOWER_PMI
, &trans_pcie
->status
);
1605 clear_bit(STATUS_TPOWER_PMI
, &trans_pcie
->status
);
1608 #ifdef CONFIG_PM_SLEEP
1609 static int iwl_trans_pcie_suspend(struct iwl_trans
*trans
)
1614 static int iwl_trans_pcie_resume(struct iwl_trans
*trans
)
1618 iwl_enable_rfkill_int(trans
);
1620 hw_rfkill
= iwl_is_rfkill_set(trans
);
1621 iwl_op_mode_hw_rf_kill(trans
->op_mode
, hw_rfkill
);
1624 iwl_enable_interrupts(trans
);
1628 #endif /* CONFIG_PM_SLEEP */
1630 #define IWL_FLUSH_WAIT_MS 2000
1632 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans
*trans
)
1634 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1635 struct iwl_tx_queue
*txq
;
1636 struct iwl_queue
*q
;
1638 unsigned long now
= jiffies
;
1641 /* waiting for all the tx frames complete might take a while */
1642 for (cnt
= 0; cnt
< trans
->cfg
->base_params
->num_of_queues
; cnt
++) {
1643 if (cnt
== trans_pcie
->cmd_queue
)
1645 txq
= &trans_pcie
->txq
[cnt
];
1647 while (q
->read_ptr
!= q
->write_ptr
&& !time_after(jiffies
,
1648 now
+ msecs_to_jiffies(IWL_FLUSH_WAIT_MS
)))
1651 if (q
->read_ptr
!= q
->write_ptr
) {
1652 IWL_ERR(trans
, "fail to flush all tx fifo queues\n");
1660 static const char *get_fh_string(int cmd
)
1662 #define IWL_CMD(x) case x: return #x
1664 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG
);
1665 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG
);
1666 IWL_CMD(FH_RSCSR_CHNL0_WPTR
);
1667 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG
);
1668 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG
);
1669 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG
);
1670 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
);
1671 IWL_CMD(FH_TSSR_TX_STATUS_REG
);
1672 IWL_CMD(FH_TSSR_TX_ERROR_REG
);
1679 int iwl_dump_fh(struct iwl_trans
*trans
, char **buf
)
1682 static const u32 fh_tbl
[] = {
1683 FH_RSCSR_CHNL0_STTS_WPTR_REG
,
1684 FH_RSCSR_CHNL0_RBDCB_BASE_REG
,
1685 FH_RSCSR_CHNL0_WPTR
,
1686 FH_MEM_RCSR_CHNL0_CONFIG_REG
,
1687 FH_MEM_RSSR_SHARED_CTRL_REG
,
1688 FH_MEM_RSSR_RX_STATUS_REG
,
1689 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
,
1690 FH_TSSR_TX_STATUS_REG
,
1691 FH_TSSR_TX_ERROR_REG
1694 #ifdef CONFIG_IWLWIFI_DEBUGFS
1697 size_t bufsz
= ARRAY_SIZE(fh_tbl
) * 48 + 40;
1699 *buf
= kmalloc(bufsz
, GFP_KERNEL
);
1703 pos
+= scnprintf(*buf
+ pos
, bufsz
- pos
,
1704 "FH register values:\n");
1706 for (i
= 0; i
< ARRAY_SIZE(fh_tbl
); i
++)
1707 pos
+= scnprintf(*buf
+ pos
, bufsz
- pos
,
1709 get_fh_string(fh_tbl
[i
]),
1710 iwl_read_direct32(trans
, fh_tbl
[i
]));
1716 IWL_ERR(trans
, "FH register values:\n");
1717 for (i
= 0; i
< ARRAY_SIZE(fh_tbl
); i
++)
1718 IWL_ERR(trans
, " %34s: 0X%08x\n",
1719 get_fh_string(fh_tbl
[i
]),
1720 iwl_read_direct32(trans
, fh_tbl
[i
]));
1725 static const char *get_csr_string(int cmd
)
1727 #define IWL_CMD(x) case x: return #x
1729 IWL_CMD(CSR_HW_IF_CONFIG_REG
);
1730 IWL_CMD(CSR_INT_COALESCING
);
1732 IWL_CMD(CSR_INT_MASK
);
1733 IWL_CMD(CSR_FH_INT_STATUS
);
1734 IWL_CMD(CSR_GPIO_IN
);
1736 IWL_CMD(CSR_GP_CNTRL
);
1737 IWL_CMD(CSR_HW_REV
);
1738 IWL_CMD(CSR_EEPROM_REG
);
1739 IWL_CMD(CSR_EEPROM_GP
);
1740 IWL_CMD(CSR_OTP_GP_REG
);
1741 IWL_CMD(CSR_GIO_REG
);
1742 IWL_CMD(CSR_GP_UCODE_REG
);
1743 IWL_CMD(CSR_GP_DRIVER_REG
);
1744 IWL_CMD(CSR_UCODE_DRV_GP1
);
1745 IWL_CMD(CSR_UCODE_DRV_GP2
);
1746 IWL_CMD(CSR_LED_REG
);
1747 IWL_CMD(CSR_DRAM_INT_TBL_REG
);
1748 IWL_CMD(CSR_GIO_CHICKEN_BITS
);
1749 IWL_CMD(CSR_ANA_PLL_CFG
);
1750 IWL_CMD(CSR_HW_REV_WA_REG
);
1751 IWL_CMD(CSR_DBG_HPET_MEM_REG
);
1758 void iwl_dump_csr(struct iwl_trans
*trans
)
1761 static const u32 csr_tbl
[] = {
1762 CSR_HW_IF_CONFIG_REG
,
1780 CSR_DRAM_INT_TBL_REG
,
1781 CSR_GIO_CHICKEN_BITS
,
1784 CSR_DBG_HPET_MEM_REG
1786 IWL_ERR(trans
, "CSR values:\n");
1787 IWL_ERR(trans
, "(2nd byte of CSR_INT_COALESCING is "
1788 "CSR_INT_PERIODIC_REG)\n");
1789 for (i
= 0; i
< ARRAY_SIZE(csr_tbl
); i
++) {
1790 IWL_ERR(trans
, " %25s: 0X%08x\n",
1791 get_csr_string(csr_tbl
[i
]),
1792 iwl_read32(trans
, csr_tbl
[i
]));
1796 #ifdef CONFIG_IWLWIFI_DEBUGFS
1797 /* create and remove of files */
1798 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1799 if (!debugfs_create_file(#name, mode, parent, trans, \
1800 &iwl_dbgfs_##name##_ops)) \
1804 /* file operation */
1805 #define DEBUGFS_READ_FUNC(name) \
1806 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1807 char __user *user_buf, \
1808 size_t count, loff_t *ppos);
1810 #define DEBUGFS_WRITE_FUNC(name) \
1811 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1812 const char __user *user_buf, \
1813 size_t count, loff_t *ppos);
1816 #define DEBUGFS_READ_FILE_OPS(name) \
1817 DEBUGFS_READ_FUNC(name); \
1818 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1819 .read = iwl_dbgfs_##name##_read, \
1820 .open = simple_open, \
1821 .llseek = generic_file_llseek, \
1824 #define DEBUGFS_WRITE_FILE_OPS(name) \
1825 DEBUGFS_WRITE_FUNC(name); \
1826 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1827 .write = iwl_dbgfs_##name##_write, \
1828 .open = simple_open, \
1829 .llseek = generic_file_llseek, \
1832 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1833 DEBUGFS_READ_FUNC(name); \
1834 DEBUGFS_WRITE_FUNC(name); \
1835 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1836 .write = iwl_dbgfs_##name##_write, \
1837 .read = iwl_dbgfs_##name##_read, \
1838 .open = simple_open, \
1839 .llseek = generic_file_llseek, \
1842 static ssize_t
iwl_dbgfs_tx_queue_read(struct file
*file
,
1843 char __user
*user_buf
,
1844 size_t count
, loff_t
*ppos
)
1846 struct iwl_trans
*trans
= file
->private_data
;
1847 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1848 struct iwl_tx_queue
*txq
;
1849 struct iwl_queue
*q
;
1856 bufsz
= sizeof(char) * 64 * trans
->cfg
->base_params
->num_of_queues
;
1858 if (!trans_pcie
->txq
)
1861 buf
= kzalloc(bufsz
, GFP_KERNEL
);
1865 for (cnt
= 0; cnt
< trans
->cfg
->base_params
->num_of_queues
; cnt
++) {
1866 txq
= &trans_pcie
->txq
[cnt
];
1868 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1869 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1870 cnt
, q
->read_ptr
, q
->write_ptr
,
1871 !!test_bit(cnt
, trans_pcie
->queue_used
),
1872 !!test_bit(cnt
, trans_pcie
->queue_stopped
));
1874 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1879 static ssize_t
iwl_dbgfs_rx_queue_read(struct file
*file
,
1880 char __user
*user_buf
,
1881 size_t count
, loff_t
*ppos
)
1883 struct iwl_trans
*trans
= file
->private_data
;
1884 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1885 struct iwl_rx_queue
*rxq
= &trans_pcie
->rxq
;
1888 const size_t bufsz
= sizeof(buf
);
1890 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "read: %u\n",
1892 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "write: %u\n",
1894 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "free_count: %u\n",
1897 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "closed_rb_num: %u\n",
1898 le16_to_cpu(rxq
->rb_stts
->closed_rb_num
) & 0x0FFF);
1900 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1901 "closed_rb_num: Not Allocated\n");
1903 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1906 static ssize_t
iwl_dbgfs_interrupt_read(struct file
*file
,
1907 char __user
*user_buf
,
1908 size_t count
, loff_t
*ppos
)
1910 struct iwl_trans
*trans
= file
->private_data
;
1911 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1912 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
1916 int bufsz
= 24 * 64; /* 24 items * 64 char per item */
1919 buf
= kzalloc(bufsz
, GFP_KERNEL
);
1923 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1924 "Interrupt Statistics Report:\n");
1926 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "HW Error:\t\t\t %u\n",
1928 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "SW Error:\t\t\t %u\n",
1930 if (isr_stats
->sw
|| isr_stats
->hw
) {
1931 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1932 "\tLast Restarting Code: 0x%X\n",
1933 isr_stats
->err_code
);
1935 #ifdef CONFIG_IWLWIFI_DEBUG
1936 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Frame transmitted:\t\t %u\n",
1938 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Alive interrupt:\t\t %u\n",
1941 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1942 "HW RF KILL switch toggled:\t %u\n", isr_stats
->rfkill
);
1944 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "CT KILL:\t\t\t %u\n",
1947 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Wakeup Interrupt:\t\t %u\n",
1950 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1951 "Rx command responses:\t\t %u\n", isr_stats
->rx
);
1953 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Tx/FH interrupt:\t\t %u\n",
1956 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Unexpected INTA:\t\t %u\n",
1957 isr_stats
->unhandled
);
1959 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1964 static ssize_t
iwl_dbgfs_interrupt_write(struct file
*file
,
1965 const char __user
*user_buf
,
1966 size_t count
, loff_t
*ppos
)
1968 struct iwl_trans
*trans
= file
->private_data
;
1969 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1970 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
1976 memset(buf
, 0, sizeof(buf
));
1977 buf_size
= min(count
, sizeof(buf
) - 1);
1978 if (copy_from_user(buf
, user_buf
, buf_size
))
1980 if (sscanf(buf
, "%x", &reset_flag
) != 1)
1982 if (reset_flag
== 0)
1983 memset(isr_stats
, 0, sizeof(*isr_stats
));
1988 static ssize_t
iwl_dbgfs_csr_write(struct file
*file
,
1989 const char __user
*user_buf
,
1990 size_t count
, loff_t
*ppos
)
1992 struct iwl_trans
*trans
= file
->private_data
;
1997 memset(buf
, 0, sizeof(buf
));
1998 buf_size
= min(count
, sizeof(buf
) - 1);
1999 if (copy_from_user(buf
, user_buf
, buf_size
))
2001 if (sscanf(buf
, "%d", &csr
) != 1)
2004 iwl_dump_csr(trans
);
2009 static ssize_t
iwl_dbgfs_fh_reg_read(struct file
*file
,
2010 char __user
*user_buf
,
2011 size_t count
, loff_t
*ppos
)
2013 struct iwl_trans
*trans
= file
->private_data
;
2016 ssize_t ret
= -EFAULT
;
2018 ret
= pos
= iwl_dump_fh(trans
, &buf
);
2020 ret
= simple_read_from_buffer(user_buf
,
2021 count
, ppos
, buf
, pos
);
2028 static ssize_t
iwl_dbgfs_fw_restart_write(struct file
*file
,
2029 const char __user
*user_buf
,
2030 size_t count
, loff_t
*ppos
)
2032 struct iwl_trans
*trans
= file
->private_data
;
2034 if (!trans
->op_mode
)
2038 iwl_op_mode_nic_error(trans
->op_mode
);
2044 DEBUGFS_READ_WRITE_FILE_OPS(interrupt
);
2045 DEBUGFS_READ_FILE_OPS(fh_reg
);
2046 DEBUGFS_READ_FILE_OPS(rx_queue
);
2047 DEBUGFS_READ_FILE_OPS(tx_queue
);
2048 DEBUGFS_WRITE_FILE_OPS(csr
);
2049 DEBUGFS_WRITE_FILE_OPS(fw_restart
);
2052 * Create the debugfs files and directories
2055 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans
*trans
,
2058 DEBUGFS_ADD_FILE(rx_queue
, dir
, S_IRUSR
);
2059 DEBUGFS_ADD_FILE(tx_queue
, dir
, S_IRUSR
);
2060 DEBUGFS_ADD_FILE(interrupt
, dir
, S_IWUSR
| S_IRUSR
);
2061 DEBUGFS_ADD_FILE(csr
, dir
, S_IWUSR
);
2062 DEBUGFS_ADD_FILE(fh_reg
, dir
, S_IRUSR
);
2063 DEBUGFS_ADD_FILE(fw_restart
, dir
, S_IWUSR
);
2067 IWL_ERR(trans
, "failed to create the trans debugfs entry\n");
2071 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans
*trans
,
2076 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2078 static const struct iwl_trans_ops trans_ops_pcie
= {
2079 .start_hw
= iwl_trans_pcie_start_hw
,
2080 .stop_hw
= iwl_trans_pcie_stop_hw
,
2081 .fw_alive
= iwl_trans_pcie_fw_alive
,
2082 .start_fw
= iwl_trans_pcie_start_fw
,
2083 .stop_device
= iwl_trans_pcie_stop_device
,
2085 .wowlan_suspend
= iwl_trans_pcie_wowlan_suspend
,
2087 .send_cmd
= iwl_trans_pcie_send_cmd
,
2089 .tx
= iwl_trans_pcie_tx
,
2090 .reclaim
= iwl_trans_pcie_reclaim
,
2092 .txq_disable
= iwl_trans_pcie_txq_disable
,
2093 .txq_enable
= iwl_trans_pcie_txq_enable
,
2095 .dbgfs_register
= iwl_trans_pcie_dbgfs_register
,
2097 .wait_tx_queue_empty
= iwl_trans_pcie_wait_tx_queue_empty
,
2099 #ifdef CONFIG_PM_SLEEP
2100 .suspend
= iwl_trans_pcie_suspend
,
2101 .resume
= iwl_trans_pcie_resume
,
2103 .write8
= iwl_trans_pcie_write8
,
2104 .write32
= iwl_trans_pcie_write32
,
2105 .read32
= iwl_trans_pcie_read32
,
2106 .configure
= iwl_trans_pcie_configure
,
2107 .set_pmi
= iwl_trans_pcie_set_pmi
,
2110 struct iwl_trans
*iwl_trans_pcie_alloc(struct pci_dev
*pdev
,
2111 const struct pci_device_id
*ent
,
2112 const struct iwl_cfg
*cfg
)
2114 struct iwl_trans_pcie
*trans_pcie
;
2115 struct iwl_trans
*trans
;
2119 trans
= kzalloc(sizeof(struct iwl_trans
) +
2120 sizeof(struct iwl_trans_pcie
), GFP_KERNEL
);
2122 if (WARN_ON(!trans
))
2125 trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2127 trans
->ops
= &trans_ops_pcie
;
2129 trans_pcie
->trans
= trans
;
2130 spin_lock_init(&trans_pcie
->irq_lock
);
2131 init_waitqueue_head(&trans_pcie
->ucode_write_waitq
);
2133 /* W/A - seems to solve weird behavior. We need to remove this if we
2134 * don't want to stay in L1 all the time. This wastes a lot of power */
2135 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
|
2136 PCIE_LINK_STATE_CLKPM
);
2138 if (pci_enable_device(pdev
)) {
2143 pci_set_master(pdev
);
2145 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(36));
2147 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(36));
2149 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
2151 err
= pci_set_consistent_dma_mask(pdev
,
2153 /* both attempts failed: */
2155 dev_printk(KERN_ERR
, &pdev
->dev
,
2156 "No suitable DMA available.\n");
2157 goto out_pci_disable_device
;
2161 err
= pci_request_regions(pdev
, DRV_NAME
);
2163 dev_printk(KERN_ERR
, &pdev
->dev
,
2164 "pci_request_regions failed\n");
2165 goto out_pci_disable_device
;
2168 trans_pcie
->hw_base
= pci_ioremap_bar(pdev
, 0);
2169 if (!trans_pcie
->hw_base
) {
2170 dev_printk(KERN_ERR
, &pdev
->dev
, "pci_ioremap_bar failed\n");
2172 goto out_pci_release_regions
;
2175 dev_printk(KERN_INFO
, &pdev
->dev
,
2176 "pci_resource_len = 0x%08llx\n",
2177 (unsigned long long) pci_resource_len(pdev
, 0));
2178 dev_printk(KERN_INFO
, &pdev
->dev
,
2179 "pci_resource_base = %p\n", trans_pcie
->hw_base
);
2181 dev_printk(KERN_INFO
, &pdev
->dev
,
2182 "HW Revision ID = 0x%X\n", pdev
->revision
);
2184 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2185 * PCI Tx retries from interfering with C3 CPU state */
2186 pci_write_config_byte(pdev
, PCI_CFG_RETRY_TIMEOUT
, 0x00);
2188 err
= pci_enable_msi(pdev
);
2190 dev_printk(KERN_ERR
, &pdev
->dev
,
2191 "pci_enable_msi failed(0X%x)\n", err
);
2193 trans
->dev
= &pdev
->dev
;
2194 trans_pcie
->irq
= pdev
->irq
;
2195 trans_pcie
->pci_dev
= pdev
;
2196 trans
->hw_rev
= iwl_read32(trans
, CSR_HW_REV
);
2197 trans
->hw_id
= (pdev
->device
<< 16) + pdev
->subsystem_device
;
2198 snprintf(trans
->hw_id_str
, sizeof(trans
->hw_id_str
),
2199 "PCI ID: 0x%04X:0x%04X", pdev
->device
, pdev
->subsystem_device
);
2201 /* TODO: Move this away, not needed if not MSI */
2202 /* enable rfkill interrupt: hw bug w/a */
2203 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
2204 if (pci_cmd
& PCI_COMMAND_INTX_DISABLE
) {
2205 pci_cmd
&= ~PCI_COMMAND_INTX_DISABLE
;
2206 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
2209 /* Initialize the wait queue for commands */
2210 init_waitqueue_head(&trans_pcie
->wait_command_queue
);
2211 spin_lock_init(&trans
->reg_lock
);
2213 snprintf(trans
->dev_cmd_pool_name
, sizeof(trans
->dev_cmd_pool_name
),
2214 "iwl_cmd_pool:%s", dev_name(trans
->dev
));
2216 trans
->dev_cmd_headroom
= 0;
2217 trans
->dev_cmd_pool
=
2218 kmem_cache_create(trans
->dev_cmd_pool_name
,
2219 sizeof(struct iwl_device_cmd
)
2220 + trans
->dev_cmd_headroom
,
2225 if (!trans
->dev_cmd_pool
)
2226 goto out_pci_disable_msi
;
2230 out_pci_disable_msi
:
2231 pci_disable_msi(pdev
);
2232 out_pci_release_regions
:
2233 pci_release_regions(pdev
);
2234 out_pci_disable_device
:
2235 pci_disable_device(pdev
);