1 /******************************************************************************
3 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/slab.h>
31 #include <linux/sched.h>
33 #include "iwl-debug.h"
37 #include "iwl-op-mode.h"
39 /* FIXME: need to abstract out TX command (once we know what it looks like) */
40 #include "dvm/commands.h"
42 #define IWL_TX_CRC_SIZE 4
43 #define IWL_TX_DELIMITER_SIZE 4
45 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
50 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
51 * of buffer descriptors, each of which points to one or more data buffers for
52 * the device to read from or fill. Driver and device exchange status of each
53 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
54 * entries in each circular buffer, to protect against confusing empty and full
57 * The device reads or writes the data in the queues via the device's several
58 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
60 * For Tx queue, there are low mark and high mark limits. If, after queuing
61 * the packet for Tx, free space become < low mark, Tx queue stopped. When
62 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
65 ***************************************************/
66 static int iwl_queue_space(const struct iwl_queue
*q
)
72 * To avoid ambiguity between empty and completely full queues, there
73 * should always be less than q->n_bd elements in the queue.
74 * If q->n_window is smaller than q->n_bd, there is no need to reserve
75 * any queue entries for this purpose.
77 if (q
->n_window
< q
->n_bd
)
83 * q->n_bd is a power of 2, so the following is equivalent to modulo by
84 * q->n_bd and is well defined for negative dividends.
86 used
= (q
->write_ptr
- q
->read_ptr
) & (q
->n_bd
- 1);
88 if (WARN_ON(used
> max
))
95 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
97 static int iwl_queue_init(struct iwl_queue
*q
, int count
, int slots_num
, u32 id
)
100 q
->n_window
= slots_num
;
103 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
104 * and iwl_queue_dec_wrap are broken. */
105 if (WARN_ON(!is_power_of_2(count
)))
108 /* slots_num must be power-of-two size, otherwise
109 * get_cmd_index is broken. */
110 if (WARN_ON(!is_power_of_2(slots_num
)))
113 q
->low_mark
= q
->n_window
/ 4;
117 q
->high_mark
= q
->n_window
/ 8;
118 if (q
->high_mark
< 2)
127 static int iwl_pcie_alloc_dma_ptr(struct iwl_trans
*trans
,
128 struct iwl_dma_ptr
*ptr
, size_t size
)
130 if (WARN_ON(ptr
->addr
))
133 ptr
->addr
= dma_alloc_coherent(trans
->dev
, size
,
134 &ptr
->dma
, GFP_KERNEL
);
141 static void iwl_pcie_free_dma_ptr(struct iwl_trans
*trans
,
142 struct iwl_dma_ptr
*ptr
)
144 if (unlikely(!ptr
->addr
))
147 dma_free_coherent(trans
->dev
, ptr
->size
, ptr
->addr
, ptr
->dma
);
148 memset(ptr
, 0, sizeof(*ptr
));
151 static void iwl_pcie_txq_stuck_timer(unsigned long data
)
153 struct iwl_txq
*txq
= (void *)data
;
154 struct iwl_queue
*q
= &txq
->q
;
155 struct iwl_trans_pcie
*trans_pcie
= txq
->trans_pcie
;
156 struct iwl_trans
*trans
= iwl_trans_pcie_get_trans(trans_pcie
);
157 u32 scd_sram_addr
= trans_pcie
->scd_base_addr
+
158 SCD_TX_STTS_QUEUE_OFFSET(txq
->q
.id
);
162 spin_lock(&txq
->lock
);
163 /* check if triggered erroneously */
164 if (txq
->q
.read_ptr
== txq
->q
.write_ptr
) {
165 spin_unlock(&txq
->lock
);
168 spin_unlock(&txq
->lock
);
170 IWL_ERR(trans
, "Queue %d stuck for %u ms.\n", txq
->q
.id
,
171 jiffies_to_msecs(trans_pcie
->wd_timeout
));
172 IWL_ERR(trans
, "Current SW read_ptr %d write_ptr %d\n",
173 txq
->q
.read_ptr
, txq
->q
.write_ptr
);
175 iwl_trans_read_mem_bytes(trans
, scd_sram_addr
, buf
, sizeof(buf
));
177 iwl_print_hex_error(trans
, buf
, sizeof(buf
));
179 for (i
= 0; i
< FH_TCSR_CHNL_NUM
; i
++)
180 IWL_ERR(trans
, "FH TRBs(%d) = 0x%08x\n", i
,
181 iwl_read_direct32(trans
, FH_TX_TRB_REG(i
)));
183 for (i
= 0; i
< trans
->cfg
->base_params
->num_of_queues
; i
++) {
184 u32 status
= iwl_read_prph(trans
, SCD_QUEUE_STATUS_BITS(i
));
185 u8 fifo
= (status
>> SCD_QUEUE_STTS_REG_POS_TXF
) & 0x7;
186 bool active
= !!(status
& BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE
));
188 iwl_trans_read_mem32(trans
,
189 trans_pcie
->scd_base_addr
+
190 SCD_TRANS_TBL_OFFSET_QUEUE(i
));
193 tbl_dw
= (tbl_dw
& 0xFFFF0000) >> 16;
195 tbl_dw
= tbl_dw
& 0x0000FFFF;
198 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
199 i
, active
? "" : "in", fifo
, tbl_dw
,
201 SCD_QUEUE_RDPTR(i
)) & (txq
->q
.n_bd
- 1),
202 iwl_read_prph(trans
, SCD_QUEUE_WRPTR(i
)));
205 for (i
= q
->read_ptr
; i
!= q
->write_ptr
;
206 i
= iwl_queue_inc_wrap(i
, q
->n_bd
))
207 IWL_ERR(trans
, "scratch %d = 0x%08x\n", i
,
208 le32_to_cpu(txq
->scratchbufs
[i
].scratch
));
210 iwl_write_prph(trans
, DEVICE_SET_NMI_REG
, 1);
214 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
216 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans
*trans
,
217 struct iwl_txq
*txq
, u16 byte_cnt
)
219 struct iwlagn_scd_bc_tbl
*scd_bc_tbl
;
220 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
221 int write_ptr
= txq
->q
.write_ptr
;
222 int txq_id
= txq
->q
.id
;
225 u16 len
= byte_cnt
+ IWL_TX_CRC_SIZE
+ IWL_TX_DELIMITER_SIZE
;
227 struct iwl_tx_cmd
*tx_cmd
=
228 (void *) txq
->entries
[txq
->q
.write_ptr
].cmd
->payload
;
230 scd_bc_tbl
= trans_pcie
->scd_bc_tbls
.addr
;
232 WARN_ON(len
> 0xFFF || write_ptr
>= TFD_QUEUE_SIZE_MAX
);
234 sta_id
= tx_cmd
->sta_id
;
235 sec_ctl
= tx_cmd
->sec_ctl
;
237 switch (sec_ctl
& TX_CMD_SEC_MSK
) {
239 len
+= IEEE80211_CCMP_MIC_LEN
;
241 case TX_CMD_SEC_TKIP
:
242 len
+= IEEE80211_TKIP_ICV_LEN
;
245 len
+= IEEE80211_WEP_IV_LEN
+ IEEE80211_WEP_ICV_LEN
;
249 if (trans_pcie
->bc_table_dword
)
250 len
= DIV_ROUND_UP(len
, 4);
252 bc_ent
= cpu_to_le16(len
| (sta_id
<< 12));
254 scd_bc_tbl
[txq_id
].tfd_offset
[write_ptr
] = bc_ent
;
256 if (write_ptr
< TFD_QUEUE_SIZE_BC_DUP
)
258 tfd_offset
[TFD_QUEUE_SIZE_MAX
+ write_ptr
] = bc_ent
;
261 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans
*trans
,
264 struct iwl_trans_pcie
*trans_pcie
=
265 IWL_TRANS_GET_PCIE_TRANS(trans
);
266 struct iwlagn_scd_bc_tbl
*scd_bc_tbl
= trans_pcie
->scd_bc_tbls
.addr
;
267 int txq_id
= txq
->q
.id
;
268 int read_ptr
= txq
->q
.read_ptr
;
271 struct iwl_tx_cmd
*tx_cmd
=
272 (void *)txq
->entries
[txq
->q
.read_ptr
].cmd
->payload
;
274 WARN_ON(read_ptr
>= TFD_QUEUE_SIZE_MAX
);
276 if (txq_id
!= trans_pcie
->cmd_queue
)
277 sta_id
= tx_cmd
->sta_id
;
279 bc_ent
= cpu_to_le16(1 | (sta_id
<< 12));
280 scd_bc_tbl
[txq_id
].tfd_offset
[read_ptr
] = bc_ent
;
282 if (read_ptr
< TFD_QUEUE_SIZE_BC_DUP
)
284 tfd_offset
[TFD_QUEUE_SIZE_MAX
+ read_ptr
] = bc_ent
;
288 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
290 void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans
*trans
, struct iwl_txq
*txq
)
292 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
294 int txq_id
= txq
->q
.id
;
296 if (!txq
->need_update
)
300 * explicitly wake up the NIC if:
301 * 1. shadow registers aren't enabled
302 * 2. NIC is woken up for CMD regardless of shadow outside this function
303 * 3. there is a chance that the NIC is asleep
305 if (!trans
->cfg
->base_params
->shadow_reg_enable
&&
306 txq_id
!= trans_pcie
->cmd_queue
&&
307 test_bit(STATUS_TPOWER_PMI
, &trans
->status
)) {
309 * wake up nic if it's powered down ...
310 * uCode will wake up, and interrupt us again, so next
311 * time we'll skip this part.
313 reg
= iwl_read32(trans
, CSR_UCODE_DRV_GP1
);
315 if (reg
& CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP
) {
316 IWL_DEBUG_INFO(trans
, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
318 iwl_set_bit(trans
, CSR_GP_CNTRL
,
319 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
325 * if not in power-save mode, uCode will never sleep when we're
326 * trying to tx (during RFKILL, we're not trying to tx).
328 IWL_DEBUG_TX(trans
, "Q:%d WR: 0x%x\n", txq_id
, txq
->q
.write_ptr
);
329 iwl_write32(trans
, HBUS_TARG_WRPTR
, txq
->q
.write_ptr
| (txq_id
<< 8));
331 txq
->need_update
= false;
334 static inline dma_addr_t
iwl_pcie_tfd_tb_get_addr(struct iwl_tfd
*tfd
, u8 idx
)
336 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
338 dma_addr_t addr
= get_unaligned_le32(&tb
->lo
);
339 if (sizeof(dma_addr_t
) > sizeof(u32
))
341 ((dma_addr_t
)(le16_to_cpu(tb
->hi_n_len
) & 0xF) << 16) << 16;
346 static inline u16
iwl_pcie_tfd_tb_get_len(struct iwl_tfd
*tfd
, u8 idx
)
348 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
350 return le16_to_cpu(tb
->hi_n_len
) >> 4;
353 static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd
*tfd
, u8 idx
,
354 dma_addr_t addr
, u16 len
)
356 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
357 u16 hi_n_len
= len
<< 4;
359 put_unaligned_le32(addr
, &tb
->lo
);
360 if (sizeof(dma_addr_t
) > sizeof(u32
))
361 hi_n_len
|= ((addr
>> 16) >> 16) & 0xF;
363 tb
->hi_n_len
= cpu_to_le16(hi_n_len
);
365 tfd
->num_tbs
= idx
+ 1;
368 static inline u8
iwl_pcie_tfd_get_num_tbs(struct iwl_tfd
*tfd
)
370 return tfd
->num_tbs
& 0x1f;
373 static void iwl_pcie_tfd_unmap(struct iwl_trans
*trans
,
374 struct iwl_cmd_meta
*meta
,
380 /* Sanity check on number of chunks */
381 num_tbs
= iwl_pcie_tfd_get_num_tbs(tfd
);
383 if (num_tbs
>= IWL_NUM_OF_TBS
) {
384 IWL_ERR(trans
, "Too many chunks: %i\n", num_tbs
);
385 /* @todo issue fatal error, it is quite serious situation */
389 /* first TB is never freed - it's the scratchbuf data */
391 for (i
= 1; i
< num_tbs
; i
++)
392 dma_unmap_single(trans
->dev
, iwl_pcie_tfd_tb_get_addr(tfd
, i
),
393 iwl_pcie_tfd_tb_get_len(tfd
, i
),
400 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
401 * @trans - transport private data
403 * @dma_dir - the direction of the DMA mapping
405 * Does NOT advance any TFD circular buffer read/write indexes
406 * Does NOT free the TFD itself (which is within circular buffer)
408 static void iwl_pcie_txq_free_tfd(struct iwl_trans
*trans
, struct iwl_txq
*txq
)
410 struct iwl_tfd
*tfd_tmp
= txq
->tfds
;
412 /* rd_ptr is bounded by n_bd and idx is bounded by n_window */
413 int rd_ptr
= txq
->q
.read_ptr
;
414 int idx
= get_cmd_index(&txq
->q
, rd_ptr
);
416 lockdep_assert_held(&txq
->lock
);
418 /* We have only q->n_window txq->entries, but we use q->n_bd tfds */
419 iwl_pcie_tfd_unmap(trans
, &txq
->entries
[idx
].meta
, &tfd_tmp
[rd_ptr
]);
425 skb
= txq
->entries
[idx
].skb
;
427 /* Can be called from irqs-disabled context
428 * If skb is not NULL, it means that the whole queue is being
429 * freed and that the queue is not empty - free the skb
432 iwl_op_mode_free_skb(trans
->op_mode
, skb
);
433 txq
->entries
[idx
].skb
= NULL
;
438 static int iwl_pcie_txq_build_tfd(struct iwl_trans
*trans
, struct iwl_txq
*txq
,
439 dma_addr_t addr
, u16 len
, u8 reset
)
442 struct iwl_tfd
*tfd
, *tfd_tmp
;
447 tfd
= &tfd_tmp
[q
->write_ptr
];
450 memset(tfd
, 0, sizeof(*tfd
));
452 num_tbs
= iwl_pcie_tfd_get_num_tbs(tfd
);
454 /* Each TFD can point to a maximum 20 Tx buffers */
455 if (num_tbs
>= IWL_NUM_OF_TBS
) {
456 IWL_ERR(trans
, "Error can not send more than %d chunks\n",
461 if (WARN(addr
& ~IWL_TX_DMA_MASK
,
462 "Unaligned address = %llx\n", (unsigned long long)addr
))
465 iwl_pcie_tfd_set_tb(tfd
, num_tbs
, addr
, len
);
470 static int iwl_pcie_txq_alloc(struct iwl_trans
*trans
,
471 struct iwl_txq
*txq
, int slots_num
,
474 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
475 size_t tfd_sz
= sizeof(struct iwl_tfd
) * TFD_QUEUE_SIZE_MAX
;
476 size_t scratchbuf_sz
;
479 if (WARN_ON(txq
->entries
|| txq
->tfds
))
482 setup_timer(&txq
->stuck_timer
, iwl_pcie_txq_stuck_timer
,
484 txq
->trans_pcie
= trans_pcie
;
486 txq
->q
.n_window
= slots_num
;
488 txq
->entries
= kcalloc(slots_num
,
489 sizeof(struct iwl_pcie_txq_entry
),
495 if (txq_id
== trans_pcie
->cmd_queue
)
496 for (i
= 0; i
< slots_num
; i
++) {
497 txq
->entries
[i
].cmd
=
498 kmalloc(sizeof(struct iwl_device_cmd
),
500 if (!txq
->entries
[i
].cmd
)
504 /* Circular buffer of transmit frame descriptors (TFDs),
505 * shared with device */
506 txq
->tfds
= dma_alloc_coherent(trans
->dev
, tfd_sz
,
507 &txq
->q
.dma_addr
, GFP_KERNEL
);
511 BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE
!= sizeof(*txq
->scratchbufs
));
512 BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf
, scratch
) !=
513 sizeof(struct iwl_cmd_header
) +
514 offsetof(struct iwl_tx_cmd
, scratch
));
516 scratchbuf_sz
= sizeof(*txq
->scratchbufs
) * slots_num
;
518 txq
->scratchbufs
= dma_alloc_coherent(trans
->dev
, scratchbuf_sz
,
519 &txq
->scratchbufs_dma
,
521 if (!txq
->scratchbufs
)
528 dma_free_coherent(trans
->dev
, tfd_sz
, txq
->tfds
, txq
->q
.dma_addr
);
530 if (txq
->entries
&& txq_id
== trans_pcie
->cmd_queue
)
531 for (i
= 0; i
< slots_num
; i
++)
532 kfree(txq
->entries
[i
].cmd
);
540 static int iwl_pcie_txq_init(struct iwl_trans
*trans
, struct iwl_txq
*txq
,
541 int slots_num
, u32 txq_id
)
545 txq
->need_update
= false;
547 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
548 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
549 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX
& (TFD_QUEUE_SIZE_MAX
- 1));
551 /* Initialize queue's high/low-water marks, and head/tail indexes */
552 ret
= iwl_queue_init(&txq
->q
, TFD_QUEUE_SIZE_MAX
, slots_num
,
557 spin_lock_init(&txq
->lock
);
560 * Tell nic where to find circular buffer of Tx Frame Descriptors for
561 * given Tx queue, and enable the DMA channel used for that queue.
562 * Circular buffer (TFD queue in DRAM) physical base address */
563 iwl_write_direct32(trans
, FH_MEM_CBBC_QUEUE(txq_id
),
564 txq
->q
.dma_addr
>> 8);
570 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's
572 static void iwl_pcie_txq_unmap(struct iwl_trans
*trans
, int txq_id
)
574 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
575 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
576 struct iwl_queue
*q
= &txq
->q
;
581 spin_lock_bh(&txq
->lock
);
582 while (q
->write_ptr
!= q
->read_ptr
) {
583 IWL_DEBUG_TX_REPLY(trans
, "Q %d Free %d\n",
584 txq_id
, q
->read_ptr
);
585 iwl_pcie_txq_free_tfd(trans
, txq
);
586 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
);
589 spin_unlock_bh(&txq
->lock
);
591 /* just in case - this queue may have been stopped */
592 iwl_wake_queue(trans
, txq
);
596 * iwl_pcie_txq_free - Deallocate DMA queue.
597 * @txq: Transmit queue to deallocate.
599 * Empty queue by removing and destroying all BD's.
601 * 0-fill, but do not free "txq" descriptor structure.
603 static void iwl_pcie_txq_free(struct iwl_trans
*trans
, int txq_id
)
605 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
606 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
607 struct device
*dev
= trans
->dev
;
613 iwl_pcie_txq_unmap(trans
, txq_id
);
615 /* De-alloc array of command/tx buffers */
616 if (txq_id
== trans_pcie
->cmd_queue
)
617 for (i
= 0; i
< txq
->q
.n_window
; i
++) {
618 kfree(txq
->entries
[i
].cmd
);
619 kfree(txq
->entries
[i
].free_buf
);
622 /* De-alloc circular buffer of TFDs */
624 dma_free_coherent(dev
, sizeof(struct iwl_tfd
) *
625 txq
->q
.n_bd
, txq
->tfds
, txq
->q
.dma_addr
);
628 dma_free_coherent(dev
,
629 sizeof(*txq
->scratchbufs
) * txq
->q
.n_window
,
630 txq
->scratchbufs
, txq
->scratchbufs_dma
);
636 del_timer_sync(&txq
->stuck_timer
);
638 /* 0-fill queue descriptor structure */
639 memset(txq
, 0, sizeof(*txq
));
643 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
645 static void iwl_pcie_txq_set_sched(struct iwl_trans
*trans
, u32 mask
)
647 struct iwl_trans_pcie __maybe_unused
*trans_pcie
=
648 IWL_TRANS_GET_PCIE_TRANS(trans
);
650 iwl_write_prph(trans
, SCD_TXFACT
, mask
);
653 void iwl_pcie_tx_start(struct iwl_trans
*trans
, u32 scd_base_addr
)
655 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
656 int nq
= trans
->cfg
->base_params
->num_of_queues
;
659 int clear_dwords
= (SCD_TRANS_TBL_OFFSET_QUEUE(nq
) -
660 SCD_CONTEXT_MEM_LOWER_BOUND
) / sizeof(u32
);
662 /* make sure all queue are not stopped/used */
663 memset(trans_pcie
->queue_stopped
, 0, sizeof(trans_pcie
->queue_stopped
));
664 memset(trans_pcie
->queue_used
, 0, sizeof(trans_pcie
->queue_used
));
666 trans_pcie
->scd_base_addr
=
667 iwl_read_prph(trans
, SCD_SRAM_BASE_ADDR
);
669 WARN_ON(scd_base_addr
!= 0 &&
670 scd_base_addr
!= trans_pcie
->scd_base_addr
);
672 /* reset context data, TX status and translation data */
673 iwl_trans_write_mem(trans
, trans_pcie
->scd_base_addr
+
674 SCD_CONTEXT_MEM_LOWER_BOUND
,
677 iwl_write_prph(trans
, SCD_DRAM_BASE_ADDR
,
678 trans_pcie
->scd_bc_tbls
.dma
>> 10);
680 /* The chain extension of the SCD doesn't work well. This feature is
681 * enabled by default by the HW, so we need to disable it manually.
683 iwl_write_prph(trans
, SCD_CHAINEXT_EN
, 0);
685 iwl_trans_ac_txq_enable(trans
, trans_pcie
->cmd_queue
,
686 trans_pcie
->cmd_fifo
);
688 /* Activate all Tx DMA/FIFO channels */
689 iwl_pcie_txq_set_sched(trans
, IWL_MASK(0, 7));
691 /* Enable DMA channel */
692 for (chan
= 0; chan
< FH_TCSR_CHNL_NUM
; chan
++)
693 iwl_write_direct32(trans
, FH_TCSR_CHNL_TX_CONFIG_REG(chan
),
694 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
695 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE
);
697 /* Update FH chicken bits */
698 reg_val
= iwl_read_direct32(trans
, FH_TX_CHICKEN_BITS_REG
);
699 iwl_write_direct32(trans
, FH_TX_CHICKEN_BITS_REG
,
700 reg_val
| FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN
);
702 /* Enable L1-Active */
703 if (trans
->cfg
->device_family
!= IWL_DEVICE_FAMILY_8000
)
704 iwl_clear_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
705 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
708 void iwl_trans_pcie_tx_reset(struct iwl_trans
*trans
)
710 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
713 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
715 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
717 iwl_write_direct32(trans
, FH_MEM_CBBC_QUEUE(txq_id
),
718 txq
->q
.dma_addr
>> 8);
719 iwl_pcie_txq_unmap(trans
, txq_id
);
721 txq
->q
.write_ptr
= 0;
724 /* Tell NIC where to find the "keep warm" buffer */
725 iwl_write_direct32(trans
, FH_KW_MEM_ADDR_REG
,
726 trans_pcie
->kw
.dma
>> 4);
728 iwl_pcie_tx_start(trans
, trans_pcie
->scd_base_addr
);
732 * iwl_pcie_tx_stop - Stop all Tx DMA channels
734 int iwl_pcie_tx_stop(struct iwl_trans
*trans
)
736 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
739 /* Turn off all Tx DMA fifos */
740 spin_lock(&trans_pcie
->irq_lock
);
742 iwl_pcie_txq_set_sched(trans
, 0);
744 /* Stop each Tx DMA channel, and wait for it to be idle */
745 for (ch
= 0; ch
< FH_TCSR_CHNL_NUM
; ch
++) {
746 iwl_write_direct32(trans
,
747 FH_TCSR_CHNL_TX_CONFIG_REG(ch
), 0x0);
748 ret
= iwl_poll_direct_bit(trans
, FH_TSSR_TX_STATUS_REG
,
749 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch
), 1000);
752 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
754 iwl_read_direct32(trans
,
755 FH_TSSR_TX_STATUS_REG
));
757 spin_unlock(&trans_pcie
->irq_lock
);
760 * This function can be called before the op_mode disabled the
761 * queues. This happens when we have an rfkill interrupt.
762 * Since we stop Tx altogether - mark the queues as stopped.
764 memset(trans_pcie
->queue_stopped
, 0, sizeof(trans_pcie
->queue_stopped
));
765 memset(trans_pcie
->queue_used
, 0, sizeof(trans_pcie
->queue_used
));
767 /* This can happen: start_hw, stop_device */
768 if (!trans_pcie
->txq
)
771 /* Unmap DMA from host system and free skb's */
772 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
774 iwl_pcie_txq_unmap(trans
, txq_id
);
780 * iwl_trans_tx_free - Free TXQ Context
782 * Destroy all TX DMA queues and structures
784 void iwl_pcie_tx_free(struct iwl_trans
*trans
)
787 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
790 if (trans_pcie
->txq
) {
792 txq_id
< trans
->cfg
->base_params
->num_of_queues
; txq_id
++)
793 iwl_pcie_txq_free(trans
, txq_id
);
796 kfree(trans_pcie
->txq
);
797 trans_pcie
->txq
= NULL
;
799 iwl_pcie_free_dma_ptr(trans
, &trans_pcie
->kw
);
801 iwl_pcie_free_dma_ptr(trans
, &trans_pcie
->scd_bc_tbls
);
805 * iwl_pcie_tx_alloc - allocate TX context
806 * Allocate all Tx DMA structures and initialize them
808 static int iwl_pcie_tx_alloc(struct iwl_trans
*trans
)
811 int txq_id
, slots_num
;
812 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
814 u16 scd_bc_tbls_size
= trans
->cfg
->base_params
->num_of_queues
*
815 sizeof(struct iwlagn_scd_bc_tbl
);
817 /*It is not allowed to alloc twice, so warn when this happens.
818 * We cannot rely on the previous allocation, so free and fail */
819 if (WARN_ON(trans_pcie
->txq
)) {
824 ret
= iwl_pcie_alloc_dma_ptr(trans
, &trans_pcie
->scd_bc_tbls
,
827 IWL_ERR(trans
, "Scheduler BC Table allocation failed\n");
831 /* Alloc keep-warm buffer */
832 ret
= iwl_pcie_alloc_dma_ptr(trans
, &trans_pcie
->kw
, IWL_KW_SIZE
);
834 IWL_ERR(trans
, "Keep Warm allocation failed\n");
838 trans_pcie
->txq
= kcalloc(trans
->cfg
->base_params
->num_of_queues
,
839 sizeof(struct iwl_txq
), GFP_KERNEL
);
840 if (!trans_pcie
->txq
) {
841 IWL_ERR(trans
, "Not enough memory for txq\n");
846 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
847 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
849 slots_num
= (txq_id
== trans_pcie
->cmd_queue
) ?
850 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
851 ret
= iwl_pcie_txq_alloc(trans
, &trans_pcie
->txq
[txq_id
],
854 IWL_ERR(trans
, "Tx %d queue alloc failed\n", txq_id
);
862 iwl_pcie_tx_free(trans
);
866 int iwl_pcie_tx_init(struct iwl_trans
*trans
)
868 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
870 int txq_id
, slots_num
;
873 if (!trans_pcie
->txq
) {
874 ret
= iwl_pcie_tx_alloc(trans
);
880 spin_lock(&trans_pcie
->irq_lock
);
882 /* Turn off all Tx DMA fifos */
883 iwl_write_prph(trans
, SCD_TXFACT
, 0);
885 /* Tell NIC where to find the "keep warm" buffer */
886 iwl_write_direct32(trans
, FH_KW_MEM_ADDR_REG
,
887 trans_pcie
->kw
.dma
>> 4);
889 spin_unlock(&trans_pcie
->irq_lock
);
891 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
892 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
894 slots_num
= (txq_id
== trans_pcie
->cmd_queue
) ?
895 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
896 ret
= iwl_pcie_txq_init(trans
, &trans_pcie
->txq
[txq_id
],
899 IWL_ERR(trans
, "Tx %d queue init failed\n", txq_id
);
906 /*Upon error, free only if we allocated something */
908 iwl_pcie_tx_free(trans
);
912 static inline void iwl_pcie_txq_progress(struct iwl_trans_pcie
*trans_pcie
,
915 if (!trans_pcie
->wd_timeout
)
919 * if empty delete timer, otherwise move timer forward
920 * since we're making progress on this queue
922 if (txq
->q
.read_ptr
== txq
->q
.write_ptr
)
923 del_timer(&txq
->stuck_timer
);
925 mod_timer(&txq
->stuck_timer
, jiffies
+ trans_pcie
->wd_timeout
);
928 /* Frees buffers until index _not_ inclusive */
929 void iwl_trans_pcie_reclaim(struct iwl_trans
*trans
, int txq_id
, int ssn
,
930 struct sk_buff_head
*skbs
)
932 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
933 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
934 /* n_bd is usually 256 => n_bd - 1 = 0xff */
935 int tfd_num
= ssn
& (txq
->q
.n_bd
- 1);
936 struct iwl_queue
*q
= &txq
->q
;
939 /* This function is not meant to release cmd queue*/
940 if (WARN_ON(txq_id
== trans_pcie
->cmd_queue
))
943 spin_lock_bh(&txq
->lock
);
946 IWL_DEBUG_TX_QUEUES(trans
, "Q %d inactive - ignoring idx %d\n",
951 if (txq
->q
.read_ptr
== tfd_num
)
954 IWL_DEBUG_TX_REPLY(trans
, "[Q %d] %d -> %d (%d)\n",
955 txq_id
, txq
->q
.read_ptr
, tfd_num
, ssn
);
957 /*Since we free until index _not_ inclusive, the one before index is
958 * the last we will free. This one must be used */
959 last_to_free
= iwl_queue_dec_wrap(tfd_num
, q
->n_bd
);
961 if (!iwl_queue_used(q
, last_to_free
)) {
963 "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
964 __func__
, txq_id
, last_to_free
, q
->n_bd
,
965 q
->write_ptr
, q
->read_ptr
);
969 if (WARN_ON(!skb_queue_empty(skbs
)))
973 q
->read_ptr
!= tfd_num
;
974 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
976 if (WARN_ON_ONCE(txq
->entries
[txq
->q
.read_ptr
].skb
== NULL
))
979 __skb_queue_tail(skbs
, txq
->entries
[txq
->q
.read_ptr
].skb
);
981 txq
->entries
[txq
->q
.read_ptr
].skb
= NULL
;
983 iwl_pcie_txq_inval_byte_cnt_tbl(trans
, txq
);
985 iwl_pcie_txq_free_tfd(trans
, txq
);
988 iwl_pcie_txq_progress(trans_pcie
, txq
);
990 if (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
)
991 iwl_wake_queue(trans
, txq
);
993 spin_unlock_bh(&txq
->lock
);
997 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
999 * When FW advances 'R' index, all entries between old and new 'R' index
1000 * need to be reclaimed. As result, some free space forms. If there is
1001 * enough free space (> low mark), wake the stack that feeds us.
1003 static void iwl_pcie_cmdq_reclaim(struct iwl_trans
*trans
, int txq_id
, int idx
)
1005 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1006 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
1007 struct iwl_queue
*q
= &txq
->q
;
1008 unsigned long flags
;
1011 lockdep_assert_held(&txq
->lock
);
1013 if ((idx
>= q
->n_bd
) || (!iwl_queue_used(q
, idx
))) {
1015 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1016 __func__
, txq_id
, idx
, q
->n_bd
,
1017 q
->write_ptr
, q
->read_ptr
);
1021 for (idx
= iwl_queue_inc_wrap(idx
, q
->n_bd
); q
->read_ptr
!= idx
;
1022 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
1025 IWL_ERR(trans
, "HCMD skipped: index (%d) %d %d\n",
1026 idx
, q
->write_ptr
, q
->read_ptr
);
1027 iwl_write_prph(trans
, DEVICE_SET_NMI_REG
, 1);
1031 if (trans
->cfg
->base_params
->apmg_wake_up_wa
&&
1032 q
->read_ptr
== q
->write_ptr
) {
1033 spin_lock_irqsave(&trans_pcie
->reg_lock
, flags
);
1034 WARN_ON(!trans_pcie
->cmd_in_flight
);
1035 trans_pcie
->cmd_in_flight
= false;
1036 __iwl_trans_pcie_clear_bit(trans
,
1038 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1039 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, flags
);
1042 iwl_pcie_txq_progress(trans_pcie
, txq
);
1045 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans
*trans
, u16 ra_tid
,
1048 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1053 scd_q2ratid
= ra_tid
& SCD_QUEUE_RA_TID_MAP_RATID_MSK
;
1055 tbl_dw_addr
= trans_pcie
->scd_base_addr
+
1056 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id
);
1058 tbl_dw
= iwl_trans_read_mem32(trans
, tbl_dw_addr
);
1061 tbl_dw
= (scd_q2ratid
<< 16) | (tbl_dw
& 0x0000FFFF);
1063 tbl_dw
= scd_q2ratid
| (tbl_dw
& 0xFFFF0000);
1065 iwl_trans_write_mem32(trans
, tbl_dw_addr
, tbl_dw
);
1070 static inline void iwl_pcie_txq_set_inactive(struct iwl_trans
*trans
,
1073 /* Simply stop the queue, but don't change any configuration;
1074 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1075 iwl_write_prph(trans
,
1076 SCD_QUEUE_STATUS_BITS(txq_id
),
1077 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE
)|
1078 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN
));
1081 /* Receiver address (actually, Rx station's index into station table),
1082 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1083 #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
1085 void iwl_trans_pcie_txq_enable(struct iwl_trans
*trans
, int txq_id
, int fifo
,
1086 int sta_id
, int tid
, int frame_limit
, u16 ssn
)
1088 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1090 if (test_and_set_bit(txq_id
, trans_pcie
->queue_used
))
1091 WARN_ONCE(1, "queue %d already used - expect issues", txq_id
);
1093 /* Stop this Tx queue before configuring it */
1094 iwl_pcie_txq_set_inactive(trans
, txq_id
);
1096 /* Set this queue as a chain-building queue unless it is CMD queue */
1097 if (txq_id
!= trans_pcie
->cmd_queue
)
1098 iwl_set_bits_prph(trans
, SCD_QUEUECHAIN_SEL
, BIT(txq_id
));
1100 /* If this queue is mapped to a certain station: it is an AGG queue */
1102 u16 ra_tid
= BUILD_RAxTID(sta_id
, tid
);
1104 /* Map receiver-address / traffic-ID to this queue */
1105 iwl_pcie_txq_set_ratid_map(trans
, ra_tid
, txq_id
);
1107 /* enable aggregations for the queue */
1108 iwl_set_bits_prph(trans
, SCD_AGGR_SEL
, BIT(txq_id
));
1109 trans_pcie
->txq
[txq_id
].ampdu
= true;
1112 * disable aggregations for the queue, this will also make the
1113 * ra_tid mapping configuration irrelevant since it is now a
1116 iwl_clear_bits_prph(trans
, SCD_AGGR_SEL
, BIT(txq_id
));
1118 ssn
= trans_pcie
->txq
[txq_id
].q
.read_ptr
;
1121 /* Place first TFD at index corresponding to start sequence number.
1122 * Assumes that ssn_idx is valid (!= 0xFFF) */
1123 trans_pcie
->txq
[txq_id
].q
.read_ptr
= (ssn
& 0xff);
1124 trans_pcie
->txq
[txq_id
].q
.write_ptr
= (ssn
& 0xff);
1126 iwl_write_direct32(trans
, HBUS_TARG_WRPTR
,
1127 (ssn
& 0xff) | (txq_id
<< 8));
1128 iwl_write_prph(trans
, SCD_QUEUE_RDPTR(txq_id
), ssn
);
1130 /* Set up Tx window size and frame limit for this queue */
1131 iwl_trans_write_mem32(trans
, trans_pcie
->scd_base_addr
+
1132 SCD_CONTEXT_QUEUE_OFFSET(txq_id
), 0);
1133 iwl_trans_write_mem32(trans
, trans_pcie
->scd_base_addr
+
1134 SCD_CONTEXT_QUEUE_OFFSET(txq_id
) + sizeof(u32
),
1135 ((frame_limit
<< SCD_QUEUE_CTX_REG2_WIN_SIZE_POS
) &
1136 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK
) |
1137 ((frame_limit
<< SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS
) &
1138 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK
));
1140 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1141 iwl_write_prph(trans
, SCD_QUEUE_STATUS_BITS(txq_id
),
1142 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE
) |
1143 (fifo
<< SCD_QUEUE_STTS_REG_POS_TXF
) |
1144 (1 << SCD_QUEUE_STTS_REG_POS_WSL
) |
1145 SCD_QUEUE_STTS_REG_MSK
);
1146 trans_pcie
->txq
[txq_id
].active
= true;
1147 IWL_DEBUG_TX_QUEUES(trans
, "Activate queue %d on FIFO %d WrPtr: %d\n",
1148 txq_id
, fifo
, ssn
& 0xff);
1151 void iwl_trans_pcie_txq_disable(struct iwl_trans
*trans
, int txq_id
)
1153 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1154 u32 stts_addr
= trans_pcie
->scd_base_addr
+
1155 SCD_TX_STTS_QUEUE_OFFSET(txq_id
);
1156 static const u32 zero_val
[4] = {};
1159 * Upon HW Rfkill - we stop the device, and then stop the queues
1160 * in the op_mode. Just for the sake of the simplicity of the op_mode,
1161 * allow the op_mode to call txq_disable after it already called
1164 if (!test_and_clear_bit(txq_id
, trans_pcie
->queue_used
)) {
1165 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED
, &trans
->status
),
1166 "queue %d not used", txq_id
);
1170 iwl_pcie_txq_set_inactive(trans
, txq_id
);
1172 iwl_trans_write_mem(trans
, stts_addr
, (void *)zero_val
,
1173 ARRAY_SIZE(zero_val
));
1175 iwl_pcie_txq_unmap(trans
, txq_id
);
1176 trans_pcie
->txq
[txq_id
].ampdu
= false;
1178 IWL_DEBUG_TX_QUEUES(trans
, "Deactivate queue %d\n", txq_id
);
1181 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1184 * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1185 * @priv: device private data point
1186 * @cmd: a pointer to the ucode command structure
1188 * The function returns < 0 values to indicate the operation
1189 * failed. On success, it returns the index (>= 0) of command in the
1192 static int iwl_pcie_enqueue_hcmd(struct iwl_trans
*trans
,
1193 struct iwl_host_cmd
*cmd
)
1195 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1196 struct iwl_txq
*txq
= &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
1197 struct iwl_queue
*q
= &txq
->q
;
1198 struct iwl_device_cmd
*out_cmd
;
1199 struct iwl_cmd_meta
*out_meta
;
1200 unsigned long flags
;
1201 void *dup_buf
= NULL
;
1202 dma_addr_t phys_addr
;
1204 u16 copy_size
, cmd_size
, scratch_size
;
1205 bool had_nocopy
= false;
1208 const u8
*cmddata
[IWL_MAX_CMD_TBS_PER_TFD
];
1209 u16 cmdlen
[IWL_MAX_CMD_TBS_PER_TFD
];
1211 copy_size
= sizeof(out_cmd
->hdr
);
1212 cmd_size
= sizeof(out_cmd
->hdr
);
1214 /* need one for the header if the first is NOCOPY */
1215 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD
> IWL_NUM_OF_TBS
- 1);
1217 for (i
= 0; i
< IWL_MAX_CMD_TBS_PER_TFD
; i
++) {
1218 cmddata
[i
] = cmd
->data
[i
];
1219 cmdlen
[i
] = cmd
->len
[i
];
1224 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1225 if (copy_size
< IWL_HCMD_SCRATCHBUF_SIZE
) {
1226 int copy
= IWL_HCMD_SCRATCHBUF_SIZE
- copy_size
;
1228 if (copy
> cmdlen
[i
])
1235 if (cmd
->dataflags
[i
] & IWL_HCMD_DFL_NOCOPY
) {
1237 if (WARN_ON(cmd
->dataflags
[i
] & IWL_HCMD_DFL_DUP
)) {
1241 } else if (cmd
->dataflags
[i
] & IWL_HCMD_DFL_DUP
) {
1243 * This is also a chunk that isn't copied
1244 * to the static buffer so set had_nocopy.
1248 /* only allowed once */
1249 if (WARN_ON(dup_buf
)) {
1254 dup_buf
= kmemdup(cmddata
[i
], cmdlen
[i
],
1259 /* NOCOPY must not be followed by normal! */
1260 if (WARN_ON(had_nocopy
)) {
1264 copy_size
+= cmdlen
[i
];
1266 cmd_size
+= cmd
->len
[i
];
1270 * If any of the command structures end up being larger than
1271 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1272 * allocated into separate TFDs, then we will need to
1273 * increase the size of the buffers.
1275 if (WARN(copy_size
> TFD_MAX_PAYLOAD_SIZE
,
1276 "Command %s (%#x) is too large (%d bytes)\n",
1277 get_cmd_string(trans_pcie
, cmd
->id
), cmd
->id
, copy_size
)) {
1282 spin_lock_bh(&txq
->lock
);
1284 if (iwl_queue_space(q
) < ((cmd
->flags
& CMD_ASYNC
) ? 2 : 1)) {
1285 spin_unlock_bh(&txq
->lock
);
1287 IWL_ERR(trans
, "No space in command queue\n");
1288 iwl_op_mode_cmd_queue_full(trans
->op_mode
);
1293 idx
= get_cmd_index(q
, q
->write_ptr
);
1294 out_cmd
= txq
->entries
[idx
].cmd
;
1295 out_meta
= &txq
->entries
[idx
].meta
;
1297 memset(out_meta
, 0, sizeof(*out_meta
)); /* re-initialize to NULL */
1298 if (cmd
->flags
& CMD_WANT_SKB
)
1299 out_meta
->source
= cmd
;
1301 /* set up the header */
1303 out_cmd
->hdr
.cmd
= cmd
->id
;
1304 out_cmd
->hdr
.flags
= 0;
1305 out_cmd
->hdr
.sequence
=
1306 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie
->cmd_queue
) |
1307 INDEX_TO_SEQ(q
->write_ptr
));
1309 /* and copy the data that needs to be copied */
1310 cmd_pos
= offsetof(struct iwl_device_cmd
, payload
);
1311 copy_size
= sizeof(out_cmd
->hdr
);
1312 for (i
= 0; i
< IWL_MAX_CMD_TBS_PER_TFD
; i
++) {
1318 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1319 if (copy_size
< IWL_HCMD_SCRATCHBUF_SIZE
) {
1320 copy
= IWL_HCMD_SCRATCHBUF_SIZE
- copy_size
;
1322 if (copy
> cmd
->len
[i
])
1326 /* copy everything if not nocopy/dup */
1327 if (!(cmd
->dataflags
[i
] & (IWL_HCMD_DFL_NOCOPY
|
1332 memcpy((u8
*)out_cmd
+ cmd_pos
, cmd
->data
[i
], copy
);
1339 "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1340 get_cmd_string(trans_pcie
, out_cmd
->hdr
.cmd
),
1341 out_cmd
->hdr
.cmd
, le16_to_cpu(out_cmd
->hdr
.sequence
),
1342 cmd_size
, q
->write_ptr
, idx
, trans_pcie
->cmd_queue
);
1344 /* start the TFD with the scratchbuf */
1345 scratch_size
= min_t(int, copy_size
, IWL_HCMD_SCRATCHBUF_SIZE
);
1346 memcpy(&txq
->scratchbufs
[q
->write_ptr
], &out_cmd
->hdr
, scratch_size
);
1347 iwl_pcie_txq_build_tfd(trans
, txq
,
1348 iwl_pcie_get_scratchbuf_dma(txq
, q
->write_ptr
),
1351 /* map first command fragment, if any remains */
1352 if (copy_size
> scratch_size
) {
1353 phys_addr
= dma_map_single(trans
->dev
,
1354 ((u8
*)&out_cmd
->hdr
) + scratch_size
,
1355 copy_size
- scratch_size
,
1357 if (dma_mapping_error(trans
->dev
, phys_addr
)) {
1358 iwl_pcie_tfd_unmap(trans
, out_meta
,
1359 &txq
->tfds
[q
->write_ptr
]);
1364 iwl_pcie_txq_build_tfd(trans
, txq
, phys_addr
,
1365 copy_size
- scratch_size
, 0);
1368 /* map the remaining (adjusted) nocopy/dup fragments */
1369 for (i
= 0; i
< IWL_MAX_CMD_TBS_PER_TFD
; i
++) {
1370 const void *data
= cmddata
[i
];
1374 if (!(cmd
->dataflags
[i
] & (IWL_HCMD_DFL_NOCOPY
|
1377 if (cmd
->dataflags
[i
] & IWL_HCMD_DFL_DUP
)
1379 phys_addr
= dma_map_single(trans
->dev
, (void *)data
,
1380 cmdlen
[i
], DMA_TO_DEVICE
);
1381 if (dma_mapping_error(trans
->dev
, phys_addr
)) {
1382 iwl_pcie_tfd_unmap(trans
, out_meta
,
1383 &txq
->tfds
[q
->write_ptr
]);
1388 iwl_pcie_txq_build_tfd(trans
, txq
, phys_addr
, cmdlen
[i
], 0);
1391 out_meta
->flags
= cmd
->flags
;
1392 if (WARN_ON_ONCE(txq
->entries
[idx
].free_buf
))
1393 kfree(txq
->entries
[idx
].free_buf
);
1394 txq
->entries
[idx
].free_buf
= dup_buf
;
1396 txq
->need_update
= true;
1398 trace_iwlwifi_dev_hcmd(trans
->dev
, cmd
, cmd_size
, &out_cmd
->hdr
);
1400 /* start timer if queue currently empty */
1401 if (q
->read_ptr
== q
->write_ptr
&& trans_pcie
->wd_timeout
)
1402 mod_timer(&txq
->stuck_timer
, jiffies
+ trans_pcie
->wd_timeout
);
1404 spin_lock_irqsave(&trans_pcie
->reg_lock
, flags
);
1407 * wake up the NIC to make sure that the firmware will see the host
1408 * command - we will let the NIC sleep once all the host commands
1409 * returned. This needs to be done only on NICs that have
1410 * apmg_wake_up_wa set.
1412 if (trans
->cfg
->base_params
->apmg_wake_up_wa
&&
1413 !trans_pcie
->cmd_in_flight
) {
1414 trans_pcie
->cmd_in_flight
= true;
1415 __iwl_trans_pcie_set_bit(trans
, CSR_GP_CNTRL
,
1416 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1417 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
1418 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN
,
1419 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
|
1420 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP
),
1423 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
1424 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1425 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, flags
);
1426 trans_pcie
->cmd_in_flight
= false;
1432 /* Increment and update queue's write index */
1433 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
1434 iwl_pcie_txq_inc_wr_ptr(trans
, txq
);
1436 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, flags
);
1439 spin_unlock_bh(&txq
->lock
);
1447 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1448 * @rxb: Rx buffer to reclaim
1449 * @handler_status: return value of the handler of the command
1450 * (put in setup_rx_handlers)
1452 * If an Rx buffer has an async callback associated with it the callback
1453 * will be executed. The attached skb (if present) will only be freed
1454 * if the callback returns 1
1456 void iwl_pcie_hcmd_complete(struct iwl_trans
*trans
,
1457 struct iwl_rx_cmd_buffer
*rxb
, int handler_status
)
1459 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
1460 u16 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
1461 int txq_id
= SEQ_TO_QUEUE(sequence
);
1462 int index
= SEQ_TO_INDEX(sequence
);
1464 struct iwl_device_cmd
*cmd
;
1465 struct iwl_cmd_meta
*meta
;
1466 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1467 struct iwl_txq
*txq
= &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
1469 /* If a Tx command is being handled and it isn't in the actual
1470 * command queue then there a command routing bug has been introduced
1471 * in the queue management code. */
1472 if (WARN(txq_id
!= trans_pcie
->cmd_queue
,
1473 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1474 txq_id
, trans_pcie
->cmd_queue
, sequence
,
1475 trans_pcie
->txq
[trans_pcie
->cmd_queue
].q
.read_ptr
,
1476 trans_pcie
->txq
[trans_pcie
->cmd_queue
].q
.write_ptr
)) {
1477 iwl_print_hex_error(trans
, pkt
, 32);
1481 spin_lock_bh(&txq
->lock
);
1483 cmd_index
= get_cmd_index(&txq
->q
, index
);
1484 cmd
= txq
->entries
[cmd_index
].cmd
;
1485 meta
= &txq
->entries
[cmd_index
].meta
;
1487 iwl_pcie_tfd_unmap(trans
, meta
, &txq
->tfds
[index
]);
1489 /* Input error checking is done when commands are added to queue. */
1490 if (meta
->flags
& CMD_WANT_SKB
) {
1491 struct page
*p
= rxb_steal_page(rxb
);
1493 meta
->source
->resp_pkt
= pkt
;
1494 meta
->source
->_rx_page_addr
= (unsigned long)page_address(p
);
1495 meta
->source
->_rx_page_order
= trans_pcie
->rx_page_order
;
1496 meta
->source
->handler_status
= handler_status
;
1499 iwl_pcie_cmdq_reclaim(trans
, txq_id
, index
);
1501 if (!(meta
->flags
& CMD_ASYNC
)) {
1502 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
)) {
1504 "HCMD_ACTIVE already clear for command %s\n",
1505 get_cmd_string(trans_pcie
, cmd
->hdr
.cmd
));
1507 clear_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
);
1508 IWL_DEBUG_INFO(trans
, "Clearing HCMD_ACTIVE for command %s\n",
1509 get_cmd_string(trans_pcie
, cmd
->hdr
.cmd
));
1510 wake_up(&trans_pcie
->wait_command_queue
);
1515 spin_unlock_bh(&txq
->lock
);
1518 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
1520 static int iwl_pcie_send_hcmd_async(struct iwl_trans
*trans
,
1521 struct iwl_host_cmd
*cmd
)
1523 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1526 /* An asynchronous command can not expect an SKB to be set. */
1527 if (WARN_ON(cmd
->flags
& CMD_WANT_SKB
))
1530 ret
= iwl_pcie_enqueue_hcmd(trans
, cmd
);
1533 "Error sending %s: enqueue_hcmd failed: %d\n",
1534 get_cmd_string(trans_pcie
, cmd
->id
), ret
);
1540 static int iwl_pcie_send_hcmd_sync(struct iwl_trans
*trans
,
1541 struct iwl_host_cmd
*cmd
)
1543 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1547 IWL_DEBUG_INFO(trans
, "Attempting to send sync command %s\n",
1548 get_cmd_string(trans_pcie
, cmd
->id
));
1550 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE
,
1552 "Command %s: a command is already active!\n",
1553 get_cmd_string(trans_pcie
, cmd
->id
)))
1556 IWL_DEBUG_INFO(trans
, "Setting HCMD_ACTIVE for command %s\n",
1557 get_cmd_string(trans_pcie
, cmd
->id
));
1559 cmd_idx
= iwl_pcie_enqueue_hcmd(trans
, cmd
);
1562 clear_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
);
1564 "Error sending %s: enqueue_hcmd failed: %d\n",
1565 get_cmd_string(trans_pcie
, cmd
->id
), ret
);
1569 ret
= wait_event_timeout(trans_pcie
->wait_command_queue
,
1570 !test_bit(STATUS_SYNC_HCMD_ACTIVE
,
1572 HOST_COMPLETE_TIMEOUT
);
1574 struct iwl_txq
*txq
= &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
1575 struct iwl_queue
*q
= &txq
->q
;
1577 IWL_ERR(trans
, "Error sending %s: time out after %dms.\n",
1578 get_cmd_string(trans_pcie
, cmd
->id
),
1579 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT
));
1581 IWL_ERR(trans
, "Current CMD queue read_ptr %d write_ptr %d\n",
1582 q
->read_ptr
, q
->write_ptr
);
1584 clear_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
);
1585 IWL_DEBUG_INFO(trans
, "Clearing HCMD_ACTIVE for command %s\n",
1586 get_cmd_string(trans_pcie
, cmd
->id
));
1589 iwl_write_prph(trans
, DEVICE_SET_NMI_REG
, 1);
1590 iwl_trans_fw_error(trans
);
1595 if (test_bit(STATUS_FW_ERROR
, &trans
->status
)) {
1596 IWL_ERR(trans
, "FW error in SYNC CMD %s\n",
1597 get_cmd_string(trans_pcie
, cmd
->id
));
1603 if (!(cmd
->flags
& CMD_SEND_IN_RFKILL
) &&
1604 test_bit(STATUS_RFKILL
, &trans
->status
)) {
1605 IWL_DEBUG_RF_KILL(trans
, "RFKILL in SYNC CMD... no rsp\n");
1610 if ((cmd
->flags
& CMD_WANT_SKB
) && !cmd
->resp_pkt
) {
1611 IWL_ERR(trans
, "Error: Response NULL in '%s'\n",
1612 get_cmd_string(trans_pcie
, cmd
->id
));
1620 if (cmd
->flags
& CMD_WANT_SKB
) {
1622 * Cancel the CMD_WANT_SKB flag for the cmd in the
1623 * TX cmd queue. Otherwise in case the cmd comes
1624 * in later, it will possibly set an invalid
1625 * address (cmd->meta.source).
1627 trans_pcie
->txq
[trans_pcie
->cmd_queue
].
1628 entries
[cmd_idx
].meta
.flags
&= ~CMD_WANT_SKB
;
1631 if (cmd
->resp_pkt
) {
1633 cmd
->resp_pkt
= NULL
;
1639 int iwl_trans_pcie_send_hcmd(struct iwl_trans
*trans
, struct iwl_host_cmd
*cmd
)
1641 if (!(cmd
->flags
& CMD_SEND_IN_RFKILL
) &&
1642 test_bit(STATUS_RFKILL
, &trans
->status
)) {
1643 IWL_DEBUG_RF_KILL(trans
, "Dropping CMD 0x%x: RF KILL\n",
1648 if (cmd
->flags
& CMD_ASYNC
)
1649 return iwl_pcie_send_hcmd_async(trans
, cmd
);
1651 /* We still can fail on RFKILL that can be asserted while we wait */
1652 return iwl_pcie_send_hcmd_sync(trans
, cmd
);
1655 int iwl_trans_pcie_tx(struct iwl_trans
*trans
, struct sk_buff
*skb
,
1656 struct iwl_device_cmd
*dev_cmd
, int txq_id
)
1658 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1659 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1660 struct iwl_tx_cmd
*tx_cmd
= (struct iwl_tx_cmd
*)dev_cmd
->payload
;
1661 struct iwl_cmd_meta
*out_meta
;
1662 struct iwl_txq
*txq
;
1663 struct iwl_queue
*q
;
1664 dma_addr_t tb0_phys
, tb1_phys
, scratch_phys
;
1666 u16 len
, tb1_len
, tb2_len
;
1667 bool wait_write_ptr
= false;
1668 __le16 fc
= hdr
->frame_control
;
1669 u8 hdr_len
= ieee80211_hdrlen(fc
);
1672 txq
= &trans_pcie
->txq
[txq_id
];
1675 if (WARN_ONCE(!test_bit(txq_id
, trans_pcie
->queue_used
),
1676 "TX on unused queue %d\n", txq_id
))
1679 spin_lock(&txq
->lock
);
1681 /* In AGG mode, the index in the ring must correspond to the WiFi
1682 * sequence number. This is a HW requirements to help the SCD to parse
1684 * Check here that the packets are in the right place on the ring.
1686 wifi_seq
= IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr
->seq_ctrl
));
1687 WARN_ONCE(txq
->ampdu
&&
1688 (wifi_seq
& 0xff) != q
->write_ptr
,
1689 "Q: %d WiFi Seq %d tfdNum %d",
1690 txq_id
, wifi_seq
, q
->write_ptr
);
1692 /* Set up driver data for this TFD */
1693 txq
->entries
[q
->write_ptr
].skb
= skb
;
1694 txq
->entries
[q
->write_ptr
].cmd
= dev_cmd
;
1696 dev_cmd
->hdr
.sequence
=
1697 cpu_to_le16((u16
)(QUEUE_TO_SEQ(txq_id
) |
1698 INDEX_TO_SEQ(q
->write_ptr
)));
1700 tb0_phys
= iwl_pcie_get_scratchbuf_dma(txq
, q
->write_ptr
);
1701 scratch_phys
= tb0_phys
+ sizeof(struct iwl_cmd_header
) +
1702 offsetof(struct iwl_tx_cmd
, scratch
);
1704 tx_cmd
->dram_lsb_ptr
= cpu_to_le32(scratch_phys
);
1705 tx_cmd
->dram_msb_ptr
= iwl_get_dma_hi_addr(scratch_phys
);
1707 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1708 out_meta
= &txq
->entries
[q
->write_ptr
].meta
;
1711 * The second TB (tb1) points to the remainder of the TX command
1712 * and the 802.11 header - dword aligned size
1713 * (This calculation modifies the TX command, so do it before the
1714 * setup of the first TB)
1716 len
= sizeof(struct iwl_tx_cmd
) + sizeof(struct iwl_cmd_header
) +
1717 hdr_len
- IWL_HCMD_SCRATCHBUF_SIZE
;
1718 tb1_len
= ALIGN(len
, 4);
1720 /* Tell NIC about any 2-byte padding after MAC header */
1722 tx_cmd
->tx_flags
|= TX_CMD_FLG_MH_PAD_MSK
;
1724 /* The first TB points to the scratchbuf data - min_copy bytes */
1725 memcpy(&txq
->scratchbufs
[q
->write_ptr
], &dev_cmd
->hdr
,
1726 IWL_HCMD_SCRATCHBUF_SIZE
);
1727 iwl_pcie_txq_build_tfd(trans
, txq
, tb0_phys
,
1728 IWL_HCMD_SCRATCHBUF_SIZE
, 1);
1730 /* there must be data left over for TB1 or this code must be changed */
1731 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd
) < IWL_HCMD_SCRATCHBUF_SIZE
);
1733 /* map the data for TB1 */
1734 tb1_addr
= ((u8
*)&dev_cmd
->hdr
) + IWL_HCMD_SCRATCHBUF_SIZE
;
1735 tb1_phys
= dma_map_single(trans
->dev
, tb1_addr
, tb1_len
, DMA_TO_DEVICE
);
1736 if (unlikely(dma_mapping_error(trans
->dev
, tb1_phys
)))
1738 iwl_pcie_txq_build_tfd(trans
, txq
, tb1_phys
, tb1_len
, 0);
1741 * Set up TFD's third entry to point directly to remainder
1742 * of skb, if any (802.11 null frames have no payload).
1744 tb2_len
= skb
->len
- hdr_len
;
1746 dma_addr_t tb2_phys
= dma_map_single(trans
->dev
,
1747 skb
->data
+ hdr_len
,
1748 tb2_len
, DMA_TO_DEVICE
);
1749 if (unlikely(dma_mapping_error(trans
->dev
, tb2_phys
))) {
1750 iwl_pcie_tfd_unmap(trans
, out_meta
,
1751 &txq
->tfds
[q
->write_ptr
]);
1754 iwl_pcie_txq_build_tfd(trans
, txq
, tb2_phys
, tb2_len
, 0);
1757 /* Set up entry for this TFD in Tx byte-count array */
1758 iwl_pcie_txq_update_byte_cnt_tbl(trans
, txq
, le16_to_cpu(tx_cmd
->len
));
1760 trace_iwlwifi_dev_tx(trans
->dev
, skb
,
1761 &txq
->tfds
[txq
->q
.write_ptr
],
1762 sizeof(struct iwl_tfd
),
1763 &dev_cmd
->hdr
, IWL_HCMD_SCRATCHBUF_SIZE
+ tb1_len
,
1764 skb
->data
+ hdr_len
, tb2_len
);
1765 trace_iwlwifi_dev_tx_data(trans
->dev
, skb
,
1766 skb
->data
+ hdr_len
, tb2_len
);
1768 if (!ieee80211_has_morefrags(fc
)) {
1769 txq
->need_update
= true;
1771 wait_write_ptr
= true;
1772 txq
->need_update
= false;
1775 /* start timer if queue currently empty */
1776 if (txq
->need_update
&& q
->read_ptr
== q
->write_ptr
&&
1777 trans_pcie
->wd_timeout
)
1778 mod_timer(&txq
->stuck_timer
, jiffies
+ trans_pcie
->wd_timeout
);
1780 /* Tell device the write index *just past* this latest filled TFD */
1781 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
1782 iwl_pcie_txq_inc_wr_ptr(trans
, txq
);
1785 * At this point the frame is "transmitted" successfully
1786 * and we will get a TX status notification eventually.
1788 if (iwl_queue_space(q
) < q
->high_mark
) {
1789 if (wait_write_ptr
) {
1790 txq
->need_update
= true;
1791 iwl_pcie_txq_inc_wr_ptr(trans
, txq
);
1793 iwl_stop_queue(trans
, txq
);
1796 spin_unlock(&txq
->lock
);
1799 spin_unlock(&txq
->lock
);