1 /******************************************************************************
3 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
4 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
6 * Portions of this file are derived from the ipw3945 project, as well
7 * as portions of the ieee80211 subsystem header files.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
22 * The full GNU General Public License is included in this distribution in the
23 * file called LICENSE.
25 * Contact Information:
26 * Intel Linux Wireless <ilw@linux.intel.com>
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
29 *****************************************************************************/
30 #include <linux/etherdevice.h>
31 #include <linux/slab.h>
32 #include <linux/sched.h>
34 #include "iwl-debug.h"
39 #include "iwl-op-mode.h"
41 /* FIXME: need to abstract out TX command (once we know what it looks like) */
42 #include "dvm/commands.h"
44 #define IWL_TX_CRC_SIZE 4
45 #define IWL_TX_DELIMITER_SIZE 4
47 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
52 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
53 * of buffer descriptors, each of which points to one or more data buffers for
54 * the device to read from or fill. Driver and device exchange status of each
55 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
56 * entries in each circular buffer, to protect against confusing empty and full
59 * The device reads or writes the data in the queues via the device's several
60 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
62 * For Tx queue, there are low mark and high mark limits. If, after queuing
63 * the packet for Tx, free space become < low mark, Tx queue stopped. When
64 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
67 ***************************************************/
68 static int iwl_queue_space(const struct iwl_queue
*q
)
74 * To avoid ambiguity between empty and completely full queues, there
75 * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue.
76 * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need
77 * to reserve any queue entries for this purpose.
79 if (q
->n_window
< TFD_QUEUE_SIZE_MAX
)
82 max
= TFD_QUEUE_SIZE_MAX
- 1;
85 * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to
86 * modulo by TFD_QUEUE_SIZE_MAX and is well defined.
88 used
= (q
->write_ptr
- q
->read_ptr
) & (TFD_QUEUE_SIZE_MAX
- 1);
90 if (WARN_ON(used
> max
))
97 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
99 static int iwl_queue_init(struct iwl_queue
*q
, int slots_num
, u32 id
)
101 q
->n_window
= slots_num
;
104 /* slots_num must be power-of-two size, otherwise
105 * get_cmd_index is broken. */
106 if (WARN_ON(!is_power_of_2(slots_num
)))
109 q
->low_mark
= q
->n_window
/ 4;
113 q
->high_mark
= q
->n_window
/ 8;
114 if (q
->high_mark
< 2)
123 static int iwl_pcie_alloc_dma_ptr(struct iwl_trans
*trans
,
124 struct iwl_dma_ptr
*ptr
, size_t size
)
126 if (WARN_ON(ptr
->addr
))
129 ptr
->addr
= dma_alloc_coherent(trans
->dev
, size
,
130 &ptr
->dma
, GFP_KERNEL
);
137 static void iwl_pcie_free_dma_ptr(struct iwl_trans
*trans
,
138 struct iwl_dma_ptr
*ptr
)
140 if (unlikely(!ptr
->addr
))
143 dma_free_coherent(trans
->dev
, ptr
->size
, ptr
->addr
, ptr
->dma
);
144 memset(ptr
, 0, sizeof(*ptr
));
147 static void iwl_pcie_txq_stuck_timer(unsigned long data
)
149 struct iwl_txq
*txq
= (void *)data
;
150 struct iwl_queue
*q
= &txq
->q
;
151 struct iwl_trans_pcie
*trans_pcie
= txq
->trans_pcie
;
152 struct iwl_trans
*trans
= iwl_trans_pcie_get_trans(trans_pcie
);
153 u32 scd_sram_addr
= trans_pcie
->scd_base_addr
+
154 SCD_TX_STTS_QUEUE_OFFSET(txq
->q
.id
);
158 spin_lock(&txq
->lock
);
159 /* check if triggered erroneously */
160 if (txq
->q
.read_ptr
== txq
->q
.write_ptr
) {
161 spin_unlock(&txq
->lock
);
164 spin_unlock(&txq
->lock
);
166 IWL_ERR(trans
, "Queue %d stuck for %u ms.\n", txq
->q
.id
,
167 jiffies_to_msecs(trans_pcie
->wd_timeout
));
168 IWL_ERR(trans
, "Current SW read_ptr %d write_ptr %d\n",
169 txq
->q
.read_ptr
, txq
->q
.write_ptr
);
171 iwl_trans_read_mem_bytes(trans
, scd_sram_addr
, buf
, sizeof(buf
));
173 iwl_print_hex_error(trans
, buf
, sizeof(buf
));
175 for (i
= 0; i
< FH_TCSR_CHNL_NUM
; i
++)
176 IWL_ERR(trans
, "FH TRBs(%d) = 0x%08x\n", i
,
177 iwl_read_direct32(trans
, FH_TX_TRB_REG(i
)));
179 for (i
= 0; i
< trans
->cfg
->base_params
->num_of_queues
; i
++) {
180 u32 status
= iwl_read_prph(trans
, SCD_QUEUE_STATUS_BITS(i
));
181 u8 fifo
= (status
>> SCD_QUEUE_STTS_REG_POS_TXF
) & 0x7;
182 bool active
= !!(status
& BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE
));
184 iwl_trans_read_mem32(trans
,
185 trans_pcie
->scd_base_addr
+
186 SCD_TRANS_TBL_OFFSET_QUEUE(i
));
189 tbl_dw
= (tbl_dw
& 0xFFFF0000) >> 16;
191 tbl_dw
= tbl_dw
& 0x0000FFFF;
194 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
195 i
, active
? "" : "in", fifo
, tbl_dw
,
196 iwl_read_prph(trans
, SCD_QUEUE_RDPTR(i
)) &
197 (TFD_QUEUE_SIZE_MAX
- 1),
198 iwl_read_prph(trans
, SCD_QUEUE_WRPTR(i
)));
201 for (i
= q
->read_ptr
; i
!= q
->write_ptr
;
202 i
= iwl_queue_inc_wrap(i
))
203 IWL_ERR(trans
, "scratch %d = 0x%08x\n", i
,
204 le32_to_cpu(txq
->scratchbufs
[i
].scratch
));
206 iwl_force_nmi(trans
);
210 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
212 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans
*trans
,
213 struct iwl_txq
*txq
, u16 byte_cnt
)
215 struct iwlagn_scd_bc_tbl
*scd_bc_tbl
;
216 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
217 int write_ptr
= txq
->q
.write_ptr
;
218 int txq_id
= txq
->q
.id
;
221 u16 len
= byte_cnt
+ IWL_TX_CRC_SIZE
+ IWL_TX_DELIMITER_SIZE
;
223 struct iwl_tx_cmd
*tx_cmd
=
224 (void *) txq
->entries
[txq
->q
.write_ptr
].cmd
->payload
;
226 scd_bc_tbl
= trans_pcie
->scd_bc_tbls
.addr
;
228 WARN_ON(len
> 0xFFF || write_ptr
>= TFD_QUEUE_SIZE_MAX
);
230 sta_id
= tx_cmd
->sta_id
;
231 sec_ctl
= tx_cmd
->sec_ctl
;
233 switch (sec_ctl
& TX_CMD_SEC_MSK
) {
235 len
+= IEEE80211_CCMP_MIC_LEN
;
237 case TX_CMD_SEC_TKIP
:
238 len
+= IEEE80211_TKIP_ICV_LEN
;
241 len
+= IEEE80211_WEP_IV_LEN
+ IEEE80211_WEP_ICV_LEN
;
245 if (trans_pcie
->bc_table_dword
)
246 len
= DIV_ROUND_UP(len
, 4);
248 bc_ent
= cpu_to_le16(len
| (sta_id
<< 12));
250 scd_bc_tbl
[txq_id
].tfd_offset
[write_ptr
] = bc_ent
;
252 if (write_ptr
< TFD_QUEUE_SIZE_BC_DUP
)
254 tfd_offset
[TFD_QUEUE_SIZE_MAX
+ write_ptr
] = bc_ent
;
257 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans
*trans
,
260 struct iwl_trans_pcie
*trans_pcie
=
261 IWL_TRANS_GET_PCIE_TRANS(trans
);
262 struct iwlagn_scd_bc_tbl
*scd_bc_tbl
= trans_pcie
->scd_bc_tbls
.addr
;
263 int txq_id
= txq
->q
.id
;
264 int read_ptr
= txq
->q
.read_ptr
;
267 struct iwl_tx_cmd
*tx_cmd
=
268 (void *)txq
->entries
[txq
->q
.read_ptr
].cmd
->payload
;
270 WARN_ON(read_ptr
>= TFD_QUEUE_SIZE_MAX
);
272 if (txq_id
!= trans_pcie
->cmd_queue
)
273 sta_id
= tx_cmd
->sta_id
;
275 bc_ent
= cpu_to_le16(1 | (sta_id
<< 12));
276 scd_bc_tbl
[txq_id
].tfd_offset
[read_ptr
] = bc_ent
;
278 if (read_ptr
< TFD_QUEUE_SIZE_BC_DUP
)
280 tfd_offset
[TFD_QUEUE_SIZE_MAX
+ read_ptr
] = bc_ent
;
284 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
286 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans
*trans
,
289 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
291 int txq_id
= txq
->q
.id
;
293 lockdep_assert_held(&txq
->lock
);
296 * explicitly wake up the NIC if:
297 * 1. shadow registers aren't enabled
298 * 2. NIC is woken up for CMD regardless of shadow outside this function
299 * 3. there is a chance that the NIC is asleep
301 if (!trans
->cfg
->base_params
->shadow_reg_enable
&&
302 txq_id
!= trans_pcie
->cmd_queue
&&
303 test_bit(STATUS_TPOWER_PMI
, &trans
->status
)) {
305 * wake up nic if it's powered down ...
306 * uCode will wake up, and interrupt us again, so next
307 * time we'll skip this part.
309 reg
= iwl_read32(trans
, CSR_UCODE_DRV_GP1
);
311 if (reg
& CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP
) {
312 IWL_DEBUG_INFO(trans
, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
314 iwl_set_bit(trans
, CSR_GP_CNTRL
,
315 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
316 txq
->need_update
= true;
322 * if not in power-save mode, uCode will never sleep when we're
323 * trying to tx (during RFKILL, we're not trying to tx).
325 IWL_DEBUG_TX(trans
, "Q:%d WR: 0x%x\n", txq_id
, txq
->q
.write_ptr
);
326 iwl_write32(trans
, HBUS_TARG_WRPTR
, txq
->q
.write_ptr
| (txq_id
<< 8));
329 void iwl_pcie_txq_check_wrptrs(struct iwl_trans
*trans
)
331 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
334 for (i
= 0; i
< trans
->cfg
->base_params
->num_of_queues
; i
++) {
335 struct iwl_txq
*txq
= &trans_pcie
->txq
[i
];
337 spin_lock_bh(&txq
->lock
);
338 if (trans_pcie
->txq
[i
].need_update
) {
339 iwl_pcie_txq_inc_wr_ptr(trans
, txq
);
340 trans_pcie
->txq
[i
].need_update
= false;
342 spin_unlock_bh(&txq
->lock
);
346 static inline dma_addr_t
iwl_pcie_tfd_tb_get_addr(struct iwl_tfd
*tfd
, u8 idx
)
348 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
350 dma_addr_t addr
= get_unaligned_le32(&tb
->lo
);
351 if (sizeof(dma_addr_t
) > sizeof(u32
))
353 ((dma_addr_t
)(le16_to_cpu(tb
->hi_n_len
) & 0xF) << 16) << 16;
358 static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd
*tfd
, u8 idx
,
359 dma_addr_t addr
, u16 len
)
361 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
362 u16 hi_n_len
= len
<< 4;
364 put_unaligned_le32(addr
, &tb
->lo
);
365 if (sizeof(dma_addr_t
) > sizeof(u32
))
366 hi_n_len
|= ((addr
>> 16) >> 16) & 0xF;
368 tb
->hi_n_len
= cpu_to_le16(hi_n_len
);
370 tfd
->num_tbs
= idx
+ 1;
373 static inline u8
iwl_pcie_tfd_get_num_tbs(struct iwl_tfd
*tfd
)
375 return tfd
->num_tbs
& 0x1f;
378 static void iwl_pcie_tfd_unmap(struct iwl_trans
*trans
,
379 struct iwl_cmd_meta
*meta
,
385 /* Sanity check on number of chunks */
386 num_tbs
= iwl_pcie_tfd_get_num_tbs(tfd
);
388 if (num_tbs
>= IWL_NUM_OF_TBS
) {
389 IWL_ERR(trans
, "Too many chunks: %i\n", num_tbs
);
390 /* @todo issue fatal error, it is quite serious situation */
394 /* first TB is never freed - it's the scratchbuf data */
396 for (i
= 1; i
< num_tbs
; i
++)
397 dma_unmap_single(trans
->dev
, iwl_pcie_tfd_tb_get_addr(tfd
, i
),
398 iwl_pcie_tfd_tb_get_len(tfd
, i
),
405 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
406 * @trans - transport private data
408 * @dma_dir - the direction of the DMA mapping
410 * Does NOT advance any TFD circular buffer read/write indexes
411 * Does NOT free the TFD itself (which is within circular buffer)
413 static void iwl_pcie_txq_free_tfd(struct iwl_trans
*trans
, struct iwl_txq
*txq
)
415 struct iwl_tfd
*tfd_tmp
= txq
->tfds
;
417 /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
418 * idx is bounded by n_window
420 int rd_ptr
= txq
->q
.read_ptr
;
421 int idx
= get_cmd_index(&txq
->q
, rd_ptr
);
423 lockdep_assert_held(&txq
->lock
);
425 /* We have only q->n_window txq->entries, but we use
426 * TFD_QUEUE_SIZE_MAX tfds
428 iwl_pcie_tfd_unmap(trans
, &txq
->entries
[idx
].meta
, &tfd_tmp
[rd_ptr
]);
434 skb
= txq
->entries
[idx
].skb
;
436 /* Can be called from irqs-disabled context
437 * If skb is not NULL, it means that the whole queue is being
438 * freed and that the queue is not empty - free the skb
441 iwl_op_mode_free_skb(trans
->op_mode
, skb
);
442 txq
->entries
[idx
].skb
= NULL
;
447 static int iwl_pcie_txq_build_tfd(struct iwl_trans
*trans
, struct iwl_txq
*txq
,
448 dma_addr_t addr
, u16 len
, bool reset
)
451 struct iwl_tfd
*tfd
, *tfd_tmp
;
456 tfd
= &tfd_tmp
[q
->write_ptr
];
459 memset(tfd
, 0, sizeof(*tfd
));
461 num_tbs
= iwl_pcie_tfd_get_num_tbs(tfd
);
463 /* Each TFD can point to a maximum 20 Tx buffers */
464 if (num_tbs
>= IWL_NUM_OF_TBS
) {
465 IWL_ERR(trans
, "Error can not send more than %d chunks\n",
470 if (WARN(addr
& ~IWL_TX_DMA_MASK
,
471 "Unaligned address = %llx\n", (unsigned long long)addr
))
474 iwl_pcie_tfd_set_tb(tfd
, num_tbs
, addr
, len
);
479 static int iwl_pcie_txq_alloc(struct iwl_trans
*trans
,
480 struct iwl_txq
*txq
, int slots_num
,
483 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
484 size_t tfd_sz
= sizeof(struct iwl_tfd
) * TFD_QUEUE_SIZE_MAX
;
485 size_t scratchbuf_sz
;
488 if (WARN_ON(txq
->entries
|| txq
->tfds
))
491 setup_timer(&txq
->stuck_timer
, iwl_pcie_txq_stuck_timer
,
493 txq
->trans_pcie
= trans_pcie
;
495 txq
->q
.n_window
= slots_num
;
497 txq
->entries
= kcalloc(slots_num
,
498 sizeof(struct iwl_pcie_txq_entry
),
504 if (txq_id
== trans_pcie
->cmd_queue
)
505 for (i
= 0; i
< slots_num
; i
++) {
506 txq
->entries
[i
].cmd
=
507 kmalloc(sizeof(struct iwl_device_cmd
),
509 if (!txq
->entries
[i
].cmd
)
513 /* Circular buffer of transmit frame descriptors (TFDs),
514 * shared with device */
515 txq
->tfds
= dma_alloc_coherent(trans
->dev
, tfd_sz
,
516 &txq
->q
.dma_addr
, GFP_KERNEL
);
520 BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE
!= sizeof(*txq
->scratchbufs
));
521 BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf
, scratch
) !=
522 sizeof(struct iwl_cmd_header
) +
523 offsetof(struct iwl_tx_cmd
, scratch
));
525 scratchbuf_sz
= sizeof(*txq
->scratchbufs
) * slots_num
;
527 txq
->scratchbufs
= dma_alloc_coherent(trans
->dev
, scratchbuf_sz
,
528 &txq
->scratchbufs_dma
,
530 if (!txq
->scratchbufs
)
537 dma_free_coherent(trans
->dev
, tfd_sz
, txq
->tfds
, txq
->q
.dma_addr
);
539 if (txq
->entries
&& txq_id
== trans_pcie
->cmd_queue
)
540 for (i
= 0; i
< slots_num
; i
++)
541 kfree(txq
->entries
[i
].cmd
);
549 static int iwl_pcie_txq_init(struct iwl_trans
*trans
, struct iwl_txq
*txq
,
550 int slots_num
, u32 txq_id
)
554 txq
->need_update
= false;
556 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
557 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
558 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX
& (TFD_QUEUE_SIZE_MAX
- 1));
560 /* Initialize queue's high/low-water marks, and head/tail indexes */
561 ret
= iwl_queue_init(&txq
->q
, slots_num
, txq_id
);
565 spin_lock_init(&txq
->lock
);
568 * Tell nic where to find circular buffer of Tx Frame Descriptors for
569 * given Tx queue, and enable the DMA channel used for that queue.
570 * Circular buffer (TFD queue in DRAM) physical base address */
571 iwl_write_direct32(trans
, FH_MEM_CBBC_QUEUE(txq_id
),
572 txq
->q
.dma_addr
>> 8);
578 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's
580 static void iwl_pcie_txq_unmap(struct iwl_trans
*trans
, int txq_id
)
582 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
583 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
584 struct iwl_queue
*q
= &txq
->q
;
586 spin_lock_bh(&txq
->lock
);
587 while (q
->write_ptr
!= q
->read_ptr
) {
588 IWL_DEBUG_TX_REPLY(trans
, "Q %d Free %d\n",
589 txq_id
, q
->read_ptr
);
590 iwl_pcie_txq_free_tfd(trans
, txq
);
591 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
);
594 spin_unlock_bh(&txq
->lock
);
596 /* just in case - this queue may have been stopped */
597 iwl_wake_queue(trans
, txq
);
601 * iwl_pcie_txq_free - Deallocate DMA queue.
602 * @txq: Transmit queue to deallocate.
604 * Empty queue by removing and destroying all BD's.
606 * 0-fill, but do not free "txq" descriptor structure.
608 static void iwl_pcie_txq_free(struct iwl_trans
*trans
, int txq_id
)
610 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
611 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
612 struct device
*dev
= trans
->dev
;
618 iwl_pcie_txq_unmap(trans
, txq_id
);
620 /* De-alloc array of command/tx buffers */
621 if (txq_id
== trans_pcie
->cmd_queue
)
622 for (i
= 0; i
< txq
->q
.n_window
; i
++) {
623 kfree(txq
->entries
[i
].cmd
);
624 kfree(txq
->entries
[i
].free_buf
);
627 /* De-alloc circular buffer of TFDs */
629 dma_free_coherent(dev
,
630 sizeof(struct iwl_tfd
) * TFD_QUEUE_SIZE_MAX
,
631 txq
->tfds
, txq
->q
.dma_addr
);
635 dma_free_coherent(dev
,
636 sizeof(*txq
->scratchbufs
) * txq
->q
.n_window
,
637 txq
->scratchbufs
, txq
->scratchbufs_dma
);
643 del_timer_sync(&txq
->stuck_timer
);
645 /* 0-fill queue descriptor structure */
646 memset(txq
, 0, sizeof(*txq
));
649 void iwl_pcie_tx_start(struct iwl_trans
*trans
, u32 scd_base_addr
)
651 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
652 int nq
= trans
->cfg
->base_params
->num_of_queues
;
655 int clear_dwords
= (SCD_TRANS_TBL_OFFSET_QUEUE(nq
) -
656 SCD_CONTEXT_MEM_LOWER_BOUND
) / sizeof(u32
);
658 /* make sure all queue are not stopped/used */
659 memset(trans_pcie
->queue_stopped
, 0, sizeof(trans_pcie
->queue_stopped
));
660 memset(trans_pcie
->queue_used
, 0, sizeof(trans_pcie
->queue_used
));
662 trans_pcie
->scd_base_addr
=
663 iwl_read_prph(trans
, SCD_SRAM_BASE_ADDR
);
665 WARN_ON(scd_base_addr
!= 0 &&
666 scd_base_addr
!= trans_pcie
->scd_base_addr
);
668 /* reset context data, TX status and translation data */
669 iwl_trans_write_mem(trans
, trans_pcie
->scd_base_addr
+
670 SCD_CONTEXT_MEM_LOWER_BOUND
,
673 iwl_write_prph(trans
, SCD_DRAM_BASE_ADDR
,
674 trans_pcie
->scd_bc_tbls
.dma
>> 10);
676 /* The chain extension of the SCD doesn't work well. This feature is
677 * enabled by default by the HW, so we need to disable it manually.
679 if (trans
->cfg
->base_params
->scd_chain_ext_wa
)
680 iwl_write_prph(trans
, SCD_CHAINEXT_EN
, 0);
682 iwl_trans_ac_txq_enable(trans
, trans_pcie
->cmd_queue
,
683 trans_pcie
->cmd_fifo
);
685 /* Activate all Tx DMA/FIFO channels */
686 iwl_scd_activate_fifos(trans
);
688 /* Enable DMA channel */
689 for (chan
= 0; chan
< FH_TCSR_CHNL_NUM
; chan
++)
690 iwl_write_direct32(trans
, FH_TCSR_CHNL_TX_CONFIG_REG(chan
),
691 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
692 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE
);
694 /* Update FH chicken bits */
695 reg_val
= iwl_read_direct32(trans
, FH_TX_CHICKEN_BITS_REG
);
696 iwl_write_direct32(trans
, FH_TX_CHICKEN_BITS_REG
,
697 reg_val
| FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN
);
699 /* Enable L1-Active */
700 if (trans
->cfg
->device_family
!= IWL_DEVICE_FAMILY_8000
)
701 iwl_clear_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
702 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
705 void iwl_trans_pcie_tx_reset(struct iwl_trans
*trans
)
707 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
710 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
712 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
714 iwl_write_direct32(trans
, FH_MEM_CBBC_QUEUE(txq_id
),
715 txq
->q
.dma_addr
>> 8);
716 iwl_pcie_txq_unmap(trans
, txq_id
);
718 txq
->q
.write_ptr
= 0;
721 /* Tell NIC where to find the "keep warm" buffer */
722 iwl_write_direct32(trans
, FH_KW_MEM_ADDR_REG
,
723 trans_pcie
->kw
.dma
>> 4);
725 iwl_pcie_tx_start(trans
, trans_pcie
->scd_base_addr
);
729 * iwl_pcie_tx_stop - Stop all Tx DMA channels
731 int iwl_pcie_tx_stop(struct iwl_trans
*trans
)
733 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
736 /* Turn off all Tx DMA fifos */
737 spin_lock(&trans_pcie
->irq_lock
);
739 iwl_scd_deactivate_fifos(trans
);
741 /* Stop each Tx DMA channel, and wait for it to be idle */
742 for (ch
= 0; ch
< FH_TCSR_CHNL_NUM
; ch
++) {
743 iwl_write_direct32(trans
,
744 FH_TCSR_CHNL_TX_CONFIG_REG(ch
), 0x0);
745 ret
= iwl_poll_direct_bit(trans
, FH_TSSR_TX_STATUS_REG
,
746 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch
), 1000);
749 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
751 iwl_read_direct32(trans
,
752 FH_TSSR_TX_STATUS_REG
));
754 spin_unlock(&trans_pcie
->irq_lock
);
757 * This function can be called before the op_mode disabled the
758 * queues. This happens when we have an rfkill interrupt.
759 * Since we stop Tx altogether - mark the queues as stopped.
761 memset(trans_pcie
->queue_stopped
, 0, sizeof(trans_pcie
->queue_stopped
));
762 memset(trans_pcie
->queue_used
, 0, sizeof(trans_pcie
->queue_used
));
764 /* This can happen: start_hw, stop_device */
765 if (!trans_pcie
->txq
)
768 /* Unmap DMA from host system and free skb's */
769 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
771 iwl_pcie_txq_unmap(trans
, txq_id
);
777 * iwl_trans_tx_free - Free TXQ Context
779 * Destroy all TX DMA queues and structures
781 void iwl_pcie_tx_free(struct iwl_trans
*trans
)
784 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
787 if (trans_pcie
->txq
) {
789 txq_id
< trans
->cfg
->base_params
->num_of_queues
; txq_id
++)
790 iwl_pcie_txq_free(trans
, txq_id
);
793 kfree(trans_pcie
->txq
);
794 trans_pcie
->txq
= NULL
;
796 iwl_pcie_free_dma_ptr(trans
, &trans_pcie
->kw
);
798 iwl_pcie_free_dma_ptr(trans
, &trans_pcie
->scd_bc_tbls
);
802 * iwl_pcie_tx_alloc - allocate TX context
803 * Allocate all Tx DMA structures and initialize them
805 static int iwl_pcie_tx_alloc(struct iwl_trans
*trans
)
808 int txq_id
, slots_num
;
809 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
811 u16 scd_bc_tbls_size
= trans
->cfg
->base_params
->num_of_queues
*
812 sizeof(struct iwlagn_scd_bc_tbl
);
814 /*It is not allowed to alloc twice, so warn when this happens.
815 * We cannot rely on the previous allocation, so free and fail */
816 if (WARN_ON(trans_pcie
->txq
)) {
821 ret
= iwl_pcie_alloc_dma_ptr(trans
, &trans_pcie
->scd_bc_tbls
,
824 IWL_ERR(trans
, "Scheduler BC Table allocation failed\n");
828 /* Alloc keep-warm buffer */
829 ret
= iwl_pcie_alloc_dma_ptr(trans
, &trans_pcie
->kw
, IWL_KW_SIZE
);
831 IWL_ERR(trans
, "Keep Warm allocation failed\n");
835 trans_pcie
->txq
= kcalloc(trans
->cfg
->base_params
->num_of_queues
,
836 sizeof(struct iwl_txq
), GFP_KERNEL
);
837 if (!trans_pcie
->txq
) {
838 IWL_ERR(trans
, "Not enough memory for txq\n");
843 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
844 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
846 slots_num
= (txq_id
== trans_pcie
->cmd_queue
) ?
847 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
848 ret
= iwl_pcie_txq_alloc(trans
, &trans_pcie
->txq
[txq_id
],
851 IWL_ERR(trans
, "Tx %d queue alloc failed\n", txq_id
);
859 iwl_pcie_tx_free(trans
);
863 int iwl_pcie_tx_init(struct iwl_trans
*trans
)
865 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
867 int txq_id
, slots_num
;
870 if (!trans_pcie
->txq
) {
871 ret
= iwl_pcie_tx_alloc(trans
);
877 spin_lock(&trans_pcie
->irq_lock
);
879 /* Turn off all Tx DMA fifos */
880 iwl_scd_deactivate_fifos(trans
);
882 /* Tell NIC where to find the "keep warm" buffer */
883 iwl_write_direct32(trans
, FH_KW_MEM_ADDR_REG
,
884 trans_pcie
->kw
.dma
>> 4);
886 spin_unlock(&trans_pcie
->irq_lock
);
888 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
889 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
891 slots_num
= (txq_id
== trans_pcie
->cmd_queue
) ?
892 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
893 ret
= iwl_pcie_txq_init(trans
, &trans_pcie
->txq
[txq_id
],
896 IWL_ERR(trans
, "Tx %d queue init failed\n", txq_id
);
903 /*Upon error, free only if we allocated something */
905 iwl_pcie_tx_free(trans
);
909 static inline void iwl_pcie_txq_progress(struct iwl_trans_pcie
*trans_pcie
,
912 if (!trans_pcie
->wd_timeout
)
916 * if empty delete timer, otherwise move timer forward
917 * since we're making progress on this queue
919 if (txq
->q
.read_ptr
== txq
->q
.write_ptr
)
920 del_timer(&txq
->stuck_timer
);
922 mod_timer(&txq
->stuck_timer
, jiffies
+ trans_pcie
->wd_timeout
);
925 /* Frees buffers until index _not_ inclusive */
926 void iwl_trans_pcie_reclaim(struct iwl_trans
*trans
, int txq_id
, int ssn
,
927 struct sk_buff_head
*skbs
)
929 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
930 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
931 int tfd_num
= ssn
& (TFD_QUEUE_SIZE_MAX
- 1);
932 struct iwl_queue
*q
= &txq
->q
;
935 /* This function is not meant to release cmd queue*/
936 if (WARN_ON(txq_id
== trans_pcie
->cmd_queue
))
939 spin_lock_bh(&txq
->lock
);
942 IWL_DEBUG_TX_QUEUES(trans
, "Q %d inactive - ignoring idx %d\n",
947 if (txq
->q
.read_ptr
== tfd_num
)
950 IWL_DEBUG_TX_REPLY(trans
, "[Q %d] %d -> %d (%d)\n",
951 txq_id
, txq
->q
.read_ptr
, tfd_num
, ssn
);
953 /*Since we free until index _not_ inclusive, the one before index is
954 * the last we will free. This one must be used */
955 last_to_free
= iwl_queue_dec_wrap(tfd_num
);
957 if (!iwl_queue_used(q
, last_to_free
)) {
959 "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
960 __func__
, txq_id
, last_to_free
, TFD_QUEUE_SIZE_MAX
,
961 q
->write_ptr
, q
->read_ptr
);
965 if (WARN_ON(!skb_queue_empty(skbs
)))
969 q
->read_ptr
!= tfd_num
;
970 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
)) {
972 if (WARN_ON_ONCE(txq
->entries
[txq
->q
.read_ptr
].skb
== NULL
))
975 __skb_queue_tail(skbs
, txq
->entries
[txq
->q
.read_ptr
].skb
);
977 txq
->entries
[txq
->q
.read_ptr
].skb
= NULL
;
979 iwl_pcie_txq_inval_byte_cnt_tbl(trans
, txq
);
981 iwl_pcie_txq_free_tfd(trans
, txq
);
984 iwl_pcie_txq_progress(trans_pcie
, txq
);
986 if (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
)
987 iwl_wake_queue(trans
, txq
);
989 spin_unlock_bh(&txq
->lock
);
993 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
995 * When FW advances 'R' index, all entries between old and new 'R' index
996 * need to be reclaimed. As result, some free space forms. If there is
997 * enough free space (> low mark), wake the stack that feeds us.
999 static void iwl_pcie_cmdq_reclaim(struct iwl_trans
*trans
, int txq_id
, int idx
)
1001 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1002 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
1003 struct iwl_queue
*q
= &txq
->q
;
1004 unsigned long flags
;
1007 lockdep_assert_held(&txq
->lock
);
1009 if ((idx
>= TFD_QUEUE_SIZE_MAX
) || (!iwl_queue_used(q
, idx
))) {
1011 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1012 __func__
, txq_id
, idx
, TFD_QUEUE_SIZE_MAX
,
1013 q
->write_ptr
, q
->read_ptr
);
1017 for (idx
= iwl_queue_inc_wrap(idx
); q
->read_ptr
!= idx
;
1018 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
)) {
1021 IWL_ERR(trans
, "HCMD skipped: index (%d) %d %d\n",
1022 idx
, q
->write_ptr
, q
->read_ptr
);
1023 iwl_force_nmi(trans
);
1027 if (trans
->cfg
->base_params
->apmg_wake_up_wa
&&
1028 q
->read_ptr
== q
->write_ptr
) {
1029 spin_lock_irqsave(&trans_pcie
->reg_lock
, flags
);
1030 WARN_ON(!trans_pcie
->cmd_in_flight
);
1031 trans_pcie
->cmd_in_flight
= false;
1032 __iwl_trans_pcie_clear_bit(trans
,
1034 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1035 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, flags
);
1038 iwl_pcie_txq_progress(trans_pcie
, txq
);
1041 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans
*trans
, u16 ra_tid
,
1044 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1049 scd_q2ratid
= ra_tid
& SCD_QUEUE_RA_TID_MAP_RATID_MSK
;
1051 tbl_dw_addr
= trans_pcie
->scd_base_addr
+
1052 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id
);
1054 tbl_dw
= iwl_trans_read_mem32(trans
, tbl_dw_addr
);
1057 tbl_dw
= (scd_q2ratid
<< 16) | (tbl_dw
& 0x0000FFFF);
1059 tbl_dw
= scd_q2ratid
| (tbl_dw
& 0xFFFF0000);
1061 iwl_trans_write_mem32(trans
, tbl_dw_addr
, tbl_dw
);
1066 /* Receiver address (actually, Rx station's index into station table),
1067 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1068 #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
1070 void iwl_trans_pcie_txq_enable(struct iwl_trans
*trans
, int txq_id
, u16 ssn
,
1071 const struct iwl_trans_txq_scd_cfg
*cfg
)
1073 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1076 if (test_and_set_bit(txq_id
, trans_pcie
->queue_used
))
1077 WARN_ONCE(1, "queue %d already used - expect issues", txq_id
);
1082 /* Disable the scheduler prior configuring the cmd queue */
1083 if (txq_id
== trans_pcie
->cmd_queue
)
1084 iwl_scd_enable_set_active(trans
, 0);
1086 /* Stop this Tx queue before configuring it */
1087 iwl_scd_txq_set_inactive(trans
, txq_id
);
1089 /* Set this queue as a chain-building queue unless it is CMD */
1090 if (txq_id
!= trans_pcie
->cmd_queue
)
1091 iwl_scd_txq_set_chain(trans
, txq_id
);
1093 if (cfg
->aggregate
) {
1094 u16 ra_tid
= BUILD_RAxTID(cfg
->sta_id
, cfg
->tid
);
1096 /* Map receiver-address / traffic-ID to this queue */
1097 iwl_pcie_txq_set_ratid_map(trans
, ra_tid
, txq_id
);
1099 /* enable aggregations for the queue */
1100 iwl_scd_txq_enable_agg(trans
, txq_id
);
1101 trans_pcie
->txq
[txq_id
].ampdu
= true;
1104 * disable aggregations for the queue, this will also
1105 * make the ra_tid mapping configuration irrelevant
1106 * since it is now a non-AGG queue.
1108 iwl_scd_txq_disable_agg(trans
, txq_id
);
1110 ssn
= trans_pcie
->txq
[txq_id
].q
.read_ptr
;
1114 /* Place first TFD at index corresponding to start sequence number.
1115 * Assumes that ssn_idx is valid (!= 0xFFF) */
1116 trans_pcie
->txq
[txq_id
].q
.read_ptr
= (ssn
& 0xff);
1117 trans_pcie
->txq
[txq_id
].q
.write_ptr
= (ssn
& 0xff);
1120 u8 frame_limit
= cfg
->frame_limit
;
1122 iwl_write_direct32(trans
, HBUS_TARG_WRPTR
,
1123 (ssn
& 0xff) | (txq_id
<< 8));
1124 iwl_write_prph(trans
, SCD_QUEUE_RDPTR(txq_id
), ssn
);
1126 /* Set up Tx window size and frame limit for this queue */
1127 iwl_trans_write_mem32(trans
, trans_pcie
->scd_base_addr
+
1128 SCD_CONTEXT_QUEUE_OFFSET(txq_id
), 0);
1129 iwl_trans_write_mem32(trans
,
1130 trans_pcie
->scd_base_addr
+
1131 SCD_CONTEXT_QUEUE_OFFSET(txq_id
) + sizeof(u32
),
1132 ((frame_limit
<< SCD_QUEUE_CTX_REG2_WIN_SIZE_POS
) &
1133 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK
) |
1134 ((frame_limit
<< SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS
) &
1135 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK
));
1137 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
1138 iwl_write_prph(trans
, SCD_QUEUE_STATUS_BITS(txq_id
),
1139 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE
) |
1140 (cfg
->fifo
<< SCD_QUEUE_STTS_REG_POS_TXF
) |
1141 (1 << SCD_QUEUE_STTS_REG_POS_WSL
) |
1142 SCD_QUEUE_STTS_REG_MSK
);
1144 /* enable the scheduler for this queue (only) */
1145 if (txq_id
== trans_pcie
->cmd_queue
)
1146 iwl_scd_enable_set_active(trans
, BIT(txq_id
));
1149 trans_pcie
->txq
[txq_id
].active
= true;
1150 IWL_DEBUG_TX_QUEUES(trans
, "Activate queue %d on FIFO %d WrPtr: %d\n",
1151 txq_id
, fifo
, ssn
& 0xff);
1154 void iwl_trans_pcie_txq_disable(struct iwl_trans
*trans
, int txq_id
,
1157 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1158 u32 stts_addr
= trans_pcie
->scd_base_addr
+
1159 SCD_TX_STTS_QUEUE_OFFSET(txq_id
);
1160 static const u32 zero_val
[4] = {};
1163 * Upon HW Rfkill - we stop the device, and then stop the queues
1164 * in the op_mode. Just for the sake of the simplicity of the op_mode,
1165 * allow the op_mode to call txq_disable after it already called
1168 if (!test_and_clear_bit(txq_id
, trans_pcie
->queue_used
)) {
1169 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED
, &trans
->status
),
1170 "queue %d not used", txq_id
);
1174 if (configure_scd
) {
1175 iwl_scd_txq_set_inactive(trans
, txq_id
);
1177 iwl_trans_write_mem(trans
, stts_addr
, (void *)zero_val
,
1178 ARRAY_SIZE(zero_val
));
1181 iwl_pcie_txq_unmap(trans
, txq_id
);
1182 trans_pcie
->txq
[txq_id
].ampdu
= false;
1184 IWL_DEBUG_TX_QUEUES(trans
, "Deactivate queue %d\n", txq_id
);
1187 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1190 * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1191 * @priv: device private data point
1192 * @cmd: a pointer to the ucode command structure
1194 * The function returns < 0 values to indicate the operation
1195 * failed. On success, it returns the index (>= 0) of command in the
1198 static int iwl_pcie_enqueue_hcmd(struct iwl_trans
*trans
,
1199 struct iwl_host_cmd
*cmd
)
1201 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1202 struct iwl_txq
*txq
= &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
1203 struct iwl_queue
*q
= &txq
->q
;
1204 struct iwl_device_cmd
*out_cmd
;
1205 struct iwl_cmd_meta
*out_meta
;
1206 unsigned long flags
;
1207 void *dup_buf
= NULL
;
1208 dma_addr_t phys_addr
;
1210 u16 copy_size
, cmd_size
, scratch_size
;
1211 bool had_nocopy
= false;
1214 const u8
*cmddata
[IWL_MAX_CMD_TBS_PER_TFD
];
1215 u16 cmdlen
[IWL_MAX_CMD_TBS_PER_TFD
];
1217 copy_size
= sizeof(out_cmd
->hdr
);
1218 cmd_size
= sizeof(out_cmd
->hdr
);
1220 /* need one for the header if the first is NOCOPY */
1221 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD
> IWL_NUM_OF_TBS
- 1);
1223 for (i
= 0; i
< IWL_MAX_CMD_TBS_PER_TFD
; i
++) {
1224 cmddata
[i
] = cmd
->data
[i
];
1225 cmdlen
[i
] = cmd
->len
[i
];
1230 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1231 if (copy_size
< IWL_HCMD_SCRATCHBUF_SIZE
) {
1232 int copy
= IWL_HCMD_SCRATCHBUF_SIZE
- copy_size
;
1234 if (copy
> cmdlen
[i
])
1241 if (cmd
->dataflags
[i
] & IWL_HCMD_DFL_NOCOPY
) {
1243 if (WARN_ON(cmd
->dataflags
[i
] & IWL_HCMD_DFL_DUP
)) {
1247 } else if (cmd
->dataflags
[i
] & IWL_HCMD_DFL_DUP
) {
1249 * This is also a chunk that isn't copied
1250 * to the static buffer so set had_nocopy.
1254 /* only allowed once */
1255 if (WARN_ON(dup_buf
)) {
1260 dup_buf
= kmemdup(cmddata
[i
], cmdlen
[i
],
1265 /* NOCOPY must not be followed by normal! */
1266 if (WARN_ON(had_nocopy
)) {
1270 copy_size
+= cmdlen
[i
];
1272 cmd_size
+= cmd
->len
[i
];
1276 * If any of the command structures end up being larger than
1277 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1278 * allocated into separate TFDs, then we will need to
1279 * increase the size of the buffers.
1281 if (WARN(copy_size
> TFD_MAX_PAYLOAD_SIZE
,
1282 "Command %s (%#x) is too large (%d bytes)\n",
1283 get_cmd_string(trans_pcie
, cmd
->id
), cmd
->id
, copy_size
)) {
1288 spin_lock_bh(&txq
->lock
);
1290 if (iwl_queue_space(q
) < ((cmd
->flags
& CMD_ASYNC
) ? 2 : 1)) {
1291 spin_unlock_bh(&txq
->lock
);
1293 IWL_ERR(trans
, "No space in command queue\n");
1294 iwl_op_mode_cmd_queue_full(trans
->op_mode
);
1299 idx
= get_cmd_index(q
, q
->write_ptr
);
1300 out_cmd
= txq
->entries
[idx
].cmd
;
1301 out_meta
= &txq
->entries
[idx
].meta
;
1303 memset(out_meta
, 0, sizeof(*out_meta
)); /* re-initialize to NULL */
1304 if (cmd
->flags
& CMD_WANT_SKB
)
1305 out_meta
->source
= cmd
;
1307 /* set up the header */
1309 out_cmd
->hdr
.cmd
= cmd
->id
;
1310 out_cmd
->hdr
.flags
= 0;
1311 out_cmd
->hdr
.sequence
=
1312 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie
->cmd_queue
) |
1313 INDEX_TO_SEQ(q
->write_ptr
));
1315 /* and copy the data that needs to be copied */
1316 cmd_pos
= offsetof(struct iwl_device_cmd
, payload
);
1317 copy_size
= sizeof(out_cmd
->hdr
);
1318 for (i
= 0; i
< IWL_MAX_CMD_TBS_PER_TFD
; i
++) {
1324 /* copy everything if not nocopy/dup */
1325 if (!(cmd
->dataflags
[i
] & (IWL_HCMD_DFL_NOCOPY
|
1326 IWL_HCMD_DFL_DUP
))) {
1329 memcpy((u8
*)out_cmd
+ cmd_pos
, cmd
->data
[i
], copy
);
1336 * Otherwise we need at least IWL_HCMD_SCRATCHBUF_SIZE copied
1337 * in total (for the scratchbuf handling), but copy up to what
1338 * we can fit into the payload for debug dump purposes.
1340 copy
= min_t(int, TFD_MAX_PAYLOAD_SIZE
- cmd_pos
, cmd
->len
[i
]);
1342 memcpy((u8
*)out_cmd
+ cmd_pos
, cmd
->data
[i
], copy
);
1345 /* However, treat copy_size the proper way, we need it below */
1346 if (copy_size
< IWL_HCMD_SCRATCHBUF_SIZE
) {
1347 copy
= IWL_HCMD_SCRATCHBUF_SIZE
- copy_size
;
1349 if (copy
> cmd
->len
[i
])
1356 "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1357 get_cmd_string(trans_pcie
, out_cmd
->hdr
.cmd
),
1358 out_cmd
->hdr
.cmd
, le16_to_cpu(out_cmd
->hdr
.sequence
),
1359 cmd_size
, q
->write_ptr
, idx
, trans_pcie
->cmd_queue
);
1361 /* start the TFD with the scratchbuf */
1362 scratch_size
= min_t(int, copy_size
, IWL_HCMD_SCRATCHBUF_SIZE
);
1363 memcpy(&txq
->scratchbufs
[q
->write_ptr
], &out_cmd
->hdr
, scratch_size
);
1364 iwl_pcie_txq_build_tfd(trans
, txq
,
1365 iwl_pcie_get_scratchbuf_dma(txq
, q
->write_ptr
),
1366 scratch_size
, true);
1368 /* map first command fragment, if any remains */
1369 if (copy_size
> scratch_size
) {
1370 phys_addr
= dma_map_single(trans
->dev
,
1371 ((u8
*)&out_cmd
->hdr
) + scratch_size
,
1372 copy_size
- scratch_size
,
1374 if (dma_mapping_error(trans
->dev
, phys_addr
)) {
1375 iwl_pcie_tfd_unmap(trans
, out_meta
,
1376 &txq
->tfds
[q
->write_ptr
]);
1381 iwl_pcie_txq_build_tfd(trans
, txq
, phys_addr
,
1382 copy_size
- scratch_size
, false);
1385 /* map the remaining (adjusted) nocopy/dup fragments */
1386 for (i
= 0; i
< IWL_MAX_CMD_TBS_PER_TFD
; i
++) {
1387 const void *data
= cmddata
[i
];
1391 if (!(cmd
->dataflags
[i
] & (IWL_HCMD_DFL_NOCOPY
|
1394 if (cmd
->dataflags
[i
] & IWL_HCMD_DFL_DUP
)
1396 phys_addr
= dma_map_single(trans
->dev
, (void *)data
,
1397 cmdlen
[i
], DMA_TO_DEVICE
);
1398 if (dma_mapping_error(trans
->dev
, phys_addr
)) {
1399 iwl_pcie_tfd_unmap(trans
, out_meta
,
1400 &txq
->tfds
[q
->write_ptr
]);
1405 iwl_pcie_txq_build_tfd(trans
, txq
, phys_addr
, cmdlen
[i
], false);
1408 out_meta
->flags
= cmd
->flags
;
1409 if (WARN_ON_ONCE(txq
->entries
[idx
].free_buf
))
1410 kfree(txq
->entries
[idx
].free_buf
);
1411 txq
->entries
[idx
].free_buf
= dup_buf
;
1413 trace_iwlwifi_dev_hcmd(trans
->dev
, cmd
, cmd_size
, &out_cmd
->hdr
);
1415 /* start timer if queue currently empty */
1416 if (q
->read_ptr
== q
->write_ptr
&& trans_pcie
->wd_timeout
)
1417 mod_timer(&txq
->stuck_timer
, jiffies
+ trans_pcie
->wd_timeout
);
1419 spin_lock_irqsave(&trans_pcie
->reg_lock
, flags
);
1422 * wake up the NIC to make sure that the firmware will see the host
1423 * command - we will let the NIC sleep once all the host commands
1424 * returned. This needs to be done only on NICs that have
1425 * apmg_wake_up_wa set.
1427 if (trans
->cfg
->base_params
->apmg_wake_up_wa
&&
1428 !trans_pcie
->cmd_in_flight
) {
1429 trans_pcie
->cmd_in_flight
= true;
1430 __iwl_trans_pcie_set_bit(trans
, CSR_GP_CNTRL
,
1431 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1432 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
1433 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN
,
1434 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
|
1435 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP
),
1438 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
1439 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1440 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, flags
);
1441 trans_pcie
->cmd_in_flight
= false;
1442 IWL_ERR(trans
, "Failed to wake NIC for hcmd\n");
1448 /* Increment and update queue's write index */
1449 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
);
1450 iwl_pcie_txq_inc_wr_ptr(trans
, txq
);
1452 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, flags
);
1455 spin_unlock_bh(&txq
->lock
);
1463 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1464 * @rxb: Rx buffer to reclaim
1465 * @handler_status: return value of the handler of the command
1466 * (put in setup_rx_handlers)
1468 * If an Rx buffer has an async callback associated with it the callback
1469 * will be executed. The attached skb (if present) will only be freed
1470 * if the callback returns 1
1472 void iwl_pcie_hcmd_complete(struct iwl_trans
*trans
,
1473 struct iwl_rx_cmd_buffer
*rxb
, int handler_status
)
1475 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
1476 u16 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
1477 int txq_id
= SEQ_TO_QUEUE(sequence
);
1478 int index
= SEQ_TO_INDEX(sequence
);
1480 struct iwl_device_cmd
*cmd
;
1481 struct iwl_cmd_meta
*meta
;
1482 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1483 struct iwl_txq
*txq
= &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
1485 /* If a Tx command is being handled and it isn't in the actual
1486 * command queue then there a command routing bug has been introduced
1487 * in the queue management code. */
1488 if (WARN(txq_id
!= trans_pcie
->cmd_queue
,
1489 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1490 txq_id
, trans_pcie
->cmd_queue
, sequence
,
1491 trans_pcie
->txq
[trans_pcie
->cmd_queue
].q
.read_ptr
,
1492 trans_pcie
->txq
[trans_pcie
->cmd_queue
].q
.write_ptr
)) {
1493 iwl_print_hex_error(trans
, pkt
, 32);
1497 spin_lock_bh(&txq
->lock
);
1499 cmd_index
= get_cmd_index(&txq
->q
, index
);
1500 cmd
= txq
->entries
[cmd_index
].cmd
;
1501 meta
= &txq
->entries
[cmd_index
].meta
;
1503 iwl_pcie_tfd_unmap(trans
, meta
, &txq
->tfds
[index
]);
1505 /* Input error checking is done when commands are added to queue. */
1506 if (meta
->flags
& CMD_WANT_SKB
) {
1507 struct page
*p
= rxb_steal_page(rxb
);
1509 meta
->source
->resp_pkt
= pkt
;
1510 meta
->source
->_rx_page_addr
= (unsigned long)page_address(p
);
1511 meta
->source
->_rx_page_order
= trans_pcie
->rx_page_order
;
1512 meta
->source
->handler_status
= handler_status
;
1515 iwl_pcie_cmdq_reclaim(trans
, txq_id
, index
);
1517 if (!(meta
->flags
& CMD_ASYNC
)) {
1518 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
)) {
1520 "HCMD_ACTIVE already clear for command %s\n",
1521 get_cmd_string(trans_pcie
, cmd
->hdr
.cmd
));
1523 clear_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
);
1524 IWL_DEBUG_INFO(trans
, "Clearing HCMD_ACTIVE for command %s\n",
1525 get_cmd_string(trans_pcie
, cmd
->hdr
.cmd
));
1526 wake_up(&trans_pcie
->wait_command_queue
);
1531 spin_unlock_bh(&txq
->lock
);
1534 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
1536 static int iwl_pcie_send_hcmd_async(struct iwl_trans
*trans
,
1537 struct iwl_host_cmd
*cmd
)
1539 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1542 /* An asynchronous command can not expect an SKB to be set. */
1543 if (WARN_ON(cmd
->flags
& CMD_WANT_SKB
))
1546 ret
= iwl_pcie_enqueue_hcmd(trans
, cmd
);
1549 "Error sending %s: enqueue_hcmd failed: %d\n",
1550 get_cmd_string(trans_pcie
, cmd
->id
), ret
);
1556 static int iwl_pcie_send_hcmd_sync(struct iwl_trans
*trans
,
1557 struct iwl_host_cmd
*cmd
)
1559 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1563 IWL_DEBUG_INFO(trans
, "Attempting to send sync command %s\n",
1564 get_cmd_string(trans_pcie
, cmd
->id
));
1566 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE
,
1568 "Command %s: a command is already active!\n",
1569 get_cmd_string(trans_pcie
, cmd
->id
)))
1572 IWL_DEBUG_INFO(trans
, "Setting HCMD_ACTIVE for command %s\n",
1573 get_cmd_string(trans_pcie
, cmd
->id
));
1575 cmd_idx
= iwl_pcie_enqueue_hcmd(trans
, cmd
);
1578 clear_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
);
1580 "Error sending %s: enqueue_hcmd failed: %d\n",
1581 get_cmd_string(trans_pcie
, cmd
->id
), ret
);
1585 ret
= wait_event_timeout(trans_pcie
->wait_command_queue
,
1586 !test_bit(STATUS_SYNC_HCMD_ACTIVE
,
1588 HOST_COMPLETE_TIMEOUT
);
1590 struct iwl_txq
*txq
= &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
1591 struct iwl_queue
*q
= &txq
->q
;
1593 IWL_ERR(trans
, "Error sending %s: time out after %dms.\n",
1594 get_cmd_string(trans_pcie
, cmd
->id
),
1595 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT
));
1597 IWL_ERR(trans
, "Current CMD queue read_ptr %d write_ptr %d\n",
1598 q
->read_ptr
, q
->write_ptr
);
1600 clear_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
);
1601 IWL_DEBUG_INFO(trans
, "Clearing HCMD_ACTIVE for command %s\n",
1602 get_cmd_string(trans_pcie
, cmd
->id
));
1605 iwl_force_nmi(trans
);
1606 iwl_trans_fw_error(trans
);
1611 if (test_bit(STATUS_FW_ERROR
, &trans
->status
)) {
1612 IWL_ERR(trans
, "FW error in SYNC CMD %s\n",
1613 get_cmd_string(trans_pcie
, cmd
->id
));
1619 if (!(cmd
->flags
& CMD_SEND_IN_RFKILL
) &&
1620 test_bit(STATUS_RFKILL
, &trans
->status
)) {
1621 IWL_DEBUG_RF_KILL(trans
, "RFKILL in SYNC CMD... no rsp\n");
1626 if ((cmd
->flags
& CMD_WANT_SKB
) && !cmd
->resp_pkt
) {
1627 IWL_ERR(trans
, "Error: Response NULL in '%s'\n",
1628 get_cmd_string(trans_pcie
, cmd
->id
));
1636 if (cmd
->flags
& CMD_WANT_SKB
) {
1638 * Cancel the CMD_WANT_SKB flag for the cmd in the
1639 * TX cmd queue. Otherwise in case the cmd comes
1640 * in later, it will possibly set an invalid
1641 * address (cmd->meta.source).
1643 trans_pcie
->txq
[trans_pcie
->cmd_queue
].
1644 entries
[cmd_idx
].meta
.flags
&= ~CMD_WANT_SKB
;
1647 if (cmd
->resp_pkt
) {
1649 cmd
->resp_pkt
= NULL
;
1655 int iwl_trans_pcie_send_hcmd(struct iwl_trans
*trans
, struct iwl_host_cmd
*cmd
)
1657 if (!(cmd
->flags
& CMD_SEND_IN_RFKILL
) &&
1658 test_bit(STATUS_RFKILL
, &trans
->status
)) {
1659 IWL_DEBUG_RF_KILL(trans
, "Dropping CMD 0x%x: RF KILL\n",
1664 if (cmd
->flags
& CMD_ASYNC
)
1665 return iwl_pcie_send_hcmd_async(trans
, cmd
);
1667 /* We still can fail on RFKILL that can be asserted while we wait */
1668 return iwl_pcie_send_hcmd_sync(trans
, cmd
);
1671 int iwl_trans_pcie_tx(struct iwl_trans
*trans
, struct sk_buff
*skb
,
1672 struct iwl_device_cmd
*dev_cmd
, int txq_id
)
1674 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1675 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1676 struct iwl_tx_cmd
*tx_cmd
= (struct iwl_tx_cmd
*)dev_cmd
->payload
;
1677 struct iwl_cmd_meta
*out_meta
;
1678 struct iwl_txq
*txq
;
1679 struct iwl_queue
*q
;
1680 dma_addr_t tb0_phys
, tb1_phys
, scratch_phys
;
1682 u16 len
, tb1_len
, tb2_len
;
1683 bool wait_write_ptr
;
1684 __le16 fc
= hdr
->frame_control
;
1685 u8 hdr_len
= ieee80211_hdrlen(fc
);
1688 txq
= &trans_pcie
->txq
[txq_id
];
1691 if (WARN_ONCE(!test_bit(txq_id
, trans_pcie
->queue_used
),
1692 "TX on unused queue %d\n", txq_id
))
1695 spin_lock(&txq
->lock
);
1697 /* In AGG mode, the index in the ring must correspond to the WiFi
1698 * sequence number. This is a HW requirements to help the SCD to parse
1700 * Check here that the packets are in the right place on the ring.
1702 wifi_seq
= IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr
->seq_ctrl
));
1703 WARN_ONCE(txq
->ampdu
&&
1704 (wifi_seq
& 0xff) != q
->write_ptr
,
1705 "Q: %d WiFi Seq %d tfdNum %d",
1706 txq_id
, wifi_seq
, q
->write_ptr
);
1708 /* Set up driver data for this TFD */
1709 txq
->entries
[q
->write_ptr
].skb
= skb
;
1710 txq
->entries
[q
->write_ptr
].cmd
= dev_cmd
;
1712 dev_cmd
->hdr
.sequence
=
1713 cpu_to_le16((u16
)(QUEUE_TO_SEQ(txq_id
) |
1714 INDEX_TO_SEQ(q
->write_ptr
)));
1716 tb0_phys
= iwl_pcie_get_scratchbuf_dma(txq
, q
->write_ptr
);
1717 scratch_phys
= tb0_phys
+ sizeof(struct iwl_cmd_header
) +
1718 offsetof(struct iwl_tx_cmd
, scratch
);
1720 tx_cmd
->dram_lsb_ptr
= cpu_to_le32(scratch_phys
);
1721 tx_cmd
->dram_msb_ptr
= iwl_get_dma_hi_addr(scratch_phys
);
1723 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1724 out_meta
= &txq
->entries
[q
->write_ptr
].meta
;
1727 * The second TB (tb1) points to the remainder of the TX command
1728 * and the 802.11 header - dword aligned size
1729 * (This calculation modifies the TX command, so do it before the
1730 * setup of the first TB)
1732 len
= sizeof(struct iwl_tx_cmd
) + sizeof(struct iwl_cmd_header
) +
1733 hdr_len
- IWL_HCMD_SCRATCHBUF_SIZE
;
1734 tb1_len
= ALIGN(len
, 4);
1736 /* Tell NIC about any 2-byte padding after MAC header */
1738 tx_cmd
->tx_flags
|= TX_CMD_FLG_MH_PAD_MSK
;
1740 /* The first TB points to the scratchbuf data - min_copy bytes */
1741 memcpy(&txq
->scratchbufs
[q
->write_ptr
], &dev_cmd
->hdr
,
1742 IWL_HCMD_SCRATCHBUF_SIZE
);
1743 iwl_pcie_txq_build_tfd(trans
, txq
, tb0_phys
,
1744 IWL_HCMD_SCRATCHBUF_SIZE
, true);
1746 /* there must be data left over for TB1 or this code must be changed */
1747 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd
) < IWL_HCMD_SCRATCHBUF_SIZE
);
1749 /* map the data for TB1 */
1750 tb1_addr
= ((u8
*)&dev_cmd
->hdr
) + IWL_HCMD_SCRATCHBUF_SIZE
;
1751 tb1_phys
= dma_map_single(trans
->dev
, tb1_addr
, tb1_len
, DMA_TO_DEVICE
);
1752 if (unlikely(dma_mapping_error(trans
->dev
, tb1_phys
)))
1754 iwl_pcie_txq_build_tfd(trans
, txq
, tb1_phys
, tb1_len
, false);
1757 * Set up TFD's third entry to point directly to remainder
1758 * of skb, if any (802.11 null frames have no payload).
1760 tb2_len
= skb
->len
- hdr_len
;
1762 dma_addr_t tb2_phys
= dma_map_single(trans
->dev
,
1763 skb
->data
+ hdr_len
,
1764 tb2_len
, DMA_TO_DEVICE
);
1765 if (unlikely(dma_mapping_error(trans
->dev
, tb2_phys
))) {
1766 iwl_pcie_tfd_unmap(trans
, out_meta
,
1767 &txq
->tfds
[q
->write_ptr
]);
1770 iwl_pcie_txq_build_tfd(trans
, txq
, tb2_phys
, tb2_len
, false);
1773 /* Set up entry for this TFD in Tx byte-count array */
1774 iwl_pcie_txq_update_byte_cnt_tbl(trans
, txq
, le16_to_cpu(tx_cmd
->len
));
1776 trace_iwlwifi_dev_tx(trans
->dev
, skb
,
1777 &txq
->tfds
[txq
->q
.write_ptr
],
1778 sizeof(struct iwl_tfd
),
1779 &dev_cmd
->hdr
, IWL_HCMD_SCRATCHBUF_SIZE
+ tb1_len
,
1780 skb
->data
+ hdr_len
, tb2_len
);
1781 trace_iwlwifi_dev_tx_data(trans
->dev
, skb
,
1782 skb
->data
+ hdr_len
, tb2_len
);
1784 wait_write_ptr
= ieee80211_has_morefrags(fc
);
1786 /* start timer if queue currently empty */
1787 if (txq
->need_update
&& q
->read_ptr
== q
->write_ptr
&&
1788 trans_pcie
->wd_timeout
)
1789 mod_timer(&txq
->stuck_timer
, jiffies
+ trans_pcie
->wd_timeout
);
1791 /* Tell device the write index *just past* this latest filled TFD */
1792 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
);
1793 if (!wait_write_ptr
)
1794 iwl_pcie_txq_inc_wr_ptr(trans
, txq
);
1797 * At this point the frame is "transmitted" successfully
1798 * and we will get a TX status notification eventually.
1800 if (iwl_queue_space(q
) < q
->high_mark
) {
1802 iwl_pcie_txq_inc_wr_ptr(trans
, txq
);
1804 iwl_stop_queue(trans
, txq
);
1806 spin_unlock(&txq
->lock
);
1809 spin_unlock(&txq
->lock
);