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iwlwifi: trans: configure the scheduler enable register
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / pcie / tx.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/slab.h>
31 #include <linux/sched.h>
32
33 #include "iwl-debug.h"
34 #include "iwl-csr.h"
35 #include "iwl-prph.h"
36 #include "iwl-io.h"
37 #include "iwl-scd.h"
38 #include "iwl-op-mode.h"
39 #include "internal.h"
40 /* FIXME: need to abstract out TX command (once we know what it looks like) */
41 #include "dvm/commands.h"
42
43 #define IWL_TX_CRC_SIZE 4
44 #define IWL_TX_DELIMITER_SIZE 4
45
46 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
47 * DMA services
48 *
49 * Theory of operation
50 *
51 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
52 * of buffer descriptors, each of which points to one or more data buffers for
53 * the device to read from or fill. Driver and device exchange status of each
54 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
55 * entries in each circular buffer, to protect against confusing empty and full
56 * queue states.
57 *
58 * The device reads or writes the data in the queues via the device's several
59 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
60 *
61 * For Tx queue, there are low mark and high mark limits. If, after queuing
62 * the packet for Tx, free space become < low mark, Tx queue stopped. When
63 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
64 * Tx queue resumed.
65 *
66 ***************************************************/
67 static int iwl_queue_space(const struct iwl_queue *q)
68 {
69 unsigned int max;
70 unsigned int used;
71
72 /*
73 * To avoid ambiguity between empty and completely full queues, there
74 * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue.
75 * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need
76 * to reserve any queue entries for this purpose.
77 */
78 if (q->n_window < TFD_QUEUE_SIZE_MAX)
79 max = q->n_window;
80 else
81 max = TFD_QUEUE_SIZE_MAX - 1;
82
83 /*
84 * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to
85 * modulo by TFD_QUEUE_SIZE_MAX and is well defined.
86 */
87 used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1);
88
89 if (WARN_ON(used > max))
90 return 0;
91
92 return max - used;
93 }
94
95 /*
96 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
97 */
98 static int iwl_queue_init(struct iwl_queue *q, int slots_num, u32 id)
99 {
100 q->n_window = slots_num;
101 q->id = id;
102
103 /* slots_num must be power-of-two size, otherwise
104 * get_cmd_index is broken. */
105 if (WARN_ON(!is_power_of_2(slots_num)))
106 return -EINVAL;
107
108 q->low_mark = q->n_window / 4;
109 if (q->low_mark < 4)
110 q->low_mark = 4;
111
112 q->high_mark = q->n_window / 8;
113 if (q->high_mark < 2)
114 q->high_mark = 2;
115
116 q->write_ptr = 0;
117 q->read_ptr = 0;
118
119 return 0;
120 }
121
122 static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
123 struct iwl_dma_ptr *ptr, size_t size)
124 {
125 if (WARN_ON(ptr->addr))
126 return -EINVAL;
127
128 ptr->addr = dma_alloc_coherent(trans->dev, size,
129 &ptr->dma, GFP_KERNEL);
130 if (!ptr->addr)
131 return -ENOMEM;
132 ptr->size = size;
133 return 0;
134 }
135
136 static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans,
137 struct iwl_dma_ptr *ptr)
138 {
139 if (unlikely(!ptr->addr))
140 return;
141
142 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
143 memset(ptr, 0, sizeof(*ptr));
144 }
145
146 static void iwl_pcie_txq_stuck_timer(unsigned long data)
147 {
148 struct iwl_txq *txq = (void *)data;
149 struct iwl_queue *q = &txq->q;
150 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
151 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
152 u32 scd_sram_addr = trans_pcie->scd_base_addr +
153 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
154 u8 buf[16];
155 int i;
156
157 spin_lock(&txq->lock);
158 /* check if triggered erroneously */
159 if (txq->q.read_ptr == txq->q.write_ptr) {
160 spin_unlock(&txq->lock);
161 return;
162 }
163 spin_unlock(&txq->lock);
164
165 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
166 jiffies_to_msecs(trans_pcie->wd_timeout));
167 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
168 txq->q.read_ptr, txq->q.write_ptr);
169
170 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
171
172 iwl_print_hex_error(trans, buf, sizeof(buf));
173
174 for (i = 0; i < FH_TCSR_CHNL_NUM; i++)
175 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i,
176 iwl_read_direct32(trans, FH_TX_TRB_REG(i)));
177
178 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
179 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i));
180 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
181 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
182 u32 tbl_dw =
183 iwl_trans_read_mem32(trans,
184 trans_pcie->scd_base_addr +
185 SCD_TRANS_TBL_OFFSET_QUEUE(i));
186
187 if (i & 0x1)
188 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
189 else
190 tbl_dw = tbl_dw & 0x0000FFFF;
191
192 IWL_ERR(trans,
193 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
194 i, active ? "" : "in", fifo, tbl_dw,
195 iwl_read_prph(trans, SCD_QUEUE_RDPTR(i)) &
196 (TFD_QUEUE_SIZE_MAX - 1),
197 iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
198 }
199
200 for (i = q->read_ptr; i != q->write_ptr;
201 i = iwl_queue_inc_wrap(i))
202 IWL_ERR(trans, "scratch %d = 0x%08x\n", i,
203 le32_to_cpu(txq->scratchbufs[i].scratch));
204
205 iwl_force_nmi(trans);
206 }
207
208 /*
209 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
210 */
211 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
212 struct iwl_txq *txq, u16 byte_cnt)
213 {
214 struct iwlagn_scd_bc_tbl *scd_bc_tbl;
215 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
216 int write_ptr = txq->q.write_ptr;
217 int txq_id = txq->q.id;
218 u8 sec_ctl = 0;
219 u8 sta_id = 0;
220 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
221 __le16 bc_ent;
222 struct iwl_tx_cmd *tx_cmd =
223 (void *) txq->entries[txq->q.write_ptr].cmd->payload;
224
225 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
226
227 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
228
229 sta_id = tx_cmd->sta_id;
230 sec_ctl = tx_cmd->sec_ctl;
231
232 switch (sec_ctl & TX_CMD_SEC_MSK) {
233 case TX_CMD_SEC_CCM:
234 len += IEEE80211_CCMP_MIC_LEN;
235 break;
236 case TX_CMD_SEC_TKIP:
237 len += IEEE80211_TKIP_ICV_LEN;
238 break;
239 case TX_CMD_SEC_WEP:
240 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
241 break;
242 }
243
244 if (trans_pcie->bc_table_dword)
245 len = DIV_ROUND_UP(len, 4);
246
247 bc_ent = cpu_to_le16(len | (sta_id << 12));
248
249 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
250
251 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
252 scd_bc_tbl[txq_id].
253 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
254 }
255
256 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
257 struct iwl_txq *txq)
258 {
259 struct iwl_trans_pcie *trans_pcie =
260 IWL_TRANS_GET_PCIE_TRANS(trans);
261 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
262 int txq_id = txq->q.id;
263 int read_ptr = txq->q.read_ptr;
264 u8 sta_id = 0;
265 __le16 bc_ent;
266 struct iwl_tx_cmd *tx_cmd =
267 (void *)txq->entries[txq->q.read_ptr].cmd->payload;
268
269 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
270
271 if (txq_id != trans_pcie->cmd_queue)
272 sta_id = tx_cmd->sta_id;
273
274 bc_ent = cpu_to_le16(1 | (sta_id << 12));
275 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
276
277 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
278 scd_bc_tbl[txq_id].
279 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
280 }
281
282 /*
283 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
284 */
285 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
286 struct iwl_txq *txq)
287 {
288 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
289 u32 reg = 0;
290 int txq_id = txq->q.id;
291
292 lockdep_assert_held(&txq->lock);
293
294 /*
295 * explicitly wake up the NIC if:
296 * 1. shadow registers aren't enabled
297 * 2. NIC is woken up for CMD regardless of shadow outside this function
298 * 3. there is a chance that the NIC is asleep
299 */
300 if (!trans->cfg->base_params->shadow_reg_enable &&
301 txq_id != trans_pcie->cmd_queue &&
302 test_bit(STATUS_TPOWER_PMI, &trans->status)) {
303 /*
304 * wake up nic if it's powered down ...
305 * uCode will wake up, and interrupt us again, so next
306 * time we'll skip this part.
307 */
308 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
309
310 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
311 IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
312 txq_id, reg);
313 iwl_set_bit(trans, CSR_GP_CNTRL,
314 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
315 txq->need_update = true;
316 return;
317 }
318 }
319
320 /*
321 * if not in power-save mode, uCode will never sleep when we're
322 * trying to tx (during RFKILL, we're not trying to tx).
323 */
324 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->q.write_ptr);
325 iwl_write32(trans, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
326 }
327
328 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
329 {
330 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
331 int i;
332
333 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
334 struct iwl_txq *txq = &trans_pcie->txq[i];
335
336 spin_lock_bh(&txq->lock);
337 if (trans_pcie->txq[i].need_update) {
338 iwl_pcie_txq_inc_wr_ptr(trans, txq);
339 trans_pcie->txq[i].need_update = false;
340 }
341 spin_unlock_bh(&txq->lock);
342 }
343 }
344
345 static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
346 {
347 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
348
349 dma_addr_t addr = get_unaligned_le32(&tb->lo);
350 if (sizeof(dma_addr_t) > sizeof(u32))
351 addr |=
352 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
353
354 return addr;
355 }
356
357 static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
358 dma_addr_t addr, u16 len)
359 {
360 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
361 u16 hi_n_len = len << 4;
362
363 put_unaligned_le32(addr, &tb->lo);
364 if (sizeof(dma_addr_t) > sizeof(u32))
365 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
366
367 tb->hi_n_len = cpu_to_le16(hi_n_len);
368
369 tfd->num_tbs = idx + 1;
370 }
371
372 static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd)
373 {
374 return tfd->num_tbs & 0x1f;
375 }
376
377 static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
378 struct iwl_cmd_meta *meta,
379 struct iwl_tfd *tfd)
380 {
381 int i;
382 int num_tbs;
383
384 /* Sanity check on number of chunks */
385 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
386
387 if (num_tbs >= IWL_NUM_OF_TBS) {
388 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
389 /* @todo issue fatal error, it is quite serious situation */
390 return;
391 }
392
393 /* first TB is never freed - it's the scratchbuf data */
394
395 for (i = 1; i < num_tbs; i++)
396 dma_unmap_single(trans->dev, iwl_pcie_tfd_tb_get_addr(tfd, i),
397 iwl_pcie_tfd_tb_get_len(tfd, i),
398 DMA_TO_DEVICE);
399
400 tfd->num_tbs = 0;
401 }
402
403 /*
404 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
405 * @trans - transport private data
406 * @txq - tx queue
407 * @dma_dir - the direction of the DMA mapping
408 *
409 * Does NOT advance any TFD circular buffer read/write indexes
410 * Does NOT free the TFD itself (which is within circular buffer)
411 */
412 static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
413 {
414 struct iwl_tfd *tfd_tmp = txq->tfds;
415
416 /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
417 * idx is bounded by n_window
418 */
419 int rd_ptr = txq->q.read_ptr;
420 int idx = get_cmd_index(&txq->q, rd_ptr);
421
422 lockdep_assert_held(&txq->lock);
423
424 /* We have only q->n_window txq->entries, but we use
425 * TFD_QUEUE_SIZE_MAX tfds
426 */
427 iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]);
428
429 /* free SKB */
430 if (txq->entries) {
431 struct sk_buff *skb;
432
433 skb = txq->entries[idx].skb;
434
435 /* Can be called from irqs-disabled context
436 * If skb is not NULL, it means that the whole queue is being
437 * freed and that the queue is not empty - free the skb
438 */
439 if (skb) {
440 iwl_op_mode_free_skb(trans->op_mode, skb);
441 txq->entries[idx].skb = NULL;
442 }
443 }
444 }
445
446 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
447 dma_addr_t addr, u16 len, bool reset)
448 {
449 struct iwl_queue *q;
450 struct iwl_tfd *tfd, *tfd_tmp;
451 u32 num_tbs;
452
453 q = &txq->q;
454 tfd_tmp = txq->tfds;
455 tfd = &tfd_tmp[q->write_ptr];
456
457 if (reset)
458 memset(tfd, 0, sizeof(*tfd));
459
460 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
461
462 /* Each TFD can point to a maximum 20 Tx buffers */
463 if (num_tbs >= IWL_NUM_OF_TBS) {
464 IWL_ERR(trans, "Error can not send more than %d chunks\n",
465 IWL_NUM_OF_TBS);
466 return -EINVAL;
467 }
468
469 if (WARN(addr & ~IWL_TX_DMA_MASK,
470 "Unaligned address = %llx\n", (unsigned long long)addr))
471 return -EINVAL;
472
473 iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len);
474
475 return 0;
476 }
477
478 static int iwl_pcie_txq_alloc(struct iwl_trans *trans,
479 struct iwl_txq *txq, int slots_num,
480 u32 txq_id)
481 {
482 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
483 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
484 size_t scratchbuf_sz;
485 int i;
486
487 if (WARN_ON(txq->entries || txq->tfds))
488 return -EINVAL;
489
490 setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer,
491 (unsigned long)txq);
492 txq->trans_pcie = trans_pcie;
493
494 txq->q.n_window = slots_num;
495
496 txq->entries = kcalloc(slots_num,
497 sizeof(struct iwl_pcie_txq_entry),
498 GFP_KERNEL);
499
500 if (!txq->entries)
501 goto error;
502
503 if (txq_id == trans_pcie->cmd_queue)
504 for (i = 0; i < slots_num; i++) {
505 txq->entries[i].cmd =
506 kmalloc(sizeof(struct iwl_device_cmd),
507 GFP_KERNEL);
508 if (!txq->entries[i].cmd)
509 goto error;
510 }
511
512 /* Circular buffer of transmit frame descriptors (TFDs),
513 * shared with device */
514 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
515 &txq->q.dma_addr, GFP_KERNEL);
516 if (!txq->tfds)
517 goto error;
518
519 BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE != sizeof(*txq->scratchbufs));
520 BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf, scratch) !=
521 sizeof(struct iwl_cmd_header) +
522 offsetof(struct iwl_tx_cmd, scratch));
523
524 scratchbuf_sz = sizeof(*txq->scratchbufs) * slots_num;
525
526 txq->scratchbufs = dma_alloc_coherent(trans->dev, scratchbuf_sz,
527 &txq->scratchbufs_dma,
528 GFP_KERNEL);
529 if (!txq->scratchbufs)
530 goto err_free_tfds;
531
532 txq->q.id = txq_id;
533
534 return 0;
535 err_free_tfds:
536 dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr);
537 error:
538 if (txq->entries && txq_id == trans_pcie->cmd_queue)
539 for (i = 0; i < slots_num; i++)
540 kfree(txq->entries[i].cmd);
541 kfree(txq->entries);
542 txq->entries = NULL;
543
544 return -ENOMEM;
545
546 }
547
548 static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
549 int slots_num, u32 txq_id)
550 {
551 int ret;
552
553 txq->need_update = false;
554
555 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
556 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
557 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
558
559 /* Initialize queue's high/low-water marks, and head/tail indexes */
560 ret = iwl_queue_init(&txq->q, slots_num, txq_id);
561 if (ret)
562 return ret;
563
564 spin_lock_init(&txq->lock);
565
566 /*
567 * Tell nic where to find circular buffer of Tx Frame Descriptors for
568 * given Tx queue, and enable the DMA channel used for that queue.
569 * Circular buffer (TFD queue in DRAM) physical base address */
570 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
571 txq->q.dma_addr >> 8);
572
573 return 0;
574 }
575
576 /*
577 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's
578 */
579 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
580 {
581 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
582 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
583 struct iwl_queue *q = &txq->q;
584
585 spin_lock_bh(&txq->lock);
586 while (q->write_ptr != q->read_ptr) {
587 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
588 txq_id, q->read_ptr);
589 iwl_pcie_txq_free_tfd(trans, txq);
590 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr);
591 }
592 txq->active = false;
593 spin_unlock_bh(&txq->lock);
594
595 /* just in case - this queue may have been stopped */
596 iwl_wake_queue(trans, txq);
597 }
598
599 /*
600 * iwl_pcie_txq_free - Deallocate DMA queue.
601 * @txq: Transmit queue to deallocate.
602 *
603 * Empty queue by removing and destroying all BD's.
604 * Free all buffers.
605 * 0-fill, but do not free "txq" descriptor structure.
606 */
607 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
608 {
609 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
610 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
611 struct device *dev = trans->dev;
612 int i;
613
614 if (WARN_ON(!txq))
615 return;
616
617 iwl_pcie_txq_unmap(trans, txq_id);
618
619 /* De-alloc array of command/tx buffers */
620 if (txq_id == trans_pcie->cmd_queue)
621 for (i = 0; i < txq->q.n_window; i++) {
622 kfree(txq->entries[i].cmd);
623 kfree(txq->entries[i].free_buf);
624 }
625
626 /* De-alloc circular buffer of TFDs */
627 if (txq->tfds) {
628 dma_free_coherent(dev,
629 sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX,
630 txq->tfds, txq->q.dma_addr);
631 txq->q.dma_addr = 0;
632 txq->tfds = NULL;
633
634 dma_free_coherent(dev,
635 sizeof(*txq->scratchbufs) * txq->q.n_window,
636 txq->scratchbufs, txq->scratchbufs_dma);
637 }
638
639 kfree(txq->entries);
640 txq->entries = NULL;
641
642 del_timer_sync(&txq->stuck_timer);
643
644 /* 0-fill queue descriptor structure */
645 memset(txq, 0, sizeof(*txq));
646 }
647
648 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
649 {
650 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
651 int nq = trans->cfg->base_params->num_of_queues;
652 int chan;
653 u32 reg_val;
654 int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
655 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
656
657 /* make sure all queue are not stopped/used */
658 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
659 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
660
661 trans_pcie->scd_base_addr =
662 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
663
664 WARN_ON(scd_base_addr != 0 &&
665 scd_base_addr != trans_pcie->scd_base_addr);
666
667 /* reset context data, TX status and translation data */
668 iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
669 SCD_CONTEXT_MEM_LOWER_BOUND,
670 NULL, clear_dwords);
671
672 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
673 trans_pcie->scd_bc_tbls.dma >> 10);
674
675 /* The chain extension of the SCD doesn't work well. This feature is
676 * enabled by default by the HW, so we need to disable it manually.
677 */
678 if (trans->cfg->base_params->scd_chain_ext_wa)
679 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
680
681 iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
682 trans_pcie->cmd_fifo);
683
684 /* Activate all Tx DMA/FIFO channels */
685 iwl_scd_activate_fifos(trans);
686
687 /* Enable DMA channel */
688 for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
689 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
690 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
691 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
692
693 /* Update FH chicken bits */
694 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
695 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
696 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
697
698 /* Enable L1-Active */
699 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
700 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
701 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
702 }
703
704 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
705 {
706 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
707 int txq_id;
708
709 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
710 txq_id++) {
711 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
712
713 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
714 txq->q.dma_addr >> 8);
715 iwl_pcie_txq_unmap(trans, txq_id);
716 txq->q.read_ptr = 0;
717 txq->q.write_ptr = 0;
718 }
719
720 /* Tell NIC where to find the "keep warm" buffer */
721 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
722 trans_pcie->kw.dma >> 4);
723
724 iwl_pcie_tx_start(trans, trans_pcie->scd_base_addr);
725 }
726
727 /*
728 * iwl_pcie_tx_stop - Stop all Tx DMA channels
729 */
730 int iwl_pcie_tx_stop(struct iwl_trans *trans)
731 {
732 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
733 int ch, txq_id, ret;
734
735 /* Turn off all Tx DMA fifos */
736 spin_lock(&trans_pcie->irq_lock);
737
738 iwl_scd_deactivate_fifos(trans);
739
740 /* Stop each Tx DMA channel, and wait for it to be idle */
741 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
742 iwl_write_direct32(trans,
743 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
744 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
745 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000);
746 if (ret < 0)
747 IWL_ERR(trans,
748 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
749 ch,
750 iwl_read_direct32(trans,
751 FH_TSSR_TX_STATUS_REG));
752 }
753 spin_unlock(&trans_pcie->irq_lock);
754
755 /*
756 * This function can be called before the op_mode disabled the
757 * queues. This happens when we have an rfkill interrupt.
758 * Since we stop Tx altogether - mark the queues as stopped.
759 */
760 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
761 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
762
763 /* This can happen: start_hw, stop_device */
764 if (!trans_pcie->txq)
765 return 0;
766
767 /* Unmap DMA from host system and free skb's */
768 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
769 txq_id++)
770 iwl_pcie_txq_unmap(trans, txq_id);
771
772 return 0;
773 }
774
775 /*
776 * iwl_trans_tx_free - Free TXQ Context
777 *
778 * Destroy all TX DMA queues and structures
779 */
780 void iwl_pcie_tx_free(struct iwl_trans *trans)
781 {
782 int txq_id;
783 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
784
785 /* Tx queues */
786 if (trans_pcie->txq) {
787 for (txq_id = 0;
788 txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
789 iwl_pcie_txq_free(trans, txq_id);
790 }
791
792 kfree(trans_pcie->txq);
793 trans_pcie->txq = NULL;
794
795 iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
796
797 iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
798 }
799
800 /*
801 * iwl_pcie_tx_alloc - allocate TX context
802 * Allocate all Tx DMA structures and initialize them
803 */
804 static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
805 {
806 int ret;
807 int txq_id, slots_num;
808 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
809
810 u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
811 sizeof(struct iwlagn_scd_bc_tbl);
812
813 /*It is not allowed to alloc twice, so warn when this happens.
814 * We cannot rely on the previous allocation, so free and fail */
815 if (WARN_ON(trans_pcie->txq)) {
816 ret = -EINVAL;
817 goto error;
818 }
819
820 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
821 scd_bc_tbls_size);
822 if (ret) {
823 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
824 goto error;
825 }
826
827 /* Alloc keep-warm buffer */
828 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
829 if (ret) {
830 IWL_ERR(trans, "Keep Warm allocation failed\n");
831 goto error;
832 }
833
834 trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
835 sizeof(struct iwl_txq), GFP_KERNEL);
836 if (!trans_pcie->txq) {
837 IWL_ERR(trans, "Not enough memory for txq\n");
838 ret = -ENOMEM;
839 goto error;
840 }
841
842 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
843 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
844 txq_id++) {
845 slots_num = (txq_id == trans_pcie->cmd_queue) ?
846 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
847 ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id],
848 slots_num, txq_id);
849 if (ret) {
850 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
851 goto error;
852 }
853 }
854
855 return 0;
856
857 error:
858 iwl_pcie_tx_free(trans);
859
860 return ret;
861 }
862 int iwl_pcie_tx_init(struct iwl_trans *trans)
863 {
864 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
865 int ret;
866 int txq_id, slots_num;
867 bool alloc = false;
868
869 if (!trans_pcie->txq) {
870 ret = iwl_pcie_tx_alloc(trans);
871 if (ret)
872 goto error;
873 alloc = true;
874 }
875
876 spin_lock(&trans_pcie->irq_lock);
877
878 /* Turn off all Tx DMA fifos */
879 iwl_scd_deactivate_fifos(trans);
880
881 /* Tell NIC where to find the "keep warm" buffer */
882 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
883 trans_pcie->kw.dma >> 4);
884
885 spin_unlock(&trans_pcie->irq_lock);
886
887 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
888 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
889 txq_id++) {
890 slots_num = (txq_id == trans_pcie->cmd_queue) ?
891 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
892 ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id],
893 slots_num, txq_id);
894 if (ret) {
895 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
896 goto error;
897 }
898 }
899
900 return 0;
901 error:
902 /*Upon error, free only if we allocated something */
903 if (alloc)
904 iwl_pcie_tx_free(trans);
905 return ret;
906 }
907
908 static inline void iwl_pcie_txq_progress(struct iwl_trans_pcie *trans_pcie,
909 struct iwl_txq *txq)
910 {
911 if (!trans_pcie->wd_timeout)
912 return;
913
914 /*
915 * if empty delete timer, otherwise move timer forward
916 * since we're making progress on this queue
917 */
918 if (txq->q.read_ptr == txq->q.write_ptr)
919 del_timer(&txq->stuck_timer);
920 else
921 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
922 }
923
924 /* Frees buffers until index _not_ inclusive */
925 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
926 struct sk_buff_head *skbs)
927 {
928 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
929 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
930 int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1);
931 struct iwl_queue *q = &txq->q;
932 int last_to_free;
933
934 /* This function is not meant to release cmd queue*/
935 if (WARN_ON(txq_id == trans_pcie->cmd_queue))
936 return;
937
938 spin_lock_bh(&txq->lock);
939
940 if (!txq->active) {
941 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
942 txq_id, ssn);
943 goto out;
944 }
945
946 if (txq->q.read_ptr == tfd_num)
947 goto out;
948
949 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
950 txq_id, txq->q.read_ptr, tfd_num, ssn);
951
952 /*Since we free until index _not_ inclusive, the one before index is
953 * the last we will free. This one must be used */
954 last_to_free = iwl_queue_dec_wrap(tfd_num);
955
956 if (!iwl_queue_used(q, last_to_free)) {
957 IWL_ERR(trans,
958 "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
959 __func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX,
960 q->write_ptr, q->read_ptr);
961 goto out;
962 }
963
964 if (WARN_ON(!skb_queue_empty(skbs)))
965 goto out;
966
967 for (;
968 q->read_ptr != tfd_num;
969 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {
970
971 if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL))
972 continue;
973
974 __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb);
975
976 txq->entries[txq->q.read_ptr].skb = NULL;
977
978 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
979
980 iwl_pcie_txq_free_tfd(trans, txq);
981 }
982
983 iwl_pcie_txq_progress(trans_pcie, txq);
984
985 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
986 iwl_wake_queue(trans, txq);
987 out:
988 spin_unlock_bh(&txq->lock);
989 }
990
991 /*
992 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
993 *
994 * When FW advances 'R' index, all entries between old and new 'R' index
995 * need to be reclaimed. As result, some free space forms. If there is
996 * enough free space (> low mark), wake the stack that feeds us.
997 */
998 static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
999 {
1000 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1001 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1002 struct iwl_queue *q = &txq->q;
1003 unsigned long flags;
1004 int nfreed = 0;
1005
1006 lockdep_assert_held(&txq->lock);
1007
1008 if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(q, idx))) {
1009 IWL_ERR(trans,
1010 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1011 __func__, txq_id, idx, TFD_QUEUE_SIZE_MAX,
1012 q->write_ptr, q->read_ptr);
1013 return;
1014 }
1015
1016 for (idx = iwl_queue_inc_wrap(idx); q->read_ptr != idx;
1017 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {
1018
1019 if (nfreed++ > 0) {
1020 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1021 idx, q->write_ptr, q->read_ptr);
1022 iwl_force_nmi(trans);
1023 }
1024 }
1025
1026 if (trans->cfg->base_params->apmg_wake_up_wa &&
1027 q->read_ptr == q->write_ptr) {
1028 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1029 WARN_ON(!trans_pcie->cmd_in_flight);
1030 trans_pcie->cmd_in_flight = false;
1031 __iwl_trans_pcie_clear_bit(trans,
1032 CSR_GP_CNTRL,
1033 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1034 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1035 }
1036
1037 iwl_pcie_txq_progress(trans_pcie, txq);
1038 }
1039
1040 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1041 u16 txq_id)
1042 {
1043 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1044 u32 tbl_dw_addr;
1045 u32 tbl_dw;
1046 u16 scd_q2ratid;
1047
1048 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1049
1050 tbl_dw_addr = trans_pcie->scd_base_addr +
1051 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1052
1053 tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1054
1055 if (txq_id & 0x1)
1056 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1057 else
1058 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1059
1060 iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1061
1062 return 0;
1063 }
1064
1065 /* Receiver address (actually, Rx station's index into station table),
1066 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1067 #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
1068
1069 void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
1070 const struct iwl_trans_txq_scd_cfg *cfg)
1071 {
1072 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1073 int fifo = -1;
1074
1075 if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1076 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1077
1078 if (cfg) {
1079 fifo = cfg->fifo;
1080
1081 /* Disable the scheduler prior configuring the cmd queue */
1082 if (txq_id == trans_pcie->cmd_queue)
1083 iwl_scd_enable_set_active(trans, 0);
1084
1085 /* Stop this Tx queue before configuring it */
1086 iwl_scd_txq_set_inactive(trans, txq_id);
1087
1088 /* Set this queue as a chain-building queue unless it is CMD */
1089 if (txq_id != trans_pcie->cmd_queue)
1090 iwl_scd_txq_set_chain(trans, txq_id);
1091
1092 if (cfg->aggregate) {
1093 u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid);
1094
1095 /* Map receiver-address / traffic-ID to this queue */
1096 iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1097
1098 /* enable aggregations for the queue */
1099 iwl_scd_txq_enable_agg(trans, txq_id);
1100 trans_pcie->txq[txq_id].ampdu = true;
1101 } else {
1102 /*
1103 * disable aggregations for the queue, this will also
1104 * make the ra_tid mapping configuration irrelevant
1105 * since it is now a non-AGG queue.
1106 */
1107 iwl_scd_txq_disable_agg(trans, txq_id);
1108
1109 ssn = trans_pcie->txq[txq_id].q.read_ptr;
1110 }
1111 }
1112
1113 /* Place first TFD at index corresponding to start sequence number.
1114 * Assumes that ssn_idx is valid (!= 0xFFF) */
1115 trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff);
1116 trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff);
1117
1118 if (cfg) {
1119 u8 frame_limit = cfg->frame_limit;
1120
1121 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1122 (ssn & 0xff) | (txq_id << 8));
1123 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1124
1125 /* Set up Tx window size and frame limit for this queue */
1126 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1127 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1128 iwl_trans_write_mem32(trans,
1129 trans_pcie->scd_base_addr +
1130 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1131 ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1132 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1133 ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1134 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1135
1136 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
1137 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1138 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1139 (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1140 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1141 SCD_QUEUE_STTS_REG_MSK);
1142
1143 /* enable the scheduler for this queue (only) */
1144 if (txq_id == trans_pcie->cmd_queue)
1145 iwl_scd_enable_set_active(trans, BIT(txq_id));
1146 }
1147
1148 trans_pcie->txq[txq_id].active = true;
1149 IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d on FIFO %d WrPtr: %d\n",
1150 txq_id, fifo, ssn & 0xff);
1151 }
1152
1153 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
1154 bool configure_scd)
1155 {
1156 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1157 u32 stts_addr = trans_pcie->scd_base_addr +
1158 SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1159 static const u32 zero_val[4] = {};
1160
1161 /*
1162 * Upon HW Rfkill - we stop the device, and then stop the queues
1163 * in the op_mode. Just for the sake of the simplicity of the op_mode,
1164 * allow the op_mode to call txq_disable after it already called
1165 * stop_device.
1166 */
1167 if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
1168 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1169 "queue %d not used", txq_id);
1170 return;
1171 }
1172
1173 if (configure_scd) {
1174 iwl_scd_txq_set_inactive(trans, txq_id);
1175
1176 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1177 ARRAY_SIZE(zero_val));
1178 }
1179
1180 iwl_pcie_txq_unmap(trans, txq_id);
1181 trans_pcie->txq[txq_id].ampdu = false;
1182
1183 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1184 }
1185
1186 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1187
1188 /*
1189 * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1190 * @priv: device private data point
1191 * @cmd: a pointer to the ucode command structure
1192 *
1193 * The function returns < 0 values to indicate the operation
1194 * failed. On success, it returns the index (>= 0) of command in the
1195 * command queue.
1196 */
1197 static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1198 struct iwl_host_cmd *cmd)
1199 {
1200 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1201 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1202 struct iwl_queue *q = &txq->q;
1203 struct iwl_device_cmd *out_cmd;
1204 struct iwl_cmd_meta *out_meta;
1205 unsigned long flags;
1206 void *dup_buf = NULL;
1207 dma_addr_t phys_addr;
1208 int idx;
1209 u16 copy_size, cmd_size, scratch_size;
1210 bool had_nocopy = false;
1211 int i, ret;
1212 u32 cmd_pos;
1213 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1214 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
1215
1216 copy_size = sizeof(out_cmd->hdr);
1217 cmd_size = sizeof(out_cmd->hdr);
1218
1219 /* need one for the header if the first is NOCOPY */
1220 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
1221
1222 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1223 cmddata[i] = cmd->data[i];
1224 cmdlen[i] = cmd->len[i];
1225
1226 if (!cmd->len[i])
1227 continue;
1228
1229 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1230 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1231 int copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1232
1233 if (copy > cmdlen[i])
1234 copy = cmdlen[i];
1235 cmdlen[i] -= copy;
1236 cmddata[i] += copy;
1237 copy_size += copy;
1238 }
1239
1240 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1241 had_nocopy = true;
1242 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1243 idx = -EINVAL;
1244 goto free_dup_buf;
1245 }
1246 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1247 /*
1248 * This is also a chunk that isn't copied
1249 * to the static buffer so set had_nocopy.
1250 */
1251 had_nocopy = true;
1252
1253 /* only allowed once */
1254 if (WARN_ON(dup_buf)) {
1255 idx = -EINVAL;
1256 goto free_dup_buf;
1257 }
1258
1259 dup_buf = kmemdup(cmddata[i], cmdlen[i],
1260 GFP_ATOMIC);
1261 if (!dup_buf)
1262 return -ENOMEM;
1263 } else {
1264 /* NOCOPY must not be followed by normal! */
1265 if (WARN_ON(had_nocopy)) {
1266 idx = -EINVAL;
1267 goto free_dup_buf;
1268 }
1269 copy_size += cmdlen[i];
1270 }
1271 cmd_size += cmd->len[i];
1272 }
1273
1274 /*
1275 * If any of the command structures end up being larger than
1276 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1277 * allocated into separate TFDs, then we will need to
1278 * increase the size of the buffers.
1279 */
1280 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1281 "Command %s (%#x) is too large (%d bytes)\n",
1282 get_cmd_string(trans_pcie, cmd->id), cmd->id, copy_size)) {
1283 idx = -EINVAL;
1284 goto free_dup_buf;
1285 }
1286
1287 spin_lock_bh(&txq->lock);
1288
1289 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1290 spin_unlock_bh(&txq->lock);
1291
1292 IWL_ERR(trans, "No space in command queue\n");
1293 iwl_op_mode_cmd_queue_full(trans->op_mode);
1294 idx = -ENOSPC;
1295 goto free_dup_buf;
1296 }
1297
1298 idx = get_cmd_index(q, q->write_ptr);
1299 out_cmd = txq->entries[idx].cmd;
1300 out_meta = &txq->entries[idx].meta;
1301
1302 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1303 if (cmd->flags & CMD_WANT_SKB)
1304 out_meta->source = cmd;
1305
1306 /* set up the header */
1307
1308 out_cmd->hdr.cmd = cmd->id;
1309 out_cmd->hdr.flags = 0;
1310 out_cmd->hdr.sequence =
1311 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1312 INDEX_TO_SEQ(q->write_ptr));
1313
1314 /* and copy the data that needs to be copied */
1315 cmd_pos = offsetof(struct iwl_device_cmd, payload);
1316 copy_size = sizeof(out_cmd->hdr);
1317 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1318 int copy;
1319
1320 if (!cmd->len[i])
1321 continue;
1322
1323 /* copy everything if not nocopy/dup */
1324 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1325 IWL_HCMD_DFL_DUP))) {
1326 copy = cmd->len[i];
1327
1328 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1329 cmd_pos += copy;
1330 copy_size += copy;
1331 continue;
1332 }
1333
1334 /*
1335 * Otherwise we need at least IWL_HCMD_SCRATCHBUF_SIZE copied
1336 * in total (for the scratchbuf handling), but copy up to what
1337 * we can fit into the payload for debug dump purposes.
1338 */
1339 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
1340
1341 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1342 cmd_pos += copy;
1343
1344 /* However, treat copy_size the proper way, we need it below */
1345 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1346 copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1347
1348 if (copy > cmd->len[i])
1349 copy = cmd->len[i];
1350 copy_size += copy;
1351 }
1352 }
1353
1354 IWL_DEBUG_HC(trans,
1355 "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1356 get_cmd_string(trans_pcie, out_cmd->hdr.cmd),
1357 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
1358 cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue);
1359
1360 /* start the TFD with the scratchbuf */
1361 scratch_size = min_t(int, copy_size, IWL_HCMD_SCRATCHBUF_SIZE);
1362 memcpy(&txq->scratchbufs[q->write_ptr], &out_cmd->hdr, scratch_size);
1363 iwl_pcie_txq_build_tfd(trans, txq,
1364 iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr),
1365 scratch_size, true);
1366
1367 /* map first command fragment, if any remains */
1368 if (copy_size > scratch_size) {
1369 phys_addr = dma_map_single(trans->dev,
1370 ((u8 *)&out_cmd->hdr) + scratch_size,
1371 copy_size - scratch_size,
1372 DMA_TO_DEVICE);
1373 if (dma_mapping_error(trans->dev, phys_addr)) {
1374 iwl_pcie_tfd_unmap(trans, out_meta,
1375 &txq->tfds[q->write_ptr]);
1376 idx = -ENOMEM;
1377 goto out;
1378 }
1379
1380 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1381 copy_size - scratch_size, false);
1382 }
1383
1384 /* map the remaining (adjusted) nocopy/dup fragments */
1385 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1386 const void *data = cmddata[i];
1387
1388 if (!cmdlen[i])
1389 continue;
1390 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1391 IWL_HCMD_DFL_DUP)))
1392 continue;
1393 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1394 data = dup_buf;
1395 phys_addr = dma_map_single(trans->dev, (void *)data,
1396 cmdlen[i], DMA_TO_DEVICE);
1397 if (dma_mapping_error(trans->dev, phys_addr)) {
1398 iwl_pcie_tfd_unmap(trans, out_meta,
1399 &txq->tfds[q->write_ptr]);
1400 idx = -ENOMEM;
1401 goto out;
1402 }
1403
1404 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false);
1405 }
1406
1407 out_meta->flags = cmd->flags;
1408 if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1409 kfree(txq->entries[idx].free_buf);
1410 txq->entries[idx].free_buf = dup_buf;
1411
1412 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr);
1413
1414 /* start timer if queue currently empty */
1415 if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout)
1416 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1417
1418 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1419
1420 /*
1421 * wake up the NIC to make sure that the firmware will see the host
1422 * command - we will let the NIC sleep once all the host commands
1423 * returned. This needs to be done only on NICs that have
1424 * apmg_wake_up_wa set.
1425 */
1426 if (trans->cfg->base_params->apmg_wake_up_wa &&
1427 !trans_pcie->cmd_in_flight) {
1428 trans_pcie->cmd_in_flight = true;
1429 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1430 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1431 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1432 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1433 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1434 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
1435 15000);
1436 if (ret < 0) {
1437 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1438 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1439 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1440 trans_pcie->cmd_in_flight = false;
1441 IWL_ERR(trans, "Failed to wake NIC for hcmd\n");
1442 idx = -EIO;
1443 goto out;
1444 }
1445 }
1446
1447 /* Increment and update queue's write index */
1448 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);
1449 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1450
1451 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1452
1453 out:
1454 spin_unlock_bh(&txq->lock);
1455 free_dup_buf:
1456 if (idx < 0)
1457 kfree(dup_buf);
1458 return idx;
1459 }
1460
1461 /*
1462 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1463 * @rxb: Rx buffer to reclaim
1464 * @handler_status: return value of the handler of the command
1465 * (put in setup_rx_handlers)
1466 *
1467 * If an Rx buffer has an async callback associated with it the callback
1468 * will be executed. The attached skb (if present) will only be freed
1469 * if the callback returns 1
1470 */
1471 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1472 struct iwl_rx_cmd_buffer *rxb, int handler_status)
1473 {
1474 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1475 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1476 int txq_id = SEQ_TO_QUEUE(sequence);
1477 int index = SEQ_TO_INDEX(sequence);
1478 int cmd_index;
1479 struct iwl_device_cmd *cmd;
1480 struct iwl_cmd_meta *meta;
1481 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1482 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1483
1484 /* If a Tx command is being handled and it isn't in the actual
1485 * command queue then there a command routing bug has been introduced
1486 * in the queue management code. */
1487 if (WARN(txq_id != trans_pcie->cmd_queue,
1488 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1489 txq_id, trans_pcie->cmd_queue, sequence,
1490 trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr,
1491 trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) {
1492 iwl_print_hex_error(trans, pkt, 32);
1493 return;
1494 }
1495
1496 spin_lock_bh(&txq->lock);
1497
1498 cmd_index = get_cmd_index(&txq->q, index);
1499 cmd = txq->entries[cmd_index].cmd;
1500 meta = &txq->entries[cmd_index].meta;
1501
1502 iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]);
1503
1504 /* Input error checking is done when commands are added to queue. */
1505 if (meta->flags & CMD_WANT_SKB) {
1506 struct page *p = rxb_steal_page(rxb);
1507
1508 meta->source->resp_pkt = pkt;
1509 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1510 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1511 meta->source->handler_status = handler_status;
1512 }
1513
1514 iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1515
1516 if (!(meta->flags & CMD_ASYNC)) {
1517 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) {
1518 IWL_WARN(trans,
1519 "HCMD_ACTIVE already clear for command %s\n",
1520 get_cmd_string(trans_pcie, cmd->hdr.cmd));
1521 }
1522 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1523 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1524 get_cmd_string(trans_pcie, cmd->hdr.cmd));
1525 wake_up(&trans_pcie->wait_command_queue);
1526 }
1527
1528 meta->flags = 0;
1529
1530 spin_unlock_bh(&txq->lock);
1531 }
1532
1533 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
1534
1535 static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1536 struct iwl_host_cmd *cmd)
1537 {
1538 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1539 int ret;
1540
1541 /* An asynchronous command can not expect an SKB to be set. */
1542 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1543 return -EINVAL;
1544
1545 ret = iwl_pcie_enqueue_hcmd(trans, cmd);
1546 if (ret < 0) {
1547 IWL_ERR(trans,
1548 "Error sending %s: enqueue_hcmd failed: %d\n",
1549 get_cmd_string(trans_pcie, cmd->id), ret);
1550 return ret;
1551 }
1552 return 0;
1553 }
1554
1555 static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1556 struct iwl_host_cmd *cmd)
1557 {
1558 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1559 int cmd_idx;
1560 int ret;
1561
1562 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1563 get_cmd_string(trans_pcie, cmd->id));
1564
1565 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
1566 &trans->status),
1567 "Command %s: a command is already active!\n",
1568 get_cmd_string(trans_pcie, cmd->id)))
1569 return -EIO;
1570
1571 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1572 get_cmd_string(trans_pcie, cmd->id));
1573
1574 cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
1575 if (cmd_idx < 0) {
1576 ret = cmd_idx;
1577 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1578 IWL_ERR(trans,
1579 "Error sending %s: enqueue_hcmd failed: %d\n",
1580 get_cmd_string(trans_pcie, cmd->id), ret);
1581 return ret;
1582 }
1583
1584 ret = wait_event_timeout(trans_pcie->wait_command_queue,
1585 !test_bit(STATUS_SYNC_HCMD_ACTIVE,
1586 &trans->status),
1587 HOST_COMPLETE_TIMEOUT);
1588 if (!ret) {
1589 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1590 struct iwl_queue *q = &txq->q;
1591
1592 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
1593 get_cmd_string(trans_pcie, cmd->id),
1594 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1595
1596 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
1597 q->read_ptr, q->write_ptr);
1598
1599 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1600 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1601 get_cmd_string(trans_pcie, cmd->id));
1602 ret = -ETIMEDOUT;
1603
1604 iwl_force_nmi(trans);
1605 iwl_trans_fw_error(trans);
1606
1607 goto cancel;
1608 }
1609
1610 if (test_bit(STATUS_FW_ERROR, &trans->status)) {
1611 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
1612 get_cmd_string(trans_pcie, cmd->id));
1613 dump_stack();
1614 ret = -EIO;
1615 goto cancel;
1616 }
1617
1618 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1619 test_bit(STATUS_RFKILL, &trans->status)) {
1620 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1621 ret = -ERFKILL;
1622 goto cancel;
1623 }
1624
1625 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1626 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1627 get_cmd_string(trans_pcie, cmd->id));
1628 ret = -EIO;
1629 goto cancel;
1630 }
1631
1632 return 0;
1633
1634 cancel:
1635 if (cmd->flags & CMD_WANT_SKB) {
1636 /*
1637 * Cancel the CMD_WANT_SKB flag for the cmd in the
1638 * TX cmd queue. Otherwise in case the cmd comes
1639 * in later, it will possibly set an invalid
1640 * address (cmd->meta.source).
1641 */
1642 trans_pcie->txq[trans_pcie->cmd_queue].
1643 entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
1644 }
1645
1646 if (cmd->resp_pkt) {
1647 iwl_free_resp(cmd);
1648 cmd->resp_pkt = NULL;
1649 }
1650
1651 return ret;
1652 }
1653
1654 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1655 {
1656 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1657 test_bit(STATUS_RFKILL, &trans->status)) {
1658 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1659 cmd->id);
1660 return -ERFKILL;
1661 }
1662
1663 if (cmd->flags & CMD_ASYNC)
1664 return iwl_pcie_send_hcmd_async(trans, cmd);
1665
1666 /* We still can fail on RFKILL that can be asserted while we wait */
1667 return iwl_pcie_send_hcmd_sync(trans, cmd);
1668 }
1669
1670 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1671 struct iwl_device_cmd *dev_cmd, int txq_id)
1672 {
1673 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1674 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1675 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
1676 struct iwl_cmd_meta *out_meta;
1677 struct iwl_txq *txq;
1678 struct iwl_queue *q;
1679 dma_addr_t tb0_phys, tb1_phys, scratch_phys;
1680 void *tb1_addr;
1681 u16 len, tb1_len, tb2_len;
1682 bool wait_write_ptr;
1683 __le16 fc = hdr->frame_control;
1684 u8 hdr_len = ieee80211_hdrlen(fc);
1685 u16 wifi_seq;
1686
1687 txq = &trans_pcie->txq[txq_id];
1688 q = &txq->q;
1689
1690 if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
1691 "TX on unused queue %d\n", txq_id))
1692 return -EINVAL;
1693
1694 spin_lock(&txq->lock);
1695
1696 /* In AGG mode, the index in the ring must correspond to the WiFi
1697 * sequence number. This is a HW requirements to help the SCD to parse
1698 * the BA.
1699 * Check here that the packets are in the right place on the ring.
1700 */
1701 wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1702 WARN_ONCE(txq->ampdu &&
1703 (wifi_seq & 0xff) != q->write_ptr,
1704 "Q: %d WiFi Seq %d tfdNum %d",
1705 txq_id, wifi_seq, q->write_ptr);
1706
1707 /* Set up driver data for this TFD */
1708 txq->entries[q->write_ptr].skb = skb;
1709 txq->entries[q->write_ptr].cmd = dev_cmd;
1710
1711 dev_cmd->hdr.sequence =
1712 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1713 INDEX_TO_SEQ(q->write_ptr)));
1714
1715 tb0_phys = iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr);
1716 scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
1717 offsetof(struct iwl_tx_cmd, scratch);
1718
1719 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1720 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1721
1722 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1723 out_meta = &txq->entries[q->write_ptr].meta;
1724
1725 /*
1726 * The second TB (tb1) points to the remainder of the TX command
1727 * and the 802.11 header - dword aligned size
1728 * (This calculation modifies the TX command, so do it before the
1729 * setup of the first TB)
1730 */
1731 len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
1732 hdr_len - IWL_HCMD_SCRATCHBUF_SIZE;
1733 tb1_len = ALIGN(len, 4);
1734
1735 /* Tell NIC about any 2-byte padding after MAC header */
1736 if (tb1_len != len)
1737 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1738
1739 /* The first TB points to the scratchbuf data - min_copy bytes */
1740 memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr,
1741 IWL_HCMD_SCRATCHBUF_SIZE);
1742 iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
1743 IWL_HCMD_SCRATCHBUF_SIZE, true);
1744
1745 /* there must be data left over for TB1 or this code must be changed */
1746 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE);
1747
1748 /* map the data for TB1 */
1749 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_HCMD_SCRATCHBUF_SIZE;
1750 tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
1751 if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
1752 goto out_err;
1753 iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false);
1754
1755 /*
1756 * Set up TFD's third entry to point directly to remainder
1757 * of skb, if any (802.11 null frames have no payload).
1758 */
1759 tb2_len = skb->len - hdr_len;
1760 if (tb2_len > 0) {
1761 dma_addr_t tb2_phys = dma_map_single(trans->dev,
1762 skb->data + hdr_len,
1763 tb2_len, DMA_TO_DEVICE);
1764 if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) {
1765 iwl_pcie_tfd_unmap(trans, out_meta,
1766 &txq->tfds[q->write_ptr]);
1767 goto out_err;
1768 }
1769 iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false);
1770 }
1771
1772 /* Set up entry for this TFD in Tx byte-count array */
1773 iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1774
1775 trace_iwlwifi_dev_tx(trans->dev, skb,
1776 &txq->tfds[txq->q.write_ptr],
1777 sizeof(struct iwl_tfd),
1778 &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len,
1779 skb->data + hdr_len, tb2_len);
1780 trace_iwlwifi_dev_tx_data(trans->dev, skb,
1781 skb->data + hdr_len, tb2_len);
1782
1783 wait_write_ptr = ieee80211_has_morefrags(fc);
1784
1785 /* start timer if queue currently empty */
1786 if (txq->need_update && q->read_ptr == q->write_ptr &&
1787 trans_pcie->wd_timeout)
1788 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1789
1790 /* Tell device the write index *just past* this latest filled TFD */
1791 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);
1792 if (!wait_write_ptr)
1793 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1794
1795 /*
1796 * At this point the frame is "transmitted" successfully
1797 * and we will get a TX status notification eventually.
1798 */
1799 if (iwl_queue_space(q) < q->high_mark) {
1800 if (wait_write_ptr)
1801 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1802 else
1803 iwl_stop_queue(trans, txq);
1804 }
1805 spin_unlock(&txq->lock);
1806 return 0;
1807 out_err:
1808 spin_unlock(&txq->lock);
1809 return -1;
1810 }
Linux kernel - Deliverables
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