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iwlwifi: mvm: Disable uAPSD for D3 image
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / pcie / tx.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/slab.h>
31 #include <linux/sched.h>
32
33 #include "iwl-debug.h"
34 #include "iwl-csr.h"
35 #include "iwl-prph.h"
36 #include "iwl-io.h"
37 #include "iwl-op-mode.h"
38 #include "internal.h"
39 /* FIXME: need to abstract out TX command (once we know what it looks like) */
40 #include "dvm/commands.h"
41
42 #define IWL_TX_CRC_SIZE 4
43 #define IWL_TX_DELIMITER_SIZE 4
44
45 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
46 * DMA services
47 *
48 * Theory of operation
49 *
50 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
51 * of buffer descriptors, each of which points to one or more data buffers for
52 * the device to read from or fill. Driver and device exchange status of each
53 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
54 * entries in each circular buffer, to protect against confusing empty and full
55 * queue states.
56 *
57 * The device reads or writes the data in the queues via the device's several
58 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
59 *
60 * For Tx queue, there are low mark and high mark limits. If, after queuing
61 * the packet for Tx, free space become < low mark, Tx queue stopped. When
62 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
63 * Tx queue resumed.
64 *
65 ***************************************************/
66 static int iwl_queue_space(const struct iwl_queue *q)
67 {
68 unsigned int max;
69 unsigned int used;
70
71 /*
72 * To avoid ambiguity between empty and completely full queues, there
73 * should always be less than q->n_bd elements in the queue.
74 * If q->n_window is smaller than q->n_bd, there is no need to reserve
75 * any queue entries for this purpose.
76 */
77 if (q->n_window < q->n_bd)
78 max = q->n_window;
79 else
80 max = q->n_bd - 1;
81
82 /*
83 * q->n_bd is a power of 2, so the following is equivalent to modulo by
84 * q->n_bd and is well defined for negative dividends.
85 */
86 used = (q->write_ptr - q->read_ptr) & (q->n_bd - 1);
87
88 if (WARN_ON(used > max))
89 return 0;
90
91 return max - used;
92 }
93
94 /*
95 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
96 */
97 static int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id)
98 {
99 q->n_bd = count;
100 q->n_window = slots_num;
101 q->id = id;
102
103 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
104 * and iwl_queue_dec_wrap are broken. */
105 if (WARN_ON(!is_power_of_2(count)))
106 return -EINVAL;
107
108 /* slots_num must be power-of-two size, otherwise
109 * get_cmd_index is broken. */
110 if (WARN_ON(!is_power_of_2(slots_num)))
111 return -EINVAL;
112
113 q->low_mark = q->n_window / 4;
114 if (q->low_mark < 4)
115 q->low_mark = 4;
116
117 q->high_mark = q->n_window / 8;
118 if (q->high_mark < 2)
119 q->high_mark = 2;
120
121 q->write_ptr = 0;
122 q->read_ptr = 0;
123
124 return 0;
125 }
126
127 static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
128 struct iwl_dma_ptr *ptr, size_t size)
129 {
130 if (WARN_ON(ptr->addr))
131 return -EINVAL;
132
133 ptr->addr = dma_alloc_coherent(trans->dev, size,
134 &ptr->dma, GFP_KERNEL);
135 if (!ptr->addr)
136 return -ENOMEM;
137 ptr->size = size;
138 return 0;
139 }
140
141 static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans,
142 struct iwl_dma_ptr *ptr)
143 {
144 if (unlikely(!ptr->addr))
145 return;
146
147 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
148 memset(ptr, 0, sizeof(*ptr));
149 }
150
151 static void iwl_pcie_txq_stuck_timer(unsigned long data)
152 {
153 struct iwl_txq *txq = (void *)data;
154 struct iwl_queue *q = &txq->q;
155 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
156 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
157 u32 scd_sram_addr = trans_pcie->scd_base_addr +
158 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
159 u8 buf[16];
160 int i;
161
162 spin_lock(&txq->lock);
163 /* check if triggered erroneously */
164 if (txq->q.read_ptr == txq->q.write_ptr) {
165 spin_unlock(&txq->lock);
166 return;
167 }
168 spin_unlock(&txq->lock);
169
170 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
171 jiffies_to_msecs(trans_pcie->wd_timeout));
172 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
173 txq->q.read_ptr, txq->q.write_ptr);
174
175 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
176
177 iwl_print_hex_error(trans, buf, sizeof(buf));
178
179 for (i = 0; i < FH_TCSR_CHNL_NUM; i++)
180 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i,
181 iwl_read_direct32(trans, FH_TX_TRB_REG(i)));
182
183 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
184 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i));
185 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
186 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
187 u32 tbl_dw =
188 iwl_trans_read_mem32(trans,
189 trans_pcie->scd_base_addr +
190 SCD_TRANS_TBL_OFFSET_QUEUE(i));
191
192 if (i & 0x1)
193 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
194 else
195 tbl_dw = tbl_dw & 0x0000FFFF;
196
197 IWL_ERR(trans,
198 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
199 i, active ? "" : "in", fifo, tbl_dw,
200 iwl_read_prph(trans,
201 SCD_QUEUE_RDPTR(i)) & (txq->q.n_bd - 1),
202 iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
203 }
204
205 for (i = q->read_ptr; i != q->write_ptr;
206 i = iwl_queue_inc_wrap(i, q->n_bd))
207 IWL_ERR(trans, "scratch %d = 0x%08x\n", i,
208 le32_to_cpu(txq->scratchbufs[i].scratch));
209
210 iwl_op_mode_nic_error(trans->op_mode);
211 }
212
213 /*
214 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
215 */
216 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
217 struct iwl_txq *txq, u16 byte_cnt)
218 {
219 struct iwlagn_scd_bc_tbl *scd_bc_tbl;
220 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
221 int write_ptr = txq->q.write_ptr;
222 int txq_id = txq->q.id;
223 u8 sec_ctl = 0;
224 u8 sta_id = 0;
225 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
226 __le16 bc_ent;
227 struct iwl_tx_cmd *tx_cmd =
228 (void *) txq->entries[txq->q.write_ptr].cmd->payload;
229
230 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
231
232 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
233
234 sta_id = tx_cmd->sta_id;
235 sec_ctl = tx_cmd->sec_ctl;
236
237 switch (sec_ctl & TX_CMD_SEC_MSK) {
238 case TX_CMD_SEC_CCM:
239 len += IEEE80211_CCMP_MIC_LEN;
240 break;
241 case TX_CMD_SEC_TKIP:
242 len += IEEE80211_TKIP_ICV_LEN;
243 break;
244 case TX_CMD_SEC_WEP:
245 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
246 break;
247 }
248
249 if (trans_pcie->bc_table_dword)
250 len = DIV_ROUND_UP(len, 4);
251
252 bc_ent = cpu_to_le16(len | (sta_id << 12));
253
254 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
255
256 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
257 scd_bc_tbl[txq_id].
258 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
259 }
260
261 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
262 struct iwl_txq *txq)
263 {
264 struct iwl_trans_pcie *trans_pcie =
265 IWL_TRANS_GET_PCIE_TRANS(trans);
266 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
267 int txq_id = txq->q.id;
268 int read_ptr = txq->q.read_ptr;
269 u8 sta_id = 0;
270 __le16 bc_ent;
271 struct iwl_tx_cmd *tx_cmd =
272 (void *)txq->entries[txq->q.read_ptr].cmd->payload;
273
274 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
275
276 if (txq_id != trans_pcie->cmd_queue)
277 sta_id = tx_cmd->sta_id;
278
279 bc_ent = cpu_to_le16(1 | (sta_id << 12));
280 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
281
282 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
283 scd_bc_tbl[txq_id].
284 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
285 }
286
287 /*
288 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
289 */
290 void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_txq *txq)
291 {
292 u32 reg = 0;
293 int txq_id = txq->q.id;
294
295 if (txq->need_update == 0)
296 return;
297
298 if (trans->cfg->base_params->shadow_reg_enable) {
299 /* shadow register enabled */
300 iwl_write32(trans, HBUS_TARG_WRPTR,
301 txq->q.write_ptr | (txq_id << 8));
302 } else {
303 struct iwl_trans_pcie *trans_pcie =
304 IWL_TRANS_GET_PCIE_TRANS(trans);
305 /* if we're trying to save power */
306 if (test_bit(STATUS_TPOWER_PMI, &trans_pcie->status)) {
307 /* wake up nic if it's powered down ...
308 * uCode will wake up, and interrupt us again, so next
309 * time we'll skip this part. */
310 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
311
312 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
313 IWL_DEBUG_INFO(trans,
314 "Tx queue %d requesting wakeup,"
315 " GP1 = 0x%x\n", txq_id, reg);
316 iwl_set_bit(trans, CSR_GP_CNTRL,
317 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
318 return;
319 }
320
321 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id,
322 txq->q.write_ptr);
323
324 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
325 txq->q.write_ptr | (txq_id << 8));
326
327 /*
328 * else not in power-save mode,
329 * uCode will never sleep when we're
330 * trying to tx (during RFKILL, we're not trying to tx).
331 */
332 } else
333 iwl_write32(trans, HBUS_TARG_WRPTR,
334 txq->q.write_ptr | (txq_id << 8));
335 }
336 txq->need_update = 0;
337 }
338
339 static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
340 {
341 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
342
343 dma_addr_t addr = get_unaligned_le32(&tb->lo);
344 if (sizeof(dma_addr_t) > sizeof(u32))
345 addr |=
346 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
347
348 return addr;
349 }
350
351 static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
352 {
353 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
354
355 return le16_to_cpu(tb->hi_n_len) >> 4;
356 }
357
358 static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
359 dma_addr_t addr, u16 len)
360 {
361 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
362 u16 hi_n_len = len << 4;
363
364 put_unaligned_le32(addr, &tb->lo);
365 if (sizeof(dma_addr_t) > sizeof(u32))
366 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
367
368 tb->hi_n_len = cpu_to_le16(hi_n_len);
369
370 tfd->num_tbs = idx + 1;
371 }
372
373 static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd)
374 {
375 return tfd->num_tbs & 0x1f;
376 }
377
378 static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
379 struct iwl_cmd_meta *meta,
380 struct iwl_tfd *tfd)
381 {
382 int i;
383 int num_tbs;
384
385 /* Sanity check on number of chunks */
386 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
387
388 if (num_tbs >= IWL_NUM_OF_TBS) {
389 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
390 /* @todo issue fatal error, it is quite serious situation */
391 return;
392 }
393
394 /* first TB is never freed - it's the scratchbuf data */
395
396 for (i = 1; i < num_tbs; i++)
397 dma_unmap_single(trans->dev, iwl_pcie_tfd_tb_get_addr(tfd, i),
398 iwl_pcie_tfd_tb_get_len(tfd, i),
399 DMA_TO_DEVICE);
400
401 tfd->num_tbs = 0;
402 }
403
404 /*
405 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
406 * @trans - transport private data
407 * @txq - tx queue
408 * @dma_dir - the direction of the DMA mapping
409 *
410 * Does NOT advance any TFD circular buffer read/write indexes
411 * Does NOT free the TFD itself (which is within circular buffer)
412 */
413 static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
414 {
415 struct iwl_tfd *tfd_tmp = txq->tfds;
416
417 /* rd_ptr is bounded by n_bd and idx is bounded by n_window */
418 int rd_ptr = txq->q.read_ptr;
419 int idx = get_cmd_index(&txq->q, rd_ptr);
420
421 lockdep_assert_held(&txq->lock);
422
423 /* We have only q->n_window txq->entries, but we use q->n_bd tfds */
424 iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]);
425
426 /* free SKB */
427 if (txq->entries) {
428 struct sk_buff *skb;
429
430 skb = txq->entries[idx].skb;
431
432 /* Can be called from irqs-disabled context
433 * If skb is not NULL, it means that the whole queue is being
434 * freed and that the queue is not empty - free the skb
435 */
436 if (skb) {
437 iwl_op_mode_free_skb(trans->op_mode, skb);
438 txq->entries[idx].skb = NULL;
439 }
440 }
441 }
442
443 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
444 dma_addr_t addr, u16 len, u8 reset)
445 {
446 struct iwl_queue *q;
447 struct iwl_tfd *tfd, *tfd_tmp;
448 u32 num_tbs;
449
450 q = &txq->q;
451 tfd_tmp = txq->tfds;
452 tfd = &tfd_tmp[q->write_ptr];
453
454 if (reset)
455 memset(tfd, 0, sizeof(*tfd));
456
457 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
458
459 /* Each TFD can point to a maximum 20 Tx buffers */
460 if (num_tbs >= IWL_NUM_OF_TBS) {
461 IWL_ERR(trans, "Error can not send more than %d chunks\n",
462 IWL_NUM_OF_TBS);
463 return -EINVAL;
464 }
465
466 if (WARN(addr & ~IWL_TX_DMA_MASK,
467 "Unaligned address = %llx\n", (unsigned long long)addr))
468 return -EINVAL;
469
470 iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len);
471
472 return 0;
473 }
474
475 static int iwl_pcie_txq_alloc(struct iwl_trans *trans,
476 struct iwl_txq *txq, int slots_num,
477 u32 txq_id)
478 {
479 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
480 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
481 size_t scratchbuf_sz;
482 int i;
483
484 if (WARN_ON(txq->entries || txq->tfds))
485 return -EINVAL;
486
487 setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer,
488 (unsigned long)txq);
489 txq->trans_pcie = trans_pcie;
490
491 txq->q.n_window = slots_num;
492
493 txq->entries = kcalloc(slots_num,
494 sizeof(struct iwl_pcie_txq_entry),
495 GFP_KERNEL);
496
497 if (!txq->entries)
498 goto error;
499
500 if (txq_id == trans_pcie->cmd_queue)
501 for (i = 0; i < slots_num; i++) {
502 txq->entries[i].cmd =
503 kmalloc(sizeof(struct iwl_device_cmd),
504 GFP_KERNEL);
505 if (!txq->entries[i].cmd)
506 goto error;
507 }
508
509 /* Circular buffer of transmit frame descriptors (TFDs),
510 * shared with device */
511 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
512 &txq->q.dma_addr, GFP_KERNEL);
513 if (!txq->tfds)
514 goto error;
515
516 BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE != sizeof(*txq->scratchbufs));
517 BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf, scratch) !=
518 sizeof(struct iwl_cmd_header) +
519 offsetof(struct iwl_tx_cmd, scratch));
520
521 scratchbuf_sz = sizeof(*txq->scratchbufs) * slots_num;
522
523 txq->scratchbufs = dma_alloc_coherent(trans->dev, scratchbuf_sz,
524 &txq->scratchbufs_dma,
525 GFP_KERNEL);
526 if (!txq->scratchbufs)
527 goto err_free_tfds;
528
529 txq->q.id = txq_id;
530
531 return 0;
532 err_free_tfds:
533 dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr);
534 error:
535 if (txq->entries && txq_id == trans_pcie->cmd_queue)
536 for (i = 0; i < slots_num; i++)
537 kfree(txq->entries[i].cmd);
538 kfree(txq->entries);
539 txq->entries = NULL;
540
541 return -ENOMEM;
542
543 }
544
545 static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
546 int slots_num, u32 txq_id)
547 {
548 int ret;
549
550 txq->need_update = 0;
551
552 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
553 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
554 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
555
556 /* Initialize queue's high/low-water marks, and head/tail indexes */
557 ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
558 txq_id);
559 if (ret)
560 return ret;
561
562 spin_lock_init(&txq->lock);
563
564 /*
565 * Tell nic where to find circular buffer of Tx Frame Descriptors for
566 * given Tx queue, and enable the DMA channel used for that queue.
567 * Circular buffer (TFD queue in DRAM) physical base address */
568 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
569 txq->q.dma_addr >> 8);
570
571 return 0;
572 }
573
574 /*
575 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's
576 */
577 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
578 {
579 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
580 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
581 struct iwl_queue *q = &txq->q;
582
583 if (!q->n_bd)
584 return;
585
586 spin_lock_bh(&txq->lock);
587 while (q->write_ptr != q->read_ptr) {
588 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
589 txq_id, q->read_ptr);
590 iwl_pcie_txq_free_tfd(trans, txq);
591 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
592 }
593 txq->active = false;
594 spin_unlock_bh(&txq->lock);
595
596 /* just in case - this queue may have been stopped */
597 iwl_wake_queue(trans, txq);
598 }
599
600 /*
601 * iwl_pcie_txq_free - Deallocate DMA queue.
602 * @txq: Transmit queue to deallocate.
603 *
604 * Empty queue by removing and destroying all BD's.
605 * Free all buffers.
606 * 0-fill, but do not free "txq" descriptor structure.
607 */
608 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
609 {
610 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
611 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
612 struct device *dev = trans->dev;
613 int i;
614
615 if (WARN_ON(!txq))
616 return;
617
618 iwl_pcie_txq_unmap(trans, txq_id);
619
620 /* De-alloc array of command/tx buffers */
621 if (txq_id == trans_pcie->cmd_queue)
622 for (i = 0; i < txq->q.n_window; i++) {
623 kfree(txq->entries[i].cmd);
624 kfree(txq->entries[i].free_buf);
625 }
626
627 /* De-alloc circular buffer of TFDs */
628 if (txq->q.n_bd) {
629 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
630 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
631 txq->q.dma_addr = 0;
632
633 dma_free_coherent(dev,
634 sizeof(*txq->scratchbufs) * txq->q.n_window,
635 txq->scratchbufs, txq->scratchbufs_dma);
636 }
637
638 kfree(txq->entries);
639 txq->entries = NULL;
640
641 del_timer_sync(&txq->stuck_timer);
642
643 /* 0-fill queue descriptor structure */
644 memset(txq, 0, sizeof(*txq));
645 }
646
647 /*
648 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
649 */
650 static void iwl_pcie_txq_set_sched(struct iwl_trans *trans, u32 mask)
651 {
652 struct iwl_trans_pcie __maybe_unused *trans_pcie =
653 IWL_TRANS_GET_PCIE_TRANS(trans);
654
655 iwl_write_prph(trans, SCD_TXFACT, mask);
656 }
657
658 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
659 {
660 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
661 int nq = trans->cfg->base_params->num_of_queues;
662 int chan;
663 u32 reg_val;
664 int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
665 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
666
667 /* make sure all queue are not stopped/used */
668 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
669 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
670
671 trans_pcie->scd_base_addr =
672 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
673
674 WARN_ON(scd_base_addr != 0 &&
675 scd_base_addr != trans_pcie->scd_base_addr);
676
677 /* reset context data, TX status and translation data */
678 iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
679 SCD_CONTEXT_MEM_LOWER_BOUND,
680 NULL, clear_dwords);
681
682 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
683 trans_pcie->scd_bc_tbls.dma >> 10);
684
685 /* The chain extension of the SCD doesn't work well. This feature is
686 * enabled by default by the HW, so we need to disable it manually.
687 */
688 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
689
690 iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
691 trans_pcie->cmd_fifo);
692
693 /* Activate all Tx DMA/FIFO channels */
694 iwl_pcie_txq_set_sched(trans, IWL_MASK(0, 7));
695
696 /* Enable DMA channel */
697 for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
698 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
699 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
700 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
701
702 /* Update FH chicken bits */
703 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
704 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
705 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
706
707 /* Enable L1-Active */
708 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
709 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
710 }
711
712 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
713 {
714 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
715 int txq_id;
716
717 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
718 txq_id++) {
719 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
720
721 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
722 txq->q.dma_addr >> 8);
723 iwl_pcie_txq_unmap(trans, txq_id);
724 txq->q.read_ptr = 0;
725 txq->q.write_ptr = 0;
726 }
727
728 /* Tell NIC where to find the "keep warm" buffer */
729 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
730 trans_pcie->kw.dma >> 4);
731
732 iwl_pcie_tx_start(trans, trans_pcie->scd_base_addr);
733 }
734
735 /*
736 * iwl_pcie_tx_stop - Stop all Tx DMA channels
737 */
738 int iwl_pcie_tx_stop(struct iwl_trans *trans)
739 {
740 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
741 int ch, txq_id, ret;
742 unsigned long flags;
743
744 /* Turn off all Tx DMA fifos */
745 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
746
747 iwl_pcie_txq_set_sched(trans, 0);
748
749 /* Stop each Tx DMA channel, and wait for it to be idle */
750 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
751 iwl_write_direct32(trans,
752 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
753 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
754 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000);
755 if (ret < 0)
756 IWL_ERR(trans,
757 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
758 ch,
759 iwl_read_direct32(trans,
760 FH_TSSR_TX_STATUS_REG));
761 }
762 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
763
764 if (!trans_pcie->txq) {
765 IWL_WARN(trans,
766 "Stopping tx queues that aren't allocated...\n");
767 return 0;
768 }
769
770 /* Unmap DMA from host system and free skb's */
771 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
772 txq_id++)
773 iwl_pcie_txq_unmap(trans, txq_id);
774
775 return 0;
776 }
777
778 /*
779 * iwl_trans_tx_free - Free TXQ Context
780 *
781 * Destroy all TX DMA queues and structures
782 */
783 void iwl_pcie_tx_free(struct iwl_trans *trans)
784 {
785 int txq_id;
786 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
787
788 /* Tx queues */
789 if (trans_pcie->txq) {
790 for (txq_id = 0;
791 txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
792 iwl_pcie_txq_free(trans, txq_id);
793 }
794
795 kfree(trans_pcie->txq);
796 trans_pcie->txq = NULL;
797
798 iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
799
800 iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
801 }
802
803 /*
804 * iwl_pcie_tx_alloc - allocate TX context
805 * Allocate all Tx DMA structures and initialize them
806 */
807 static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
808 {
809 int ret;
810 int txq_id, slots_num;
811 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
812
813 u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
814 sizeof(struct iwlagn_scd_bc_tbl);
815
816 /*It is not allowed to alloc twice, so warn when this happens.
817 * We cannot rely on the previous allocation, so free and fail */
818 if (WARN_ON(trans_pcie->txq)) {
819 ret = -EINVAL;
820 goto error;
821 }
822
823 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
824 scd_bc_tbls_size);
825 if (ret) {
826 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
827 goto error;
828 }
829
830 /* Alloc keep-warm buffer */
831 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
832 if (ret) {
833 IWL_ERR(trans, "Keep Warm allocation failed\n");
834 goto error;
835 }
836
837 trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
838 sizeof(struct iwl_txq), GFP_KERNEL);
839 if (!trans_pcie->txq) {
840 IWL_ERR(trans, "Not enough memory for txq\n");
841 ret = -ENOMEM;
842 goto error;
843 }
844
845 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
846 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
847 txq_id++) {
848 slots_num = (txq_id == trans_pcie->cmd_queue) ?
849 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
850 ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id],
851 slots_num, txq_id);
852 if (ret) {
853 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
854 goto error;
855 }
856 }
857
858 return 0;
859
860 error:
861 iwl_pcie_tx_free(trans);
862
863 return ret;
864 }
865 int iwl_pcie_tx_init(struct iwl_trans *trans)
866 {
867 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
868 int ret;
869 int txq_id, slots_num;
870 unsigned long flags;
871 bool alloc = false;
872
873 if (!trans_pcie->txq) {
874 ret = iwl_pcie_tx_alloc(trans);
875 if (ret)
876 goto error;
877 alloc = true;
878 }
879
880 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
881
882 /* Turn off all Tx DMA fifos */
883 iwl_write_prph(trans, SCD_TXFACT, 0);
884
885 /* Tell NIC where to find the "keep warm" buffer */
886 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
887 trans_pcie->kw.dma >> 4);
888
889 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
890
891 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
892 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
893 txq_id++) {
894 slots_num = (txq_id == trans_pcie->cmd_queue) ?
895 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
896 ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id],
897 slots_num, txq_id);
898 if (ret) {
899 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
900 goto error;
901 }
902 }
903
904 return 0;
905 error:
906 /*Upon error, free only if we allocated something */
907 if (alloc)
908 iwl_pcie_tx_free(trans);
909 return ret;
910 }
911
912 static inline void iwl_pcie_txq_progress(struct iwl_trans_pcie *trans_pcie,
913 struct iwl_txq *txq)
914 {
915 if (!trans_pcie->wd_timeout)
916 return;
917
918 /*
919 * if empty delete timer, otherwise move timer forward
920 * since we're making progress on this queue
921 */
922 if (txq->q.read_ptr == txq->q.write_ptr)
923 del_timer(&txq->stuck_timer);
924 else
925 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
926 }
927
928 /* Frees buffers until index _not_ inclusive */
929 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
930 struct sk_buff_head *skbs)
931 {
932 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
933 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
934 /* n_bd is usually 256 => n_bd - 1 = 0xff */
935 int tfd_num = ssn & (txq->q.n_bd - 1);
936 struct iwl_queue *q = &txq->q;
937 int last_to_free;
938
939 /* This function is not meant to release cmd queue*/
940 if (WARN_ON(txq_id == trans_pcie->cmd_queue))
941 return;
942
943 spin_lock_bh(&txq->lock);
944
945 if (!txq->active) {
946 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
947 txq_id, ssn);
948 goto out;
949 }
950
951 if (txq->q.read_ptr == tfd_num)
952 goto out;
953
954 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
955 txq_id, txq->q.read_ptr, tfd_num, ssn);
956
957 /*Since we free until index _not_ inclusive, the one before index is
958 * the last we will free. This one must be used */
959 last_to_free = iwl_queue_dec_wrap(tfd_num, q->n_bd);
960
961 if (!iwl_queue_used(q, last_to_free)) {
962 IWL_ERR(trans,
963 "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
964 __func__, txq_id, last_to_free, q->n_bd,
965 q->write_ptr, q->read_ptr);
966 goto out;
967 }
968
969 if (WARN_ON(!skb_queue_empty(skbs)))
970 goto out;
971
972 for (;
973 q->read_ptr != tfd_num;
974 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
975
976 if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL))
977 continue;
978
979 __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb);
980
981 txq->entries[txq->q.read_ptr].skb = NULL;
982
983 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
984
985 iwl_pcie_txq_free_tfd(trans, txq);
986 }
987
988 iwl_pcie_txq_progress(trans_pcie, txq);
989
990 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
991 iwl_wake_queue(trans, txq);
992 out:
993 spin_unlock_bh(&txq->lock);
994 }
995
996 /*
997 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
998 *
999 * When FW advances 'R' index, all entries between old and new 'R' index
1000 * need to be reclaimed. As result, some free space forms. If there is
1001 * enough free space (> low mark), wake the stack that feeds us.
1002 */
1003 static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
1004 {
1005 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1006 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1007 struct iwl_queue *q = &txq->q;
1008 int nfreed = 0;
1009
1010 lockdep_assert_held(&txq->lock);
1011
1012 if ((idx >= q->n_bd) || (!iwl_queue_used(q, idx))) {
1013 IWL_ERR(trans,
1014 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1015 __func__, txq_id, idx, q->n_bd,
1016 q->write_ptr, q->read_ptr);
1017 return;
1018 }
1019
1020 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
1021 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1022
1023 if (nfreed++ > 0) {
1024 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1025 idx, q->write_ptr, q->read_ptr);
1026 iwl_op_mode_nic_error(trans->op_mode);
1027 }
1028 }
1029
1030 iwl_pcie_txq_progress(trans_pcie, txq);
1031 }
1032
1033 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1034 u16 txq_id)
1035 {
1036 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1037 u32 tbl_dw_addr;
1038 u32 tbl_dw;
1039 u16 scd_q2ratid;
1040
1041 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1042
1043 tbl_dw_addr = trans_pcie->scd_base_addr +
1044 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1045
1046 tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1047
1048 if (txq_id & 0x1)
1049 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1050 else
1051 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1052
1053 iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1054
1055 return 0;
1056 }
1057
1058 static inline void iwl_pcie_txq_set_inactive(struct iwl_trans *trans,
1059 u16 txq_id)
1060 {
1061 /* Simply stop the queue, but don't change any configuration;
1062 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1063 iwl_write_prph(trans,
1064 SCD_QUEUE_STATUS_BITS(txq_id),
1065 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1066 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
1067 }
1068
1069 /* Receiver address (actually, Rx station's index into station table),
1070 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1071 #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
1072
1073 void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo,
1074 int sta_id, int tid, int frame_limit, u16 ssn)
1075 {
1076 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1077
1078 if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1079 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1080
1081 /* Stop this Tx queue before configuring it */
1082 iwl_pcie_txq_set_inactive(trans, txq_id);
1083
1084 /* Set this queue as a chain-building queue unless it is CMD queue */
1085 if (txq_id != trans_pcie->cmd_queue)
1086 iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id));
1087
1088 /* If this queue is mapped to a certain station: it is an AGG queue */
1089 if (sta_id >= 0) {
1090 u16 ra_tid = BUILD_RAxTID(sta_id, tid);
1091
1092 /* Map receiver-address / traffic-ID to this queue */
1093 iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1094
1095 /* enable aggregations for the queue */
1096 iwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));
1097 trans_pcie->txq[txq_id].ampdu = true;
1098 } else {
1099 /*
1100 * disable aggregations for the queue, this will also make the
1101 * ra_tid mapping configuration irrelevant since it is now a
1102 * non-AGG queue.
1103 */
1104 iwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));
1105 }
1106
1107 /* Place first TFD at index corresponding to start sequence number.
1108 * Assumes that ssn_idx is valid (!= 0xFFF) */
1109 trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff);
1110 trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff);
1111
1112 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1113 (ssn & 0xff) | (txq_id << 8));
1114 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1115
1116 /* Set up Tx window size and frame limit for this queue */
1117 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1118 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1119 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1120 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1121 ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1122 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1123 ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1124 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1125
1126 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1127 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1128 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1129 (fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1130 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1131 SCD_QUEUE_STTS_REG_MSK);
1132 trans_pcie->txq[txq_id].active = true;
1133 IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d on FIFO %d WrPtr: %d\n",
1134 txq_id, fifo, ssn & 0xff);
1135 }
1136
1137 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id)
1138 {
1139 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1140 u32 stts_addr = trans_pcie->scd_base_addr +
1141 SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1142 static const u32 zero_val[4] = {};
1143
1144 if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
1145 WARN_ONCE(1, "queue %d not used", txq_id);
1146 return;
1147 }
1148
1149 iwl_pcie_txq_set_inactive(trans, txq_id);
1150
1151 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1152 ARRAY_SIZE(zero_val));
1153
1154 iwl_pcie_txq_unmap(trans, txq_id);
1155 trans_pcie->txq[txq_id].ampdu = false;
1156
1157 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1158 }
1159
1160 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1161
1162 /*
1163 * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1164 * @priv: device private data point
1165 * @cmd: a pointer to the ucode command structure
1166 *
1167 * The function returns < 0 values to indicate the operation
1168 * failed. On success, it returns the index (>= 0) of command in the
1169 * command queue.
1170 */
1171 static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1172 struct iwl_host_cmd *cmd)
1173 {
1174 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1175 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1176 struct iwl_queue *q = &txq->q;
1177 struct iwl_device_cmd *out_cmd;
1178 struct iwl_cmd_meta *out_meta;
1179 void *dup_buf = NULL;
1180 dma_addr_t phys_addr;
1181 int idx;
1182 u16 copy_size, cmd_size, scratch_size;
1183 bool had_nocopy = false;
1184 int i;
1185 u32 cmd_pos;
1186 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1187 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
1188
1189 copy_size = sizeof(out_cmd->hdr);
1190 cmd_size = sizeof(out_cmd->hdr);
1191
1192 /* need one for the header if the first is NOCOPY */
1193 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
1194
1195 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1196 cmddata[i] = cmd->data[i];
1197 cmdlen[i] = cmd->len[i];
1198
1199 if (!cmd->len[i])
1200 continue;
1201
1202 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1203 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1204 int copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1205
1206 if (copy > cmdlen[i])
1207 copy = cmdlen[i];
1208 cmdlen[i] -= copy;
1209 cmddata[i] += copy;
1210 copy_size += copy;
1211 }
1212
1213 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1214 had_nocopy = true;
1215 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1216 idx = -EINVAL;
1217 goto free_dup_buf;
1218 }
1219 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1220 /*
1221 * This is also a chunk that isn't copied
1222 * to the static buffer so set had_nocopy.
1223 */
1224 had_nocopy = true;
1225
1226 /* only allowed once */
1227 if (WARN_ON(dup_buf)) {
1228 idx = -EINVAL;
1229 goto free_dup_buf;
1230 }
1231
1232 dup_buf = kmemdup(cmddata[i], cmdlen[i],
1233 GFP_ATOMIC);
1234 if (!dup_buf)
1235 return -ENOMEM;
1236 } else {
1237 /* NOCOPY must not be followed by normal! */
1238 if (WARN_ON(had_nocopy)) {
1239 idx = -EINVAL;
1240 goto free_dup_buf;
1241 }
1242 copy_size += cmdlen[i];
1243 }
1244 cmd_size += cmd->len[i];
1245 }
1246
1247 /*
1248 * If any of the command structures end up being larger than
1249 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1250 * allocated into separate TFDs, then we will need to
1251 * increase the size of the buffers.
1252 */
1253 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1254 "Command %s (%#x) is too large (%d bytes)\n",
1255 get_cmd_string(trans_pcie, cmd->id), cmd->id, copy_size)) {
1256 idx = -EINVAL;
1257 goto free_dup_buf;
1258 }
1259
1260 spin_lock_bh(&txq->lock);
1261
1262 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1263 spin_unlock_bh(&txq->lock);
1264
1265 IWL_ERR(trans, "No space in command queue\n");
1266 iwl_op_mode_cmd_queue_full(trans->op_mode);
1267 idx = -ENOSPC;
1268 goto free_dup_buf;
1269 }
1270
1271 idx = get_cmd_index(q, q->write_ptr);
1272 out_cmd = txq->entries[idx].cmd;
1273 out_meta = &txq->entries[idx].meta;
1274
1275 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1276 if (cmd->flags & CMD_WANT_SKB)
1277 out_meta->source = cmd;
1278
1279 /* set up the header */
1280
1281 out_cmd->hdr.cmd = cmd->id;
1282 out_cmd->hdr.flags = 0;
1283 out_cmd->hdr.sequence =
1284 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1285 INDEX_TO_SEQ(q->write_ptr));
1286
1287 /* and copy the data that needs to be copied */
1288 cmd_pos = offsetof(struct iwl_device_cmd, payload);
1289 copy_size = sizeof(out_cmd->hdr);
1290 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1291 int copy = 0;
1292
1293 if (!cmd->len[i])
1294 continue;
1295
1296 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1297 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1298 copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1299
1300 if (copy > cmd->len[i])
1301 copy = cmd->len[i];
1302 }
1303
1304 /* copy everything if not nocopy/dup */
1305 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1306 IWL_HCMD_DFL_DUP)))
1307 copy = cmd->len[i];
1308
1309 if (copy) {
1310 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1311 cmd_pos += copy;
1312 copy_size += copy;
1313 }
1314 }
1315
1316 IWL_DEBUG_HC(trans,
1317 "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1318 get_cmd_string(trans_pcie, out_cmd->hdr.cmd),
1319 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
1320 cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue);
1321
1322 /* start the TFD with the scratchbuf */
1323 scratch_size = min_t(int, copy_size, IWL_HCMD_SCRATCHBUF_SIZE);
1324 memcpy(&txq->scratchbufs[q->write_ptr], &out_cmd->hdr, scratch_size);
1325 iwl_pcie_txq_build_tfd(trans, txq,
1326 iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr),
1327 scratch_size, 1);
1328
1329 /* map first command fragment, if any remains */
1330 if (copy_size > scratch_size) {
1331 phys_addr = dma_map_single(trans->dev,
1332 ((u8 *)&out_cmd->hdr) + scratch_size,
1333 copy_size - scratch_size,
1334 DMA_TO_DEVICE);
1335 if (dma_mapping_error(trans->dev, phys_addr)) {
1336 iwl_pcie_tfd_unmap(trans, out_meta,
1337 &txq->tfds[q->write_ptr]);
1338 idx = -ENOMEM;
1339 goto out;
1340 }
1341
1342 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1343 copy_size - scratch_size, 0);
1344 }
1345
1346 /* map the remaining (adjusted) nocopy/dup fragments */
1347 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1348 const void *data = cmddata[i];
1349
1350 if (!cmdlen[i])
1351 continue;
1352 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1353 IWL_HCMD_DFL_DUP)))
1354 continue;
1355 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1356 data = dup_buf;
1357 phys_addr = dma_map_single(trans->dev, (void *)data,
1358 cmdlen[i], DMA_TO_DEVICE);
1359 if (dma_mapping_error(trans->dev, phys_addr)) {
1360 iwl_pcie_tfd_unmap(trans, out_meta,
1361 &txq->tfds[q->write_ptr]);
1362 idx = -ENOMEM;
1363 goto out;
1364 }
1365
1366 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], 0);
1367 }
1368
1369 out_meta->flags = cmd->flags;
1370 if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1371 kfree(txq->entries[idx].free_buf);
1372 txq->entries[idx].free_buf = dup_buf;
1373
1374 txq->need_update = 1;
1375
1376 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr);
1377
1378 /* start timer if queue currently empty */
1379 if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout)
1380 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1381
1382 /* Increment and update queue's write index */
1383 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1384 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1385
1386 out:
1387 spin_unlock_bh(&txq->lock);
1388 free_dup_buf:
1389 if (idx < 0)
1390 kfree(dup_buf);
1391 return idx;
1392 }
1393
1394 /*
1395 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1396 * @rxb: Rx buffer to reclaim
1397 * @handler_status: return value of the handler of the command
1398 * (put in setup_rx_handlers)
1399 *
1400 * If an Rx buffer has an async callback associated with it the callback
1401 * will be executed. The attached skb (if present) will only be freed
1402 * if the callback returns 1
1403 */
1404 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1405 struct iwl_rx_cmd_buffer *rxb, int handler_status)
1406 {
1407 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1408 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1409 int txq_id = SEQ_TO_QUEUE(sequence);
1410 int index = SEQ_TO_INDEX(sequence);
1411 int cmd_index;
1412 struct iwl_device_cmd *cmd;
1413 struct iwl_cmd_meta *meta;
1414 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1415 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1416
1417 /* If a Tx command is being handled and it isn't in the actual
1418 * command queue then there a command routing bug has been introduced
1419 * in the queue management code. */
1420 if (WARN(txq_id != trans_pcie->cmd_queue,
1421 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1422 txq_id, trans_pcie->cmd_queue, sequence,
1423 trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr,
1424 trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) {
1425 iwl_print_hex_error(trans, pkt, 32);
1426 return;
1427 }
1428
1429 spin_lock_bh(&txq->lock);
1430
1431 cmd_index = get_cmd_index(&txq->q, index);
1432 cmd = txq->entries[cmd_index].cmd;
1433 meta = &txq->entries[cmd_index].meta;
1434
1435 iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]);
1436
1437 /* Input error checking is done when commands are added to queue. */
1438 if (meta->flags & CMD_WANT_SKB) {
1439 struct page *p = rxb_steal_page(rxb);
1440
1441 meta->source->resp_pkt = pkt;
1442 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1443 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1444 meta->source->handler_status = handler_status;
1445 }
1446
1447 iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1448
1449 if (!(meta->flags & CMD_ASYNC)) {
1450 if (!test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) {
1451 IWL_WARN(trans,
1452 "HCMD_ACTIVE already clear for command %s\n",
1453 get_cmd_string(trans_pcie, cmd->hdr.cmd));
1454 }
1455 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
1456 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1457 get_cmd_string(trans_pcie, cmd->hdr.cmd));
1458 wake_up(&trans_pcie->wait_command_queue);
1459 }
1460
1461 meta->flags = 0;
1462
1463 spin_unlock_bh(&txq->lock);
1464 }
1465
1466 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
1467
1468 static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1469 struct iwl_host_cmd *cmd)
1470 {
1471 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1472 int ret;
1473
1474 /* An asynchronous command can not expect an SKB to be set. */
1475 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1476 return -EINVAL;
1477
1478 ret = iwl_pcie_enqueue_hcmd(trans, cmd);
1479 if (ret < 0) {
1480 IWL_ERR(trans,
1481 "Error sending %s: enqueue_hcmd failed: %d\n",
1482 get_cmd_string(trans_pcie, cmd->id), ret);
1483 return ret;
1484 }
1485 return 0;
1486 }
1487
1488 static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1489 struct iwl_host_cmd *cmd)
1490 {
1491 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1492 int cmd_idx;
1493 int ret;
1494
1495 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1496 get_cmd_string(trans_pcie, cmd->id));
1497
1498 if (WARN_ON(test_and_set_bit(STATUS_HCMD_ACTIVE,
1499 &trans_pcie->status))) {
1500 IWL_ERR(trans, "Command %s: a command is already active!\n",
1501 get_cmd_string(trans_pcie, cmd->id));
1502 return -EIO;
1503 }
1504
1505 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1506 get_cmd_string(trans_pcie, cmd->id));
1507
1508 cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
1509 if (cmd_idx < 0) {
1510 ret = cmd_idx;
1511 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
1512 IWL_ERR(trans,
1513 "Error sending %s: enqueue_hcmd failed: %d\n",
1514 get_cmd_string(trans_pcie, cmd->id), ret);
1515 return ret;
1516 }
1517
1518 ret = wait_event_timeout(trans_pcie->wait_command_queue,
1519 !test_bit(STATUS_HCMD_ACTIVE,
1520 &trans_pcie->status),
1521 HOST_COMPLETE_TIMEOUT);
1522 if (!ret) {
1523 if (test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) {
1524 struct iwl_txq *txq =
1525 &trans_pcie->txq[trans_pcie->cmd_queue];
1526 struct iwl_queue *q = &txq->q;
1527
1528 IWL_ERR(trans,
1529 "Error sending %s: time out after %dms.\n",
1530 get_cmd_string(trans_pcie, cmd->id),
1531 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1532
1533 IWL_ERR(trans,
1534 "Current CMD queue read_ptr %d write_ptr %d\n",
1535 q->read_ptr, q->write_ptr);
1536
1537 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
1538 IWL_DEBUG_INFO(trans,
1539 "Clearing HCMD_ACTIVE for command %s\n",
1540 get_cmd_string(trans_pcie, cmd->id));
1541 ret = -ETIMEDOUT;
1542 goto cancel;
1543 }
1544 }
1545
1546 if (test_bit(STATUS_FW_ERROR, &trans_pcie->status)) {
1547 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
1548 get_cmd_string(trans_pcie, cmd->id));
1549 dump_stack();
1550 ret = -EIO;
1551 goto cancel;
1552 }
1553
1554 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1555 test_bit(STATUS_RFKILL, &trans_pcie->status)) {
1556 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1557 ret = -ERFKILL;
1558 goto cancel;
1559 }
1560
1561 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1562 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1563 get_cmd_string(trans_pcie, cmd->id));
1564 ret = -EIO;
1565 goto cancel;
1566 }
1567
1568 return 0;
1569
1570 cancel:
1571 if (cmd->flags & CMD_WANT_SKB) {
1572 /*
1573 * Cancel the CMD_WANT_SKB flag for the cmd in the
1574 * TX cmd queue. Otherwise in case the cmd comes
1575 * in later, it will possibly set an invalid
1576 * address (cmd->meta.source).
1577 */
1578 trans_pcie->txq[trans_pcie->cmd_queue].
1579 entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
1580 }
1581
1582 if (cmd->resp_pkt) {
1583 iwl_free_resp(cmd);
1584 cmd->resp_pkt = NULL;
1585 }
1586
1587 return ret;
1588 }
1589
1590 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1591 {
1592 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1593
1594 if (test_bit(STATUS_FW_ERROR, &trans_pcie->status))
1595 return -EIO;
1596
1597 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1598 test_bit(STATUS_RFKILL, &trans_pcie->status)) {
1599 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1600 cmd->id);
1601 return -ERFKILL;
1602 }
1603
1604 if (cmd->flags & CMD_ASYNC)
1605 return iwl_pcie_send_hcmd_async(trans, cmd);
1606
1607 /* We still can fail on RFKILL that can be asserted while we wait */
1608 return iwl_pcie_send_hcmd_sync(trans, cmd);
1609 }
1610
1611 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1612 struct iwl_device_cmd *dev_cmd, int txq_id)
1613 {
1614 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1615 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1616 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
1617 struct iwl_cmd_meta *out_meta;
1618 struct iwl_txq *txq;
1619 struct iwl_queue *q;
1620 dma_addr_t tb0_phys, tb1_phys, scratch_phys;
1621 void *tb1_addr;
1622 u16 len, tb1_len, tb2_len;
1623 u8 wait_write_ptr = 0;
1624 __le16 fc = hdr->frame_control;
1625 u8 hdr_len = ieee80211_hdrlen(fc);
1626 u16 wifi_seq;
1627
1628 txq = &trans_pcie->txq[txq_id];
1629 q = &txq->q;
1630
1631 if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
1632 "TX on unused queue %d\n", txq_id))
1633 return -EINVAL;
1634
1635 spin_lock(&txq->lock);
1636
1637 /* In AGG mode, the index in the ring must correspond to the WiFi
1638 * sequence number. This is a HW requirements to help the SCD to parse
1639 * the BA.
1640 * Check here that the packets are in the right place on the ring.
1641 */
1642 wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1643 WARN_ONCE(txq->ampdu &&
1644 (wifi_seq & 0xff) != q->write_ptr,
1645 "Q: %d WiFi Seq %d tfdNum %d",
1646 txq_id, wifi_seq, q->write_ptr);
1647
1648 /* Set up driver data for this TFD */
1649 txq->entries[q->write_ptr].skb = skb;
1650 txq->entries[q->write_ptr].cmd = dev_cmd;
1651
1652 dev_cmd->hdr.cmd = REPLY_TX;
1653 dev_cmd->hdr.sequence =
1654 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1655 INDEX_TO_SEQ(q->write_ptr)));
1656
1657 tb0_phys = iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr);
1658 scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
1659 offsetof(struct iwl_tx_cmd, scratch);
1660
1661 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1662 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1663
1664 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1665 out_meta = &txq->entries[q->write_ptr].meta;
1666
1667 /*
1668 * The second TB (tb1) points to the remainder of the TX command
1669 * and the 802.11 header - dword aligned size
1670 * (This calculation modifies the TX command, so do it before the
1671 * setup of the first TB)
1672 */
1673 len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
1674 hdr_len - IWL_HCMD_SCRATCHBUF_SIZE;
1675 tb1_len = ALIGN(len, 4);
1676
1677 /* Tell NIC about any 2-byte padding after MAC header */
1678 if (tb1_len != len)
1679 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1680
1681 /* The first TB points to the scratchbuf data - min_copy bytes */
1682 memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr,
1683 IWL_HCMD_SCRATCHBUF_SIZE);
1684 iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
1685 IWL_HCMD_SCRATCHBUF_SIZE, 1);
1686
1687 /* there must be data left over for TB1 or this code must be changed */
1688 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE);
1689
1690 /* map the data for TB1 */
1691 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_HCMD_SCRATCHBUF_SIZE;
1692 tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
1693 if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
1694 goto out_err;
1695 iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, 0);
1696
1697 /*
1698 * Set up TFD's third entry to point directly to remainder
1699 * of skb, if any (802.11 null frames have no payload).
1700 */
1701 tb2_len = skb->len - hdr_len;
1702 if (tb2_len > 0) {
1703 dma_addr_t tb2_phys = dma_map_single(trans->dev,
1704 skb->data + hdr_len,
1705 tb2_len, DMA_TO_DEVICE);
1706 if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) {
1707 iwl_pcie_tfd_unmap(trans, out_meta,
1708 &txq->tfds[q->write_ptr]);
1709 goto out_err;
1710 }
1711 iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, 0);
1712 }
1713
1714 /* Set up entry for this TFD in Tx byte-count array */
1715 iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1716
1717 trace_iwlwifi_dev_tx(trans->dev, skb,
1718 &txq->tfds[txq->q.write_ptr],
1719 sizeof(struct iwl_tfd),
1720 &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len,
1721 skb->data + hdr_len, tb2_len);
1722 trace_iwlwifi_dev_tx_data(trans->dev, skb,
1723 skb->data + hdr_len, tb2_len);
1724
1725 if (!ieee80211_has_morefrags(fc)) {
1726 txq->need_update = 1;
1727 } else {
1728 wait_write_ptr = 1;
1729 txq->need_update = 0;
1730 }
1731
1732 /* start timer if queue currently empty */
1733 if (txq->need_update && q->read_ptr == q->write_ptr &&
1734 trans_pcie->wd_timeout)
1735 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1736
1737 /* Tell device the write index *just past* this latest filled TFD */
1738 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1739 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1740
1741 /*
1742 * At this point the frame is "transmitted" successfully
1743 * and we will get a TX status notification eventually,
1744 * regardless of the value of ret. "ret" only indicates
1745 * whether or not we should update the write pointer.
1746 */
1747 if (iwl_queue_space(q) < q->high_mark) {
1748 if (wait_write_ptr) {
1749 txq->need_update = 1;
1750 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1751 } else {
1752 iwl_stop_queue(trans, txq);
1753 }
1754 }
1755 spin_unlock(&txq->lock);
1756 return 0;
1757 out_err:
1758 spin_unlock(&txq->lock);
1759 return -1;
1760 }
Linux kernel - Deliverables
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