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Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / pcie / tx.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/slab.h>
31 #include <linux/sched.h>
32
33 #include "iwl-debug.h"
34 #include "iwl-csr.h"
35 #include "iwl-prph.h"
36 #include "iwl-io.h"
37 #include "iwl-op-mode.h"
38 #include "internal.h"
39 /* FIXME: need to abstract out TX command (once we know what it looks like) */
40 #include "dvm/commands.h"
41
42 #define IWL_TX_CRC_SIZE 4
43 #define IWL_TX_DELIMITER_SIZE 4
44
45 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
46 * DMA services
47 *
48 * Theory of operation
49 *
50 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
51 * of buffer descriptors, each of which points to one or more data buffers for
52 * the device to read from or fill. Driver and device exchange status of each
53 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
54 * entries in each circular buffer, to protect against confusing empty and full
55 * queue states.
56 *
57 * The device reads or writes the data in the queues via the device's several
58 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
59 *
60 * For Tx queue, there are low mark and high mark limits. If, after queuing
61 * the packet for Tx, free space become < low mark, Tx queue stopped. When
62 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
63 * Tx queue resumed.
64 *
65 ***************************************************/
66 static int iwl_queue_space(const struct iwl_queue *q)
67 {
68 unsigned int max;
69 unsigned int used;
70
71 /*
72 * To avoid ambiguity between empty and completely full queues, there
73 * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue.
74 * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need
75 * to reserve any queue entries for this purpose.
76 */
77 if (q->n_window < TFD_QUEUE_SIZE_MAX)
78 max = q->n_window;
79 else
80 max = TFD_QUEUE_SIZE_MAX - 1;
81
82 /*
83 * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to
84 * modulo by TFD_QUEUE_SIZE_MAX and is well defined.
85 */
86 used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1);
87
88 if (WARN_ON(used > max))
89 return 0;
90
91 return max - used;
92 }
93
94 /*
95 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
96 */
97 static int iwl_queue_init(struct iwl_queue *q, int slots_num, u32 id)
98 {
99 q->n_window = slots_num;
100 q->id = id;
101
102 /* slots_num must be power-of-two size, otherwise
103 * get_cmd_index is broken. */
104 if (WARN_ON(!is_power_of_2(slots_num)))
105 return -EINVAL;
106
107 q->low_mark = q->n_window / 4;
108 if (q->low_mark < 4)
109 q->low_mark = 4;
110
111 q->high_mark = q->n_window / 8;
112 if (q->high_mark < 2)
113 q->high_mark = 2;
114
115 q->write_ptr = 0;
116 q->read_ptr = 0;
117
118 return 0;
119 }
120
121 static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
122 struct iwl_dma_ptr *ptr, size_t size)
123 {
124 if (WARN_ON(ptr->addr))
125 return -EINVAL;
126
127 ptr->addr = dma_alloc_coherent(trans->dev, size,
128 &ptr->dma, GFP_KERNEL);
129 if (!ptr->addr)
130 return -ENOMEM;
131 ptr->size = size;
132 return 0;
133 }
134
135 static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans,
136 struct iwl_dma_ptr *ptr)
137 {
138 if (unlikely(!ptr->addr))
139 return;
140
141 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
142 memset(ptr, 0, sizeof(*ptr));
143 }
144
145 static void iwl_pcie_txq_stuck_timer(unsigned long data)
146 {
147 struct iwl_txq *txq = (void *)data;
148 struct iwl_queue *q = &txq->q;
149 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
150 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
151 u32 scd_sram_addr = trans_pcie->scd_base_addr +
152 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
153 u8 buf[16];
154 int i;
155
156 spin_lock(&txq->lock);
157 /* check if triggered erroneously */
158 if (txq->q.read_ptr == txq->q.write_ptr) {
159 spin_unlock(&txq->lock);
160 return;
161 }
162 spin_unlock(&txq->lock);
163
164 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
165 jiffies_to_msecs(trans_pcie->wd_timeout));
166 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
167 txq->q.read_ptr, txq->q.write_ptr);
168
169 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
170
171 iwl_print_hex_error(trans, buf, sizeof(buf));
172
173 for (i = 0; i < FH_TCSR_CHNL_NUM; i++)
174 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i,
175 iwl_read_direct32(trans, FH_TX_TRB_REG(i)));
176
177 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
178 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i));
179 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
180 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
181 u32 tbl_dw =
182 iwl_trans_read_mem32(trans,
183 trans_pcie->scd_base_addr +
184 SCD_TRANS_TBL_OFFSET_QUEUE(i));
185
186 if (i & 0x1)
187 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
188 else
189 tbl_dw = tbl_dw & 0x0000FFFF;
190
191 IWL_ERR(trans,
192 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
193 i, active ? "" : "in", fifo, tbl_dw,
194 iwl_read_prph(trans, SCD_QUEUE_RDPTR(i)) &
195 (TFD_QUEUE_SIZE_MAX - 1),
196 iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
197 }
198
199 for (i = q->read_ptr; i != q->write_ptr;
200 i = iwl_queue_inc_wrap(i))
201 IWL_ERR(trans, "scratch %d = 0x%08x\n", i,
202 le32_to_cpu(txq->scratchbufs[i].scratch));
203
204 iwl_force_nmi(trans);
205 }
206
207 /*
208 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
209 */
210 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
211 struct iwl_txq *txq, u16 byte_cnt)
212 {
213 struct iwlagn_scd_bc_tbl *scd_bc_tbl;
214 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
215 int write_ptr = txq->q.write_ptr;
216 int txq_id = txq->q.id;
217 u8 sec_ctl = 0;
218 u8 sta_id = 0;
219 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
220 __le16 bc_ent;
221 struct iwl_tx_cmd *tx_cmd =
222 (void *) txq->entries[txq->q.write_ptr].cmd->payload;
223
224 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
225
226 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
227
228 sta_id = tx_cmd->sta_id;
229 sec_ctl = tx_cmd->sec_ctl;
230
231 switch (sec_ctl & TX_CMD_SEC_MSK) {
232 case TX_CMD_SEC_CCM:
233 len += IEEE80211_CCMP_MIC_LEN;
234 break;
235 case TX_CMD_SEC_TKIP:
236 len += IEEE80211_TKIP_ICV_LEN;
237 break;
238 case TX_CMD_SEC_WEP:
239 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
240 break;
241 }
242
243 if (trans_pcie->bc_table_dword)
244 len = DIV_ROUND_UP(len, 4);
245
246 bc_ent = cpu_to_le16(len | (sta_id << 12));
247
248 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
249
250 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
251 scd_bc_tbl[txq_id].
252 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
253 }
254
255 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
256 struct iwl_txq *txq)
257 {
258 struct iwl_trans_pcie *trans_pcie =
259 IWL_TRANS_GET_PCIE_TRANS(trans);
260 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
261 int txq_id = txq->q.id;
262 int read_ptr = txq->q.read_ptr;
263 u8 sta_id = 0;
264 __le16 bc_ent;
265 struct iwl_tx_cmd *tx_cmd =
266 (void *)txq->entries[txq->q.read_ptr].cmd->payload;
267
268 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
269
270 if (txq_id != trans_pcie->cmd_queue)
271 sta_id = tx_cmd->sta_id;
272
273 bc_ent = cpu_to_le16(1 | (sta_id << 12));
274 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
275
276 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
277 scd_bc_tbl[txq_id].
278 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
279 }
280
281 /*
282 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
283 */
284 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
285 struct iwl_txq *txq)
286 {
287 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
288 u32 reg = 0;
289 int txq_id = txq->q.id;
290
291 lockdep_assert_held(&txq->lock);
292
293 /*
294 * explicitly wake up the NIC if:
295 * 1. shadow registers aren't enabled
296 * 2. NIC is woken up for CMD regardless of shadow outside this function
297 * 3. there is a chance that the NIC is asleep
298 */
299 if (!trans->cfg->base_params->shadow_reg_enable &&
300 txq_id != trans_pcie->cmd_queue &&
301 test_bit(STATUS_TPOWER_PMI, &trans->status)) {
302 /*
303 * wake up nic if it's powered down ...
304 * uCode will wake up, and interrupt us again, so next
305 * time we'll skip this part.
306 */
307 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
308
309 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
310 IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
311 txq_id, reg);
312 iwl_set_bit(trans, CSR_GP_CNTRL,
313 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
314 txq->need_update = true;
315 return;
316 }
317 }
318
319 /*
320 * if not in power-save mode, uCode will never sleep when we're
321 * trying to tx (during RFKILL, we're not trying to tx).
322 */
323 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->q.write_ptr);
324 iwl_write32(trans, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
325 }
326
327 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
328 {
329 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
330 int i;
331
332 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
333 struct iwl_txq *txq = &trans_pcie->txq[i];
334
335 spin_lock_bh(&txq->lock);
336 if (trans_pcie->txq[i].need_update) {
337 iwl_pcie_txq_inc_wr_ptr(trans, txq);
338 trans_pcie->txq[i].need_update = false;
339 }
340 spin_unlock_bh(&txq->lock);
341 }
342 }
343
344 static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
345 {
346 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
347
348 dma_addr_t addr = get_unaligned_le32(&tb->lo);
349 if (sizeof(dma_addr_t) > sizeof(u32))
350 addr |=
351 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
352
353 return addr;
354 }
355
356 static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
357 dma_addr_t addr, u16 len)
358 {
359 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
360 u16 hi_n_len = len << 4;
361
362 put_unaligned_le32(addr, &tb->lo);
363 if (sizeof(dma_addr_t) > sizeof(u32))
364 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
365
366 tb->hi_n_len = cpu_to_le16(hi_n_len);
367
368 tfd->num_tbs = idx + 1;
369 }
370
371 static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd)
372 {
373 return tfd->num_tbs & 0x1f;
374 }
375
376 static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
377 struct iwl_cmd_meta *meta,
378 struct iwl_tfd *tfd)
379 {
380 int i;
381 int num_tbs;
382
383 /* Sanity check on number of chunks */
384 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
385
386 if (num_tbs >= IWL_NUM_OF_TBS) {
387 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
388 /* @todo issue fatal error, it is quite serious situation */
389 return;
390 }
391
392 /* first TB is never freed - it's the scratchbuf data */
393
394 for (i = 1; i < num_tbs; i++)
395 dma_unmap_single(trans->dev, iwl_pcie_tfd_tb_get_addr(tfd, i),
396 iwl_pcie_tfd_tb_get_len(tfd, i),
397 DMA_TO_DEVICE);
398
399 tfd->num_tbs = 0;
400 }
401
402 /*
403 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
404 * @trans - transport private data
405 * @txq - tx queue
406 * @dma_dir - the direction of the DMA mapping
407 *
408 * Does NOT advance any TFD circular buffer read/write indexes
409 * Does NOT free the TFD itself (which is within circular buffer)
410 */
411 static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
412 {
413 struct iwl_tfd *tfd_tmp = txq->tfds;
414
415 /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
416 * idx is bounded by n_window
417 */
418 int rd_ptr = txq->q.read_ptr;
419 int idx = get_cmd_index(&txq->q, rd_ptr);
420
421 lockdep_assert_held(&txq->lock);
422
423 /* We have only q->n_window txq->entries, but we use
424 * TFD_QUEUE_SIZE_MAX tfds
425 */
426 iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]);
427
428 /* free SKB */
429 if (txq->entries) {
430 struct sk_buff *skb;
431
432 skb = txq->entries[idx].skb;
433
434 /* Can be called from irqs-disabled context
435 * If skb is not NULL, it means that the whole queue is being
436 * freed and that the queue is not empty - free the skb
437 */
438 if (skb) {
439 iwl_op_mode_free_skb(trans->op_mode, skb);
440 txq->entries[idx].skb = NULL;
441 }
442 }
443 }
444
445 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
446 dma_addr_t addr, u16 len, bool reset)
447 {
448 struct iwl_queue *q;
449 struct iwl_tfd *tfd, *tfd_tmp;
450 u32 num_tbs;
451
452 q = &txq->q;
453 tfd_tmp = txq->tfds;
454 tfd = &tfd_tmp[q->write_ptr];
455
456 if (reset)
457 memset(tfd, 0, sizeof(*tfd));
458
459 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
460
461 /* Each TFD can point to a maximum 20 Tx buffers */
462 if (num_tbs >= IWL_NUM_OF_TBS) {
463 IWL_ERR(trans, "Error can not send more than %d chunks\n",
464 IWL_NUM_OF_TBS);
465 return -EINVAL;
466 }
467
468 if (WARN(addr & ~IWL_TX_DMA_MASK,
469 "Unaligned address = %llx\n", (unsigned long long)addr))
470 return -EINVAL;
471
472 iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len);
473
474 return 0;
475 }
476
477 static int iwl_pcie_txq_alloc(struct iwl_trans *trans,
478 struct iwl_txq *txq, int slots_num,
479 u32 txq_id)
480 {
481 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
482 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
483 size_t scratchbuf_sz;
484 int i;
485
486 if (WARN_ON(txq->entries || txq->tfds))
487 return -EINVAL;
488
489 setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer,
490 (unsigned long)txq);
491 txq->trans_pcie = trans_pcie;
492
493 txq->q.n_window = slots_num;
494
495 txq->entries = kcalloc(slots_num,
496 sizeof(struct iwl_pcie_txq_entry),
497 GFP_KERNEL);
498
499 if (!txq->entries)
500 goto error;
501
502 if (txq_id == trans_pcie->cmd_queue)
503 for (i = 0; i < slots_num; i++) {
504 txq->entries[i].cmd =
505 kmalloc(sizeof(struct iwl_device_cmd),
506 GFP_KERNEL);
507 if (!txq->entries[i].cmd)
508 goto error;
509 }
510
511 /* Circular buffer of transmit frame descriptors (TFDs),
512 * shared with device */
513 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
514 &txq->q.dma_addr, GFP_KERNEL);
515 if (!txq->tfds)
516 goto error;
517
518 BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE != sizeof(*txq->scratchbufs));
519 BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf, scratch) !=
520 sizeof(struct iwl_cmd_header) +
521 offsetof(struct iwl_tx_cmd, scratch));
522
523 scratchbuf_sz = sizeof(*txq->scratchbufs) * slots_num;
524
525 txq->scratchbufs = dma_alloc_coherent(trans->dev, scratchbuf_sz,
526 &txq->scratchbufs_dma,
527 GFP_KERNEL);
528 if (!txq->scratchbufs)
529 goto err_free_tfds;
530
531 txq->q.id = txq_id;
532
533 return 0;
534 err_free_tfds:
535 dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr);
536 error:
537 if (txq->entries && txq_id == trans_pcie->cmd_queue)
538 for (i = 0; i < slots_num; i++)
539 kfree(txq->entries[i].cmd);
540 kfree(txq->entries);
541 txq->entries = NULL;
542
543 return -ENOMEM;
544
545 }
546
547 static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
548 int slots_num, u32 txq_id)
549 {
550 int ret;
551
552 txq->need_update = false;
553
554 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
555 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
556 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
557
558 /* Initialize queue's high/low-water marks, and head/tail indexes */
559 ret = iwl_queue_init(&txq->q, slots_num, txq_id);
560 if (ret)
561 return ret;
562
563 spin_lock_init(&txq->lock);
564
565 /*
566 * Tell nic where to find circular buffer of Tx Frame Descriptors for
567 * given Tx queue, and enable the DMA channel used for that queue.
568 * Circular buffer (TFD queue in DRAM) physical base address */
569 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
570 txq->q.dma_addr >> 8);
571
572 return 0;
573 }
574
575 /*
576 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's
577 */
578 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
579 {
580 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
581 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
582 struct iwl_queue *q = &txq->q;
583
584 spin_lock_bh(&txq->lock);
585 while (q->write_ptr != q->read_ptr) {
586 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
587 txq_id, q->read_ptr);
588 iwl_pcie_txq_free_tfd(trans, txq);
589 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr);
590 }
591 txq->active = false;
592 spin_unlock_bh(&txq->lock);
593
594 /* just in case - this queue may have been stopped */
595 iwl_wake_queue(trans, txq);
596 }
597
598 /*
599 * iwl_pcie_txq_free - Deallocate DMA queue.
600 * @txq: Transmit queue to deallocate.
601 *
602 * Empty queue by removing and destroying all BD's.
603 * Free all buffers.
604 * 0-fill, but do not free "txq" descriptor structure.
605 */
606 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
607 {
608 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
609 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
610 struct device *dev = trans->dev;
611 int i;
612
613 if (WARN_ON(!txq))
614 return;
615
616 iwl_pcie_txq_unmap(trans, txq_id);
617
618 /* De-alloc array of command/tx buffers */
619 if (txq_id == trans_pcie->cmd_queue)
620 for (i = 0; i < txq->q.n_window; i++) {
621 kfree(txq->entries[i].cmd);
622 kfree(txq->entries[i].free_buf);
623 }
624
625 /* De-alloc circular buffer of TFDs */
626 if (txq->tfds) {
627 dma_free_coherent(dev,
628 sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX,
629 txq->tfds, txq->q.dma_addr);
630 txq->q.dma_addr = 0;
631 txq->tfds = NULL;
632
633 dma_free_coherent(dev,
634 sizeof(*txq->scratchbufs) * txq->q.n_window,
635 txq->scratchbufs, txq->scratchbufs_dma);
636 }
637
638 kfree(txq->entries);
639 txq->entries = NULL;
640
641 del_timer_sync(&txq->stuck_timer);
642
643 /* 0-fill queue descriptor structure */
644 memset(txq, 0, sizeof(*txq));
645 }
646
647 /*
648 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
649 */
650 static void iwl_pcie_txq_set_sched(struct iwl_trans *trans, u32 mask)
651 {
652 struct iwl_trans_pcie __maybe_unused *trans_pcie =
653 IWL_TRANS_GET_PCIE_TRANS(trans);
654
655 iwl_write_prph(trans, SCD_TXFACT, mask);
656 }
657
658 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
659 {
660 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
661 int nq = trans->cfg->base_params->num_of_queues;
662 int chan;
663 u32 reg_val;
664 int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
665 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
666
667 /* make sure all queue are not stopped/used */
668 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
669 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
670
671 trans_pcie->scd_base_addr =
672 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
673
674 WARN_ON(scd_base_addr != 0 &&
675 scd_base_addr != trans_pcie->scd_base_addr);
676
677 /* reset context data, TX status and translation data */
678 iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
679 SCD_CONTEXT_MEM_LOWER_BOUND,
680 NULL, clear_dwords);
681
682 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
683 trans_pcie->scd_bc_tbls.dma >> 10);
684
685 /* The chain extension of the SCD doesn't work well. This feature is
686 * enabled by default by the HW, so we need to disable it manually.
687 */
688 if (trans->cfg->base_params->scd_chain_ext_wa)
689 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
690
691 iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
692 trans_pcie->cmd_fifo);
693
694 /* Activate all Tx DMA/FIFO channels */
695 iwl_pcie_txq_set_sched(trans, IWL_MASK(0, 7));
696
697 /* Enable DMA channel */
698 for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
699 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
700 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
701 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
702
703 /* Update FH chicken bits */
704 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
705 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
706 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
707
708 /* Enable L1-Active */
709 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
710 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
711 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
712 }
713
714 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
715 {
716 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
717 int txq_id;
718
719 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
720 txq_id++) {
721 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
722
723 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
724 txq->q.dma_addr >> 8);
725 iwl_pcie_txq_unmap(trans, txq_id);
726 txq->q.read_ptr = 0;
727 txq->q.write_ptr = 0;
728 }
729
730 /* Tell NIC where to find the "keep warm" buffer */
731 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
732 trans_pcie->kw.dma >> 4);
733
734 iwl_pcie_tx_start(trans, trans_pcie->scd_base_addr);
735 }
736
737 /*
738 * iwl_pcie_tx_stop - Stop all Tx DMA channels
739 */
740 int iwl_pcie_tx_stop(struct iwl_trans *trans)
741 {
742 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
743 int ch, txq_id, ret;
744
745 /* Turn off all Tx DMA fifos */
746 spin_lock(&trans_pcie->irq_lock);
747
748 iwl_pcie_txq_set_sched(trans, 0);
749
750 /* Stop each Tx DMA channel, and wait for it to be idle */
751 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
752 iwl_write_direct32(trans,
753 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
754 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
755 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000);
756 if (ret < 0)
757 IWL_ERR(trans,
758 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
759 ch,
760 iwl_read_direct32(trans,
761 FH_TSSR_TX_STATUS_REG));
762 }
763 spin_unlock(&trans_pcie->irq_lock);
764
765 /*
766 * This function can be called before the op_mode disabled the
767 * queues. This happens when we have an rfkill interrupt.
768 * Since we stop Tx altogether - mark the queues as stopped.
769 */
770 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
771 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
772
773 /* This can happen: start_hw, stop_device */
774 if (!trans_pcie->txq)
775 return 0;
776
777 /* Unmap DMA from host system and free skb's */
778 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
779 txq_id++)
780 iwl_pcie_txq_unmap(trans, txq_id);
781
782 return 0;
783 }
784
785 /*
786 * iwl_trans_tx_free - Free TXQ Context
787 *
788 * Destroy all TX DMA queues and structures
789 */
790 void iwl_pcie_tx_free(struct iwl_trans *trans)
791 {
792 int txq_id;
793 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
794
795 /* Tx queues */
796 if (trans_pcie->txq) {
797 for (txq_id = 0;
798 txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
799 iwl_pcie_txq_free(trans, txq_id);
800 }
801
802 kfree(trans_pcie->txq);
803 trans_pcie->txq = NULL;
804
805 iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
806
807 iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
808 }
809
810 /*
811 * iwl_pcie_tx_alloc - allocate TX context
812 * Allocate all Tx DMA structures and initialize them
813 */
814 static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
815 {
816 int ret;
817 int txq_id, slots_num;
818 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
819
820 u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
821 sizeof(struct iwlagn_scd_bc_tbl);
822
823 /*It is not allowed to alloc twice, so warn when this happens.
824 * We cannot rely on the previous allocation, so free and fail */
825 if (WARN_ON(trans_pcie->txq)) {
826 ret = -EINVAL;
827 goto error;
828 }
829
830 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
831 scd_bc_tbls_size);
832 if (ret) {
833 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
834 goto error;
835 }
836
837 /* Alloc keep-warm buffer */
838 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
839 if (ret) {
840 IWL_ERR(trans, "Keep Warm allocation failed\n");
841 goto error;
842 }
843
844 trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
845 sizeof(struct iwl_txq), GFP_KERNEL);
846 if (!trans_pcie->txq) {
847 IWL_ERR(trans, "Not enough memory for txq\n");
848 ret = -ENOMEM;
849 goto error;
850 }
851
852 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
853 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
854 txq_id++) {
855 slots_num = (txq_id == trans_pcie->cmd_queue) ?
856 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
857 ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id],
858 slots_num, txq_id);
859 if (ret) {
860 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
861 goto error;
862 }
863 }
864
865 return 0;
866
867 error:
868 iwl_pcie_tx_free(trans);
869
870 return ret;
871 }
872 int iwl_pcie_tx_init(struct iwl_trans *trans)
873 {
874 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
875 int ret;
876 int txq_id, slots_num;
877 bool alloc = false;
878
879 if (!trans_pcie->txq) {
880 ret = iwl_pcie_tx_alloc(trans);
881 if (ret)
882 goto error;
883 alloc = true;
884 }
885
886 spin_lock(&trans_pcie->irq_lock);
887
888 /* Turn off all Tx DMA fifos */
889 iwl_write_prph(trans, SCD_TXFACT, 0);
890
891 /* Tell NIC where to find the "keep warm" buffer */
892 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
893 trans_pcie->kw.dma >> 4);
894
895 spin_unlock(&trans_pcie->irq_lock);
896
897 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
898 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
899 txq_id++) {
900 slots_num = (txq_id == trans_pcie->cmd_queue) ?
901 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
902 ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id],
903 slots_num, txq_id);
904 if (ret) {
905 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
906 goto error;
907 }
908 }
909
910 return 0;
911 error:
912 /*Upon error, free only if we allocated something */
913 if (alloc)
914 iwl_pcie_tx_free(trans);
915 return ret;
916 }
917
918 static inline void iwl_pcie_txq_progress(struct iwl_trans_pcie *trans_pcie,
919 struct iwl_txq *txq)
920 {
921 if (!trans_pcie->wd_timeout)
922 return;
923
924 /*
925 * if empty delete timer, otherwise move timer forward
926 * since we're making progress on this queue
927 */
928 if (txq->q.read_ptr == txq->q.write_ptr)
929 del_timer(&txq->stuck_timer);
930 else
931 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
932 }
933
934 /* Frees buffers until index _not_ inclusive */
935 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
936 struct sk_buff_head *skbs)
937 {
938 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
939 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
940 int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1);
941 struct iwl_queue *q = &txq->q;
942 int last_to_free;
943
944 /* This function is not meant to release cmd queue*/
945 if (WARN_ON(txq_id == trans_pcie->cmd_queue))
946 return;
947
948 spin_lock_bh(&txq->lock);
949
950 if (!txq->active) {
951 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
952 txq_id, ssn);
953 goto out;
954 }
955
956 if (txq->q.read_ptr == tfd_num)
957 goto out;
958
959 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
960 txq_id, txq->q.read_ptr, tfd_num, ssn);
961
962 /*Since we free until index _not_ inclusive, the one before index is
963 * the last we will free. This one must be used */
964 last_to_free = iwl_queue_dec_wrap(tfd_num);
965
966 if (!iwl_queue_used(q, last_to_free)) {
967 IWL_ERR(trans,
968 "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
969 __func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX,
970 q->write_ptr, q->read_ptr);
971 goto out;
972 }
973
974 if (WARN_ON(!skb_queue_empty(skbs)))
975 goto out;
976
977 for (;
978 q->read_ptr != tfd_num;
979 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {
980
981 if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL))
982 continue;
983
984 __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb);
985
986 txq->entries[txq->q.read_ptr].skb = NULL;
987
988 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
989
990 iwl_pcie_txq_free_tfd(trans, txq);
991 }
992
993 iwl_pcie_txq_progress(trans_pcie, txq);
994
995 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
996 iwl_wake_queue(trans, txq);
997 out:
998 spin_unlock_bh(&txq->lock);
999 }
1000
1001 /*
1002 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
1003 *
1004 * When FW advances 'R' index, all entries between old and new 'R' index
1005 * need to be reclaimed. As result, some free space forms. If there is
1006 * enough free space (> low mark), wake the stack that feeds us.
1007 */
1008 static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
1009 {
1010 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1011 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1012 struct iwl_queue *q = &txq->q;
1013 unsigned long flags;
1014 int nfreed = 0;
1015
1016 lockdep_assert_held(&txq->lock);
1017
1018 if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(q, idx))) {
1019 IWL_ERR(trans,
1020 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1021 __func__, txq_id, idx, TFD_QUEUE_SIZE_MAX,
1022 q->write_ptr, q->read_ptr);
1023 return;
1024 }
1025
1026 for (idx = iwl_queue_inc_wrap(idx); q->read_ptr != idx;
1027 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {
1028
1029 if (nfreed++ > 0) {
1030 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1031 idx, q->write_ptr, q->read_ptr);
1032 iwl_force_nmi(trans);
1033 }
1034 }
1035
1036 if (trans->cfg->base_params->apmg_wake_up_wa &&
1037 q->read_ptr == q->write_ptr) {
1038 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1039 WARN_ON(!trans_pcie->cmd_in_flight);
1040 trans_pcie->cmd_in_flight = false;
1041 __iwl_trans_pcie_clear_bit(trans,
1042 CSR_GP_CNTRL,
1043 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1044 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1045 }
1046
1047 iwl_pcie_txq_progress(trans_pcie, txq);
1048 }
1049
1050 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1051 u16 txq_id)
1052 {
1053 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1054 u32 tbl_dw_addr;
1055 u32 tbl_dw;
1056 u16 scd_q2ratid;
1057
1058 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1059
1060 tbl_dw_addr = trans_pcie->scd_base_addr +
1061 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1062
1063 tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1064
1065 if (txq_id & 0x1)
1066 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1067 else
1068 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1069
1070 iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1071
1072 return 0;
1073 }
1074
1075 static inline void iwl_pcie_txq_set_inactive(struct iwl_trans *trans,
1076 u16 txq_id)
1077 {
1078 /* Simply stop the queue, but don't change any configuration;
1079 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1080 iwl_write_prph(trans,
1081 SCD_QUEUE_STATUS_BITS(txq_id),
1082 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1083 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
1084 }
1085
1086 /* Receiver address (actually, Rx station's index into station table),
1087 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1088 #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
1089
1090 void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo,
1091 int sta_id, int tid, int frame_limit, u16 ssn)
1092 {
1093 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1094
1095 if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1096 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1097
1098 /* Stop this Tx queue before configuring it */
1099 iwl_pcie_txq_set_inactive(trans, txq_id);
1100
1101 /* Set this queue as a chain-building queue unless it is CMD queue */
1102 if (txq_id != trans_pcie->cmd_queue)
1103 iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id));
1104
1105 /* If this queue is mapped to a certain station: it is an AGG queue */
1106 if (sta_id >= 0) {
1107 u16 ra_tid = BUILD_RAxTID(sta_id, tid);
1108
1109 /* Map receiver-address / traffic-ID to this queue */
1110 iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1111
1112 /* enable aggregations for the queue */
1113 iwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));
1114 trans_pcie->txq[txq_id].ampdu = true;
1115 } else {
1116 /*
1117 * disable aggregations for the queue, this will also make the
1118 * ra_tid mapping configuration irrelevant since it is now a
1119 * non-AGG queue.
1120 */
1121 iwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));
1122
1123 ssn = trans_pcie->txq[txq_id].q.read_ptr;
1124 }
1125
1126 /* Place first TFD at index corresponding to start sequence number.
1127 * Assumes that ssn_idx is valid (!= 0xFFF) */
1128 trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff);
1129 trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff);
1130
1131 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1132 (ssn & 0xff) | (txq_id << 8));
1133 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1134
1135 /* Set up Tx window size and frame limit for this queue */
1136 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1137 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1138 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1139 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1140 ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1141 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1142 ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1143 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1144
1145 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1146 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1147 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1148 (fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1149 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1150 SCD_QUEUE_STTS_REG_MSK);
1151 trans_pcie->txq[txq_id].active = true;
1152 IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d on FIFO %d WrPtr: %d\n",
1153 txq_id, fifo, ssn & 0xff);
1154 }
1155
1156 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id)
1157 {
1158 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1159 u32 stts_addr = trans_pcie->scd_base_addr +
1160 SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1161 static const u32 zero_val[4] = {};
1162
1163 /*
1164 * Upon HW Rfkill - we stop the device, and then stop the queues
1165 * in the op_mode. Just for the sake of the simplicity of the op_mode,
1166 * allow the op_mode to call txq_disable after it already called
1167 * stop_device.
1168 */
1169 if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
1170 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1171 "queue %d not used", txq_id);
1172 return;
1173 }
1174
1175 iwl_pcie_txq_set_inactive(trans, txq_id);
1176
1177 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1178 ARRAY_SIZE(zero_val));
1179
1180 iwl_pcie_txq_unmap(trans, txq_id);
1181 trans_pcie->txq[txq_id].ampdu = false;
1182
1183 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1184 }
1185
1186 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1187
1188 /*
1189 * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1190 * @priv: device private data point
1191 * @cmd: a pointer to the ucode command structure
1192 *
1193 * The function returns < 0 values to indicate the operation
1194 * failed. On success, it returns the index (>= 0) of command in the
1195 * command queue.
1196 */
1197 static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1198 struct iwl_host_cmd *cmd)
1199 {
1200 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1201 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1202 struct iwl_queue *q = &txq->q;
1203 struct iwl_device_cmd *out_cmd;
1204 struct iwl_cmd_meta *out_meta;
1205 unsigned long flags;
1206 void *dup_buf = NULL;
1207 dma_addr_t phys_addr;
1208 int idx;
1209 u16 copy_size, cmd_size, scratch_size;
1210 bool had_nocopy = false;
1211 int i, ret;
1212 u32 cmd_pos;
1213 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1214 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
1215
1216 copy_size = sizeof(out_cmd->hdr);
1217 cmd_size = sizeof(out_cmd->hdr);
1218
1219 /* need one for the header if the first is NOCOPY */
1220 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
1221
1222 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1223 cmddata[i] = cmd->data[i];
1224 cmdlen[i] = cmd->len[i];
1225
1226 if (!cmd->len[i])
1227 continue;
1228
1229 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1230 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1231 int copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1232
1233 if (copy > cmdlen[i])
1234 copy = cmdlen[i];
1235 cmdlen[i] -= copy;
1236 cmddata[i] += copy;
1237 copy_size += copy;
1238 }
1239
1240 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1241 had_nocopy = true;
1242 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1243 idx = -EINVAL;
1244 goto free_dup_buf;
1245 }
1246 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1247 /*
1248 * This is also a chunk that isn't copied
1249 * to the static buffer so set had_nocopy.
1250 */
1251 had_nocopy = true;
1252
1253 /* only allowed once */
1254 if (WARN_ON(dup_buf)) {
1255 idx = -EINVAL;
1256 goto free_dup_buf;
1257 }
1258
1259 dup_buf = kmemdup(cmddata[i], cmdlen[i],
1260 GFP_ATOMIC);
1261 if (!dup_buf)
1262 return -ENOMEM;
1263 } else {
1264 /* NOCOPY must not be followed by normal! */
1265 if (WARN_ON(had_nocopy)) {
1266 idx = -EINVAL;
1267 goto free_dup_buf;
1268 }
1269 copy_size += cmdlen[i];
1270 }
1271 cmd_size += cmd->len[i];
1272 }
1273
1274 /*
1275 * If any of the command structures end up being larger than
1276 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1277 * allocated into separate TFDs, then we will need to
1278 * increase the size of the buffers.
1279 */
1280 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1281 "Command %s (%#x) is too large (%d bytes)\n",
1282 get_cmd_string(trans_pcie, cmd->id), cmd->id, copy_size)) {
1283 idx = -EINVAL;
1284 goto free_dup_buf;
1285 }
1286
1287 spin_lock_bh(&txq->lock);
1288
1289 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1290 spin_unlock_bh(&txq->lock);
1291
1292 IWL_ERR(trans, "No space in command queue\n");
1293 iwl_op_mode_cmd_queue_full(trans->op_mode);
1294 idx = -ENOSPC;
1295 goto free_dup_buf;
1296 }
1297
1298 idx = get_cmd_index(q, q->write_ptr);
1299 out_cmd = txq->entries[idx].cmd;
1300 out_meta = &txq->entries[idx].meta;
1301
1302 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1303 if (cmd->flags & CMD_WANT_SKB)
1304 out_meta->source = cmd;
1305
1306 /* set up the header */
1307
1308 out_cmd->hdr.cmd = cmd->id;
1309 out_cmd->hdr.flags = 0;
1310 out_cmd->hdr.sequence =
1311 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1312 INDEX_TO_SEQ(q->write_ptr));
1313
1314 /* and copy the data that needs to be copied */
1315 cmd_pos = offsetof(struct iwl_device_cmd, payload);
1316 copy_size = sizeof(out_cmd->hdr);
1317 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1318 int copy;
1319
1320 if (!cmd->len[i])
1321 continue;
1322
1323 /* copy everything if not nocopy/dup */
1324 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1325 IWL_HCMD_DFL_DUP))) {
1326 copy = cmd->len[i];
1327
1328 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1329 cmd_pos += copy;
1330 copy_size += copy;
1331 continue;
1332 }
1333
1334 /*
1335 * Otherwise we need at least IWL_HCMD_SCRATCHBUF_SIZE copied
1336 * in total (for the scratchbuf handling), but copy up to what
1337 * we can fit into the payload for debug dump purposes.
1338 */
1339 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
1340
1341 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1342 cmd_pos += copy;
1343
1344 /* However, treat copy_size the proper way, we need it below */
1345 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1346 copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1347
1348 if (copy > cmd->len[i])
1349 copy = cmd->len[i];
1350 copy_size += copy;
1351 }
1352 }
1353
1354 IWL_DEBUG_HC(trans,
1355 "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1356 get_cmd_string(trans_pcie, out_cmd->hdr.cmd),
1357 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
1358 cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue);
1359
1360 /* start the TFD with the scratchbuf */
1361 scratch_size = min_t(int, copy_size, IWL_HCMD_SCRATCHBUF_SIZE);
1362 memcpy(&txq->scratchbufs[q->write_ptr], &out_cmd->hdr, scratch_size);
1363 iwl_pcie_txq_build_tfd(trans, txq,
1364 iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr),
1365 scratch_size, true);
1366
1367 /* map first command fragment, if any remains */
1368 if (copy_size > scratch_size) {
1369 phys_addr = dma_map_single(trans->dev,
1370 ((u8 *)&out_cmd->hdr) + scratch_size,
1371 copy_size - scratch_size,
1372 DMA_TO_DEVICE);
1373 if (dma_mapping_error(trans->dev, phys_addr)) {
1374 iwl_pcie_tfd_unmap(trans, out_meta,
1375 &txq->tfds[q->write_ptr]);
1376 idx = -ENOMEM;
1377 goto out;
1378 }
1379
1380 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1381 copy_size - scratch_size, false);
1382 }
1383
1384 /* map the remaining (adjusted) nocopy/dup fragments */
1385 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1386 const void *data = cmddata[i];
1387
1388 if (!cmdlen[i])
1389 continue;
1390 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1391 IWL_HCMD_DFL_DUP)))
1392 continue;
1393 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1394 data = dup_buf;
1395 phys_addr = dma_map_single(trans->dev, (void *)data,
1396 cmdlen[i], DMA_TO_DEVICE);
1397 if (dma_mapping_error(trans->dev, phys_addr)) {
1398 iwl_pcie_tfd_unmap(trans, out_meta,
1399 &txq->tfds[q->write_ptr]);
1400 idx = -ENOMEM;
1401 goto out;
1402 }
1403
1404 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false);
1405 }
1406
1407 out_meta->flags = cmd->flags;
1408 if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1409 kfree(txq->entries[idx].free_buf);
1410 txq->entries[idx].free_buf = dup_buf;
1411
1412 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr);
1413
1414 /* start timer if queue currently empty */
1415 if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout)
1416 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1417
1418 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1419
1420 /*
1421 * wake up the NIC to make sure that the firmware will see the host
1422 * command - we will let the NIC sleep once all the host commands
1423 * returned. This needs to be done only on NICs that have
1424 * apmg_wake_up_wa set.
1425 */
1426 if (trans->cfg->base_params->apmg_wake_up_wa &&
1427 !trans_pcie->cmd_in_flight) {
1428 trans_pcie->cmd_in_flight = true;
1429 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1430 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1431 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1432 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1433 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1434 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
1435 15000);
1436 if (ret < 0) {
1437 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1438 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1439 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1440 trans_pcie->cmd_in_flight = false;
1441 IWL_ERR(trans, "Failed to wake NIC for hcmd\n");
1442 idx = -EIO;
1443 goto out;
1444 }
1445 }
1446
1447 /* Increment and update queue's write index */
1448 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);
1449 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1450
1451 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1452
1453 out:
1454 spin_unlock_bh(&txq->lock);
1455 free_dup_buf:
1456 if (idx < 0)
1457 kfree(dup_buf);
1458 return idx;
1459 }
1460
1461 /*
1462 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1463 * @rxb: Rx buffer to reclaim
1464 * @handler_status: return value of the handler of the command
1465 * (put in setup_rx_handlers)
1466 *
1467 * If an Rx buffer has an async callback associated with it the callback
1468 * will be executed. The attached skb (if present) will only be freed
1469 * if the callback returns 1
1470 */
1471 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1472 struct iwl_rx_cmd_buffer *rxb, int handler_status)
1473 {
1474 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1475 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1476 int txq_id = SEQ_TO_QUEUE(sequence);
1477 int index = SEQ_TO_INDEX(sequence);
1478 int cmd_index;
1479 struct iwl_device_cmd *cmd;
1480 struct iwl_cmd_meta *meta;
1481 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1482 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1483
1484 /* If a Tx command is being handled and it isn't in the actual
1485 * command queue then there a command routing bug has been introduced
1486 * in the queue management code. */
1487 if (WARN(txq_id != trans_pcie->cmd_queue,
1488 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1489 txq_id, trans_pcie->cmd_queue, sequence,
1490 trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr,
1491 trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) {
1492 iwl_print_hex_error(trans, pkt, 32);
1493 return;
1494 }
1495
1496 spin_lock_bh(&txq->lock);
1497
1498 cmd_index = get_cmd_index(&txq->q, index);
1499 cmd = txq->entries[cmd_index].cmd;
1500 meta = &txq->entries[cmd_index].meta;
1501
1502 iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]);
1503
1504 /* Input error checking is done when commands are added to queue. */
1505 if (meta->flags & CMD_WANT_SKB) {
1506 struct page *p = rxb_steal_page(rxb);
1507
1508 meta->source->resp_pkt = pkt;
1509 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1510 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1511 meta->source->handler_status = handler_status;
1512 }
1513
1514 iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1515
1516 if (!(meta->flags & CMD_ASYNC)) {
1517 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) {
1518 IWL_WARN(trans,
1519 "HCMD_ACTIVE already clear for command %s\n",
1520 get_cmd_string(trans_pcie, cmd->hdr.cmd));
1521 }
1522 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1523 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1524 get_cmd_string(trans_pcie, cmd->hdr.cmd));
1525 wake_up(&trans_pcie->wait_command_queue);
1526 }
1527
1528 meta->flags = 0;
1529
1530 spin_unlock_bh(&txq->lock);
1531 }
1532
1533 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
1534
1535 static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1536 struct iwl_host_cmd *cmd)
1537 {
1538 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1539 int ret;
1540
1541 /* An asynchronous command can not expect an SKB to be set. */
1542 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1543 return -EINVAL;
1544
1545 ret = iwl_pcie_enqueue_hcmd(trans, cmd);
1546 if (ret < 0) {
1547 IWL_ERR(trans,
1548 "Error sending %s: enqueue_hcmd failed: %d\n",
1549 get_cmd_string(trans_pcie, cmd->id), ret);
1550 return ret;
1551 }
1552 return 0;
1553 }
1554
1555 static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1556 struct iwl_host_cmd *cmd)
1557 {
1558 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1559 int cmd_idx;
1560 int ret;
1561
1562 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1563 get_cmd_string(trans_pcie, cmd->id));
1564
1565 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
1566 &trans->status),
1567 "Command %s: a command is already active!\n",
1568 get_cmd_string(trans_pcie, cmd->id)))
1569 return -EIO;
1570
1571 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1572 get_cmd_string(trans_pcie, cmd->id));
1573
1574 cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
1575 if (cmd_idx < 0) {
1576 ret = cmd_idx;
1577 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1578 IWL_ERR(trans,
1579 "Error sending %s: enqueue_hcmd failed: %d\n",
1580 get_cmd_string(trans_pcie, cmd->id), ret);
1581 return ret;
1582 }
1583
1584 ret = wait_event_timeout(trans_pcie->wait_command_queue,
1585 !test_bit(STATUS_SYNC_HCMD_ACTIVE,
1586 &trans->status),
1587 HOST_COMPLETE_TIMEOUT);
1588 if (!ret) {
1589 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1590 struct iwl_queue *q = &txq->q;
1591
1592 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
1593 get_cmd_string(trans_pcie, cmd->id),
1594 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1595
1596 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
1597 q->read_ptr, q->write_ptr);
1598
1599 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1600 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1601 get_cmd_string(trans_pcie, cmd->id));
1602 ret = -ETIMEDOUT;
1603
1604 iwl_force_nmi(trans);
1605 iwl_trans_fw_error(trans);
1606
1607 goto cancel;
1608 }
1609
1610 if (test_bit(STATUS_FW_ERROR, &trans->status)) {
1611 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
1612 get_cmd_string(trans_pcie, cmd->id));
1613 dump_stack();
1614 ret = -EIO;
1615 goto cancel;
1616 }
1617
1618 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1619 test_bit(STATUS_RFKILL, &trans->status)) {
1620 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1621 ret = -ERFKILL;
1622 goto cancel;
1623 }
1624
1625 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1626 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1627 get_cmd_string(trans_pcie, cmd->id));
1628 ret = -EIO;
1629 goto cancel;
1630 }
1631
1632 return 0;
1633
1634 cancel:
1635 if (cmd->flags & CMD_WANT_SKB) {
1636 /*
1637 * Cancel the CMD_WANT_SKB flag for the cmd in the
1638 * TX cmd queue. Otherwise in case the cmd comes
1639 * in later, it will possibly set an invalid
1640 * address (cmd->meta.source).
1641 */
1642 trans_pcie->txq[trans_pcie->cmd_queue].
1643 entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
1644 }
1645
1646 if (cmd->resp_pkt) {
1647 iwl_free_resp(cmd);
1648 cmd->resp_pkt = NULL;
1649 }
1650
1651 return ret;
1652 }
1653
1654 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1655 {
1656 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1657 test_bit(STATUS_RFKILL, &trans->status)) {
1658 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1659 cmd->id);
1660 return -ERFKILL;
1661 }
1662
1663 if (cmd->flags & CMD_ASYNC)
1664 return iwl_pcie_send_hcmd_async(trans, cmd);
1665
1666 /* We still can fail on RFKILL that can be asserted while we wait */
1667 return iwl_pcie_send_hcmd_sync(trans, cmd);
1668 }
1669
1670 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1671 struct iwl_device_cmd *dev_cmd, int txq_id)
1672 {
1673 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1674 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1675 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
1676 struct iwl_cmd_meta *out_meta;
1677 struct iwl_txq *txq;
1678 struct iwl_queue *q;
1679 dma_addr_t tb0_phys, tb1_phys, scratch_phys;
1680 void *tb1_addr;
1681 u16 len, tb1_len, tb2_len;
1682 bool wait_write_ptr;
1683 __le16 fc = hdr->frame_control;
1684 u8 hdr_len = ieee80211_hdrlen(fc);
1685 u16 wifi_seq;
1686
1687 txq = &trans_pcie->txq[txq_id];
1688 q = &txq->q;
1689
1690 if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
1691 "TX on unused queue %d\n", txq_id))
1692 return -EINVAL;
1693
1694 spin_lock(&txq->lock);
1695
1696 /* In AGG mode, the index in the ring must correspond to the WiFi
1697 * sequence number. This is a HW requirements to help the SCD to parse
1698 * the BA.
1699 * Check here that the packets are in the right place on the ring.
1700 */
1701 wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1702 WARN_ONCE(txq->ampdu &&
1703 (wifi_seq & 0xff) != q->write_ptr,
1704 "Q: %d WiFi Seq %d tfdNum %d",
1705 txq_id, wifi_seq, q->write_ptr);
1706
1707 /* Set up driver data for this TFD */
1708 txq->entries[q->write_ptr].skb = skb;
1709 txq->entries[q->write_ptr].cmd = dev_cmd;
1710
1711 dev_cmd->hdr.sequence =
1712 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1713 INDEX_TO_SEQ(q->write_ptr)));
1714
1715 tb0_phys = iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr);
1716 scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
1717 offsetof(struct iwl_tx_cmd, scratch);
1718
1719 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1720 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1721
1722 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1723 out_meta = &txq->entries[q->write_ptr].meta;
1724
1725 /*
1726 * The second TB (tb1) points to the remainder of the TX command
1727 * and the 802.11 header - dword aligned size
1728 * (This calculation modifies the TX command, so do it before the
1729 * setup of the first TB)
1730 */
1731 len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
1732 hdr_len - IWL_HCMD_SCRATCHBUF_SIZE;
1733 tb1_len = ALIGN(len, 4);
1734
1735 /* Tell NIC about any 2-byte padding after MAC header */
1736 if (tb1_len != len)
1737 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1738
1739 /* The first TB points to the scratchbuf data - min_copy bytes */
1740 memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr,
1741 IWL_HCMD_SCRATCHBUF_SIZE);
1742 iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
1743 IWL_HCMD_SCRATCHBUF_SIZE, true);
1744
1745 /* there must be data left over for TB1 or this code must be changed */
1746 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE);
1747
1748 /* map the data for TB1 */
1749 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_HCMD_SCRATCHBUF_SIZE;
1750 tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
1751 if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
1752 goto out_err;
1753 iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false);
1754
1755 /*
1756 * Set up TFD's third entry to point directly to remainder
1757 * of skb, if any (802.11 null frames have no payload).
1758 */
1759 tb2_len = skb->len - hdr_len;
1760 if (tb2_len > 0) {
1761 dma_addr_t tb2_phys = dma_map_single(trans->dev,
1762 skb->data + hdr_len,
1763 tb2_len, DMA_TO_DEVICE);
1764 if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) {
1765 iwl_pcie_tfd_unmap(trans, out_meta,
1766 &txq->tfds[q->write_ptr]);
1767 goto out_err;
1768 }
1769 iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false);
1770 }
1771
1772 /* Set up entry for this TFD in Tx byte-count array */
1773 iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1774
1775 trace_iwlwifi_dev_tx(trans->dev, skb,
1776 &txq->tfds[txq->q.write_ptr],
1777 sizeof(struct iwl_tfd),
1778 &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len,
1779 skb->data + hdr_len, tb2_len);
1780 trace_iwlwifi_dev_tx_data(trans->dev, skb,
1781 skb->data + hdr_len, tb2_len);
1782
1783 wait_write_ptr = ieee80211_has_morefrags(fc);
1784
1785 /* start timer if queue currently empty */
1786 if (txq->need_update && q->read_ptr == q->write_ptr &&
1787 trans_pcie->wd_timeout)
1788 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1789
1790 /* Tell device the write index *just past* this latest filled TFD */
1791 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);
1792 if (!wait_write_ptr)
1793 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1794
1795 /*
1796 * At this point the frame is "transmitted" successfully
1797 * and we will get a TX status notification eventually.
1798 */
1799 if (iwl_queue_space(q) < q->high_mark) {
1800 if (wait_write_ptr)
1801 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1802 else
1803 iwl_stop_queue(trans, txq);
1804 }
1805 spin_unlock(&txq->lock);
1806 return 0;
1807 out_err:
1808 spin_unlock(&txq->lock);
1809 return -1;
1810 }
Linux kernel - Deliverables
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