projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
iwlwifi: fix rate control regression
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / pcie / tx.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/slab.h>
31 #include <linux/sched.h>
32
33 #include "iwl-debug.h"
34 #include "iwl-csr.h"
35 #include "iwl-prph.h"
36 #include "iwl-io.h"
37 #include "iwl-op-mode.h"
38 #include "internal.h"
39 /* FIXME: need to abstract out TX command (once we know what it looks like) */
40 #include "dvm/commands.h"
41
42 #define IWL_TX_CRC_SIZE 4
43 #define IWL_TX_DELIMITER_SIZE 4
44
45 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
46 * DMA services
47 *
48 * Theory of operation
49 *
50 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
51 * of buffer descriptors, each of which points to one or more data buffers for
52 * the device to read from or fill. Driver and device exchange status of each
53 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
54 * entries in each circular buffer, to protect against confusing empty and full
55 * queue states.
56 *
57 * The device reads or writes the data in the queues via the device's several
58 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
59 *
60 * For Tx queue, there are low mark and high mark limits. If, after queuing
61 * the packet for Tx, free space become < low mark, Tx queue stopped. When
62 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
63 * Tx queue resumed.
64 *
65 ***************************************************/
66 static int iwl_queue_space(const struct iwl_queue *q)
67 {
68 int s = q->read_ptr - q->write_ptr;
69
70 if (q->read_ptr > q->write_ptr)
71 s -= q->n_bd;
72
73 if (s <= 0)
74 s += q->n_window;
75 /* keep some reserve to not confuse empty and full situations */
76 s -= 2;
77 if (s < 0)
78 s = 0;
79 return s;
80 }
81
82 /*
83 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
84 */
85 static int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id)
86 {
87 q->n_bd = count;
88 q->n_window = slots_num;
89 q->id = id;
90
91 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
92 * and iwl_queue_dec_wrap are broken. */
93 if (WARN_ON(!is_power_of_2(count)))
94 return -EINVAL;
95
96 /* slots_num must be power-of-two size, otherwise
97 * get_cmd_index is broken. */
98 if (WARN_ON(!is_power_of_2(slots_num)))
99 return -EINVAL;
100
101 q->low_mark = q->n_window / 4;
102 if (q->low_mark < 4)
103 q->low_mark = 4;
104
105 q->high_mark = q->n_window / 8;
106 if (q->high_mark < 2)
107 q->high_mark = 2;
108
109 q->write_ptr = 0;
110 q->read_ptr = 0;
111
112 return 0;
113 }
114
115 static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
116 struct iwl_dma_ptr *ptr, size_t size)
117 {
118 if (WARN_ON(ptr->addr))
119 return -EINVAL;
120
121 ptr->addr = dma_alloc_coherent(trans->dev, size,
122 &ptr->dma, GFP_KERNEL);
123 if (!ptr->addr)
124 return -ENOMEM;
125 ptr->size = size;
126 return 0;
127 }
128
129 static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans,
130 struct iwl_dma_ptr *ptr)
131 {
132 if (unlikely(!ptr->addr))
133 return;
134
135 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
136 memset(ptr, 0, sizeof(*ptr));
137 }
138
139 static void iwl_pcie_txq_stuck_timer(unsigned long data)
140 {
141 struct iwl_txq *txq = (void *)data;
142 struct iwl_queue *q = &txq->q;
143 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
144 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
145 u32 scd_sram_addr = trans_pcie->scd_base_addr +
146 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
147 u8 buf[16];
148 int i;
149
150 spin_lock(&txq->lock);
151 /* check if triggered erroneously */
152 if (txq->q.read_ptr == txq->q.write_ptr) {
153 spin_unlock(&txq->lock);
154 return;
155 }
156 spin_unlock(&txq->lock);
157
158 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
159 jiffies_to_msecs(trans_pcie->wd_timeout));
160 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
161 txq->q.read_ptr, txq->q.write_ptr);
162
163 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
164
165 iwl_print_hex_error(trans, buf, sizeof(buf));
166
167 for (i = 0; i < FH_TCSR_CHNL_NUM; i++)
168 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i,
169 iwl_read_direct32(trans, FH_TX_TRB_REG(i)));
170
171 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
172 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i));
173 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
174 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
175 u32 tbl_dw =
176 iwl_trans_read_mem32(trans,
177 trans_pcie->scd_base_addr +
178 SCD_TRANS_TBL_OFFSET_QUEUE(i));
179
180 if (i & 0x1)
181 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
182 else
183 tbl_dw = tbl_dw & 0x0000FFFF;
184
185 IWL_ERR(trans,
186 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
187 i, active ? "" : "in", fifo, tbl_dw,
188 iwl_read_prph(trans,
189 SCD_QUEUE_RDPTR(i)) & (txq->q.n_bd - 1),
190 iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
191 }
192
193 for (i = q->read_ptr; i != q->write_ptr;
194 i = iwl_queue_inc_wrap(i, q->n_bd))
195 IWL_ERR(trans, "scratch %d = 0x%08x\n", i,
196 le32_to_cpu(txq->scratchbufs[i].scratch));
197
198 iwl_op_mode_nic_error(trans->op_mode);
199 }
200
201 /*
202 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
203 */
204 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
205 struct iwl_txq *txq, u16 byte_cnt)
206 {
207 struct iwlagn_scd_bc_tbl *scd_bc_tbl;
208 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
209 int write_ptr = txq->q.write_ptr;
210 int txq_id = txq->q.id;
211 u8 sec_ctl = 0;
212 u8 sta_id = 0;
213 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
214 __le16 bc_ent;
215 struct iwl_tx_cmd *tx_cmd =
216 (void *) txq->entries[txq->q.write_ptr].cmd->payload;
217
218 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
219
220 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
221
222 sta_id = tx_cmd->sta_id;
223 sec_ctl = tx_cmd->sec_ctl;
224
225 switch (sec_ctl & TX_CMD_SEC_MSK) {
226 case TX_CMD_SEC_CCM:
227 len += CCMP_MIC_LEN;
228 break;
229 case TX_CMD_SEC_TKIP:
230 len += TKIP_ICV_LEN;
231 break;
232 case TX_CMD_SEC_WEP:
233 len += WEP_IV_LEN + WEP_ICV_LEN;
234 break;
235 }
236
237 if (trans_pcie->bc_table_dword)
238 len = DIV_ROUND_UP(len, 4);
239
240 bc_ent = cpu_to_le16(len | (sta_id << 12));
241
242 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
243
244 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
245 scd_bc_tbl[txq_id].
246 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
247 }
248
249 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
250 struct iwl_txq *txq)
251 {
252 struct iwl_trans_pcie *trans_pcie =
253 IWL_TRANS_GET_PCIE_TRANS(trans);
254 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
255 int txq_id = txq->q.id;
256 int read_ptr = txq->q.read_ptr;
257 u8 sta_id = 0;
258 __le16 bc_ent;
259 struct iwl_tx_cmd *tx_cmd =
260 (void *)txq->entries[txq->q.read_ptr].cmd->payload;
261
262 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
263
264 if (txq_id != trans_pcie->cmd_queue)
265 sta_id = tx_cmd->sta_id;
266
267 bc_ent = cpu_to_le16(1 | (sta_id << 12));
268 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
269
270 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
271 scd_bc_tbl[txq_id].
272 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
273 }
274
275 /*
276 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
277 */
278 void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_txq *txq)
279 {
280 u32 reg = 0;
281 int txq_id = txq->q.id;
282
283 if (txq->need_update == 0)
284 return;
285
286 if (trans->cfg->base_params->shadow_reg_enable) {
287 /* shadow register enabled */
288 iwl_write32(trans, HBUS_TARG_WRPTR,
289 txq->q.write_ptr | (txq_id << 8));
290 } else {
291 struct iwl_trans_pcie *trans_pcie =
292 IWL_TRANS_GET_PCIE_TRANS(trans);
293 /* if we're trying to save power */
294 if (test_bit(STATUS_TPOWER_PMI, &trans_pcie->status)) {
295 /* wake up nic if it's powered down ...
296 * uCode will wake up, and interrupt us again, so next
297 * time we'll skip this part. */
298 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
299
300 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
301 IWL_DEBUG_INFO(trans,
302 "Tx queue %d requesting wakeup,"
303 " GP1 = 0x%x\n", txq_id, reg);
304 iwl_set_bit(trans, CSR_GP_CNTRL,
305 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
306 return;
307 }
308
309 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id,
310 txq->q.write_ptr);
311
312 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
313 txq->q.write_ptr | (txq_id << 8));
314
315 /*
316 * else not in power-save mode,
317 * uCode will never sleep when we're
318 * trying to tx (during RFKILL, we're not trying to tx).
319 */
320 } else
321 iwl_write32(trans, HBUS_TARG_WRPTR,
322 txq->q.write_ptr | (txq_id << 8));
323 }
324 txq->need_update = 0;
325 }
326
327 static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
328 {
329 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
330
331 dma_addr_t addr = get_unaligned_le32(&tb->lo);
332 if (sizeof(dma_addr_t) > sizeof(u32))
333 addr |=
334 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
335
336 return addr;
337 }
338
339 static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
340 {
341 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
342
343 return le16_to_cpu(tb->hi_n_len) >> 4;
344 }
345
346 static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
347 dma_addr_t addr, u16 len)
348 {
349 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
350 u16 hi_n_len = len << 4;
351
352 put_unaligned_le32(addr, &tb->lo);
353 if (sizeof(dma_addr_t) > sizeof(u32))
354 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
355
356 tb->hi_n_len = cpu_to_le16(hi_n_len);
357
358 tfd->num_tbs = idx + 1;
359 }
360
361 static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd)
362 {
363 return tfd->num_tbs & 0x1f;
364 }
365
366 static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
367 struct iwl_cmd_meta *meta,
368 struct iwl_tfd *tfd)
369 {
370 int i;
371 int num_tbs;
372
373 /* Sanity check on number of chunks */
374 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
375
376 if (num_tbs >= IWL_NUM_OF_TBS) {
377 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
378 /* @todo issue fatal error, it is quite serious situation */
379 return;
380 }
381
382 /* first TB is never freed - it's the scratchbuf data */
383
384 for (i = 1; i < num_tbs; i++)
385 dma_unmap_single(trans->dev, iwl_pcie_tfd_tb_get_addr(tfd, i),
386 iwl_pcie_tfd_tb_get_len(tfd, i),
387 DMA_TO_DEVICE);
388
389 tfd->num_tbs = 0;
390 }
391
392 /*
393 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
394 * @trans - transport private data
395 * @txq - tx queue
396 * @dma_dir - the direction of the DMA mapping
397 *
398 * Does NOT advance any TFD circular buffer read/write indexes
399 * Does NOT free the TFD itself (which is within circular buffer)
400 */
401 static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
402 {
403 struct iwl_tfd *tfd_tmp = txq->tfds;
404
405 /* rd_ptr is bounded by n_bd and idx is bounded by n_window */
406 int rd_ptr = txq->q.read_ptr;
407 int idx = get_cmd_index(&txq->q, rd_ptr);
408
409 lockdep_assert_held(&txq->lock);
410
411 /* We have only q->n_window txq->entries, but we use q->n_bd tfds */
412 iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]);
413
414 /* free SKB */
415 if (txq->entries) {
416 struct sk_buff *skb;
417
418 skb = txq->entries[idx].skb;
419
420 /* Can be called from irqs-disabled context
421 * If skb is not NULL, it means that the whole queue is being
422 * freed and that the queue is not empty - free the skb
423 */
424 if (skb) {
425 iwl_op_mode_free_skb(trans->op_mode, skb);
426 txq->entries[idx].skb = NULL;
427 }
428 }
429 }
430
431 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
432 dma_addr_t addr, u16 len, u8 reset)
433 {
434 struct iwl_queue *q;
435 struct iwl_tfd *tfd, *tfd_tmp;
436 u32 num_tbs;
437
438 q = &txq->q;
439 tfd_tmp = txq->tfds;
440 tfd = &tfd_tmp[q->write_ptr];
441
442 if (reset)
443 memset(tfd, 0, sizeof(*tfd));
444
445 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
446
447 /* Each TFD can point to a maximum 20 Tx buffers */
448 if (num_tbs >= IWL_NUM_OF_TBS) {
449 IWL_ERR(trans, "Error can not send more than %d chunks\n",
450 IWL_NUM_OF_TBS);
451 return -EINVAL;
452 }
453
454 if (WARN_ON(addr & ~DMA_BIT_MASK(36)))
455 return -EINVAL;
456
457 if (unlikely(addr & ~IWL_TX_DMA_MASK))
458 IWL_ERR(trans, "Unaligned address = %llx\n",
459 (unsigned long long)addr);
460
461 iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len);
462
463 return 0;
464 }
465
466 static int iwl_pcie_txq_alloc(struct iwl_trans *trans,
467 struct iwl_txq *txq, int slots_num,
468 u32 txq_id)
469 {
470 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
471 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
472 size_t scratchbuf_sz;
473 int i;
474
475 if (WARN_ON(txq->entries || txq->tfds))
476 return -EINVAL;
477
478 setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer,
479 (unsigned long)txq);
480 txq->trans_pcie = trans_pcie;
481
482 txq->q.n_window = slots_num;
483
484 txq->entries = kcalloc(slots_num,
485 sizeof(struct iwl_pcie_txq_entry),
486 GFP_KERNEL);
487
488 if (!txq->entries)
489 goto error;
490
491 if (txq_id == trans_pcie->cmd_queue)
492 for (i = 0; i < slots_num; i++) {
493 txq->entries[i].cmd =
494 kmalloc(sizeof(struct iwl_device_cmd),
495 GFP_KERNEL);
496 if (!txq->entries[i].cmd)
497 goto error;
498 }
499
500 /* Circular buffer of transmit frame descriptors (TFDs),
501 * shared with device */
502 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
503 &txq->q.dma_addr, GFP_KERNEL);
504 if (!txq->tfds)
505 goto error;
506
507 BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE != sizeof(*txq->scratchbufs));
508 BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf, scratch) !=
509 sizeof(struct iwl_cmd_header) +
510 offsetof(struct iwl_tx_cmd, scratch));
511
512 scratchbuf_sz = sizeof(*txq->scratchbufs) * slots_num;
513
514 txq->scratchbufs = dma_alloc_coherent(trans->dev, scratchbuf_sz,
515 &txq->scratchbufs_dma,
516 GFP_KERNEL);
517 if (!txq->scratchbufs)
518 goto err_free_tfds;
519
520 txq->q.id = txq_id;
521
522 return 0;
523 err_free_tfds:
524 dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr);
525 error:
526 if (txq->entries && txq_id == trans_pcie->cmd_queue)
527 for (i = 0; i < slots_num; i++)
528 kfree(txq->entries[i].cmd);
529 kfree(txq->entries);
530 txq->entries = NULL;
531
532 return -ENOMEM;
533
534 }
535
536 static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
537 int slots_num, u32 txq_id)
538 {
539 int ret;
540
541 txq->need_update = 0;
542
543 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
544 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
545 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
546
547 /* Initialize queue's high/low-water marks, and head/tail indexes */
548 ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
549 txq_id);
550 if (ret)
551 return ret;
552
553 spin_lock_init(&txq->lock);
554
555 /*
556 * Tell nic where to find circular buffer of Tx Frame Descriptors for
557 * given Tx queue, and enable the DMA channel used for that queue.
558 * Circular buffer (TFD queue in DRAM) physical base address */
559 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
560 txq->q.dma_addr >> 8);
561
562 return 0;
563 }
564
565 /*
566 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's
567 */
568 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
569 {
570 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
571 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
572 struct iwl_queue *q = &txq->q;
573
574 if (!q->n_bd)
575 return;
576
577 spin_lock_bh(&txq->lock);
578 while (q->write_ptr != q->read_ptr) {
579 iwl_pcie_txq_free_tfd(trans, txq);
580 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
581 }
582 spin_unlock_bh(&txq->lock);
583 }
584
585 /*
586 * iwl_pcie_txq_free - Deallocate DMA queue.
587 * @txq: Transmit queue to deallocate.
588 *
589 * Empty queue by removing and destroying all BD's.
590 * Free all buffers.
591 * 0-fill, but do not free "txq" descriptor structure.
592 */
593 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
594 {
595 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
596 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
597 struct device *dev = trans->dev;
598 int i;
599
600 if (WARN_ON(!txq))
601 return;
602
603 iwl_pcie_txq_unmap(trans, txq_id);
604
605 /* De-alloc array of command/tx buffers */
606 if (txq_id == trans_pcie->cmd_queue)
607 for (i = 0; i < txq->q.n_window; i++) {
608 kfree(txq->entries[i].cmd);
609 kfree(txq->entries[i].free_buf);
610 }
611
612 /* De-alloc circular buffer of TFDs */
613 if (txq->q.n_bd) {
614 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
615 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
616 txq->q.dma_addr = 0;
617
618 dma_free_coherent(dev,
619 sizeof(*txq->scratchbufs) * txq->q.n_window,
620 txq->scratchbufs, txq->scratchbufs_dma);
621 }
622
623 kfree(txq->entries);
624 txq->entries = NULL;
625
626 del_timer_sync(&txq->stuck_timer);
627
628 /* 0-fill queue descriptor structure */
629 memset(txq, 0, sizeof(*txq));
630 }
631
632 /*
633 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
634 */
635 static void iwl_pcie_txq_set_sched(struct iwl_trans *trans, u32 mask)
636 {
637 struct iwl_trans_pcie __maybe_unused *trans_pcie =
638 IWL_TRANS_GET_PCIE_TRANS(trans);
639
640 iwl_write_prph(trans, SCD_TXFACT, mask);
641 }
642
643 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
644 {
645 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
646 int nq = trans->cfg->base_params->num_of_queues;
647 int chan;
648 u32 reg_val;
649 int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
650 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
651
652 /* make sure all queue are not stopped/used */
653 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
654 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
655
656 trans_pcie->scd_base_addr =
657 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
658
659 WARN_ON(scd_base_addr != 0 &&
660 scd_base_addr != trans_pcie->scd_base_addr);
661
662 /* reset context data, TX status and translation data */
663 iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
664 SCD_CONTEXT_MEM_LOWER_BOUND,
665 NULL, clear_dwords);
666
667 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
668 trans_pcie->scd_bc_tbls.dma >> 10);
669
670 /* The chain extension of the SCD doesn't work well. This feature is
671 * enabled by default by the HW, so we need to disable it manually.
672 */
673 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
674
675 iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
676 trans_pcie->cmd_fifo);
677
678 /* Activate all Tx DMA/FIFO channels */
679 iwl_pcie_txq_set_sched(trans, IWL_MASK(0, 7));
680
681 /* Enable DMA channel */
682 for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
683 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
684 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
685 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
686
687 /* Update FH chicken bits */
688 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
689 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
690 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
691
692 /* Enable L1-Active */
693 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
694 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
695 }
696
697 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
698 {
699 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
700 int txq_id;
701
702 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
703 txq_id++) {
704 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
705
706 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
707 txq->q.dma_addr >> 8);
708 iwl_pcie_txq_unmap(trans, txq_id);
709 txq->q.read_ptr = 0;
710 txq->q.write_ptr = 0;
711 }
712
713 /* Tell NIC where to find the "keep warm" buffer */
714 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
715 trans_pcie->kw.dma >> 4);
716
717 iwl_pcie_tx_start(trans, trans_pcie->scd_base_addr);
718 }
719
720 /*
721 * iwl_pcie_tx_stop - Stop all Tx DMA channels
722 */
723 int iwl_pcie_tx_stop(struct iwl_trans *trans)
724 {
725 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
726 int ch, txq_id, ret;
727 unsigned long flags;
728
729 /* Turn off all Tx DMA fifos */
730 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
731
732 iwl_pcie_txq_set_sched(trans, 0);
733
734 /* Stop each Tx DMA channel, and wait for it to be idle */
735 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
736 iwl_write_direct32(trans,
737 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
738 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
739 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000);
740 if (ret < 0)
741 IWL_ERR(trans,
742 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
743 ch,
744 iwl_read_direct32(trans,
745 FH_TSSR_TX_STATUS_REG));
746 }
747 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
748
749 if (!trans_pcie->txq) {
750 IWL_WARN(trans,
751 "Stopping tx queues that aren't allocated...\n");
752 return 0;
753 }
754
755 /* Unmap DMA from host system and free skb's */
756 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
757 txq_id++)
758 iwl_pcie_txq_unmap(trans, txq_id);
759
760 return 0;
761 }
762
763 /*
764 * iwl_trans_tx_free - Free TXQ Context
765 *
766 * Destroy all TX DMA queues and structures
767 */
768 void iwl_pcie_tx_free(struct iwl_trans *trans)
769 {
770 int txq_id;
771 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
772
773 /* Tx queues */
774 if (trans_pcie->txq) {
775 for (txq_id = 0;
776 txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
777 iwl_pcie_txq_free(trans, txq_id);
778 }
779
780 kfree(trans_pcie->txq);
781 trans_pcie->txq = NULL;
782
783 iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
784
785 iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
786 }
787
788 /*
789 * iwl_pcie_tx_alloc - allocate TX context
790 * Allocate all Tx DMA structures and initialize them
791 */
792 static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
793 {
794 int ret;
795 int txq_id, slots_num;
796 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
797
798 u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
799 sizeof(struct iwlagn_scd_bc_tbl);
800
801 /*It is not allowed to alloc twice, so warn when this happens.
802 * We cannot rely on the previous allocation, so free and fail */
803 if (WARN_ON(trans_pcie->txq)) {
804 ret = -EINVAL;
805 goto error;
806 }
807
808 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
809 scd_bc_tbls_size);
810 if (ret) {
811 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
812 goto error;
813 }
814
815 /* Alloc keep-warm buffer */
816 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
817 if (ret) {
818 IWL_ERR(trans, "Keep Warm allocation failed\n");
819 goto error;
820 }
821
822 trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
823 sizeof(struct iwl_txq), GFP_KERNEL);
824 if (!trans_pcie->txq) {
825 IWL_ERR(trans, "Not enough memory for txq\n");
826 ret = ENOMEM;
827 goto error;
828 }
829
830 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
831 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
832 txq_id++) {
833 slots_num = (txq_id == trans_pcie->cmd_queue) ?
834 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
835 ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id],
836 slots_num, txq_id);
837 if (ret) {
838 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
839 goto error;
840 }
841 }
842
843 return 0;
844
845 error:
846 iwl_pcie_tx_free(trans);
847
848 return ret;
849 }
850 int iwl_pcie_tx_init(struct iwl_trans *trans)
851 {
852 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
853 int ret;
854 int txq_id, slots_num;
855 unsigned long flags;
856 bool alloc = false;
857
858 if (!trans_pcie->txq) {
859 ret = iwl_pcie_tx_alloc(trans);
860 if (ret)
861 goto error;
862 alloc = true;
863 }
864
865 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
866
867 /* Turn off all Tx DMA fifos */
868 iwl_write_prph(trans, SCD_TXFACT, 0);
869
870 /* Tell NIC where to find the "keep warm" buffer */
871 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
872 trans_pcie->kw.dma >> 4);
873
874 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
875
876 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
877 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
878 txq_id++) {
879 slots_num = (txq_id == trans_pcie->cmd_queue) ?
880 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
881 ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id],
882 slots_num, txq_id);
883 if (ret) {
884 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
885 goto error;
886 }
887 }
888
889 return 0;
890 error:
891 /*Upon error, free only if we allocated something */
892 if (alloc)
893 iwl_pcie_tx_free(trans);
894 return ret;
895 }
896
897 static inline void iwl_pcie_txq_progress(struct iwl_trans_pcie *trans_pcie,
898 struct iwl_txq *txq)
899 {
900 if (!trans_pcie->wd_timeout)
901 return;
902
903 /*
904 * if empty delete timer, otherwise move timer forward
905 * since we're making progress on this queue
906 */
907 if (txq->q.read_ptr == txq->q.write_ptr)
908 del_timer(&txq->stuck_timer);
909 else
910 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
911 }
912
913 /* Frees buffers until index _not_ inclusive */
914 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
915 struct sk_buff_head *skbs)
916 {
917 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
918 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
919 /* n_bd is usually 256 => n_bd - 1 = 0xff */
920 int tfd_num = ssn & (txq->q.n_bd - 1);
921 struct iwl_queue *q = &txq->q;
922 int last_to_free;
923
924 /* This function is not meant to release cmd queue*/
925 if (WARN_ON(txq_id == trans_pcie->cmd_queue))
926 return;
927
928 spin_lock_bh(&txq->lock);
929
930 if (txq->q.read_ptr == tfd_num)
931 goto out;
932
933 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
934 txq_id, txq->q.read_ptr, tfd_num, ssn);
935
936 /*Since we free until index _not_ inclusive, the one before index is
937 * the last we will free. This one must be used */
938 last_to_free = iwl_queue_dec_wrap(tfd_num, q->n_bd);
939
940 if (!iwl_queue_used(q, last_to_free)) {
941 IWL_ERR(trans,
942 "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
943 __func__, txq_id, last_to_free, q->n_bd,
944 q->write_ptr, q->read_ptr);
945 goto out;
946 }
947
948 if (WARN_ON(!skb_queue_empty(skbs)))
949 goto out;
950
951 for (;
952 q->read_ptr != tfd_num;
953 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
954
955 if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL))
956 continue;
957
958 __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb);
959
960 txq->entries[txq->q.read_ptr].skb = NULL;
961
962 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
963
964 iwl_pcie_txq_free_tfd(trans, txq);
965 }
966
967 iwl_pcie_txq_progress(trans_pcie, txq);
968
969 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
970 iwl_wake_queue(trans, txq);
971 out:
972 spin_unlock_bh(&txq->lock);
973 }
974
975 /*
976 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
977 *
978 * When FW advances 'R' index, all entries between old and new 'R' index
979 * need to be reclaimed. As result, some free space forms. If there is
980 * enough free space (> low mark), wake the stack that feeds us.
981 */
982 static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
983 {
984 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
985 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
986 struct iwl_queue *q = &txq->q;
987 int nfreed = 0;
988
989 lockdep_assert_held(&txq->lock);
990
991 if ((idx >= q->n_bd) || (!iwl_queue_used(q, idx))) {
992 IWL_ERR(trans,
993 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
994 __func__, txq_id, idx, q->n_bd,
995 q->write_ptr, q->read_ptr);
996 return;
997 }
998
999 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
1000 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1001
1002 if (nfreed++ > 0) {
1003 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1004 idx, q->write_ptr, q->read_ptr);
1005 iwl_op_mode_nic_error(trans->op_mode);
1006 }
1007 }
1008
1009 iwl_pcie_txq_progress(trans_pcie, txq);
1010 }
1011
1012 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1013 u16 txq_id)
1014 {
1015 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1016 u32 tbl_dw_addr;
1017 u32 tbl_dw;
1018 u16 scd_q2ratid;
1019
1020 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1021
1022 tbl_dw_addr = trans_pcie->scd_base_addr +
1023 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1024
1025 tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1026
1027 if (txq_id & 0x1)
1028 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1029 else
1030 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1031
1032 iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1033
1034 return 0;
1035 }
1036
1037 static inline void iwl_pcie_txq_set_inactive(struct iwl_trans *trans,
1038 u16 txq_id)
1039 {
1040 /* Simply stop the queue, but don't change any configuration;
1041 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1042 iwl_write_prph(trans,
1043 SCD_QUEUE_STATUS_BITS(txq_id),
1044 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1045 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
1046 }
1047
1048 void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo,
1049 int sta_id, int tid, int frame_limit, u16 ssn)
1050 {
1051 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1052
1053 if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1054 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1055
1056 /* Stop this Tx queue before configuring it */
1057 iwl_pcie_txq_set_inactive(trans, txq_id);
1058
1059 /* Set this queue as a chain-building queue unless it is CMD queue */
1060 if (txq_id != trans_pcie->cmd_queue)
1061 iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id));
1062
1063 /* If this queue is mapped to a certain station: it is an AGG queue */
1064 if (sta_id >= 0) {
1065 u16 ra_tid = BUILD_RAxTID(sta_id, tid);
1066
1067 /* Map receiver-address / traffic-ID to this queue */
1068 iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1069
1070 /* enable aggregations for the queue */
1071 iwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));
1072 } else {
1073 /*
1074 * disable aggregations for the queue, this will also make the
1075 * ra_tid mapping configuration irrelevant since it is now a
1076 * non-AGG queue.
1077 */
1078 iwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));
1079 }
1080
1081 /* Place first TFD at index corresponding to start sequence number.
1082 * Assumes that ssn_idx is valid (!= 0xFFF) */
1083 trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff);
1084 trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff);
1085
1086 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1087 (ssn & 0xff) | (txq_id << 8));
1088 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1089
1090 /* Set up Tx window size and frame limit for this queue */
1091 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1092 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1093 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1094 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1095 ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1096 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1097 ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1098 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1099
1100 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1101 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1102 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1103 (fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1104 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1105 SCD_QUEUE_STTS_REG_MSK);
1106 IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d on FIFO %d WrPtr: %d\n",
1107 txq_id, fifo, ssn & 0xff);
1108 }
1109
1110 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id)
1111 {
1112 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1113 u32 stts_addr = trans_pcie->scd_base_addr +
1114 SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1115 static const u32 zero_val[4] = {};
1116
1117 if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
1118 WARN_ONCE(1, "queue %d not used", txq_id);
1119 return;
1120 }
1121
1122 iwl_pcie_txq_set_inactive(trans, txq_id);
1123
1124 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1125 ARRAY_SIZE(zero_val));
1126
1127 iwl_pcie_txq_unmap(trans, txq_id);
1128
1129 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1130 }
1131
1132 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1133
1134 /*
1135 * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1136 * @priv: device private data point
1137 * @cmd: a point to the ucode command structure
1138 *
1139 * The function returns < 0 values to indicate the operation is
1140 * failed. On success, it turns the index (> 0) of command in the
1141 * command queue.
1142 */
1143 static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1144 struct iwl_host_cmd *cmd)
1145 {
1146 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1147 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1148 struct iwl_queue *q = &txq->q;
1149 struct iwl_device_cmd *out_cmd;
1150 struct iwl_cmd_meta *out_meta;
1151 void *dup_buf = NULL;
1152 dma_addr_t phys_addr;
1153 int idx;
1154 u16 copy_size, cmd_size, scratch_size;
1155 bool had_nocopy = false;
1156 int i;
1157 u32 cmd_pos;
1158 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1159 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
1160
1161 copy_size = sizeof(out_cmd->hdr);
1162 cmd_size = sizeof(out_cmd->hdr);
1163
1164 /* need one for the header if the first is NOCOPY */
1165 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
1166
1167 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1168 cmddata[i] = cmd->data[i];
1169 cmdlen[i] = cmd->len[i];
1170
1171 if (!cmd->len[i])
1172 continue;
1173
1174 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1175 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1176 int copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1177
1178 if (copy > cmdlen[i])
1179 copy = cmdlen[i];
1180 cmdlen[i] -= copy;
1181 cmddata[i] += copy;
1182 copy_size += copy;
1183 }
1184
1185 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1186 had_nocopy = true;
1187 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1188 idx = -EINVAL;
1189 goto free_dup_buf;
1190 }
1191 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1192 /*
1193 * This is also a chunk that isn't copied
1194 * to the static buffer so set had_nocopy.
1195 */
1196 had_nocopy = true;
1197
1198 /* only allowed once */
1199 if (WARN_ON(dup_buf)) {
1200 idx = -EINVAL;
1201 goto free_dup_buf;
1202 }
1203
1204 dup_buf = kmemdup(cmddata[i], cmdlen[i],
1205 GFP_ATOMIC);
1206 if (!dup_buf)
1207 return -ENOMEM;
1208 } else {
1209 /* NOCOPY must not be followed by normal! */
1210 if (WARN_ON(had_nocopy)) {
1211 idx = -EINVAL;
1212 goto free_dup_buf;
1213 }
1214 copy_size += cmdlen[i];
1215 }
1216 cmd_size += cmd->len[i];
1217 }
1218
1219 /*
1220 * If any of the command structures end up being larger than
1221 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1222 * allocated into separate TFDs, then we will need to
1223 * increase the size of the buffers.
1224 */
1225 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1226 "Command %s (%#x) is too large (%d bytes)\n",
1227 get_cmd_string(trans_pcie, cmd->id), cmd->id, copy_size)) {
1228 idx = -EINVAL;
1229 goto free_dup_buf;
1230 }
1231
1232 spin_lock_bh(&txq->lock);
1233
1234 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1235 spin_unlock_bh(&txq->lock);
1236
1237 IWL_ERR(trans, "No space in command queue\n");
1238 iwl_op_mode_cmd_queue_full(trans->op_mode);
1239 idx = -ENOSPC;
1240 goto free_dup_buf;
1241 }
1242
1243 idx = get_cmd_index(q, q->write_ptr);
1244 out_cmd = txq->entries[idx].cmd;
1245 out_meta = &txq->entries[idx].meta;
1246
1247 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1248 if (cmd->flags & CMD_WANT_SKB)
1249 out_meta->source = cmd;
1250
1251 /* set up the header */
1252
1253 out_cmd->hdr.cmd = cmd->id;
1254 out_cmd->hdr.flags = 0;
1255 out_cmd->hdr.sequence =
1256 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1257 INDEX_TO_SEQ(q->write_ptr));
1258
1259 /* and copy the data that needs to be copied */
1260 cmd_pos = offsetof(struct iwl_device_cmd, payload);
1261 copy_size = sizeof(out_cmd->hdr);
1262 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1263 int copy = 0;
1264
1265 if (!cmd->len[i])
1266 continue;
1267
1268 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1269 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1270 copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1271
1272 if (copy > cmd->len[i])
1273 copy = cmd->len[i];
1274 }
1275
1276 /* copy everything if not nocopy/dup */
1277 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1278 IWL_HCMD_DFL_DUP)))
1279 copy = cmd->len[i];
1280
1281 if (copy) {
1282 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1283 cmd_pos += copy;
1284 copy_size += copy;
1285 }
1286 }
1287
1288 IWL_DEBUG_HC(trans,
1289 "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1290 get_cmd_string(trans_pcie, out_cmd->hdr.cmd),
1291 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
1292 cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue);
1293
1294 /* start the TFD with the scratchbuf */
1295 scratch_size = min_t(int, copy_size, IWL_HCMD_SCRATCHBUF_SIZE);
1296 memcpy(&txq->scratchbufs[q->write_ptr], &out_cmd->hdr, scratch_size);
1297 iwl_pcie_txq_build_tfd(trans, txq,
1298 iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr),
1299 scratch_size, 1);
1300
1301 /* map first command fragment, if any remains */
1302 if (copy_size > scratch_size) {
1303 phys_addr = dma_map_single(trans->dev,
1304 ((u8 *)&out_cmd->hdr) + scratch_size,
1305 copy_size - scratch_size,
1306 DMA_TO_DEVICE);
1307 if (dma_mapping_error(trans->dev, phys_addr)) {
1308 iwl_pcie_tfd_unmap(trans, out_meta,
1309 &txq->tfds[q->write_ptr]);
1310 idx = -ENOMEM;
1311 goto out;
1312 }
1313
1314 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1315 copy_size - scratch_size, 0);
1316 }
1317
1318 /* map the remaining (adjusted) nocopy/dup fragments */
1319 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1320 const void *data = cmddata[i];
1321
1322 if (!cmdlen[i])
1323 continue;
1324 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1325 IWL_HCMD_DFL_DUP)))
1326 continue;
1327 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1328 data = dup_buf;
1329 phys_addr = dma_map_single(trans->dev, (void *)data,
1330 cmdlen[i], DMA_TO_DEVICE);
1331 if (dma_mapping_error(trans->dev, phys_addr)) {
1332 iwl_pcie_tfd_unmap(trans, out_meta,
1333 &txq->tfds[q->write_ptr]);
1334 idx = -ENOMEM;
1335 goto out;
1336 }
1337
1338 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], 0);
1339 }
1340
1341 out_meta->flags = cmd->flags;
1342 if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1343 kfree(txq->entries[idx].free_buf);
1344 txq->entries[idx].free_buf = dup_buf;
1345
1346 txq->need_update = 1;
1347
1348 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr);
1349
1350 /* start timer if queue currently empty */
1351 if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout)
1352 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1353
1354 /* Increment and update queue's write index */
1355 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1356 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1357
1358 out:
1359 spin_unlock_bh(&txq->lock);
1360 free_dup_buf:
1361 if (idx < 0)
1362 kfree(dup_buf);
1363 return idx;
1364 }
1365
1366 /*
1367 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1368 * @rxb: Rx buffer to reclaim
1369 * @handler_status: return value of the handler of the command
1370 * (put in setup_rx_handlers)
1371 *
1372 * If an Rx buffer has an async callback associated with it the callback
1373 * will be executed. The attached skb (if present) will only be freed
1374 * if the callback returns 1
1375 */
1376 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1377 struct iwl_rx_cmd_buffer *rxb, int handler_status)
1378 {
1379 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1380 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1381 int txq_id = SEQ_TO_QUEUE(sequence);
1382 int index = SEQ_TO_INDEX(sequence);
1383 int cmd_index;
1384 struct iwl_device_cmd *cmd;
1385 struct iwl_cmd_meta *meta;
1386 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1387 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1388
1389 /* If a Tx command is being handled and it isn't in the actual
1390 * command queue then there a command routing bug has been introduced
1391 * in the queue management code. */
1392 if (WARN(txq_id != trans_pcie->cmd_queue,
1393 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1394 txq_id, trans_pcie->cmd_queue, sequence,
1395 trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr,
1396 trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) {
1397 iwl_print_hex_error(trans, pkt, 32);
1398 return;
1399 }
1400
1401 spin_lock_bh(&txq->lock);
1402
1403 cmd_index = get_cmd_index(&txq->q, index);
1404 cmd = txq->entries[cmd_index].cmd;
1405 meta = &txq->entries[cmd_index].meta;
1406
1407 iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]);
1408
1409 /* Input error checking is done when commands are added to queue. */
1410 if (meta->flags & CMD_WANT_SKB) {
1411 struct page *p = rxb_steal_page(rxb);
1412
1413 meta->source->resp_pkt = pkt;
1414 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1415 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1416 meta->source->handler_status = handler_status;
1417 }
1418
1419 iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1420
1421 if (!(meta->flags & CMD_ASYNC)) {
1422 if (!test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) {
1423 IWL_WARN(trans,
1424 "HCMD_ACTIVE already clear for command %s\n",
1425 get_cmd_string(trans_pcie, cmd->hdr.cmd));
1426 }
1427 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
1428 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1429 get_cmd_string(trans_pcie, cmd->hdr.cmd));
1430 wake_up(&trans_pcie->wait_command_queue);
1431 }
1432
1433 meta->flags = 0;
1434
1435 spin_unlock_bh(&txq->lock);
1436 }
1437
1438 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
1439
1440 static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1441 struct iwl_host_cmd *cmd)
1442 {
1443 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1444 int ret;
1445
1446 /* An asynchronous command can not expect an SKB to be set. */
1447 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1448 return -EINVAL;
1449
1450 ret = iwl_pcie_enqueue_hcmd(trans, cmd);
1451 if (ret < 0) {
1452 IWL_ERR(trans,
1453 "Error sending %s: enqueue_hcmd failed: %d\n",
1454 get_cmd_string(trans_pcie, cmd->id), ret);
1455 return ret;
1456 }
1457 return 0;
1458 }
1459
1460 static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1461 struct iwl_host_cmd *cmd)
1462 {
1463 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1464 int cmd_idx;
1465 int ret;
1466
1467 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1468 get_cmd_string(trans_pcie, cmd->id));
1469
1470 if (WARN_ON(test_and_set_bit(STATUS_HCMD_ACTIVE,
1471 &trans_pcie->status))) {
1472 IWL_ERR(trans, "Command %s: a command is already active!\n",
1473 get_cmd_string(trans_pcie, cmd->id));
1474 return -EIO;
1475 }
1476
1477 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1478 get_cmd_string(trans_pcie, cmd->id));
1479
1480 cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
1481 if (cmd_idx < 0) {
1482 ret = cmd_idx;
1483 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
1484 IWL_ERR(trans,
1485 "Error sending %s: enqueue_hcmd failed: %d\n",
1486 get_cmd_string(trans_pcie, cmd->id), ret);
1487 return ret;
1488 }
1489
1490 ret = wait_event_timeout(trans_pcie->wait_command_queue,
1491 !test_bit(STATUS_HCMD_ACTIVE,
1492 &trans_pcie->status),
1493 HOST_COMPLETE_TIMEOUT);
1494 if (!ret) {
1495 if (test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) {
1496 struct iwl_txq *txq =
1497 &trans_pcie->txq[trans_pcie->cmd_queue];
1498 struct iwl_queue *q = &txq->q;
1499
1500 IWL_ERR(trans,
1501 "Error sending %s: time out after %dms.\n",
1502 get_cmd_string(trans_pcie, cmd->id),
1503 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1504
1505 IWL_ERR(trans,
1506 "Current CMD queue read_ptr %d write_ptr %d\n",
1507 q->read_ptr, q->write_ptr);
1508
1509 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
1510 IWL_DEBUG_INFO(trans,
1511 "Clearing HCMD_ACTIVE for command %s\n",
1512 get_cmd_string(trans_pcie, cmd->id));
1513 ret = -ETIMEDOUT;
1514 goto cancel;
1515 }
1516 }
1517
1518 if (test_bit(STATUS_FW_ERROR, &trans_pcie->status)) {
1519 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
1520 get_cmd_string(trans_pcie, cmd->id));
1521 ret = -EIO;
1522 goto cancel;
1523 }
1524
1525 if (test_bit(STATUS_RFKILL, &trans_pcie->status)) {
1526 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1527 ret = -ERFKILL;
1528 goto cancel;
1529 }
1530
1531 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1532 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1533 get_cmd_string(trans_pcie, cmd->id));
1534 ret = -EIO;
1535 goto cancel;
1536 }
1537
1538 return 0;
1539
1540 cancel:
1541 if (cmd->flags & CMD_WANT_SKB) {
1542 /*
1543 * Cancel the CMD_WANT_SKB flag for the cmd in the
1544 * TX cmd queue. Otherwise in case the cmd comes
1545 * in later, it will possibly set an invalid
1546 * address (cmd->meta.source).
1547 */
1548 trans_pcie->txq[trans_pcie->cmd_queue].
1549 entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
1550 }
1551
1552 if (cmd->resp_pkt) {
1553 iwl_free_resp(cmd);
1554 cmd->resp_pkt = NULL;
1555 }
1556
1557 return ret;
1558 }
1559
1560 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1561 {
1562 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1563
1564 if (test_bit(STATUS_FW_ERROR, &trans_pcie->status))
1565 return -EIO;
1566
1567 if (test_bit(STATUS_RFKILL, &trans_pcie->status)) {
1568 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1569 cmd->id);
1570 return -ERFKILL;
1571 }
1572
1573 if (cmd->flags & CMD_ASYNC)
1574 return iwl_pcie_send_hcmd_async(trans, cmd);
1575
1576 /* We still can fail on RFKILL that can be asserted while we wait */
1577 return iwl_pcie_send_hcmd_sync(trans, cmd);
1578 }
1579
1580 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1581 struct iwl_device_cmd *dev_cmd, int txq_id)
1582 {
1583 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1584 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1585 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
1586 struct iwl_cmd_meta *out_meta;
1587 struct iwl_txq *txq;
1588 struct iwl_queue *q;
1589 dma_addr_t tb0_phys, tb1_phys, scratch_phys;
1590 void *tb1_addr;
1591 u16 len, tb1_len, tb2_len;
1592 u8 wait_write_ptr = 0;
1593 __le16 fc = hdr->frame_control;
1594 u8 hdr_len = ieee80211_hdrlen(fc);
1595 u16 __maybe_unused wifi_seq;
1596
1597 txq = &trans_pcie->txq[txq_id];
1598 q = &txq->q;
1599
1600 if (unlikely(!test_bit(txq_id, trans_pcie->queue_used))) {
1601 WARN_ON_ONCE(1);
1602 return -EINVAL;
1603 }
1604
1605 spin_lock(&txq->lock);
1606
1607 /* In AGG mode, the index in the ring must correspond to the WiFi
1608 * sequence number. This is a HW requirements to help the SCD to parse
1609 * the BA.
1610 * Check here that the packets are in the right place on the ring.
1611 */
1612 #ifdef CONFIG_IWLWIFI_DEBUG
1613 wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1614 WARN_ONCE((iwl_read_prph(trans, SCD_AGGR_SEL) & BIT(txq_id)) &&
1615 ((wifi_seq & 0xff) != q->write_ptr),
1616 "Q: %d WiFi Seq %d tfdNum %d",
1617 txq_id, wifi_seq, q->write_ptr);
1618 #endif
1619
1620 /* Set up driver data for this TFD */
1621 txq->entries[q->write_ptr].skb = skb;
1622 txq->entries[q->write_ptr].cmd = dev_cmd;
1623
1624 dev_cmd->hdr.cmd = REPLY_TX;
1625 dev_cmd->hdr.sequence =
1626 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1627 INDEX_TO_SEQ(q->write_ptr)));
1628
1629 tb0_phys = iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr);
1630 scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
1631 offsetof(struct iwl_tx_cmd, scratch);
1632
1633 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1634 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1635
1636 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1637 out_meta = &txq->entries[q->write_ptr].meta;
1638
1639 /*
1640 * The second TB (tb1) points to the remainder of the TX command
1641 * and the 802.11 header - dword aligned size
1642 * (This calculation modifies the TX command, so do it before the
1643 * setup of the first TB)
1644 */
1645 len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
1646 hdr_len - IWL_HCMD_SCRATCHBUF_SIZE;
1647 tb1_len = (len + 3) & ~3;
1648
1649 /* Tell NIC about any 2-byte padding after MAC header */
1650 if (tb1_len != len)
1651 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1652
1653 /* The first TB points to the scratchbuf data - min_copy bytes */
1654 memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr,
1655 IWL_HCMD_SCRATCHBUF_SIZE);
1656 iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
1657 IWL_HCMD_SCRATCHBUF_SIZE, 1);
1658
1659 /* there must be data left over for TB1 or this code must be changed */
1660 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE);
1661
1662 /* map the data for TB1 */
1663 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_HCMD_SCRATCHBUF_SIZE;
1664 tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
1665 if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
1666 goto out_err;
1667 iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, 0);
1668
1669 /*
1670 * Set up TFD's third entry to point directly to remainder
1671 * of skb, if any (802.11 null frames have no payload).
1672 */
1673 tb2_len = skb->len - hdr_len;
1674 if (tb2_len > 0) {
1675 dma_addr_t tb2_phys = dma_map_single(trans->dev,
1676 skb->data + hdr_len,
1677 tb2_len, DMA_TO_DEVICE);
1678 if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) {
1679 iwl_pcie_tfd_unmap(trans, out_meta,
1680 &txq->tfds[q->write_ptr]);
1681 goto out_err;
1682 }
1683 iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, 0);
1684 }
1685
1686 /* Set up entry for this TFD in Tx byte-count array */
1687 iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1688
1689 trace_iwlwifi_dev_tx(trans->dev, skb,
1690 &txq->tfds[txq->q.write_ptr],
1691 sizeof(struct iwl_tfd),
1692 &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len,
1693 skb->data + hdr_len, tb2_len);
1694 trace_iwlwifi_dev_tx_data(trans->dev, skb,
1695 skb->data + hdr_len, tb2_len);
1696
1697 if (!ieee80211_has_morefrags(fc)) {
1698 txq->need_update = 1;
1699 } else {
1700 wait_write_ptr = 1;
1701 txq->need_update = 0;
1702 }
1703
1704 /* start timer if queue currently empty */
1705 if (txq->need_update && q->read_ptr == q->write_ptr &&
1706 trans_pcie->wd_timeout)
1707 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1708
1709 /* Tell device the write index *just past* this latest filled TFD */
1710 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1711 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1712
1713 /*
1714 * At this point the frame is "transmitted" successfully
1715 * and we will get a TX status notification eventually,
1716 * regardless of the value of ret. "ret" only indicates
1717 * whether or not we should update the write pointer.
1718 */
1719 if (iwl_queue_space(q) < q->high_mark) {
1720 if (wait_write_ptr) {
1721 txq->need_update = 1;
1722 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1723 } else {
1724 iwl_stop_queue(trans, txq);
1725 }
1726 }
1727 spin_unlock(&txq->lock);
1728 return 0;
1729 out_err:
1730 spin_unlock(&txq->lock);
1731 return -1;
1732 }
Linux kernel - Deliverables
This page took 0.1121 seconds and 6 git commands to generate.