1 /******************************************************************************
3 * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/slab.h>
31 #include <linux/sched.h>
33 #include "iwl-debug.h"
37 #include "iwl-op-mode.h"
39 /* FIXME: need to abstract out TX command (once we know what it looks like) */
40 #include "dvm/commands.h"
42 #define IWL_TX_CRC_SIZE 4
43 #define IWL_TX_DELIMITER_SIZE 4
45 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
50 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
51 * of buffer descriptors, each of which points to one or more data buffers for
52 * the device to read from or fill. Driver and device exchange status of each
53 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
54 * entries in each circular buffer, to protect against confusing empty and full
57 * The device reads or writes the data in the queues via the device's several
58 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
60 * For Tx queue, there are low mark and high mark limits. If, after queuing
61 * the packet for Tx, free space become < low mark, Tx queue stopped. When
62 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
65 ***************************************************/
66 static int iwl_queue_space(const struct iwl_queue
*q
)
68 int s
= q
->read_ptr
- q
->write_ptr
;
70 if (q
->read_ptr
> q
->write_ptr
)
75 /* keep some reserve to not confuse empty and full situations */
83 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
85 static int iwl_queue_init(struct iwl_queue
*q
, int count
, int slots_num
, u32 id
)
88 q
->n_window
= slots_num
;
91 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
92 * and iwl_queue_dec_wrap are broken. */
93 if (WARN_ON(!is_power_of_2(count
)))
96 /* slots_num must be power-of-two size, otherwise
97 * get_cmd_index is broken. */
98 if (WARN_ON(!is_power_of_2(slots_num
)))
101 q
->low_mark
= q
->n_window
/ 4;
105 q
->high_mark
= q
->n_window
/ 8;
106 if (q
->high_mark
< 2)
116 static int iwl_pcie_alloc_dma_ptr(struct iwl_trans
*trans
,
117 struct iwl_dma_ptr
*ptr
, size_t size
)
119 if (WARN_ON(ptr
->addr
))
122 ptr
->addr
= dma_alloc_coherent(trans
->dev
, size
,
123 &ptr
->dma
, GFP_KERNEL
);
130 static void iwl_pcie_free_dma_ptr(struct iwl_trans
*trans
,
131 struct iwl_dma_ptr
*ptr
)
133 if (unlikely(!ptr
->addr
))
136 dma_free_coherent(trans
->dev
, ptr
->size
, ptr
->addr
, ptr
->dma
);
137 memset(ptr
, 0, sizeof(*ptr
));
140 static void iwl_pcie_txq_stuck_timer(unsigned long data
)
142 struct iwl_txq
*txq
= (void *)data
;
143 struct iwl_queue
*q
= &txq
->q
;
144 struct iwl_trans_pcie
*trans_pcie
= txq
->trans_pcie
;
145 struct iwl_trans
*trans
= iwl_trans_pcie_get_trans(trans_pcie
);
146 u32 scd_sram_addr
= trans_pcie
->scd_base_addr
+
147 SCD_TX_STTS_QUEUE_OFFSET(txq
->q
.id
);
151 spin_lock(&txq
->lock
);
152 /* check if triggered erroneously */
153 if (txq
->q
.read_ptr
== txq
->q
.write_ptr
) {
154 spin_unlock(&txq
->lock
);
157 spin_unlock(&txq
->lock
);
159 IWL_ERR(trans
, "Queue %d stuck for %u ms.\n", txq
->q
.id
,
160 jiffies_to_msecs(trans_pcie
->wd_timeout
));
161 IWL_ERR(trans
, "Current SW read_ptr %d write_ptr %d\n",
162 txq
->q
.read_ptr
, txq
->q
.write_ptr
);
164 iwl_read_targ_mem_bytes(trans
, scd_sram_addr
, buf
, sizeof(buf
));
166 iwl_print_hex_error(trans
, buf
, sizeof(buf
));
168 for (i
= 0; i
< FH_TCSR_CHNL_NUM
; i
++)
169 IWL_ERR(trans
, "FH TRBs(%d) = 0x%08x\n", i
,
170 iwl_read_direct32(trans
, FH_TX_TRB_REG(i
)));
172 for (i
= 0; i
< trans
->cfg
->base_params
->num_of_queues
; i
++) {
173 u32 status
= iwl_read_prph(trans
, SCD_QUEUE_STATUS_BITS(i
));
174 u8 fifo
= (status
>> SCD_QUEUE_STTS_REG_POS_TXF
) & 0x7;
175 bool active
= !!(status
& BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE
));
177 iwl_read_targ_mem(trans
,
178 trans_pcie
->scd_base_addr
+
179 SCD_TRANS_TBL_OFFSET_QUEUE(i
));
182 tbl_dw
= (tbl_dw
& 0xFFFF0000) >> 16;
184 tbl_dw
= tbl_dw
& 0x0000FFFF;
187 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
188 i
, active
? "" : "in", fifo
, tbl_dw
,
190 SCD_QUEUE_RDPTR(i
)) & (txq
->q
.n_bd
- 1),
191 iwl_read_prph(trans
, SCD_QUEUE_WRPTR(i
)));
194 for (i
= q
->read_ptr
; i
!= q
->write_ptr
;
195 i
= iwl_queue_inc_wrap(i
, q
->n_bd
)) {
196 struct iwl_tx_cmd
*tx_cmd
=
197 (struct iwl_tx_cmd
*)txq
->entries
[i
].cmd
->payload
;
198 IWL_ERR(trans
, "scratch %d = 0x%08x\n", i
,
199 get_unaligned_le32(&tx_cmd
->scratch
));
202 iwl_op_mode_nic_error(trans
->op_mode
);
206 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
208 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans
*trans
,
209 struct iwl_txq
*txq
, u16 byte_cnt
)
211 struct iwlagn_scd_bc_tbl
*scd_bc_tbl
;
212 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
213 int write_ptr
= txq
->q
.write_ptr
;
214 int txq_id
= txq
->q
.id
;
217 u16 len
= byte_cnt
+ IWL_TX_CRC_SIZE
+ IWL_TX_DELIMITER_SIZE
;
219 struct iwl_tx_cmd
*tx_cmd
=
220 (void *) txq
->entries
[txq
->q
.write_ptr
].cmd
->payload
;
222 scd_bc_tbl
= trans_pcie
->scd_bc_tbls
.addr
;
224 WARN_ON(len
> 0xFFF || write_ptr
>= TFD_QUEUE_SIZE_MAX
);
226 sta_id
= tx_cmd
->sta_id
;
227 sec_ctl
= tx_cmd
->sec_ctl
;
229 switch (sec_ctl
& TX_CMD_SEC_MSK
) {
233 case TX_CMD_SEC_TKIP
:
237 len
+= WEP_IV_LEN
+ WEP_ICV_LEN
;
241 bc_ent
= cpu_to_le16((len
& 0xFFF) | (sta_id
<< 12));
243 scd_bc_tbl
[txq_id
].tfd_offset
[write_ptr
] = bc_ent
;
245 if (write_ptr
< TFD_QUEUE_SIZE_BC_DUP
)
247 tfd_offset
[TFD_QUEUE_SIZE_MAX
+ write_ptr
] = bc_ent
;
250 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans
*trans
,
253 struct iwl_trans_pcie
*trans_pcie
=
254 IWL_TRANS_GET_PCIE_TRANS(trans
);
255 struct iwlagn_scd_bc_tbl
*scd_bc_tbl
= trans_pcie
->scd_bc_tbls
.addr
;
256 int txq_id
= txq
->q
.id
;
257 int read_ptr
= txq
->q
.read_ptr
;
260 struct iwl_tx_cmd
*tx_cmd
=
261 (void *)txq
->entries
[txq
->q
.read_ptr
].cmd
->payload
;
263 WARN_ON(read_ptr
>= TFD_QUEUE_SIZE_MAX
);
265 if (txq_id
!= trans_pcie
->cmd_queue
)
266 sta_id
= tx_cmd
->sta_id
;
268 bc_ent
= cpu_to_le16(1 | (sta_id
<< 12));
269 scd_bc_tbl
[txq_id
].tfd_offset
[read_ptr
] = bc_ent
;
271 if (read_ptr
< TFD_QUEUE_SIZE_BC_DUP
)
273 tfd_offset
[TFD_QUEUE_SIZE_MAX
+ read_ptr
] = bc_ent
;
277 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
279 void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans
*trans
, struct iwl_txq
*txq
)
282 int txq_id
= txq
->q
.id
;
284 if (txq
->need_update
== 0)
287 if (trans
->cfg
->base_params
->shadow_reg_enable
) {
288 /* shadow register enabled */
289 iwl_write32(trans
, HBUS_TARG_WRPTR
,
290 txq
->q
.write_ptr
| (txq_id
<< 8));
292 struct iwl_trans_pcie
*trans_pcie
=
293 IWL_TRANS_GET_PCIE_TRANS(trans
);
294 /* if we're trying to save power */
295 if (test_bit(STATUS_TPOWER_PMI
, &trans_pcie
->status
)) {
296 /* wake up nic if it's powered down ...
297 * uCode will wake up, and interrupt us again, so next
298 * time we'll skip this part. */
299 reg
= iwl_read32(trans
, CSR_UCODE_DRV_GP1
);
301 if (reg
& CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP
) {
302 IWL_DEBUG_INFO(trans
,
303 "Tx queue %d requesting wakeup,"
304 " GP1 = 0x%x\n", txq_id
, reg
);
305 iwl_set_bit(trans
, CSR_GP_CNTRL
,
306 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
310 iwl_write_direct32(trans
, HBUS_TARG_WRPTR
,
311 txq
->q
.write_ptr
| (txq_id
<< 8));
314 * else not in power-save mode,
315 * uCode will never sleep when we're
316 * trying to tx (during RFKILL, we're not trying to tx).
319 iwl_write32(trans
, HBUS_TARG_WRPTR
,
320 txq
->q
.write_ptr
| (txq_id
<< 8));
322 txq
->need_update
= 0;
325 static inline dma_addr_t
iwl_pcie_tfd_tb_get_addr(struct iwl_tfd
*tfd
, u8 idx
)
327 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
329 dma_addr_t addr
= get_unaligned_le32(&tb
->lo
);
330 if (sizeof(dma_addr_t
) > sizeof(u32
))
332 ((dma_addr_t
)(le16_to_cpu(tb
->hi_n_len
) & 0xF) << 16) << 16;
337 static inline u16
iwl_pcie_tfd_tb_get_len(struct iwl_tfd
*tfd
, u8 idx
)
339 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
341 return le16_to_cpu(tb
->hi_n_len
) >> 4;
344 static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd
*tfd
, u8 idx
,
345 dma_addr_t addr
, u16 len
)
347 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
348 u16 hi_n_len
= len
<< 4;
350 put_unaligned_le32(addr
, &tb
->lo
);
351 if (sizeof(dma_addr_t
) > sizeof(u32
))
352 hi_n_len
|= ((addr
>> 16) >> 16) & 0xF;
354 tb
->hi_n_len
= cpu_to_le16(hi_n_len
);
356 tfd
->num_tbs
= idx
+ 1;
359 static inline u8
iwl_pcie_tfd_get_num_tbs(struct iwl_tfd
*tfd
)
361 return tfd
->num_tbs
& 0x1f;
364 static void iwl_pcie_tfd_unmap(struct iwl_trans
*trans
,
365 struct iwl_cmd_meta
*meta
, struct iwl_tfd
*tfd
,
366 enum dma_data_direction dma_dir
)
371 /* Sanity check on number of chunks */
372 num_tbs
= iwl_pcie_tfd_get_num_tbs(tfd
);
374 if (num_tbs
>= IWL_NUM_OF_TBS
) {
375 IWL_ERR(trans
, "Too many chunks: %i\n", num_tbs
);
376 /* @todo issue fatal error, it is quite serious situation */
382 dma_unmap_single(trans
->dev
,
383 dma_unmap_addr(meta
, mapping
),
384 dma_unmap_len(meta
, len
),
387 /* Unmap chunks, if any. */
388 for (i
= 1; i
< num_tbs
; i
++)
389 dma_unmap_single(trans
->dev
, iwl_pcie_tfd_tb_get_addr(tfd
, i
),
390 iwl_pcie_tfd_tb_get_len(tfd
, i
), dma_dir
);
396 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
397 * @trans - transport private data
399 * @dma_dir - the direction of the DMA mapping
401 * Does NOT advance any TFD circular buffer read/write indexes
402 * Does NOT free the TFD itself (which is within circular buffer)
404 static void iwl_pcie_txq_free_tfd(struct iwl_trans
*trans
, struct iwl_txq
*txq
,
405 enum dma_data_direction dma_dir
)
407 struct iwl_tfd
*tfd_tmp
= txq
->tfds
;
409 /* rd_ptr is bounded by n_bd and idx is bounded by n_window */
410 int rd_ptr
= txq
->q
.read_ptr
;
411 int idx
= get_cmd_index(&txq
->q
, rd_ptr
);
413 lockdep_assert_held(&txq
->lock
);
415 /* We have only q->n_window txq->entries, but we use q->n_bd tfds */
416 iwl_pcie_tfd_unmap(trans
, &txq
->entries
[idx
].meta
, &tfd_tmp
[rd_ptr
],
423 skb
= txq
->entries
[idx
].skb
;
425 /* Can be called from irqs-disabled context
426 * If skb is not NULL, it means that the whole queue is being
427 * freed and that the queue is not empty - free the skb
430 iwl_op_mode_free_skb(trans
->op_mode
, skb
);
431 txq
->entries
[idx
].skb
= NULL
;
436 static int iwl_pcie_txq_build_tfd(struct iwl_trans
*trans
, struct iwl_txq
*txq
,
437 dma_addr_t addr
, u16 len
, u8 reset
)
440 struct iwl_tfd
*tfd
, *tfd_tmp
;
445 tfd
= &tfd_tmp
[q
->write_ptr
];
448 memset(tfd
, 0, sizeof(*tfd
));
450 num_tbs
= iwl_pcie_tfd_get_num_tbs(tfd
);
452 /* Each TFD can point to a maximum 20 Tx buffers */
453 if (num_tbs
>= IWL_NUM_OF_TBS
) {
454 IWL_ERR(trans
, "Error can not send more than %d chunks\n",
459 if (WARN_ON(addr
& ~DMA_BIT_MASK(36)))
462 if (unlikely(addr
& ~IWL_TX_DMA_MASK
))
463 IWL_ERR(trans
, "Unaligned address = %llx\n",
464 (unsigned long long)addr
);
466 iwl_pcie_tfd_set_tb(tfd
, num_tbs
, addr
, len
);
471 static int iwl_pcie_txq_alloc(struct iwl_trans
*trans
,
472 struct iwl_txq
*txq
, int slots_num
,
475 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
476 size_t tfd_sz
= sizeof(struct iwl_tfd
) * TFD_QUEUE_SIZE_MAX
;
479 if (WARN_ON(txq
->entries
|| txq
->tfds
))
482 setup_timer(&txq
->stuck_timer
, iwl_pcie_txq_stuck_timer
,
484 txq
->trans_pcie
= trans_pcie
;
486 txq
->q
.n_window
= slots_num
;
488 txq
->entries
= kcalloc(slots_num
,
489 sizeof(struct iwl_pcie_txq_entry
),
495 if (txq_id
== trans_pcie
->cmd_queue
)
496 for (i
= 0; i
< slots_num
; i
++) {
497 txq
->entries
[i
].cmd
=
498 kmalloc(sizeof(struct iwl_device_cmd
),
500 if (!txq
->entries
[i
].cmd
)
504 /* Circular buffer of transmit frame descriptors (TFDs),
505 * shared with device */
506 txq
->tfds
= dma_alloc_coherent(trans
->dev
, tfd_sz
,
507 &txq
->q
.dma_addr
, GFP_KERNEL
);
509 IWL_ERR(trans
, "dma_alloc_coherent(%zd) failed\n", tfd_sz
);
516 if (txq
->entries
&& txq_id
== trans_pcie
->cmd_queue
)
517 for (i
= 0; i
< slots_num
; i
++)
518 kfree(txq
->entries
[i
].cmd
);
526 static int iwl_pcie_txq_init(struct iwl_trans
*trans
, struct iwl_txq
*txq
,
527 int slots_num
, u32 txq_id
)
531 txq
->need_update
= 0;
533 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
534 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
535 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX
& (TFD_QUEUE_SIZE_MAX
- 1));
537 /* Initialize queue's high/low-water marks, and head/tail indexes */
538 ret
= iwl_queue_init(&txq
->q
, TFD_QUEUE_SIZE_MAX
, slots_num
,
543 spin_lock_init(&txq
->lock
);
546 * Tell nic where to find circular buffer of Tx Frame Descriptors for
547 * given Tx queue, and enable the DMA channel used for that queue.
548 * Circular buffer (TFD queue in DRAM) physical base address */
549 iwl_write_direct32(trans
, FH_MEM_CBBC_QUEUE(txq_id
),
550 txq
->q
.dma_addr
>> 8);
556 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's
558 static void iwl_pcie_txq_unmap(struct iwl_trans
*trans
, int txq_id
)
560 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
561 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
562 struct iwl_queue
*q
= &txq
->q
;
563 enum dma_data_direction dma_dir
;
568 /* In the command queue, all the TBs are mapped as BIDI
569 * so unmap them as such.
571 if (txq_id
== trans_pcie
->cmd_queue
)
572 dma_dir
= DMA_BIDIRECTIONAL
;
574 dma_dir
= DMA_TO_DEVICE
;
576 spin_lock_bh(&txq
->lock
);
577 while (q
->write_ptr
!= q
->read_ptr
) {
578 iwl_pcie_txq_free_tfd(trans
, txq
, dma_dir
);
579 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
);
581 spin_unlock_bh(&txq
->lock
);
585 * iwl_pcie_txq_free - Deallocate DMA queue.
586 * @txq: Transmit queue to deallocate.
588 * Empty queue by removing and destroying all BD's.
590 * 0-fill, but do not free "txq" descriptor structure.
592 static void iwl_pcie_txq_free(struct iwl_trans
*trans
, int txq_id
)
594 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
595 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
596 struct device
*dev
= trans
->dev
;
602 iwl_pcie_txq_unmap(trans
, txq_id
);
604 /* De-alloc array of command/tx buffers */
605 if (txq_id
== trans_pcie
->cmd_queue
)
606 for (i
= 0; i
< txq
->q
.n_window
; i
++) {
607 kfree(txq
->entries
[i
].cmd
);
608 kfree(txq
->entries
[i
].copy_cmd
);
609 kfree(txq
->entries
[i
].free_buf
);
612 /* De-alloc circular buffer of TFDs */
614 dma_free_coherent(dev
, sizeof(struct iwl_tfd
) *
615 txq
->q
.n_bd
, txq
->tfds
, txq
->q
.dma_addr
);
616 memset(&txq
->q
.dma_addr
, 0, sizeof(txq
->q
.dma_addr
));
622 del_timer_sync(&txq
->stuck_timer
);
624 /* 0-fill queue descriptor structure */
625 memset(txq
, 0, sizeof(*txq
));
629 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
631 static void iwl_pcie_txq_set_sched(struct iwl_trans
*trans
, u32 mask
)
633 struct iwl_trans_pcie __maybe_unused
*trans_pcie
=
634 IWL_TRANS_GET_PCIE_TRANS(trans
);
636 iwl_write_prph(trans
, SCD_TXFACT
, mask
);
639 void iwl_pcie_tx_start(struct iwl_trans
*trans
, u32 scd_base_addr
)
641 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
646 /* make sure all queue are not stopped/used */
647 memset(trans_pcie
->queue_stopped
, 0, sizeof(trans_pcie
->queue_stopped
));
648 memset(trans_pcie
->queue_used
, 0, sizeof(trans_pcie
->queue_used
));
650 trans_pcie
->scd_base_addr
=
651 iwl_read_prph(trans
, SCD_SRAM_BASE_ADDR
);
653 WARN_ON(scd_base_addr
!= 0 &&
654 scd_base_addr
!= trans_pcie
->scd_base_addr
);
656 a
= trans_pcie
->scd_base_addr
+ SCD_CONTEXT_MEM_LOWER_BOUND
;
657 /* reset conext data memory */
658 for (; a
< trans_pcie
->scd_base_addr
+ SCD_CONTEXT_MEM_UPPER_BOUND
;
660 iwl_write_targ_mem(trans
, a
, 0);
661 /* reset tx status memory */
662 for (; a
< trans_pcie
->scd_base_addr
+ SCD_TX_STTS_MEM_UPPER_BOUND
;
664 iwl_write_targ_mem(trans
, a
, 0);
665 for (; a
< trans_pcie
->scd_base_addr
+
666 SCD_TRANS_TBL_OFFSET_QUEUE(
667 trans
->cfg
->base_params
->num_of_queues
);
669 iwl_write_targ_mem(trans
, a
, 0);
671 iwl_write_prph(trans
, SCD_DRAM_BASE_ADDR
,
672 trans_pcie
->scd_bc_tbls
.dma
>> 10);
674 /* The chain extension of the SCD doesn't work well. This feature is
675 * enabled by default by the HW, so we need to disable it manually.
677 iwl_write_prph(trans
, SCD_CHAINEXT_EN
, 0);
679 iwl_trans_ac_txq_enable(trans
, trans_pcie
->cmd_queue
,
680 trans_pcie
->cmd_fifo
);
682 /* Activate all Tx DMA/FIFO channels */
683 iwl_pcie_txq_set_sched(trans
, IWL_MASK(0, 7));
685 /* Enable DMA channel */
686 for (chan
= 0; chan
< FH_TCSR_CHNL_NUM
; chan
++)
687 iwl_write_direct32(trans
, FH_TCSR_CHNL_TX_CONFIG_REG(chan
),
688 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
689 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE
);
691 /* Update FH chicken bits */
692 reg_val
= iwl_read_direct32(trans
, FH_TX_CHICKEN_BITS_REG
);
693 iwl_write_direct32(trans
, FH_TX_CHICKEN_BITS_REG
,
694 reg_val
| FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN
);
696 /* Enable L1-Active */
697 iwl_clear_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
698 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
702 * iwl_pcie_tx_stop - Stop all Tx DMA channels
704 int iwl_pcie_tx_stop(struct iwl_trans
*trans
)
706 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
710 /* Turn off all Tx DMA fifos */
711 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
713 iwl_pcie_txq_set_sched(trans
, 0);
715 /* Stop each Tx DMA channel, and wait for it to be idle */
716 for (ch
= 0; ch
< FH_TCSR_CHNL_NUM
; ch
++) {
717 iwl_write_direct32(trans
,
718 FH_TCSR_CHNL_TX_CONFIG_REG(ch
), 0x0);
719 ret
= iwl_poll_direct_bit(trans
, FH_TSSR_TX_STATUS_REG
,
720 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch
), 1000);
723 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
725 iwl_read_direct32(trans
,
726 FH_TSSR_TX_STATUS_REG
));
728 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
730 if (!trans_pcie
->txq
) {
732 "Stopping tx queues that aren't allocated...\n");
736 /* Unmap DMA from host system and free skb's */
737 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
739 iwl_pcie_txq_unmap(trans
, txq_id
);
745 * iwl_trans_tx_free - Free TXQ Context
747 * Destroy all TX DMA queues and structures
749 void iwl_pcie_tx_free(struct iwl_trans
*trans
)
752 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
755 if (trans_pcie
->txq
) {
757 txq_id
< trans
->cfg
->base_params
->num_of_queues
; txq_id
++)
758 iwl_pcie_txq_free(trans
, txq_id
);
761 kfree(trans_pcie
->txq
);
762 trans_pcie
->txq
= NULL
;
764 iwl_pcie_free_dma_ptr(trans
, &trans_pcie
->kw
);
766 iwl_pcie_free_dma_ptr(trans
, &trans_pcie
->scd_bc_tbls
);
770 * iwl_pcie_tx_alloc - allocate TX context
771 * Allocate all Tx DMA structures and initialize them
773 static int iwl_pcie_tx_alloc(struct iwl_trans
*trans
)
776 int txq_id
, slots_num
;
777 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
779 u16 scd_bc_tbls_size
= trans
->cfg
->base_params
->num_of_queues
*
780 sizeof(struct iwlagn_scd_bc_tbl
);
782 /*It is not allowed to alloc twice, so warn when this happens.
783 * We cannot rely on the previous allocation, so free and fail */
784 if (WARN_ON(trans_pcie
->txq
)) {
789 ret
= iwl_pcie_alloc_dma_ptr(trans
, &trans_pcie
->scd_bc_tbls
,
792 IWL_ERR(trans
, "Scheduler BC Table allocation failed\n");
796 /* Alloc keep-warm buffer */
797 ret
= iwl_pcie_alloc_dma_ptr(trans
, &trans_pcie
->kw
, IWL_KW_SIZE
);
799 IWL_ERR(trans
, "Keep Warm allocation failed\n");
803 trans_pcie
->txq
= kcalloc(trans
->cfg
->base_params
->num_of_queues
,
804 sizeof(struct iwl_txq
), GFP_KERNEL
);
805 if (!trans_pcie
->txq
) {
806 IWL_ERR(trans
, "Not enough memory for txq\n");
811 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
812 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
814 slots_num
= (txq_id
== trans_pcie
->cmd_queue
) ?
815 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
816 ret
= iwl_pcie_txq_alloc(trans
, &trans_pcie
->txq
[txq_id
],
819 IWL_ERR(trans
, "Tx %d queue alloc failed\n", txq_id
);
827 iwl_pcie_tx_free(trans
);
831 int iwl_pcie_tx_init(struct iwl_trans
*trans
)
833 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
835 int txq_id
, slots_num
;
839 if (!trans_pcie
->txq
) {
840 ret
= iwl_pcie_tx_alloc(trans
);
846 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
848 /* Turn off all Tx DMA fifos */
849 iwl_write_prph(trans
, SCD_TXFACT
, 0);
851 /* Tell NIC where to find the "keep warm" buffer */
852 iwl_write_direct32(trans
, FH_KW_MEM_ADDR_REG
,
853 trans_pcie
->kw
.dma
>> 4);
855 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
857 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
858 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
860 slots_num
= (txq_id
== trans_pcie
->cmd_queue
) ?
861 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
862 ret
= iwl_pcie_txq_init(trans
, &trans_pcie
->txq
[txq_id
],
865 IWL_ERR(trans
, "Tx %d queue init failed\n", txq_id
);
872 /*Upon error, free only if we allocated something */
874 iwl_pcie_tx_free(trans
);
878 static inline void iwl_pcie_txq_progress(struct iwl_trans_pcie
*trans_pcie
,
881 if (!trans_pcie
->wd_timeout
)
885 * if empty delete timer, otherwise move timer forward
886 * since we're making progress on this queue
888 if (txq
->q
.read_ptr
== txq
->q
.write_ptr
)
889 del_timer(&txq
->stuck_timer
);
891 mod_timer(&txq
->stuck_timer
, jiffies
+ trans_pcie
->wd_timeout
);
894 /* Frees buffers until index _not_ inclusive */
895 static int iwl_pcie_txq_reclaim(struct iwl_trans
*trans
, int txq_id
, int index
,
896 struct sk_buff_head
*skbs
)
898 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
899 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
900 struct iwl_queue
*q
= &txq
->q
;
904 /* This function is not meant to release cmd queue*/
905 if (WARN_ON(txq_id
== trans_pcie
->cmd_queue
))
908 lockdep_assert_held(&txq
->lock
);
910 /*Since we free until index _not_ inclusive, the one before index is
911 * the last we will free. This one must be used */
912 last_to_free
= iwl_queue_dec_wrap(index
, q
->n_bd
);
914 if ((index
>= q
->n_bd
) ||
915 (iwl_queue_used(q
, last_to_free
) == 0)) {
917 "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
918 __func__
, txq_id
, last_to_free
, q
->n_bd
,
919 q
->write_ptr
, q
->read_ptr
);
923 if (WARN_ON(!skb_queue_empty(skbs
)))
927 q
->read_ptr
!= index
;
928 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
930 if (WARN_ON_ONCE(txq
->entries
[txq
->q
.read_ptr
].skb
== NULL
))
933 __skb_queue_tail(skbs
, txq
->entries
[txq
->q
.read_ptr
].skb
);
935 txq
->entries
[txq
->q
.read_ptr
].skb
= NULL
;
937 iwl_pcie_txq_inval_byte_cnt_tbl(trans
, txq
);
939 iwl_pcie_txq_free_tfd(trans
, txq
, DMA_TO_DEVICE
);
943 iwl_pcie_txq_progress(trans_pcie
, txq
);
948 void iwl_trans_pcie_reclaim(struct iwl_trans
*trans
, int txq_id
, int ssn
,
949 struct sk_buff_head
*skbs
)
951 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
952 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
953 /* n_bd is usually 256 => n_bd - 1 = 0xff */
954 int tfd_num
= ssn
& (txq
->q
.n_bd
- 1);
956 spin_lock(&txq
->lock
);
958 if (txq
->q
.read_ptr
!= tfd_num
) {
959 IWL_DEBUG_TX_REPLY(trans
, "[Q %d] %d -> %d (%d)\n",
960 txq_id
, txq
->q
.read_ptr
, tfd_num
, ssn
);
961 iwl_pcie_txq_reclaim(trans
, txq_id
, tfd_num
, skbs
);
962 if (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
)
963 iwl_wake_queue(trans
, txq
);
966 spin_unlock(&txq
->lock
);
970 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
972 * When FW advances 'R' index, all entries between old and new 'R' index
973 * need to be reclaimed. As result, some free space forms. If there is
974 * enough free space (> low mark), wake the stack that feeds us.
976 static void iwl_pcie_cmdq_reclaim(struct iwl_trans
*trans
, int txq_id
, int idx
)
978 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
979 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
980 struct iwl_queue
*q
= &txq
->q
;
983 lockdep_assert_held(&txq
->lock
);
985 if ((idx
>= q
->n_bd
) || (iwl_queue_used(q
, idx
) == 0)) {
987 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
988 __func__
, txq_id
, idx
, q
->n_bd
,
989 q
->write_ptr
, q
->read_ptr
);
993 for (idx
= iwl_queue_inc_wrap(idx
, q
->n_bd
); q
->read_ptr
!= idx
;
994 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
997 IWL_ERR(trans
, "HCMD skipped: index (%d) %d %d\n",
998 idx
, q
->write_ptr
, q
->read_ptr
);
999 iwl_op_mode_nic_error(trans
->op_mode
);
1003 iwl_pcie_txq_progress(trans_pcie
, txq
);
1006 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans
*trans
, u16 ra_tid
,
1009 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1014 scd_q2ratid
= ra_tid
& SCD_QUEUE_RA_TID_MAP_RATID_MSK
;
1016 tbl_dw_addr
= trans_pcie
->scd_base_addr
+
1017 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id
);
1019 tbl_dw
= iwl_read_targ_mem(trans
, tbl_dw_addr
);
1022 tbl_dw
= (scd_q2ratid
<< 16) | (tbl_dw
& 0x0000FFFF);
1024 tbl_dw
= scd_q2ratid
| (tbl_dw
& 0xFFFF0000);
1026 iwl_write_targ_mem(trans
, tbl_dw_addr
, tbl_dw
);
1031 static inline void iwl_pcie_txq_set_inactive(struct iwl_trans
*trans
,
1034 /* Simply stop the queue, but don't change any configuration;
1035 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1036 iwl_write_prph(trans
,
1037 SCD_QUEUE_STATUS_BITS(txq_id
),
1038 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE
)|
1039 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN
));
1042 void iwl_trans_pcie_txq_enable(struct iwl_trans
*trans
, int txq_id
, int fifo
,
1043 int sta_id
, int tid
, int frame_limit
, u16 ssn
)
1045 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1047 if (test_and_set_bit(txq_id
, trans_pcie
->queue_used
))
1048 WARN_ONCE(1, "queue %d already used - expect issues", txq_id
);
1050 /* Stop this Tx queue before configuring it */
1051 iwl_pcie_txq_set_inactive(trans
, txq_id
);
1053 /* Set this queue as a chain-building queue unless it is CMD queue */
1054 if (txq_id
!= trans_pcie
->cmd_queue
)
1055 iwl_set_bits_prph(trans
, SCD_QUEUECHAIN_SEL
, BIT(txq_id
));
1057 /* If this queue is mapped to a certain station: it is an AGG queue */
1058 if (sta_id
!= IWL_INVALID_STATION
) {
1059 u16 ra_tid
= BUILD_RAxTID(sta_id
, tid
);
1061 /* Map receiver-address / traffic-ID to this queue */
1062 iwl_pcie_txq_set_ratid_map(trans
, ra_tid
, txq_id
);
1064 /* enable aggregations for the queue */
1065 iwl_set_bits_prph(trans
, SCD_AGGR_SEL
, BIT(txq_id
));
1068 * disable aggregations for the queue, this will also make the
1069 * ra_tid mapping configuration irrelevant since it is now a
1072 iwl_clear_bits_prph(trans
, SCD_AGGR_SEL
, BIT(txq_id
));
1075 /* Place first TFD at index corresponding to start sequence number.
1076 * Assumes that ssn_idx is valid (!= 0xFFF) */
1077 trans_pcie
->txq
[txq_id
].q
.read_ptr
= (ssn
& 0xff);
1078 trans_pcie
->txq
[txq_id
].q
.write_ptr
= (ssn
& 0xff);
1080 iwl_write_direct32(trans
, HBUS_TARG_WRPTR
,
1081 (ssn
& 0xff) | (txq_id
<< 8));
1082 iwl_write_prph(trans
, SCD_QUEUE_RDPTR(txq_id
), ssn
);
1084 /* Set up Tx window size and frame limit for this queue */
1085 iwl_write_targ_mem(trans
, trans_pcie
->scd_base_addr
+
1086 SCD_CONTEXT_QUEUE_OFFSET(txq_id
), 0);
1087 iwl_write_targ_mem(trans
, trans_pcie
->scd_base_addr
+
1088 SCD_CONTEXT_QUEUE_OFFSET(txq_id
) + sizeof(u32
),
1089 ((frame_limit
<< SCD_QUEUE_CTX_REG2_WIN_SIZE_POS
) &
1090 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK
) |
1091 ((frame_limit
<< SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS
) &
1092 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK
));
1094 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1095 iwl_write_prph(trans
, SCD_QUEUE_STATUS_BITS(txq_id
),
1096 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE
) |
1097 (fifo
<< SCD_QUEUE_STTS_REG_POS_TXF
) |
1098 (1 << SCD_QUEUE_STTS_REG_POS_WSL
) |
1099 SCD_QUEUE_STTS_REG_MSK
);
1100 IWL_DEBUG_TX_QUEUES(trans
, "Activate queue %d on FIFO %d WrPtr: %d\n",
1101 txq_id
, fifo
, ssn
& 0xff);
1104 void iwl_trans_pcie_txq_disable(struct iwl_trans
*trans
, int txq_id
)
1106 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1107 u32 stts_addr
= trans_pcie
->scd_base_addr
+
1108 SCD_TX_STTS_QUEUE_OFFSET(txq_id
);
1109 static const u32 zero_val
[4] = {};
1111 if (!test_and_clear_bit(txq_id
, trans_pcie
->queue_used
)) {
1112 WARN_ONCE(1, "queue %d not used", txq_id
);
1116 iwl_pcie_txq_set_inactive(trans
, txq_id
);
1118 _iwl_write_targ_mem_dwords(trans
, stts_addr
,
1119 zero_val
, ARRAY_SIZE(zero_val
));
1121 iwl_pcie_txq_unmap(trans
, txq_id
);
1123 IWL_DEBUG_TX_QUEUES(trans
, "Deactivate queue %d\n", txq_id
);
1126 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1129 * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1130 * @priv: device private data point
1131 * @cmd: a point to the ucode command structure
1133 * The function returns < 0 values to indicate the operation is
1134 * failed. On success, it turns the index (> 0) of command in the
1137 static int iwl_pcie_enqueue_hcmd(struct iwl_trans
*trans
,
1138 struct iwl_host_cmd
*cmd
)
1140 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1141 struct iwl_txq
*txq
= &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
1142 struct iwl_queue
*q
= &txq
->q
;
1143 struct iwl_device_cmd
*out_cmd
;
1144 struct iwl_cmd_meta
*out_meta
;
1145 void *dup_buf
= NULL
;
1146 dma_addr_t phys_addr
;
1148 u16 copy_size
, cmd_size
;
1149 bool had_nocopy
= false;
1153 copy_size
= sizeof(out_cmd
->hdr
);
1154 cmd_size
= sizeof(out_cmd
->hdr
);
1156 /* need one for the header if the first is NOCOPY */
1157 BUILD_BUG_ON(IWL_MAX_CMD_TFDS
> IWL_NUM_OF_TBS
- 1);
1159 for (i
= 0; i
< IWL_MAX_CMD_TFDS
; i
++) {
1162 if (cmd
->dataflags
[i
] & IWL_HCMD_DFL_NOCOPY
) {
1164 if (WARN_ON(cmd
->dataflags
[i
] & IWL_HCMD_DFL_DUP
)) {
1168 } else if (cmd
->dataflags
[i
] & IWL_HCMD_DFL_DUP
) {
1170 * This is also a chunk that isn't copied
1171 * to the static buffer so set had_nocopy.
1175 /* only allowed once */
1176 if (WARN_ON(dup_buf
)) {
1181 dup_buf
= kmemdup(cmd
->data
[i
], cmd
->len
[i
],
1186 /* NOCOPY must not be followed by normal! */
1187 if (WARN_ON(had_nocopy
)) {
1191 copy_size
+= cmd
->len
[i
];
1193 cmd_size
+= cmd
->len
[i
];
1197 * If any of the command structures end up being larger than
1198 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1199 * allocated into separate TFDs, then we will need to
1200 * increase the size of the buffers.
1202 if (WARN(copy_size
> TFD_MAX_PAYLOAD_SIZE
,
1203 "Command %s (%#x) is too large (%d bytes)\n",
1204 get_cmd_string(trans_pcie
, cmd
->id
), cmd
->id
, copy_size
)) {
1209 spin_lock_bh(&txq
->lock
);
1211 if (iwl_queue_space(q
) < ((cmd
->flags
& CMD_ASYNC
) ? 2 : 1)) {
1212 spin_unlock_bh(&txq
->lock
);
1214 IWL_ERR(trans
, "No space in command queue\n");
1215 iwl_op_mode_cmd_queue_full(trans
->op_mode
);
1220 idx
= get_cmd_index(q
, q
->write_ptr
);
1221 out_cmd
= txq
->entries
[idx
].cmd
;
1222 out_meta
= &txq
->entries
[idx
].meta
;
1224 memset(out_meta
, 0, sizeof(*out_meta
)); /* re-initialize to NULL */
1225 if (cmd
->flags
& CMD_WANT_SKB
)
1226 out_meta
->source
= cmd
;
1228 /* set up the header */
1230 out_cmd
->hdr
.cmd
= cmd
->id
;
1231 out_cmd
->hdr
.flags
= 0;
1232 out_cmd
->hdr
.sequence
=
1233 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie
->cmd_queue
) |
1234 INDEX_TO_SEQ(q
->write_ptr
));
1236 /* and copy the data that needs to be copied */
1237 cmd_pos
= offsetof(struct iwl_device_cmd
, payload
);
1238 for (i
= 0; i
< IWL_MAX_CMD_TFDS
; i
++) {
1241 if (cmd
->dataflags
[i
] & (IWL_HCMD_DFL_NOCOPY
|
1244 memcpy((u8
*)out_cmd
+ cmd_pos
, cmd
->data
[i
], cmd
->len
[i
]);
1245 cmd_pos
+= cmd
->len
[i
];
1248 WARN_ON_ONCE(txq
->entries
[idx
].copy_cmd
);
1251 * since out_cmd will be the source address of the FH, it will write
1252 * the retry count there. So when the user needs to receivce the HCMD
1253 * that corresponds to the response in the response handler, it needs
1254 * to set CMD_WANT_HCMD.
1256 if (cmd
->flags
& CMD_WANT_HCMD
) {
1257 txq
->entries
[idx
].copy_cmd
=
1258 kmemdup(out_cmd
, cmd_pos
, GFP_ATOMIC
);
1259 if (unlikely(!txq
->entries
[idx
].copy_cmd
)) {
1266 "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1267 get_cmd_string(trans_pcie
, out_cmd
->hdr
.cmd
),
1268 out_cmd
->hdr
.cmd
, le16_to_cpu(out_cmd
->hdr
.sequence
),
1269 cmd_size
, q
->write_ptr
, idx
, trans_pcie
->cmd_queue
);
1271 phys_addr
= dma_map_single(trans
->dev
, &out_cmd
->hdr
, copy_size
,
1273 if (unlikely(dma_mapping_error(trans
->dev
, phys_addr
))) {
1278 dma_unmap_addr_set(out_meta
, mapping
, phys_addr
);
1279 dma_unmap_len_set(out_meta
, len
, copy_size
);
1281 iwl_pcie_txq_build_tfd(trans
, txq
, phys_addr
, copy_size
, 1);
1283 for (i
= 0; i
< IWL_MAX_CMD_TFDS
; i
++) {
1284 const void *data
= cmd
->data
[i
];
1288 if (!(cmd
->dataflags
[i
] & (IWL_HCMD_DFL_NOCOPY
|
1291 if (cmd
->dataflags
[i
] & IWL_HCMD_DFL_DUP
)
1293 phys_addr
= dma_map_single(trans
->dev
, (void *)data
,
1294 cmd
->len
[i
], DMA_BIDIRECTIONAL
);
1295 if (dma_mapping_error(trans
->dev
, phys_addr
)) {
1296 iwl_pcie_tfd_unmap(trans
, out_meta
,
1297 &txq
->tfds
[q
->write_ptr
],
1303 iwl_pcie_txq_build_tfd(trans
, txq
, phys_addr
, cmd
->len
[i
], 0);
1306 out_meta
->flags
= cmd
->flags
;
1307 if (WARN_ON_ONCE(txq
->entries
[idx
].free_buf
))
1308 kfree(txq
->entries
[idx
].free_buf
);
1309 txq
->entries
[idx
].free_buf
= dup_buf
;
1311 txq
->need_update
= 1;
1313 trace_iwlwifi_dev_hcmd(trans
->dev
, cmd
, cmd_size
,
1314 &out_cmd
->hdr
, copy_size
);
1316 /* start timer if queue currently empty */
1317 if (q
->read_ptr
== q
->write_ptr
&& trans_pcie
->wd_timeout
)
1318 mod_timer(&txq
->stuck_timer
, jiffies
+ trans_pcie
->wd_timeout
);
1320 /* Increment and update queue's write index */
1321 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
1322 iwl_pcie_txq_inc_wr_ptr(trans
, txq
);
1325 spin_unlock_bh(&txq
->lock
);
1333 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1334 * @rxb: Rx buffer to reclaim
1335 * @handler_status: return value of the handler of the command
1336 * (put in setup_rx_handlers)
1338 * If an Rx buffer has an async callback associated with it the callback
1339 * will be executed. The attached skb (if present) will only be freed
1340 * if the callback returns 1
1342 void iwl_pcie_hcmd_complete(struct iwl_trans
*trans
,
1343 struct iwl_rx_cmd_buffer
*rxb
, int handler_status
)
1345 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
1346 u16 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
1347 int txq_id
= SEQ_TO_QUEUE(sequence
);
1348 int index
= SEQ_TO_INDEX(sequence
);
1350 struct iwl_device_cmd
*cmd
;
1351 struct iwl_cmd_meta
*meta
;
1352 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1353 struct iwl_txq
*txq
= &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
1355 /* If a Tx command is being handled and it isn't in the actual
1356 * command queue then there a command routing bug has been introduced
1357 * in the queue management code. */
1358 if (WARN(txq_id
!= trans_pcie
->cmd_queue
,
1359 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1360 txq_id
, trans_pcie
->cmd_queue
, sequence
,
1361 trans_pcie
->txq
[trans_pcie
->cmd_queue
].q
.read_ptr
,
1362 trans_pcie
->txq
[trans_pcie
->cmd_queue
].q
.write_ptr
)) {
1363 iwl_print_hex_error(trans
, pkt
, 32);
1367 spin_lock(&txq
->lock
);
1369 cmd_index
= get_cmd_index(&txq
->q
, index
);
1370 cmd
= txq
->entries
[cmd_index
].cmd
;
1371 meta
= &txq
->entries
[cmd_index
].meta
;
1373 iwl_pcie_tfd_unmap(trans
, meta
, &txq
->tfds
[index
], DMA_BIDIRECTIONAL
);
1375 /* Input error checking is done when commands are added to queue. */
1376 if (meta
->flags
& CMD_WANT_SKB
) {
1377 struct page
*p
= rxb_steal_page(rxb
);
1379 meta
->source
->resp_pkt
= pkt
;
1380 meta
->source
->_rx_page_addr
= (unsigned long)page_address(p
);
1381 meta
->source
->_rx_page_order
= trans_pcie
->rx_page_order
;
1382 meta
->source
->handler_status
= handler_status
;
1385 iwl_pcie_cmdq_reclaim(trans
, txq_id
, index
);
1387 if (!(meta
->flags
& CMD_ASYNC
)) {
1388 if (!test_bit(STATUS_HCMD_ACTIVE
, &trans_pcie
->status
)) {
1390 "HCMD_ACTIVE already clear for command %s\n",
1391 get_cmd_string(trans_pcie
, cmd
->hdr
.cmd
));
1393 clear_bit(STATUS_HCMD_ACTIVE
, &trans_pcie
->status
);
1394 IWL_DEBUG_INFO(trans
, "Clearing HCMD_ACTIVE for command %s\n",
1395 get_cmd_string(trans_pcie
, cmd
->hdr
.cmd
));
1396 wake_up(&trans_pcie
->wait_command_queue
);
1401 spin_unlock(&txq
->lock
);
1404 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
1406 static int iwl_pcie_send_hcmd_async(struct iwl_trans
*trans
,
1407 struct iwl_host_cmd
*cmd
)
1409 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1412 /* An asynchronous command can not expect an SKB to be set. */
1413 if (WARN_ON(cmd
->flags
& CMD_WANT_SKB
))
1417 ret
= iwl_pcie_enqueue_hcmd(trans
, cmd
);
1420 "Error sending %s: enqueue_hcmd failed: %d\n",
1421 get_cmd_string(trans_pcie
, cmd
->id
), ret
);
1427 static int iwl_pcie_send_hcmd_sync(struct iwl_trans
*trans
,
1428 struct iwl_host_cmd
*cmd
)
1430 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1434 IWL_DEBUG_INFO(trans
, "Attempting to send sync command %s\n",
1435 get_cmd_string(trans_pcie
, cmd
->id
));
1437 if (WARN_ON(test_and_set_bit(STATUS_HCMD_ACTIVE
,
1438 &trans_pcie
->status
))) {
1439 IWL_ERR(trans
, "Command %s: a command is already active!\n",
1440 get_cmd_string(trans_pcie
, cmd
->id
));
1444 IWL_DEBUG_INFO(trans
, "Setting HCMD_ACTIVE for command %s\n",
1445 get_cmd_string(trans_pcie
, cmd
->id
));
1447 cmd_idx
= iwl_pcie_enqueue_hcmd(trans
, cmd
);
1450 clear_bit(STATUS_HCMD_ACTIVE
, &trans_pcie
->status
);
1452 "Error sending %s: enqueue_hcmd failed: %d\n",
1453 get_cmd_string(trans_pcie
, cmd
->id
), ret
);
1457 ret
= wait_event_timeout(trans_pcie
->wait_command_queue
,
1458 !test_bit(STATUS_HCMD_ACTIVE
,
1459 &trans_pcie
->status
),
1460 HOST_COMPLETE_TIMEOUT
);
1462 if (test_bit(STATUS_HCMD_ACTIVE
, &trans_pcie
->status
)) {
1463 struct iwl_txq
*txq
=
1464 &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
1465 struct iwl_queue
*q
= &txq
->q
;
1468 "Error sending %s: time out after %dms.\n",
1469 get_cmd_string(trans_pcie
, cmd
->id
),
1470 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT
));
1473 "Current CMD queue read_ptr %d write_ptr %d\n",
1474 q
->read_ptr
, q
->write_ptr
);
1476 clear_bit(STATUS_HCMD_ACTIVE
, &trans_pcie
->status
);
1477 IWL_DEBUG_INFO(trans
,
1478 "Clearing HCMD_ACTIVE for command %s\n",
1479 get_cmd_string(trans_pcie
, cmd
->id
));
1485 if (test_bit(STATUS_FW_ERROR
, &trans_pcie
->status
)) {
1486 IWL_ERR(trans
, "FW error in SYNC CMD %s\n",
1487 get_cmd_string(trans_pcie
, cmd
->id
));
1492 if (test_bit(STATUS_RFKILL
, &trans_pcie
->status
)) {
1493 IWL_DEBUG_RF_KILL(trans
, "RFKILL in SYNC CMD... no rsp\n");
1498 if ((cmd
->flags
& CMD_WANT_SKB
) && !cmd
->resp_pkt
) {
1499 IWL_ERR(trans
, "Error: Response NULL in '%s'\n",
1500 get_cmd_string(trans_pcie
, cmd
->id
));
1508 if (cmd
->flags
& CMD_WANT_SKB
) {
1510 * Cancel the CMD_WANT_SKB flag for the cmd in the
1511 * TX cmd queue. Otherwise in case the cmd comes
1512 * in later, it will possibly set an invalid
1513 * address (cmd->meta.source).
1515 trans_pcie
->txq
[trans_pcie
->cmd_queue
].
1516 entries
[cmd_idx
].meta
.flags
&= ~CMD_WANT_SKB
;
1519 if (cmd
->resp_pkt
) {
1521 cmd
->resp_pkt
= NULL
;
1527 int iwl_trans_pcie_send_hcmd(struct iwl_trans
*trans
, struct iwl_host_cmd
*cmd
)
1529 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1531 if (test_bit(STATUS_FW_ERROR
, &trans_pcie
->status
))
1534 if (test_bit(STATUS_RFKILL
, &trans_pcie
->status
))
1537 if (cmd
->flags
& CMD_ASYNC
)
1538 return iwl_pcie_send_hcmd_async(trans
, cmd
);
1540 /* We still can fail on RFKILL that can be asserted while we wait */
1541 return iwl_pcie_send_hcmd_sync(trans
, cmd
);
1544 int iwl_trans_pcie_tx(struct iwl_trans
*trans
, struct sk_buff
*skb
,
1545 struct iwl_device_cmd
*dev_cmd
, int txq_id
)
1547 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1548 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1549 struct iwl_tx_cmd
*tx_cmd
= (struct iwl_tx_cmd
*)dev_cmd
->payload
;
1550 struct iwl_cmd_meta
*out_meta
;
1551 struct iwl_txq
*txq
;
1552 struct iwl_queue
*q
;
1553 dma_addr_t phys_addr
= 0;
1554 dma_addr_t txcmd_phys
;
1555 dma_addr_t scratch_phys
;
1556 u16 len
, firstlen
, secondlen
;
1557 u8 wait_write_ptr
= 0;
1558 __le16 fc
= hdr
->frame_control
;
1559 u8 hdr_len
= ieee80211_hdrlen(fc
);
1560 u16 __maybe_unused wifi_seq
;
1562 txq
= &trans_pcie
->txq
[txq_id
];
1565 if (unlikely(!test_bit(txq_id
, trans_pcie
->queue_used
))) {
1570 spin_lock(&txq
->lock
);
1572 /* In AGG mode, the index in the ring must correspond to the WiFi
1573 * sequence number. This is a HW requirements to help the SCD to parse
1575 * Check here that the packets are in the right place on the ring.
1577 #ifdef CONFIG_IWLWIFI_DEBUG
1578 wifi_seq
= SEQ_TO_SN(le16_to_cpu(hdr
->seq_ctrl
));
1579 WARN_ONCE((iwl_read_prph(trans
, SCD_AGGR_SEL
) & BIT(txq_id
)) &&
1580 ((wifi_seq
& 0xff) != q
->write_ptr
),
1581 "Q: %d WiFi Seq %d tfdNum %d",
1582 txq_id
, wifi_seq
, q
->write_ptr
);
1585 /* Set up driver data for this TFD */
1586 txq
->entries
[q
->write_ptr
].skb
= skb
;
1587 txq
->entries
[q
->write_ptr
].cmd
= dev_cmd
;
1589 dev_cmd
->hdr
.cmd
= REPLY_TX
;
1590 dev_cmd
->hdr
.sequence
=
1591 cpu_to_le16((u16
)(QUEUE_TO_SEQ(txq_id
) |
1592 INDEX_TO_SEQ(q
->write_ptr
)));
1594 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1595 out_meta
= &txq
->entries
[q
->write_ptr
].meta
;
1598 * Use the first empty entry in this queue's command buffer array
1599 * to contain the Tx command and MAC header concatenated together
1600 * (payload data will be in another buffer).
1601 * Size of this varies, due to varying MAC header length.
1602 * If end is not dword aligned, we'll have 2 extra bytes at the end
1603 * of the MAC header (device reads on dword boundaries).
1604 * We'll tell device about this padding later.
1606 len
= sizeof(struct iwl_tx_cmd
) +
1607 sizeof(struct iwl_cmd_header
) + hdr_len
;
1608 firstlen
= (len
+ 3) & ~3;
1610 /* Tell NIC about any 2-byte padding after MAC header */
1611 if (firstlen
!= len
)
1612 tx_cmd
->tx_flags
|= TX_CMD_FLG_MH_PAD_MSK
;
1614 /* Physical address of this Tx command's header (not MAC header!),
1615 * within command buffer array. */
1616 txcmd_phys
= dma_map_single(trans
->dev
,
1617 &dev_cmd
->hdr
, firstlen
,
1619 if (unlikely(dma_mapping_error(trans
->dev
, txcmd_phys
)))
1621 dma_unmap_addr_set(out_meta
, mapping
, txcmd_phys
);
1622 dma_unmap_len_set(out_meta
, len
, firstlen
);
1624 if (!ieee80211_has_morefrags(fc
)) {
1625 txq
->need_update
= 1;
1628 txq
->need_update
= 0;
1631 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1632 * if any (802.11 null frames have no payload). */
1633 secondlen
= skb
->len
- hdr_len
;
1634 if (secondlen
> 0) {
1635 phys_addr
= dma_map_single(trans
->dev
, skb
->data
+ hdr_len
,
1636 secondlen
, DMA_TO_DEVICE
);
1637 if (unlikely(dma_mapping_error(trans
->dev
, phys_addr
))) {
1638 dma_unmap_single(trans
->dev
,
1639 dma_unmap_addr(out_meta
, mapping
),
1640 dma_unmap_len(out_meta
, len
),
1646 /* Attach buffers to TFD */
1647 iwl_pcie_txq_build_tfd(trans
, txq
, txcmd_phys
, firstlen
, 1);
1649 iwl_pcie_txq_build_tfd(trans
, txq
, phys_addr
, secondlen
, 0);
1651 scratch_phys
= txcmd_phys
+ sizeof(struct iwl_cmd_header
) +
1652 offsetof(struct iwl_tx_cmd
, scratch
);
1654 /* take back ownership of DMA buffer to enable update */
1655 dma_sync_single_for_cpu(trans
->dev
, txcmd_phys
, firstlen
,
1657 tx_cmd
->dram_lsb_ptr
= cpu_to_le32(scratch_phys
);
1658 tx_cmd
->dram_msb_ptr
= iwl_get_dma_hi_addr(scratch_phys
);
1660 IWL_DEBUG_TX(trans
, "sequence nr = 0X%x\n",
1661 le16_to_cpu(dev_cmd
->hdr
.sequence
));
1662 IWL_DEBUG_TX(trans
, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd
->tx_flags
));
1664 /* Set up entry for this TFD in Tx byte-count array */
1665 iwl_pcie_txq_update_byte_cnt_tbl(trans
, txq
, le16_to_cpu(tx_cmd
->len
));
1667 dma_sync_single_for_device(trans
->dev
, txcmd_phys
, firstlen
,
1670 trace_iwlwifi_dev_tx(trans
->dev
, skb
,
1671 &txq
->tfds
[txq
->q
.write_ptr
],
1672 sizeof(struct iwl_tfd
),
1673 &dev_cmd
->hdr
, firstlen
,
1674 skb
->data
+ hdr_len
, secondlen
);
1675 trace_iwlwifi_dev_tx_data(trans
->dev
, skb
,
1676 skb
->data
+ hdr_len
, secondlen
);
1678 /* start timer if queue currently empty */
1679 if (txq
->need_update
&& q
->read_ptr
== q
->write_ptr
&&
1680 trans_pcie
->wd_timeout
)
1681 mod_timer(&txq
->stuck_timer
, jiffies
+ trans_pcie
->wd_timeout
);
1683 /* Tell device the write index *just past* this latest filled TFD */
1684 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
1685 iwl_pcie_txq_inc_wr_ptr(trans
, txq
);
1688 * At this point the frame is "transmitted" successfully
1689 * and we will get a TX status notification eventually,
1690 * regardless of the value of ret. "ret" only indicates
1691 * whether or not we should update the write pointer.
1693 if (iwl_queue_space(q
) < q
->high_mark
) {
1694 if (wait_write_ptr
) {
1695 txq
->need_update
= 1;
1696 iwl_pcie_txq_inc_wr_ptr(trans
, txq
);
1698 iwl_stop_queue(trans
, txq
);
1701 spin_unlock(&txq
->lock
);
1704 spin_unlock(&txq
->lock
);