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mwl8k: allow more time for firmware commands to complete
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
1 /*
2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
4 *
5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/sched.h>
16 #include <linux/spinlock.h>
17 #include <linux/list.h>
18 #include <linux/pci.h>
19 #include <linux/delay.h>
20 #include <linux/completion.h>
21 #include <linux/etherdevice.h>
22 #include <net/mac80211.h>
23 #include <linux/moduleparam.h>
24 #include <linux/firmware.h>
25 #include <linux/workqueue.h>
26
27 #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28 #define MWL8K_NAME KBUILD_MODNAME
29 #define MWL8K_VERSION "0.10"
30
31 /* Register definitions */
32 #define MWL8K_HIU_GEN_PTR 0x00000c10
33 #define MWL8K_MODE_STA 0x0000005a
34 #define MWL8K_MODE_AP 0x000000a5
35 #define MWL8K_HIU_INT_CODE 0x00000c14
36 #define MWL8K_FWSTA_READY 0xf0f1f2f4
37 #define MWL8K_FWAP_READY 0xf1f2f4a5
38 #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
39 #define MWL8K_HIU_SCRATCH 0x00000c40
40
41 /* Host->device communications */
42 #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43 #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44 #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45 #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46 #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
47 #define MWL8K_H2A_INT_DUMMY (1 << 20)
48 #define MWL8K_H2A_INT_RESET (1 << 15)
49 #define MWL8K_H2A_INT_DOORBELL (1 << 1)
50 #define MWL8K_H2A_INT_PPA_READY (1 << 0)
51
52 /* Device->host communications */
53 #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54 #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55 #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56 #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57 #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
58 #define MWL8K_A2H_INT_DUMMY (1 << 20)
59 #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60 #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61 #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62 #define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63 #define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64 #define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65 #define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66 #define MWL8K_A2H_INT_RX_READY (1 << 1)
67 #define MWL8K_A2H_INT_TX_DONE (1 << 0)
68
69 #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
79
80 #define MWL8K_RX_QUEUES 1
81 #define MWL8K_TX_QUEUES 4
82
83 struct rxd_ops {
84 int rxd_size;
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
88 __le16 *qos);
89 };
90
91 struct mwl8k_device_info {
92 char *part_name;
93 char *helper_image;
94 char *fw_image;
95 struct rxd_ops *rxd_ops;
96 u16 modes;
97 };
98
99 struct mwl8k_rx_queue {
100 int rxd_count;
101
102 /* hw receives here */
103 int head;
104
105 /* refill descs here */
106 int tail;
107
108 void *rxd;
109 dma_addr_t rxd_dma;
110 struct {
111 struct sk_buff *skb;
112 DECLARE_PCI_UNMAP_ADDR(dma)
113 } *buf;
114 };
115
116 struct mwl8k_tx_queue {
117 /* hw transmits here */
118 int head;
119
120 /* sw appends here */
121 int tail;
122
123 struct ieee80211_tx_queue_stats stats;
124 struct mwl8k_tx_desc *txd;
125 dma_addr_t txd_dma;
126 struct sk_buff **skb;
127 };
128
129 /* Pointers to the firmware data and meta information about it. */
130 struct mwl8k_firmware {
131 /* Boot helper code */
132 struct firmware *helper;
133
134 /* Microcode */
135 struct firmware *ucode;
136 };
137
138 struct mwl8k_priv {
139 void __iomem *sram;
140 void __iomem *regs;
141 struct ieee80211_hw *hw;
142
143 struct pci_dev *pdev;
144
145 struct mwl8k_device_info *device_info;
146 bool ap_fw;
147 struct rxd_ops *rxd_ops;
148
149 /* firmware files and meta data */
150 struct mwl8k_firmware fw;
151
152 /* firmware access */
153 struct mutex fw_mutex;
154 struct task_struct *fw_mutex_owner;
155 int fw_mutex_depth;
156 struct completion *hostcmd_wait;
157
158 /* lock held over TX and TX reap */
159 spinlock_t tx_lock;
160
161 /* TX quiesce completion, protected by fw_mutex and tx_lock */
162 struct completion *tx_wait;
163
164 struct ieee80211_vif *vif;
165
166 struct ieee80211_channel *current_channel;
167
168 /* power management status cookie from firmware */
169 u32 *cookie;
170 dma_addr_t cookie_dma;
171
172 u16 num_mcaddrs;
173 u8 hw_rev;
174 u32 fw_rev;
175
176 /*
177 * Running count of TX packets in flight, to avoid
178 * iterating over the transmit rings each time.
179 */
180 int pending_tx_pkts;
181
182 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
183 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
184
185 /* PHY parameters */
186 struct ieee80211_supported_band band;
187 struct ieee80211_channel channels[14];
188 struct ieee80211_rate rates[14];
189
190 bool radio_on;
191 bool radio_short_preamble;
192 bool sniffer_enabled;
193 bool wmm_enabled;
194
195 /* XXX need to convert this to handle multiple interfaces */
196 bool capture_beacon;
197 u8 capture_bssid[ETH_ALEN];
198 struct sk_buff *beacon_skb;
199
200 /*
201 * This FJ worker has to be global as it is scheduled from the
202 * RX handler. At this point we don't know which interface it
203 * belongs to until the list of bssids waiting to complete join
204 * is checked.
205 */
206 struct work_struct finalize_join_worker;
207
208 /* Tasklet to reclaim TX descriptors and buffers after tx */
209 struct tasklet_struct tx_reclaim_task;
210 };
211
212 /* Per interface specific private data */
213 struct mwl8k_vif {
214 /* backpointer to parent config block */
215 struct mwl8k_priv *priv;
216
217 /* BSS config of AP or IBSS from mac80211*/
218 struct ieee80211_bss_conf bss_info;
219
220 /* BSSID of AP or IBSS */
221 u8 bssid[ETH_ALEN];
222 u8 mac_addr[ETH_ALEN];
223
224 /* Index into station database.Returned by update_sta_db call */
225 u8 peer_id;
226
227 /* Non AMPDU sequence number assigned by driver */
228 u16 seqno;
229 };
230
231 #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
232
233 static const struct ieee80211_channel mwl8k_channels[] = {
234 { .center_freq = 2412, .hw_value = 1, },
235 { .center_freq = 2417, .hw_value = 2, },
236 { .center_freq = 2422, .hw_value = 3, },
237 { .center_freq = 2427, .hw_value = 4, },
238 { .center_freq = 2432, .hw_value = 5, },
239 { .center_freq = 2437, .hw_value = 6, },
240 { .center_freq = 2442, .hw_value = 7, },
241 { .center_freq = 2447, .hw_value = 8, },
242 { .center_freq = 2452, .hw_value = 9, },
243 { .center_freq = 2457, .hw_value = 10, },
244 { .center_freq = 2462, .hw_value = 11, },
245 };
246
247 static const struct ieee80211_rate mwl8k_rates[] = {
248 { .bitrate = 10, .hw_value = 2, },
249 { .bitrate = 20, .hw_value = 4, },
250 { .bitrate = 55, .hw_value = 11, },
251 { .bitrate = 110, .hw_value = 22, },
252 { .bitrate = 220, .hw_value = 44, },
253 { .bitrate = 60, .hw_value = 12, },
254 { .bitrate = 90, .hw_value = 18, },
255 { .bitrate = 120, .hw_value = 24, },
256 { .bitrate = 180, .hw_value = 36, },
257 { .bitrate = 240, .hw_value = 48, },
258 { .bitrate = 360, .hw_value = 72, },
259 { .bitrate = 480, .hw_value = 96, },
260 { .bitrate = 540, .hw_value = 108, },
261 { .bitrate = 720, .hw_value = 144, },
262 };
263
264 static const u8 mwl8k_rateids[12] = {
265 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108,
266 };
267
268 /* Set or get info from Firmware */
269 #define MWL8K_CMD_SET 0x0001
270 #define MWL8K_CMD_GET 0x0000
271
272 /* Firmware command codes */
273 #define MWL8K_CMD_CODE_DNLD 0x0001
274 #define MWL8K_CMD_GET_HW_SPEC 0x0003
275 #define MWL8K_CMD_SET_HW_SPEC 0x0004
276 #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
277 #define MWL8K_CMD_GET_STAT 0x0014
278 #define MWL8K_CMD_RADIO_CONTROL 0x001c
279 #define MWL8K_CMD_RF_TX_POWER 0x001e
280 #define MWL8K_CMD_RF_ANTENNA 0x0020
281 #define MWL8K_CMD_SET_PRE_SCAN 0x0107
282 #define MWL8K_CMD_SET_POST_SCAN 0x0108
283 #define MWL8K_CMD_SET_RF_CHANNEL 0x010a
284 #define MWL8K_CMD_SET_AID 0x010d
285 #define MWL8K_CMD_SET_RATE 0x0110
286 #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
287 #define MWL8K_CMD_RTS_THRESHOLD 0x0113
288 #define MWL8K_CMD_SET_SLOT 0x0114
289 #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
290 #define MWL8K_CMD_SET_WMM_MODE 0x0123
291 #define MWL8K_CMD_MIMO_CONFIG 0x0125
292 #define MWL8K_CMD_USE_FIXED_RATE 0x0126
293 #define MWL8K_CMD_ENABLE_SNIFFER 0x0150
294 #define MWL8K_CMD_SET_MAC_ADDR 0x0202
295 #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
296 #define MWL8K_CMD_UPDATE_STADB 0x1123
297
298 static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
299 {
300 #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
301 snprintf(buf, bufsize, "%s", #x);\
302 return buf;\
303 } while (0)
304 switch (cmd & ~0x8000) {
305 MWL8K_CMDNAME(CODE_DNLD);
306 MWL8K_CMDNAME(GET_HW_SPEC);
307 MWL8K_CMDNAME(SET_HW_SPEC);
308 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
309 MWL8K_CMDNAME(GET_STAT);
310 MWL8K_CMDNAME(RADIO_CONTROL);
311 MWL8K_CMDNAME(RF_TX_POWER);
312 MWL8K_CMDNAME(RF_ANTENNA);
313 MWL8K_CMDNAME(SET_PRE_SCAN);
314 MWL8K_CMDNAME(SET_POST_SCAN);
315 MWL8K_CMDNAME(SET_RF_CHANNEL);
316 MWL8K_CMDNAME(SET_AID);
317 MWL8K_CMDNAME(SET_RATE);
318 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
319 MWL8K_CMDNAME(RTS_THRESHOLD);
320 MWL8K_CMDNAME(SET_SLOT);
321 MWL8K_CMDNAME(SET_EDCA_PARAMS);
322 MWL8K_CMDNAME(SET_WMM_MODE);
323 MWL8K_CMDNAME(MIMO_CONFIG);
324 MWL8K_CMDNAME(USE_FIXED_RATE);
325 MWL8K_CMDNAME(ENABLE_SNIFFER);
326 MWL8K_CMDNAME(SET_MAC_ADDR);
327 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
328 MWL8K_CMDNAME(UPDATE_STADB);
329 default:
330 snprintf(buf, bufsize, "0x%x", cmd);
331 }
332 #undef MWL8K_CMDNAME
333
334 return buf;
335 }
336
337 /* Hardware and firmware reset */
338 static void mwl8k_hw_reset(struct mwl8k_priv *priv)
339 {
340 iowrite32(MWL8K_H2A_INT_RESET,
341 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
342 iowrite32(MWL8K_H2A_INT_RESET,
343 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
344 msleep(20);
345 }
346
347 /* Release fw image */
348 static void mwl8k_release_fw(struct firmware **fw)
349 {
350 if (*fw == NULL)
351 return;
352 release_firmware(*fw);
353 *fw = NULL;
354 }
355
356 static void mwl8k_release_firmware(struct mwl8k_priv *priv)
357 {
358 mwl8k_release_fw(&priv->fw.ucode);
359 mwl8k_release_fw(&priv->fw.helper);
360 }
361
362 /* Request fw image */
363 static int mwl8k_request_fw(struct mwl8k_priv *priv,
364 const char *fname, struct firmware **fw)
365 {
366 /* release current image */
367 if (*fw != NULL)
368 mwl8k_release_fw(fw);
369
370 return request_firmware((const struct firmware **)fw,
371 fname, &priv->pdev->dev);
372 }
373
374 static int mwl8k_request_firmware(struct mwl8k_priv *priv)
375 {
376 struct mwl8k_device_info *di = priv->device_info;
377 int rc;
378
379 if (di->helper_image != NULL) {
380 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw.helper);
381 if (rc) {
382 printk(KERN_ERR "%s: Error requesting helper "
383 "firmware file %s\n", pci_name(priv->pdev),
384 di->helper_image);
385 return rc;
386 }
387 }
388
389 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw.ucode);
390 if (rc) {
391 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
392 pci_name(priv->pdev), di->fw_image);
393 mwl8k_release_fw(&priv->fw.helper);
394 return rc;
395 }
396
397 return 0;
398 }
399
400 MODULE_FIRMWARE("mwl8k/helper_8687.fw");
401 MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
402
403 struct mwl8k_cmd_pkt {
404 __le16 code;
405 __le16 length;
406 __le16 seq_num;
407 __le16 result;
408 char payload[0];
409 } __attribute__((packed));
410
411 /*
412 * Firmware loading.
413 */
414 static int
415 mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
416 {
417 void __iomem *regs = priv->regs;
418 dma_addr_t dma_addr;
419 int loops;
420
421 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
422 if (pci_dma_mapping_error(priv->pdev, dma_addr))
423 return -ENOMEM;
424
425 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
426 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
427 iowrite32(MWL8K_H2A_INT_DOORBELL,
428 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
429 iowrite32(MWL8K_H2A_INT_DUMMY,
430 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
431
432 loops = 1000;
433 do {
434 u32 int_code;
435
436 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
437 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
438 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
439 break;
440 }
441
442 cond_resched();
443 udelay(1);
444 } while (--loops);
445
446 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
447
448 return loops ? 0 : -ETIMEDOUT;
449 }
450
451 static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
452 const u8 *data, size_t length)
453 {
454 struct mwl8k_cmd_pkt *cmd;
455 int done;
456 int rc = 0;
457
458 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
459 if (cmd == NULL)
460 return -ENOMEM;
461
462 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
463 cmd->seq_num = 0;
464 cmd->result = 0;
465
466 done = 0;
467 while (length) {
468 int block_size = length > 256 ? 256 : length;
469
470 memcpy(cmd->payload, data + done, block_size);
471 cmd->length = cpu_to_le16(block_size);
472
473 rc = mwl8k_send_fw_load_cmd(priv, cmd,
474 sizeof(*cmd) + block_size);
475 if (rc)
476 break;
477
478 done += block_size;
479 length -= block_size;
480 }
481
482 if (!rc) {
483 cmd->length = 0;
484 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
485 }
486
487 kfree(cmd);
488
489 return rc;
490 }
491
492 static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
493 const u8 *data, size_t length)
494 {
495 unsigned char *buffer;
496 int may_continue, rc = 0;
497 u32 done, prev_block_size;
498
499 buffer = kmalloc(1024, GFP_KERNEL);
500 if (buffer == NULL)
501 return -ENOMEM;
502
503 done = 0;
504 prev_block_size = 0;
505 may_continue = 1000;
506 while (may_continue > 0) {
507 u32 block_size;
508
509 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
510 if (block_size & 1) {
511 block_size &= ~1;
512 may_continue--;
513 } else {
514 done += prev_block_size;
515 length -= prev_block_size;
516 }
517
518 if (block_size > 1024 || block_size > length) {
519 rc = -EOVERFLOW;
520 break;
521 }
522
523 if (length == 0) {
524 rc = 0;
525 break;
526 }
527
528 if (block_size == 0) {
529 rc = -EPROTO;
530 may_continue--;
531 udelay(1);
532 continue;
533 }
534
535 prev_block_size = block_size;
536 memcpy(buffer, data + done, block_size);
537
538 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
539 if (rc)
540 break;
541 }
542
543 if (!rc && length != 0)
544 rc = -EREMOTEIO;
545
546 kfree(buffer);
547
548 return rc;
549 }
550
551 static int mwl8k_load_firmware(struct ieee80211_hw *hw)
552 {
553 struct mwl8k_priv *priv = hw->priv;
554 struct firmware *fw = priv->fw.ucode;
555 struct mwl8k_device_info *di = priv->device_info;
556 int rc;
557 int loops;
558
559 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
560 struct firmware *helper = priv->fw.helper;
561
562 if (helper == NULL) {
563 printk(KERN_ERR "%s: helper image needed but none "
564 "given\n", pci_name(priv->pdev));
565 return -EINVAL;
566 }
567
568 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
569 if (rc) {
570 printk(KERN_ERR "%s: unable to load firmware "
571 "helper image\n", pci_name(priv->pdev));
572 return rc;
573 }
574 msleep(1);
575
576 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
577 } else {
578 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
579 }
580
581 if (rc) {
582 printk(KERN_ERR "%s: unable to load firmware image\n",
583 pci_name(priv->pdev));
584 return rc;
585 }
586
587 if (di->modes & BIT(NL80211_IFTYPE_AP))
588 iowrite32(MWL8K_MODE_AP, priv->regs + MWL8K_HIU_GEN_PTR);
589 else
590 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
591 msleep(1);
592
593 loops = 200000;
594 do {
595 u32 ready_code;
596
597 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
598 if (ready_code == MWL8K_FWAP_READY) {
599 priv->ap_fw = 1;
600 break;
601 } else if (ready_code == MWL8K_FWSTA_READY) {
602 priv->ap_fw = 0;
603 break;
604 }
605
606 cond_resched();
607 udelay(1);
608 } while (--loops);
609
610 return loops ? 0 : -ETIMEDOUT;
611 }
612
613
614 /*
615 * Defines shared between transmission and reception.
616 */
617 /* HT control fields for firmware */
618 struct ewc_ht_info {
619 __le16 control1;
620 __le16 control2;
621 __le16 control3;
622 } __attribute__((packed));
623
624 /* Firmware Station database operations */
625 #define MWL8K_STA_DB_ADD_ENTRY 0
626 #define MWL8K_STA_DB_MODIFY_ENTRY 1
627 #define MWL8K_STA_DB_DEL_ENTRY 2
628 #define MWL8K_STA_DB_FLUSH 3
629
630 /* Peer Entry flags - used to define the type of the peer node */
631 #define MWL8K_PEER_TYPE_ACCESSPOINT 2
632
633 struct peer_capability_info {
634 /* Peer type - AP vs. STA. */
635 __u8 peer_type;
636
637 /* Basic 802.11 capabilities from assoc resp. */
638 __le16 basic_caps;
639
640 /* Set if peer supports 802.11n high throughput (HT). */
641 __u8 ht_support;
642
643 /* Valid if HT is supported. */
644 __le16 ht_caps;
645 __u8 extended_ht_caps;
646 struct ewc_ht_info ewc_info;
647
648 /* Legacy rate table. Intersection of our rates and peer rates. */
649 __u8 legacy_rates[12];
650
651 /* HT rate table. Intersection of our rates and peer rates. */
652 __u8 ht_rates[16];
653 __u8 pad[16];
654
655 /* If set, interoperability mode, no proprietary extensions. */
656 __u8 interop;
657 __u8 pad2;
658 __u8 station_id;
659 __le16 amsdu_enabled;
660 } __attribute__((packed));
661
662 /* Inline functions to manipulate QoS field in data descriptor. */
663 static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
664 {
665 u16 val_mask = 1 << 4;
666
667 /* End of Service Period Bit 4 */
668 return qos | val_mask;
669 }
670
671 static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
672 {
673 u16 val_mask = 0x3;
674 u8 shift = 5;
675 u16 qos_mask = ~(val_mask << shift);
676
677 /* Ack Policy Bit 5-6 */
678 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
679 }
680
681 static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
682 {
683 u16 val_mask = 1 << 7;
684
685 /* AMSDU present Bit 7 */
686 return qos | val_mask;
687 }
688
689 static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
690 {
691 u16 val_mask = 0xff;
692 u8 shift = 8;
693 u16 qos_mask = ~(val_mask << shift);
694
695 /* Queue Length Bits 8-15 */
696 return (qos & qos_mask) | ((len & val_mask) << shift);
697 }
698
699 /* DMA header used by firmware and hardware. */
700 struct mwl8k_dma_data {
701 __le16 fwlen;
702 struct ieee80211_hdr wh;
703 char data[0];
704 } __attribute__((packed));
705
706 /* Routines to add/remove DMA header from skb. */
707 static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
708 {
709 struct mwl8k_dma_data *tr;
710 int hdrlen;
711
712 tr = (struct mwl8k_dma_data *)skb->data;
713 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
714
715 if (hdrlen != sizeof(tr->wh)) {
716 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
717 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
718 *((__le16 *)(tr->data - 2)) = qos;
719 } else {
720 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
721 }
722 }
723
724 if (hdrlen != sizeof(*tr))
725 skb_pull(skb, sizeof(*tr) - hdrlen);
726 }
727
728 static inline void mwl8k_add_dma_header(struct sk_buff *skb)
729 {
730 struct ieee80211_hdr *wh;
731 int hdrlen;
732 struct mwl8k_dma_data *tr;
733
734 /*
735 * Add a firmware DMA header; the firmware requires that we
736 * present a 2-byte payload length followed by a 4-address
737 * header (without QoS field), followed (optionally) by any
738 * WEP/ExtIV header (but only filled in for CCMP).
739 */
740 wh = (struct ieee80211_hdr *)skb->data;
741
742 hdrlen = ieee80211_hdrlen(wh->frame_control);
743 if (hdrlen != sizeof(*tr))
744 skb_push(skb, sizeof(*tr) - hdrlen);
745
746 if (ieee80211_is_data_qos(wh->frame_control))
747 hdrlen -= 2;
748
749 tr = (struct mwl8k_dma_data *)skb->data;
750 if (wh != &tr->wh)
751 memmove(&tr->wh, wh, hdrlen);
752 if (hdrlen != sizeof(tr->wh))
753 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
754
755 /*
756 * Firmware length is the length of the fully formed "802.11
757 * payload". That is, everything except for the 802.11 header.
758 * This includes all crypto material including the MIC.
759 */
760 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr));
761 }
762
763
764 /*
765 * Packet reception for 88w8366.
766 */
767 struct mwl8k_rxd_8366 {
768 __le16 pkt_len;
769 __u8 sq2;
770 __u8 rate;
771 __le32 pkt_phys_addr;
772 __le32 next_rxd_phys_addr;
773 __le16 qos_control;
774 __le16 htsig2;
775 __le32 hw_rssi_info;
776 __le32 hw_noise_floor_info;
777 __u8 noise_floor;
778 __u8 pad0[3];
779 __u8 rssi;
780 __u8 rx_status;
781 __u8 channel;
782 __u8 rx_ctrl;
783 } __attribute__((packed));
784
785 #define MWL8K_8366_RATE_INFO_MCS_FORMAT 0x80
786 #define MWL8K_8366_RATE_INFO_40MHZ 0x40
787 #define MWL8K_8366_RATE_INFO_RATEID(x) ((x) & 0x3f)
788
789 #define MWL8K_8366_RX_CTRL_OWNED_BY_HOST 0x80
790
791 static void mwl8k_rxd_8366_init(void *_rxd, dma_addr_t next_dma_addr)
792 {
793 struct mwl8k_rxd_8366 *rxd = _rxd;
794
795 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
796 rxd->rx_ctrl = MWL8K_8366_RX_CTRL_OWNED_BY_HOST;
797 }
798
799 static void mwl8k_rxd_8366_refill(void *_rxd, dma_addr_t addr, int len)
800 {
801 struct mwl8k_rxd_8366 *rxd = _rxd;
802
803 rxd->pkt_len = cpu_to_le16(len);
804 rxd->pkt_phys_addr = cpu_to_le32(addr);
805 wmb();
806 rxd->rx_ctrl = 0;
807 }
808
809 static int
810 mwl8k_rxd_8366_process(void *_rxd, struct ieee80211_rx_status *status,
811 __le16 *qos)
812 {
813 struct mwl8k_rxd_8366 *rxd = _rxd;
814
815 if (!(rxd->rx_ctrl & MWL8K_8366_RX_CTRL_OWNED_BY_HOST))
816 return -1;
817 rmb();
818
819 memset(status, 0, sizeof(*status));
820
821 status->signal = -rxd->rssi;
822 status->noise = -rxd->noise_floor;
823
824 if (rxd->rate & MWL8K_8366_RATE_INFO_MCS_FORMAT) {
825 status->flag |= RX_FLAG_HT;
826 if (rxd->rate & MWL8K_8366_RATE_INFO_40MHZ)
827 status->flag |= RX_FLAG_40MHZ;
828 status->rate_idx = MWL8K_8366_RATE_INFO_RATEID(rxd->rate);
829 } else {
830 int i;
831
832 for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) {
833 if (mwl8k_rates[i].hw_value == rxd->rate) {
834 status->rate_idx = i;
835 break;
836 }
837 }
838 }
839
840 status->band = IEEE80211_BAND_2GHZ;
841 status->freq = ieee80211_channel_to_frequency(rxd->channel);
842
843 *qos = rxd->qos_control;
844
845 return le16_to_cpu(rxd->pkt_len);
846 }
847
848 static struct rxd_ops rxd_8366_ops = {
849 .rxd_size = sizeof(struct mwl8k_rxd_8366),
850 .rxd_init = mwl8k_rxd_8366_init,
851 .rxd_refill = mwl8k_rxd_8366_refill,
852 .rxd_process = mwl8k_rxd_8366_process,
853 };
854
855 /*
856 * Packet reception for 88w8687.
857 */
858 struct mwl8k_rxd_8687 {
859 __le16 pkt_len;
860 __u8 link_quality;
861 __u8 noise_level;
862 __le32 pkt_phys_addr;
863 __le32 next_rxd_phys_addr;
864 __le16 qos_control;
865 __le16 rate_info;
866 __le32 pad0[4];
867 __u8 rssi;
868 __u8 channel;
869 __le16 pad1;
870 __u8 rx_ctrl;
871 __u8 rx_status;
872 __u8 pad2[2];
873 } __attribute__((packed));
874
875 #define MWL8K_8687_RATE_INFO_SHORTPRE 0x8000
876 #define MWL8K_8687_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
877 #define MWL8K_8687_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
878 #define MWL8K_8687_RATE_INFO_40MHZ 0x0004
879 #define MWL8K_8687_RATE_INFO_SHORTGI 0x0002
880 #define MWL8K_8687_RATE_INFO_MCS_FORMAT 0x0001
881
882 #define MWL8K_8687_RX_CTRL_OWNED_BY_HOST 0x02
883
884 static void mwl8k_rxd_8687_init(void *_rxd, dma_addr_t next_dma_addr)
885 {
886 struct mwl8k_rxd_8687 *rxd = _rxd;
887
888 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
889 rxd->rx_ctrl = MWL8K_8687_RX_CTRL_OWNED_BY_HOST;
890 }
891
892 static void mwl8k_rxd_8687_refill(void *_rxd, dma_addr_t addr, int len)
893 {
894 struct mwl8k_rxd_8687 *rxd = _rxd;
895
896 rxd->pkt_len = cpu_to_le16(len);
897 rxd->pkt_phys_addr = cpu_to_le32(addr);
898 wmb();
899 rxd->rx_ctrl = 0;
900 }
901
902 static int
903 mwl8k_rxd_8687_process(void *_rxd, struct ieee80211_rx_status *status,
904 __le16 *qos)
905 {
906 struct mwl8k_rxd_8687 *rxd = _rxd;
907 u16 rate_info;
908
909 if (!(rxd->rx_ctrl & MWL8K_8687_RX_CTRL_OWNED_BY_HOST))
910 return -1;
911 rmb();
912
913 rate_info = le16_to_cpu(rxd->rate_info);
914
915 memset(status, 0, sizeof(*status));
916
917 status->signal = -rxd->rssi;
918 status->noise = -rxd->noise_level;
919 status->qual = rxd->link_quality;
920 status->antenna = MWL8K_8687_RATE_INFO_ANTSELECT(rate_info);
921 status->rate_idx = MWL8K_8687_RATE_INFO_RATEID(rate_info);
922
923 if (rate_info & MWL8K_8687_RATE_INFO_SHORTPRE)
924 status->flag |= RX_FLAG_SHORTPRE;
925 if (rate_info & MWL8K_8687_RATE_INFO_40MHZ)
926 status->flag |= RX_FLAG_40MHZ;
927 if (rate_info & MWL8K_8687_RATE_INFO_SHORTGI)
928 status->flag |= RX_FLAG_SHORT_GI;
929 if (rate_info & MWL8K_8687_RATE_INFO_MCS_FORMAT)
930 status->flag |= RX_FLAG_HT;
931
932 status->band = IEEE80211_BAND_2GHZ;
933 status->freq = ieee80211_channel_to_frequency(rxd->channel);
934
935 *qos = rxd->qos_control;
936
937 return le16_to_cpu(rxd->pkt_len);
938 }
939
940 static struct rxd_ops rxd_8687_ops = {
941 .rxd_size = sizeof(struct mwl8k_rxd_8687),
942 .rxd_init = mwl8k_rxd_8687_init,
943 .rxd_refill = mwl8k_rxd_8687_refill,
944 .rxd_process = mwl8k_rxd_8687_process,
945 };
946
947
948 #define MWL8K_RX_DESCS 256
949 #define MWL8K_RX_MAXSZ 3800
950
951 static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
952 {
953 struct mwl8k_priv *priv = hw->priv;
954 struct mwl8k_rx_queue *rxq = priv->rxq + index;
955 int size;
956 int i;
957
958 rxq->rxd_count = 0;
959 rxq->head = 0;
960 rxq->tail = 0;
961
962 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
963
964 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
965 if (rxq->rxd == NULL) {
966 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
967 wiphy_name(hw->wiphy));
968 return -ENOMEM;
969 }
970 memset(rxq->rxd, 0, size);
971
972 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
973 if (rxq->buf == NULL) {
974 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
975 wiphy_name(hw->wiphy));
976 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
977 return -ENOMEM;
978 }
979 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
980
981 for (i = 0; i < MWL8K_RX_DESCS; i++) {
982 int desc_size;
983 void *rxd;
984 int nexti;
985 dma_addr_t next_dma_addr;
986
987 desc_size = priv->rxd_ops->rxd_size;
988 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
989
990 nexti = i + 1;
991 if (nexti == MWL8K_RX_DESCS)
992 nexti = 0;
993 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
994
995 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
996 }
997
998 return 0;
999 }
1000
1001 static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
1002 {
1003 struct mwl8k_priv *priv = hw->priv;
1004 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1005 int refilled;
1006
1007 refilled = 0;
1008 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
1009 struct sk_buff *skb;
1010 dma_addr_t addr;
1011 int rx;
1012 void *rxd;
1013
1014 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
1015 if (skb == NULL)
1016 break;
1017
1018 addr = pci_map_single(priv->pdev, skb->data,
1019 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
1020
1021 rxq->rxd_count++;
1022 rx = rxq->tail++;
1023 if (rxq->tail == MWL8K_RX_DESCS)
1024 rxq->tail = 0;
1025 rxq->buf[rx].skb = skb;
1026 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
1027
1028 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
1029 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
1030
1031 refilled++;
1032 }
1033
1034 return refilled;
1035 }
1036
1037 /* Must be called only when the card's reception is completely halted */
1038 static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
1039 {
1040 struct mwl8k_priv *priv = hw->priv;
1041 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1042 int i;
1043
1044 for (i = 0; i < MWL8K_RX_DESCS; i++) {
1045 if (rxq->buf[i].skb != NULL) {
1046 pci_unmap_single(priv->pdev,
1047 pci_unmap_addr(&rxq->buf[i], dma),
1048 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1049 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
1050
1051 kfree_skb(rxq->buf[i].skb);
1052 rxq->buf[i].skb = NULL;
1053 }
1054 }
1055
1056 kfree(rxq->buf);
1057 rxq->buf = NULL;
1058
1059 pci_free_consistent(priv->pdev,
1060 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
1061 rxq->rxd, rxq->rxd_dma);
1062 rxq->rxd = NULL;
1063 }
1064
1065
1066 /*
1067 * Scan a list of BSSIDs to process for finalize join.
1068 * Allows for extension to process multiple BSSIDs.
1069 */
1070 static inline int
1071 mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
1072 {
1073 return priv->capture_beacon &&
1074 ieee80211_is_beacon(wh->frame_control) &&
1075 !compare_ether_addr(wh->addr3, priv->capture_bssid);
1076 }
1077
1078 static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
1079 struct sk_buff *skb)
1080 {
1081 struct mwl8k_priv *priv = hw->priv;
1082
1083 priv->capture_beacon = false;
1084 memset(priv->capture_bssid, 0, ETH_ALEN);
1085
1086 /*
1087 * Use GFP_ATOMIC as rxq_process is called from
1088 * the primary interrupt handler, memory allocation call
1089 * must not sleep.
1090 */
1091 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
1092 if (priv->beacon_skb != NULL)
1093 ieee80211_queue_work(hw, &priv->finalize_join_worker);
1094 }
1095
1096 static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1097 {
1098 struct mwl8k_priv *priv = hw->priv;
1099 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1100 int processed;
1101
1102 processed = 0;
1103 while (rxq->rxd_count && limit--) {
1104 struct sk_buff *skb;
1105 void *rxd;
1106 int pkt_len;
1107 struct ieee80211_rx_status status;
1108 __le16 qos;
1109
1110 skb = rxq->buf[rxq->head].skb;
1111 if (skb == NULL)
1112 break;
1113
1114 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1115
1116 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos);
1117 if (pkt_len < 0)
1118 break;
1119
1120 rxq->buf[rxq->head].skb = NULL;
1121
1122 pci_unmap_single(priv->pdev,
1123 pci_unmap_addr(&rxq->buf[rxq->head], dma),
1124 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1125 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
1126
1127 rxq->head++;
1128 if (rxq->head == MWL8K_RX_DESCS)
1129 rxq->head = 0;
1130
1131 rxq->rxd_count--;
1132
1133 skb_put(skb, pkt_len);
1134 mwl8k_remove_dma_header(skb, qos);
1135
1136 /*
1137 * Check for a pending join operation. Save a
1138 * copy of the beacon and schedule a tasklet to
1139 * send a FINALIZE_JOIN command to the firmware.
1140 */
1141 if (mwl8k_capture_bssid(priv, (void *)skb->data))
1142 mwl8k_save_beacon(hw, skb);
1143
1144 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1145 ieee80211_rx_irqsafe(hw, skb);
1146
1147 processed++;
1148 }
1149
1150 return processed;
1151 }
1152
1153
1154 /*
1155 * Packet transmission.
1156 */
1157
1158 /* Transmit packet ACK policy */
1159 #define MWL8K_TXD_ACK_POLICY_NORMAL 0
1160 #define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
1161
1162 #define MWL8K_TXD_STATUS_OK 0x00000001
1163 #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1164 #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1165 #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
1166 #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
1167
1168 struct mwl8k_tx_desc {
1169 __le32 status;
1170 __u8 data_rate;
1171 __u8 tx_priority;
1172 __le16 qos_control;
1173 __le32 pkt_phys_addr;
1174 __le16 pkt_len;
1175 __u8 dest_MAC_addr[ETH_ALEN];
1176 __le32 next_txd_phys_addr;
1177 __le32 reserved;
1178 __le16 rate_info;
1179 __u8 peer_id;
1180 __u8 tx_frag_cnt;
1181 } __attribute__((packed));
1182
1183 #define MWL8K_TX_DESCS 128
1184
1185 static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1186 {
1187 struct mwl8k_priv *priv = hw->priv;
1188 struct mwl8k_tx_queue *txq = priv->txq + index;
1189 int size;
1190 int i;
1191
1192 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1193 txq->stats.limit = MWL8K_TX_DESCS;
1194 txq->head = 0;
1195 txq->tail = 0;
1196
1197 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1198
1199 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1200 if (txq->txd == NULL) {
1201 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
1202 wiphy_name(hw->wiphy));
1203 return -ENOMEM;
1204 }
1205 memset(txq->txd, 0, size);
1206
1207 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1208 if (txq->skb == NULL) {
1209 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
1210 wiphy_name(hw->wiphy));
1211 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
1212 return -ENOMEM;
1213 }
1214 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
1215
1216 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1217 struct mwl8k_tx_desc *tx_desc;
1218 int nexti;
1219
1220 tx_desc = txq->txd + i;
1221 nexti = (i + 1) % MWL8K_TX_DESCS;
1222
1223 tx_desc->status = 0;
1224 tx_desc->next_txd_phys_addr =
1225 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
1226 }
1227
1228 return 0;
1229 }
1230
1231 static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1232 {
1233 iowrite32(MWL8K_H2A_INT_PPA_READY,
1234 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1235 iowrite32(MWL8K_H2A_INT_DUMMY,
1236 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1237 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1238 }
1239
1240 struct mwl8k_txq_info {
1241 u32 fw_owned;
1242 u32 drv_owned;
1243 u32 unused;
1244 u32 len;
1245 u32 head;
1246 u32 tail;
1247 };
1248
1249 static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
1250 struct mwl8k_txq_info *txinfo)
1251 {
1252 int count, desc, status;
1253 struct mwl8k_tx_queue *txq;
1254 struct mwl8k_tx_desc *tx_desc;
1255 int ndescs = 0;
1256
1257 memset(txinfo, 0, MWL8K_TX_QUEUES * sizeof(struct mwl8k_txq_info));
1258
1259 for (count = 0; count < MWL8K_TX_QUEUES; count++) {
1260 txq = priv->txq + count;
1261 txinfo[count].len = txq->stats.len;
1262 txinfo[count].head = txq->head;
1263 txinfo[count].tail = txq->tail;
1264 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1265 tx_desc = txq->txd + desc;
1266 status = le32_to_cpu(tx_desc->status);
1267
1268 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1269 txinfo[count].fw_owned++;
1270 else
1271 txinfo[count].drv_owned++;
1272
1273 if (tx_desc->pkt_len == 0)
1274 txinfo[count].unused++;
1275 }
1276 }
1277
1278 return ndescs;
1279 }
1280
1281 /*
1282 * Must be called with priv->fw_mutex held and tx queues stopped.
1283 */
1284 static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
1285 {
1286 struct mwl8k_priv *priv = hw->priv;
1287 DECLARE_COMPLETION_ONSTACK(tx_wait);
1288 u32 count;
1289 unsigned long timeout;
1290
1291 might_sleep();
1292
1293 spin_lock_bh(&priv->tx_lock);
1294 count = priv->pending_tx_pkts;
1295 if (count)
1296 priv->tx_wait = &tx_wait;
1297 spin_unlock_bh(&priv->tx_lock);
1298
1299 if (count) {
1300 struct mwl8k_txq_info txinfo[MWL8K_TX_QUEUES];
1301 int index;
1302 int newcount;
1303
1304 timeout = wait_for_completion_timeout(&tx_wait,
1305 msecs_to_jiffies(5000));
1306 if (timeout)
1307 return 0;
1308
1309 spin_lock_bh(&priv->tx_lock);
1310 priv->tx_wait = NULL;
1311 newcount = priv->pending_tx_pkts;
1312 mwl8k_scan_tx_ring(priv, txinfo);
1313 spin_unlock_bh(&priv->tx_lock);
1314
1315 printk(KERN_ERR "%s(%u) TIMEDOUT:5000ms Pend:%u-->%u\n",
1316 __func__, __LINE__, count, newcount);
1317
1318 for (index = 0; index < MWL8K_TX_QUEUES; index++)
1319 printk(KERN_ERR "TXQ:%u L:%u H:%u T:%u FW:%u "
1320 "DRV:%u U:%u\n",
1321 index,
1322 txinfo[index].len,
1323 txinfo[index].head,
1324 txinfo[index].tail,
1325 txinfo[index].fw_owned,
1326 txinfo[index].drv_owned,
1327 txinfo[index].unused);
1328
1329 return -ETIMEDOUT;
1330 }
1331
1332 return 0;
1333 }
1334
1335 #define MWL8K_TXD_SUCCESS(status) \
1336 ((status) & (MWL8K_TXD_STATUS_OK | \
1337 MWL8K_TXD_STATUS_OK_RETRY | \
1338 MWL8K_TXD_STATUS_OK_MORE_RETRY))
1339
1340 static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1341 {
1342 struct mwl8k_priv *priv = hw->priv;
1343 struct mwl8k_tx_queue *txq = priv->txq + index;
1344 int wake = 0;
1345
1346 while (txq->stats.len > 0) {
1347 int tx;
1348 struct mwl8k_tx_desc *tx_desc;
1349 unsigned long addr;
1350 int size;
1351 struct sk_buff *skb;
1352 struct ieee80211_tx_info *info;
1353 u32 status;
1354
1355 tx = txq->head;
1356 tx_desc = txq->txd + tx;
1357
1358 status = le32_to_cpu(tx_desc->status);
1359
1360 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1361 if (!force)
1362 break;
1363 tx_desc->status &=
1364 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1365 }
1366
1367 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1368 BUG_ON(txq->stats.len == 0);
1369 txq->stats.len--;
1370 priv->pending_tx_pkts--;
1371
1372 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
1373 size = le16_to_cpu(tx_desc->pkt_len);
1374 skb = txq->skb[tx];
1375 txq->skb[tx] = NULL;
1376
1377 BUG_ON(skb == NULL);
1378 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1379
1380 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
1381
1382 /* Mark descriptor as unused */
1383 tx_desc->pkt_phys_addr = 0;
1384 tx_desc->pkt_len = 0;
1385
1386 info = IEEE80211_SKB_CB(skb);
1387 ieee80211_tx_info_clear_status(info);
1388 if (MWL8K_TXD_SUCCESS(status))
1389 info->flags |= IEEE80211_TX_STAT_ACK;
1390
1391 ieee80211_tx_status_irqsafe(hw, skb);
1392
1393 wake = 1;
1394 }
1395
1396 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
1397 ieee80211_wake_queue(hw, index);
1398 }
1399
1400 /* must be called only when the card's transmit is completely halted */
1401 static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1402 {
1403 struct mwl8k_priv *priv = hw->priv;
1404 struct mwl8k_tx_queue *txq = priv->txq + index;
1405
1406 mwl8k_txq_reclaim(hw, index, 1);
1407
1408 kfree(txq->skb);
1409 txq->skb = NULL;
1410
1411 pci_free_consistent(priv->pdev,
1412 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1413 txq->txd, txq->txd_dma);
1414 txq->txd = NULL;
1415 }
1416
1417 static int
1418 mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1419 {
1420 struct mwl8k_priv *priv = hw->priv;
1421 struct ieee80211_tx_info *tx_info;
1422 struct mwl8k_vif *mwl8k_vif;
1423 struct ieee80211_hdr *wh;
1424 struct mwl8k_tx_queue *txq;
1425 struct mwl8k_tx_desc *tx;
1426 dma_addr_t dma;
1427 u32 txstatus;
1428 u8 txdatarate;
1429 u16 qos;
1430
1431 wh = (struct ieee80211_hdr *)skb->data;
1432 if (ieee80211_is_data_qos(wh->frame_control))
1433 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1434 else
1435 qos = 0;
1436
1437 mwl8k_add_dma_header(skb);
1438 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
1439
1440 tx_info = IEEE80211_SKB_CB(skb);
1441 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
1442
1443 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1444 u16 seqno = mwl8k_vif->seqno;
1445
1446 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1447 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1448 mwl8k_vif->seqno = seqno++ % 4096;
1449 }
1450
1451 /* Setup firmware control bit fields for each frame type. */
1452 txstatus = 0;
1453 txdatarate = 0;
1454 if (ieee80211_is_mgmt(wh->frame_control) ||
1455 ieee80211_is_ctl(wh->frame_control)) {
1456 txdatarate = 0;
1457 qos = mwl8k_qos_setbit_eosp(qos);
1458 /* Set Queue size to unspecified */
1459 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1460 } else if (ieee80211_is_data(wh->frame_control)) {
1461 txdatarate = 1;
1462 if (is_multicast_ether_addr(wh->addr1))
1463 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1464
1465 /* Send pkt in an aggregate if AMPDU frame. */
1466 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1467 qos = mwl8k_qos_setbit_ack(qos,
1468 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1469 else
1470 qos = mwl8k_qos_setbit_ack(qos,
1471 MWL8K_TXD_ACK_POLICY_NORMAL);
1472
1473 if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
1474 qos = mwl8k_qos_setbit_amsdu(qos);
1475 }
1476
1477 dma = pci_map_single(priv->pdev, skb->data,
1478 skb->len, PCI_DMA_TODEVICE);
1479
1480 if (pci_dma_mapping_error(priv->pdev, dma)) {
1481 printk(KERN_DEBUG "%s: failed to dma map skb, "
1482 "dropping TX frame.\n", wiphy_name(hw->wiphy));
1483 dev_kfree_skb(skb);
1484 return NETDEV_TX_OK;
1485 }
1486
1487 spin_lock_bh(&priv->tx_lock);
1488
1489 txq = priv->txq + index;
1490
1491 BUG_ON(txq->skb[txq->tail] != NULL);
1492 txq->skb[txq->tail] = skb;
1493
1494 tx = txq->txd + txq->tail;
1495 tx->data_rate = txdatarate;
1496 tx->tx_priority = index;
1497 tx->qos_control = cpu_to_le16(qos);
1498 tx->pkt_phys_addr = cpu_to_le32(dma);
1499 tx->pkt_len = cpu_to_le16(skb->len);
1500 tx->rate_info = 0;
1501 tx->peer_id = mwl8k_vif->peer_id;
1502 wmb();
1503 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1504
1505 txq->stats.count++;
1506 txq->stats.len++;
1507 priv->pending_tx_pkts++;
1508
1509 txq->tail++;
1510 if (txq->tail == MWL8K_TX_DESCS)
1511 txq->tail = 0;
1512
1513 if (txq->head == txq->tail)
1514 ieee80211_stop_queue(hw, index);
1515
1516 mwl8k_tx_start(priv);
1517
1518 spin_unlock_bh(&priv->tx_lock);
1519
1520 return NETDEV_TX_OK;
1521 }
1522
1523
1524 /*
1525 * Firmware access.
1526 *
1527 * We have the following requirements for issuing firmware commands:
1528 * - Some commands require that the packet transmit path is idle when
1529 * the command is issued. (For simplicity, we'll just quiesce the
1530 * transmit path for every command.)
1531 * - There are certain sequences of commands that need to be issued to
1532 * the hardware sequentially, with no other intervening commands.
1533 *
1534 * This leads to an implementation of a "firmware lock" as a mutex that
1535 * can be taken recursively, and which is taken by both the low-level
1536 * command submission function (mwl8k_post_cmd) as well as any users of
1537 * that function that require issuing of an atomic sequence of commands,
1538 * and quiesces the transmit path whenever it's taken.
1539 */
1540 static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1541 {
1542 struct mwl8k_priv *priv = hw->priv;
1543
1544 if (priv->fw_mutex_owner != current) {
1545 int rc;
1546
1547 mutex_lock(&priv->fw_mutex);
1548 ieee80211_stop_queues(hw);
1549
1550 rc = mwl8k_tx_wait_empty(hw);
1551 if (rc) {
1552 ieee80211_wake_queues(hw);
1553 mutex_unlock(&priv->fw_mutex);
1554
1555 return rc;
1556 }
1557
1558 priv->fw_mutex_owner = current;
1559 }
1560
1561 priv->fw_mutex_depth++;
1562
1563 return 0;
1564 }
1565
1566 static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1567 {
1568 struct mwl8k_priv *priv = hw->priv;
1569
1570 if (!--priv->fw_mutex_depth) {
1571 ieee80211_wake_queues(hw);
1572 priv->fw_mutex_owner = NULL;
1573 mutex_unlock(&priv->fw_mutex);
1574 }
1575 }
1576
1577
1578 /*
1579 * Command processing.
1580 */
1581
1582 /* Timeout firmware commands after 10s */
1583 #define MWL8K_CMD_TIMEOUT_MS 10000
1584
1585 static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1586 {
1587 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1588 struct mwl8k_priv *priv = hw->priv;
1589 void __iomem *regs = priv->regs;
1590 dma_addr_t dma_addr;
1591 unsigned int dma_size;
1592 int rc;
1593 unsigned long timeout = 0;
1594 u8 buf[32];
1595
1596 cmd->result = 0xffff;
1597 dma_size = le16_to_cpu(cmd->length);
1598 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1599 PCI_DMA_BIDIRECTIONAL);
1600 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1601 return -ENOMEM;
1602
1603 rc = mwl8k_fw_lock(hw);
1604 if (rc) {
1605 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1606 PCI_DMA_BIDIRECTIONAL);
1607 return rc;
1608 }
1609
1610 priv->hostcmd_wait = &cmd_wait;
1611 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1612 iowrite32(MWL8K_H2A_INT_DOORBELL,
1613 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1614 iowrite32(MWL8K_H2A_INT_DUMMY,
1615 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1616
1617 timeout = wait_for_completion_timeout(&cmd_wait,
1618 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1619
1620 priv->hostcmd_wait = NULL;
1621
1622 mwl8k_fw_unlock(hw);
1623
1624 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1625 PCI_DMA_BIDIRECTIONAL);
1626
1627 if (!timeout) {
1628 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
1629 wiphy_name(hw->wiphy),
1630 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1631 MWL8K_CMD_TIMEOUT_MS);
1632 rc = -ETIMEDOUT;
1633 } else {
1634 int ms;
1635
1636 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
1637
1638 rc = cmd->result ? -EINVAL : 0;
1639 if (rc)
1640 printk(KERN_ERR "%s: Command %s error 0x%x\n",
1641 wiphy_name(hw->wiphy),
1642 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1643 le16_to_cpu(cmd->result));
1644 else if (ms > 2000)
1645 printk(KERN_NOTICE "%s: Command %s took %d ms\n",
1646 wiphy_name(hw->wiphy),
1647 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1648 ms);
1649 }
1650
1651 return rc;
1652 }
1653
1654 /*
1655 * CMD_GET_HW_SPEC (STA version).
1656 */
1657 struct mwl8k_cmd_get_hw_spec_sta {
1658 struct mwl8k_cmd_pkt header;
1659 __u8 hw_rev;
1660 __u8 host_interface;
1661 __le16 num_mcaddrs;
1662 __u8 perm_addr[ETH_ALEN];
1663 __le16 region_code;
1664 __le32 fw_rev;
1665 __le32 ps_cookie;
1666 __le32 caps;
1667 __u8 mcs_bitmap[16];
1668 __le32 rx_queue_ptr;
1669 __le32 num_tx_queues;
1670 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1671 __le32 caps2;
1672 __le32 num_tx_desc_per_queue;
1673 __le32 total_rxd;
1674 } __attribute__((packed));
1675
1676 static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
1677 {
1678 struct mwl8k_priv *priv = hw->priv;
1679 struct mwl8k_cmd_get_hw_spec_sta *cmd;
1680 int rc;
1681 int i;
1682
1683 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1684 if (cmd == NULL)
1685 return -ENOMEM;
1686
1687 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1688 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1689
1690 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1691 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1692 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1693 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1694 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1695 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1696 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1697 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1698
1699 rc = mwl8k_post_cmd(hw, &cmd->header);
1700
1701 if (!rc) {
1702 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1703 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1704 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1705 priv->hw_rev = cmd->hw_rev;
1706 }
1707
1708 kfree(cmd);
1709 return rc;
1710 }
1711
1712 /*
1713 * CMD_GET_HW_SPEC (AP version).
1714 */
1715 struct mwl8k_cmd_get_hw_spec_ap {
1716 struct mwl8k_cmd_pkt header;
1717 __u8 hw_rev;
1718 __u8 host_interface;
1719 __le16 num_wcb;
1720 __le16 num_mcaddrs;
1721 __u8 perm_addr[ETH_ALEN];
1722 __le16 region_code;
1723 __le16 num_antenna;
1724 __le32 fw_rev;
1725 __le32 wcbbase0;
1726 __le32 rxwrptr;
1727 __le32 rxrdptr;
1728 __le32 ps_cookie;
1729 __le32 wcbbase1;
1730 __le32 wcbbase2;
1731 __le32 wcbbase3;
1732 } __attribute__((packed));
1733
1734 static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
1735 {
1736 struct mwl8k_priv *priv = hw->priv;
1737 struct mwl8k_cmd_get_hw_spec_ap *cmd;
1738 int rc;
1739
1740 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1741 if (cmd == NULL)
1742 return -ENOMEM;
1743
1744 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1745 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1746
1747 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1748 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1749
1750 rc = mwl8k_post_cmd(hw, &cmd->header);
1751
1752 if (!rc) {
1753 int off;
1754
1755 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1756 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1757 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1758 priv->hw_rev = cmd->hw_rev;
1759
1760 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
1761 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
1762
1763 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
1764 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1765
1766 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
1767 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1768
1769 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
1770 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
1771
1772 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
1773 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
1774
1775 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
1776 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
1777 }
1778
1779 kfree(cmd);
1780 return rc;
1781 }
1782
1783 /*
1784 * CMD_SET_HW_SPEC.
1785 */
1786 struct mwl8k_cmd_set_hw_spec {
1787 struct mwl8k_cmd_pkt header;
1788 __u8 hw_rev;
1789 __u8 host_interface;
1790 __le16 num_mcaddrs;
1791 __u8 perm_addr[ETH_ALEN];
1792 __le16 region_code;
1793 __le32 fw_rev;
1794 __le32 ps_cookie;
1795 __le32 caps;
1796 __le32 rx_queue_ptr;
1797 __le32 num_tx_queues;
1798 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1799 __le32 flags;
1800 __le32 num_tx_desc_per_queue;
1801 __le32 total_rxd;
1802 } __attribute__((packed));
1803
1804 #define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
1805
1806 static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
1807 {
1808 struct mwl8k_priv *priv = hw->priv;
1809 struct mwl8k_cmd_set_hw_spec *cmd;
1810 int rc;
1811 int i;
1812
1813 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1814 if (cmd == NULL)
1815 return -ENOMEM;
1816
1817 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
1818 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1819
1820 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1821 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1822 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1823 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1824 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1825 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT);
1826 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1827 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1828
1829 rc = mwl8k_post_cmd(hw, &cmd->header);
1830 kfree(cmd);
1831
1832 return rc;
1833 }
1834
1835 /*
1836 * CMD_MAC_MULTICAST_ADR.
1837 */
1838 struct mwl8k_cmd_mac_multicast_adr {
1839 struct mwl8k_cmd_pkt header;
1840 __le16 action;
1841 __le16 numaddr;
1842 __u8 addr[0][ETH_ALEN];
1843 };
1844
1845 #define MWL8K_ENABLE_RX_DIRECTED 0x0001
1846 #define MWL8K_ENABLE_RX_MULTICAST 0x0002
1847 #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1848 #define MWL8K_ENABLE_RX_BROADCAST 0x0008
1849
1850 static struct mwl8k_cmd_pkt *
1851 __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
1852 int mc_count, struct dev_addr_list *mclist)
1853 {
1854 struct mwl8k_priv *priv = hw->priv;
1855 struct mwl8k_cmd_mac_multicast_adr *cmd;
1856 int size;
1857
1858 if (allmulti || mc_count > priv->num_mcaddrs) {
1859 allmulti = 1;
1860 mc_count = 0;
1861 }
1862
1863 size = sizeof(*cmd) + mc_count * ETH_ALEN;
1864
1865 cmd = kzalloc(size, GFP_ATOMIC);
1866 if (cmd == NULL)
1867 return NULL;
1868
1869 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1870 cmd->header.length = cpu_to_le16(size);
1871 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1872 MWL8K_ENABLE_RX_BROADCAST);
1873
1874 if (allmulti) {
1875 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1876 } else if (mc_count) {
1877 int i;
1878
1879 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1880 cmd->numaddr = cpu_to_le16(mc_count);
1881 for (i = 0; i < mc_count && mclist; i++) {
1882 if (mclist->da_addrlen != ETH_ALEN) {
1883 kfree(cmd);
1884 return NULL;
1885 }
1886 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1887 mclist = mclist->next;
1888 }
1889 }
1890
1891 return &cmd->header;
1892 }
1893
1894 /*
1895 * CMD_802_11_GET_STAT.
1896 */
1897 struct mwl8k_cmd_802_11_get_stat {
1898 struct mwl8k_cmd_pkt header;
1899 __le32 stats[64];
1900 } __attribute__((packed));
1901
1902 #define MWL8K_STAT_ACK_FAILURE 9
1903 #define MWL8K_STAT_RTS_FAILURE 12
1904 #define MWL8K_STAT_FCS_ERROR 24
1905 #define MWL8K_STAT_RTS_SUCCESS 11
1906
1907 static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1908 struct ieee80211_low_level_stats *stats)
1909 {
1910 struct mwl8k_cmd_802_11_get_stat *cmd;
1911 int rc;
1912
1913 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1914 if (cmd == NULL)
1915 return -ENOMEM;
1916
1917 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1918 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1919
1920 rc = mwl8k_post_cmd(hw, &cmd->header);
1921 if (!rc) {
1922 stats->dot11ACKFailureCount =
1923 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1924 stats->dot11RTSFailureCount =
1925 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1926 stats->dot11FCSErrorCount =
1927 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1928 stats->dot11RTSSuccessCount =
1929 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1930 }
1931 kfree(cmd);
1932
1933 return rc;
1934 }
1935
1936 /*
1937 * CMD_802_11_RADIO_CONTROL.
1938 */
1939 struct mwl8k_cmd_802_11_radio_control {
1940 struct mwl8k_cmd_pkt header;
1941 __le16 action;
1942 __le16 control;
1943 __le16 radio_on;
1944 } __attribute__((packed));
1945
1946 static int
1947 mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
1948 {
1949 struct mwl8k_priv *priv = hw->priv;
1950 struct mwl8k_cmd_802_11_radio_control *cmd;
1951 int rc;
1952
1953 if (enable == priv->radio_on && !force)
1954 return 0;
1955
1956 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1957 if (cmd == NULL)
1958 return -ENOMEM;
1959
1960 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1961 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1962 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1963 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
1964 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1965
1966 rc = mwl8k_post_cmd(hw, &cmd->header);
1967 kfree(cmd);
1968
1969 if (!rc)
1970 priv->radio_on = enable;
1971
1972 return rc;
1973 }
1974
1975 static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1976 {
1977 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1978 }
1979
1980 static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1981 {
1982 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1983 }
1984
1985 static int
1986 mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1987 {
1988 struct mwl8k_priv *priv;
1989
1990 if (hw == NULL || hw->priv == NULL)
1991 return -EINVAL;
1992 priv = hw->priv;
1993
1994 priv->radio_short_preamble = short_preamble;
1995
1996 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
1997 }
1998
1999 /*
2000 * CMD_802_11_RF_TX_POWER.
2001 */
2002 #define MWL8K_TX_POWER_LEVEL_TOTAL 8
2003
2004 struct mwl8k_cmd_802_11_rf_tx_power {
2005 struct mwl8k_cmd_pkt header;
2006 __le16 action;
2007 __le16 support_level;
2008 __le16 current_level;
2009 __le16 reserved;
2010 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
2011 } __attribute__((packed));
2012
2013 static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
2014 {
2015 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
2016 int rc;
2017
2018 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2019 if (cmd == NULL)
2020 return -ENOMEM;
2021
2022 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
2023 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2024 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2025 cmd->support_level = cpu_to_le16(dBm);
2026
2027 rc = mwl8k_post_cmd(hw, &cmd->header);
2028 kfree(cmd);
2029
2030 return rc;
2031 }
2032
2033 /*
2034 * CMD_RF_ANTENNA.
2035 */
2036 struct mwl8k_cmd_rf_antenna {
2037 struct mwl8k_cmd_pkt header;
2038 __le16 antenna;
2039 __le16 mode;
2040 } __attribute__((packed));
2041
2042 #define MWL8K_RF_ANTENNA_RX 1
2043 #define MWL8K_RF_ANTENNA_TX 2
2044
2045 static int
2046 mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2047 {
2048 struct mwl8k_cmd_rf_antenna *cmd;
2049 int rc;
2050
2051 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2052 if (cmd == NULL)
2053 return -ENOMEM;
2054
2055 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2056 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2057 cmd->antenna = cpu_to_le16(antenna);
2058 cmd->mode = cpu_to_le16(mask);
2059
2060 rc = mwl8k_post_cmd(hw, &cmd->header);
2061 kfree(cmd);
2062
2063 return rc;
2064 }
2065
2066 /*
2067 * CMD_SET_PRE_SCAN.
2068 */
2069 struct mwl8k_cmd_set_pre_scan {
2070 struct mwl8k_cmd_pkt header;
2071 } __attribute__((packed));
2072
2073 static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2074 {
2075 struct mwl8k_cmd_set_pre_scan *cmd;
2076 int rc;
2077
2078 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2079 if (cmd == NULL)
2080 return -ENOMEM;
2081
2082 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2083 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2084
2085 rc = mwl8k_post_cmd(hw, &cmd->header);
2086 kfree(cmd);
2087
2088 return rc;
2089 }
2090
2091 /*
2092 * CMD_SET_POST_SCAN.
2093 */
2094 struct mwl8k_cmd_set_post_scan {
2095 struct mwl8k_cmd_pkt header;
2096 __le32 isibss;
2097 __u8 bssid[ETH_ALEN];
2098 } __attribute__((packed));
2099
2100 static int
2101 mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
2102 {
2103 struct mwl8k_cmd_set_post_scan *cmd;
2104 int rc;
2105
2106 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2107 if (cmd == NULL)
2108 return -ENOMEM;
2109
2110 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2111 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2112 cmd->isibss = 0;
2113 memcpy(cmd->bssid, mac, ETH_ALEN);
2114
2115 rc = mwl8k_post_cmd(hw, &cmd->header);
2116 kfree(cmd);
2117
2118 return rc;
2119 }
2120
2121 /*
2122 * CMD_SET_RF_CHANNEL.
2123 */
2124 struct mwl8k_cmd_set_rf_channel {
2125 struct mwl8k_cmd_pkt header;
2126 __le16 action;
2127 __u8 current_channel;
2128 __le32 channel_flags;
2129 } __attribute__((packed));
2130
2131 static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
2132 struct ieee80211_channel *channel)
2133 {
2134 struct mwl8k_cmd_set_rf_channel *cmd;
2135 int rc;
2136
2137 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2138 if (cmd == NULL)
2139 return -ENOMEM;
2140
2141 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2142 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2143 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2144 cmd->current_channel = channel->hw_value;
2145 if (channel->band == IEEE80211_BAND_2GHZ)
2146 cmd->channel_flags = cpu_to_le32(0x00000081);
2147 else
2148 cmd->channel_flags = cpu_to_le32(0x00000000);
2149
2150 rc = mwl8k_post_cmd(hw, &cmd->header);
2151 kfree(cmd);
2152
2153 return rc;
2154 }
2155
2156 /*
2157 * CMD_SET_SLOT.
2158 */
2159 struct mwl8k_cmd_set_slot {
2160 struct mwl8k_cmd_pkt header;
2161 __le16 action;
2162 __u8 short_slot;
2163 } __attribute__((packed));
2164
2165 static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
2166 {
2167 struct mwl8k_cmd_set_slot *cmd;
2168 int rc;
2169
2170 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2171 if (cmd == NULL)
2172 return -ENOMEM;
2173
2174 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
2175 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2176 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2177 cmd->short_slot = short_slot_time;
2178
2179 rc = mwl8k_post_cmd(hw, &cmd->header);
2180 kfree(cmd);
2181
2182 return rc;
2183 }
2184
2185 /*
2186 * CMD_MIMO_CONFIG.
2187 */
2188 struct mwl8k_cmd_mimo_config {
2189 struct mwl8k_cmd_pkt header;
2190 __le32 action;
2191 __u8 rx_antenna_map;
2192 __u8 tx_antenna_map;
2193 } __attribute__((packed));
2194
2195 static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
2196 {
2197 struct mwl8k_cmd_mimo_config *cmd;
2198 int rc;
2199
2200 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2201 if (cmd == NULL)
2202 return -ENOMEM;
2203
2204 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
2205 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2206 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2207 cmd->rx_antenna_map = rx;
2208 cmd->tx_antenna_map = tx;
2209
2210 rc = mwl8k_post_cmd(hw, &cmd->header);
2211 kfree(cmd);
2212
2213 return rc;
2214 }
2215
2216 /*
2217 * CMD_ENABLE_SNIFFER.
2218 */
2219 struct mwl8k_cmd_enable_sniffer {
2220 struct mwl8k_cmd_pkt header;
2221 __le32 action;
2222 } __attribute__((packed));
2223
2224 static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2225 {
2226 struct mwl8k_cmd_enable_sniffer *cmd;
2227 int rc;
2228
2229 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2230 if (cmd == NULL)
2231 return -ENOMEM;
2232
2233 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
2234 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2235 cmd->action = cpu_to_le32(!!enable);
2236
2237 rc = mwl8k_post_cmd(hw, &cmd->header);
2238 kfree(cmd);
2239
2240 return rc;
2241 }
2242
2243 /*
2244 * CMD_SET_MAC_ADDR.
2245 */
2246 struct mwl8k_cmd_set_mac_addr {
2247 struct mwl8k_cmd_pkt header;
2248 union {
2249 struct {
2250 __le16 mac_type;
2251 __u8 mac_addr[ETH_ALEN];
2252 } mbss;
2253 __u8 mac_addr[ETH_ALEN];
2254 };
2255 } __attribute__((packed));
2256
2257 static int mwl8k_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
2258 {
2259 struct mwl8k_priv *priv = hw->priv;
2260 struct mwl8k_cmd_set_mac_addr *cmd;
2261 int rc;
2262
2263 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2264 if (cmd == NULL)
2265 return -ENOMEM;
2266
2267 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
2268 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2269 if (priv->ap_fw) {
2270 cmd->mbss.mac_type = 0;
2271 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
2272 } else {
2273 memcpy(cmd->mac_addr, mac, ETH_ALEN);
2274 }
2275
2276 rc = mwl8k_post_cmd(hw, &cmd->header);
2277 kfree(cmd);
2278
2279 return rc;
2280 }
2281
2282
2283 /*
2284 * CMD_SET_RATEADAPT_MODE.
2285 */
2286 struct mwl8k_cmd_set_rate_adapt_mode {
2287 struct mwl8k_cmd_pkt header;
2288 __le16 action;
2289 __le16 mode;
2290 } __attribute__((packed));
2291
2292 static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
2293 {
2294 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2295 int rc;
2296
2297 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2298 if (cmd == NULL)
2299 return -ENOMEM;
2300
2301 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2302 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2303 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2304 cmd->mode = cpu_to_le16(mode);
2305
2306 rc = mwl8k_post_cmd(hw, &cmd->header);
2307 kfree(cmd);
2308
2309 return rc;
2310 }
2311
2312 /*
2313 * CMD_SET_WMM_MODE.
2314 */
2315 struct mwl8k_cmd_set_wmm {
2316 struct mwl8k_cmd_pkt header;
2317 __le16 action;
2318 } __attribute__((packed));
2319
2320 static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
2321 {
2322 struct mwl8k_priv *priv = hw->priv;
2323 struct mwl8k_cmd_set_wmm *cmd;
2324 int rc;
2325
2326 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2327 if (cmd == NULL)
2328 return -ENOMEM;
2329
2330 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
2331 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2332 cmd->action = cpu_to_le16(!!enable);
2333
2334 rc = mwl8k_post_cmd(hw, &cmd->header);
2335 kfree(cmd);
2336
2337 if (!rc)
2338 priv->wmm_enabled = enable;
2339
2340 return rc;
2341 }
2342
2343 /*
2344 * CMD_SET_RTS_THRESHOLD.
2345 */
2346 struct mwl8k_cmd_rts_threshold {
2347 struct mwl8k_cmd_pkt header;
2348 __le16 action;
2349 __le16 threshold;
2350 } __attribute__((packed));
2351
2352 static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
2353 u16 action, u16 threshold)
2354 {
2355 struct mwl8k_cmd_rts_threshold *cmd;
2356 int rc;
2357
2358 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2359 if (cmd == NULL)
2360 return -ENOMEM;
2361
2362 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2363 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2364 cmd->action = cpu_to_le16(action);
2365 cmd->threshold = cpu_to_le16(threshold);
2366
2367 rc = mwl8k_post_cmd(hw, &cmd->header);
2368 kfree(cmd);
2369
2370 return rc;
2371 }
2372
2373 /*
2374 * CMD_SET_EDCA_PARAMS.
2375 */
2376 struct mwl8k_cmd_set_edca_params {
2377 struct mwl8k_cmd_pkt header;
2378
2379 /* See MWL8K_SET_EDCA_XXX below */
2380 __le16 action;
2381
2382 /* TX opportunity in units of 32 us */
2383 __le16 txop;
2384
2385 union {
2386 struct {
2387 /* Log exponent of max contention period: 0...15 */
2388 __le32 log_cw_max;
2389
2390 /* Log exponent of min contention period: 0...15 */
2391 __le32 log_cw_min;
2392
2393 /* Adaptive interframe spacing in units of 32us */
2394 __u8 aifs;
2395
2396 /* TX queue to configure */
2397 __u8 txq;
2398 } ap;
2399 struct {
2400 /* Log exponent of max contention period: 0...15 */
2401 __u8 log_cw_max;
2402
2403 /* Log exponent of min contention period: 0...15 */
2404 __u8 log_cw_min;
2405
2406 /* Adaptive interframe spacing in units of 32us */
2407 __u8 aifs;
2408
2409 /* TX queue to configure */
2410 __u8 txq;
2411 } sta;
2412 };
2413 } __attribute__((packed));
2414
2415 #define MWL8K_SET_EDCA_CW 0x01
2416 #define MWL8K_SET_EDCA_TXOP 0x02
2417 #define MWL8K_SET_EDCA_AIFS 0x04
2418
2419 #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2420 MWL8K_SET_EDCA_TXOP | \
2421 MWL8K_SET_EDCA_AIFS)
2422
2423 static int
2424 mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2425 __u16 cw_min, __u16 cw_max,
2426 __u8 aifs, __u16 txop)
2427 {
2428 struct mwl8k_priv *priv = hw->priv;
2429 struct mwl8k_cmd_set_edca_params *cmd;
2430 int rc;
2431
2432 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2433 if (cmd == NULL)
2434 return -ENOMEM;
2435
2436 /*
2437 * Queues 0 (BE) and 1 (BK) are swapped in hardware for
2438 * this call.
2439 */
2440 qnum ^= !(qnum >> 1);
2441
2442 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2443 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2444 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2445 cmd->txop = cpu_to_le16(txop);
2446 if (priv->ap_fw) {
2447 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
2448 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
2449 cmd->ap.aifs = aifs;
2450 cmd->ap.txq = qnum;
2451 } else {
2452 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
2453 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
2454 cmd->sta.aifs = aifs;
2455 cmd->sta.txq = qnum;
2456 }
2457
2458 rc = mwl8k_post_cmd(hw, &cmd->header);
2459 kfree(cmd);
2460
2461 return rc;
2462 }
2463
2464 /*
2465 * CMD_FINALIZE_JOIN.
2466 */
2467
2468 /* FJ beacon buffer size is compiled into the firmware. */
2469 #define MWL8K_FJ_BEACON_MAXLEN 128
2470
2471 struct mwl8k_cmd_finalize_join {
2472 struct mwl8k_cmd_pkt header;
2473 __le32 sleep_interval; /* Number of beacon periods to sleep */
2474 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2475 } __attribute__((packed));
2476
2477 static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2478 __u16 framelen, __u16 dtim)
2479 {
2480 struct mwl8k_cmd_finalize_join *cmd;
2481 struct ieee80211_mgmt *payload = frame;
2482 u16 hdrlen;
2483 u32 payload_len;
2484 int rc;
2485
2486 if (frame == NULL)
2487 return -EINVAL;
2488
2489 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2490 if (cmd == NULL)
2491 return -ENOMEM;
2492
2493 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2494 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2495 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2496
2497 hdrlen = ieee80211_hdrlen(payload->frame_control);
2498
2499 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2500
2501 /* XXX TBD Might just have to abort and return an error */
2502 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2503 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
2504 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2505 payload_len, MWL8K_FJ_BEACON_MAXLEN);
2506
2507 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2508 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2509
2510 if (payload && payload_len)
2511 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2512
2513 rc = mwl8k_post_cmd(hw, &cmd->header);
2514 kfree(cmd);
2515 return rc;
2516 }
2517
2518 /*
2519 * CMD_UPDATE_STADB.
2520 */
2521 struct mwl8k_cmd_update_sta_db {
2522 struct mwl8k_cmd_pkt header;
2523
2524 /* See STADB_ACTION_TYPE */
2525 __le32 action;
2526
2527 /* Peer MAC address */
2528 __u8 peer_addr[ETH_ALEN];
2529
2530 __le32 reserved;
2531
2532 /* Peer info - valid during add/update. */
2533 struct peer_capability_info peer_info;
2534 } __attribute__((packed));
2535
2536 static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2537 struct ieee80211_vif *vif, __u32 action)
2538 {
2539 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2540 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2541 struct mwl8k_cmd_update_sta_db *cmd;
2542 struct peer_capability_info *peer_info;
2543 int rc;
2544
2545 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2546 if (cmd == NULL)
2547 return -ENOMEM;
2548
2549 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2550 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2551
2552 cmd->action = cpu_to_le32(action);
2553 peer_info = &cmd->peer_info;
2554 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
2555
2556 switch (action) {
2557 case MWL8K_STA_DB_ADD_ENTRY:
2558 case MWL8K_STA_DB_MODIFY_ENTRY:
2559 /* Build peer_info block */
2560 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2561 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2562 memcpy(peer_info->legacy_rates, mwl8k_rateids,
2563 sizeof(mwl8k_rateids));
2564 peer_info->interop = 1;
2565 peer_info->amsdu_enabled = 0;
2566
2567 rc = mwl8k_post_cmd(hw, &cmd->header);
2568 if (rc == 0)
2569 mv_vif->peer_id = peer_info->station_id;
2570
2571 break;
2572
2573 case MWL8K_STA_DB_DEL_ENTRY:
2574 case MWL8K_STA_DB_FLUSH:
2575 default:
2576 rc = mwl8k_post_cmd(hw, &cmd->header);
2577 if (rc == 0)
2578 mv_vif->peer_id = 0;
2579 break;
2580 }
2581 kfree(cmd);
2582
2583 return rc;
2584 }
2585
2586 /*
2587 * CMD_SET_AID.
2588 */
2589 #define MWL8K_FRAME_PROT_DISABLED 0x00
2590 #define MWL8K_FRAME_PROT_11G 0x07
2591 #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2592 #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
2593
2594 struct mwl8k_cmd_update_set_aid {
2595 struct mwl8k_cmd_pkt header;
2596 __le16 aid;
2597
2598 /* AP's MAC address (BSSID) */
2599 __u8 bssid[ETH_ALEN];
2600 __le16 protection_mode;
2601 __u8 supp_rates[14];
2602 } __attribute__((packed));
2603
2604 static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2605 struct ieee80211_vif *vif)
2606 {
2607 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2608 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2609 struct mwl8k_cmd_update_set_aid *cmd;
2610 u16 prot_mode;
2611 int rc;
2612
2613 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2614 if (cmd == NULL)
2615 return -ENOMEM;
2616
2617 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2618 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2619 cmd->aid = cpu_to_le16(info->aid);
2620
2621 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
2622
2623 if (info->use_cts_prot) {
2624 prot_mode = MWL8K_FRAME_PROT_11G;
2625 } else {
2626 switch (info->ht_operation_mode &
2627 IEEE80211_HT_OP_MODE_PROTECTION) {
2628 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2629 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2630 break;
2631 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2632 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2633 break;
2634 default:
2635 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2636 break;
2637 }
2638 }
2639 cmd->protection_mode = cpu_to_le16(prot_mode);
2640
2641 memcpy(cmd->supp_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
2642
2643 rc = mwl8k_post_cmd(hw, &cmd->header);
2644 kfree(cmd);
2645
2646 return rc;
2647 }
2648
2649 /*
2650 * CMD_SET_RATE.
2651 */
2652 struct mwl8k_cmd_update_rateset {
2653 struct mwl8k_cmd_pkt header;
2654 __u8 legacy_rates[14];
2655
2656 /* Bitmap for supported MCS codes. */
2657 __u8 mcs_set[16];
2658 __u8 reserved[16];
2659 } __attribute__((packed));
2660
2661 static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2662 struct ieee80211_vif *vif)
2663 {
2664 struct mwl8k_cmd_update_rateset *cmd;
2665 int rc;
2666
2667 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2668 if (cmd == NULL)
2669 return -ENOMEM;
2670
2671 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2672 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2673 memcpy(cmd->legacy_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
2674
2675 rc = mwl8k_post_cmd(hw, &cmd->header);
2676 kfree(cmd);
2677
2678 return rc;
2679 }
2680
2681 /*
2682 * CMD_USE_FIXED_RATE.
2683 */
2684 #define MWL8K_RATE_TABLE_SIZE 8
2685 #define MWL8K_UCAST_RATE 0
2686 #define MWL8K_USE_AUTO_RATE 0x0002
2687
2688 struct mwl8k_rate_entry {
2689 /* Set to 1 if HT rate, 0 if legacy. */
2690 __le32 is_ht_rate;
2691
2692 /* Set to 1 to use retry_count field. */
2693 __le32 enable_retry;
2694
2695 /* Specified legacy rate or MCS. */
2696 __le32 rate;
2697
2698 /* Number of allowed retries. */
2699 __le32 retry_count;
2700 } __attribute__((packed));
2701
2702 struct mwl8k_rate_table {
2703 /* 1 to allow specified rate and below */
2704 __le32 allow_rate_drop;
2705 __le32 num_rates;
2706 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2707 } __attribute__((packed));
2708
2709 struct mwl8k_cmd_use_fixed_rate {
2710 struct mwl8k_cmd_pkt header;
2711 __le32 action;
2712 struct mwl8k_rate_table rate_table;
2713
2714 /* Unicast, Broadcast or Multicast */
2715 __le32 rate_type;
2716 __le32 reserved1;
2717 __le32 reserved2;
2718 } __attribute__((packed));
2719
2720 static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2721 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2722 {
2723 struct mwl8k_cmd_use_fixed_rate *cmd;
2724 int count;
2725 int rc;
2726
2727 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2728 if (cmd == NULL)
2729 return -ENOMEM;
2730
2731 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2732 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2733
2734 cmd->action = cpu_to_le32(action);
2735 cmd->rate_type = cpu_to_le32(rate_type);
2736
2737 if (rate_table != NULL) {
2738 /*
2739 * Copy over each field manually so that endian
2740 * conversion can be done.
2741 */
2742 cmd->rate_table.allow_rate_drop =
2743 cpu_to_le32(rate_table->allow_rate_drop);
2744 cmd->rate_table.num_rates =
2745 cpu_to_le32(rate_table->num_rates);
2746
2747 for (count = 0; count < rate_table->num_rates; count++) {
2748 struct mwl8k_rate_entry *dst =
2749 &cmd->rate_table.rate_entry[count];
2750 struct mwl8k_rate_entry *src =
2751 &rate_table->rate_entry[count];
2752
2753 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2754 dst->enable_retry = cpu_to_le32(src->enable_retry);
2755 dst->rate = cpu_to_le32(src->rate);
2756 dst->retry_count = cpu_to_le32(src->retry_count);
2757 }
2758 }
2759
2760 rc = mwl8k_post_cmd(hw, &cmd->header);
2761 kfree(cmd);
2762
2763 return rc;
2764 }
2765
2766
2767 /*
2768 * Interrupt handling.
2769 */
2770 static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2771 {
2772 struct ieee80211_hw *hw = dev_id;
2773 struct mwl8k_priv *priv = hw->priv;
2774 u32 status;
2775
2776 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2777 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2778
2779 if (!status)
2780 return IRQ_NONE;
2781
2782 if (status & MWL8K_A2H_INT_TX_DONE)
2783 tasklet_schedule(&priv->tx_reclaim_task);
2784
2785 if (status & MWL8K_A2H_INT_RX_READY) {
2786 while (rxq_process(hw, 0, 1))
2787 rxq_refill(hw, 0, 1);
2788 }
2789
2790 if (status & MWL8K_A2H_INT_OPC_DONE) {
2791 if (priv->hostcmd_wait != NULL)
2792 complete(priv->hostcmd_wait);
2793 }
2794
2795 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
2796 if (!mutex_is_locked(&priv->fw_mutex) &&
2797 priv->radio_on && priv->pending_tx_pkts)
2798 mwl8k_tx_start(priv);
2799 }
2800
2801 return IRQ_HANDLED;
2802 }
2803
2804
2805 /*
2806 * Core driver operations.
2807 */
2808 static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2809 {
2810 struct mwl8k_priv *priv = hw->priv;
2811 int index = skb_get_queue_mapping(skb);
2812 int rc;
2813
2814 if (priv->current_channel == NULL) {
2815 printk(KERN_DEBUG "%s: dropped TX frame since radio "
2816 "disabled\n", wiphy_name(hw->wiphy));
2817 dev_kfree_skb(skb);
2818 return NETDEV_TX_OK;
2819 }
2820
2821 rc = mwl8k_txq_xmit(hw, index, skb);
2822
2823 return rc;
2824 }
2825
2826 static int mwl8k_start(struct ieee80211_hw *hw)
2827 {
2828 struct mwl8k_priv *priv = hw->priv;
2829 int rc;
2830
2831 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
2832 IRQF_SHARED, MWL8K_NAME, hw);
2833 if (rc) {
2834 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2835 wiphy_name(hw->wiphy));
2836 return -EIO;
2837 }
2838
2839 /* Enable tx reclaim tasklet */
2840 tasklet_enable(&priv->tx_reclaim_task);
2841
2842 /* Enable interrupts */
2843 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2844
2845 rc = mwl8k_fw_lock(hw);
2846 if (!rc) {
2847 rc = mwl8k_cmd_802_11_radio_enable(hw);
2848
2849 if (!priv->ap_fw) {
2850 if (!rc)
2851 rc = mwl8k_enable_sniffer(hw, 0);
2852
2853 if (!rc)
2854 rc = mwl8k_cmd_set_pre_scan(hw);
2855
2856 if (!rc)
2857 rc = mwl8k_cmd_set_post_scan(hw,
2858 "\x00\x00\x00\x00\x00\x00");
2859 }
2860
2861 if (!rc)
2862 rc = mwl8k_cmd_setrateadaptmode(hw, 0);
2863
2864 if (!rc)
2865 rc = mwl8k_set_wmm(hw, 0);
2866
2867 mwl8k_fw_unlock(hw);
2868 }
2869
2870 if (rc) {
2871 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2872 free_irq(priv->pdev->irq, hw);
2873 tasklet_disable(&priv->tx_reclaim_task);
2874 }
2875
2876 return rc;
2877 }
2878
2879 static void mwl8k_stop(struct ieee80211_hw *hw)
2880 {
2881 struct mwl8k_priv *priv = hw->priv;
2882 int i;
2883
2884 mwl8k_cmd_802_11_radio_disable(hw);
2885
2886 ieee80211_stop_queues(hw);
2887
2888 /* Disable interrupts */
2889 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2890 free_irq(priv->pdev->irq, hw);
2891
2892 /* Stop finalize join worker */
2893 cancel_work_sync(&priv->finalize_join_worker);
2894 if (priv->beacon_skb != NULL)
2895 dev_kfree_skb(priv->beacon_skb);
2896
2897 /* Stop tx reclaim tasklet */
2898 tasklet_disable(&priv->tx_reclaim_task);
2899
2900 /* Return all skbs to mac80211 */
2901 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2902 mwl8k_txq_reclaim(hw, i, 1);
2903 }
2904
2905 static int mwl8k_add_interface(struct ieee80211_hw *hw,
2906 struct ieee80211_if_init_conf *conf)
2907 {
2908 struct mwl8k_priv *priv = hw->priv;
2909 struct mwl8k_vif *mwl8k_vif;
2910
2911 /*
2912 * We only support one active interface at a time.
2913 */
2914 if (priv->vif != NULL)
2915 return -EBUSY;
2916
2917 /*
2918 * We only support managed interfaces for now.
2919 */
2920 if (conf->type != NL80211_IFTYPE_STATION)
2921 return -EINVAL;
2922
2923 /*
2924 * Reject interface creation if sniffer mode is active, as
2925 * STA operation is mutually exclusive with hardware sniffer
2926 * mode.
2927 */
2928 if (priv->sniffer_enabled) {
2929 printk(KERN_INFO "%s: unable to create STA "
2930 "interface due to sniffer mode being enabled\n",
2931 wiphy_name(hw->wiphy));
2932 return -EINVAL;
2933 }
2934
2935 /* Clean out driver private area */
2936 mwl8k_vif = MWL8K_VIF(conf->vif);
2937 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2938
2939 /* Set and save the mac address */
2940 mwl8k_set_mac_addr(hw, conf->mac_addr);
2941 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
2942
2943 /* Back pointer to parent config block */
2944 mwl8k_vif->priv = priv;
2945
2946 /* Set Initial sequence number to zero */
2947 mwl8k_vif->seqno = 0;
2948
2949 priv->vif = conf->vif;
2950 priv->current_channel = NULL;
2951
2952 return 0;
2953 }
2954
2955 static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2956 struct ieee80211_if_init_conf *conf)
2957 {
2958 struct mwl8k_priv *priv = hw->priv;
2959
2960 if (priv->vif == NULL)
2961 return;
2962
2963 mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
2964
2965 priv->vif = NULL;
2966 }
2967
2968 static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
2969 {
2970 struct ieee80211_conf *conf = &hw->conf;
2971 struct mwl8k_priv *priv = hw->priv;
2972 int rc;
2973
2974 if (conf->flags & IEEE80211_CONF_IDLE) {
2975 mwl8k_cmd_802_11_radio_disable(hw);
2976 priv->current_channel = NULL;
2977 return 0;
2978 }
2979
2980 rc = mwl8k_fw_lock(hw);
2981 if (rc)
2982 return rc;
2983
2984 rc = mwl8k_cmd_802_11_radio_enable(hw);
2985 if (rc)
2986 goto out;
2987
2988 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2989 if (rc)
2990 goto out;
2991
2992 priv->current_channel = conf->channel;
2993
2994 if (conf->power_level > 18)
2995 conf->power_level = 18;
2996 rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level);
2997 if (rc)
2998 goto out;
2999
3000 if (priv->ap_fw) {
3001 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
3002 if (!rc)
3003 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
3004 } else {
3005 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
3006 }
3007
3008 out:
3009 mwl8k_fw_unlock(hw);
3010
3011 return rc;
3012 }
3013
3014 static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
3015 struct ieee80211_vif *vif,
3016 struct ieee80211_bss_conf *info,
3017 u32 changed)
3018 {
3019 struct mwl8k_priv *priv = hw->priv;
3020 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3021 int rc;
3022
3023 if (changed & BSS_CHANGED_BSSID)
3024 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
3025
3026 if ((changed & BSS_CHANGED_ASSOC) == 0)
3027 return;
3028
3029 priv->capture_beacon = false;
3030
3031 rc = mwl8k_fw_lock(hw);
3032 if (rc)
3033 return;
3034
3035 if (info->assoc) {
3036 memcpy(&mwl8k_vif->bss_info, info,
3037 sizeof(struct ieee80211_bss_conf));
3038
3039 /* Install rates */
3040 rc = mwl8k_update_rateset(hw, vif);
3041 if (rc)
3042 goto out;
3043
3044 /* Turn on rate adaptation */
3045 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
3046 MWL8K_UCAST_RATE, NULL);
3047 if (rc)
3048 goto out;
3049
3050 /* Set radio preamble */
3051 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
3052 if (rc)
3053 goto out;
3054
3055 /* Set slot time */
3056 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
3057 if (rc)
3058 goto out;
3059
3060 /* Update peer rate info */
3061 rc = mwl8k_cmd_update_sta_db(hw, vif,
3062 MWL8K_STA_DB_MODIFY_ENTRY);
3063 if (rc)
3064 goto out;
3065
3066 /* Set AID */
3067 rc = mwl8k_cmd_set_aid(hw, vif);
3068 if (rc)
3069 goto out;
3070
3071 /*
3072 * Finalize the join. Tell rx handler to process
3073 * next beacon from our BSSID.
3074 */
3075 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
3076 priv->capture_beacon = true;
3077 } else {
3078 rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
3079 memset(&mwl8k_vif->bss_info, 0,
3080 sizeof(struct ieee80211_bss_conf));
3081 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
3082 }
3083
3084 out:
3085 mwl8k_fw_unlock(hw);
3086 }
3087
3088 static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
3089 int mc_count, struct dev_addr_list *mclist)
3090 {
3091 struct mwl8k_cmd_pkt *cmd;
3092
3093 /*
3094 * Synthesize and return a command packet that programs the
3095 * hardware multicast address filter. At this point we don't
3096 * know whether FIF_ALLMULTI is being requested, but if it is,
3097 * we'll end up throwing this packet away and creating a new
3098 * one in mwl8k_configure_filter().
3099 */
3100 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
3101
3102 return (unsigned long)cmd;
3103 }
3104
3105 static int
3106 mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
3107 unsigned int changed_flags,
3108 unsigned int *total_flags)
3109 {
3110 struct mwl8k_priv *priv = hw->priv;
3111
3112 /*
3113 * Hardware sniffer mode is mutually exclusive with STA
3114 * operation, so refuse to enable sniffer mode if a STA
3115 * interface is active.
3116 */
3117 if (priv->vif != NULL) {
3118 if (net_ratelimit())
3119 printk(KERN_INFO "%s: not enabling sniffer "
3120 "mode because STA interface is active\n",
3121 wiphy_name(hw->wiphy));
3122 return 0;
3123 }
3124
3125 if (!priv->sniffer_enabled) {
3126 if (mwl8k_enable_sniffer(hw, 1))
3127 return 0;
3128 priv->sniffer_enabled = true;
3129 }
3130
3131 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
3132 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
3133 FIF_OTHER_BSS;
3134
3135 return 1;
3136 }
3137
3138 static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3139 unsigned int changed_flags,
3140 unsigned int *total_flags,
3141 u64 multicast)
3142 {
3143 struct mwl8k_priv *priv = hw->priv;
3144 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
3145
3146 /*
3147 * AP firmware doesn't allow fine-grained control over
3148 * the receive filter.
3149 */
3150 if (priv->ap_fw) {
3151 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3152 kfree(cmd);
3153 return;
3154 }
3155
3156 /*
3157 * Enable hardware sniffer mode if FIF_CONTROL or
3158 * FIF_OTHER_BSS is requested.
3159 */
3160 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
3161 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
3162 kfree(cmd);
3163 return;
3164 }
3165
3166 /* Clear unsupported feature flags */
3167 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3168
3169 if (mwl8k_fw_lock(hw))
3170 return;
3171
3172 if (priv->sniffer_enabled) {
3173 mwl8k_enable_sniffer(hw, 0);
3174 priv->sniffer_enabled = false;
3175 }
3176
3177 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
3178 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
3179 /*
3180 * Disable the BSS filter.
3181 */
3182 mwl8k_cmd_set_pre_scan(hw);
3183 } else {
3184 u8 *bssid;
3185
3186 /*
3187 * Enable the BSS filter.
3188 *
3189 * If there is an active STA interface, use that
3190 * interface's BSSID, otherwise use a dummy one
3191 * (where the OUI part needs to be nonzero for
3192 * the BSSID to be accepted by POST_SCAN).
3193 */
3194 bssid = "\x01\x00\x00\x00\x00\x00";
3195 if (priv->vif != NULL)
3196 bssid = MWL8K_VIF(priv->vif)->bssid;
3197
3198 mwl8k_cmd_set_post_scan(hw, bssid);
3199 }
3200 }
3201
3202 /*
3203 * If FIF_ALLMULTI is being requested, throw away the command
3204 * packet that ->prepare_multicast() built and replace it with
3205 * a command packet that enables reception of all multicast
3206 * packets.
3207 */
3208 if (*total_flags & FIF_ALLMULTI) {
3209 kfree(cmd);
3210 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
3211 }
3212
3213 if (cmd != NULL) {
3214 mwl8k_post_cmd(hw, cmd);
3215 kfree(cmd);
3216 }
3217
3218 mwl8k_fw_unlock(hw);
3219 }
3220
3221 static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3222 {
3223 return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value);
3224 }
3225
3226 static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3227 const struct ieee80211_tx_queue_params *params)
3228 {
3229 struct mwl8k_priv *priv = hw->priv;
3230 int rc;
3231
3232 rc = mwl8k_fw_lock(hw);
3233 if (!rc) {
3234 if (!priv->wmm_enabled)
3235 rc = mwl8k_set_wmm(hw, 1);
3236
3237 if (!rc)
3238 rc = mwl8k_set_edca_params(hw, queue,
3239 params->cw_min,
3240 params->cw_max,
3241 params->aifs,
3242 params->txop);
3243
3244 mwl8k_fw_unlock(hw);
3245 }
3246
3247 return rc;
3248 }
3249
3250 static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3251 struct ieee80211_tx_queue_stats *stats)
3252 {
3253 struct mwl8k_priv *priv = hw->priv;
3254 struct mwl8k_tx_queue *txq;
3255 int index;
3256
3257 spin_lock_bh(&priv->tx_lock);
3258 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3259 txq = priv->txq + index;
3260 memcpy(&stats[index], &txq->stats,
3261 sizeof(struct ieee80211_tx_queue_stats));
3262 }
3263 spin_unlock_bh(&priv->tx_lock);
3264
3265 return 0;
3266 }
3267
3268 static int mwl8k_get_stats(struct ieee80211_hw *hw,
3269 struct ieee80211_low_level_stats *stats)
3270 {
3271 return mwl8k_cmd_802_11_get_stat(hw, stats);
3272 }
3273
3274 static const struct ieee80211_ops mwl8k_ops = {
3275 .tx = mwl8k_tx,
3276 .start = mwl8k_start,
3277 .stop = mwl8k_stop,
3278 .add_interface = mwl8k_add_interface,
3279 .remove_interface = mwl8k_remove_interface,
3280 .config = mwl8k_config,
3281 .bss_info_changed = mwl8k_bss_info_changed,
3282 .prepare_multicast = mwl8k_prepare_multicast,
3283 .configure_filter = mwl8k_configure_filter,
3284 .set_rts_threshold = mwl8k_set_rts_threshold,
3285 .conf_tx = mwl8k_conf_tx,
3286 .get_tx_stats = mwl8k_get_tx_stats,
3287 .get_stats = mwl8k_get_stats,
3288 };
3289
3290 static void mwl8k_tx_reclaim_handler(unsigned long data)
3291 {
3292 int i;
3293 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
3294 struct mwl8k_priv *priv = hw->priv;
3295
3296 spin_lock_bh(&priv->tx_lock);
3297 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3298 mwl8k_txq_reclaim(hw, i, 0);
3299
3300 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
3301 complete(priv->tx_wait);
3302 priv->tx_wait = NULL;
3303 }
3304 spin_unlock_bh(&priv->tx_lock);
3305 }
3306
3307 static void mwl8k_finalize_join_worker(struct work_struct *work)
3308 {
3309 struct mwl8k_priv *priv =
3310 container_of(work, struct mwl8k_priv, finalize_join_worker);
3311 struct sk_buff *skb = priv->beacon_skb;
3312 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
3313
3314 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
3315 dev_kfree_skb(skb);
3316
3317 priv->beacon_skb = NULL;
3318 }
3319
3320 enum {
3321 MWL8687 = 0,
3322 MWL8366,
3323 };
3324
3325 static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
3326 {
3327 .part_name = "88w8687",
3328 .helper_image = "mwl8k/helper_8687.fw",
3329 .fw_image = "mwl8k/fmimage_8687.fw",
3330 .rxd_ops = &rxd_8687_ops,
3331 .modes = BIT(NL80211_IFTYPE_STATION),
3332 },
3333 {
3334 .part_name = "88w8366",
3335 .helper_image = "mwl8k/helper_8366.fw",
3336 .fw_image = "mwl8k/fmimage_8366.fw",
3337 .rxd_ops = &rxd_8366_ops,
3338 .modes = 0,
3339 },
3340 };
3341
3342 static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
3343 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
3344 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
3345 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
3346 { },
3347 };
3348 MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3349
3350 static int __devinit mwl8k_probe(struct pci_dev *pdev,
3351 const struct pci_device_id *id)
3352 {
3353 static int printed_version = 0;
3354 struct ieee80211_hw *hw;
3355 struct mwl8k_priv *priv;
3356 int rc;
3357 int i;
3358
3359 if (!printed_version) {
3360 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3361 printed_version = 1;
3362 }
3363
3364 rc = pci_enable_device(pdev);
3365 if (rc) {
3366 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3367 MWL8K_NAME);
3368 return rc;
3369 }
3370
3371 rc = pci_request_regions(pdev, MWL8K_NAME);
3372 if (rc) {
3373 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3374 MWL8K_NAME);
3375 return rc;
3376 }
3377
3378 pci_set_master(pdev);
3379
3380 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3381 if (hw == NULL) {
3382 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3383 rc = -ENOMEM;
3384 goto err_free_reg;
3385 }
3386
3387 priv = hw->priv;
3388 priv->hw = hw;
3389 priv->pdev = pdev;
3390 priv->device_info = &mwl8k_info_tbl[id->driver_data];
3391 priv->rxd_ops = priv->device_info->rxd_ops;
3392 priv->sniffer_enabled = false;
3393 priv->wmm_enabled = false;
3394 priv->pending_tx_pkts = 0;
3395
3396 SET_IEEE80211_DEV(hw, &pdev->dev);
3397 pci_set_drvdata(pdev, hw);
3398
3399 priv->sram = pci_iomap(pdev, 0, 0x10000);
3400 if (priv->sram == NULL) {
3401 printk(KERN_ERR "%s: Cannot map device SRAM\n",
3402 wiphy_name(hw->wiphy));
3403 goto err_iounmap;
3404 }
3405
3406 /*
3407 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3408 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3409 */
3410 priv->regs = pci_iomap(pdev, 1, 0x10000);
3411 if (priv->regs == NULL) {
3412 priv->regs = pci_iomap(pdev, 2, 0x10000);
3413 if (priv->regs == NULL) {
3414 printk(KERN_ERR "%s: Cannot map device registers\n",
3415 wiphy_name(hw->wiphy));
3416 goto err_iounmap;
3417 }
3418 }
3419
3420 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3421 priv->band.band = IEEE80211_BAND_2GHZ;
3422 priv->band.channels = priv->channels;
3423 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3424 priv->band.bitrates = priv->rates;
3425 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3426 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3427
3428 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3429 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3430
3431 /*
3432 * Extra headroom is the size of the required DMA header
3433 * minus the size of the smallest 802.11 frame (CTS frame).
3434 */
3435 hw->extra_tx_headroom =
3436 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3437
3438 hw->channel_change_time = 10;
3439
3440 hw->queues = MWL8K_TX_QUEUES;
3441
3442 hw->wiphy->interface_modes = priv->device_info->modes;
3443
3444 /* Set rssi and noise values to dBm */
3445 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
3446 hw->vif_data_size = sizeof(struct mwl8k_vif);
3447 priv->vif = NULL;
3448
3449 /* Set default radio state and preamble */
3450 priv->radio_on = 0;
3451 priv->radio_short_preamble = 0;
3452
3453 /* Finalize join worker */
3454 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3455
3456 /* TX reclaim tasklet */
3457 tasklet_init(&priv->tx_reclaim_task,
3458 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3459 tasklet_disable(&priv->tx_reclaim_task);
3460
3461 /* Power management cookie */
3462 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3463 if (priv->cookie == NULL)
3464 goto err_iounmap;
3465
3466 rc = mwl8k_rxq_init(hw, 0);
3467 if (rc)
3468 goto err_iounmap;
3469 rxq_refill(hw, 0, INT_MAX);
3470
3471 mutex_init(&priv->fw_mutex);
3472 priv->fw_mutex_owner = NULL;
3473 priv->fw_mutex_depth = 0;
3474 priv->hostcmd_wait = NULL;
3475
3476 spin_lock_init(&priv->tx_lock);
3477
3478 priv->tx_wait = NULL;
3479
3480 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3481 rc = mwl8k_txq_init(hw, i);
3482 if (rc)
3483 goto err_free_queues;
3484 }
3485
3486 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3487 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3488 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3489 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3490
3491 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
3492 IRQF_SHARED, MWL8K_NAME, hw);
3493 if (rc) {
3494 printk(KERN_ERR "%s: failed to register IRQ handler\n",
3495 wiphy_name(hw->wiphy));
3496 goto err_free_queues;
3497 }
3498
3499 /* Reset firmware and hardware */
3500 mwl8k_hw_reset(priv);
3501
3502 /* Ask userland hotplug daemon for the device firmware */
3503 rc = mwl8k_request_firmware(priv);
3504 if (rc) {
3505 printk(KERN_ERR "%s: Firmware files not found\n",
3506 wiphy_name(hw->wiphy));
3507 goto err_free_irq;
3508 }
3509
3510 /* Load firmware into hardware */
3511 rc = mwl8k_load_firmware(hw);
3512 if (rc) {
3513 printk(KERN_ERR "%s: Cannot start firmware\n",
3514 wiphy_name(hw->wiphy));
3515 goto err_stop_firmware;
3516 }
3517
3518 /* Reclaim memory once firmware is successfully loaded */
3519 mwl8k_release_firmware(priv);
3520
3521 /*
3522 * Temporarily enable interrupts. Initial firmware host
3523 * commands use interrupts and avoids polling. Disable
3524 * interrupts when done.
3525 */
3526 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3527
3528 /* Get config data, mac addrs etc */
3529 if (priv->ap_fw) {
3530 rc = mwl8k_cmd_get_hw_spec_ap(hw);
3531 if (!rc)
3532 rc = mwl8k_cmd_set_hw_spec(hw);
3533 } else {
3534 rc = mwl8k_cmd_get_hw_spec_sta(hw);
3535 }
3536 if (rc) {
3537 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3538 wiphy_name(hw->wiphy));
3539 goto err_stop_firmware;
3540 }
3541
3542 /* Turn radio off */
3543 rc = mwl8k_cmd_802_11_radio_disable(hw);
3544 if (rc) {
3545 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
3546 goto err_stop_firmware;
3547 }
3548
3549 /* Clear MAC address */
3550 rc = mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
3551 if (rc) {
3552 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3553 wiphy_name(hw->wiphy));
3554 goto err_stop_firmware;
3555 }
3556
3557 /* Disable interrupts */
3558 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3559 free_irq(priv->pdev->irq, hw);
3560
3561 rc = ieee80211_register_hw(hw);
3562 if (rc) {
3563 printk(KERN_ERR "%s: Cannot register device\n",
3564 wiphy_name(hw->wiphy));
3565 goto err_stop_firmware;
3566 }
3567
3568 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
3569 wiphy_name(hw->wiphy), priv->device_info->part_name,
3570 priv->hw_rev, hw->wiphy->perm_addr,
3571 priv->ap_fw ? "AP" : "STA",
3572 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3573 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
3574
3575 return 0;
3576
3577 err_stop_firmware:
3578 mwl8k_hw_reset(priv);
3579 mwl8k_release_firmware(priv);
3580
3581 err_free_irq:
3582 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3583 free_irq(priv->pdev->irq, hw);
3584
3585 err_free_queues:
3586 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3587 mwl8k_txq_deinit(hw, i);
3588 mwl8k_rxq_deinit(hw, 0);
3589
3590 err_iounmap:
3591 if (priv->cookie != NULL)
3592 pci_free_consistent(priv->pdev, 4,
3593 priv->cookie, priv->cookie_dma);
3594
3595 if (priv->regs != NULL)
3596 pci_iounmap(pdev, priv->regs);
3597
3598 if (priv->sram != NULL)
3599 pci_iounmap(pdev, priv->sram);
3600
3601 pci_set_drvdata(pdev, NULL);
3602 ieee80211_free_hw(hw);
3603
3604 err_free_reg:
3605 pci_release_regions(pdev);
3606 pci_disable_device(pdev);
3607
3608 return rc;
3609 }
3610
3611 static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
3612 {
3613 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3614 }
3615
3616 static void __devexit mwl8k_remove(struct pci_dev *pdev)
3617 {
3618 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3619 struct mwl8k_priv *priv;
3620 int i;
3621
3622 if (hw == NULL)
3623 return;
3624 priv = hw->priv;
3625
3626 ieee80211_stop_queues(hw);
3627
3628 ieee80211_unregister_hw(hw);
3629
3630 /* Remove tx reclaim tasklet */
3631 tasklet_kill(&priv->tx_reclaim_task);
3632
3633 /* Stop hardware */
3634 mwl8k_hw_reset(priv);
3635
3636 /* Return all skbs to mac80211 */
3637 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3638 mwl8k_txq_reclaim(hw, i, 1);
3639
3640 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3641 mwl8k_txq_deinit(hw, i);
3642
3643 mwl8k_rxq_deinit(hw, 0);
3644
3645 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
3646
3647 pci_iounmap(pdev, priv->regs);
3648 pci_iounmap(pdev, priv->sram);
3649 pci_set_drvdata(pdev, NULL);
3650 ieee80211_free_hw(hw);
3651 pci_release_regions(pdev);
3652 pci_disable_device(pdev);
3653 }
3654
3655 static struct pci_driver mwl8k_driver = {
3656 .name = MWL8K_NAME,
3657 .id_table = mwl8k_pci_id_table,
3658 .probe = mwl8k_probe,
3659 .remove = __devexit_p(mwl8k_remove),
3660 .shutdown = __devexit_p(mwl8k_shutdown),
3661 };
3662
3663 static int __init mwl8k_init(void)
3664 {
3665 return pci_register_driver(&mwl8k_driver);
3666 }
3667
3668 static void __exit mwl8k_exit(void)
3669 {
3670 pci_unregister_driver(&mwl8k_driver);
3671 }
3672
3673 module_init(mwl8k_init);
3674 module_exit(mwl8k_exit);
3675
3676 MODULE_DESCRIPTION(MWL8K_DESC);
3677 MODULE_VERSION(MWL8K_VERSION);
3678 MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3679 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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