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mwl8k: use the mac80211-provided workqueue instead of creating our own
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
1 /*
2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
4 *
5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/spinlock.h>
16 #include <linux/list.h>
17 #include <linux/pci.h>
18 #include <linux/delay.h>
19 #include <linux/completion.h>
20 #include <linux/etherdevice.h>
21 #include <net/mac80211.h>
22 #include <linux/moduleparam.h>
23 #include <linux/firmware.h>
24 #include <linux/workqueue.h>
25
26 #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
27 #define MWL8K_NAME KBUILD_MODNAME
28 #define MWL8K_VERSION "0.10"
29
30 static DEFINE_PCI_DEVICE_TABLE(mwl8k_table) = {
31 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = 8687, },
32 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = 8687, },
33 { }
34 };
35 MODULE_DEVICE_TABLE(pci, mwl8k_table);
36
37 /* Register definitions */
38 #define MWL8K_HIU_GEN_PTR 0x00000c10
39 #define MWL8K_MODE_STA 0x0000005a
40 #define MWL8K_MODE_AP 0x000000a5
41 #define MWL8K_HIU_INT_CODE 0x00000c14
42 #define MWL8K_FWSTA_READY 0xf0f1f2f4
43 #define MWL8K_FWAP_READY 0xf1f2f4a5
44 #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
45 #define MWL8K_HIU_SCRATCH 0x00000c40
46
47 /* Host->device communications */
48 #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
49 #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
50 #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
51 #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
52 #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
53 #define MWL8K_H2A_INT_DUMMY (1 << 20)
54 #define MWL8K_H2A_INT_RESET (1 << 15)
55 #define MWL8K_H2A_INT_DOORBELL (1 << 1)
56 #define MWL8K_H2A_INT_PPA_READY (1 << 0)
57
58 /* Device->host communications */
59 #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
60 #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
61 #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
62 #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
63 #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
64 #define MWL8K_A2H_INT_DUMMY (1 << 20)
65 #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
66 #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
67 #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
68 #define MWL8K_A2H_INT_RADIO_ON (1 << 6)
69 #define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
70 #define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
71 #define MWL8K_A2H_INT_OPC_DONE (1 << 2)
72 #define MWL8K_A2H_INT_RX_READY (1 << 1)
73 #define MWL8K_A2H_INT_TX_DONE (1 << 0)
74
75 #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
76 MWL8K_A2H_INT_CHNL_SWITCHED | \
77 MWL8K_A2H_INT_QUEUE_EMPTY | \
78 MWL8K_A2H_INT_RADAR_DETECT | \
79 MWL8K_A2H_INT_RADIO_ON | \
80 MWL8K_A2H_INT_RADIO_OFF | \
81 MWL8K_A2H_INT_MAC_EVENT | \
82 MWL8K_A2H_INT_OPC_DONE | \
83 MWL8K_A2H_INT_RX_READY | \
84 MWL8K_A2H_INT_TX_DONE)
85
86 /* WME stream classes */
87 #define WME_AC_BE 0 /* best effort */
88 #define WME_AC_BK 1 /* background */
89 #define WME_AC_VI 2 /* video */
90 #define WME_AC_VO 3 /* voice */
91
92 #define MWL8K_RX_QUEUES 1
93 #define MWL8K_TX_QUEUES 4
94
95 struct mwl8k_rx_queue {
96 int rx_desc_count;
97
98 /* hw receives here */
99 int rx_head;
100
101 /* refill descs here */
102 int rx_tail;
103
104 struct mwl8k_rx_desc *rx_desc_area;
105 dma_addr_t rx_desc_dma;
106 struct sk_buff **rx_skb;
107 };
108
109 struct mwl8k_tx_queue {
110 /* hw transmits here */
111 int tx_head;
112
113 /* sw appends here */
114 int tx_tail;
115
116 struct ieee80211_tx_queue_stats tx_stats;
117 struct mwl8k_tx_desc *tx_desc_area;
118 dma_addr_t tx_desc_dma;
119 struct sk_buff **tx_skb;
120 };
121
122 /* Pointers to the firmware data and meta information about it. */
123 struct mwl8k_firmware {
124 /* Microcode */
125 struct firmware *ucode;
126
127 /* Boot helper code */
128 struct firmware *helper;
129 };
130
131 struct mwl8k_priv {
132 void __iomem *regs;
133 struct ieee80211_hw *hw;
134
135 struct pci_dev *pdev;
136
137 /* firmware files and meta data */
138 struct mwl8k_firmware fw;
139 u32 part_num;
140
141 /* firmware access */
142 struct mutex fw_mutex;
143 struct task_struct *fw_mutex_owner;
144 int fw_mutex_depth;
145 struct completion *hostcmd_wait;
146
147 /* lock held over TX and TX reap */
148 spinlock_t tx_lock;
149
150 /* TX quiesce completion, protected by fw_mutex and tx_lock */
151 struct completion *tx_wait;
152
153 struct ieee80211_vif *vif;
154
155 struct ieee80211_channel *current_channel;
156
157 /* power management status cookie from firmware */
158 u32 *cookie;
159 dma_addr_t cookie_dma;
160
161 u16 num_mcaddrs;
162 u8 hw_rev;
163 u32 fw_rev;
164
165 /*
166 * Running count of TX packets in flight, to avoid
167 * iterating over the transmit rings each time.
168 */
169 int pending_tx_pkts;
170
171 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
172 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
173
174 /* PHY parameters */
175 struct ieee80211_supported_band band;
176 struct ieee80211_channel channels[14];
177 struct ieee80211_rate rates[12];
178
179 bool radio_on;
180 bool radio_short_preamble;
181 bool wmm_enabled;
182
183 /* XXX need to convert this to handle multiple interfaces */
184 bool capture_beacon;
185 u8 capture_bssid[ETH_ALEN];
186 struct sk_buff *beacon_skb;
187
188 /*
189 * This FJ worker has to be global as it is scheduled from the
190 * RX handler. At this point we don't know which interface it
191 * belongs to until the list of bssids waiting to complete join
192 * is checked.
193 */
194 struct work_struct finalize_join_worker;
195
196 /* Tasklet to reclaim TX descriptors and buffers after tx */
197 struct tasklet_struct tx_reclaim_task;
198 };
199
200 /* Per interface specific private data */
201 struct mwl8k_vif {
202 /* backpointer to parent config block */
203 struct mwl8k_priv *priv;
204
205 /* BSS config of AP or IBSS from mac80211*/
206 struct ieee80211_bss_conf bss_info;
207
208 /* BSSID of AP or IBSS */
209 u8 bssid[ETH_ALEN];
210 u8 mac_addr[ETH_ALEN];
211
212 /*
213 * Subset of supported legacy rates.
214 * Intersection of AP and STA supported rates.
215 */
216 struct ieee80211_rate legacy_rates[12];
217
218 /* number of supported legacy rates */
219 u8 legacy_nrates;
220
221 /* Index into station database.Returned by update_sta_db call */
222 u8 peer_id;
223
224 /* Non AMPDU sequence number assigned by driver */
225 u16 seqno;
226 };
227
228 #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
229
230 static const struct ieee80211_channel mwl8k_channels[] = {
231 { .center_freq = 2412, .hw_value = 1, },
232 { .center_freq = 2417, .hw_value = 2, },
233 { .center_freq = 2422, .hw_value = 3, },
234 { .center_freq = 2427, .hw_value = 4, },
235 { .center_freq = 2432, .hw_value = 5, },
236 { .center_freq = 2437, .hw_value = 6, },
237 { .center_freq = 2442, .hw_value = 7, },
238 { .center_freq = 2447, .hw_value = 8, },
239 { .center_freq = 2452, .hw_value = 9, },
240 { .center_freq = 2457, .hw_value = 10, },
241 { .center_freq = 2462, .hw_value = 11, },
242 };
243
244 static const struct ieee80211_rate mwl8k_rates[] = {
245 { .bitrate = 10, .hw_value = 2, },
246 { .bitrate = 20, .hw_value = 4, },
247 { .bitrate = 55, .hw_value = 11, },
248 { .bitrate = 60, .hw_value = 12, },
249 { .bitrate = 90, .hw_value = 18, },
250 { .bitrate = 110, .hw_value = 22, },
251 { .bitrate = 120, .hw_value = 24, },
252 { .bitrate = 180, .hw_value = 36, },
253 { .bitrate = 240, .hw_value = 48, },
254 { .bitrate = 360, .hw_value = 72, },
255 { .bitrate = 480, .hw_value = 96, },
256 { .bitrate = 540, .hw_value = 108, },
257 };
258
259 /* Set or get info from Firmware */
260 #define MWL8K_CMD_SET 0x0001
261 #define MWL8K_CMD_GET 0x0000
262
263 /* Firmware command codes */
264 #define MWL8K_CMD_CODE_DNLD 0x0001
265 #define MWL8K_CMD_GET_HW_SPEC 0x0003
266 #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
267 #define MWL8K_CMD_GET_STAT 0x0014
268 #define MWL8K_CMD_RADIO_CONTROL 0x001c
269 #define MWL8K_CMD_RF_TX_POWER 0x001e
270 #define MWL8K_CMD_SET_PRE_SCAN 0x0107
271 #define MWL8K_CMD_SET_POST_SCAN 0x0108
272 #define MWL8K_CMD_SET_RF_CHANNEL 0x010a
273 #define MWL8K_CMD_SET_AID 0x010d
274 #define MWL8K_CMD_SET_RATE 0x0110
275 #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
276 #define MWL8K_CMD_RTS_THRESHOLD 0x0113
277 #define MWL8K_CMD_SET_SLOT 0x0114
278 #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
279 #define MWL8K_CMD_SET_WMM_MODE 0x0123
280 #define MWL8K_CMD_MIMO_CONFIG 0x0125
281 #define MWL8K_CMD_USE_FIXED_RATE 0x0126
282 #define MWL8K_CMD_ENABLE_SNIFFER 0x0150
283 #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
284 #define MWL8K_CMD_UPDATE_STADB 0x1123
285
286 static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
287 {
288 #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
289 snprintf(buf, bufsize, "%s", #x);\
290 return buf;\
291 } while (0)
292 switch (cmd & ~0x8000) {
293 MWL8K_CMDNAME(CODE_DNLD);
294 MWL8K_CMDNAME(GET_HW_SPEC);
295 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
296 MWL8K_CMDNAME(GET_STAT);
297 MWL8K_CMDNAME(RADIO_CONTROL);
298 MWL8K_CMDNAME(RF_TX_POWER);
299 MWL8K_CMDNAME(SET_PRE_SCAN);
300 MWL8K_CMDNAME(SET_POST_SCAN);
301 MWL8K_CMDNAME(SET_RF_CHANNEL);
302 MWL8K_CMDNAME(SET_AID);
303 MWL8K_CMDNAME(SET_RATE);
304 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
305 MWL8K_CMDNAME(RTS_THRESHOLD);
306 MWL8K_CMDNAME(SET_SLOT);
307 MWL8K_CMDNAME(SET_EDCA_PARAMS);
308 MWL8K_CMDNAME(SET_WMM_MODE);
309 MWL8K_CMDNAME(MIMO_CONFIG);
310 MWL8K_CMDNAME(USE_FIXED_RATE);
311 MWL8K_CMDNAME(ENABLE_SNIFFER);
312 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
313 MWL8K_CMDNAME(UPDATE_STADB);
314 default:
315 snprintf(buf, bufsize, "0x%x", cmd);
316 }
317 #undef MWL8K_CMDNAME
318
319 return buf;
320 }
321
322 /* Hardware and firmware reset */
323 static void mwl8k_hw_reset(struct mwl8k_priv *priv)
324 {
325 iowrite32(MWL8K_H2A_INT_RESET,
326 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
327 iowrite32(MWL8K_H2A_INT_RESET,
328 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
329 msleep(20);
330 }
331
332 /* Release fw image */
333 static void mwl8k_release_fw(struct firmware **fw)
334 {
335 if (*fw == NULL)
336 return;
337 release_firmware(*fw);
338 *fw = NULL;
339 }
340
341 static void mwl8k_release_firmware(struct mwl8k_priv *priv)
342 {
343 mwl8k_release_fw(&priv->fw.ucode);
344 mwl8k_release_fw(&priv->fw.helper);
345 }
346
347 /* Request fw image */
348 static int mwl8k_request_fw(struct mwl8k_priv *priv,
349 const char *fname, struct firmware **fw)
350 {
351 /* release current image */
352 if (*fw != NULL)
353 mwl8k_release_fw(fw);
354
355 return request_firmware((const struct firmware **)fw,
356 fname, &priv->pdev->dev);
357 }
358
359 static int mwl8k_request_firmware(struct mwl8k_priv *priv, u32 part_num)
360 {
361 u8 filename[64];
362 int rc;
363
364 priv->part_num = part_num;
365
366 snprintf(filename, sizeof(filename),
367 "mwl8k/helper_%u.fw", priv->part_num);
368
369 rc = mwl8k_request_fw(priv, filename, &priv->fw.helper);
370 if (rc) {
371 printk(KERN_ERR "%s: Error requesting helper firmware "
372 "file %s\n", pci_name(priv->pdev), filename);
373 return rc;
374 }
375
376 snprintf(filename, sizeof(filename),
377 "mwl8k/fmimage_%u.fw", priv->part_num);
378
379 rc = mwl8k_request_fw(priv, filename, &priv->fw.ucode);
380 if (rc) {
381 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
382 pci_name(priv->pdev), filename);
383 mwl8k_release_fw(&priv->fw.helper);
384 return rc;
385 }
386
387 return 0;
388 }
389
390 struct mwl8k_cmd_pkt {
391 __le16 code;
392 __le16 length;
393 __le16 seq_num;
394 __le16 result;
395 char payload[0];
396 } __attribute__((packed));
397
398 /*
399 * Firmware loading.
400 */
401 static int
402 mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
403 {
404 void __iomem *regs = priv->regs;
405 dma_addr_t dma_addr;
406 int loops;
407
408 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
409 if (pci_dma_mapping_error(priv->pdev, dma_addr))
410 return -ENOMEM;
411
412 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
413 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
414 iowrite32(MWL8K_H2A_INT_DOORBELL,
415 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
416 iowrite32(MWL8K_H2A_INT_DUMMY,
417 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
418
419 loops = 1000;
420 do {
421 u32 int_code;
422
423 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
424 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
425 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
426 break;
427 }
428
429 udelay(1);
430 } while (--loops);
431
432 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
433
434 return loops ? 0 : -ETIMEDOUT;
435 }
436
437 static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
438 const u8 *data, size_t length)
439 {
440 struct mwl8k_cmd_pkt *cmd;
441 int done;
442 int rc = 0;
443
444 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
445 if (cmd == NULL)
446 return -ENOMEM;
447
448 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
449 cmd->seq_num = 0;
450 cmd->result = 0;
451
452 done = 0;
453 while (length) {
454 int block_size = length > 256 ? 256 : length;
455
456 memcpy(cmd->payload, data + done, block_size);
457 cmd->length = cpu_to_le16(block_size);
458
459 rc = mwl8k_send_fw_load_cmd(priv, cmd,
460 sizeof(*cmd) + block_size);
461 if (rc)
462 break;
463
464 done += block_size;
465 length -= block_size;
466 }
467
468 if (!rc) {
469 cmd->length = 0;
470 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
471 }
472
473 kfree(cmd);
474
475 return rc;
476 }
477
478 static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
479 const u8 *data, size_t length)
480 {
481 unsigned char *buffer;
482 int may_continue, rc = 0;
483 u32 done, prev_block_size;
484
485 buffer = kmalloc(1024, GFP_KERNEL);
486 if (buffer == NULL)
487 return -ENOMEM;
488
489 done = 0;
490 prev_block_size = 0;
491 may_continue = 1000;
492 while (may_continue > 0) {
493 u32 block_size;
494
495 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
496 if (block_size & 1) {
497 block_size &= ~1;
498 may_continue--;
499 } else {
500 done += prev_block_size;
501 length -= prev_block_size;
502 }
503
504 if (block_size > 1024 || block_size > length) {
505 rc = -EOVERFLOW;
506 break;
507 }
508
509 if (length == 0) {
510 rc = 0;
511 break;
512 }
513
514 if (block_size == 0) {
515 rc = -EPROTO;
516 may_continue--;
517 udelay(1);
518 continue;
519 }
520
521 prev_block_size = block_size;
522 memcpy(buffer, data + done, block_size);
523
524 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
525 if (rc)
526 break;
527 }
528
529 if (!rc && length != 0)
530 rc = -EREMOTEIO;
531
532 kfree(buffer);
533
534 return rc;
535 }
536
537 static int mwl8k_load_firmware(struct ieee80211_hw *hw)
538 {
539 struct mwl8k_priv *priv = hw->priv;
540 struct firmware *fw = priv->fw.ucode;
541 int rc;
542 int loops;
543
544 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
545 struct firmware *helper = priv->fw.helper;
546
547 if (helper == NULL) {
548 printk(KERN_ERR "%s: helper image needed but none "
549 "given\n", pci_name(priv->pdev));
550 return -EINVAL;
551 }
552
553 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
554 if (rc) {
555 printk(KERN_ERR "%s: unable to load firmware "
556 "helper image\n", pci_name(priv->pdev));
557 return rc;
558 }
559 msleep(1);
560
561 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
562 } else {
563 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
564 }
565
566 if (rc) {
567 printk(KERN_ERR "%s: unable to load firmware image\n",
568 pci_name(priv->pdev));
569 return rc;
570 }
571
572 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
573 msleep(1);
574
575 loops = 200000;
576 do {
577 if (ioread32(priv->regs + MWL8K_HIU_INT_CODE)
578 == MWL8K_FWSTA_READY)
579 break;
580 udelay(1);
581 } while (--loops);
582
583 return loops ? 0 : -ETIMEDOUT;
584 }
585
586
587 /*
588 * Defines shared between transmission and reception.
589 */
590 /* HT control fields for firmware */
591 struct ewc_ht_info {
592 __le16 control1;
593 __le16 control2;
594 __le16 control3;
595 } __attribute__((packed));
596
597 /* Firmware Station database operations */
598 #define MWL8K_STA_DB_ADD_ENTRY 0
599 #define MWL8K_STA_DB_MODIFY_ENTRY 1
600 #define MWL8K_STA_DB_DEL_ENTRY 2
601 #define MWL8K_STA_DB_FLUSH 3
602
603 /* Peer Entry flags - used to define the type of the peer node */
604 #define MWL8K_PEER_TYPE_ACCESSPOINT 2
605
606 #define MWL8K_IEEE_LEGACY_DATA_RATES 12
607 #define MWL8K_MCS_BITMAP_SIZE 16
608
609 struct peer_capability_info {
610 /* Peer type - AP vs. STA. */
611 __u8 peer_type;
612
613 /* Basic 802.11 capabilities from assoc resp. */
614 __le16 basic_caps;
615
616 /* Set if peer supports 802.11n high throughput (HT). */
617 __u8 ht_support;
618
619 /* Valid if HT is supported. */
620 __le16 ht_caps;
621 __u8 extended_ht_caps;
622 struct ewc_ht_info ewc_info;
623
624 /* Legacy rate table. Intersection of our rates and peer rates. */
625 __u8 legacy_rates[MWL8K_IEEE_LEGACY_DATA_RATES];
626
627 /* HT rate table. Intersection of our rates and peer rates. */
628 __u8 ht_rates[MWL8K_MCS_BITMAP_SIZE];
629 __u8 pad[16];
630
631 /* If set, interoperability mode, no proprietary extensions. */
632 __u8 interop;
633 __u8 pad2;
634 __u8 station_id;
635 __le16 amsdu_enabled;
636 } __attribute__((packed));
637
638 /* Inline functions to manipulate QoS field in data descriptor. */
639 static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
640 {
641 u16 val_mask = 1 << 4;
642
643 /* End of Service Period Bit 4 */
644 return qos | val_mask;
645 }
646
647 static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
648 {
649 u16 val_mask = 0x3;
650 u8 shift = 5;
651 u16 qos_mask = ~(val_mask << shift);
652
653 /* Ack Policy Bit 5-6 */
654 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
655 }
656
657 static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
658 {
659 u16 val_mask = 1 << 7;
660
661 /* AMSDU present Bit 7 */
662 return qos | val_mask;
663 }
664
665 static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
666 {
667 u16 val_mask = 0xff;
668 u8 shift = 8;
669 u16 qos_mask = ~(val_mask << shift);
670
671 /* Queue Length Bits 8-15 */
672 return (qos & qos_mask) | ((len & val_mask) << shift);
673 }
674
675 /* DMA header used by firmware and hardware. */
676 struct mwl8k_dma_data {
677 __le16 fwlen;
678 struct ieee80211_hdr wh;
679 } __attribute__((packed));
680
681 /* Routines to add/remove DMA header from skb. */
682 static inline void mwl8k_remove_dma_header(struct sk_buff *skb)
683 {
684 struct mwl8k_dma_data *tr = (struct mwl8k_dma_data *)skb->data;
685 void *dst, *src = &tr->wh;
686 int hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
687 u16 space = sizeof(struct mwl8k_dma_data) - hdrlen;
688
689 dst = (void *)tr + space;
690 if (dst != src) {
691 memmove(dst, src, hdrlen);
692 skb_pull(skb, space);
693 }
694 }
695
696 static inline void mwl8k_add_dma_header(struct sk_buff *skb)
697 {
698 struct ieee80211_hdr *wh;
699 u32 hdrlen, pktlen;
700 struct mwl8k_dma_data *tr;
701
702 wh = (struct ieee80211_hdr *)skb->data;
703 hdrlen = ieee80211_hdrlen(wh->frame_control);
704 pktlen = skb->len;
705
706 /*
707 * Copy up/down the 802.11 header; the firmware requires
708 * we present a 2-byte payload length followed by a
709 * 4-address header (w/o QoS), followed (optionally) by
710 * any WEP/ExtIV header (but only filled in for CCMP).
711 */
712 if (hdrlen != sizeof(struct mwl8k_dma_data))
713 skb_push(skb, sizeof(struct mwl8k_dma_data) - hdrlen);
714
715 tr = (struct mwl8k_dma_data *)skb->data;
716 if (wh != &tr->wh)
717 memmove(&tr->wh, wh, hdrlen);
718
719 /* Clear addr4 */
720 memset(tr->wh.addr4, 0, ETH_ALEN);
721
722 /*
723 * Firmware length is the length of the fully formed "802.11
724 * payload". That is, everything except for the 802.11 header.
725 * This includes all crypto material including the MIC.
726 */
727 tr->fwlen = cpu_to_le16(pktlen - hdrlen);
728 }
729
730
731 /*
732 * Packet reception.
733 */
734 #define MWL8K_RX_CTRL_OWNED_BY_HOST 0x02
735
736 struct mwl8k_rx_desc {
737 __le16 pkt_len;
738 __u8 link_quality;
739 __u8 noise_level;
740 __le32 pkt_phys_addr;
741 __le32 next_rx_desc_phys_addr;
742 __le16 qos_control;
743 __le16 rate_info;
744 __le32 pad0[4];
745 __u8 rssi;
746 __u8 channel;
747 __le16 pad1;
748 __u8 rx_ctrl;
749 __u8 rx_status;
750 __u8 pad2[2];
751 } __attribute__((packed));
752
753 #define MWL8K_RX_DESCS 256
754 #define MWL8K_RX_MAXSZ 3800
755
756 static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
757 {
758 struct mwl8k_priv *priv = hw->priv;
759 struct mwl8k_rx_queue *rxq = priv->rxq + index;
760 int size;
761 int i;
762
763 rxq->rx_desc_count = 0;
764 rxq->rx_head = 0;
765 rxq->rx_tail = 0;
766
767 size = MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc);
768
769 rxq->rx_desc_area =
770 pci_alloc_consistent(priv->pdev, size, &rxq->rx_desc_dma);
771 if (rxq->rx_desc_area == NULL) {
772 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
773 wiphy_name(hw->wiphy));
774 return -ENOMEM;
775 }
776 memset(rxq->rx_desc_area, 0, size);
777
778 rxq->rx_skb = kmalloc(MWL8K_RX_DESCS *
779 sizeof(*rxq->rx_skb), GFP_KERNEL);
780 if (rxq->rx_skb == NULL) {
781 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
782 wiphy_name(hw->wiphy));
783 pci_free_consistent(priv->pdev, size,
784 rxq->rx_desc_area, rxq->rx_desc_dma);
785 return -ENOMEM;
786 }
787 memset(rxq->rx_skb, 0, MWL8K_RX_DESCS * sizeof(*rxq->rx_skb));
788
789 for (i = 0; i < MWL8K_RX_DESCS; i++) {
790 struct mwl8k_rx_desc *rx_desc;
791 int nexti;
792
793 rx_desc = rxq->rx_desc_area + i;
794 nexti = (i + 1) % MWL8K_RX_DESCS;
795
796 rx_desc->next_rx_desc_phys_addr =
797 cpu_to_le32(rxq->rx_desc_dma
798 + nexti * sizeof(*rx_desc));
799 rx_desc->rx_ctrl = MWL8K_RX_CTRL_OWNED_BY_HOST;
800 }
801
802 return 0;
803 }
804
805 static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
806 {
807 struct mwl8k_priv *priv = hw->priv;
808 struct mwl8k_rx_queue *rxq = priv->rxq + index;
809 int refilled;
810
811 refilled = 0;
812 while (rxq->rx_desc_count < MWL8K_RX_DESCS && limit--) {
813 struct sk_buff *skb;
814 int rx;
815
816 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
817 if (skb == NULL)
818 break;
819
820 rxq->rx_desc_count++;
821
822 rx = rxq->rx_tail;
823 rxq->rx_tail = (rx + 1) % MWL8K_RX_DESCS;
824
825 rxq->rx_desc_area[rx].pkt_phys_addr =
826 cpu_to_le32(pci_map_single(priv->pdev, skb->data,
827 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE));
828
829 rxq->rx_desc_area[rx].pkt_len = cpu_to_le16(MWL8K_RX_MAXSZ);
830 rxq->rx_skb[rx] = skb;
831 wmb();
832 rxq->rx_desc_area[rx].rx_ctrl = 0;
833
834 refilled++;
835 }
836
837 return refilled;
838 }
839
840 /* Must be called only when the card's reception is completely halted */
841 static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
842 {
843 struct mwl8k_priv *priv = hw->priv;
844 struct mwl8k_rx_queue *rxq = priv->rxq + index;
845 int i;
846
847 for (i = 0; i < MWL8K_RX_DESCS; i++) {
848 if (rxq->rx_skb[i] != NULL) {
849 unsigned long addr;
850
851 addr = le32_to_cpu(rxq->rx_desc_area[i].pkt_phys_addr);
852 pci_unmap_single(priv->pdev, addr, MWL8K_RX_MAXSZ,
853 PCI_DMA_FROMDEVICE);
854 kfree_skb(rxq->rx_skb[i]);
855 rxq->rx_skb[i] = NULL;
856 }
857 }
858
859 kfree(rxq->rx_skb);
860 rxq->rx_skb = NULL;
861
862 pci_free_consistent(priv->pdev,
863 MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc),
864 rxq->rx_desc_area, rxq->rx_desc_dma);
865 rxq->rx_desc_area = NULL;
866 }
867
868
869 /*
870 * Scan a list of BSSIDs to process for finalize join.
871 * Allows for extension to process multiple BSSIDs.
872 */
873 static inline int
874 mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
875 {
876 return priv->capture_beacon &&
877 ieee80211_is_beacon(wh->frame_control) &&
878 !compare_ether_addr(wh->addr3, priv->capture_bssid);
879 }
880
881 static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
882 struct sk_buff *skb)
883 {
884 struct mwl8k_priv *priv = hw->priv;
885
886 priv->capture_beacon = false;
887 memset(priv->capture_bssid, 0, ETH_ALEN);
888
889 /*
890 * Use GFP_ATOMIC as rxq_process is called from
891 * the primary interrupt handler, memory allocation call
892 * must not sleep.
893 */
894 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
895 if (priv->beacon_skb != NULL)
896 ieee80211_queue_work(hw, &priv->finalize_join_worker);
897 }
898
899 static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
900 {
901 struct mwl8k_priv *priv = hw->priv;
902 struct mwl8k_rx_queue *rxq = priv->rxq + index;
903 int processed;
904
905 processed = 0;
906 while (rxq->rx_desc_count && limit--) {
907 struct mwl8k_rx_desc *rx_desc;
908 struct sk_buff *skb;
909 struct ieee80211_rx_status status;
910 unsigned long addr;
911 struct ieee80211_hdr *wh;
912
913 rx_desc = rxq->rx_desc_area + rxq->rx_head;
914 if (!(rx_desc->rx_ctrl & MWL8K_RX_CTRL_OWNED_BY_HOST))
915 break;
916 rmb();
917
918 skb = rxq->rx_skb[rxq->rx_head];
919 if (skb == NULL)
920 break;
921 rxq->rx_skb[rxq->rx_head] = NULL;
922
923 rxq->rx_head = (rxq->rx_head + 1) % MWL8K_RX_DESCS;
924 rxq->rx_desc_count--;
925
926 addr = le32_to_cpu(rx_desc->pkt_phys_addr);
927 pci_unmap_single(priv->pdev, addr,
928 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
929
930 skb_put(skb, le16_to_cpu(rx_desc->pkt_len));
931 mwl8k_remove_dma_header(skb);
932
933 wh = (struct ieee80211_hdr *)skb->data;
934
935 /*
936 * Check for a pending join operation. Save a
937 * copy of the beacon and schedule a tasklet to
938 * send a FINALIZE_JOIN command to the firmware.
939 */
940 if (mwl8k_capture_bssid(priv, wh))
941 mwl8k_save_beacon(hw, skb);
942
943 memset(&status, 0, sizeof(status));
944 status.mactime = 0;
945 status.signal = -rx_desc->rssi;
946 status.noise = -rx_desc->noise_level;
947 status.qual = rx_desc->link_quality;
948 status.antenna = 1;
949 status.rate_idx = 1;
950 status.flag = 0;
951 status.band = IEEE80211_BAND_2GHZ;
952 status.freq = ieee80211_channel_to_frequency(rx_desc->channel);
953 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
954 ieee80211_rx_irqsafe(hw, skb);
955
956 processed++;
957 }
958
959 return processed;
960 }
961
962
963 /*
964 * Packet transmission.
965 */
966
967 /* Transmit queue assignment. */
968 enum {
969 MWL8K_WME_AC_BK = 0, /* background access */
970 MWL8K_WME_AC_BE = 1, /* best effort access */
971 MWL8K_WME_AC_VI = 2, /* video access */
972 MWL8K_WME_AC_VO = 3, /* voice access */
973 };
974
975 /* Transmit packet ACK policy */
976 #define MWL8K_TXD_ACK_POLICY_NORMAL 0
977 #define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
978
979 #define GET_TXQ(_ac) (\
980 ((_ac) == WME_AC_VO) ? MWL8K_WME_AC_VO : \
981 ((_ac) == WME_AC_VI) ? MWL8K_WME_AC_VI : \
982 ((_ac) == WME_AC_BK) ? MWL8K_WME_AC_BK : \
983 MWL8K_WME_AC_BE)
984
985 #define MWL8K_TXD_STATUS_OK 0x00000001
986 #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
987 #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
988 #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
989 #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
990
991 struct mwl8k_tx_desc {
992 __le32 status;
993 __u8 data_rate;
994 __u8 tx_priority;
995 __le16 qos_control;
996 __le32 pkt_phys_addr;
997 __le16 pkt_len;
998 __u8 dest_MAC_addr[ETH_ALEN];
999 __le32 next_tx_desc_phys_addr;
1000 __le32 reserved;
1001 __le16 rate_info;
1002 __u8 peer_id;
1003 __u8 tx_frag_cnt;
1004 } __attribute__((packed));
1005
1006 #define MWL8K_TX_DESCS 128
1007
1008 static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1009 {
1010 struct mwl8k_priv *priv = hw->priv;
1011 struct mwl8k_tx_queue *txq = priv->txq + index;
1012 int size;
1013 int i;
1014
1015 memset(&txq->tx_stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1016 txq->tx_stats.limit = MWL8K_TX_DESCS;
1017 txq->tx_head = 0;
1018 txq->tx_tail = 0;
1019
1020 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1021
1022 txq->tx_desc_area =
1023 pci_alloc_consistent(priv->pdev, size, &txq->tx_desc_dma);
1024 if (txq->tx_desc_area == NULL) {
1025 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
1026 wiphy_name(hw->wiphy));
1027 return -ENOMEM;
1028 }
1029 memset(txq->tx_desc_area, 0, size);
1030
1031 txq->tx_skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->tx_skb),
1032 GFP_KERNEL);
1033 if (txq->tx_skb == NULL) {
1034 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
1035 wiphy_name(hw->wiphy));
1036 pci_free_consistent(priv->pdev, size,
1037 txq->tx_desc_area, txq->tx_desc_dma);
1038 return -ENOMEM;
1039 }
1040 memset(txq->tx_skb, 0, MWL8K_TX_DESCS * sizeof(*txq->tx_skb));
1041
1042 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1043 struct mwl8k_tx_desc *tx_desc;
1044 int nexti;
1045
1046 tx_desc = txq->tx_desc_area + i;
1047 nexti = (i + 1) % MWL8K_TX_DESCS;
1048
1049 tx_desc->status = 0;
1050 tx_desc->next_tx_desc_phys_addr =
1051 cpu_to_le32(txq->tx_desc_dma +
1052 nexti * sizeof(*tx_desc));
1053 }
1054
1055 return 0;
1056 }
1057
1058 static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1059 {
1060 iowrite32(MWL8K_H2A_INT_PPA_READY,
1061 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1062 iowrite32(MWL8K_H2A_INT_DUMMY,
1063 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1064 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1065 }
1066
1067 struct mwl8k_txq_info {
1068 u32 fw_owned;
1069 u32 drv_owned;
1070 u32 unused;
1071 u32 len;
1072 u32 head;
1073 u32 tail;
1074 };
1075
1076 static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
1077 struct mwl8k_txq_info *txinfo)
1078 {
1079 int count, desc, status;
1080 struct mwl8k_tx_queue *txq;
1081 struct mwl8k_tx_desc *tx_desc;
1082 int ndescs = 0;
1083
1084 memset(txinfo, 0, MWL8K_TX_QUEUES * sizeof(struct mwl8k_txq_info));
1085
1086 for (count = 0; count < MWL8K_TX_QUEUES; count++) {
1087 txq = priv->txq + count;
1088 txinfo[count].len = txq->tx_stats.len;
1089 txinfo[count].head = txq->tx_head;
1090 txinfo[count].tail = txq->tx_tail;
1091 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1092 tx_desc = txq->tx_desc_area + desc;
1093 status = le32_to_cpu(tx_desc->status);
1094
1095 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1096 txinfo[count].fw_owned++;
1097 else
1098 txinfo[count].drv_owned++;
1099
1100 if (tx_desc->pkt_len == 0)
1101 txinfo[count].unused++;
1102 }
1103 }
1104
1105 return ndescs;
1106 }
1107
1108 /*
1109 * Must be called with priv->fw_mutex held and tx queues stopped.
1110 */
1111 static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
1112 {
1113 struct mwl8k_priv *priv = hw->priv;
1114 DECLARE_COMPLETION_ONSTACK(tx_wait);
1115 u32 count;
1116 unsigned long timeout;
1117
1118 might_sleep();
1119
1120 spin_lock_bh(&priv->tx_lock);
1121 count = priv->pending_tx_pkts;
1122 if (count)
1123 priv->tx_wait = &tx_wait;
1124 spin_unlock_bh(&priv->tx_lock);
1125
1126 if (count) {
1127 struct mwl8k_txq_info txinfo[MWL8K_TX_QUEUES];
1128 int index;
1129 int newcount;
1130
1131 timeout = wait_for_completion_timeout(&tx_wait,
1132 msecs_to_jiffies(5000));
1133 if (timeout)
1134 return 0;
1135
1136 spin_lock_bh(&priv->tx_lock);
1137 priv->tx_wait = NULL;
1138 newcount = priv->pending_tx_pkts;
1139 mwl8k_scan_tx_ring(priv, txinfo);
1140 spin_unlock_bh(&priv->tx_lock);
1141
1142 printk(KERN_ERR "%s(%u) TIMEDOUT:5000ms Pend:%u-->%u\n",
1143 __func__, __LINE__, count, newcount);
1144
1145 for (index = 0; index < MWL8K_TX_QUEUES; index++)
1146 printk(KERN_ERR "TXQ:%u L:%u H:%u T:%u FW:%u "
1147 "DRV:%u U:%u\n",
1148 index,
1149 txinfo[index].len,
1150 txinfo[index].head,
1151 txinfo[index].tail,
1152 txinfo[index].fw_owned,
1153 txinfo[index].drv_owned,
1154 txinfo[index].unused);
1155
1156 return -ETIMEDOUT;
1157 }
1158
1159 return 0;
1160 }
1161
1162 #define MWL8K_TXD_SUCCESS(status) \
1163 ((status) & (MWL8K_TXD_STATUS_OK | \
1164 MWL8K_TXD_STATUS_OK_RETRY | \
1165 MWL8K_TXD_STATUS_OK_MORE_RETRY))
1166
1167 static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1168 {
1169 struct mwl8k_priv *priv = hw->priv;
1170 struct mwl8k_tx_queue *txq = priv->txq + index;
1171 int wake = 0;
1172
1173 while (txq->tx_stats.len > 0) {
1174 int tx;
1175 struct mwl8k_tx_desc *tx_desc;
1176 unsigned long addr;
1177 int size;
1178 struct sk_buff *skb;
1179 struct ieee80211_tx_info *info;
1180 u32 status;
1181
1182 tx = txq->tx_head;
1183 tx_desc = txq->tx_desc_area + tx;
1184
1185 status = le32_to_cpu(tx_desc->status);
1186
1187 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1188 if (!force)
1189 break;
1190 tx_desc->status &=
1191 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1192 }
1193
1194 txq->tx_head = (tx + 1) % MWL8K_TX_DESCS;
1195 BUG_ON(txq->tx_stats.len == 0);
1196 txq->tx_stats.len--;
1197 priv->pending_tx_pkts--;
1198
1199 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
1200 size = le16_to_cpu(tx_desc->pkt_len);
1201 skb = txq->tx_skb[tx];
1202 txq->tx_skb[tx] = NULL;
1203
1204 BUG_ON(skb == NULL);
1205 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1206
1207 mwl8k_remove_dma_header(skb);
1208
1209 /* Mark descriptor as unused */
1210 tx_desc->pkt_phys_addr = 0;
1211 tx_desc->pkt_len = 0;
1212
1213 info = IEEE80211_SKB_CB(skb);
1214 ieee80211_tx_info_clear_status(info);
1215 if (MWL8K_TXD_SUCCESS(status))
1216 info->flags |= IEEE80211_TX_STAT_ACK;
1217
1218 ieee80211_tx_status_irqsafe(hw, skb);
1219
1220 wake = 1;
1221 }
1222
1223 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
1224 ieee80211_wake_queue(hw, index);
1225 }
1226
1227 /* must be called only when the card's transmit is completely halted */
1228 static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1229 {
1230 struct mwl8k_priv *priv = hw->priv;
1231 struct mwl8k_tx_queue *txq = priv->txq + index;
1232
1233 mwl8k_txq_reclaim(hw, index, 1);
1234
1235 kfree(txq->tx_skb);
1236 txq->tx_skb = NULL;
1237
1238 pci_free_consistent(priv->pdev,
1239 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1240 txq->tx_desc_area, txq->tx_desc_dma);
1241 txq->tx_desc_area = NULL;
1242 }
1243
1244 static int
1245 mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1246 {
1247 struct mwl8k_priv *priv = hw->priv;
1248 struct ieee80211_tx_info *tx_info;
1249 struct mwl8k_vif *mwl8k_vif;
1250 struct ieee80211_hdr *wh;
1251 struct mwl8k_tx_queue *txq;
1252 struct mwl8k_tx_desc *tx;
1253 dma_addr_t dma;
1254 u32 txstatus;
1255 u8 txdatarate;
1256 u16 qos;
1257
1258 wh = (struct ieee80211_hdr *)skb->data;
1259 if (ieee80211_is_data_qos(wh->frame_control))
1260 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1261 else
1262 qos = 0;
1263
1264 mwl8k_add_dma_header(skb);
1265 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
1266
1267 tx_info = IEEE80211_SKB_CB(skb);
1268 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
1269
1270 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1271 u16 seqno = mwl8k_vif->seqno;
1272
1273 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1274 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1275 mwl8k_vif->seqno = seqno++ % 4096;
1276 }
1277
1278 /* Setup firmware control bit fields for each frame type. */
1279 txstatus = 0;
1280 txdatarate = 0;
1281 if (ieee80211_is_mgmt(wh->frame_control) ||
1282 ieee80211_is_ctl(wh->frame_control)) {
1283 txdatarate = 0;
1284 qos = mwl8k_qos_setbit_eosp(qos);
1285 /* Set Queue size to unspecified */
1286 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1287 } else if (ieee80211_is_data(wh->frame_control)) {
1288 txdatarate = 1;
1289 if (is_multicast_ether_addr(wh->addr1))
1290 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1291
1292 /* Send pkt in an aggregate if AMPDU frame. */
1293 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1294 qos = mwl8k_qos_setbit_ack(qos,
1295 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1296 else
1297 qos = mwl8k_qos_setbit_ack(qos,
1298 MWL8K_TXD_ACK_POLICY_NORMAL);
1299
1300 if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
1301 qos = mwl8k_qos_setbit_amsdu(qos);
1302 }
1303
1304 dma = pci_map_single(priv->pdev, skb->data,
1305 skb->len, PCI_DMA_TODEVICE);
1306
1307 if (pci_dma_mapping_error(priv->pdev, dma)) {
1308 printk(KERN_DEBUG "%s: failed to dma map skb, "
1309 "dropping TX frame.\n", wiphy_name(hw->wiphy));
1310 dev_kfree_skb(skb);
1311 return NETDEV_TX_OK;
1312 }
1313
1314 spin_lock_bh(&priv->tx_lock);
1315
1316 txq = priv->txq + index;
1317
1318 BUG_ON(txq->tx_skb[txq->tx_tail] != NULL);
1319 txq->tx_skb[txq->tx_tail] = skb;
1320
1321 tx = txq->tx_desc_area + txq->tx_tail;
1322 tx->data_rate = txdatarate;
1323 tx->tx_priority = index;
1324 tx->qos_control = cpu_to_le16(qos);
1325 tx->pkt_phys_addr = cpu_to_le32(dma);
1326 tx->pkt_len = cpu_to_le16(skb->len);
1327 tx->rate_info = 0;
1328 tx->peer_id = mwl8k_vif->peer_id;
1329 wmb();
1330 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1331
1332 txq->tx_stats.count++;
1333 txq->tx_stats.len++;
1334 priv->pending_tx_pkts++;
1335
1336 txq->tx_tail++;
1337 if (txq->tx_tail == MWL8K_TX_DESCS)
1338 txq->tx_tail = 0;
1339
1340 if (txq->tx_head == txq->tx_tail)
1341 ieee80211_stop_queue(hw, index);
1342
1343 mwl8k_tx_start(priv);
1344
1345 spin_unlock_bh(&priv->tx_lock);
1346
1347 return NETDEV_TX_OK;
1348 }
1349
1350
1351 /*
1352 * Firmware access.
1353 *
1354 * We have the following requirements for issuing firmware commands:
1355 * - Some commands require that the packet transmit path is idle when
1356 * the command is issued. (For simplicity, we'll just quiesce the
1357 * transmit path for every command.)
1358 * - There are certain sequences of commands that need to be issued to
1359 * the hardware sequentially, with no other intervening commands.
1360 *
1361 * This leads to an implementation of a "firmware lock" as a mutex that
1362 * can be taken recursively, and which is taken by both the low-level
1363 * command submission function (mwl8k_post_cmd) as well as any users of
1364 * that function that require issuing of an atomic sequence of commands,
1365 * and quiesces the transmit path whenever it's taken.
1366 */
1367 static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1368 {
1369 struct mwl8k_priv *priv = hw->priv;
1370
1371 if (priv->fw_mutex_owner != current) {
1372 int rc;
1373
1374 mutex_lock(&priv->fw_mutex);
1375 ieee80211_stop_queues(hw);
1376
1377 rc = mwl8k_tx_wait_empty(hw);
1378 if (rc) {
1379 ieee80211_wake_queues(hw);
1380 mutex_unlock(&priv->fw_mutex);
1381
1382 return rc;
1383 }
1384
1385 priv->fw_mutex_owner = current;
1386 }
1387
1388 priv->fw_mutex_depth++;
1389
1390 return 0;
1391 }
1392
1393 static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1394 {
1395 struct mwl8k_priv *priv = hw->priv;
1396
1397 if (!--priv->fw_mutex_depth) {
1398 ieee80211_wake_queues(hw);
1399 priv->fw_mutex_owner = NULL;
1400 mutex_unlock(&priv->fw_mutex);
1401 }
1402 }
1403
1404
1405 /*
1406 * Command processing.
1407 */
1408
1409 /* Timeout firmware commands after 2000ms */
1410 #define MWL8K_CMD_TIMEOUT_MS 2000
1411
1412 static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1413 {
1414 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1415 struct mwl8k_priv *priv = hw->priv;
1416 void __iomem *regs = priv->regs;
1417 dma_addr_t dma_addr;
1418 unsigned int dma_size;
1419 int rc;
1420 unsigned long timeout = 0;
1421 u8 buf[32];
1422
1423 cmd->result = 0xffff;
1424 dma_size = le16_to_cpu(cmd->length);
1425 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1426 PCI_DMA_BIDIRECTIONAL);
1427 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1428 return -ENOMEM;
1429
1430 rc = mwl8k_fw_lock(hw);
1431 if (rc) {
1432 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1433 PCI_DMA_BIDIRECTIONAL);
1434 return rc;
1435 }
1436
1437 priv->hostcmd_wait = &cmd_wait;
1438 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1439 iowrite32(MWL8K_H2A_INT_DOORBELL,
1440 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1441 iowrite32(MWL8K_H2A_INT_DUMMY,
1442 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1443
1444 timeout = wait_for_completion_timeout(&cmd_wait,
1445 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1446
1447 priv->hostcmd_wait = NULL;
1448
1449 mwl8k_fw_unlock(hw);
1450
1451 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1452 PCI_DMA_BIDIRECTIONAL);
1453
1454 if (!timeout) {
1455 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
1456 wiphy_name(hw->wiphy),
1457 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1458 MWL8K_CMD_TIMEOUT_MS);
1459 rc = -ETIMEDOUT;
1460 } else {
1461 rc = cmd->result ? -EINVAL : 0;
1462 if (rc)
1463 printk(KERN_ERR "%s: Command %s error 0x%x\n",
1464 wiphy_name(hw->wiphy),
1465 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1466 le16_to_cpu(cmd->result));
1467 }
1468
1469 return rc;
1470 }
1471
1472 /*
1473 * GET_HW_SPEC.
1474 */
1475 struct mwl8k_cmd_get_hw_spec {
1476 struct mwl8k_cmd_pkt header;
1477 __u8 hw_rev;
1478 __u8 host_interface;
1479 __le16 num_mcaddrs;
1480 __u8 perm_addr[ETH_ALEN];
1481 __le16 region_code;
1482 __le32 fw_rev;
1483 __le32 ps_cookie;
1484 __le32 caps;
1485 __u8 mcs_bitmap[16];
1486 __le32 rx_queue_ptr;
1487 __le32 num_tx_queues;
1488 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1489 __le32 caps2;
1490 __le32 num_tx_desc_per_queue;
1491 __le32 total_rx_desc;
1492 } __attribute__((packed));
1493
1494 static int mwl8k_cmd_get_hw_spec(struct ieee80211_hw *hw)
1495 {
1496 struct mwl8k_priv *priv = hw->priv;
1497 struct mwl8k_cmd_get_hw_spec *cmd;
1498 int rc;
1499 int i;
1500
1501 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1502 if (cmd == NULL)
1503 return -ENOMEM;
1504
1505 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1506 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1507
1508 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1509 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1510 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rx_desc_dma);
1511 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1512 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1513 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].tx_desc_dma);
1514 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1515 cmd->total_rx_desc = cpu_to_le32(MWL8K_RX_DESCS);
1516
1517 rc = mwl8k_post_cmd(hw, &cmd->header);
1518
1519 if (!rc) {
1520 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1521 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1522 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1523 priv->hw_rev = cmd->hw_rev;
1524 }
1525
1526 kfree(cmd);
1527 return rc;
1528 }
1529
1530 /*
1531 * CMD_MAC_MULTICAST_ADR.
1532 */
1533 struct mwl8k_cmd_mac_multicast_adr {
1534 struct mwl8k_cmd_pkt header;
1535 __le16 action;
1536 __le16 numaddr;
1537 __u8 addr[0][ETH_ALEN];
1538 };
1539
1540 #define MWL8K_ENABLE_RX_DIRECTED 0x0001
1541 #define MWL8K_ENABLE_RX_MULTICAST 0x0002
1542 #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1543 #define MWL8K_ENABLE_RX_BROADCAST 0x0008
1544
1545 static struct mwl8k_cmd_pkt *
1546 __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw,
1547 int mc_count, struct dev_addr_list *mclist)
1548 {
1549 struct mwl8k_priv *priv = hw->priv;
1550 struct mwl8k_cmd_mac_multicast_adr *cmd;
1551 int allmulti;
1552 int size;
1553
1554 allmulti = 0;
1555 if (mc_count > priv->num_mcaddrs) {
1556 allmulti = 1;
1557 mc_count = 0;
1558 }
1559
1560 size = sizeof(*cmd) + mc_count * ETH_ALEN;
1561
1562 cmd = kzalloc(size, GFP_ATOMIC);
1563 if (cmd == NULL)
1564 return NULL;
1565
1566 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1567 cmd->header.length = cpu_to_le16(size);
1568 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1569 MWL8K_ENABLE_RX_BROADCAST);
1570
1571 if (allmulti) {
1572 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1573 } else if (mc_count) {
1574 int i;
1575
1576 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1577 cmd->numaddr = cpu_to_le16(mc_count);
1578 for (i = 0; i < mc_count && mclist; i++) {
1579 if (mclist->da_addrlen != ETH_ALEN) {
1580 kfree(cmd);
1581 return NULL;
1582 }
1583 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1584 mclist = mclist->next;
1585 }
1586 }
1587
1588 return &cmd->header;
1589 }
1590
1591 /*
1592 * CMD_802_11_GET_STAT.
1593 */
1594 struct mwl8k_cmd_802_11_get_stat {
1595 struct mwl8k_cmd_pkt header;
1596 __le32 stats[64];
1597 } __attribute__((packed));
1598
1599 #define MWL8K_STAT_ACK_FAILURE 9
1600 #define MWL8K_STAT_RTS_FAILURE 12
1601 #define MWL8K_STAT_FCS_ERROR 24
1602 #define MWL8K_STAT_RTS_SUCCESS 11
1603
1604 static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1605 struct ieee80211_low_level_stats *stats)
1606 {
1607 struct mwl8k_cmd_802_11_get_stat *cmd;
1608 int rc;
1609
1610 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1611 if (cmd == NULL)
1612 return -ENOMEM;
1613
1614 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1615 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1616
1617 rc = mwl8k_post_cmd(hw, &cmd->header);
1618 if (!rc) {
1619 stats->dot11ACKFailureCount =
1620 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1621 stats->dot11RTSFailureCount =
1622 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1623 stats->dot11FCSErrorCount =
1624 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1625 stats->dot11RTSSuccessCount =
1626 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1627 }
1628 kfree(cmd);
1629
1630 return rc;
1631 }
1632
1633 /*
1634 * CMD_802_11_RADIO_CONTROL.
1635 */
1636 struct mwl8k_cmd_802_11_radio_control {
1637 struct mwl8k_cmd_pkt header;
1638 __le16 action;
1639 __le16 control;
1640 __le16 radio_on;
1641 } __attribute__((packed));
1642
1643 static int
1644 mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
1645 {
1646 struct mwl8k_priv *priv = hw->priv;
1647 struct mwl8k_cmd_802_11_radio_control *cmd;
1648 int rc;
1649
1650 if (enable == priv->radio_on && !force)
1651 return 0;
1652
1653 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1654 if (cmd == NULL)
1655 return -ENOMEM;
1656
1657 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1658 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1659 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1660 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
1661 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1662
1663 rc = mwl8k_post_cmd(hw, &cmd->header);
1664 kfree(cmd);
1665
1666 if (!rc)
1667 priv->radio_on = enable;
1668
1669 return rc;
1670 }
1671
1672 static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1673 {
1674 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1675 }
1676
1677 static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1678 {
1679 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1680 }
1681
1682 static int
1683 mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1684 {
1685 struct mwl8k_priv *priv;
1686
1687 if (hw == NULL || hw->priv == NULL)
1688 return -EINVAL;
1689 priv = hw->priv;
1690
1691 priv->radio_short_preamble = short_preamble;
1692
1693 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
1694 }
1695
1696 /*
1697 * CMD_802_11_RF_TX_POWER.
1698 */
1699 #define MWL8K_TX_POWER_LEVEL_TOTAL 8
1700
1701 struct mwl8k_cmd_802_11_rf_tx_power {
1702 struct mwl8k_cmd_pkt header;
1703 __le16 action;
1704 __le16 support_level;
1705 __le16 current_level;
1706 __le16 reserved;
1707 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1708 } __attribute__((packed));
1709
1710 static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1711 {
1712 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
1713 int rc;
1714
1715 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1716 if (cmd == NULL)
1717 return -ENOMEM;
1718
1719 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1720 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1721 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1722 cmd->support_level = cpu_to_le16(dBm);
1723
1724 rc = mwl8k_post_cmd(hw, &cmd->header);
1725 kfree(cmd);
1726
1727 return rc;
1728 }
1729
1730 /*
1731 * CMD_SET_PRE_SCAN.
1732 */
1733 struct mwl8k_cmd_set_pre_scan {
1734 struct mwl8k_cmd_pkt header;
1735 } __attribute__((packed));
1736
1737 static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
1738 {
1739 struct mwl8k_cmd_set_pre_scan *cmd;
1740 int rc;
1741
1742 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1743 if (cmd == NULL)
1744 return -ENOMEM;
1745
1746 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
1747 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1748
1749 rc = mwl8k_post_cmd(hw, &cmd->header);
1750 kfree(cmd);
1751
1752 return rc;
1753 }
1754
1755 /*
1756 * CMD_SET_POST_SCAN.
1757 */
1758 struct mwl8k_cmd_set_post_scan {
1759 struct mwl8k_cmd_pkt header;
1760 __le32 isibss;
1761 __u8 bssid[ETH_ALEN];
1762 } __attribute__((packed));
1763
1764 static int
1765 mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
1766 {
1767 struct mwl8k_cmd_set_post_scan *cmd;
1768 int rc;
1769
1770 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1771 if (cmd == NULL)
1772 return -ENOMEM;
1773
1774 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
1775 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1776 cmd->isibss = 0;
1777 memcpy(cmd->bssid, mac, ETH_ALEN);
1778
1779 rc = mwl8k_post_cmd(hw, &cmd->header);
1780 kfree(cmd);
1781
1782 return rc;
1783 }
1784
1785 /*
1786 * CMD_SET_RF_CHANNEL.
1787 */
1788 struct mwl8k_cmd_set_rf_channel {
1789 struct mwl8k_cmd_pkt header;
1790 __le16 action;
1791 __u8 current_channel;
1792 __le32 channel_flags;
1793 } __attribute__((packed));
1794
1795 static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
1796 struct ieee80211_channel *channel)
1797 {
1798 struct mwl8k_cmd_set_rf_channel *cmd;
1799 int rc;
1800
1801 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1802 if (cmd == NULL)
1803 return -ENOMEM;
1804
1805 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
1806 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1807 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1808 cmd->current_channel = channel->hw_value;
1809 if (channel->band == IEEE80211_BAND_2GHZ)
1810 cmd->channel_flags = cpu_to_le32(0x00000081);
1811 else
1812 cmd->channel_flags = cpu_to_le32(0x00000000);
1813
1814 rc = mwl8k_post_cmd(hw, &cmd->header);
1815 kfree(cmd);
1816
1817 return rc;
1818 }
1819
1820 /*
1821 * CMD_SET_SLOT.
1822 */
1823 struct mwl8k_cmd_set_slot {
1824 struct mwl8k_cmd_pkt header;
1825 __le16 action;
1826 __u8 short_slot;
1827 } __attribute__((packed));
1828
1829 static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
1830 {
1831 struct mwl8k_cmd_set_slot *cmd;
1832 int rc;
1833
1834 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1835 if (cmd == NULL)
1836 return -ENOMEM;
1837
1838 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
1839 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1840 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1841 cmd->short_slot = short_slot_time;
1842
1843 rc = mwl8k_post_cmd(hw, &cmd->header);
1844 kfree(cmd);
1845
1846 return rc;
1847 }
1848
1849 /*
1850 * CMD_MIMO_CONFIG.
1851 */
1852 struct mwl8k_cmd_mimo_config {
1853 struct mwl8k_cmd_pkt header;
1854 __le32 action;
1855 __u8 rx_antenna_map;
1856 __u8 tx_antenna_map;
1857 } __attribute__((packed));
1858
1859 static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
1860 {
1861 struct mwl8k_cmd_mimo_config *cmd;
1862 int rc;
1863
1864 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1865 if (cmd == NULL)
1866 return -ENOMEM;
1867
1868 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
1869 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1870 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
1871 cmd->rx_antenna_map = rx;
1872 cmd->tx_antenna_map = tx;
1873
1874 rc = mwl8k_post_cmd(hw, &cmd->header);
1875 kfree(cmd);
1876
1877 return rc;
1878 }
1879
1880 /*
1881 * CMD_ENABLE_SNIFFER.
1882 */
1883 struct mwl8k_cmd_enable_sniffer {
1884 struct mwl8k_cmd_pkt header;
1885 __le32 action;
1886 } __attribute__((packed));
1887
1888 static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
1889 {
1890 struct mwl8k_cmd_enable_sniffer *cmd;
1891 int rc;
1892
1893 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1894 if (cmd == NULL)
1895 return -ENOMEM;
1896
1897 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
1898 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1899 cmd->action = cpu_to_le32(!!enable);
1900
1901 rc = mwl8k_post_cmd(hw, &cmd->header);
1902 kfree(cmd);
1903
1904 return rc;
1905 }
1906
1907 /*
1908 * CMD_SET_RATEADAPT_MODE.
1909 */
1910 struct mwl8k_cmd_set_rate_adapt_mode {
1911 struct mwl8k_cmd_pkt header;
1912 __le16 action;
1913 __le16 mode;
1914 } __attribute__((packed));
1915
1916 static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
1917 {
1918 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
1919 int rc;
1920
1921 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1922 if (cmd == NULL)
1923 return -ENOMEM;
1924
1925 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
1926 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1927 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1928 cmd->mode = cpu_to_le16(mode);
1929
1930 rc = mwl8k_post_cmd(hw, &cmd->header);
1931 kfree(cmd);
1932
1933 return rc;
1934 }
1935
1936 /*
1937 * CMD_SET_WMM_MODE.
1938 */
1939 struct mwl8k_cmd_set_wmm {
1940 struct mwl8k_cmd_pkt header;
1941 __le16 action;
1942 } __attribute__((packed));
1943
1944 static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
1945 {
1946 struct mwl8k_priv *priv = hw->priv;
1947 struct mwl8k_cmd_set_wmm *cmd;
1948 int rc;
1949
1950 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1951 if (cmd == NULL)
1952 return -ENOMEM;
1953
1954 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
1955 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1956 cmd->action = cpu_to_le16(!!enable);
1957
1958 rc = mwl8k_post_cmd(hw, &cmd->header);
1959 kfree(cmd);
1960
1961 if (!rc)
1962 priv->wmm_enabled = enable;
1963
1964 return rc;
1965 }
1966
1967 /*
1968 * CMD_SET_RTS_THRESHOLD.
1969 */
1970 struct mwl8k_cmd_rts_threshold {
1971 struct mwl8k_cmd_pkt header;
1972 __le16 action;
1973 __le16 threshold;
1974 } __attribute__((packed));
1975
1976 static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
1977 u16 action, u16 threshold)
1978 {
1979 struct mwl8k_cmd_rts_threshold *cmd;
1980 int rc;
1981
1982 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1983 if (cmd == NULL)
1984 return -ENOMEM;
1985
1986 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
1987 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1988 cmd->action = cpu_to_le16(action);
1989 cmd->threshold = cpu_to_le16(threshold);
1990
1991 rc = mwl8k_post_cmd(hw, &cmd->header);
1992 kfree(cmd);
1993
1994 return rc;
1995 }
1996
1997 /*
1998 * CMD_SET_EDCA_PARAMS.
1999 */
2000 struct mwl8k_cmd_set_edca_params {
2001 struct mwl8k_cmd_pkt header;
2002
2003 /* See MWL8K_SET_EDCA_XXX below */
2004 __le16 action;
2005
2006 /* TX opportunity in units of 32 us */
2007 __le16 txop;
2008
2009 /* Log exponent of max contention period: 0...15*/
2010 __u8 log_cw_max;
2011
2012 /* Log exponent of min contention period: 0...15 */
2013 __u8 log_cw_min;
2014
2015 /* Adaptive interframe spacing in units of 32us */
2016 __u8 aifs;
2017
2018 /* TX queue to configure */
2019 __u8 txq;
2020 } __attribute__((packed));
2021
2022 #define MWL8K_SET_EDCA_CW 0x01
2023 #define MWL8K_SET_EDCA_TXOP 0x02
2024 #define MWL8K_SET_EDCA_AIFS 0x04
2025
2026 #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2027 MWL8K_SET_EDCA_TXOP | \
2028 MWL8K_SET_EDCA_AIFS)
2029
2030 static int
2031 mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2032 __u16 cw_min, __u16 cw_max,
2033 __u8 aifs, __u16 txop)
2034 {
2035 struct mwl8k_cmd_set_edca_params *cmd;
2036 int rc;
2037
2038 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2039 if (cmd == NULL)
2040 return -ENOMEM;
2041
2042 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2043 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2044 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2045 cmd->txop = cpu_to_le16(txop);
2046 cmd->log_cw_max = (u8)ilog2(cw_max + 1);
2047 cmd->log_cw_min = (u8)ilog2(cw_min + 1);
2048 cmd->aifs = aifs;
2049 cmd->txq = qnum;
2050
2051 rc = mwl8k_post_cmd(hw, &cmd->header);
2052 kfree(cmd);
2053
2054 return rc;
2055 }
2056
2057 /*
2058 * CMD_FINALIZE_JOIN.
2059 */
2060
2061 /* FJ beacon buffer size is compiled into the firmware. */
2062 #define MWL8K_FJ_BEACON_MAXLEN 128
2063
2064 struct mwl8k_cmd_finalize_join {
2065 struct mwl8k_cmd_pkt header;
2066 __le32 sleep_interval; /* Number of beacon periods to sleep */
2067 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2068 } __attribute__((packed));
2069
2070 static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2071 __u16 framelen, __u16 dtim)
2072 {
2073 struct mwl8k_cmd_finalize_join *cmd;
2074 struct ieee80211_mgmt *payload = frame;
2075 u16 hdrlen;
2076 u32 payload_len;
2077 int rc;
2078
2079 if (frame == NULL)
2080 return -EINVAL;
2081
2082 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2083 if (cmd == NULL)
2084 return -ENOMEM;
2085
2086 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2087 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2088 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2089
2090 hdrlen = ieee80211_hdrlen(payload->frame_control);
2091
2092 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2093
2094 /* XXX TBD Might just have to abort and return an error */
2095 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2096 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
2097 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2098 payload_len, MWL8K_FJ_BEACON_MAXLEN);
2099
2100 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2101 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2102
2103 if (payload && payload_len)
2104 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2105
2106 rc = mwl8k_post_cmd(hw, &cmd->header);
2107 kfree(cmd);
2108 return rc;
2109 }
2110
2111 /*
2112 * CMD_UPDATE_STADB.
2113 */
2114 struct mwl8k_cmd_update_sta_db {
2115 struct mwl8k_cmd_pkt header;
2116
2117 /* See STADB_ACTION_TYPE */
2118 __le32 action;
2119
2120 /* Peer MAC address */
2121 __u8 peer_addr[ETH_ALEN];
2122
2123 __le32 reserved;
2124
2125 /* Peer info - valid during add/update. */
2126 struct peer_capability_info peer_info;
2127 } __attribute__((packed));
2128
2129 static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2130 struct ieee80211_vif *vif, __u32 action)
2131 {
2132 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2133 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2134 struct mwl8k_cmd_update_sta_db *cmd;
2135 struct peer_capability_info *peer_info;
2136 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2137 int rc;
2138 __u8 count, *rates;
2139
2140 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2141 if (cmd == NULL)
2142 return -ENOMEM;
2143
2144 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2145 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2146
2147 cmd->action = cpu_to_le32(action);
2148 peer_info = &cmd->peer_info;
2149 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
2150
2151 switch (action) {
2152 case MWL8K_STA_DB_ADD_ENTRY:
2153 case MWL8K_STA_DB_MODIFY_ENTRY:
2154 /* Build peer_info block */
2155 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2156 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2157 peer_info->interop = 1;
2158 peer_info->amsdu_enabled = 0;
2159
2160 rates = peer_info->legacy_rates;
2161 for (count = 0; count < mv_vif->legacy_nrates; count++)
2162 rates[count] = bitrates[count].hw_value;
2163
2164 rc = mwl8k_post_cmd(hw, &cmd->header);
2165 if (rc == 0)
2166 mv_vif->peer_id = peer_info->station_id;
2167
2168 break;
2169
2170 case MWL8K_STA_DB_DEL_ENTRY:
2171 case MWL8K_STA_DB_FLUSH:
2172 default:
2173 rc = mwl8k_post_cmd(hw, &cmd->header);
2174 if (rc == 0)
2175 mv_vif->peer_id = 0;
2176 break;
2177 }
2178 kfree(cmd);
2179
2180 return rc;
2181 }
2182
2183 /*
2184 * CMD_SET_AID.
2185 */
2186 #define MWL8K_RATE_INDEX_MAX_ARRAY 14
2187
2188 #define MWL8K_FRAME_PROT_DISABLED 0x00
2189 #define MWL8K_FRAME_PROT_11G 0x07
2190 #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2191 #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
2192
2193 struct mwl8k_cmd_update_set_aid {
2194 struct mwl8k_cmd_pkt header;
2195 __le16 aid;
2196
2197 /* AP's MAC address (BSSID) */
2198 __u8 bssid[ETH_ALEN];
2199 __le16 protection_mode;
2200 __u8 supp_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2201 } __attribute__((packed));
2202
2203 static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2204 struct ieee80211_vif *vif)
2205 {
2206 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2207 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2208 struct mwl8k_cmd_update_set_aid *cmd;
2209 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2210 int count;
2211 u16 prot_mode;
2212 int rc;
2213
2214 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2215 if (cmd == NULL)
2216 return -ENOMEM;
2217
2218 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2219 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2220 cmd->aid = cpu_to_le16(info->aid);
2221
2222 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
2223
2224 if (info->use_cts_prot) {
2225 prot_mode = MWL8K_FRAME_PROT_11G;
2226 } else {
2227 switch (info->ht_operation_mode &
2228 IEEE80211_HT_OP_MODE_PROTECTION) {
2229 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2230 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2231 break;
2232 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2233 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2234 break;
2235 default:
2236 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2237 break;
2238 }
2239 }
2240 cmd->protection_mode = cpu_to_le16(prot_mode);
2241
2242 for (count = 0; count < mv_vif->legacy_nrates; count++)
2243 cmd->supp_rates[count] = bitrates[count].hw_value;
2244
2245 rc = mwl8k_post_cmd(hw, &cmd->header);
2246 kfree(cmd);
2247
2248 return rc;
2249 }
2250
2251 /*
2252 * CMD_SET_RATE.
2253 */
2254 struct mwl8k_cmd_update_rateset {
2255 struct mwl8k_cmd_pkt header;
2256 __u8 legacy_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2257
2258 /* Bitmap for supported MCS codes. */
2259 __u8 mcs_set[MWL8K_IEEE_LEGACY_DATA_RATES];
2260 __u8 reserved[MWL8K_IEEE_LEGACY_DATA_RATES];
2261 } __attribute__((packed));
2262
2263 static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2264 struct ieee80211_vif *vif)
2265 {
2266 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2267 struct mwl8k_cmd_update_rateset *cmd;
2268 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2269 int count;
2270 int rc;
2271
2272 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2273 if (cmd == NULL)
2274 return -ENOMEM;
2275
2276 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2277 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2278
2279 for (count = 0; count < mv_vif->legacy_nrates; count++)
2280 cmd->legacy_rates[count] = bitrates[count].hw_value;
2281
2282 rc = mwl8k_post_cmd(hw, &cmd->header);
2283 kfree(cmd);
2284
2285 return rc;
2286 }
2287
2288 /*
2289 * CMD_USE_FIXED_RATE.
2290 */
2291 #define MWL8K_RATE_TABLE_SIZE 8
2292 #define MWL8K_UCAST_RATE 0
2293 #define MWL8K_USE_AUTO_RATE 0x0002
2294
2295 struct mwl8k_rate_entry {
2296 /* Set to 1 if HT rate, 0 if legacy. */
2297 __le32 is_ht_rate;
2298
2299 /* Set to 1 to use retry_count field. */
2300 __le32 enable_retry;
2301
2302 /* Specified legacy rate or MCS. */
2303 __le32 rate;
2304
2305 /* Number of allowed retries. */
2306 __le32 retry_count;
2307 } __attribute__((packed));
2308
2309 struct mwl8k_rate_table {
2310 /* 1 to allow specified rate and below */
2311 __le32 allow_rate_drop;
2312 __le32 num_rates;
2313 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2314 } __attribute__((packed));
2315
2316 struct mwl8k_cmd_use_fixed_rate {
2317 struct mwl8k_cmd_pkt header;
2318 __le32 action;
2319 struct mwl8k_rate_table rate_table;
2320
2321 /* Unicast, Broadcast or Multicast */
2322 __le32 rate_type;
2323 __le32 reserved1;
2324 __le32 reserved2;
2325 } __attribute__((packed));
2326
2327 static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2328 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2329 {
2330 struct mwl8k_cmd_use_fixed_rate *cmd;
2331 int count;
2332 int rc;
2333
2334 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2335 if (cmd == NULL)
2336 return -ENOMEM;
2337
2338 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2339 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2340
2341 cmd->action = cpu_to_le32(action);
2342 cmd->rate_type = cpu_to_le32(rate_type);
2343
2344 if (rate_table != NULL) {
2345 /*
2346 * Copy over each field manually so that endian
2347 * conversion can be done.
2348 */
2349 cmd->rate_table.allow_rate_drop =
2350 cpu_to_le32(rate_table->allow_rate_drop);
2351 cmd->rate_table.num_rates =
2352 cpu_to_le32(rate_table->num_rates);
2353
2354 for (count = 0; count < rate_table->num_rates; count++) {
2355 struct mwl8k_rate_entry *dst =
2356 &cmd->rate_table.rate_entry[count];
2357 struct mwl8k_rate_entry *src =
2358 &rate_table->rate_entry[count];
2359
2360 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2361 dst->enable_retry = cpu_to_le32(src->enable_retry);
2362 dst->rate = cpu_to_le32(src->rate);
2363 dst->retry_count = cpu_to_le32(src->retry_count);
2364 }
2365 }
2366
2367 rc = mwl8k_post_cmd(hw, &cmd->header);
2368 kfree(cmd);
2369
2370 return rc;
2371 }
2372
2373
2374 /*
2375 * Interrupt handling.
2376 */
2377 static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2378 {
2379 struct ieee80211_hw *hw = dev_id;
2380 struct mwl8k_priv *priv = hw->priv;
2381 u32 status;
2382
2383 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2384 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2385
2386 if (!status)
2387 return IRQ_NONE;
2388
2389 if (status & MWL8K_A2H_INT_TX_DONE)
2390 tasklet_schedule(&priv->tx_reclaim_task);
2391
2392 if (status & MWL8K_A2H_INT_RX_READY) {
2393 while (rxq_process(hw, 0, 1))
2394 rxq_refill(hw, 0, 1);
2395 }
2396
2397 if (status & MWL8K_A2H_INT_OPC_DONE) {
2398 if (priv->hostcmd_wait != NULL)
2399 complete(priv->hostcmd_wait);
2400 }
2401
2402 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
2403 if (!mutex_is_locked(&priv->fw_mutex) &&
2404 priv->radio_on && priv->pending_tx_pkts)
2405 mwl8k_tx_start(priv);
2406 }
2407
2408 return IRQ_HANDLED;
2409 }
2410
2411
2412 /*
2413 * Core driver operations.
2414 */
2415 static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2416 {
2417 struct mwl8k_priv *priv = hw->priv;
2418 int index = skb_get_queue_mapping(skb);
2419 int rc;
2420
2421 if (priv->current_channel == NULL) {
2422 printk(KERN_DEBUG "%s: dropped TX frame since radio "
2423 "disabled\n", wiphy_name(hw->wiphy));
2424 dev_kfree_skb(skb);
2425 return NETDEV_TX_OK;
2426 }
2427
2428 rc = mwl8k_txq_xmit(hw, index, skb);
2429
2430 return rc;
2431 }
2432
2433 static int mwl8k_start(struct ieee80211_hw *hw)
2434 {
2435 struct mwl8k_priv *priv = hw->priv;
2436 int rc;
2437
2438 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
2439 IRQF_SHARED, MWL8K_NAME, hw);
2440 if (rc) {
2441 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2442 wiphy_name(hw->wiphy));
2443 return -EIO;
2444 }
2445
2446 /* Enable tx reclaim tasklet */
2447 tasklet_enable(&priv->tx_reclaim_task);
2448
2449 /* Enable interrupts */
2450 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2451
2452 rc = mwl8k_fw_lock(hw);
2453 if (!rc) {
2454 rc = mwl8k_cmd_802_11_radio_enable(hw);
2455
2456 if (!rc)
2457 rc = mwl8k_cmd_set_pre_scan(hw);
2458
2459 if (!rc)
2460 rc = mwl8k_cmd_set_post_scan(hw,
2461 "\x00\x00\x00\x00\x00\x00");
2462
2463 if (!rc)
2464 rc = mwl8k_cmd_setrateadaptmode(hw, 0);
2465
2466 if (!rc)
2467 rc = mwl8k_set_wmm(hw, 0);
2468
2469 if (!rc)
2470 rc = mwl8k_enable_sniffer(hw, 0);
2471
2472 mwl8k_fw_unlock(hw);
2473 }
2474
2475 if (rc) {
2476 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2477 free_irq(priv->pdev->irq, hw);
2478 tasklet_disable(&priv->tx_reclaim_task);
2479 }
2480
2481 return rc;
2482 }
2483
2484 static void mwl8k_stop(struct ieee80211_hw *hw)
2485 {
2486 struct mwl8k_priv *priv = hw->priv;
2487 int i;
2488
2489 mwl8k_cmd_802_11_radio_disable(hw);
2490
2491 ieee80211_stop_queues(hw);
2492
2493 /* Disable interrupts */
2494 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2495 free_irq(priv->pdev->irq, hw);
2496
2497 /* Stop finalize join worker */
2498 cancel_work_sync(&priv->finalize_join_worker);
2499 if (priv->beacon_skb != NULL)
2500 dev_kfree_skb(priv->beacon_skb);
2501
2502 /* Stop tx reclaim tasklet */
2503 tasklet_disable(&priv->tx_reclaim_task);
2504
2505 /* Return all skbs to mac80211 */
2506 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2507 mwl8k_txq_reclaim(hw, i, 1);
2508 }
2509
2510 static int mwl8k_add_interface(struct ieee80211_hw *hw,
2511 struct ieee80211_if_init_conf *conf)
2512 {
2513 struct mwl8k_priv *priv = hw->priv;
2514 struct mwl8k_vif *mwl8k_vif;
2515
2516 /*
2517 * We only support one active interface at a time.
2518 */
2519 if (priv->vif != NULL)
2520 return -EBUSY;
2521
2522 /*
2523 * We only support managed interfaces for now.
2524 */
2525 if (conf->type != NL80211_IFTYPE_STATION)
2526 return -EINVAL;
2527
2528 /* Clean out driver private area */
2529 mwl8k_vif = MWL8K_VIF(conf->vif);
2530 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2531
2532 /* Save the mac address */
2533 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
2534
2535 /* Back pointer to parent config block */
2536 mwl8k_vif->priv = priv;
2537
2538 /* Setup initial PHY parameters */
2539 memcpy(mwl8k_vif->legacy_rates,
2540 priv->rates, sizeof(mwl8k_vif->legacy_rates));
2541 mwl8k_vif->legacy_nrates = ARRAY_SIZE(priv->rates);
2542
2543 /* Set Initial sequence number to zero */
2544 mwl8k_vif->seqno = 0;
2545
2546 priv->vif = conf->vif;
2547 priv->current_channel = NULL;
2548
2549 return 0;
2550 }
2551
2552 static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2553 struct ieee80211_if_init_conf *conf)
2554 {
2555 struct mwl8k_priv *priv = hw->priv;
2556
2557 if (priv->vif == NULL)
2558 return;
2559
2560 priv->vif = NULL;
2561 }
2562
2563 static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
2564 {
2565 struct ieee80211_conf *conf = &hw->conf;
2566 struct mwl8k_priv *priv = hw->priv;
2567 int rc;
2568
2569 if (conf->flags & IEEE80211_CONF_IDLE) {
2570 mwl8k_cmd_802_11_radio_disable(hw);
2571 priv->current_channel = NULL;
2572 return 0;
2573 }
2574
2575 rc = mwl8k_fw_lock(hw);
2576 if (rc)
2577 return rc;
2578
2579 rc = mwl8k_cmd_802_11_radio_enable(hw);
2580 if (rc)
2581 goto out;
2582
2583 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2584 if (rc)
2585 goto out;
2586
2587 priv->current_channel = conf->channel;
2588
2589 if (conf->power_level > 18)
2590 conf->power_level = 18;
2591 rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level);
2592 if (rc)
2593 goto out;
2594
2595 if (mwl8k_cmd_mimo_config(hw, 0x7, 0x7))
2596 rc = -EINVAL;
2597
2598 out:
2599 mwl8k_fw_unlock(hw);
2600
2601 return rc;
2602 }
2603
2604 static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
2605 struct ieee80211_vif *vif,
2606 struct ieee80211_bss_conf *info,
2607 u32 changed)
2608 {
2609 struct mwl8k_priv *priv = hw->priv;
2610 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
2611 int rc;
2612
2613 if (changed & BSS_CHANGED_BSSID)
2614 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
2615
2616 if ((changed & BSS_CHANGED_ASSOC) == 0)
2617 return;
2618
2619 priv->capture_beacon = false;
2620
2621 rc = mwl8k_fw_lock(hw);
2622 if (rc)
2623 return;
2624
2625 if (info->assoc) {
2626 memcpy(&mwl8k_vif->bss_info, info,
2627 sizeof(struct ieee80211_bss_conf));
2628
2629 /* Install rates */
2630 rc = mwl8k_update_rateset(hw, vif);
2631 if (rc)
2632 goto out;
2633
2634 /* Turn on rate adaptation */
2635 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
2636 MWL8K_UCAST_RATE, NULL);
2637 if (rc)
2638 goto out;
2639
2640 /* Set radio preamble */
2641 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
2642 if (rc)
2643 goto out;
2644
2645 /* Set slot time */
2646 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
2647 if (rc)
2648 goto out;
2649
2650 /* Update peer rate info */
2651 rc = mwl8k_cmd_update_sta_db(hw, vif,
2652 MWL8K_STA_DB_MODIFY_ENTRY);
2653 if (rc)
2654 goto out;
2655
2656 /* Set AID */
2657 rc = mwl8k_cmd_set_aid(hw, vif);
2658 if (rc)
2659 goto out;
2660
2661 /*
2662 * Finalize the join. Tell rx handler to process
2663 * next beacon from our BSSID.
2664 */
2665 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
2666 priv->capture_beacon = true;
2667 } else {
2668 rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
2669 memset(&mwl8k_vif->bss_info, 0,
2670 sizeof(struct ieee80211_bss_conf));
2671 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
2672 }
2673
2674 out:
2675 mwl8k_fw_unlock(hw);
2676 }
2677
2678 static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
2679 int mc_count, struct dev_addr_list *mclist)
2680 {
2681 struct mwl8k_cmd_pkt *cmd;
2682
2683 cmd = __mwl8k_cmd_mac_multicast_adr(hw, mc_count, mclist);
2684
2685 return (unsigned long)cmd;
2686 }
2687
2688 static void mwl8k_configure_filter(struct ieee80211_hw *hw,
2689 unsigned int changed_flags,
2690 unsigned int *total_flags,
2691 u64 multicast)
2692 {
2693 struct mwl8k_priv *priv = hw->priv;
2694 struct mwl8k_cmd_pkt *multicast_adr_cmd;
2695
2696 /* Clear unsupported feature flags */
2697 *total_flags &= FIF_BCN_PRBRESP_PROMISC;
2698
2699 if (mwl8k_fw_lock(hw))
2700 return;
2701
2702 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2703 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2704 mwl8k_cmd_set_pre_scan(hw);
2705 else {
2706 u8 *bssid;
2707
2708 bssid = "\x00\x00\x00\x00\x00\x00";
2709 if (priv->vif != NULL)
2710 bssid = MWL8K_VIF(priv->vif)->bssid;
2711
2712 mwl8k_cmd_set_post_scan(hw, bssid);
2713 }
2714 }
2715
2716 multicast_adr_cmd = (void *)(unsigned long)multicast;
2717 if (multicast_adr_cmd != NULL) {
2718 mwl8k_post_cmd(hw, multicast_adr_cmd);
2719 kfree(multicast_adr_cmd);
2720 }
2721
2722 mwl8k_fw_unlock(hw);
2723 }
2724
2725 static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2726 {
2727 return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value);
2728 }
2729
2730 static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2731 const struct ieee80211_tx_queue_params *params)
2732 {
2733 struct mwl8k_priv *priv = hw->priv;
2734 int rc;
2735
2736 rc = mwl8k_fw_lock(hw);
2737 if (!rc) {
2738 if (!priv->wmm_enabled)
2739 rc = mwl8k_set_wmm(hw, 1);
2740
2741 if (!rc)
2742 rc = mwl8k_set_edca_params(hw, queue,
2743 params->cw_min,
2744 params->cw_max,
2745 params->aifs,
2746 params->txop);
2747
2748 mwl8k_fw_unlock(hw);
2749 }
2750
2751 return rc;
2752 }
2753
2754 static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
2755 struct ieee80211_tx_queue_stats *stats)
2756 {
2757 struct mwl8k_priv *priv = hw->priv;
2758 struct mwl8k_tx_queue *txq;
2759 int index;
2760
2761 spin_lock_bh(&priv->tx_lock);
2762 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
2763 txq = priv->txq + index;
2764 memcpy(&stats[index], &txq->tx_stats,
2765 sizeof(struct ieee80211_tx_queue_stats));
2766 }
2767 spin_unlock_bh(&priv->tx_lock);
2768
2769 return 0;
2770 }
2771
2772 static int mwl8k_get_stats(struct ieee80211_hw *hw,
2773 struct ieee80211_low_level_stats *stats)
2774 {
2775 return mwl8k_cmd_802_11_get_stat(hw, stats);
2776 }
2777
2778 static const struct ieee80211_ops mwl8k_ops = {
2779 .tx = mwl8k_tx,
2780 .start = mwl8k_start,
2781 .stop = mwl8k_stop,
2782 .add_interface = mwl8k_add_interface,
2783 .remove_interface = mwl8k_remove_interface,
2784 .config = mwl8k_config,
2785 .bss_info_changed = mwl8k_bss_info_changed,
2786 .prepare_multicast = mwl8k_prepare_multicast,
2787 .configure_filter = mwl8k_configure_filter,
2788 .set_rts_threshold = mwl8k_set_rts_threshold,
2789 .conf_tx = mwl8k_conf_tx,
2790 .get_tx_stats = mwl8k_get_tx_stats,
2791 .get_stats = mwl8k_get_stats,
2792 };
2793
2794 static void mwl8k_tx_reclaim_handler(unsigned long data)
2795 {
2796 int i;
2797 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
2798 struct mwl8k_priv *priv = hw->priv;
2799
2800 spin_lock_bh(&priv->tx_lock);
2801 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2802 mwl8k_txq_reclaim(hw, i, 0);
2803
2804 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
2805 complete(priv->tx_wait);
2806 priv->tx_wait = NULL;
2807 }
2808 spin_unlock_bh(&priv->tx_lock);
2809 }
2810
2811 static void mwl8k_finalize_join_worker(struct work_struct *work)
2812 {
2813 struct mwl8k_priv *priv =
2814 container_of(work, struct mwl8k_priv, finalize_join_worker);
2815 struct sk_buff *skb = priv->beacon_skb;
2816 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
2817
2818 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
2819 dev_kfree_skb(skb);
2820
2821 priv->beacon_skb = NULL;
2822 }
2823
2824 static int __devinit mwl8k_probe(struct pci_dev *pdev,
2825 const struct pci_device_id *id)
2826 {
2827 static int printed_version = 0;
2828 struct ieee80211_hw *hw;
2829 struct mwl8k_priv *priv;
2830 int rc;
2831 int i;
2832
2833 if (!printed_version) {
2834 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
2835 printed_version = 1;
2836 }
2837
2838 rc = pci_enable_device(pdev);
2839 if (rc) {
2840 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
2841 MWL8K_NAME);
2842 return rc;
2843 }
2844
2845 rc = pci_request_regions(pdev, MWL8K_NAME);
2846 if (rc) {
2847 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
2848 MWL8K_NAME);
2849 return rc;
2850 }
2851
2852 pci_set_master(pdev);
2853
2854 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
2855 if (hw == NULL) {
2856 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
2857 rc = -ENOMEM;
2858 goto err_free_reg;
2859 }
2860
2861 priv = hw->priv;
2862 priv->hw = hw;
2863 priv->pdev = pdev;
2864 priv->wmm_enabled = false;
2865 priv->pending_tx_pkts = 0;
2866
2867 SET_IEEE80211_DEV(hw, &pdev->dev);
2868 pci_set_drvdata(pdev, hw);
2869
2870 priv->regs = pci_iomap(pdev, 1, 0x10000);
2871 if (priv->regs == NULL) {
2872 printk(KERN_ERR "%s: Cannot map device memory\n",
2873 wiphy_name(hw->wiphy));
2874 goto err_iounmap;
2875 }
2876
2877 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
2878 priv->band.band = IEEE80211_BAND_2GHZ;
2879 priv->band.channels = priv->channels;
2880 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
2881 priv->band.bitrates = priv->rates;
2882 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
2883 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
2884
2885 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
2886 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
2887
2888 /*
2889 * Extra headroom is the size of the required DMA header
2890 * minus the size of the smallest 802.11 frame (CTS frame).
2891 */
2892 hw->extra_tx_headroom =
2893 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
2894
2895 hw->channel_change_time = 10;
2896
2897 hw->queues = MWL8K_TX_QUEUES;
2898
2899 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
2900
2901 /* Set rssi and noise values to dBm */
2902 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
2903 hw->vif_data_size = sizeof(struct mwl8k_vif);
2904 priv->vif = NULL;
2905
2906 /* Set default radio state and preamble */
2907 priv->radio_on = 0;
2908 priv->radio_short_preamble = 0;
2909
2910 /* Finalize join worker */
2911 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
2912
2913 /* TX reclaim tasklet */
2914 tasklet_init(&priv->tx_reclaim_task,
2915 mwl8k_tx_reclaim_handler, (unsigned long)hw);
2916 tasklet_disable(&priv->tx_reclaim_task);
2917
2918 /* Power management cookie */
2919 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
2920 if (priv->cookie == NULL)
2921 goto err_iounmap;
2922
2923 rc = mwl8k_rxq_init(hw, 0);
2924 if (rc)
2925 goto err_iounmap;
2926 rxq_refill(hw, 0, INT_MAX);
2927
2928 mutex_init(&priv->fw_mutex);
2929 priv->fw_mutex_owner = NULL;
2930 priv->fw_mutex_depth = 0;
2931 priv->hostcmd_wait = NULL;
2932
2933 spin_lock_init(&priv->tx_lock);
2934
2935 priv->tx_wait = NULL;
2936
2937 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
2938 rc = mwl8k_txq_init(hw, i);
2939 if (rc)
2940 goto err_free_queues;
2941 }
2942
2943 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2944 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2945 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
2946 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
2947
2948 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
2949 IRQF_SHARED, MWL8K_NAME, hw);
2950 if (rc) {
2951 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2952 wiphy_name(hw->wiphy));
2953 goto err_free_queues;
2954 }
2955
2956 /* Reset firmware and hardware */
2957 mwl8k_hw_reset(priv);
2958
2959 /* Ask userland hotplug daemon for the device firmware */
2960 rc = mwl8k_request_firmware(priv, (u32)id->driver_data);
2961 if (rc) {
2962 printk(KERN_ERR "%s: Firmware files not found\n",
2963 wiphy_name(hw->wiphy));
2964 goto err_free_irq;
2965 }
2966
2967 /* Load firmware into hardware */
2968 rc = mwl8k_load_firmware(hw);
2969 if (rc) {
2970 printk(KERN_ERR "%s: Cannot start firmware\n",
2971 wiphy_name(hw->wiphy));
2972 goto err_stop_firmware;
2973 }
2974
2975 /* Reclaim memory once firmware is successfully loaded */
2976 mwl8k_release_firmware(priv);
2977
2978 /*
2979 * Temporarily enable interrupts. Initial firmware host
2980 * commands use interrupts and avoids polling. Disable
2981 * interrupts when done.
2982 */
2983 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2984
2985 /* Get config data, mac addrs etc */
2986 rc = mwl8k_cmd_get_hw_spec(hw);
2987 if (rc) {
2988 printk(KERN_ERR "%s: Cannot initialise firmware\n",
2989 wiphy_name(hw->wiphy));
2990 goto err_stop_firmware;
2991 }
2992
2993 /* Turn radio off */
2994 rc = mwl8k_cmd_802_11_radio_disable(hw);
2995 if (rc) {
2996 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
2997 goto err_stop_firmware;
2998 }
2999
3000 /* Disable interrupts */
3001 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3002 free_irq(priv->pdev->irq, hw);
3003
3004 rc = ieee80211_register_hw(hw);
3005 if (rc) {
3006 printk(KERN_ERR "%s: Cannot register device\n",
3007 wiphy_name(hw->wiphy));
3008 goto err_stop_firmware;
3009 }
3010
3011 printk(KERN_INFO "%s: 88w%u v%d, %pM, firmware version %u.%u.%u.%u\n",
3012 wiphy_name(hw->wiphy), priv->part_num, priv->hw_rev,
3013 hw->wiphy->perm_addr,
3014 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3015 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
3016
3017 return 0;
3018
3019 err_stop_firmware:
3020 mwl8k_hw_reset(priv);
3021 mwl8k_release_firmware(priv);
3022
3023 err_free_irq:
3024 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3025 free_irq(priv->pdev->irq, hw);
3026
3027 err_free_queues:
3028 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3029 mwl8k_txq_deinit(hw, i);
3030 mwl8k_rxq_deinit(hw, 0);
3031
3032 err_iounmap:
3033 if (priv->cookie != NULL)
3034 pci_free_consistent(priv->pdev, 4,
3035 priv->cookie, priv->cookie_dma);
3036
3037 if (priv->regs != NULL)
3038 pci_iounmap(pdev, priv->regs);
3039
3040 pci_set_drvdata(pdev, NULL);
3041 ieee80211_free_hw(hw);
3042
3043 err_free_reg:
3044 pci_release_regions(pdev);
3045 pci_disable_device(pdev);
3046
3047 return rc;
3048 }
3049
3050 static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
3051 {
3052 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3053 }
3054
3055 static void __devexit mwl8k_remove(struct pci_dev *pdev)
3056 {
3057 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3058 struct mwl8k_priv *priv;
3059 int i;
3060
3061 if (hw == NULL)
3062 return;
3063 priv = hw->priv;
3064
3065 ieee80211_stop_queues(hw);
3066
3067 ieee80211_unregister_hw(hw);
3068
3069 /* Remove tx reclaim tasklet */
3070 tasklet_kill(&priv->tx_reclaim_task);
3071
3072 /* Stop hardware */
3073 mwl8k_hw_reset(priv);
3074
3075 /* Return all skbs to mac80211 */
3076 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3077 mwl8k_txq_reclaim(hw, i, 1);
3078
3079 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3080 mwl8k_txq_deinit(hw, i);
3081
3082 mwl8k_rxq_deinit(hw, 0);
3083
3084 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
3085
3086 pci_iounmap(pdev, priv->regs);
3087 pci_set_drvdata(pdev, NULL);
3088 ieee80211_free_hw(hw);
3089 pci_release_regions(pdev);
3090 pci_disable_device(pdev);
3091 }
3092
3093 static struct pci_driver mwl8k_driver = {
3094 .name = MWL8K_NAME,
3095 .id_table = mwl8k_table,
3096 .probe = mwl8k_probe,
3097 .remove = __devexit_p(mwl8k_remove),
3098 .shutdown = __devexit_p(mwl8k_shutdown),
3099 };
3100
3101 static int __init mwl8k_init(void)
3102 {
3103 return pci_register_driver(&mwl8k_driver);
3104 }
3105
3106 static void __exit mwl8k_exit(void)
3107 {
3108 pci_unregister_driver(&mwl8k_driver);
3109 }
3110
3111 module_init(mwl8k_init);
3112 module_exit(mwl8k_exit);
3113
3114 MODULE_DESCRIPTION(MWL8K_DESC);
3115 MODULE_VERSION(MWL8K_VERSION);
3116 MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3117 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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