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mwl8k: change pci id table driver data to a structure pointer
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
1 /*
2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
4 *
5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/sched.h>
16 #include <linux/spinlock.h>
17 #include <linux/list.h>
18 #include <linux/pci.h>
19 #include <linux/delay.h>
20 #include <linux/completion.h>
21 #include <linux/etherdevice.h>
22 #include <net/mac80211.h>
23 #include <linux/moduleparam.h>
24 #include <linux/firmware.h>
25 #include <linux/workqueue.h>
26
27 #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28 #define MWL8K_NAME KBUILD_MODNAME
29 #define MWL8K_VERSION "0.10"
30
31 /* Register definitions */
32 #define MWL8K_HIU_GEN_PTR 0x00000c10
33 #define MWL8K_MODE_STA 0x0000005a
34 #define MWL8K_MODE_AP 0x000000a5
35 #define MWL8K_HIU_INT_CODE 0x00000c14
36 #define MWL8K_FWSTA_READY 0xf0f1f2f4
37 #define MWL8K_FWAP_READY 0xf1f2f4a5
38 #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
39 #define MWL8K_HIU_SCRATCH 0x00000c40
40
41 /* Host->device communications */
42 #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43 #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44 #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45 #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46 #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
47 #define MWL8K_H2A_INT_DUMMY (1 << 20)
48 #define MWL8K_H2A_INT_RESET (1 << 15)
49 #define MWL8K_H2A_INT_DOORBELL (1 << 1)
50 #define MWL8K_H2A_INT_PPA_READY (1 << 0)
51
52 /* Device->host communications */
53 #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54 #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55 #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56 #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57 #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
58 #define MWL8K_A2H_INT_DUMMY (1 << 20)
59 #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60 #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61 #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62 #define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63 #define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64 #define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65 #define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66 #define MWL8K_A2H_INT_RX_READY (1 << 1)
67 #define MWL8K_A2H_INT_TX_DONE (1 << 0)
68
69 #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
79
80 #define MWL8K_RX_QUEUES 1
81 #define MWL8K_TX_QUEUES 4
82
83 struct mwl8k_device_info {
84 int part_num;
85 };
86
87 struct mwl8k_rx_queue {
88 int rxd_count;
89
90 /* hw receives here */
91 int head;
92
93 /* refill descs here */
94 int tail;
95
96 struct mwl8k_rx_desc *rxd;
97 dma_addr_t rxd_dma;
98 struct sk_buff **skb;
99 };
100
101 struct mwl8k_tx_queue {
102 /* hw transmits here */
103 int head;
104
105 /* sw appends here */
106 int tail;
107
108 struct ieee80211_tx_queue_stats stats;
109 struct mwl8k_tx_desc *txd;
110 dma_addr_t txd_dma;
111 struct sk_buff **skb;
112 };
113
114 /* Pointers to the firmware data and meta information about it. */
115 struct mwl8k_firmware {
116 /* Microcode */
117 struct firmware *ucode;
118
119 /* Boot helper code */
120 struct firmware *helper;
121 };
122
123 struct mwl8k_priv {
124 void __iomem *sram;
125 void __iomem *regs;
126 struct ieee80211_hw *hw;
127
128 struct pci_dev *pdev;
129
130 struct mwl8k_device_info *device_info;
131
132 /* firmware files and meta data */
133 struct mwl8k_firmware fw;
134
135 /* firmware access */
136 struct mutex fw_mutex;
137 struct task_struct *fw_mutex_owner;
138 int fw_mutex_depth;
139 struct completion *hostcmd_wait;
140
141 /* lock held over TX and TX reap */
142 spinlock_t tx_lock;
143
144 /* TX quiesce completion, protected by fw_mutex and tx_lock */
145 struct completion *tx_wait;
146
147 struct ieee80211_vif *vif;
148
149 struct ieee80211_channel *current_channel;
150
151 /* power management status cookie from firmware */
152 u32 *cookie;
153 dma_addr_t cookie_dma;
154
155 u16 num_mcaddrs;
156 u8 hw_rev;
157 u32 fw_rev;
158
159 /*
160 * Running count of TX packets in flight, to avoid
161 * iterating over the transmit rings each time.
162 */
163 int pending_tx_pkts;
164
165 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
166 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
167
168 /* PHY parameters */
169 struct ieee80211_supported_band band;
170 struct ieee80211_channel channels[14];
171 struct ieee80211_rate rates[13];
172
173 bool radio_on;
174 bool radio_short_preamble;
175 bool sniffer_enabled;
176 bool wmm_enabled;
177
178 /* XXX need to convert this to handle multiple interfaces */
179 bool capture_beacon;
180 u8 capture_bssid[ETH_ALEN];
181 struct sk_buff *beacon_skb;
182
183 /*
184 * This FJ worker has to be global as it is scheduled from the
185 * RX handler. At this point we don't know which interface it
186 * belongs to until the list of bssids waiting to complete join
187 * is checked.
188 */
189 struct work_struct finalize_join_worker;
190
191 /* Tasklet to reclaim TX descriptors and buffers after tx */
192 struct tasklet_struct tx_reclaim_task;
193 };
194
195 /* Per interface specific private data */
196 struct mwl8k_vif {
197 /* backpointer to parent config block */
198 struct mwl8k_priv *priv;
199
200 /* BSS config of AP or IBSS from mac80211*/
201 struct ieee80211_bss_conf bss_info;
202
203 /* BSSID of AP or IBSS */
204 u8 bssid[ETH_ALEN];
205 u8 mac_addr[ETH_ALEN];
206
207 /*
208 * Subset of supported legacy rates.
209 * Intersection of AP and STA supported rates.
210 */
211 struct ieee80211_rate legacy_rates[13];
212
213 /* number of supported legacy rates */
214 u8 legacy_nrates;
215
216 /* Index into station database.Returned by update_sta_db call */
217 u8 peer_id;
218
219 /* Non AMPDU sequence number assigned by driver */
220 u16 seqno;
221 };
222
223 #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
224
225 static const struct ieee80211_channel mwl8k_channels[] = {
226 { .center_freq = 2412, .hw_value = 1, },
227 { .center_freq = 2417, .hw_value = 2, },
228 { .center_freq = 2422, .hw_value = 3, },
229 { .center_freq = 2427, .hw_value = 4, },
230 { .center_freq = 2432, .hw_value = 5, },
231 { .center_freq = 2437, .hw_value = 6, },
232 { .center_freq = 2442, .hw_value = 7, },
233 { .center_freq = 2447, .hw_value = 8, },
234 { .center_freq = 2452, .hw_value = 9, },
235 { .center_freq = 2457, .hw_value = 10, },
236 { .center_freq = 2462, .hw_value = 11, },
237 };
238
239 static const struct ieee80211_rate mwl8k_rates[] = {
240 { .bitrate = 10, .hw_value = 2, },
241 { .bitrate = 20, .hw_value = 4, },
242 { .bitrate = 55, .hw_value = 11, },
243 { .bitrate = 110, .hw_value = 22, },
244 { .bitrate = 220, .hw_value = 44, },
245 { .bitrate = 60, .hw_value = 12, },
246 { .bitrate = 90, .hw_value = 18, },
247 { .bitrate = 120, .hw_value = 24, },
248 { .bitrate = 180, .hw_value = 36, },
249 { .bitrate = 240, .hw_value = 48, },
250 { .bitrate = 360, .hw_value = 72, },
251 { .bitrate = 480, .hw_value = 96, },
252 { .bitrate = 540, .hw_value = 108, },
253 };
254
255 /* Set or get info from Firmware */
256 #define MWL8K_CMD_SET 0x0001
257 #define MWL8K_CMD_GET 0x0000
258
259 /* Firmware command codes */
260 #define MWL8K_CMD_CODE_DNLD 0x0001
261 #define MWL8K_CMD_GET_HW_SPEC 0x0003
262 #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
263 #define MWL8K_CMD_GET_STAT 0x0014
264 #define MWL8K_CMD_RADIO_CONTROL 0x001c
265 #define MWL8K_CMD_RF_TX_POWER 0x001e
266 #define MWL8K_CMD_SET_PRE_SCAN 0x0107
267 #define MWL8K_CMD_SET_POST_SCAN 0x0108
268 #define MWL8K_CMD_SET_RF_CHANNEL 0x010a
269 #define MWL8K_CMD_SET_AID 0x010d
270 #define MWL8K_CMD_SET_RATE 0x0110
271 #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
272 #define MWL8K_CMD_RTS_THRESHOLD 0x0113
273 #define MWL8K_CMD_SET_SLOT 0x0114
274 #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
275 #define MWL8K_CMD_SET_WMM_MODE 0x0123
276 #define MWL8K_CMD_MIMO_CONFIG 0x0125
277 #define MWL8K_CMD_USE_FIXED_RATE 0x0126
278 #define MWL8K_CMD_ENABLE_SNIFFER 0x0150
279 #define MWL8K_CMD_SET_MAC_ADDR 0x0202
280 #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
281 #define MWL8K_CMD_UPDATE_STADB 0x1123
282
283 static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
284 {
285 #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
286 snprintf(buf, bufsize, "%s", #x);\
287 return buf;\
288 } while (0)
289 switch (cmd & ~0x8000) {
290 MWL8K_CMDNAME(CODE_DNLD);
291 MWL8K_CMDNAME(GET_HW_SPEC);
292 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
293 MWL8K_CMDNAME(GET_STAT);
294 MWL8K_CMDNAME(RADIO_CONTROL);
295 MWL8K_CMDNAME(RF_TX_POWER);
296 MWL8K_CMDNAME(SET_PRE_SCAN);
297 MWL8K_CMDNAME(SET_POST_SCAN);
298 MWL8K_CMDNAME(SET_RF_CHANNEL);
299 MWL8K_CMDNAME(SET_AID);
300 MWL8K_CMDNAME(SET_RATE);
301 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
302 MWL8K_CMDNAME(RTS_THRESHOLD);
303 MWL8K_CMDNAME(SET_SLOT);
304 MWL8K_CMDNAME(SET_EDCA_PARAMS);
305 MWL8K_CMDNAME(SET_WMM_MODE);
306 MWL8K_CMDNAME(MIMO_CONFIG);
307 MWL8K_CMDNAME(USE_FIXED_RATE);
308 MWL8K_CMDNAME(ENABLE_SNIFFER);
309 MWL8K_CMDNAME(SET_MAC_ADDR);
310 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
311 MWL8K_CMDNAME(UPDATE_STADB);
312 default:
313 snprintf(buf, bufsize, "0x%x", cmd);
314 }
315 #undef MWL8K_CMDNAME
316
317 return buf;
318 }
319
320 /* Hardware and firmware reset */
321 static void mwl8k_hw_reset(struct mwl8k_priv *priv)
322 {
323 iowrite32(MWL8K_H2A_INT_RESET,
324 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
325 iowrite32(MWL8K_H2A_INT_RESET,
326 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
327 msleep(20);
328 }
329
330 /* Release fw image */
331 static void mwl8k_release_fw(struct firmware **fw)
332 {
333 if (*fw == NULL)
334 return;
335 release_firmware(*fw);
336 *fw = NULL;
337 }
338
339 static void mwl8k_release_firmware(struct mwl8k_priv *priv)
340 {
341 mwl8k_release_fw(&priv->fw.ucode);
342 mwl8k_release_fw(&priv->fw.helper);
343 }
344
345 /* Request fw image */
346 static int mwl8k_request_fw(struct mwl8k_priv *priv,
347 const char *fname, struct firmware **fw)
348 {
349 /* release current image */
350 if (*fw != NULL)
351 mwl8k_release_fw(fw);
352
353 return request_firmware((const struct firmware **)fw,
354 fname, &priv->pdev->dev);
355 }
356
357 static int mwl8k_request_firmware(struct mwl8k_priv *priv)
358 {
359 u8 filename[64];
360 int rc;
361
362 snprintf(filename, sizeof(filename),
363 "mwl8k/helper_%u.fw", priv->device_info->part_num);
364
365 rc = mwl8k_request_fw(priv, filename, &priv->fw.helper);
366 if (rc) {
367 printk(KERN_ERR "%s: Error requesting helper firmware "
368 "file %s\n", pci_name(priv->pdev), filename);
369 return rc;
370 }
371
372 snprintf(filename, sizeof(filename),
373 "mwl8k/fmimage_%u.fw", priv->device_info->part_num);
374
375 rc = mwl8k_request_fw(priv, filename, &priv->fw.ucode);
376 if (rc) {
377 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
378 pci_name(priv->pdev), filename);
379 mwl8k_release_fw(&priv->fw.helper);
380 return rc;
381 }
382
383 return 0;
384 }
385
386 struct mwl8k_cmd_pkt {
387 __le16 code;
388 __le16 length;
389 __le16 seq_num;
390 __le16 result;
391 char payload[0];
392 } __attribute__((packed));
393
394 /*
395 * Firmware loading.
396 */
397 static int
398 mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
399 {
400 void __iomem *regs = priv->regs;
401 dma_addr_t dma_addr;
402 int loops;
403
404 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
405 if (pci_dma_mapping_error(priv->pdev, dma_addr))
406 return -ENOMEM;
407
408 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
409 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
410 iowrite32(MWL8K_H2A_INT_DOORBELL,
411 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
412 iowrite32(MWL8K_H2A_INT_DUMMY,
413 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
414
415 loops = 1000;
416 do {
417 u32 int_code;
418
419 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
420 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
421 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
422 break;
423 }
424
425 cond_resched();
426 udelay(1);
427 } while (--loops);
428
429 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
430
431 return loops ? 0 : -ETIMEDOUT;
432 }
433
434 static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
435 const u8 *data, size_t length)
436 {
437 struct mwl8k_cmd_pkt *cmd;
438 int done;
439 int rc = 0;
440
441 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
442 if (cmd == NULL)
443 return -ENOMEM;
444
445 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
446 cmd->seq_num = 0;
447 cmd->result = 0;
448
449 done = 0;
450 while (length) {
451 int block_size = length > 256 ? 256 : length;
452
453 memcpy(cmd->payload, data + done, block_size);
454 cmd->length = cpu_to_le16(block_size);
455
456 rc = mwl8k_send_fw_load_cmd(priv, cmd,
457 sizeof(*cmd) + block_size);
458 if (rc)
459 break;
460
461 done += block_size;
462 length -= block_size;
463 }
464
465 if (!rc) {
466 cmd->length = 0;
467 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
468 }
469
470 kfree(cmd);
471
472 return rc;
473 }
474
475 static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
476 const u8 *data, size_t length)
477 {
478 unsigned char *buffer;
479 int may_continue, rc = 0;
480 u32 done, prev_block_size;
481
482 buffer = kmalloc(1024, GFP_KERNEL);
483 if (buffer == NULL)
484 return -ENOMEM;
485
486 done = 0;
487 prev_block_size = 0;
488 may_continue = 1000;
489 while (may_continue > 0) {
490 u32 block_size;
491
492 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
493 if (block_size & 1) {
494 block_size &= ~1;
495 may_continue--;
496 } else {
497 done += prev_block_size;
498 length -= prev_block_size;
499 }
500
501 if (block_size > 1024 || block_size > length) {
502 rc = -EOVERFLOW;
503 break;
504 }
505
506 if (length == 0) {
507 rc = 0;
508 break;
509 }
510
511 if (block_size == 0) {
512 rc = -EPROTO;
513 may_continue--;
514 udelay(1);
515 continue;
516 }
517
518 prev_block_size = block_size;
519 memcpy(buffer, data + done, block_size);
520
521 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
522 if (rc)
523 break;
524 }
525
526 if (!rc && length != 0)
527 rc = -EREMOTEIO;
528
529 kfree(buffer);
530
531 return rc;
532 }
533
534 static int mwl8k_load_firmware(struct ieee80211_hw *hw)
535 {
536 struct mwl8k_priv *priv = hw->priv;
537 struct firmware *fw = priv->fw.ucode;
538 int rc;
539 int loops;
540
541 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
542 struct firmware *helper = priv->fw.helper;
543
544 if (helper == NULL) {
545 printk(KERN_ERR "%s: helper image needed but none "
546 "given\n", pci_name(priv->pdev));
547 return -EINVAL;
548 }
549
550 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
551 if (rc) {
552 printk(KERN_ERR "%s: unable to load firmware "
553 "helper image\n", pci_name(priv->pdev));
554 return rc;
555 }
556 msleep(1);
557
558 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
559 } else {
560 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
561 }
562
563 if (rc) {
564 printk(KERN_ERR "%s: unable to load firmware image\n",
565 pci_name(priv->pdev));
566 return rc;
567 }
568
569 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
570 msleep(1);
571
572 loops = 200000;
573 do {
574 if (ioread32(priv->regs + MWL8K_HIU_INT_CODE)
575 == MWL8K_FWSTA_READY)
576 break;
577 udelay(1);
578 } while (--loops);
579
580 return loops ? 0 : -ETIMEDOUT;
581 }
582
583
584 /*
585 * Defines shared between transmission and reception.
586 */
587 /* HT control fields for firmware */
588 struct ewc_ht_info {
589 __le16 control1;
590 __le16 control2;
591 __le16 control3;
592 } __attribute__((packed));
593
594 /* Firmware Station database operations */
595 #define MWL8K_STA_DB_ADD_ENTRY 0
596 #define MWL8K_STA_DB_MODIFY_ENTRY 1
597 #define MWL8K_STA_DB_DEL_ENTRY 2
598 #define MWL8K_STA_DB_FLUSH 3
599
600 /* Peer Entry flags - used to define the type of the peer node */
601 #define MWL8K_PEER_TYPE_ACCESSPOINT 2
602
603 #define MWL8K_IEEE_LEGACY_DATA_RATES 13
604 #define MWL8K_MCS_BITMAP_SIZE 16
605
606 struct peer_capability_info {
607 /* Peer type - AP vs. STA. */
608 __u8 peer_type;
609
610 /* Basic 802.11 capabilities from assoc resp. */
611 __le16 basic_caps;
612
613 /* Set if peer supports 802.11n high throughput (HT). */
614 __u8 ht_support;
615
616 /* Valid if HT is supported. */
617 __le16 ht_caps;
618 __u8 extended_ht_caps;
619 struct ewc_ht_info ewc_info;
620
621 /* Legacy rate table. Intersection of our rates and peer rates. */
622 __u8 legacy_rates[MWL8K_IEEE_LEGACY_DATA_RATES];
623
624 /* HT rate table. Intersection of our rates and peer rates. */
625 __u8 ht_rates[MWL8K_MCS_BITMAP_SIZE];
626 __u8 pad[16];
627
628 /* If set, interoperability mode, no proprietary extensions. */
629 __u8 interop;
630 __u8 pad2;
631 __u8 station_id;
632 __le16 amsdu_enabled;
633 } __attribute__((packed));
634
635 /* Inline functions to manipulate QoS field in data descriptor. */
636 static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
637 {
638 u16 val_mask = 1 << 4;
639
640 /* End of Service Period Bit 4 */
641 return qos | val_mask;
642 }
643
644 static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
645 {
646 u16 val_mask = 0x3;
647 u8 shift = 5;
648 u16 qos_mask = ~(val_mask << shift);
649
650 /* Ack Policy Bit 5-6 */
651 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
652 }
653
654 static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
655 {
656 u16 val_mask = 1 << 7;
657
658 /* AMSDU present Bit 7 */
659 return qos | val_mask;
660 }
661
662 static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
663 {
664 u16 val_mask = 0xff;
665 u8 shift = 8;
666 u16 qos_mask = ~(val_mask << shift);
667
668 /* Queue Length Bits 8-15 */
669 return (qos & qos_mask) | ((len & val_mask) << shift);
670 }
671
672 /* DMA header used by firmware and hardware. */
673 struct mwl8k_dma_data {
674 __le16 fwlen;
675 struct ieee80211_hdr wh;
676 } __attribute__((packed));
677
678 /* Routines to add/remove DMA header from skb. */
679 static inline void mwl8k_remove_dma_header(struct sk_buff *skb)
680 {
681 struct mwl8k_dma_data *tr = (struct mwl8k_dma_data *)skb->data;
682 void *dst, *src = &tr->wh;
683 int hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
684 u16 space = sizeof(struct mwl8k_dma_data) - hdrlen;
685
686 dst = (void *)tr + space;
687 if (dst != src) {
688 memmove(dst, src, hdrlen);
689 skb_pull(skb, space);
690 }
691 }
692
693 static inline void mwl8k_add_dma_header(struct sk_buff *skb)
694 {
695 struct ieee80211_hdr *wh;
696 u32 hdrlen, pktlen;
697 struct mwl8k_dma_data *tr;
698
699 wh = (struct ieee80211_hdr *)skb->data;
700 hdrlen = ieee80211_hdrlen(wh->frame_control);
701 pktlen = skb->len;
702
703 /*
704 * Copy up/down the 802.11 header; the firmware requires
705 * we present a 2-byte payload length followed by a
706 * 4-address header (w/o QoS), followed (optionally) by
707 * any WEP/ExtIV header (but only filled in for CCMP).
708 */
709 if (hdrlen != sizeof(struct mwl8k_dma_data))
710 skb_push(skb, sizeof(struct mwl8k_dma_data) - hdrlen);
711
712 tr = (struct mwl8k_dma_data *)skb->data;
713 if (wh != &tr->wh)
714 memmove(&tr->wh, wh, hdrlen);
715
716 /* Clear addr4 */
717 memset(tr->wh.addr4, 0, ETH_ALEN);
718
719 /*
720 * Firmware length is the length of the fully formed "802.11
721 * payload". That is, everything except for the 802.11 header.
722 * This includes all crypto material including the MIC.
723 */
724 tr->fwlen = cpu_to_le16(pktlen - hdrlen);
725 }
726
727
728 /*
729 * Packet reception.
730 */
731 #define MWL8K_RX_CTRL_OWNED_BY_HOST 0x02
732
733 struct mwl8k_rx_desc {
734 __le16 pkt_len;
735 __u8 link_quality;
736 __u8 noise_level;
737 __le32 pkt_phys_addr;
738 __le32 next_rxd_phys_addr;
739 __le16 qos_control;
740 __le16 rate_info;
741 __le32 pad0[4];
742 __u8 rssi;
743 __u8 channel;
744 __le16 pad1;
745 __u8 rx_ctrl;
746 __u8 rx_status;
747 __u8 pad2[2];
748 } __attribute__((packed));
749
750 #define MWL8K_RX_DESCS 256
751 #define MWL8K_RX_MAXSZ 3800
752
753 #define RATE_INFO_SHORTPRE 0x8000
754 #define RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
755 #define RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
756 #define RATE_INFO_40MHZ 0x0004
757 #define RATE_INFO_SHORTGI 0x0002
758 #define RATE_INFO_MCS_FORMAT 0x0001
759
760 static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
761 {
762 struct mwl8k_priv *priv = hw->priv;
763 struct mwl8k_rx_queue *rxq = priv->rxq + index;
764 int size;
765 int i;
766
767 rxq->rxd_count = 0;
768 rxq->head = 0;
769 rxq->tail = 0;
770
771 size = MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc);
772
773 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
774 if (rxq->rxd == NULL) {
775 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
776 wiphy_name(hw->wiphy));
777 return -ENOMEM;
778 }
779 memset(rxq->rxd, 0, size);
780
781 rxq->skb = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->skb), GFP_KERNEL);
782 if (rxq->skb == NULL) {
783 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
784 wiphy_name(hw->wiphy));
785 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
786 return -ENOMEM;
787 }
788 memset(rxq->skb, 0, MWL8K_RX_DESCS * sizeof(*rxq->skb));
789
790 for (i = 0; i < MWL8K_RX_DESCS; i++) {
791 struct mwl8k_rx_desc *rx_desc;
792 int nexti;
793
794 rx_desc = rxq->rxd + i;
795 nexti = (i + 1) % MWL8K_RX_DESCS;
796
797 rx_desc->next_rxd_phys_addr =
798 cpu_to_le32(rxq->rxd_dma + nexti * sizeof(*rx_desc));
799 rx_desc->rx_ctrl = MWL8K_RX_CTRL_OWNED_BY_HOST;
800 }
801
802 return 0;
803 }
804
805 static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
806 {
807 struct mwl8k_priv *priv = hw->priv;
808 struct mwl8k_rx_queue *rxq = priv->rxq + index;
809 int refilled;
810
811 refilled = 0;
812 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
813 struct sk_buff *skb;
814 int rx;
815
816 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
817 if (skb == NULL)
818 break;
819
820 rxq->rxd_count++;
821
822 rx = rxq->tail;
823 rxq->tail = (rx + 1) % MWL8K_RX_DESCS;
824
825 rxq->rxd[rx].pkt_phys_addr =
826 cpu_to_le32(pci_map_single(priv->pdev, skb->data,
827 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE));
828
829 rxq->rxd[rx].pkt_len = cpu_to_le16(MWL8K_RX_MAXSZ);
830 rxq->skb[rx] = skb;
831 wmb();
832 rxq->rxd[rx].rx_ctrl = 0;
833
834 refilled++;
835 }
836
837 return refilled;
838 }
839
840 /* Must be called only when the card's reception is completely halted */
841 static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
842 {
843 struct mwl8k_priv *priv = hw->priv;
844 struct mwl8k_rx_queue *rxq = priv->rxq + index;
845 int i;
846
847 for (i = 0; i < MWL8K_RX_DESCS; i++) {
848 if (rxq->skb[i] != NULL) {
849 unsigned long addr;
850
851 addr = le32_to_cpu(rxq->rxd[i].pkt_phys_addr);
852 pci_unmap_single(priv->pdev, addr, MWL8K_RX_MAXSZ,
853 PCI_DMA_FROMDEVICE);
854 kfree_skb(rxq->skb[i]);
855 rxq->skb[i] = NULL;
856 }
857 }
858
859 kfree(rxq->skb);
860 rxq->skb = NULL;
861
862 pci_free_consistent(priv->pdev,
863 MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc),
864 rxq->rxd, rxq->rxd_dma);
865 rxq->rxd = NULL;
866 }
867
868
869 /*
870 * Scan a list of BSSIDs to process for finalize join.
871 * Allows for extension to process multiple BSSIDs.
872 */
873 static inline int
874 mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
875 {
876 return priv->capture_beacon &&
877 ieee80211_is_beacon(wh->frame_control) &&
878 !compare_ether_addr(wh->addr3, priv->capture_bssid);
879 }
880
881 static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
882 struct sk_buff *skb)
883 {
884 struct mwl8k_priv *priv = hw->priv;
885
886 priv->capture_beacon = false;
887 memset(priv->capture_bssid, 0, ETH_ALEN);
888
889 /*
890 * Use GFP_ATOMIC as rxq_process is called from
891 * the primary interrupt handler, memory allocation call
892 * must not sleep.
893 */
894 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
895 if (priv->beacon_skb != NULL)
896 ieee80211_queue_work(hw, &priv->finalize_join_worker);
897 }
898
899 static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
900 {
901 struct mwl8k_priv *priv = hw->priv;
902 struct mwl8k_rx_queue *rxq = priv->rxq + index;
903 int processed;
904
905 processed = 0;
906 while (rxq->rxd_count && limit--) {
907 struct mwl8k_rx_desc *rx_desc;
908 struct sk_buff *skb;
909 struct ieee80211_rx_status status;
910 unsigned long addr;
911 struct ieee80211_hdr *wh;
912 u16 rate_info;
913
914 rx_desc = rxq->rxd + rxq->head;
915 if (!(rx_desc->rx_ctrl & MWL8K_RX_CTRL_OWNED_BY_HOST))
916 break;
917 rmb();
918
919 skb = rxq->skb[rxq->head];
920 if (skb == NULL)
921 break;
922 rxq->skb[rxq->head] = NULL;
923
924 rxq->head = (rxq->head + 1) % MWL8K_RX_DESCS;
925 rxq->rxd_count--;
926
927 addr = le32_to_cpu(rx_desc->pkt_phys_addr);
928 pci_unmap_single(priv->pdev, addr,
929 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
930
931 skb_put(skb, le16_to_cpu(rx_desc->pkt_len));
932 mwl8k_remove_dma_header(skb);
933
934 wh = (struct ieee80211_hdr *)skb->data;
935
936 /*
937 * Check for a pending join operation. Save a
938 * copy of the beacon and schedule a tasklet to
939 * send a FINALIZE_JOIN command to the firmware.
940 */
941 if (mwl8k_capture_bssid(priv, wh))
942 mwl8k_save_beacon(hw, skb);
943
944 rate_info = le16_to_cpu(rx_desc->rate_info);
945
946 memset(&status, 0, sizeof(status));
947 status.mactime = 0;
948 status.signal = -rx_desc->rssi;
949 status.noise = -rx_desc->noise_level;
950 status.qual = rx_desc->link_quality;
951 status.antenna = RATE_INFO_ANTSELECT(rate_info);
952 status.rate_idx = RATE_INFO_RATEID(rate_info);
953 status.flag = 0;
954 if (rate_info & RATE_INFO_SHORTPRE)
955 status.flag |= RX_FLAG_SHORTPRE;
956 if (rate_info & RATE_INFO_40MHZ)
957 status.flag |= RX_FLAG_40MHZ;
958 if (rate_info & RATE_INFO_SHORTGI)
959 status.flag |= RX_FLAG_SHORT_GI;
960 if (rate_info & RATE_INFO_MCS_FORMAT)
961 status.flag |= RX_FLAG_HT;
962 status.band = IEEE80211_BAND_2GHZ;
963 status.freq = ieee80211_channel_to_frequency(rx_desc->channel);
964 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
965 ieee80211_rx_irqsafe(hw, skb);
966
967 processed++;
968 }
969
970 return processed;
971 }
972
973
974 /*
975 * Packet transmission.
976 */
977
978 /* Transmit packet ACK policy */
979 #define MWL8K_TXD_ACK_POLICY_NORMAL 0
980 #define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
981
982 #define MWL8K_TXD_STATUS_OK 0x00000001
983 #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
984 #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
985 #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
986 #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
987
988 struct mwl8k_tx_desc {
989 __le32 status;
990 __u8 data_rate;
991 __u8 tx_priority;
992 __le16 qos_control;
993 __le32 pkt_phys_addr;
994 __le16 pkt_len;
995 __u8 dest_MAC_addr[ETH_ALEN];
996 __le32 next_txd_phys_addr;
997 __le32 reserved;
998 __le16 rate_info;
999 __u8 peer_id;
1000 __u8 tx_frag_cnt;
1001 } __attribute__((packed));
1002
1003 #define MWL8K_TX_DESCS 128
1004
1005 static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1006 {
1007 struct mwl8k_priv *priv = hw->priv;
1008 struct mwl8k_tx_queue *txq = priv->txq + index;
1009 int size;
1010 int i;
1011
1012 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1013 txq->stats.limit = MWL8K_TX_DESCS;
1014 txq->head = 0;
1015 txq->tail = 0;
1016
1017 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1018
1019 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1020 if (txq->txd == NULL) {
1021 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
1022 wiphy_name(hw->wiphy));
1023 return -ENOMEM;
1024 }
1025 memset(txq->txd, 0, size);
1026
1027 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1028 if (txq->skb == NULL) {
1029 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
1030 wiphy_name(hw->wiphy));
1031 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
1032 return -ENOMEM;
1033 }
1034 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
1035
1036 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1037 struct mwl8k_tx_desc *tx_desc;
1038 int nexti;
1039
1040 tx_desc = txq->txd + i;
1041 nexti = (i + 1) % MWL8K_TX_DESCS;
1042
1043 tx_desc->status = 0;
1044 tx_desc->next_txd_phys_addr =
1045 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
1046 }
1047
1048 return 0;
1049 }
1050
1051 static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1052 {
1053 iowrite32(MWL8K_H2A_INT_PPA_READY,
1054 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1055 iowrite32(MWL8K_H2A_INT_DUMMY,
1056 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1057 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1058 }
1059
1060 struct mwl8k_txq_info {
1061 u32 fw_owned;
1062 u32 drv_owned;
1063 u32 unused;
1064 u32 len;
1065 u32 head;
1066 u32 tail;
1067 };
1068
1069 static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
1070 struct mwl8k_txq_info *txinfo)
1071 {
1072 int count, desc, status;
1073 struct mwl8k_tx_queue *txq;
1074 struct mwl8k_tx_desc *tx_desc;
1075 int ndescs = 0;
1076
1077 memset(txinfo, 0, MWL8K_TX_QUEUES * sizeof(struct mwl8k_txq_info));
1078
1079 for (count = 0; count < MWL8K_TX_QUEUES; count++) {
1080 txq = priv->txq + count;
1081 txinfo[count].len = txq->stats.len;
1082 txinfo[count].head = txq->head;
1083 txinfo[count].tail = txq->tail;
1084 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1085 tx_desc = txq->txd + desc;
1086 status = le32_to_cpu(tx_desc->status);
1087
1088 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1089 txinfo[count].fw_owned++;
1090 else
1091 txinfo[count].drv_owned++;
1092
1093 if (tx_desc->pkt_len == 0)
1094 txinfo[count].unused++;
1095 }
1096 }
1097
1098 return ndescs;
1099 }
1100
1101 /*
1102 * Must be called with priv->fw_mutex held and tx queues stopped.
1103 */
1104 static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
1105 {
1106 struct mwl8k_priv *priv = hw->priv;
1107 DECLARE_COMPLETION_ONSTACK(tx_wait);
1108 u32 count;
1109 unsigned long timeout;
1110
1111 might_sleep();
1112
1113 spin_lock_bh(&priv->tx_lock);
1114 count = priv->pending_tx_pkts;
1115 if (count)
1116 priv->tx_wait = &tx_wait;
1117 spin_unlock_bh(&priv->tx_lock);
1118
1119 if (count) {
1120 struct mwl8k_txq_info txinfo[MWL8K_TX_QUEUES];
1121 int index;
1122 int newcount;
1123
1124 timeout = wait_for_completion_timeout(&tx_wait,
1125 msecs_to_jiffies(5000));
1126 if (timeout)
1127 return 0;
1128
1129 spin_lock_bh(&priv->tx_lock);
1130 priv->tx_wait = NULL;
1131 newcount = priv->pending_tx_pkts;
1132 mwl8k_scan_tx_ring(priv, txinfo);
1133 spin_unlock_bh(&priv->tx_lock);
1134
1135 printk(KERN_ERR "%s(%u) TIMEDOUT:5000ms Pend:%u-->%u\n",
1136 __func__, __LINE__, count, newcount);
1137
1138 for (index = 0; index < MWL8K_TX_QUEUES; index++)
1139 printk(KERN_ERR "TXQ:%u L:%u H:%u T:%u FW:%u "
1140 "DRV:%u U:%u\n",
1141 index,
1142 txinfo[index].len,
1143 txinfo[index].head,
1144 txinfo[index].tail,
1145 txinfo[index].fw_owned,
1146 txinfo[index].drv_owned,
1147 txinfo[index].unused);
1148
1149 return -ETIMEDOUT;
1150 }
1151
1152 return 0;
1153 }
1154
1155 #define MWL8K_TXD_SUCCESS(status) \
1156 ((status) & (MWL8K_TXD_STATUS_OK | \
1157 MWL8K_TXD_STATUS_OK_RETRY | \
1158 MWL8K_TXD_STATUS_OK_MORE_RETRY))
1159
1160 static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1161 {
1162 struct mwl8k_priv *priv = hw->priv;
1163 struct mwl8k_tx_queue *txq = priv->txq + index;
1164 int wake = 0;
1165
1166 while (txq->stats.len > 0) {
1167 int tx;
1168 struct mwl8k_tx_desc *tx_desc;
1169 unsigned long addr;
1170 int size;
1171 struct sk_buff *skb;
1172 struct ieee80211_tx_info *info;
1173 u32 status;
1174
1175 tx = txq->head;
1176 tx_desc = txq->txd + tx;
1177
1178 status = le32_to_cpu(tx_desc->status);
1179
1180 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1181 if (!force)
1182 break;
1183 tx_desc->status &=
1184 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1185 }
1186
1187 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1188 BUG_ON(txq->stats.len == 0);
1189 txq->stats.len--;
1190 priv->pending_tx_pkts--;
1191
1192 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
1193 size = le16_to_cpu(tx_desc->pkt_len);
1194 skb = txq->skb[tx];
1195 txq->skb[tx] = NULL;
1196
1197 BUG_ON(skb == NULL);
1198 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1199
1200 mwl8k_remove_dma_header(skb);
1201
1202 /* Mark descriptor as unused */
1203 tx_desc->pkt_phys_addr = 0;
1204 tx_desc->pkt_len = 0;
1205
1206 info = IEEE80211_SKB_CB(skb);
1207 ieee80211_tx_info_clear_status(info);
1208 if (MWL8K_TXD_SUCCESS(status))
1209 info->flags |= IEEE80211_TX_STAT_ACK;
1210
1211 ieee80211_tx_status_irqsafe(hw, skb);
1212
1213 wake = 1;
1214 }
1215
1216 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
1217 ieee80211_wake_queue(hw, index);
1218 }
1219
1220 /* must be called only when the card's transmit is completely halted */
1221 static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1222 {
1223 struct mwl8k_priv *priv = hw->priv;
1224 struct mwl8k_tx_queue *txq = priv->txq + index;
1225
1226 mwl8k_txq_reclaim(hw, index, 1);
1227
1228 kfree(txq->skb);
1229 txq->skb = NULL;
1230
1231 pci_free_consistent(priv->pdev,
1232 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1233 txq->txd, txq->txd_dma);
1234 txq->txd = NULL;
1235 }
1236
1237 static int
1238 mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1239 {
1240 struct mwl8k_priv *priv = hw->priv;
1241 struct ieee80211_tx_info *tx_info;
1242 struct mwl8k_vif *mwl8k_vif;
1243 struct ieee80211_hdr *wh;
1244 struct mwl8k_tx_queue *txq;
1245 struct mwl8k_tx_desc *tx;
1246 dma_addr_t dma;
1247 u32 txstatus;
1248 u8 txdatarate;
1249 u16 qos;
1250
1251 wh = (struct ieee80211_hdr *)skb->data;
1252 if (ieee80211_is_data_qos(wh->frame_control))
1253 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1254 else
1255 qos = 0;
1256
1257 mwl8k_add_dma_header(skb);
1258 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
1259
1260 tx_info = IEEE80211_SKB_CB(skb);
1261 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
1262
1263 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1264 u16 seqno = mwl8k_vif->seqno;
1265
1266 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1267 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1268 mwl8k_vif->seqno = seqno++ % 4096;
1269 }
1270
1271 /* Setup firmware control bit fields for each frame type. */
1272 txstatus = 0;
1273 txdatarate = 0;
1274 if (ieee80211_is_mgmt(wh->frame_control) ||
1275 ieee80211_is_ctl(wh->frame_control)) {
1276 txdatarate = 0;
1277 qos = mwl8k_qos_setbit_eosp(qos);
1278 /* Set Queue size to unspecified */
1279 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1280 } else if (ieee80211_is_data(wh->frame_control)) {
1281 txdatarate = 1;
1282 if (is_multicast_ether_addr(wh->addr1))
1283 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1284
1285 /* Send pkt in an aggregate if AMPDU frame. */
1286 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1287 qos = mwl8k_qos_setbit_ack(qos,
1288 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1289 else
1290 qos = mwl8k_qos_setbit_ack(qos,
1291 MWL8K_TXD_ACK_POLICY_NORMAL);
1292
1293 if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
1294 qos = mwl8k_qos_setbit_amsdu(qos);
1295 }
1296
1297 dma = pci_map_single(priv->pdev, skb->data,
1298 skb->len, PCI_DMA_TODEVICE);
1299
1300 if (pci_dma_mapping_error(priv->pdev, dma)) {
1301 printk(KERN_DEBUG "%s: failed to dma map skb, "
1302 "dropping TX frame.\n", wiphy_name(hw->wiphy));
1303 dev_kfree_skb(skb);
1304 return NETDEV_TX_OK;
1305 }
1306
1307 spin_lock_bh(&priv->tx_lock);
1308
1309 txq = priv->txq + index;
1310
1311 BUG_ON(txq->skb[txq->tail] != NULL);
1312 txq->skb[txq->tail] = skb;
1313
1314 tx = txq->txd + txq->tail;
1315 tx->data_rate = txdatarate;
1316 tx->tx_priority = index;
1317 tx->qos_control = cpu_to_le16(qos);
1318 tx->pkt_phys_addr = cpu_to_le32(dma);
1319 tx->pkt_len = cpu_to_le16(skb->len);
1320 tx->rate_info = 0;
1321 tx->peer_id = mwl8k_vif->peer_id;
1322 wmb();
1323 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1324
1325 txq->stats.count++;
1326 txq->stats.len++;
1327 priv->pending_tx_pkts++;
1328
1329 txq->tail++;
1330 if (txq->tail == MWL8K_TX_DESCS)
1331 txq->tail = 0;
1332
1333 if (txq->head == txq->tail)
1334 ieee80211_stop_queue(hw, index);
1335
1336 mwl8k_tx_start(priv);
1337
1338 spin_unlock_bh(&priv->tx_lock);
1339
1340 return NETDEV_TX_OK;
1341 }
1342
1343
1344 /*
1345 * Firmware access.
1346 *
1347 * We have the following requirements for issuing firmware commands:
1348 * - Some commands require that the packet transmit path is idle when
1349 * the command is issued. (For simplicity, we'll just quiesce the
1350 * transmit path for every command.)
1351 * - There are certain sequences of commands that need to be issued to
1352 * the hardware sequentially, with no other intervening commands.
1353 *
1354 * This leads to an implementation of a "firmware lock" as a mutex that
1355 * can be taken recursively, and which is taken by both the low-level
1356 * command submission function (mwl8k_post_cmd) as well as any users of
1357 * that function that require issuing of an atomic sequence of commands,
1358 * and quiesces the transmit path whenever it's taken.
1359 */
1360 static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1361 {
1362 struct mwl8k_priv *priv = hw->priv;
1363
1364 if (priv->fw_mutex_owner != current) {
1365 int rc;
1366
1367 mutex_lock(&priv->fw_mutex);
1368 ieee80211_stop_queues(hw);
1369
1370 rc = mwl8k_tx_wait_empty(hw);
1371 if (rc) {
1372 ieee80211_wake_queues(hw);
1373 mutex_unlock(&priv->fw_mutex);
1374
1375 return rc;
1376 }
1377
1378 priv->fw_mutex_owner = current;
1379 }
1380
1381 priv->fw_mutex_depth++;
1382
1383 return 0;
1384 }
1385
1386 static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1387 {
1388 struct mwl8k_priv *priv = hw->priv;
1389
1390 if (!--priv->fw_mutex_depth) {
1391 ieee80211_wake_queues(hw);
1392 priv->fw_mutex_owner = NULL;
1393 mutex_unlock(&priv->fw_mutex);
1394 }
1395 }
1396
1397
1398 /*
1399 * Command processing.
1400 */
1401
1402 /* Timeout firmware commands after 2000ms */
1403 #define MWL8K_CMD_TIMEOUT_MS 2000
1404
1405 static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1406 {
1407 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1408 struct mwl8k_priv *priv = hw->priv;
1409 void __iomem *regs = priv->regs;
1410 dma_addr_t dma_addr;
1411 unsigned int dma_size;
1412 int rc;
1413 unsigned long timeout = 0;
1414 u8 buf[32];
1415
1416 cmd->result = 0xffff;
1417 dma_size = le16_to_cpu(cmd->length);
1418 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1419 PCI_DMA_BIDIRECTIONAL);
1420 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1421 return -ENOMEM;
1422
1423 rc = mwl8k_fw_lock(hw);
1424 if (rc) {
1425 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1426 PCI_DMA_BIDIRECTIONAL);
1427 return rc;
1428 }
1429
1430 priv->hostcmd_wait = &cmd_wait;
1431 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1432 iowrite32(MWL8K_H2A_INT_DOORBELL,
1433 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1434 iowrite32(MWL8K_H2A_INT_DUMMY,
1435 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1436
1437 timeout = wait_for_completion_timeout(&cmd_wait,
1438 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1439
1440 priv->hostcmd_wait = NULL;
1441
1442 mwl8k_fw_unlock(hw);
1443
1444 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1445 PCI_DMA_BIDIRECTIONAL);
1446
1447 if (!timeout) {
1448 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
1449 wiphy_name(hw->wiphy),
1450 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1451 MWL8K_CMD_TIMEOUT_MS);
1452 rc = -ETIMEDOUT;
1453 } else {
1454 rc = cmd->result ? -EINVAL : 0;
1455 if (rc)
1456 printk(KERN_ERR "%s: Command %s error 0x%x\n",
1457 wiphy_name(hw->wiphy),
1458 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1459 le16_to_cpu(cmd->result));
1460 }
1461
1462 return rc;
1463 }
1464
1465 /*
1466 * GET_HW_SPEC.
1467 */
1468 struct mwl8k_cmd_get_hw_spec {
1469 struct mwl8k_cmd_pkt header;
1470 __u8 hw_rev;
1471 __u8 host_interface;
1472 __le16 num_mcaddrs;
1473 __u8 perm_addr[ETH_ALEN];
1474 __le16 region_code;
1475 __le32 fw_rev;
1476 __le32 ps_cookie;
1477 __le32 caps;
1478 __u8 mcs_bitmap[16];
1479 __le32 rx_queue_ptr;
1480 __le32 num_tx_queues;
1481 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1482 __le32 caps2;
1483 __le32 num_tx_desc_per_queue;
1484 __le32 total_rxd;
1485 } __attribute__((packed));
1486
1487 static int mwl8k_cmd_get_hw_spec(struct ieee80211_hw *hw)
1488 {
1489 struct mwl8k_priv *priv = hw->priv;
1490 struct mwl8k_cmd_get_hw_spec *cmd;
1491 int rc;
1492 int i;
1493
1494 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1495 if (cmd == NULL)
1496 return -ENOMEM;
1497
1498 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1499 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1500
1501 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1502 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1503 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1504 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1505 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1506 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1507 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1508 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1509
1510 rc = mwl8k_post_cmd(hw, &cmd->header);
1511
1512 if (!rc) {
1513 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1514 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1515 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1516 priv->hw_rev = cmd->hw_rev;
1517 }
1518
1519 kfree(cmd);
1520 return rc;
1521 }
1522
1523 /*
1524 * CMD_MAC_MULTICAST_ADR.
1525 */
1526 struct mwl8k_cmd_mac_multicast_adr {
1527 struct mwl8k_cmd_pkt header;
1528 __le16 action;
1529 __le16 numaddr;
1530 __u8 addr[0][ETH_ALEN];
1531 };
1532
1533 #define MWL8K_ENABLE_RX_DIRECTED 0x0001
1534 #define MWL8K_ENABLE_RX_MULTICAST 0x0002
1535 #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1536 #define MWL8K_ENABLE_RX_BROADCAST 0x0008
1537
1538 static struct mwl8k_cmd_pkt *
1539 __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
1540 int mc_count, struct dev_addr_list *mclist)
1541 {
1542 struct mwl8k_priv *priv = hw->priv;
1543 struct mwl8k_cmd_mac_multicast_adr *cmd;
1544 int size;
1545
1546 if (allmulti || mc_count > priv->num_mcaddrs) {
1547 allmulti = 1;
1548 mc_count = 0;
1549 }
1550
1551 size = sizeof(*cmd) + mc_count * ETH_ALEN;
1552
1553 cmd = kzalloc(size, GFP_ATOMIC);
1554 if (cmd == NULL)
1555 return NULL;
1556
1557 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1558 cmd->header.length = cpu_to_le16(size);
1559 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1560 MWL8K_ENABLE_RX_BROADCAST);
1561
1562 if (allmulti) {
1563 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1564 } else if (mc_count) {
1565 int i;
1566
1567 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1568 cmd->numaddr = cpu_to_le16(mc_count);
1569 for (i = 0; i < mc_count && mclist; i++) {
1570 if (mclist->da_addrlen != ETH_ALEN) {
1571 kfree(cmd);
1572 return NULL;
1573 }
1574 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1575 mclist = mclist->next;
1576 }
1577 }
1578
1579 return &cmd->header;
1580 }
1581
1582 /*
1583 * CMD_802_11_GET_STAT.
1584 */
1585 struct mwl8k_cmd_802_11_get_stat {
1586 struct mwl8k_cmd_pkt header;
1587 __le32 stats[64];
1588 } __attribute__((packed));
1589
1590 #define MWL8K_STAT_ACK_FAILURE 9
1591 #define MWL8K_STAT_RTS_FAILURE 12
1592 #define MWL8K_STAT_FCS_ERROR 24
1593 #define MWL8K_STAT_RTS_SUCCESS 11
1594
1595 static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1596 struct ieee80211_low_level_stats *stats)
1597 {
1598 struct mwl8k_cmd_802_11_get_stat *cmd;
1599 int rc;
1600
1601 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1602 if (cmd == NULL)
1603 return -ENOMEM;
1604
1605 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1606 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1607
1608 rc = mwl8k_post_cmd(hw, &cmd->header);
1609 if (!rc) {
1610 stats->dot11ACKFailureCount =
1611 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1612 stats->dot11RTSFailureCount =
1613 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1614 stats->dot11FCSErrorCount =
1615 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1616 stats->dot11RTSSuccessCount =
1617 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1618 }
1619 kfree(cmd);
1620
1621 return rc;
1622 }
1623
1624 /*
1625 * CMD_802_11_RADIO_CONTROL.
1626 */
1627 struct mwl8k_cmd_802_11_radio_control {
1628 struct mwl8k_cmd_pkt header;
1629 __le16 action;
1630 __le16 control;
1631 __le16 radio_on;
1632 } __attribute__((packed));
1633
1634 static int
1635 mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
1636 {
1637 struct mwl8k_priv *priv = hw->priv;
1638 struct mwl8k_cmd_802_11_radio_control *cmd;
1639 int rc;
1640
1641 if (enable == priv->radio_on && !force)
1642 return 0;
1643
1644 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1645 if (cmd == NULL)
1646 return -ENOMEM;
1647
1648 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1649 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1650 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1651 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
1652 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1653
1654 rc = mwl8k_post_cmd(hw, &cmd->header);
1655 kfree(cmd);
1656
1657 if (!rc)
1658 priv->radio_on = enable;
1659
1660 return rc;
1661 }
1662
1663 static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1664 {
1665 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1666 }
1667
1668 static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1669 {
1670 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1671 }
1672
1673 static int
1674 mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1675 {
1676 struct mwl8k_priv *priv;
1677
1678 if (hw == NULL || hw->priv == NULL)
1679 return -EINVAL;
1680 priv = hw->priv;
1681
1682 priv->radio_short_preamble = short_preamble;
1683
1684 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
1685 }
1686
1687 /*
1688 * CMD_802_11_RF_TX_POWER.
1689 */
1690 #define MWL8K_TX_POWER_LEVEL_TOTAL 8
1691
1692 struct mwl8k_cmd_802_11_rf_tx_power {
1693 struct mwl8k_cmd_pkt header;
1694 __le16 action;
1695 __le16 support_level;
1696 __le16 current_level;
1697 __le16 reserved;
1698 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1699 } __attribute__((packed));
1700
1701 static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1702 {
1703 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
1704 int rc;
1705
1706 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1707 if (cmd == NULL)
1708 return -ENOMEM;
1709
1710 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1711 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1712 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1713 cmd->support_level = cpu_to_le16(dBm);
1714
1715 rc = mwl8k_post_cmd(hw, &cmd->header);
1716 kfree(cmd);
1717
1718 return rc;
1719 }
1720
1721 /*
1722 * CMD_SET_PRE_SCAN.
1723 */
1724 struct mwl8k_cmd_set_pre_scan {
1725 struct mwl8k_cmd_pkt header;
1726 } __attribute__((packed));
1727
1728 static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
1729 {
1730 struct mwl8k_cmd_set_pre_scan *cmd;
1731 int rc;
1732
1733 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1734 if (cmd == NULL)
1735 return -ENOMEM;
1736
1737 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
1738 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1739
1740 rc = mwl8k_post_cmd(hw, &cmd->header);
1741 kfree(cmd);
1742
1743 return rc;
1744 }
1745
1746 /*
1747 * CMD_SET_POST_SCAN.
1748 */
1749 struct mwl8k_cmd_set_post_scan {
1750 struct mwl8k_cmd_pkt header;
1751 __le32 isibss;
1752 __u8 bssid[ETH_ALEN];
1753 } __attribute__((packed));
1754
1755 static int
1756 mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
1757 {
1758 struct mwl8k_cmd_set_post_scan *cmd;
1759 int rc;
1760
1761 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1762 if (cmd == NULL)
1763 return -ENOMEM;
1764
1765 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
1766 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1767 cmd->isibss = 0;
1768 memcpy(cmd->bssid, mac, ETH_ALEN);
1769
1770 rc = mwl8k_post_cmd(hw, &cmd->header);
1771 kfree(cmd);
1772
1773 return rc;
1774 }
1775
1776 /*
1777 * CMD_SET_RF_CHANNEL.
1778 */
1779 struct mwl8k_cmd_set_rf_channel {
1780 struct mwl8k_cmd_pkt header;
1781 __le16 action;
1782 __u8 current_channel;
1783 __le32 channel_flags;
1784 } __attribute__((packed));
1785
1786 static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
1787 struct ieee80211_channel *channel)
1788 {
1789 struct mwl8k_cmd_set_rf_channel *cmd;
1790 int rc;
1791
1792 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1793 if (cmd == NULL)
1794 return -ENOMEM;
1795
1796 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
1797 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1798 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1799 cmd->current_channel = channel->hw_value;
1800 if (channel->band == IEEE80211_BAND_2GHZ)
1801 cmd->channel_flags = cpu_to_le32(0x00000081);
1802 else
1803 cmd->channel_flags = cpu_to_le32(0x00000000);
1804
1805 rc = mwl8k_post_cmd(hw, &cmd->header);
1806 kfree(cmd);
1807
1808 return rc;
1809 }
1810
1811 /*
1812 * CMD_SET_SLOT.
1813 */
1814 struct mwl8k_cmd_set_slot {
1815 struct mwl8k_cmd_pkt header;
1816 __le16 action;
1817 __u8 short_slot;
1818 } __attribute__((packed));
1819
1820 static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
1821 {
1822 struct mwl8k_cmd_set_slot *cmd;
1823 int rc;
1824
1825 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1826 if (cmd == NULL)
1827 return -ENOMEM;
1828
1829 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
1830 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1831 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1832 cmd->short_slot = short_slot_time;
1833
1834 rc = mwl8k_post_cmd(hw, &cmd->header);
1835 kfree(cmd);
1836
1837 return rc;
1838 }
1839
1840 /*
1841 * CMD_MIMO_CONFIG.
1842 */
1843 struct mwl8k_cmd_mimo_config {
1844 struct mwl8k_cmd_pkt header;
1845 __le32 action;
1846 __u8 rx_antenna_map;
1847 __u8 tx_antenna_map;
1848 } __attribute__((packed));
1849
1850 static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
1851 {
1852 struct mwl8k_cmd_mimo_config *cmd;
1853 int rc;
1854
1855 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1856 if (cmd == NULL)
1857 return -ENOMEM;
1858
1859 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
1860 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1861 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
1862 cmd->rx_antenna_map = rx;
1863 cmd->tx_antenna_map = tx;
1864
1865 rc = mwl8k_post_cmd(hw, &cmd->header);
1866 kfree(cmd);
1867
1868 return rc;
1869 }
1870
1871 /*
1872 * CMD_ENABLE_SNIFFER.
1873 */
1874 struct mwl8k_cmd_enable_sniffer {
1875 struct mwl8k_cmd_pkt header;
1876 __le32 action;
1877 } __attribute__((packed));
1878
1879 static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
1880 {
1881 struct mwl8k_cmd_enable_sniffer *cmd;
1882 int rc;
1883
1884 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1885 if (cmd == NULL)
1886 return -ENOMEM;
1887
1888 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
1889 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1890 cmd->action = cpu_to_le32(!!enable);
1891
1892 rc = mwl8k_post_cmd(hw, &cmd->header);
1893 kfree(cmd);
1894
1895 return rc;
1896 }
1897
1898 /*
1899 * CMD_SET_MAC_ADDR.
1900 */
1901 struct mwl8k_cmd_set_mac_addr {
1902 struct mwl8k_cmd_pkt header;
1903 __u8 mac_addr[ETH_ALEN];
1904 } __attribute__((packed));
1905
1906 static int mwl8k_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
1907 {
1908 struct mwl8k_cmd_set_mac_addr *cmd;
1909 int rc;
1910
1911 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1912 if (cmd == NULL)
1913 return -ENOMEM;
1914
1915 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
1916 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1917 memcpy(cmd->mac_addr, mac, ETH_ALEN);
1918
1919 rc = mwl8k_post_cmd(hw, &cmd->header);
1920 kfree(cmd);
1921
1922 return rc;
1923 }
1924
1925
1926 /*
1927 * CMD_SET_RATEADAPT_MODE.
1928 */
1929 struct mwl8k_cmd_set_rate_adapt_mode {
1930 struct mwl8k_cmd_pkt header;
1931 __le16 action;
1932 __le16 mode;
1933 } __attribute__((packed));
1934
1935 static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
1936 {
1937 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
1938 int rc;
1939
1940 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1941 if (cmd == NULL)
1942 return -ENOMEM;
1943
1944 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
1945 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1946 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1947 cmd->mode = cpu_to_le16(mode);
1948
1949 rc = mwl8k_post_cmd(hw, &cmd->header);
1950 kfree(cmd);
1951
1952 return rc;
1953 }
1954
1955 /*
1956 * CMD_SET_WMM_MODE.
1957 */
1958 struct mwl8k_cmd_set_wmm {
1959 struct mwl8k_cmd_pkt header;
1960 __le16 action;
1961 } __attribute__((packed));
1962
1963 static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
1964 {
1965 struct mwl8k_priv *priv = hw->priv;
1966 struct mwl8k_cmd_set_wmm *cmd;
1967 int rc;
1968
1969 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1970 if (cmd == NULL)
1971 return -ENOMEM;
1972
1973 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
1974 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1975 cmd->action = cpu_to_le16(!!enable);
1976
1977 rc = mwl8k_post_cmd(hw, &cmd->header);
1978 kfree(cmd);
1979
1980 if (!rc)
1981 priv->wmm_enabled = enable;
1982
1983 return rc;
1984 }
1985
1986 /*
1987 * CMD_SET_RTS_THRESHOLD.
1988 */
1989 struct mwl8k_cmd_rts_threshold {
1990 struct mwl8k_cmd_pkt header;
1991 __le16 action;
1992 __le16 threshold;
1993 } __attribute__((packed));
1994
1995 static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
1996 u16 action, u16 threshold)
1997 {
1998 struct mwl8k_cmd_rts_threshold *cmd;
1999 int rc;
2000
2001 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2002 if (cmd == NULL)
2003 return -ENOMEM;
2004
2005 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2006 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2007 cmd->action = cpu_to_le16(action);
2008 cmd->threshold = cpu_to_le16(threshold);
2009
2010 rc = mwl8k_post_cmd(hw, &cmd->header);
2011 kfree(cmd);
2012
2013 return rc;
2014 }
2015
2016 /*
2017 * CMD_SET_EDCA_PARAMS.
2018 */
2019 struct mwl8k_cmd_set_edca_params {
2020 struct mwl8k_cmd_pkt header;
2021
2022 /* See MWL8K_SET_EDCA_XXX below */
2023 __le16 action;
2024
2025 /* TX opportunity in units of 32 us */
2026 __le16 txop;
2027
2028 /* Log exponent of max contention period: 0...15*/
2029 __u8 log_cw_max;
2030
2031 /* Log exponent of min contention period: 0...15 */
2032 __u8 log_cw_min;
2033
2034 /* Adaptive interframe spacing in units of 32us */
2035 __u8 aifs;
2036
2037 /* TX queue to configure */
2038 __u8 txq;
2039 } __attribute__((packed));
2040
2041 #define MWL8K_SET_EDCA_CW 0x01
2042 #define MWL8K_SET_EDCA_TXOP 0x02
2043 #define MWL8K_SET_EDCA_AIFS 0x04
2044
2045 #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2046 MWL8K_SET_EDCA_TXOP | \
2047 MWL8K_SET_EDCA_AIFS)
2048
2049 static int
2050 mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2051 __u16 cw_min, __u16 cw_max,
2052 __u8 aifs, __u16 txop)
2053 {
2054 struct mwl8k_cmd_set_edca_params *cmd;
2055 int rc;
2056
2057 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2058 if (cmd == NULL)
2059 return -ENOMEM;
2060
2061 /*
2062 * Queues 0 (BE) and 1 (BK) are swapped in hardware for
2063 * this call.
2064 */
2065 qnum ^= !(qnum >> 1);
2066
2067 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2068 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2069 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2070 cmd->txop = cpu_to_le16(txop);
2071 cmd->log_cw_max = (u8)ilog2(cw_max + 1);
2072 cmd->log_cw_min = (u8)ilog2(cw_min + 1);
2073 cmd->aifs = aifs;
2074 cmd->txq = qnum;
2075
2076 rc = mwl8k_post_cmd(hw, &cmd->header);
2077 kfree(cmd);
2078
2079 return rc;
2080 }
2081
2082 /*
2083 * CMD_FINALIZE_JOIN.
2084 */
2085
2086 /* FJ beacon buffer size is compiled into the firmware. */
2087 #define MWL8K_FJ_BEACON_MAXLEN 128
2088
2089 struct mwl8k_cmd_finalize_join {
2090 struct mwl8k_cmd_pkt header;
2091 __le32 sleep_interval; /* Number of beacon periods to sleep */
2092 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2093 } __attribute__((packed));
2094
2095 static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2096 __u16 framelen, __u16 dtim)
2097 {
2098 struct mwl8k_cmd_finalize_join *cmd;
2099 struct ieee80211_mgmt *payload = frame;
2100 u16 hdrlen;
2101 u32 payload_len;
2102 int rc;
2103
2104 if (frame == NULL)
2105 return -EINVAL;
2106
2107 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2108 if (cmd == NULL)
2109 return -ENOMEM;
2110
2111 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2112 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2113 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2114
2115 hdrlen = ieee80211_hdrlen(payload->frame_control);
2116
2117 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2118
2119 /* XXX TBD Might just have to abort and return an error */
2120 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2121 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
2122 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2123 payload_len, MWL8K_FJ_BEACON_MAXLEN);
2124
2125 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2126 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2127
2128 if (payload && payload_len)
2129 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2130
2131 rc = mwl8k_post_cmd(hw, &cmd->header);
2132 kfree(cmd);
2133 return rc;
2134 }
2135
2136 /*
2137 * CMD_UPDATE_STADB.
2138 */
2139 struct mwl8k_cmd_update_sta_db {
2140 struct mwl8k_cmd_pkt header;
2141
2142 /* See STADB_ACTION_TYPE */
2143 __le32 action;
2144
2145 /* Peer MAC address */
2146 __u8 peer_addr[ETH_ALEN];
2147
2148 __le32 reserved;
2149
2150 /* Peer info - valid during add/update. */
2151 struct peer_capability_info peer_info;
2152 } __attribute__((packed));
2153
2154 static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2155 struct ieee80211_vif *vif, __u32 action)
2156 {
2157 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2158 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2159 struct mwl8k_cmd_update_sta_db *cmd;
2160 struct peer_capability_info *peer_info;
2161 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2162 int rc;
2163 __u8 count, *rates;
2164
2165 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2166 if (cmd == NULL)
2167 return -ENOMEM;
2168
2169 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2170 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2171
2172 cmd->action = cpu_to_le32(action);
2173 peer_info = &cmd->peer_info;
2174 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
2175
2176 switch (action) {
2177 case MWL8K_STA_DB_ADD_ENTRY:
2178 case MWL8K_STA_DB_MODIFY_ENTRY:
2179 /* Build peer_info block */
2180 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2181 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2182 peer_info->interop = 1;
2183 peer_info->amsdu_enabled = 0;
2184
2185 rates = peer_info->legacy_rates;
2186 for (count = 0; count < mv_vif->legacy_nrates; count++)
2187 rates[count] = bitrates[count].hw_value;
2188
2189 rc = mwl8k_post_cmd(hw, &cmd->header);
2190 if (rc == 0)
2191 mv_vif->peer_id = peer_info->station_id;
2192
2193 break;
2194
2195 case MWL8K_STA_DB_DEL_ENTRY:
2196 case MWL8K_STA_DB_FLUSH:
2197 default:
2198 rc = mwl8k_post_cmd(hw, &cmd->header);
2199 if (rc == 0)
2200 mv_vif->peer_id = 0;
2201 break;
2202 }
2203 kfree(cmd);
2204
2205 return rc;
2206 }
2207
2208 /*
2209 * CMD_SET_AID.
2210 */
2211 #define MWL8K_RATE_INDEX_MAX_ARRAY 14
2212
2213 #define MWL8K_FRAME_PROT_DISABLED 0x00
2214 #define MWL8K_FRAME_PROT_11G 0x07
2215 #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2216 #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
2217
2218 struct mwl8k_cmd_update_set_aid {
2219 struct mwl8k_cmd_pkt header;
2220 __le16 aid;
2221
2222 /* AP's MAC address (BSSID) */
2223 __u8 bssid[ETH_ALEN];
2224 __le16 protection_mode;
2225 __u8 supp_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2226 } __attribute__((packed));
2227
2228 static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2229 struct ieee80211_vif *vif)
2230 {
2231 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2232 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2233 struct mwl8k_cmd_update_set_aid *cmd;
2234 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2235 int count;
2236 u16 prot_mode;
2237 int rc;
2238
2239 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2240 if (cmd == NULL)
2241 return -ENOMEM;
2242
2243 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2244 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2245 cmd->aid = cpu_to_le16(info->aid);
2246
2247 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
2248
2249 if (info->use_cts_prot) {
2250 prot_mode = MWL8K_FRAME_PROT_11G;
2251 } else {
2252 switch (info->ht_operation_mode &
2253 IEEE80211_HT_OP_MODE_PROTECTION) {
2254 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2255 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2256 break;
2257 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2258 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2259 break;
2260 default:
2261 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2262 break;
2263 }
2264 }
2265 cmd->protection_mode = cpu_to_le16(prot_mode);
2266
2267 for (count = 0; count < mv_vif->legacy_nrates; count++)
2268 cmd->supp_rates[count] = bitrates[count].hw_value;
2269
2270 rc = mwl8k_post_cmd(hw, &cmd->header);
2271 kfree(cmd);
2272
2273 return rc;
2274 }
2275
2276 /*
2277 * CMD_SET_RATE.
2278 */
2279 struct mwl8k_cmd_update_rateset {
2280 struct mwl8k_cmd_pkt header;
2281 __u8 legacy_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2282
2283 /* Bitmap for supported MCS codes. */
2284 __u8 mcs_set[MWL8K_IEEE_LEGACY_DATA_RATES];
2285 __u8 reserved[MWL8K_IEEE_LEGACY_DATA_RATES];
2286 } __attribute__((packed));
2287
2288 static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2289 struct ieee80211_vif *vif)
2290 {
2291 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2292 struct mwl8k_cmd_update_rateset *cmd;
2293 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2294 int count;
2295 int rc;
2296
2297 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2298 if (cmd == NULL)
2299 return -ENOMEM;
2300
2301 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2302 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2303
2304 for (count = 0; count < mv_vif->legacy_nrates; count++)
2305 cmd->legacy_rates[count] = bitrates[count].hw_value;
2306
2307 rc = mwl8k_post_cmd(hw, &cmd->header);
2308 kfree(cmd);
2309
2310 return rc;
2311 }
2312
2313 /*
2314 * CMD_USE_FIXED_RATE.
2315 */
2316 #define MWL8K_RATE_TABLE_SIZE 8
2317 #define MWL8K_UCAST_RATE 0
2318 #define MWL8K_USE_AUTO_RATE 0x0002
2319
2320 struct mwl8k_rate_entry {
2321 /* Set to 1 if HT rate, 0 if legacy. */
2322 __le32 is_ht_rate;
2323
2324 /* Set to 1 to use retry_count field. */
2325 __le32 enable_retry;
2326
2327 /* Specified legacy rate or MCS. */
2328 __le32 rate;
2329
2330 /* Number of allowed retries. */
2331 __le32 retry_count;
2332 } __attribute__((packed));
2333
2334 struct mwl8k_rate_table {
2335 /* 1 to allow specified rate and below */
2336 __le32 allow_rate_drop;
2337 __le32 num_rates;
2338 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2339 } __attribute__((packed));
2340
2341 struct mwl8k_cmd_use_fixed_rate {
2342 struct mwl8k_cmd_pkt header;
2343 __le32 action;
2344 struct mwl8k_rate_table rate_table;
2345
2346 /* Unicast, Broadcast or Multicast */
2347 __le32 rate_type;
2348 __le32 reserved1;
2349 __le32 reserved2;
2350 } __attribute__((packed));
2351
2352 static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2353 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2354 {
2355 struct mwl8k_cmd_use_fixed_rate *cmd;
2356 int count;
2357 int rc;
2358
2359 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2360 if (cmd == NULL)
2361 return -ENOMEM;
2362
2363 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2364 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2365
2366 cmd->action = cpu_to_le32(action);
2367 cmd->rate_type = cpu_to_le32(rate_type);
2368
2369 if (rate_table != NULL) {
2370 /*
2371 * Copy over each field manually so that endian
2372 * conversion can be done.
2373 */
2374 cmd->rate_table.allow_rate_drop =
2375 cpu_to_le32(rate_table->allow_rate_drop);
2376 cmd->rate_table.num_rates =
2377 cpu_to_le32(rate_table->num_rates);
2378
2379 for (count = 0; count < rate_table->num_rates; count++) {
2380 struct mwl8k_rate_entry *dst =
2381 &cmd->rate_table.rate_entry[count];
2382 struct mwl8k_rate_entry *src =
2383 &rate_table->rate_entry[count];
2384
2385 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2386 dst->enable_retry = cpu_to_le32(src->enable_retry);
2387 dst->rate = cpu_to_le32(src->rate);
2388 dst->retry_count = cpu_to_le32(src->retry_count);
2389 }
2390 }
2391
2392 rc = mwl8k_post_cmd(hw, &cmd->header);
2393 kfree(cmd);
2394
2395 return rc;
2396 }
2397
2398
2399 /*
2400 * Interrupt handling.
2401 */
2402 static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2403 {
2404 struct ieee80211_hw *hw = dev_id;
2405 struct mwl8k_priv *priv = hw->priv;
2406 u32 status;
2407
2408 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2409 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2410
2411 if (!status)
2412 return IRQ_NONE;
2413
2414 if (status & MWL8K_A2H_INT_TX_DONE)
2415 tasklet_schedule(&priv->tx_reclaim_task);
2416
2417 if (status & MWL8K_A2H_INT_RX_READY) {
2418 while (rxq_process(hw, 0, 1))
2419 rxq_refill(hw, 0, 1);
2420 }
2421
2422 if (status & MWL8K_A2H_INT_OPC_DONE) {
2423 if (priv->hostcmd_wait != NULL)
2424 complete(priv->hostcmd_wait);
2425 }
2426
2427 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
2428 if (!mutex_is_locked(&priv->fw_mutex) &&
2429 priv->radio_on && priv->pending_tx_pkts)
2430 mwl8k_tx_start(priv);
2431 }
2432
2433 return IRQ_HANDLED;
2434 }
2435
2436
2437 /*
2438 * Core driver operations.
2439 */
2440 static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2441 {
2442 struct mwl8k_priv *priv = hw->priv;
2443 int index = skb_get_queue_mapping(skb);
2444 int rc;
2445
2446 if (priv->current_channel == NULL) {
2447 printk(KERN_DEBUG "%s: dropped TX frame since radio "
2448 "disabled\n", wiphy_name(hw->wiphy));
2449 dev_kfree_skb(skb);
2450 return NETDEV_TX_OK;
2451 }
2452
2453 rc = mwl8k_txq_xmit(hw, index, skb);
2454
2455 return rc;
2456 }
2457
2458 static int mwl8k_start(struct ieee80211_hw *hw)
2459 {
2460 struct mwl8k_priv *priv = hw->priv;
2461 int rc;
2462
2463 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
2464 IRQF_SHARED, MWL8K_NAME, hw);
2465 if (rc) {
2466 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2467 wiphy_name(hw->wiphy));
2468 return -EIO;
2469 }
2470
2471 /* Enable tx reclaim tasklet */
2472 tasklet_enable(&priv->tx_reclaim_task);
2473
2474 /* Enable interrupts */
2475 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2476
2477 rc = mwl8k_fw_lock(hw);
2478 if (!rc) {
2479 rc = mwl8k_cmd_802_11_radio_enable(hw);
2480
2481 if (!rc)
2482 rc = mwl8k_cmd_set_pre_scan(hw);
2483
2484 if (!rc)
2485 rc = mwl8k_cmd_set_post_scan(hw,
2486 "\x00\x00\x00\x00\x00\x00");
2487
2488 if (!rc)
2489 rc = mwl8k_cmd_setrateadaptmode(hw, 0);
2490
2491 if (!rc)
2492 rc = mwl8k_set_wmm(hw, 0);
2493
2494 if (!rc)
2495 rc = mwl8k_enable_sniffer(hw, 0);
2496
2497 mwl8k_fw_unlock(hw);
2498 }
2499
2500 if (rc) {
2501 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2502 free_irq(priv->pdev->irq, hw);
2503 tasklet_disable(&priv->tx_reclaim_task);
2504 }
2505
2506 return rc;
2507 }
2508
2509 static void mwl8k_stop(struct ieee80211_hw *hw)
2510 {
2511 struct mwl8k_priv *priv = hw->priv;
2512 int i;
2513
2514 mwl8k_cmd_802_11_radio_disable(hw);
2515
2516 ieee80211_stop_queues(hw);
2517
2518 /* Disable interrupts */
2519 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2520 free_irq(priv->pdev->irq, hw);
2521
2522 /* Stop finalize join worker */
2523 cancel_work_sync(&priv->finalize_join_worker);
2524 if (priv->beacon_skb != NULL)
2525 dev_kfree_skb(priv->beacon_skb);
2526
2527 /* Stop tx reclaim tasklet */
2528 tasklet_disable(&priv->tx_reclaim_task);
2529
2530 /* Return all skbs to mac80211 */
2531 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2532 mwl8k_txq_reclaim(hw, i, 1);
2533 }
2534
2535 static int mwl8k_add_interface(struct ieee80211_hw *hw,
2536 struct ieee80211_if_init_conf *conf)
2537 {
2538 struct mwl8k_priv *priv = hw->priv;
2539 struct mwl8k_vif *mwl8k_vif;
2540
2541 /*
2542 * We only support one active interface at a time.
2543 */
2544 if (priv->vif != NULL)
2545 return -EBUSY;
2546
2547 /*
2548 * We only support managed interfaces for now.
2549 */
2550 if (conf->type != NL80211_IFTYPE_STATION)
2551 return -EINVAL;
2552
2553 /*
2554 * Reject interface creation if sniffer mode is active, as
2555 * STA operation is mutually exclusive with hardware sniffer
2556 * mode.
2557 */
2558 if (priv->sniffer_enabled) {
2559 printk(KERN_INFO "%s: unable to create STA "
2560 "interface due to sniffer mode being enabled\n",
2561 wiphy_name(hw->wiphy));
2562 return -EINVAL;
2563 }
2564
2565 /* Clean out driver private area */
2566 mwl8k_vif = MWL8K_VIF(conf->vif);
2567 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2568
2569 /* Set and save the mac address */
2570 mwl8k_set_mac_addr(hw, conf->mac_addr);
2571 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
2572
2573 /* Back pointer to parent config block */
2574 mwl8k_vif->priv = priv;
2575
2576 /* Setup initial PHY parameters */
2577 memcpy(mwl8k_vif->legacy_rates,
2578 priv->rates, sizeof(mwl8k_vif->legacy_rates));
2579 mwl8k_vif->legacy_nrates = ARRAY_SIZE(priv->rates);
2580
2581 /* Set Initial sequence number to zero */
2582 mwl8k_vif->seqno = 0;
2583
2584 priv->vif = conf->vif;
2585 priv->current_channel = NULL;
2586
2587 return 0;
2588 }
2589
2590 static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2591 struct ieee80211_if_init_conf *conf)
2592 {
2593 struct mwl8k_priv *priv = hw->priv;
2594
2595 if (priv->vif == NULL)
2596 return;
2597
2598 mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
2599
2600 priv->vif = NULL;
2601 }
2602
2603 static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
2604 {
2605 struct ieee80211_conf *conf = &hw->conf;
2606 struct mwl8k_priv *priv = hw->priv;
2607 int rc;
2608
2609 if (conf->flags & IEEE80211_CONF_IDLE) {
2610 mwl8k_cmd_802_11_radio_disable(hw);
2611 priv->current_channel = NULL;
2612 return 0;
2613 }
2614
2615 rc = mwl8k_fw_lock(hw);
2616 if (rc)
2617 return rc;
2618
2619 rc = mwl8k_cmd_802_11_radio_enable(hw);
2620 if (rc)
2621 goto out;
2622
2623 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2624 if (rc)
2625 goto out;
2626
2627 priv->current_channel = conf->channel;
2628
2629 if (conf->power_level > 18)
2630 conf->power_level = 18;
2631 rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level);
2632 if (rc)
2633 goto out;
2634
2635 if (mwl8k_cmd_mimo_config(hw, 0x7, 0x7))
2636 rc = -EINVAL;
2637
2638 out:
2639 mwl8k_fw_unlock(hw);
2640
2641 return rc;
2642 }
2643
2644 static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
2645 struct ieee80211_vif *vif,
2646 struct ieee80211_bss_conf *info,
2647 u32 changed)
2648 {
2649 struct mwl8k_priv *priv = hw->priv;
2650 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
2651 int rc;
2652
2653 if (changed & BSS_CHANGED_BSSID)
2654 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
2655
2656 if ((changed & BSS_CHANGED_ASSOC) == 0)
2657 return;
2658
2659 priv->capture_beacon = false;
2660
2661 rc = mwl8k_fw_lock(hw);
2662 if (rc)
2663 return;
2664
2665 if (info->assoc) {
2666 memcpy(&mwl8k_vif->bss_info, info,
2667 sizeof(struct ieee80211_bss_conf));
2668
2669 /* Install rates */
2670 rc = mwl8k_update_rateset(hw, vif);
2671 if (rc)
2672 goto out;
2673
2674 /* Turn on rate adaptation */
2675 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
2676 MWL8K_UCAST_RATE, NULL);
2677 if (rc)
2678 goto out;
2679
2680 /* Set radio preamble */
2681 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
2682 if (rc)
2683 goto out;
2684
2685 /* Set slot time */
2686 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
2687 if (rc)
2688 goto out;
2689
2690 /* Update peer rate info */
2691 rc = mwl8k_cmd_update_sta_db(hw, vif,
2692 MWL8K_STA_DB_MODIFY_ENTRY);
2693 if (rc)
2694 goto out;
2695
2696 /* Set AID */
2697 rc = mwl8k_cmd_set_aid(hw, vif);
2698 if (rc)
2699 goto out;
2700
2701 /*
2702 * Finalize the join. Tell rx handler to process
2703 * next beacon from our BSSID.
2704 */
2705 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
2706 priv->capture_beacon = true;
2707 } else {
2708 rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
2709 memset(&mwl8k_vif->bss_info, 0,
2710 sizeof(struct ieee80211_bss_conf));
2711 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
2712 }
2713
2714 out:
2715 mwl8k_fw_unlock(hw);
2716 }
2717
2718 static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
2719 int mc_count, struct dev_addr_list *mclist)
2720 {
2721 struct mwl8k_cmd_pkt *cmd;
2722
2723 /*
2724 * Synthesize and return a command packet that programs the
2725 * hardware multicast address filter. At this point we don't
2726 * know whether FIF_ALLMULTI is being requested, but if it is,
2727 * we'll end up throwing this packet away and creating a new
2728 * one in mwl8k_configure_filter().
2729 */
2730 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
2731
2732 return (unsigned long)cmd;
2733 }
2734
2735 static int
2736 mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
2737 unsigned int changed_flags,
2738 unsigned int *total_flags)
2739 {
2740 struct mwl8k_priv *priv = hw->priv;
2741
2742 /*
2743 * Hardware sniffer mode is mutually exclusive with STA
2744 * operation, so refuse to enable sniffer mode if a STA
2745 * interface is active.
2746 */
2747 if (priv->vif != NULL) {
2748 if (net_ratelimit())
2749 printk(KERN_INFO "%s: not enabling sniffer "
2750 "mode because STA interface is active\n",
2751 wiphy_name(hw->wiphy));
2752 return 0;
2753 }
2754
2755 if (!priv->sniffer_enabled) {
2756 if (mwl8k_enable_sniffer(hw, 1))
2757 return 0;
2758 priv->sniffer_enabled = true;
2759 }
2760
2761 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
2762 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
2763 FIF_OTHER_BSS;
2764
2765 return 1;
2766 }
2767
2768 static void mwl8k_configure_filter(struct ieee80211_hw *hw,
2769 unsigned int changed_flags,
2770 unsigned int *total_flags,
2771 u64 multicast)
2772 {
2773 struct mwl8k_priv *priv = hw->priv;
2774 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
2775
2776 /*
2777 * Enable hardware sniffer mode if FIF_CONTROL or
2778 * FIF_OTHER_BSS is requested.
2779 */
2780 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
2781 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
2782 kfree(cmd);
2783 return;
2784 }
2785
2786 /* Clear unsupported feature flags */
2787 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
2788
2789 if (mwl8k_fw_lock(hw))
2790 return;
2791
2792 if (priv->sniffer_enabled) {
2793 mwl8k_enable_sniffer(hw, 0);
2794 priv->sniffer_enabled = false;
2795 }
2796
2797 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2798 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
2799 /*
2800 * Disable the BSS filter.
2801 */
2802 mwl8k_cmd_set_pre_scan(hw);
2803 } else {
2804 u8 *bssid;
2805
2806 /*
2807 * Enable the BSS filter.
2808 *
2809 * If there is an active STA interface, use that
2810 * interface's BSSID, otherwise use a dummy one
2811 * (where the OUI part needs to be nonzero for
2812 * the BSSID to be accepted by POST_SCAN).
2813 */
2814 bssid = "\x01\x00\x00\x00\x00\x00";
2815 if (priv->vif != NULL)
2816 bssid = MWL8K_VIF(priv->vif)->bssid;
2817
2818 mwl8k_cmd_set_post_scan(hw, bssid);
2819 }
2820 }
2821
2822 /*
2823 * If FIF_ALLMULTI is being requested, throw away the command
2824 * packet that ->prepare_multicast() built and replace it with
2825 * a command packet that enables reception of all multicast
2826 * packets.
2827 */
2828 if (*total_flags & FIF_ALLMULTI) {
2829 kfree(cmd);
2830 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
2831 }
2832
2833 if (cmd != NULL) {
2834 mwl8k_post_cmd(hw, cmd);
2835 kfree(cmd);
2836 }
2837
2838 mwl8k_fw_unlock(hw);
2839 }
2840
2841 static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2842 {
2843 return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value);
2844 }
2845
2846 static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2847 const struct ieee80211_tx_queue_params *params)
2848 {
2849 struct mwl8k_priv *priv = hw->priv;
2850 int rc;
2851
2852 rc = mwl8k_fw_lock(hw);
2853 if (!rc) {
2854 if (!priv->wmm_enabled)
2855 rc = mwl8k_set_wmm(hw, 1);
2856
2857 if (!rc)
2858 rc = mwl8k_set_edca_params(hw, queue,
2859 params->cw_min,
2860 params->cw_max,
2861 params->aifs,
2862 params->txop);
2863
2864 mwl8k_fw_unlock(hw);
2865 }
2866
2867 return rc;
2868 }
2869
2870 static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
2871 struct ieee80211_tx_queue_stats *stats)
2872 {
2873 struct mwl8k_priv *priv = hw->priv;
2874 struct mwl8k_tx_queue *txq;
2875 int index;
2876
2877 spin_lock_bh(&priv->tx_lock);
2878 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
2879 txq = priv->txq + index;
2880 memcpy(&stats[index], &txq->stats,
2881 sizeof(struct ieee80211_tx_queue_stats));
2882 }
2883 spin_unlock_bh(&priv->tx_lock);
2884
2885 return 0;
2886 }
2887
2888 static int mwl8k_get_stats(struct ieee80211_hw *hw,
2889 struct ieee80211_low_level_stats *stats)
2890 {
2891 return mwl8k_cmd_802_11_get_stat(hw, stats);
2892 }
2893
2894 static const struct ieee80211_ops mwl8k_ops = {
2895 .tx = mwl8k_tx,
2896 .start = mwl8k_start,
2897 .stop = mwl8k_stop,
2898 .add_interface = mwl8k_add_interface,
2899 .remove_interface = mwl8k_remove_interface,
2900 .config = mwl8k_config,
2901 .bss_info_changed = mwl8k_bss_info_changed,
2902 .prepare_multicast = mwl8k_prepare_multicast,
2903 .configure_filter = mwl8k_configure_filter,
2904 .set_rts_threshold = mwl8k_set_rts_threshold,
2905 .conf_tx = mwl8k_conf_tx,
2906 .get_tx_stats = mwl8k_get_tx_stats,
2907 .get_stats = mwl8k_get_stats,
2908 };
2909
2910 static void mwl8k_tx_reclaim_handler(unsigned long data)
2911 {
2912 int i;
2913 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
2914 struct mwl8k_priv *priv = hw->priv;
2915
2916 spin_lock_bh(&priv->tx_lock);
2917 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2918 mwl8k_txq_reclaim(hw, i, 0);
2919
2920 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
2921 complete(priv->tx_wait);
2922 priv->tx_wait = NULL;
2923 }
2924 spin_unlock_bh(&priv->tx_lock);
2925 }
2926
2927 static void mwl8k_finalize_join_worker(struct work_struct *work)
2928 {
2929 struct mwl8k_priv *priv =
2930 container_of(work, struct mwl8k_priv, finalize_join_worker);
2931 struct sk_buff *skb = priv->beacon_skb;
2932 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
2933
2934 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
2935 dev_kfree_skb(skb);
2936
2937 priv->beacon_skb = NULL;
2938 }
2939
2940 static struct mwl8k_device_info di_8687 = {
2941 .part_num = 8687,
2942 };
2943
2944 static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
2945 {
2946 PCI_VDEVICE(MARVELL, 0x2a2b),
2947 .driver_data = (unsigned long)&di_8687,
2948 }, {
2949 PCI_VDEVICE(MARVELL, 0x2a30),
2950 .driver_data = (unsigned long)&di_8687,
2951 }, {
2952 },
2953 };
2954 MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
2955
2956 static int __devinit mwl8k_probe(struct pci_dev *pdev,
2957 const struct pci_device_id *id)
2958 {
2959 static int printed_version = 0;
2960 struct ieee80211_hw *hw;
2961 struct mwl8k_priv *priv;
2962 int rc;
2963 int i;
2964
2965 if (!printed_version) {
2966 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
2967 printed_version = 1;
2968 }
2969
2970 rc = pci_enable_device(pdev);
2971 if (rc) {
2972 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
2973 MWL8K_NAME);
2974 return rc;
2975 }
2976
2977 rc = pci_request_regions(pdev, MWL8K_NAME);
2978 if (rc) {
2979 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
2980 MWL8K_NAME);
2981 return rc;
2982 }
2983
2984 pci_set_master(pdev);
2985
2986 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
2987 if (hw == NULL) {
2988 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
2989 rc = -ENOMEM;
2990 goto err_free_reg;
2991 }
2992
2993 priv = hw->priv;
2994 priv->hw = hw;
2995 priv->pdev = pdev;
2996 priv->device_info = (void *)id->driver_data;
2997 priv->sniffer_enabled = false;
2998 priv->wmm_enabled = false;
2999 priv->pending_tx_pkts = 0;
3000
3001 SET_IEEE80211_DEV(hw, &pdev->dev);
3002 pci_set_drvdata(pdev, hw);
3003
3004 priv->sram = pci_iomap(pdev, 0, 0x10000);
3005 if (priv->sram == NULL) {
3006 printk(KERN_ERR "%s: Cannot map device SRAM\n",
3007 wiphy_name(hw->wiphy));
3008 goto err_iounmap;
3009 }
3010
3011 /*
3012 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3013 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3014 */
3015 priv->regs = pci_iomap(pdev, 1, 0x10000);
3016 if (priv->regs == NULL) {
3017 priv->regs = pci_iomap(pdev, 2, 0x10000);
3018 if (priv->regs == NULL) {
3019 printk(KERN_ERR "%s: Cannot map device registers\n",
3020 wiphy_name(hw->wiphy));
3021 goto err_iounmap;
3022 }
3023 }
3024
3025 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3026 priv->band.band = IEEE80211_BAND_2GHZ;
3027 priv->band.channels = priv->channels;
3028 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3029 priv->band.bitrates = priv->rates;
3030 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3031 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3032
3033 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3034 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3035
3036 /*
3037 * Extra headroom is the size of the required DMA header
3038 * minus the size of the smallest 802.11 frame (CTS frame).
3039 */
3040 hw->extra_tx_headroom =
3041 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3042
3043 hw->channel_change_time = 10;
3044
3045 hw->queues = MWL8K_TX_QUEUES;
3046
3047 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
3048
3049 /* Set rssi and noise values to dBm */
3050 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
3051 hw->vif_data_size = sizeof(struct mwl8k_vif);
3052 priv->vif = NULL;
3053
3054 /* Set default radio state and preamble */
3055 priv->radio_on = 0;
3056 priv->radio_short_preamble = 0;
3057
3058 /* Finalize join worker */
3059 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3060
3061 /* TX reclaim tasklet */
3062 tasklet_init(&priv->tx_reclaim_task,
3063 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3064 tasklet_disable(&priv->tx_reclaim_task);
3065
3066 /* Power management cookie */
3067 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3068 if (priv->cookie == NULL)
3069 goto err_iounmap;
3070
3071 rc = mwl8k_rxq_init(hw, 0);
3072 if (rc)
3073 goto err_iounmap;
3074 rxq_refill(hw, 0, INT_MAX);
3075
3076 mutex_init(&priv->fw_mutex);
3077 priv->fw_mutex_owner = NULL;
3078 priv->fw_mutex_depth = 0;
3079 priv->hostcmd_wait = NULL;
3080
3081 spin_lock_init(&priv->tx_lock);
3082
3083 priv->tx_wait = NULL;
3084
3085 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3086 rc = mwl8k_txq_init(hw, i);
3087 if (rc)
3088 goto err_free_queues;
3089 }
3090
3091 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3092 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3093 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3094 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3095
3096 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
3097 IRQF_SHARED, MWL8K_NAME, hw);
3098 if (rc) {
3099 printk(KERN_ERR "%s: failed to register IRQ handler\n",
3100 wiphy_name(hw->wiphy));
3101 goto err_free_queues;
3102 }
3103
3104 /* Reset firmware and hardware */
3105 mwl8k_hw_reset(priv);
3106
3107 /* Ask userland hotplug daemon for the device firmware */
3108 rc = mwl8k_request_firmware(priv);
3109 if (rc) {
3110 printk(KERN_ERR "%s: Firmware files not found\n",
3111 wiphy_name(hw->wiphy));
3112 goto err_free_irq;
3113 }
3114
3115 /* Load firmware into hardware */
3116 rc = mwl8k_load_firmware(hw);
3117 if (rc) {
3118 printk(KERN_ERR "%s: Cannot start firmware\n",
3119 wiphy_name(hw->wiphy));
3120 goto err_stop_firmware;
3121 }
3122
3123 /* Reclaim memory once firmware is successfully loaded */
3124 mwl8k_release_firmware(priv);
3125
3126 /*
3127 * Temporarily enable interrupts. Initial firmware host
3128 * commands use interrupts and avoids polling. Disable
3129 * interrupts when done.
3130 */
3131 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3132
3133 /* Get config data, mac addrs etc */
3134 rc = mwl8k_cmd_get_hw_spec(hw);
3135 if (rc) {
3136 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3137 wiphy_name(hw->wiphy));
3138 goto err_stop_firmware;
3139 }
3140
3141 /* Turn radio off */
3142 rc = mwl8k_cmd_802_11_radio_disable(hw);
3143 if (rc) {
3144 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
3145 goto err_stop_firmware;
3146 }
3147
3148 /* Clear MAC address */
3149 rc = mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
3150 if (rc) {
3151 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3152 wiphy_name(hw->wiphy));
3153 goto err_stop_firmware;
3154 }
3155
3156 /* Disable interrupts */
3157 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3158 free_irq(priv->pdev->irq, hw);
3159
3160 rc = ieee80211_register_hw(hw);
3161 if (rc) {
3162 printk(KERN_ERR "%s: Cannot register device\n",
3163 wiphy_name(hw->wiphy));
3164 goto err_stop_firmware;
3165 }
3166
3167 printk(KERN_INFO "%s: 88w%u v%d, %pM, firmware version %u.%u.%u.%u\n",
3168 wiphy_name(hw->wiphy), priv->device_info->part_num,
3169 priv->hw_rev, hw->wiphy->perm_addr,
3170 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3171 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
3172
3173 return 0;
3174
3175 err_stop_firmware:
3176 mwl8k_hw_reset(priv);
3177 mwl8k_release_firmware(priv);
3178
3179 err_free_irq:
3180 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3181 free_irq(priv->pdev->irq, hw);
3182
3183 err_free_queues:
3184 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3185 mwl8k_txq_deinit(hw, i);
3186 mwl8k_rxq_deinit(hw, 0);
3187
3188 err_iounmap:
3189 if (priv->cookie != NULL)
3190 pci_free_consistent(priv->pdev, 4,
3191 priv->cookie, priv->cookie_dma);
3192
3193 if (priv->regs != NULL)
3194 pci_iounmap(pdev, priv->regs);
3195
3196 if (priv->sram != NULL)
3197 pci_iounmap(pdev, priv->sram);
3198
3199 pci_set_drvdata(pdev, NULL);
3200 ieee80211_free_hw(hw);
3201
3202 err_free_reg:
3203 pci_release_regions(pdev);
3204 pci_disable_device(pdev);
3205
3206 return rc;
3207 }
3208
3209 static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
3210 {
3211 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3212 }
3213
3214 static void __devexit mwl8k_remove(struct pci_dev *pdev)
3215 {
3216 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3217 struct mwl8k_priv *priv;
3218 int i;
3219
3220 if (hw == NULL)
3221 return;
3222 priv = hw->priv;
3223
3224 ieee80211_stop_queues(hw);
3225
3226 ieee80211_unregister_hw(hw);
3227
3228 /* Remove tx reclaim tasklet */
3229 tasklet_kill(&priv->tx_reclaim_task);
3230
3231 /* Stop hardware */
3232 mwl8k_hw_reset(priv);
3233
3234 /* Return all skbs to mac80211 */
3235 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3236 mwl8k_txq_reclaim(hw, i, 1);
3237
3238 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3239 mwl8k_txq_deinit(hw, i);
3240
3241 mwl8k_rxq_deinit(hw, 0);
3242
3243 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
3244
3245 pci_iounmap(pdev, priv->regs);
3246 pci_iounmap(pdev, priv->sram);
3247 pci_set_drvdata(pdev, NULL);
3248 ieee80211_free_hw(hw);
3249 pci_release_regions(pdev);
3250 pci_disable_device(pdev);
3251 }
3252
3253 static struct pci_driver mwl8k_driver = {
3254 .name = MWL8K_NAME,
3255 .id_table = mwl8k_pci_id_table,
3256 .probe = mwl8k_probe,
3257 .remove = __devexit_p(mwl8k_remove),
3258 .shutdown = __devexit_p(mwl8k_shutdown),
3259 };
3260
3261 static int __init mwl8k_init(void)
3262 {
3263 return pci_register_driver(&mwl8k_driver);
3264 }
3265
3266 static void __exit mwl8k_exit(void)
3267 {
3268 pci_unregister_driver(&mwl8k_driver);
3269 }
3270
3271 module_init(mwl8k_init);
3272 module_exit(mwl8k_exit);
3273
3274 MODULE_DESCRIPTION(MWL8K_DESC);
3275 MODULE_VERSION(MWL8K_VERSION);
3276 MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3277 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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