projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
mwl8k: pci BAR mapping changes
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
1 /*
2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
4 *
5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/sched.h>
16 #include <linux/spinlock.h>
17 #include <linux/list.h>
18 #include <linux/pci.h>
19 #include <linux/delay.h>
20 #include <linux/completion.h>
21 #include <linux/etherdevice.h>
22 #include <net/mac80211.h>
23 #include <linux/moduleparam.h>
24 #include <linux/firmware.h>
25 #include <linux/workqueue.h>
26
27 #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28 #define MWL8K_NAME KBUILD_MODNAME
29 #define MWL8K_VERSION "0.10"
30
31 static DEFINE_PCI_DEVICE_TABLE(mwl8k_table) = {
32 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = 8687, },
33 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = 8687, },
34 { }
35 };
36 MODULE_DEVICE_TABLE(pci, mwl8k_table);
37
38 /* Register definitions */
39 #define MWL8K_HIU_GEN_PTR 0x00000c10
40 #define MWL8K_MODE_STA 0x0000005a
41 #define MWL8K_MODE_AP 0x000000a5
42 #define MWL8K_HIU_INT_CODE 0x00000c14
43 #define MWL8K_FWSTA_READY 0xf0f1f2f4
44 #define MWL8K_FWAP_READY 0xf1f2f4a5
45 #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
46 #define MWL8K_HIU_SCRATCH 0x00000c40
47
48 /* Host->device communications */
49 #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
50 #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
51 #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
52 #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
53 #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
54 #define MWL8K_H2A_INT_DUMMY (1 << 20)
55 #define MWL8K_H2A_INT_RESET (1 << 15)
56 #define MWL8K_H2A_INT_DOORBELL (1 << 1)
57 #define MWL8K_H2A_INT_PPA_READY (1 << 0)
58
59 /* Device->host communications */
60 #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
61 #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
62 #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
63 #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
64 #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
65 #define MWL8K_A2H_INT_DUMMY (1 << 20)
66 #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
67 #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
68 #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
69 #define MWL8K_A2H_INT_RADIO_ON (1 << 6)
70 #define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
71 #define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
72 #define MWL8K_A2H_INT_OPC_DONE (1 << 2)
73 #define MWL8K_A2H_INT_RX_READY (1 << 1)
74 #define MWL8K_A2H_INT_TX_DONE (1 << 0)
75
76 #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
77 MWL8K_A2H_INT_CHNL_SWITCHED | \
78 MWL8K_A2H_INT_QUEUE_EMPTY | \
79 MWL8K_A2H_INT_RADAR_DETECT | \
80 MWL8K_A2H_INT_RADIO_ON | \
81 MWL8K_A2H_INT_RADIO_OFF | \
82 MWL8K_A2H_INT_MAC_EVENT | \
83 MWL8K_A2H_INT_OPC_DONE | \
84 MWL8K_A2H_INT_RX_READY | \
85 MWL8K_A2H_INT_TX_DONE)
86
87 #define MWL8K_RX_QUEUES 1
88 #define MWL8K_TX_QUEUES 4
89
90 struct mwl8k_rx_queue {
91 int rxd_count;
92
93 /* hw receives here */
94 int head;
95
96 /* refill descs here */
97 int tail;
98
99 struct mwl8k_rx_desc *rxd;
100 dma_addr_t rxd_dma;
101 struct sk_buff **skb;
102 };
103
104 struct mwl8k_tx_queue {
105 /* hw transmits here */
106 int head;
107
108 /* sw appends here */
109 int tail;
110
111 struct ieee80211_tx_queue_stats stats;
112 struct mwl8k_tx_desc *txd;
113 dma_addr_t txd_dma;
114 struct sk_buff **skb;
115 };
116
117 /* Pointers to the firmware data and meta information about it. */
118 struct mwl8k_firmware {
119 /* Microcode */
120 struct firmware *ucode;
121
122 /* Boot helper code */
123 struct firmware *helper;
124 };
125
126 struct mwl8k_priv {
127 void __iomem *sram;
128 void __iomem *regs;
129 struct ieee80211_hw *hw;
130
131 struct pci_dev *pdev;
132
133 /* firmware files and meta data */
134 struct mwl8k_firmware fw;
135 u32 part_num;
136
137 /* firmware access */
138 struct mutex fw_mutex;
139 struct task_struct *fw_mutex_owner;
140 int fw_mutex_depth;
141 struct completion *hostcmd_wait;
142
143 /* lock held over TX and TX reap */
144 spinlock_t tx_lock;
145
146 /* TX quiesce completion, protected by fw_mutex and tx_lock */
147 struct completion *tx_wait;
148
149 struct ieee80211_vif *vif;
150
151 struct ieee80211_channel *current_channel;
152
153 /* power management status cookie from firmware */
154 u32 *cookie;
155 dma_addr_t cookie_dma;
156
157 u16 num_mcaddrs;
158 u8 hw_rev;
159 u32 fw_rev;
160
161 /*
162 * Running count of TX packets in flight, to avoid
163 * iterating over the transmit rings each time.
164 */
165 int pending_tx_pkts;
166
167 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
168 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
169
170 /* PHY parameters */
171 struct ieee80211_supported_band band;
172 struct ieee80211_channel channels[14];
173 struct ieee80211_rate rates[13];
174
175 bool radio_on;
176 bool radio_short_preamble;
177 bool sniffer_enabled;
178 bool wmm_enabled;
179
180 /* XXX need to convert this to handle multiple interfaces */
181 bool capture_beacon;
182 u8 capture_bssid[ETH_ALEN];
183 struct sk_buff *beacon_skb;
184
185 /*
186 * This FJ worker has to be global as it is scheduled from the
187 * RX handler. At this point we don't know which interface it
188 * belongs to until the list of bssids waiting to complete join
189 * is checked.
190 */
191 struct work_struct finalize_join_worker;
192
193 /* Tasklet to reclaim TX descriptors and buffers after tx */
194 struct tasklet_struct tx_reclaim_task;
195 };
196
197 /* Per interface specific private data */
198 struct mwl8k_vif {
199 /* backpointer to parent config block */
200 struct mwl8k_priv *priv;
201
202 /* BSS config of AP or IBSS from mac80211*/
203 struct ieee80211_bss_conf bss_info;
204
205 /* BSSID of AP or IBSS */
206 u8 bssid[ETH_ALEN];
207 u8 mac_addr[ETH_ALEN];
208
209 /*
210 * Subset of supported legacy rates.
211 * Intersection of AP and STA supported rates.
212 */
213 struct ieee80211_rate legacy_rates[13];
214
215 /* number of supported legacy rates */
216 u8 legacy_nrates;
217
218 /* Index into station database.Returned by update_sta_db call */
219 u8 peer_id;
220
221 /* Non AMPDU sequence number assigned by driver */
222 u16 seqno;
223 };
224
225 #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
226
227 static const struct ieee80211_channel mwl8k_channels[] = {
228 { .center_freq = 2412, .hw_value = 1, },
229 { .center_freq = 2417, .hw_value = 2, },
230 { .center_freq = 2422, .hw_value = 3, },
231 { .center_freq = 2427, .hw_value = 4, },
232 { .center_freq = 2432, .hw_value = 5, },
233 { .center_freq = 2437, .hw_value = 6, },
234 { .center_freq = 2442, .hw_value = 7, },
235 { .center_freq = 2447, .hw_value = 8, },
236 { .center_freq = 2452, .hw_value = 9, },
237 { .center_freq = 2457, .hw_value = 10, },
238 { .center_freq = 2462, .hw_value = 11, },
239 };
240
241 static const struct ieee80211_rate mwl8k_rates[] = {
242 { .bitrate = 10, .hw_value = 2, },
243 { .bitrate = 20, .hw_value = 4, },
244 { .bitrate = 55, .hw_value = 11, },
245 { .bitrate = 110, .hw_value = 22, },
246 { .bitrate = 220, .hw_value = 44, },
247 { .bitrate = 60, .hw_value = 12, },
248 { .bitrate = 90, .hw_value = 18, },
249 { .bitrate = 120, .hw_value = 24, },
250 { .bitrate = 180, .hw_value = 36, },
251 { .bitrate = 240, .hw_value = 48, },
252 { .bitrate = 360, .hw_value = 72, },
253 { .bitrate = 480, .hw_value = 96, },
254 { .bitrate = 540, .hw_value = 108, },
255 };
256
257 /* Set or get info from Firmware */
258 #define MWL8K_CMD_SET 0x0001
259 #define MWL8K_CMD_GET 0x0000
260
261 /* Firmware command codes */
262 #define MWL8K_CMD_CODE_DNLD 0x0001
263 #define MWL8K_CMD_GET_HW_SPEC 0x0003
264 #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
265 #define MWL8K_CMD_GET_STAT 0x0014
266 #define MWL8K_CMD_RADIO_CONTROL 0x001c
267 #define MWL8K_CMD_RF_TX_POWER 0x001e
268 #define MWL8K_CMD_SET_PRE_SCAN 0x0107
269 #define MWL8K_CMD_SET_POST_SCAN 0x0108
270 #define MWL8K_CMD_SET_RF_CHANNEL 0x010a
271 #define MWL8K_CMD_SET_AID 0x010d
272 #define MWL8K_CMD_SET_RATE 0x0110
273 #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
274 #define MWL8K_CMD_RTS_THRESHOLD 0x0113
275 #define MWL8K_CMD_SET_SLOT 0x0114
276 #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
277 #define MWL8K_CMD_SET_WMM_MODE 0x0123
278 #define MWL8K_CMD_MIMO_CONFIG 0x0125
279 #define MWL8K_CMD_USE_FIXED_RATE 0x0126
280 #define MWL8K_CMD_ENABLE_SNIFFER 0x0150
281 #define MWL8K_CMD_SET_MAC_ADDR 0x0202
282 #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
283 #define MWL8K_CMD_UPDATE_STADB 0x1123
284
285 static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
286 {
287 #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
288 snprintf(buf, bufsize, "%s", #x);\
289 return buf;\
290 } while (0)
291 switch (cmd & ~0x8000) {
292 MWL8K_CMDNAME(CODE_DNLD);
293 MWL8K_CMDNAME(GET_HW_SPEC);
294 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
295 MWL8K_CMDNAME(GET_STAT);
296 MWL8K_CMDNAME(RADIO_CONTROL);
297 MWL8K_CMDNAME(RF_TX_POWER);
298 MWL8K_CMDNAME(SET_PRE_SCAN);
299 MWL8K_CMDNAME(SET_POST_SCAN);
300 MWL8K_CMDNAME(SET_RF_CHANNEL);
301 MWL8K_CMDNAME(SET_AID);
302 MWL8K_CMDNAME(SET_RATE);
303 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
304 MWL8K_CMDNAME(RTS_THRESHOLD);
305 MWL8K_CMDNAME(SET_SLOT);
306 MWL8K_CMDNAME(SET_EDCA_PARAMS);
307 MWL8K_CMDNAME(SET_WMM_MODE);
308 MWL8K_CMDNAME(MIMO_CONFIG);
309 MWL8K_CMDNAME(USE_FIXED_RATE);
310 MWL8K_CMDNAME(ENABLE_SNIFFER);
311 MWL8K_CMDNAME(SET_MAC_ADDR);
312 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
313 MWL8K_CMDNAME(UPDATE_STADB);
314 default:
315 snprintf(buf, bufsize, "0x%x", cmd);
316 }
317 #undef MWL8K_CMDNAME
318
319 return buf;
320 }
321
322 /* Hardware and firmware reset */
323 static void mwl8k_hw_reset(struct mwl8k_priv *priv)
324 {
325 iowrite32(MWL8K_H2A_INT_RESET,
326 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
327 iowrite32(MWL8K_H2A_INT_RESET,
328 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
329 msleep(20);
330 }
331
332 /* Release fw image */
333 static void mwl8k_release_fw(struct firmware **fw)
334 {
335 if (*fw == NULL)
336 return;
337 release_firmware(*fw);
338 *fw = NULL;
339 }
340
341 static void mwl8k_release_firmware(struct mwl8k_priv *priv)
342 {
343 mwl8k_release_fw(&priv->fw.ucode);
344 mwl8k_release_fw(&priv->fw.helper);
345 }
346
347 /* Request fw image */
348 static int mwl8k_request_fw(struct mwl8k_priv *priv,
349 const char *fname, struct firmware **fw)
350 {
351 /* release current image */
352 if (*fw != NULL)
353 mwl8k_release_fw(fw);
354
355 return request_firmware((const struct firmware **)fw,
356 fname, &priv->pdev->dev);
357 }
358
359 static int mwl8k_request_firmware(struct mwl8k_priv *priv, u32 part_num)
360 {
361 u8 filename[64];
362 int rc;
363
364 priv->part_num = part_num;
365
366 snprintf(filename, sizeof(filename),
367 "mwl8k/helper_%u.fw", priv->part_num);
368
369 rc = mwl8k_request_fw(priv, filename, &priv->fw.helper);
370 if (rc) {
371 printk(KERN_ERR "%s: Error requesting helper firmware "
372 "file %s\n", pci_name(priv->pdev), filename);
373 return rc;
374 }
375
376 snprintf(filename, sizeof(filename),
377 "mwl8k/fmimage_%u.fw", priv->part_num);
378
379 rc = mwl8k_request_fw(priv, filename, &priv->fw.ucode);
380 if (rc) {
381 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
382 pci_name(priv->pdev), filename);
383 mwl8k_release_fw(&priv->fw.helper);
384 return rc;
385 }
386
387 return 0;
388 }
389
390 struct mwl8k_cmd_pkt {
391 __le16 code;
392 __le16 length;
393 __le16 seq_num;
394 __le16 result;
395 char payload[0];
396 } __attribute__((packed));
397
398 /*
399 * Firmware loading.
400 */
401 static int
402 mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
403 {
404 void __iomem *regs = priv->regs;
405 dma_addr_t dma_addr;
406 int loops;
407
408 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
409 if (pci_dma_mapping_error(priv->pdev, dma_addr))
410 return -ENOMEM;
411
412 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
413 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
414 iowrite32(MWL8K_H2A_INT_DOORBELL,
415 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
416 iowrite32(MWL8K_H2A_INT_DUMMY,
417 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
418
419 loops = 1000;
420 do {
421 u32 int_code;
422
423 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
424 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
425 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
426 break;
427 }
428
429 cond_resched();
430 udelay(1);
431 } while (--loops);
432
433 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
434
435 return loops ? 0 : -ETIMEDOUT;
436 }
437
438 static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
439 const u8 *data, size_t length)
440 {
441 struct mwl8k_cmd_pkt *cmd;
442 int done;
443 int rc = 0;
444
445 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
446 if (cmd == NULL)
447 return -ENOMEM;
448
449 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
450 cmd->seq_num = 0;
451 cmd->result = 0;
452
453 done = 0;
454 while (length) {
455 int block_size = length > 256 ? 256 : length;
456
457 memcpy(cmd->payload, data + done, block_size);
458 cmd->length = cpu_to_le16(block_size);
459
460 rc = mwl8k_send_fw_load_cmd(priv, cmd,
461 sizeof(*cmd) + block_size);
462 if (rc)
463 break;
464
465 done += block_size;
466 length -= block_size;
467 }
468
469 if (!rc) {
470 cmd->length = 0;
471 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
472 }
473
474 kfree(cmd);
475
476 return rc;
477 }
478
479 static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
480 const u8 *data, size_t length)
481 {
482 unsigned char *buffer;
483 int may_continue, rc = 0;
484 u32 done, prev_block_size;
485
486 buffer = kmalloc(1024, GFP_KERNEL);
487 if (buffer == NULL)
488 return -ENOMEM;
489
490 done = 0;
491 prev_block_size = 0;
492 may_continue = 1000;
493 while (may_continue > 0) {
494 u32 block_size;
495
496 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
497 if (block_size & 1) {
498 block_size &= ~1;
499 may_continue--;
500 } else {
501 done += prev_block_size;
502 length -= prev_block_size;
503 }
504
505 if (block_size > 1024 || block_size > length) {
506 rc = -EOVERFLOW;
507 break;
508 }
509
510 if (length == 0) {
511 rc = 0;
512 break;
513 }
514
515 if (block_size == 0) {
516 rc = -EPROTO;
517 may_continue--;
518 udelay(1);
519 continue;
520 }
521
522 prev_block_size = block_size;
523 memcpy(buffer, data + done, block_size);
524
525 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
526 if (rc)
527 break;
528 }
529
530 if (!rc && length != 0)
531 rc = -EREMOTEIO;
532
533 kfree(buffer);
534
535 return rc;
536 }
537
538 static int mwl8k_load_firmware(struct ieee80211_hw *hw)
539 {
540 struct mwl8k_priv *priv = hw->priv;
541 struct firmware *fw = priv->fw.ucode;
542 int rc;
543 int loops;
544
545 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
546 struct firmware *helper = priv->fw.helper;
547
548 if (helper == NULL) {
549 printk(KERN_ERR "%s: helper image needed but none "
550 "given\n", pci_name(priv->pdev));
551 return -EINVAL;
552 }
553
554 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
555 if (rc) {
556 printk(KERN_ERR "%s: unable to load firmware "
557 "helper image\n", pci_name(priv->pdev));
558 return rc;
559 }
560 msleep(1);
561
562 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
563 } else {
564 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
565 }
566
567 if (rc) {
568 printk(KERN_ERR "%s: unable to load firmware image\n",
569 pci_name(priv->pdev));
570 return rc;
571 }
572
573 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
574 msleep(1);
575
576 loops = 200000;
577 do {
578 if (ioread32(priv->regs + MWL8K_HIU_INT_CODE)
579 == MWL8K_FWSTA_READY)
580 break;
581 udelay(1);
582 } while (--loops);
583
584 return loops ? 0 : -ETIMEDOUT;
585 }
586
587
588 /*
589 * Defines shared between transmission and reception.
590 */
591 /* HT control fields for firmware */
592 struct ewc_ht_info {
593 __le16 control1;
594 __le16 control2;
595 __le16 control3;
596 } __attribute__((packed));
597
598 /* Firmware Station database operations */
599 #define MWL8K_STA_DB_ADD_ENTRY 0
600 #define MWL8K_STA_DB_MODIFY_ENTRY 1
601 #define MWL8K_STA_DB_DEL_ENTRY 2
602 #define MWL8K_STA_DB_FLUSH 3
603
604 /* Peer Entry flags - used to define the type of the peer node */
605 #define MWL8K_PEER_TYPE_ACCESSPOINT 2
606
607 #define MWL8K_IEEE_LEGACY_DATA_RATES 13
608 #define MWL8K_MCS_BITMAP_SIZE 16
609
610 struct peer_capability_info {
611 /* Peer type - AP vs. STA. */
612 __u8 peer_type;
613
614 /* Basic 802.11 capabilities from assoc resp. */
615 __le16 basic_caps;
616
617 /* Set if peer supports 802.11n high throughput (HT). */
618 __u8 ht_support;
619
620 /* Valid if HT is supported. */
621 __le16 ht_caps;
622 __u8 extended_ht_caps;
623 struct ewc_ht_info ewc_info;
624
625 /* Legacy rate table. Intersection of our rates and peer rates. */
626 __u8 legacy_rates[MWL8K_IEEE_LEGACY_DATA_RATES];
627
628 /* HT rate table. Intersection of our rates and peer rates. */
629 __u8 ht_rates[MWL8K_MCS_BITMAP_SIZE];
630 __u8 pad[16];
631
632 /* If set, interoperability mode, no proprietary extensions. */
633 __u8 interop;
634 __u8 pad2;
635 __u8 station_id;
636 __le16 amsdu_enabled;
637 } __attribute__((packed));
638
639 /* Inline functions to manipulate QoS field in data descriptor. */
640 static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
641 {
642 u16 val_mask = 1 << 4;
643
644 /* End of Service Period Bit 4 */
645 return qos | val_mask;
646 }
647
648 static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
649 {
650 u16 val_mask = 0x3;
651 u8 shift = 5;
652 u16 qos_mask = ~(val_mask << shift);
653
654 /* Ack Policy Bit 5-6 */
655 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
656 }
657
658 static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
659 {
660 u16 val_mask = 1 << 7;
661
662 /* AMSDU present Bit 7 */
663 return qos | val_mask;
664 }
665
666 static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
667 {
668 u16 val_mask = 0xff;
669 u8 shift = 8;
670 u16 qos_mask = ~(val_mask << shift);
671
672 /* Queue Length Bits 8-15 */
673 return (qos & qos_mask) | ((len & val_mask) << shift);
674 }
675
676 /* DMA header used by firmware and hardware. */
677 struct mwl8k_dma_data {
678 __le16 fwlen;
679 struct ieee80211_hdr wh;
680 } __attribute__((packed));
681
682 /* Routines to add/remove DMA header from skb. */
683 static inline void mwl8k_remove_dma_header(struct sk_buff *skb)
684 {
685 struct mwl8k_dma_data *tr = (struct mwl8k_dma_data *)skb->data;
686 void *dst, *src = &tr->wh;
687 int hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
688 u16 space = sizeof(struct mwl8k_dma_data) - hdrlen;
689
690 dst = (void *)tr + space;
691 if (dst != src) {
692 memmove(dst, src, hdrlen);
693 skb_pull(skb, space);
694 }
695 }
696
697 static inline void mwl8k_add_dma_header(struct sk_buff *skb)
698 {
699 struct ieee80211_hdr *wh;
700 u32 hdrlen, pktlen;
701 struct mwl8k_dma_data *tr;
702
703 wh = (struct ieee80211_hdr *)skb->data;
704 hdrlen = ieee80211_hdrlen(wh->frame_control);
705 pktlen = skb->len;
706
707 /*
708 * Copy up/down the 802.11 header; the firmware requires
709 * we present a 2-byte payload length followed by a
710 * 4-address header (w/o QoS), followed (optionally) by
711 * any WEP/ExtIV header (but only filled in for CCMP).
712 */
713 if (hdrlen != sizeof(struct mwl8k_dma_data))
714 skb_push(skb, sizeof(struct mwl8k_dma_data) - hdrlen);
715
716 tr = (struct mwl8k_dma_data *)skb->data;
717 if (wh != &tr->wh)
718 memmove(&tr->wh, wh, hdrlen);
719
720 /* Clear addr4 */
721 memset(tr->wh.addr4, 0, ETH_ALEN);
722
723 /*
724 * Firmware length is the length of the fully formed "802.11
725 * payload". That is, everything except for the 802.11 header.
726 * This includes all crypto material including the MIC.
727 */
728 tr->fwlen = cpu_to_le16(pktlen - hdrlen);
729 }
730
731
732 /*
733 * Packet reception.
734 */
735 #define MWL8K_RX_CTRL_OWNED_BY_HOST 0x02
736
737 struct mwl8k_rx_desc {
738 __le16 pkt_len;
739 __u8 link_quality;
740 __u8 noise_level;
741 __le32 pkt_phys_addr;
742 __le32 next_rxd_phys_addr;
743 __le16 qos_control;
744 __le16 rate_info;
745 __le32 pad0[4];
746 __u8 rssi;
747 __u8 channel;
748 __le16 pad1;
749 __u8 rx_ctrl;
750 __u8 rx_status;
751 __u8 pad2[2];
752 } __attribute__((packed));
753
754 #define MWL8K_RX_DESCS 256
755 #define MWL8K_RX_MAXSZ 3800
756
757 #define RATE_INFO_SHORTPRE 0x8000
758 #define RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
759 #define RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
760 #define RATE_INFO_40MHZ 0x0004
761 #define RATE_INFO_SHORTGI 0x0002
762 #define RATE_INFO_MCS_FORMAT 0x0001
763
764 static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
765 {
766 struct mwl8k_priv *priv = hw->priv;
767 struct mwl8k_rx_queue *rxq = priv->rxq + index;
768 int size;
769 int i;
770
771 rxq->rxd_count = 0;
772 rxq->head = 0;
773 rxq->tail = 0;
774
775 size = MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc);
776
777 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
778 if (rxq->rxd == NULL) {
779 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
780 wiphy_name(hw->wiphy));
781 return -ENOMEM;
782 }
783 memset(rxq->rxd, 0, size);
784
785 rxq->skb = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->skb), GFP_KERNEL);
786 if (rxq->skb == NULL) {
787 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
788 wiphy_name(hw->wiphy));
789 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
790 return -ENOMEM;
791 }
792 memset(rxq->skb, 0, MWL8K_RX_DESCS * sizeof(*rxq->skb));
793
794 for (i = 0; i < MWL8K_RX_DESCS; i++) {
795 struct mwl8k_rx_desc *rx_desc;
796 int nexti;
797
798 rx_desc = rxq->rxd + i;
799 nexti = (i + 1) % MWL8K_RX_DESCS;
800
801 rx_desc->next_rxd_phys_addr =
802 cpu_to_le32(rxq->rxd_dma + nexti * sizeof(*rx_desc));
803 rx_desc->rx_ctrl = MWL8K_RX_CTRL_OWNED_BY_HOST;
804 }
805
806 return 0;
807 }
808
809 static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
810 {
811 struct mwl8k_priv *priv = hw->priv;
812 struct mwl8k_rx_queue *rxq = priv->rxq + index;
813 int refilled;
814
815 refilled = 0;
816 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
817 struct sk_buff *skb;
818 int rx;
819
820 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
821 if (skb == NULL)
822 break;
823
824 rxq->rxd_count++;
825
826 rx = rxq->tail;
827 rxq->tail = (rx + 1) % MWL8K_RX_DESCS;
828
829 rxq->rxd[rx].pkt_phys_addr =
830 cpu_to_le32(pci_map_single(priv->pdev, skb->data,
831 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE));
832
833 rxq->rxd[rx].pkt_len = cpu_to_le16(MWL8K_RX_MAXSZ);
834 rxq->skb[rx] = skb;
835 wmb();
836 rxq->rxd[rx].rx_ctrl = 0;
837
838 refilled++;
839 }
840
841 return refilled;
842 }
843
844 /* Must be called only when the card's reception is completely halted */
845 static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
846 {
847 struct mwl8k_priv *priv = hw->priv;
848 struct mwl8k_rx_queue *rxq = priv->rxq + index;
849 int i;
850
851 for (i = 0; i < MWL8K_RX_DESCS; i++) {
852 if (rxq->skb[i] != NULL) {
853 unsigned long addr;
854
855 addr = le32_to_cpu(rxq->rxd[i].pkt_phys_addr);
856 pci_unmap_single(priv->pdev, addr, MWL8K_RX_MAXSZ,
857 PCI_DMA_FROMDEVICE);
858 kfree_skb(rxq->skb[i]);
859 rxq->skb[i] = NULL;
860 }
861 }
862
863 kfree(rxq->skb);
864 rxq->skb = NULL;
865
866 pci_free_consistent(priv->pdev,
867 MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc),
868 rxq->rxd, rxq->rxd_dma);
869 rxq->rxd = NULL;
870 }
871
872
873 /*
874 * Scan a list of BSSIDs to process for finalize join.
875 * Allows for extension to process multiple BSSIDs.
876 */
877 static inline int
878 mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
879 {
880 return priv->capture_beacon &&
881 ieee80211_is_beacon(wh->frame_control) &&
882 !compare_ether_addr(wh->addr3, priv->capture_bssid);
883 }
884
885 static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
886 struct sk_buff *skb)
887 {
888 struct mwl8k_priv *priv = hw->priv;
889
890 priv->capture_beacon = false;
891 memset(priv->capture_bssid, 0, ETH_ALEN);
892
893 /*
894 * Use GFP_ATOMIC as rxq_process is called from
895 * the primary interrupt handler, memory allocation call
896 * must not sleep.
897 */
898 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
899 if (priv->beacon_skb != NULL)
900 ieee80211_queue_work(hw, &priv->finalize_join_worker);
901 }
902
903 static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
904 {
905 struct mwl8k_priv *priv = hw->priv;
906 struct mwl8k_rx_queue *rxq = priv->rxq + index;
907 int processed;
908
909 processed = 0;
910 while (rxq->rxd_count && limit--) {
911 struct mwl8k_rx_desc *rx_desc;
912 struct sk_buff *skb;
913 struct ieee80211_rx_status status;
914 unsigned long addr;
915 struct ieee80211_hdr *wh;
916 u16 rate_info;
917
918 rx_desc = rxq->rxd + rxq->head;
919 if (!(rx_desc->rx_ctrl & MWL8K_RX_CTRL_OWNED_BY_HOST))
920 break;
921 rmb();
922
923 skb = rxq->skb[rxq->head];
924 if (skb == NULL)
925 break;
926 rxq->skb[rxq->head] = NULL;
927
928 rxq->head = (rxq->head + 1) % MWL8K_RX_DESCS;
929 rxq->rxd_count--;
930
931 addr = le32_to_cpu(rx_desc->pkt_phys_addr);
932 pci_unmap_single(priv->pdev, addr,
933 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
934
935 skb_put(skb, le16_to_cpu(rx_desc->pkt_len));
936 mwl8k_remove_dma_header(skb);
937
938 wh = (struct ieee80211_hdr *)skb->data;
939
940 /*
941 * Check for a pending join operation. Save a
942 * copy of the beacon and schedule a tasklet to
943 * send a FINALIZE_JOIN command to the firmware.
944 */
945 if (mwl8k_capture_bssid(priv, wh))
946 mwl8k_save_beacon(hw, skb);
947
948 rate_info = le16_to_cpu(rx_desc->rate_info);
949
950 memset(&status, 0, sizeof(status));
951 status.mactime = 0;
952 status.signal = -rx_desc->rssi;
953 status.noise = -rx_desc->noise_level;
954 status.qual = rx_desc->link_quality;
955 status.antenna = RATE_INFO_ANTSELECT(rate_info);
956 status.rate_idx = RATE_INFO_RATEID(rate_info);
957 status.flag = 0;
958 if (rate_info & RATE_INFO_SHORTPRE)
959 status.flag |= RX_FLAG_SHORTPRE;
960 if (rate_info & RATE_INFO_40MHZ)
961 status.flag |= RX_FLAG_40MHZ;
962 if (rate_info & RATE_INFO_SHORTGI)
963 status.flag |= RX_FLAG_SHORT_GI;
964 if (rate_info & RATE_INFO_MCS_FORMAT)
965 status.flag |= RX_FLAG_HT;
966 status.band = IEEE80211_BAND_2GHZ;
967 status.freq = ieee80211_channel_to_frequency(rx_desc->channel);
968 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
969 ieee80211_rx_irqsafe(hw, skb);
970
971 processed++;
972 }
973
974 return processed;
975 }
976
977
978 /*
979 * Packet transmission.
980 */
981
982 /* Transmit packet ACK policy */
983 #define MWL8K_TXD_ACK_POLICY_NORMAL 0
984 #define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
985
986 #define MWL8K_TXD_STATUS_OK 0x00000001
987 #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
988 #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
989 #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
990 #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
991
992 struct mwl8k_tx_desc {
993 __le32 status;
994 __u8 data_rate;
995 __u8 tx_priority;
996 __le16 qos_control;
997 __le32 pkt_phys_addr;
998 __le16 pkt_len;
999 __u8 dest_MAC_addr[ETH_ALEN];
1000 __le32 next_txd_phys_addr;
1001 __le32 reserved;
1002 __le16 rate_info;
1003 __u8 peer_id;
1004 __u8 tx_frag_cnt;
1005 } __attribute__((packed));
1006
1007 #define MWL8K_TX_DESCS 128
1008
1009 static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1010 {
1011 struct mwl8k_priv *priv = hw->priv;
1012 struct mwl8k_tx_queue *txq = priv->txq + index;
1013 int size;
1014 int i;
1015
1016 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1017 txq->stats.limit = MWL8K_TX_DESCS;
1018 txq->head = 0;
1019 txq->tail = 0;
1020
1021 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1022
1023 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1024 if (txq->txd == NULL) {
1025 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
1026 wiphy_name(hw->wiphy));
1027 return -ENOMEM;
1028 }
1029 memset(txq->txd, 0, size);
1030
1031 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1032 if (txq->skb == NULL) {
1033 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
1034 wiphy_name(hw->wiphy));
1035 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
1036 return -ENOMEM;
1037 }
1038 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
1039
1040 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1041 struct mwl8k_tx_desc *tx_desc;
1042 int nexti;
1043
1044 tx_desc = txq->txd + i;
1045 nexti = (i + 1) % MWL8K_TX_DESCS;
1046
1047 tx_desc->status = 0;
1048 tx_desc->next_txd_phys_addr =
1049 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
1050 }
1051
1052 return 0;
1053 }
1054
1055 static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1056 {
1057 iowrite32(MWL8K_H2A_INT_PPA_READY,
1058 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1059 iowrite32(MWL8K_H2A_INT_DUMMY,
1060 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1061 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1062 }
1063
1064 struct mwl8k_txq_info {
1065 u32 fw_owned;
1066 u32 drv_owned;
1067 u32 unused;
1068 u32 len;
1069 u32 head;
1070 u32 tail;
1071 };
1072
1073 static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
1074 struct mwl8k_txq_info *txinfo)
1075 {
1076 int count, desc, status;
1077 struct mwl8k_tx_queue *txq;
1078 struct mwl8k_tx_desc *tx_desc;
1079 int ndescs = 0;
1080
1081 memset(txinfo, 0, MWL8K_TX_QUEUES * sizeof(struct mwl8k_txq_info));
1082
1083 for (count = 0; count < MWL8K_TX_QUEUES; count++) {
1084 txq = priv->txq + count;
1085 txinfo[count].len = txq->stats.len;
1086 txinfo[count].head = txq->head;
1087 txinfo[count].tail = txq->tail;
1088 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1089 tx_desc = txq->txd + desc;
1090 status = le32_to_cpu(tx_desc->status);
1091
1092 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1093 txinfo[count].fw_owned++;
1094 else
1095 txinfo[count].drv_owned++;
1096
1097 if (tx_desc->pkt_len == 0)
1098 txinfo[count].unused++;
1099 }
1100 }
1101
1102 return ndescs;
1103 }
1104
1105 /*
1106 * Must be called with priv->fw_mutex held and tx queues stopped.
1107 */
1108 static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
1109 {
1110 struct mwl8k_priv *priv = hw->priv;
1111 DECLARE_COMPLETION_ONSTACK(tx_wait);
1112 u32 count;
1113 unsigned long timeout;
1114
1115 might_sleep();
1116
1117 spin_lock_bh(&priv->tx_lock);
1118 count = priv->pending_tx_pkts;
1119 if (count)
1120 priv->tx_wait = &tx_wait;
1121 spin_unlock_bh(&priv->tx_lock);
1122
1123 if (count) {
1124 struct mwl8k_txq_info txinfo[MWL8K_TX_QUEUES];
1125 int index;
1126 int newcount;
1127
1128 timeout = wait_for_completion_timeout(&tx_wait,
1129 msecs_to_jiffies(5000));
1130 if (timeout)
1131 return 0;
1132
1133 spin_lock_bh(&priv->tx_lock);
1134 priv->tx_wait = NULL;
1135 newcount = priv->pending_tx_pkts;
1136 mwl8k_scan_tx_ring(priv, txinfo);
1137 spin_unlock_bh(&priv->tx_lock);
1138
1139 printk(KERN_ERR "%s(%u) TIMEDOUT:5000ms Pend:%u-->%u\n",
1140 __func__, __LINE__, count, newcount);
1141
1142 for (index = 0; index < MWL8K_TX_QUEUES; index++)
1143 printk(KERN_ERR "TXQ:%u L:%u H:%u T:%u FW:%u "
1144 "DRV:%u U:%u\n",
1145 index,
1146 txinfo[index].len,
1147 txinfo[index].head,
1148 txinfo[index].tail,
1149 txinfo[index].fw_owned,
1150 txinfo[index].drv_owned,
1151 txinfo[index].unused);
1152
1153 return -ETIMEDOUT;
1154 }
1155
1156 return 0;
1157 }
1158
1159 #define MWL8K_TXD_SUCCESS(status) \
1160 ((status) & (MWL8K_TXD_STATUS_OK | \
1161 MWL8K_TXD_STATUS_OK_RETRY | \
1162 MWL8K_TXD_STATUS_OK_MORE_RETRY))
1163
1164 static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1165 {
1166 struct mwl8k_priv *priv = hw->priv;
1167 struct mwl8k_tx_queue *txq = priv->txq + index;
1168 int wake = 0;
1169
1170 while (txq->stats.len > 0) {
1171 int tx;
1172 struct mwl8k_tx_desc *tx_desc;
1173 unsigned long addr;
1174 int size;
1175 struct sk_buff *skb;
1176 struct ieee80211_tx_info *info;
1177 u32 status;
1178
1179 tx = txq->head;
1180 tx_desc = txq->txd + tx;
1181
1182 status = le32_to_cpu(tx_desc->status);
1183
1184 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1185 if (!force)
1186 break;
1187 tx_desc->status &=
1188 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1189 }
1190
1191 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1192 BUG_ON(txq->stats.len == 0);
1193 txq->stats.len--;
1194 priv->pending_tx_pkts--;
1195
1196 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
1197 size = le16_to_cpu(tx_desc->pkt_len);
1198 skb = txq->skb[tx];
1199 txq->skb[tx] = NULL;
1200
1201 BUG_ON(skb == NULL);
1202 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1203
1204 mwl8k_remove_dma_header(skb);
1205
1206 /* Mark descriptor as unused */
1207 tx_desc->pkt_phys_addr = 0;
1208 tx_desc->pkt_len = 0;
1209
1210 info = IEEE80211_SKB_CB(skb);
1211 ieee80211_tx_info_clear_status(info);
1212 if (MWL8K_TXD_SUCCESS(status))
1213 info->flags |= IEEE80211_TX_STAT_ACK;
1214
1215 ieee80211_tx_status_irqsafe(hw, skb);
1216
1217 wake = 1;
1218 }
1219
1220 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
1221 ieee80211_wake_queue(hw, index);
1222 }
1223
1224 /* must be called only when the card's transmit is completely halted */
1225 static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1226 {
1227 struct mwl8k_priv *priv = hw->priv;
1228 struct mwl8k_tx_queue *txq = priv->txq + index;
1229
1230 mwl8k_txq_reclaim(hw, index, 1);
1231
1232 kfree(txq->skb);
1233 txq->skb = NULL;
1234
1235 pci_free_consistent(priv->pdev,
1236 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1237 txq->txd, txq->txd_dma);
1238 txq->txd = NULL;
1239 }
1240
1241 static int
1242 mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1243 {
1244 struct mwl8k_priv *priv = hw->priv;
1245 struct ieee80211_tx_info *tx_info;
1246 struct mwl8k_vif *mwl8k_vif;
1247 struct ieee80211_hdr *wh;
1248 struct mwl8k_tx_queue *txq;
1249 struct mwl8k_tx_desc *tx;
1250 dma_addr_t dma;
1251 u32 txstatus;
1252 u8 txdatarate;
1253 u16 qos;
1254
1255 wh = (struct ieee80211_hdr *)skb->data;
1256 if (ieee80211_is_data_qos(wh->frame_control))
1257 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1258 else
1259 qos = 0;
1260
1261 mwl8k_add_dma_header(skb);
1262 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
1263
1264 tx_info = IEEE80211_SKB_CB(skb);
1265 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
1266
1267 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1268 u16 seqno = mwl8k_vif->seqno;
1269
1270 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1271 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1272 mwl8k_vif->seqno = seqno++ % 4096;
1273 }
1274
1275 /* Setup firmware control bit fields for each frame type. */
1276 txstatus = 0;
1277 txdatarate = 0;
1278 if (ieee80211_is_mgmt(wh->frame_control) ||
1279 ieee80211_is_ctl(wh->frame_control)) {
1280 txdatarate = 0;
1281 qos = mwl8k_qos_setbit_eosp(qos);
1282 /* Set Queue size to unspecified */
1283 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1284 } else if (ieee80211_is_data(wh->frame_control)) {
1285 txdatarate = 1;
1286 if (is_multicast_ether_addr(wh->addr1))
1287 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1288
1289 /* Send pkt in an aggregate if AMPDU frame. */
1290 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1291 qos = mwl8k_qos_setbit_ack(qos,
1292 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1293 else
1294 qos = mwl8k_qos_setbit_ack(qos,
1295 MWL8K_TXD_ACK_POLICY_NORMAL);
1296
1297 if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
1298 qos = mwl8k_qos_setbit_amsdu(qos);
1299 }
1300
1301 dma = pci_map_single(priv->pdev, skb->data,
1302 skb->len, PCI_DMA_TODEVICE);
1303
1304 if (pci_dma_mapping_error(priv->pdev, dma)) {
1305 printk(KERN_DEBUG "%s: failed to dma map skb, "
1306 "dropping TX frame.\n", wiphy_name(hw->wiphy));
1307 dev_kfree_skb(skb);
1308 return NETDEV_TX_OK;
1309 }
1310
1311 spin_lock_bh(&priv->tx_lock);
1312
1313 txq = priv->txq + index;
1314
1315 BUG_ON(txq->skb[txq->tail] != NULL);
1316 txq->skb[txq->tail] = skb;
1317
1318 tx = txq->txd + txq->tail;
1319 tx->data_rate = txdatarate;
1320 tx->tx_priority = index;
1321 tx->qos_control = cpu_to_le16(qos);
1322 tx->pkt_phys_addr = cpu_to_le32(dma);
1323 tx->pkt_len = cpu_to_le16(skb->len);
1324 tx->rate_info = 0;
1325 tx->peer_id = mwl8k_vif->peer_id;
1326 wmb();
1327 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1328
1329 txq->stats.count++;
1330 txq->stats.len++;
1331 priv->pending_tx_pkts++;
1332
1333 txq->tail++;
1334 if (txq->tail == MWL8K_TX_DESCS)
1335 txq->tail = 0;
1336
1337 if (txq->head == txq->tail)
1338 ieee80211_stop_queue(hw, index);
1339
1340 mwl8k_tx_start(priv);
1341
1342 spin_unlock_bh(&priv->tx_lock);
1343
1344 return NETDEV_TX_OK;
1345 }
1346
1347
1348 /*
1349 * Firmware access.
1350 *
1351 * We have the following requirements for issuing firmware commands:
1352 * - Some commands require that the packet transmit path is idle when
1353 * the command is issued. (For simplicity, we'll just quiesce the
1354 * transmit path for every command.)
1355 * - There are certain sequences of commands that need to be issued to
1356 * the hardware sequentially, with no other intervening commands.
1357 *
1358 * This leads to an implementation of a "firmware lock" as a mutex that
1359 * can be taken recursively, and which is taken by both the low-level
1360 * command submission function (mwl8k_post_cmd) as well as any users of
1361 * that function that require issuing of an atomic sequence of commands,
1362 * and quiesces the transmit path whenever it's taken.
1363 */
1364 static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1365 {
1366 struct mwl8k_priv *priv = hw->priv;
1367
1368 if (priv->fw_mutex_owner != current) {
1369 int rc;
1370
1371 mutex_lock(&priv->fw_mutex);
1372 ieee80211_stop_queues(hw);
1373
1374 rc = mwl8k_tx_wait_empty(hw);
1375 if (rc) {
1376 ieee80211_wake_queues(hw);
1377 mutex_unlock(&priv->fw_mutex);
1378
1379 return rc;
1380 }
1381
1382 priv->fw_mutex_owner = current;
1383 }
1384
1385 priv->fw_mutex_depth++;
1386
1387 return 0;
1388 }
1389
1390 static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1391 {
1392 struct mwl8k_priv *priv = hw->priv;
1393
1394 if (!--priv->fw_mutex_depth) {
1395 ieee80211_wake_queues(hw);
1396 priv->fw_mutex_owner = NULL;
1397 mutex_unlock(&priv->fw_mutex);
1398 }
1399 }
1400
1401
1402 /*
1403 * Command processing.
1404 */
1405
1406 /* Timeout firmware commands after 2000ms */
1407 #define MWL8K_CMD_TIMEOUT_MS 2000
1408
1409 static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1410 {
1411 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1412 struct mwl8k_priv *priv = hw->priv;
1413 void __iomem *regs = priv->regs;
1414 dma_addr_t dma_addr;
1415 unsigned int dma_size;
1416 int rc;
1417 unsigned long timeout = 0;
1418 u8 buf[32];
1419
1420 cmd->result = 0xffff;
1421 dma_size = le16_to_cpu(cmd->length);
1422 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1423 PCI_DMA_BIDIRECTIONAL);
1424 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1425 return -ENOMEM;
1426
1427 rc = mwl8k_fw_lock(hw);
1428 if (rc) {
1429 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1430 PCI_DMA_BIDIRECTIONAL);
1431 return rc;
1432 }
1433
1434 priv->hostcmd_wait = &cmd_wait;
1435 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1436 iowrite32(MWL8K_H2A_INT_DOORBELL,
1437 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1438 iowrite32(MWL8K_H2A_INT_DUMMY,
1439 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1440
1441 timeout = wait_for_completion_timeout(&cmd_wait,
1442 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1443
1444 priv->hostcmd_wait = NULL;
1445
1446 mwl8k_fw_unlock(hw);
1447
1448 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1449 PCI_DMA_BIDIRECTIONAL);
1450
1451 if (!timeout) {
1452 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
1453 wiphy_name(hw->wiphy),
1454 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1455 MWL8K_CMD_TIMEOUT_MS);
1456 rc = -ETIMEDOUT;
1457 } else {
1458 rc = cmd->result ? -EINVAL : 0;
1459 if (rc)
1460 printk(KERN_ERR "%s: Command %s error 0x%x\n",
1461 wiphy_name(hw->wiphy),
1462 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1463 le16_to_cpu(cmd->result));
1464 }
1465
1466 return rc;
1467 }
1468
1469 /*
1470 * GET_HW_SPEC.
1471 */
1472 struct mwl8k_cmd_get_hw_spec {
1473 struct mwl8k_cmd_pkt header;
1474 __u8 hw_rev;
1475 __u8 host_interface;
1476 __le16 num_mcaddrs;
1477 __u8 perm_addr[ETH_ALEN];
1478 __le16 region_code;
1479 __le32 fw_rev;
1480 __le32 ps_cookie;
1481 __le32 caps;
1482 __u8 mcs_bitmap[16];
1483 __le32 rx_queue_ptr;
1484 __le32 num_tx_queues;
1485 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1486 __le32 caps2;
1487 __le32 num_tx_desc_per_queue;
1488 __le32 total_rxd;
1489 } __attribute__((packed));
1490
1491 static int mwl8k_cmd_get_hw_spec(struct ieee80211_hw *hw)
1492 {
1493 struct mwl8k_priv *priv = hw->priv;
1494 struct mwl8k_cmd_get_hw_spec *cmd;
1495 int rc;
1496 int i;
1497
1498 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1499 if (cmd == NULL)
1500 return -ENOMEM;
1501
1502 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1503 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1504
1505 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1506 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1507 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1508 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1509 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1510 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1511 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1512 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1513
1514 rc = mwl8k_post_cmd(hw, &cmd->header);
1515
1516 if (!rc) {
1517 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1518 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1519 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1520 priv->hw_rev = cmd->hw_rev;
1521 }
1522
1523 kfree(cmd);
1524 return rc;
1525 }
1526
1527 /*
1528 * CMD_MAC_MULTICAST_ADR.
1529 */
1530 struct mwl8k_cmd_mac_multicast_adr {
1531 struct mwl8k_cmd_pkt header;
1532 __le16 action;
1533 __le16 numaddr;
1534 __u8 addr[0][ETH_ALEN];
1535 };
1536
1537 #define MWL8K_ENABLE_RX_DIRECTED 0x0001
1538 #define MWL8K_ENABLE_RX_MULTICAST 0x0002
1539 #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1540 #define MWL8K_ENABLE_RX_BROADCAST 0x0008
1541
1542 static struct mwl8k_cmd_pkt *
1543 __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
1544 int mc_count, struct dev_addr_list *mclist)
1545 {
1546 struct mwl8k_priv *priv = hw->priv;
1547 struct mwl8k_cmd_mac_multicast_adr *cmd;
1548 int size;
1549
1550 if (allmulti || mc_count > priv->num_mcaddrs) {
1551 allmulti = 1;
1552 mc_count = 0;
1553 }
1554
1555 size = sizeof(*cmd) + mc_count * ETH_ALEN;
1556
1557 cmd = kzalloc(size, GFP_ATOMIC);
1558 if (cmd == NULL)
1559 return NULL;
1560
1561 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1562 cmd->header.length = cpu_to_le16(size);
1563 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1564 MWL8K_ENABLE_RX_BROADCAST);
1565
1566 if (allmulti) {
1567 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1568 } else if (mc_count) {
1569 int i;
1570
1571 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1572 cmd->numaddr = cpu_to_le16(mc_count);
1573 for (i = 0; i < mc_count && mclist; i++) {
1574 if (mclist->da_addrlen != ETH_ALEN) {
1575 kfree(cmd);
1576 return NULL;
1577 }
1578 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1579 mclist = mclist->next;
1580 }
1581 }
1582
1583 return &cmd->header;
1584 }
1585
1586 /*
1587 * CMD_802_11_GET_STAT.
1588 */
1589 struct mwl8k_cmd_802_11_get_stat {
1590 struct mwl8k_cmd_pkt header;
1591 __le32 stats[64];
1592 } __attribute__((packed));
1593
1594 #define MWL8K_STAT_ACK_FAILURE 9
1595 #define MWL8K_STAT_RTS_FAILURE 12
1596 #define MWL8K_STAT_FCS_ERROR 24
1597 #define MWL8K_STAT_RTS_SUCCESS 11
1598
1599 static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1600 struct ieee80211_low_level_stats *stats)
1601 {
1602 struct mwl8k_cmd_802_11_get_stat *cmd;
1603 int rc;
1604
1605 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1606 if (cmd == NULL)
1607 return -ENOMEM;
1608
1609 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1610 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1611
1612 rc = mwl8k_post_cmd(hw, &cmd->header);
1613 if (!rc) {
1614 stats->dot11ACKFailureCount =
1615 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1616 stats->dot11RTSFailureCount =
1617 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1618 stats->dot11FCSErrorCount =
1619 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1620 stats->dot11RTSSuccessCount =
1621 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1622 }
1623 kfree(cmd);
1624
1625 return rc;
1626 }
1627
1628 /*
1629 * CMD_802_11_RADIO_CONTROL.
1630 */
1631 struct mwl8k_cmd_802_11_radio_control {
1632 struct mwl8k_cmd_pkt header;
1633 __le16 action;
1634 __le16 control;
1635 __le16 radio_on;
1636 } __attribute__((packed));
1637
1638 static int
1639 mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
1640 {
1641 struct mwl8k_priv *priv = hw->priv;
1642 struct mwl8k_cmd_802_11_radio_control *cmd;
1643 int rc;
1644
1645 if (enable == priv->radio_on && !force)
1646 return 0;
1647
1648 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1649 if (cmd == NULL)
1650 return -ENOMEM;
1651
1652 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1653 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1654 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1655 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
1656 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1657
1658 rc = mwl8k_post_cmd(hw, &cmd->header);
1659 kfree(cmd);
1660
1661 if (!rc)
1662 priv->radio_on = enable;
1663
1664 return rc;
1665 }
1666
1667 static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1668 {
1669 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1670 }
1671
1672 static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1673 {
1674 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1675 }
1676
1677 static int
1678 mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1679 {
1680 struct mwl8k_priv *priv;
1681
1682 if (hw == NULL || hw->priv == NULL)
1683 return -EINVAL;
1684 priv = hw->priv;
1685
1686 priv->radio_short_preamble = short_preamble;
1687
1688 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
1689 }
1690
1691 /*
1692 * CMD_802_11_RF_TX_POWER.
1693 */
1694 #define MWL8K_TX_POWER_LEVEL_TOTAL 8
1695
1696 struct mwl8k_cmd_802_11_rf_tx_power {
1697 struct mwl8k_cmd_pkt header;
1698 __le16 action;
1699 __le16 support_level;
1700 __le16 current_level;
1701 __le16 reserved;
1702 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1703 } __attribute__((packed));
1704
1705 static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1706 {
1707 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
1708 int rc;
1709
1710 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1711 if (cmd == NULL)
1712 return -ENOMEM;
1713
1714 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1715 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1716 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1717 cmd->support_level = cpu_to_le16(dBm);
1718
1719 rc = mwl8k_post_cmd(hw, &cmd->header);
1720 kfree(cmd);
1721
1722 return rc;
1723 }
1724
1725 /*
1726 * CMD_SET_PRE_SCAN.
1727 */
1728 struct mwl8k_cmd_set_pre_scan {
1729 struct mwl8k_cmd_pkt header;
1730 } __attribute__((packed));
1731
1732 static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
1733 {
1734 struct mwl8k_cmd_set_pre_scan *cmd;
1735 int rc;
1736
1737 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1738 if (cmd == NULL)
1739 return -ENOMEM;
1740
1741 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
1742 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1743
1744 rc = mwl8k_post_cmd(hw, &cmd->header);
1745 kfree(cmd);
1746
1747 return rc;
1748 }
1749
1750 /*
1751 * CMD_SET_POST_SCAN.
1752 */
1753 struct mwl8k_cmd_set_post_scan {
1754 struct mwl8k_cmd_pkt header;
1755 __le32 isibss;
1756 __u8 bssid[ETH_ALEN];
1757 } __attribute__((packed));
1758
1759 static int
1760 mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
1761 {
1762 struct mwl8k_cmd_set_post_scan *cmd;
1763 int rc;
1764
1765 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1766 if (cmd == NULL)
1767 return -ENOMEM;
1768
1769 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
1770 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1771 cmd->isibss = 0;
1772 memcpy(cmd->bssid, mac, ETH_ALEN);
1773
1774 rc = mwl8k_post_cmd(hw, &cmd->header);
1775 kfree(cmd);
1776
1777 return rc;
1778 }
1779
1780 /*
1781 * CMD_SET_RF_CHANNEL.
1782 */
1783 struct mwl8k_cmd_set_rf_channel {
1784 struct mwl8k_cmd_pkt header;
1785 __le16 action;
1786 __u8 current_channel;
1787 __le32 channel_flags;
1788 } __attribute__((packed));
1789
1790 static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
1791 struct ieee80211_channel *channel)
1792 {
1793 struct mwl8k_cmd_set_rf_channel *cmd;
1794 int rc;
1795
1796 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1797 if (cmd == NULL)
1798 return -ENOMEM;
1799
1800 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
1801 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1802 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1803 cmd->current_channel = channel->hw_value;
1804 if (channel->band == IEEE80211_BAND_2GHZ)
1805 cmd->channel_flags = cpu_to_le32(0x00000081);
1806 else
1807 cmd->channel_flags = cpu_to_le32(0x00000000);
1808
1809 rc = mwl8k_post_cmd(hw, &cmd->header);
1810 kfree(cmd);
1811
1812 return rc;
1813 }
1814
1815 /*
1816 * CMD_SET_SLOT.
1817 */
1818 struct mwl8k_cmd_set_slot {
1819 struct mwl8k_cmd_pkt header;
1820 __le16 action;
1821 __u8 short_slot;
1822 } __attribute__((packed));
1823
1824 static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
1825 {
1826 struct mwl8k_cmd_set_slot *cmd;
1827 int rc;
1828
1829 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1830 if (cmd == NULL)
1831 return -ENOMEM;
1832
1833 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
1834 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1835 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1836 cmd->short_slot = short_slot_time;
1837
1838 rc = mwl8k_post_cmd(hw, &cmd->header);
1839 kfree(cmd);
1840
1841 return rc;
1842 }
1843
1844 /*
1845 * CMD_MIMO_CONFIG.
1846 */
1847 struct mwl8k_cmd_mimo_config {
1848 struct mwl8k_cmd_pkt header;
1849 __le32 action;
1850 __u8 rx_antenna_map;
1851 __u8 tx_antenna_map;
1852 } __attribute__((packed));
1853
1854 static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
1855 {
1856 struct mwl8k_cmd_mimo_config *cmd;
1857 int rc;
1858
1859 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1860 if (cmd == NULL)
1861 return -ENOMEM;
1862
1863 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
1864 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1865 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
1866 cmd->rx_antenna_map = rx;
1867 cmd->tx_antenna_map = tx;
1868
1869 rc = mwl8k_post_cmd(hw, &cmd->header);
1870 kfree(cmd);
1871
1872 return rc;
1873 }
1874
1875 /*
1876 * CMD_ENABLE_SNIFFER.
1877 */
1878 struct mwl8k_cmd_enable_sniffer {
1879 struct mwl8k_cmd_pkt header;
1880 __le32 action;
1881 } __attribute__((packed));
1882
1883 static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
1884 {
1885 struct mwl8k_cmd_enable_sniffer *cmd;
1886 int rc;
1887
1888 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1889 if (cmd == NULL)
1890 return -ENOMEM;
1891
1892 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
1893 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1894 cmd->action = cpu_to_le32(!!enable);
1895
1896 rc = mwl8k_post_cmd(hw, &cmd->header);
1897 kfree(cmd);
1898
1899 return rc;
1900 }
1901
1902 /*
1903 * CMD_SET_MAC_ADDR.
1904 */
1905 struct mwl8k_cmd_set_mac_addr {
1906 struct mwl8k_cmd_pkt header;
1907 __u8 mac_addr[ETH_ALEN];
1908 } __attribute__((packed));
1909
1910 static int mwl8k_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
1911 {
1912 struct mwl8k_cmd_set_mac_addr *cmd;
1913 int rc;
1914
1915 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1916 if (cmd == NULL)
1917 return -ENOMEM;
1918
1919 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
1920 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1921 memcpy(cmd->mac_addr, mac, ETH_ALEN);
1922
1923 rc = mwl8k_post_cmd(hw, &cmd->header);
1924 kfree(cmd);
1925
1926 return rc;
1927 }
1928
1929
1930 /*
1931 * CMD_SET_RATEADAPT_MODE.
1932 */
1933 struct mwl8k_cmd_set_rate_adapt_mode {
1934 struct mwl8k_cmd_pkt header;
1935 __le16 action;
1936 __le16 mode;
1937 } __attribute__((packed));
1938
1939 static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
1940 {
1941 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
1942 int rc;
1943
1944 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1945 if (cmd == NULL)
1946 return -ENOMEM;
1947
1948 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
1949 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1950 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1951 cmd->mode = cpu_to_le16(mode);
1952
1953 rc = mwl8k_post_cmd(hw, &cmd->header);
1954 kfree(cmd);
1955
1956 return rc;
1957 }
1958
1959 /*
1960 * CMD_SET_WMM_MODE.
1961 */
1962 struct mwl8k_cmd_set_wmm {
1963 struct mwl8k_cmd_pkt header;
1964 __le16 action;
1965 } __attribute__((packed));
1966
1967 static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
1968 {
1969 struct mwl8k_priv *priv = hw->priv;
1970 struct mwl8k_cmd_set_wmm *cmd;
1971 int rc;
1972
1973 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1974 if (cmd == NULL)
1975 return -ENOMEM;
1976
1977 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
1978 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1979 cmd->action = cpu_to_le16(!!enable);
1980
1981 rc = mwl8k_post_cmd(hw, &cmd->header);
1982 kfree(cmd);
1983
1984 if (!rc)
1985 priv->wmm_enabled = enable;
1986
1987 return rc;
1988 }
1989
1990 /*
1991 * CMD_SET_RTS_THRESHOLD.
1992 */
1993 struct mwl8k_cmd_rts_threshold {
1994 struct mwl8k_cmd_pkt header;
1995 __le16 action;
1996 __le16 threshold;
1997 } __attribute__((packed));
1998
1999 static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
2000 u16 action, u16 threshold)
2001 {
2002 struct mwl8k_cmd_rts_threshold *cmd;
2003 int rc;
2004
2005 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2006 if (cmd == NULL)
2007 return -ENOMEM;
2008
2009 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2010 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2011 cmd->action = cpu_to_le16(action);
2012 cmd->threshold = cpu_to_le16(threshold);
2013
2014 rc = mwl8k_post_cmd(hw, &cmd->header);
2015 kfree(cmd);
2016
2017 return rc;
2018 }
2019
2020 /*
2021 * CMD_SET_EDCA_PARAMS.
2022 */
2023 struct mwl8k_cmd_set_edca_params {
2024 struct mwl8k_cmd_pkt header;
2025
2026 /* See MWL8K_SET_EDCA_XXX below */
2027 __le16 action;
2028
2029 /* TX opportunity in units of 32 us */
2030 __le16 txop;
2031
2032 /* Log exponent of max contention period: 0...15*/
2033 __u8 log_cw_max;
2034
2035 /* Log exponent of min contention period: 0...15 */
2036 __u8 log_cw_min;
2037
2038 /* Adaptive interframe spacing in units of 32us */
2039 __u8 aifs;
2040
2041 /* TX queue to configure */
2042 __u8 txq;
2043 } __attribute__((packed));
2044
2045 #define MWL8K_SET_EDCA_CW 0x01
2046 #define MWL8K_SET_EDCA_TXOP 0x02
2047 #define MWL8K_SET_EDCA_AIFS 0x04
2048
2049 #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2050 MWL8K_SET_EDCA_TXOP | \
2051 MWL8K_SET_EDCA_AIFS)
2052
2053 static int
2054 mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2055 __u16 cw_min, __u16 cw_max,
2056 __u8 aifs, __u16 txop)
2057 {
2058 struct mwl8k_cmd_set_edca_params *cmd;
2059 int rc;
2060
2061 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2062 if (cmd == NULL)
2063 return -ENOMEM;
2064
2065 /*
2066 * Queues 0 (BE) and 1 (BK) are swapped in hardware for
2067 * this call.
2068 */
2069 qnum ^= !(qnum >> 1);
2070
2071 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2072 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2073 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2074 cmd->txop = cpu_to_le16(txop);
2075 cmd->log_cw_max = (u8)ilog2(cw_max + 1);
2076 cmd->log_cw_min = (u8)ilog2(cw_min + 1);
2077 cmd->aifs = aifs;
2078 cmd->txq = qnum;
2079
2080 rc = mwl8k_post_cmd(hw, &cmd->header);
2081 kfree(cmd);
2082
2083 return rc;
2084 }
2085
2086 /*
2087 * CMD_FINALIZE_JOIN.
2088 */
2089
2090 /* FJ beacon buffer size is compiled into the firmware. */
2091 #define MWL8K_FJ_BEACON_MAXLEN 128
2092
2093 struct mwl8k_cmd_finalize_join {
2094 struct mwl8k_cmd_pkt header;
2095 __le32 sleep_interval; /* Number of beacon periods to sleep */
2096 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2097 } __attribute__((packed));
2098
2099 static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2100 __u16 framelen, __u16 dtim)
2101 {
2102 struct mwl8k_cmd_finalize_join *cmd;
2103 struct ieee80211_mgmt *payload = frame;
2104 u16 hdrlen;
2105 u32 payload_len;
2106 int rc;
2107
2108 if (frame == NULL)
2109 return -EINVAL;
2110
2111 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2112 if (cmd == NULL)
2113 return -ENOMEM;
2114
2115 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2116 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2117 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2118
2119 hdrlen = ieee80211_hdrlen(payload->frame_control);
2120
2121 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2122
2123 /* XXX TBD Might just have to abort and return an error */
2124 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2125 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
2126 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2127 payload_len, MWL8K_FJ_BEACON_MAXLEN);
2128
2129 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2130 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2131
2132 if (payload && payload_len)
2133 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2134
2135 rc = mwl8k_post_cmd(hw, &cmd->header);
2136 kfree(cmd);
2137 return rc;
2138 }
2139
2140 /*
2141 * CMD_UPDATE_STADB.
2142 */
2143 struct mwl8k_cmd_update_sta_db {
2144 struct mwl8k_cmd_pkt header;
2145
2146 /* See STADB_ACTION_TYPE */
2147 __le32 action;
2148
2149 /* Peer MAC address */
2150 __u8 peer_addr[ETH_ALEN];
2151
2152 __le32 reserved;
2153
2154 /* Peer info - valid during add/update. */
2155 struct peer_capability_info peer_info;
2156 } __attribute__((packed));
2157
2158 static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2159 struct ieee80211_vif *vif, __u32 action)
2160 {
2161 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2162 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2163 struct mwl8k_cmd_update_sta_db *cmd;
2164 struct peer_capability_info *peer_info;
2165 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2166 int rc;
2167 __u8 count, *rates;
2168
2169 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2170 if (cmd == NULL)
2171 return -ENOMEM;
2172
2173 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2174 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2175
2176 cmd->action = cpu_to_le32(action);
2177 peer_info = &cmd->peer_info;
2178 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
2179
2180 switch (action) {
2181 case MWL8K_STA_DB_ADD_ENTRY:
2182 case MWL8K_STA_DB_MODIFY_ENTRY:
2183 /* Build peer_info block */
2184 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2185 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2186 peer_info->interop = 1;
2187 peer_info->amsdu_enabled = 0;
2188
2189 rates = peer_info->legacy_rates;
2190 for (count = 0; count < mv_vif->legacy_nrates; count++)
2191 rates[count] = bitrates[count].hw_value;
2192
2193 rc = mwl8k_post_cmd(hw, &cmd->header);
2194 if (rc == 0)
2195 mv_vif->peer_id = peer_info->station_id;
2196
2197 break;
2198
2199 case MWL8K_STA_DB_DEL_ENTRY:
2200 case MWL8K_STA_DB_FLUSH:
2201 default:
2202 rc = mwl8k_post_cmd(hw, &cmd->header);
2203 if (rc == 0)
2204 mv_vif->peer_id = 0;
2205 break;
2206 }
2207 kfree(cmd);
2208
2209 return rc;
2210 }
2211
2212 /*
2213 * CMD_SET_AID.
2214 */
2215 #define MWL8K_RATE_INDEX_MAX_ARRAY 14
2216
2217 #define MWL8K_FRAME_PROT_DISABLED 0x00
2218 #define MWL8K_FRAME_PROT_11G 0x07
2219 #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2220 #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
2221
2222 struct mwl8k_cmd_update_set_aid {
2223 struct mwl8k_cmd_pkt header;
2224 __le16 aid;
2225
2226 /* AP's MAC address (BSSID) */
2227 __u8 bssid[ETH_ALEN];
2228 __le16 protection_mode;
2229 __u8 supp_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2230 } __attribute__((packed));
2231
2232 static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2233 struct ieee80211_vif *vif)
2234 {
2235 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2236 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2237 struct mwl8k_cmd_update_set_aid *cmd;
2238 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2239 int count;
2240 u16 prot_mode;
2241 int rc;
2242
2243 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2244 if (cmd == NULL)
2245 return -ENOMEM;
2246
2247 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2248 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2249 cmd->aid = cpu_to_le16(info->aid);
2250
2251 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
2252
2253 if (info->use_cts_prot) {
2254 prot_mode = MWL8K_FRAME_PROT_11G;
2255 } else {
2256 switch (info->ht_operation_mode &
2257 IEEE80211_HT_OP_MODE_PROTECTION) {
2258 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2259 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2260 break;
2261 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2262 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2263 break;
2264 default:
2265 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2266 break;
2267 }
2268 }
2269 cmd->protection_mode = cpu_to_le16(prot_mode);
2270
2271 for (count = 0; count < mv_vif->legacy_nrates; count++)
2272 cmd->supp_rates[count] = bitrates[count].hw_value;
2273
2274 rc = mwl8k_post_cmd(hw, &cmd->header);
2275 kfree(cmd);
2276
2277 return rc;
2278 }
2279
2280 /*
2281 * CMD_SET_RATE.
2282 */
2283 struct mwl8k_cmd_update_rateset {
2284 struct mwl8k_cmd_pkt header;
2285 __u8 legacy_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2286
2287 /* Bitmap for supported MCS codes. */
2288 __u8 mcs_set[MWL8K_IEEE_LEGACY_DATA_RATES];
2289 __u8 reserved[MWL8K_IEEE_LEGACY_DATA_RATES];
2290 } __attribute__((packed));
2291
2292 static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2293 struct ieee80211_vif *vif)
2294 {
2295 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2296 struct mwl8k_cmd_update_rateset *cmd;
2297 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2298 int count;
2299 int rc;
2300
2301 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2302 if (cmd == NULL)
2303 return -ENOMEM;
2304
2305 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2306 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2307
2308 for (count = 0; count < mv_vif->legacy_nrates; count++)
2309 cmd->legacy_rates[count] = bitrates[count].hw_value;
2310
2311 rc = mwl8k_post_cmd(hw, &cmd->header);
2312 kfree(cmd);
2313
2314 return rc;
2315 }
2316
2317 /*
2318 * CMD_USE_FIXED_RATE.
2319 */
2320 #define MWL8K_RATE_TABLE_SIZE 8
2321 #define MWL8K_UCAST_RATE 0
2322 #define MWL8K_USE_AUTO_RATE 0x0002
2323
2324 struct mwl8k_rate_entry {
2325 /* Set to 1 if HT rate, 0 if legacy. */
2326 __le32 is_ht_rate;
2327
2328 /* Set to 1 to use retry_count field. */
2329 __le32 enable_retry;
2330
2331 /* Specified legacy rate or MCS. */
2332 __le32 rate;
2333
2334 /* Number of allowed retries. */
2335 __le32 retry_count;
2336 } __attribute__((packed));
2337
2338 struct mwl8k_rate_table {
2339 /* 1 to allow specified rate and below */
2340 __le32 allow_rate_drop;
2341 __le32 num_rates;
2342 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2343 } __attribute__((packed));
2344
2345 struct mwl8k_cmd_use_fixed_rate {
2346 struct mwl8k_cmd_pkt header;
2347 __le32 action;
2348 struct mwl8k_rate_table rate_table;
2349
2350 /* Unicast, Broadcast or Multicast */
2351 __le32 rate_type;
2352 __le32 reserved1;
2353 __le32 reserved2;
2354 } __attribute__((packed));
2355
2356 static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2357 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2358 {
2359 struct mwl8k_cmd_use_fixed_rate *cmd;
2360 int count;
2361 int rc;
2362
2363 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2364 if (cmd == NULL)
2365 return -ENOMEM;
2366
2367 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2368 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2369
2370 cmd->action = cpu_to_le32(action);
2371 cmd->rate_type = cpu_to_le32(rate_type);
2372
2373 if (rate_table != NULL) {
2374 /*
2375 * Copy over each field manually so that endian
2376 * conversion can be done.
2377 */
2378 cmd->rate_table.allow_rate_drop =
2379 cpu_to_le32(rate_table->allow_rate_drop);
2380 cmd->rate_table.num_rates =
2381 cpu_to_le32(rate_table->num_rates);
2382
2383 for (count = 0; count < rate_table->num_rates; count++) {
2384 struct mwl8k_rate_entry *dst =
2385 &cmd->rate_table.rate_entry[count];
2386 struct mwl8k_rate_entry *src =
2387 &rate_table->rate_entry[count];
2388
2389 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2390 dst->enable_retry = cpu_to_le32(src->enable_retry);
2391 dst->rate = cpu_to_le32(src->rate);
2392 dst->retry_count = cpu_to_le32(src->retry_count);
2393 }
2394 }
2395
2396 rc = mwl8k_post_cmd(hw, &cmd->header);
2397 kfree(cmd);
2398
2399 return rc;
2400 }
2401
2402
2403 /*
2404 * Interrupt handling.
2405 */
2406 static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2407 {
2408 struct ieee80211_hw *hw = dev_id;
2409 struct mwl8k_priv *priv = hw->priv;
2410 u32 status;
2411
2412 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2413 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2414
2415 if (!status)
2416 return IRQ_NONE;
2417
2418 if (status & MWL8K_A2H_INT_TX_DONE)
2419 tasklet_schedule(&priv->tx_reclaim_task);
2420
2421 if (status & MWL8K_A2H_INT_RX_READY) {
2422 while (rxq_process(hw, 0, 1))
2423 rxq_refill(hw, 0, 1);
2424 }
2425
2426 if (status & MWL8K_A2H_INT_OPC_DONE) {
2427 if (priv->hostcmd_wait != NULL)
2428 complete(priv->hostcmd_wait);
2429 }
2430
2431 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
2432 if (!mutex_is_locked(&priv->fw_mutex) &&
2433 priv->radio_on && priv->pending_tx_pkts)
2434 mwl8k_tx_start(priv);
2435 }
2436
2437 return IRQ_HANDLED;
2438 }
2439
2440
2441 /*
2442 * Core driver operations.
2443 */
2444 static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2445 {
2446 struct mwl8k_priv *priv = hw->priv;
2447 int index = skb_get_queue_mapping(skb);
2448 int rc;
2449
2450 if (priv->current_channel == NULL) {
2451 printk(KERN_DEBUG "%s: dropped TX frame since radio "
2452 "disabled\n", wiphy_name(hw->wiphy));
2453 dev_kfree_skb(skb);
2454 return NETDEV_TX_OK;
2455 }
2456
2457 rc = mwl8k_txq_xmit(hw, index, skb);
2458
2459 return rc;
2460 }
2461
2462 static int mwl8k_start(struct ieee80211_hw *hw)
2463 {
2464 struct mwl8k_priv *priv = hw->priv;
2465 int rc;
2466
2467 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
2468 IRQF_SHARED, MWL8K_NAME, hw);
2469 if (rc) {
2470 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2471 wiphy_name(hw->wiphy));
2472 return -EIO;
2473 }
2474
2475 /* Enable tx reclaim tasklet */
2476 tasklet_enable(&priv->tx_reclaim_task);
2477
2478 /* Enable interrupts */
2479 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2480
2481 rc = mwl8k_fw_lock(hw);
2482 if (!rc) {
2483 rc = mwl8k_cmd_802_11_radio_enable(hw);
2484
2485 if (!rc)
2486 rc = mwl8k_cmd_set_pre_scan(hw);
2487
2488 if (!rc)
2489 rc = mwl8k_cmd_set_post_scan(hw,
2490 "\x00\x00\x00\x00\x00\x00");
2491
2492 if (!rc)
2493 rc = mwl8k_cmd_setrateadaptmode(hw, 0);
2494
2495 if (!rc)
2496 rc = mwl8k_set_wmm(hw, 0);
2497
2498 if (!rc)
2499 rc = mwl8k_enable_sniffer(hw, 0);
2500
2501 mwl8k_fw_unlock(hw);
2502 }
2503
2504 if (rc) {
2505 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2506 free_irq(priv->pdev->irq, hw);
2507 tasklet_disable(&priv->tx_reclaim_task);
2508 }
2509
2510 return rc;
2511 }
2512
2513 static void mwl8k_stop(struct ieee80211_hw *hw)
2514 {
2515 struct mwl8k_priv *priv = hw->priv;
2516 int i;
2517
2518 mwl8k_cmd_802_11_radio_disable(hw);
2519
2520 ieee80211_stop_queues(hw);
2521
2522 /* Disable interrupts */
2523 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2524 free_irq(priv->pdev->irq, hw);
2525
2526 /* Stop finalize join worker */
2527 cancel_work_sync(&priv->finalize_join_worker);
2528 if (priv->beacon_skb != NULL)
2529 dev_kfree_skb(priv->beacon_skb);
2530
2531 /* Stop tx reclaim tasklet */
2532 tasklet_disable(&priv->tx_reclaim_task);
2533
2534 /* Return all skbs to mac80211 */
2535 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2536 mwl8k_txq_reclaim(hw, i, 1);
2537 }
2538
2539 static int mwl8k_add_interface(struct ieee80211_hw *hw,
2540 struct ieee80211_if_init_conf *conf)
2541 {
2542 struct mwl8k_priv *priv = hw->priv;
2543 struct mwl8k_vif *mwl8k_vif;
2544
2545 /*
2546 * We only support one active interface at a time.
2547 */
2548 if (priv->vif != NULL)
2549 return -EBUSY;
2550
2551 /*
2552 * We only support managed interfaces for now.
2553 */
2554 if (conf->type != NL80211_IFTYPE_STATION)
2555 return -EINVAL;
2556
2557 /*
2558 * Reject interface creation if sniffer mode is active, as
2559 * STA operation is mutually exclusive with hardware sniffer
2560 * mode.
2561 */
2562 if (priv->sniffer_enabled) {
2563 printk(KERN_INFO "%s: unable to create STA "
2564 "interface due to sniffer mode being enabled\n",
2565 wiphy_name(hw->wiphy));
2566 return -EINVAL;
2567 }
2568
2569 /* Clean out driver private area */
2570 mwl8k_vif = MWL8K_VIF(conf->vif);
2571 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2572
2573 /* Set and save the mac address */
2574 mwl8k_set_mac_addr(hw, conf->mac_addr);
2575 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
2576
2577 /* Back pointer to parent config block */
2578 mwl8k_vif->priv = priv;
2579
2580 /* Setup initial PHY parameters */
2581 memcpy(mwl8k_vif->legacy_rates,
2582 priv->rates, sizeof(mwl8k_vif->legacy_rates));
2583 mwl8k_vif->legacy_nrates = ARRAY_SIZE(priv->rates);
2584
2585 /* Set Initial sequence number to zero */
2586 mwl8k_vif->seqno = 0;
2587
2588 priv->vif = conf->vif;
2589 priv->current_channel = NULL;
2590
2591 return 0;
2592 }
2593
2594 static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2595 struct ieee80211_if_init_conf *conf)
2596 {
2597 struct mwl8k_priv *priv = hw->priv;
2598
2599 if (priv->vif == NULL)
2600 return;
2601
2602 mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
2603
2604 priv->vif = NULL;
2605 }
2606
2607 static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
2608 {
2609 struct ieee80211_conf *conf = &hw->conf;
2610 struct mwl8k_priv *priv = hw->priv;
2611 int rc;
2612
2613 if (conf->flags & IEEE80211_CONF_IDLE) {
2614 mwl8k_cmd_802_11_radio_disable(hw);
2615 priv->current_channel = NULL;
2616 return 0;
2617 }
2618
2619 rc = mwl8k_fw_lock(hw);
2620 if (rc)
2621 return rc;
2622
2623 rc = mwl8k_cmd_802_11_radio_enable(hw);
2624 if (rc)
2625 goto out;
2626
2627 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2628 if (rc)
2629 goto out;
2630
2631 priv->current_channel = conf->channel;
2632
2633 if (conf->power_level > 18)
2634 conf->power_level = 18;
2635 rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level);
2636 if (rc)
2637 goto out;
2638
2639 if (mwl8k_cmd_mimo_config(hw, 0x7, 0x7))
2640 rc = -EINVAL;
2641
2642 out:
2643 mwl8k_fw_unlock(hw);
2644
2645 return rc;
2646 }
2647
2648 static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
2649 struct ieee80211_vif *vif,
2650 struct ieee80211_bss_conf *info,
2651 u32 changed)
2652 {
2653 struct mwl8k_priv *priv = hw->priv;
2654 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
2655 int rc;
2656
2657 if (changed & BSS_CHANGED_BSSID)
2658 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
2659
2660 if ((changed & BSS_CHANGED_ASSOC) == 0)
2661 return;
2662
2663 priv->capture_beacon = false;
2664
2665 rc = mwl8k_fw_lock(hw);
2666 if (rc)
2667 return;
2668
2669 if (info->assoc) {
2670 memcpy(&mwl8k_vif->bss_info, info,
2671 sizeof(struct ieee80211_bss_conf));
2672
2673 /* Install rates */
2674 rc = mwl8k_update_rateset(hw, vif);
2675 if (rc)
2676 goto out;
2677
2678 /* Turn on rate adaptation */
2679 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
2680 MWL8K_UCAST_RATE, NULL);
2681 if (rc)
2682 goto out;
2683
2684 /* Set radio preamble */
2685 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
2686 if (rc)
2687 goto out;
2688
2689 /* Set slot time */
2690 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
2691 if (rc)
2692 goto out;
2693
2694 /* Update peer rate info */
2695 rc = mwl8k_cmd_update_sta_db(hw, vif,
2696 MWL8K_STA_DB_MODIFY_ENTRY);
2697 if (rc)
2698 goto out;
2699
2700 /* Set AID */
2701 rc = mwl8k_cmd_set_aid(hw, vif);
2702 if (rc)
2703 goto out;
2704
2705 /*
2706 * Finalize the join. Tell rx handler to process
2707 * next beacon from our BSSID.
2708 */
2709 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
2710 priv->capture_beacon = true;
2711 } else {
2712 rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
2713 memset(&mwl8k_vif->bss_info, 0,
2714 sizeof(struct ieee80211_bss_conf));
2715 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
2716 }
2717
2718 out:
2719 mwl8k_fw_unlock(hw);
2720 }
2721
2722 static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
2723 int mc_count, struct dev_addr_list *mclist)
2724 {
2725 struct mwl8k_cmd_pkt *cmd;
2726
2727 /*
2728 * Synthesize and return a command packet that programs the
2729 * hardware multicast address filter. At this point we don't
2730 * know whether FIF_ALLMULTI is being requested, but if it is,
2731 * we'll end up throwing this packet away and creating a new
2732 * one in mwl8k_configure_filter().
2733 */
2734 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
2735
2736 return (unsigned long)cmd;
2737 }
2738
2739 static int
2740 mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
2741 unsigned int changed_flags,
2742 unsigned int *total_flags)
2743 {
2744 struct mwl8k_priv *priv = hw->priv;
2745
2746 /*
2747 * Hardware sniffer mode is mutually exclusive with STA
2748 * operation, so refuse to enable sniffer mode if a STA
2749 * interface is active.
2750 */
2751 if (priv->vif != NULL) {
2752 if (net_ratelimit())
2753 printk(KERN_INFO "%s: not enabling sniffer "
2754 "mode because STA interface is active\n",
2755 wiphy_name(hw->wiphy));
2756 return 0;
2757 }
2758
2759 if (!priv->sniffer_enabled) {
2760 if (mwl8k_enable_sniffer(hw, 1))
2761 return 0;
2762 priv->sniffer_enabled = true;
2763 }
2764
2765 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
2766 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
2767 FIF_OTHER_BSS;
2768
2769 return 1;
2770 }
2771
2772 static void mwl8k_configure_filter(struct ieee80211_hw *hw,
2773 unsigned int changed_flags,
2774 unsigned int *total_flags,
2775 u64 multicast)
2776 {
2777 struct mwl8k_priv *priv = hw->priv;
2778 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
2779
2780 /*
2781 * Enable hardware sniffer mode if FIF_CONTROL or
2782 * FIF_OTHER_BSS is requested.
2783 */
2784 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
2785 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
2786 kfree(cmd);
2787 return;
2788 }
2789
2790 /* Clear unsupported feature flags */
2791 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
2792
2793 if (mwl8k_fw_lock(hw))
2794 return;
2795
2796 if (priv->sniffer_enabled) {
2797 mwl8k_enable_sniffer(hw, 0);
2798 priv->sniffer_enabled = false;
2799 }
2800
2801 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2802 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
2803 /*
2804 * Disable the BSS filter.
2805 */
2806 mwl8k_cmd_set_pre_scan(hw);
2807 } else {
2808 u8 *bssid;
2809
2810 /*
2811 * Enable the BSS filter.
2812 *
2813 * If there is an active STA interface, use that
2814 * interface's BSSID, otherwise use a dummy one
2815 * (where the OUI part needs to be nonzero for
2816 * the BSSID to be accepted by POST_SCAN).
2817 */
2818 bssid = "\x01\x00\x00\x00\x00\x00";
2819 if (priv->vif != NULL)
2820 bssid = MWL8K_VIF(priv->vif)->bssid;
2821
2822 mwl8k_cmd_set_post_scan(hw, bssid);
2823 }
2824 }
2825
2826 /*
2827 * If FIF_ALLMULTI is being requested, throw away the command
2828 * packet that ->prepare_multicast() built and replace it with
2829 * a command packet that enables reception of all multicast
2830 * packets.
2831 */
2832 if (*total_flags & FIF_ALLMULTI) {
2833 kfree(cmd);
2834 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
2835 }
2836
2837 if (cmd != NULL) {
2838 mwl8k_post_cmd(hw, cmd);
2839 kfree(cmd);
2840 }
2841
2842 mwl8k_fw_unlock(hw);
2843 }
2844
2845 static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2846 {
2847 return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value);
2848 }
2849
2850 static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2851 const struct ieee80211_tx_queue_params *params)
2852 {
2853 struct mwl8k_priv *priv = hw->priv;
2854 int rc;
2855
2856 rc = mwl8k_fw_lock(hw);
2857 if (!rc) {
2858 if (!priv->wmm_enabled)
2859 rc = mwl8k_set_wmm(hw, 1);
2860
2861 if (!rc)
2862 rc = mwl8k_set_edca_params(hw, queue,
2863 params->cw_min,
2864 params->cw_max,
2865 params->aifs,
2866 params->txop);
2867
2868 mwl8k_fw_unlock(hw);
2869 }
2870
2871 return rc;
2872 }
2873
2874 static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
2875 struct ieee80211_tx_queue_stats *stats)
2876 {
2877 struct mwl8k_priv *priv = hw->priv;
2878 struct mwl8k_tx_queue *txq;
2879 int index;
2880
2881 spin_lock_bh(&priv->tx_lock);
2882 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
2883 txq = priv->txq + index;
2884 memcpy(&stats[index], &txq->stats,
2885 sizeof(struct ieee80211_tx_queue_stats));
2886 }
2887 spin_unlock_bh(&priv->tx_lock);
2888
2889 return 0;
2890 }
2891
2892 static int mwl8k_get_stats(struct ieee80211_hw *hw,
2893 struct ieee80211_low_level_stats *stats)
2894 {
2895 return mwl8k_cmd_802_11_get_stat(hw, stats);
2896 }
2897
2898 static const struct ieee80211_ops mwl8k_ops = {
2899 .tx = mwl8k_tx,
2900 .start = mwl8k_start,
2901 .stop = mwl8k_stop,
2902 .add_interface = mwl8k_add_interface,
2903 .remove_interface = mwl8k_remove_interface,
2904 .config = mwl8k_config,
2905 .bss_info_changed = mwl8k_bss_info_changed,
2906 .prepare_multicast = mwl8k_prepare_multicast,
2907 .configure_filter = mwl8k_configure_filter,
2908 .set_rts_threshold = mwl8k_set_rts_threshold,
2909 .conf_tx = mwl8k_conf_tx,
2910 .get_tx_stats = mwl8k_get_tx_stats,
2911 .get_stats = mwl8k_get_stats,
2912 };
2913
2914 static void mwl8k_tx_reclaim_handler(unsigned long data)
2915 {
2916 int i;
2917 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
2918 struct mwl8k_priv *priv = hw->priv;
2919
2920 spin_lock_bh(&priv->tx_lock);
2921 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2922 mwl8k_txq_reclaim(hw, i, 0);
2923
2924 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
2925 complete(priv->tx_wait);
2926 priv->tx_wait = NULL;
2927 }
2928 spin_unlock_bh(&priv->tx_lock);
2929 }
2930
2931 static void mwl8k_finalize_join_worker(struct work_struct *work)
2932 {
2933 struct mwl8k_priv *priv =
2934 container_of(work, struct mwl8k_priv, finalize_join_worker);
2935 struct sk_buff *skb = priv->beacon_skb;
2936 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
2937
2938 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
2939 dev_kfree_skb(skb);
2940
2941 priv->beacon_skb = NULL;
2942 }
2943
2944 static int __devinit mwl8k_probe(struct pci_dev *pdev,
2945 const struct pci_device_id *id)
2946 {
2947 static int printed_version = 0;
2948 struct ieee80211_hw *hw;
2949 struct mwl8k_priv *priv;
2950 int rc;
2951 int i;
2952
2953 if (!printed_version) {
2954 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
2955 printed_version = 1;
2956 }
2957
2958 rc = pci_enable_device(pdev);
2959 if (rc) {
2960 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
2961 MWL8K_NAME);
2962 return rc;
2963 }
2964
2965 rc = pci_request_regions(pdev, MWL8K_NAME);
2966 if (rc) {
2967 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
2968 MWL8K_NAME);
2969 return rc;
2970 }
2971
2972 pci_set_master(pdev);
2973
2974 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
2975 if (hw == NULL) {
2976 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
2977 rc = -ENOMEM;
2978 goto err_free_reg;
2979 }
2980
2981 priv = hw->priv;
2982 priv->hw = hw;
2983 priv->pdev = pdev;
2984 priv->sniffer_enabled = false;
2985 priv->wmm_enabled = false;
2986 priv->pending_tx_pkts = 0;
2987
2988 SET_IEEE80211_DEV(hw, &pdev->dev);
2989 pci_set_drvdata(pdev, hw);
2990
2991 priv->sram = pci_iomap(pdev, 0, 0x10000);
2992 if (priv->sram == NULL) {
2993 printk(KERN_ERR "%s: Cannot map device SRAM\n",
2994 wiphy_name(hw->wiphy));
2995 goto err_iounmap;
2996 }
2997
2998 /*
2999 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3000 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3001 */
3002 priv->regs = pci_iomap(pdev, 1, 0x10000);
3003 if (priv->regs == NULL) {
3004 priv->regs = pci_iomap(pdev, 2, 0x10000);
3005 if (priv->regs == NULL) {
3006 printk(KERN_ERR "%s: Cannot map device registers\n",
3007 wiphy_name(hw->wiphy));
3008 goto err_iounmap;
3009 }
3010 }
3011
3012 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3013 priv->band.band = IEEE80211_BAND_2GHZ;
3014 priv->band.channels = priv->channels;
3015 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3016 priv->band.bitrates = priv->rates;
3017 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3018 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3019
3020 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3021 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3022
3023 /*
3024 * Extra headroom is the size of the required DMA header
3025 * minus the size of the smallest 802.11 frame (CTS frame).
3026 */
3027 hw->extra_tx_headroom =
3028 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3029
3030 hw->channel_change_time = 10;
3031
3032 hw->queues = MWL8K_TX_QUEUES;
3033
3034 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
3035
3036 /* Set rssi and noise values to dBm */
3037 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
3038 hw->vif_data_size = sizeof(struct mwl8k_vif);
3039 priv->vif = NULL;
3040
3041 /* Set default radio state and preamble */
3042 priv->radio_on = 0;
3043 priv->radio_short_preamble = 0;
3044
3045 /* Finalize join worker */
3046 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3047
3048 /* TX reclaim tasklet */
3049 tasklet_init(&priv->tx_reclaim_task,
3050 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3051 tasklet_disable(&priv->tx_reclaim_task);
3052
3053 /* Power management cookie */
3054 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3055 if (priv->cookie == NULL)
3056 goto err_iounmap;
3057
3058 rc = mwl8k_rxq_init(hw, 0);
3059 if (rc)
3060 goto err_iounmap;
3061 rxq_refill(hw, 0, INT_MAX);
3062
3063 mutex_init(&priv->fw_mutex);
3064 priv->fw_mutex_owner = NULL;
3065 priv->fw_mutex_depth = 0;
3066 priv->hostcmd_wait = NULL;
3067
3068 spin_lock_init(&priv->tx_lock);
3069
3070 priv->tx_wait = NULL;
3071
3072 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3073 rc = mwl8k_txq_init(hw, i);
3074 if (rc)
3075 goto err_free_queues;
3076 }
3077
3078 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3079 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3080 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3081 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3082
3083 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
3084 IRQF_SHARED, MWL8K_NAME, hw);
3085 if (rc) {
3086 printk(KERN_ERR "%s: failed to register IRQ handler\n",
3087 wiphy_name(hw->wiphy));
3088 goto err_free_queues;
3089 }
3090
3091 /* Reset firmware and hardware */
3092 mwl8k_hw_reset(priv);
3093
3094 /* Ask userland hotplug daemon for the device firmware */
3095 rc = mwl8k_request_firmware(priv, (u32)id->driver_data);
3096 if (rc) {
3097 printk(KERN_ERR "%s: Firmware files not found\n",
3098 wiphy_name(hw->wiphy));
3099 goto err_free_irq;
3100 }
3101
3102 /* Load firmware into hardware */
3103 rc = mwl8k_load_firmware(hw);
3104 if (rc) {
3105 printk(KERN_ERR "%s: Cannot start firmware\n",
3106 wiphy_name(hw->wiphy));
3107 goto err_stop_firmware;
3108 }
3109
3110 /* Reclaim memory once firmware is successfully loaded */
3111 mwl8k_release_firmware(priv);
3112
3113 /*
3114 * Temporarily enable interrupts. Initial firmware host
3115 * commands use interrupts and avoids polling. Disable
3116 * interrupts when done.
3117 */
3118 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3119
3120 /* Get config data, mac addrs etc */
3121 rc = mwl8k_cmd_get_hw_spec(hw);
3122 if (rc) {
3123 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3124 wiphy_name(hw->wiphy));
3125 goto err_stop_firmware;
3126 }
3127
3128 /* Turn radio off */
3129 rc = mwl8k_cmd_802_11_radio_disable(hw);
3130 if (rc) {
3131 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
3132 goto err_stop_firmware;
3133 }
3134
3135 /* Clear MAC address */
3136 rc = mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
3137 if (rc) {
3138 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3139 wiphy_name(hw->wiphy));
3140 goto err_stop_firmware;
3141 }
3142
3143 /* Disable interrupts */
3144 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3145 free_irq(priv->pdev->irq, hw);
3146
3147 rc = ieee80211_register_hw(hw);
3148 if (rc) {
3149 printk(KERN_ERR "%s: Cannot register device\n",
3150 wiphy_name(hw->wiphy));
3151 goto err_stop_firmware;
3152 }
3153
3154 printk(KERN_INFO "%s: 88w%u v%d, %pM, firmware version %u.%u.%u.%u\n",
3155 wiphy_name(hw->wiphy), priv->part_num, priv->hw_rev,
3156 hw->wiphy->perm_addr,
3157 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3158 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
3159
3160 return 0;
3161
3162 err_stop_firmware:
3163 mwl8k_hw_reset(priv);
3164 mwl8k_release_firmware(priv);
3165
3166 err_free_irq:
3167 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3168 free_irq(priv->pdev->irq, hw);
3169
3170 err_free_queues:
3171 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3172 mwl8k_txq_deinit(hw, i);
3173 mwl8k_rxq_deinit(hw, 0);
3174
3175 err_iounmap:
3176 if (priv->cookie != NULL)
3177 pci_free_consistent(priv->pdev, 4,
3178 priv->cookie, priv->cookie_dma);
3179
3180 if (priv->regs != NULL)
3181 pci_iounmap(pdev, priv->regs);
3182
3183 if (priv->sram != NULL)
3184 pci_iounmap(pdev, priv->sram);
3185
3186 pci_set_drvdata(pdev, NULL);
3187 ieee80211_free_hw(hw);
3188
3189 err_free_reg:
3190 pci_release_regions(pdev);
3191 pci_disable_device(pdev);
3192
3193 return rc;
3194 }
3195
3196 static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
3197 {
3198 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3199 }
3200
3201 static void __devexit mwl8k_remove(struct pci_dev *pdev)
3202 {
3203 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3204 struct mwl8k_priv *priv;
3205 int i;
3206
3207 if (hw == NULL)
3208 return;
3209 priv = hw->priv;
3210
3211 ieee80211_stop_queues(hw);
3212
3213 ieee80211_unregister_hw(hw);
3214
3215 /* Remove tx reclaim tasklet */
3216 tasklet_kill(&priv->tx_reclaim_task);
3217
3218 /* Stop hardware */
3219 mwl8k_hw_reset(priv);
3220
3221 /* Return all skbs to mac80211 */
3222 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3223 mwl8k_txq_reclaim(hw, i, 1);
3224
3225 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3226 mwl8k_txq_deinit(hw, i);
3227
3228 mwl8k_rxq_deinit(hw, 0);
3229
3230 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
3231
3232 pci_iounmap(pdev, priv->regs);
3233 pci_iounmap(pdev, priv->sram);
3234 pci_set_drvdata(pdev, NULL);
3235 ieee80211_free_hw(hw);
3236 pci_release_regions(pdev);
3237 pci_disable_device(pdev);
3238 }
3239
3240 static struct pci_driver mwl8k_driver = {
3241 .name = MWL8K_NAME,
3242 .id_table = mwl8k_table,
3243 .probe = mwl8k_probe,
3244 .remove = __devexit_p(mwl8k_remove),
3245 .shutdown = __devexit_p(mwl8k_shutdown),
3246 };
3247
3248 static int __init mwl8k_init(void)
3249 {
3250 return pci_register_driver(&mwl8k_driver);
3251 }
3252
3253 static void __exit mwl8k_exit(void)
3254 {
3255 pci_unregister_driver(&mwl8k_driver);
3256 }
3257
3258 module_init(mwl8k_init);
3259 module_exit(mwl8k_exit);
3260
3261 MODULE_DESCRIPTION(MWL8K_DESC);
3262 MODULE_VERSION(MWL8K_VERSION);
3263 MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3264 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.152744 seconds and 6 git commands to generate.