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mwl8k: enforce FIF_BCN_PRBRESP_PROMISC when no STA interfaces are active
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
1 /*
2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
4 *
5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/spinlock.h>
16 #include <linux/list.h>
17 #include <linux/pci.h>
18 #include <linux/delay.h>
19 #include <linux/completion.h>
20 #include <linux/etherdevice.h>
21 #include <net/mac80211.h>
22 #include <linux/moduleparam.h>
23 #include <linux/firmware.h>
24 #include <linux/workqueue.h>
25
26 #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
27 #define MWL8K_NAME KBUILD_MODNAME
28 #define MWL8K_VERSION "0.10"
29
30 static DEFINE_PCI_DEVICE_TABLE(mwl8k_table) = {
31 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = 8687, },
32 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = 8687, },
33 { }
34 };
35 MODULE_DEVICE_TABLE(pci, mwl8k_table);
36
37 /* Register definitions */
38 #define MWL8K_HIU_GEN_PTR 0x00000c10
39 #define MWL8K_MODE_STA 0x0000005a
40 #define MWL8K_MODE_AP 0x000000a5
41 #define MWL8K_HIU_INT_CODE 0x00000c14
42 #define MWL8K_FWSTA_READY 0xf0f1f2f4
43 #define MWL8K_FWAP_READY 0xf1f2f4a5
44 #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
45 #define MWL8K_HIU_SCRATCH 0x00000c40
46
47 /* Host->device communications */
48 #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
49 #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
50 #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
51 #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
52 #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
53 #define MWL8K_H2A_INT_DUMMY (1 << 20)
54 #define MWL8K_H2A_INT_RESET (1 << 15)
55 #define MWL8K_H2A_INT_DOORBELL (1 << 1)
56 #define MWL8K_H2A_INT_PPA_READY (1 << 0)
57
58 /* Device->host communications */
59 #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
60 #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
61 #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
62 #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
63 #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
64 #define MWL8K_A2H_INT_DUMMY (1 << 20)
65 #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
66 #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
67 #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
68 #define MWL8K_A2H_INT_RADIO_ON (1 << 6)
69 #define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
70 #define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
71 #define MWL8K_A2H_INT_OPC_DONE (1 << 2)
72 #define MWL8K_A2H_INT_RX_READY (1 << 1)
73 #define MWL8K_A2H_INT_TX_DONE (1 << 0)
74
75 #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
76 MWL8K_A2H_INT_CHNL_SWITCHED | \
77 MWL8K_A2H_INT_QUEUE_EMPTY | \
78 MWL8K_A2H_INT_RADAR_DETECT | \
79 MWL8K_A2H_INT_RADIO_ON | \
80 MWL8K_A2H_INT_RADIO_OFF | \
81 MWL8K_A2H_INT_MAC_EVENT | \
82 MWL8K_A2H_INT_OPC_DONE | \
83 MWL8K_A2H_INT_RX_READY | \
84 MWL8K_A2H_INT_TX_DONE)
85
86 /* WME stream classes */
87 #define WME_AC_BE 0 /* best effort */
88 #define WME_AC_BK 1 /* background */
89 #define WME_AC_VI 2 /* video */
90 #define WME_AC_VO 3 /* voice */
91
92 #define MWL8K_RX_QUEUES 1
93 #define MWL8K_TX_QUEUES 4
94
95 struct mwl8k_rx_queue {
96 int rx_desc_count;
97
98 /* hw receives here */
99 int rx_head;
100
101 /* refill descs here */
102 int rx_tail;
103
104 struct mwl8k_rx_desc *rx_desc_area;
105 dma_addr_t rx_desc_dma;
106 struct sk_buff **rx_skb;
107 };
108
109 struct mwl8k_tx_queue {
110 /* hw transmits here */
111 int tx_head;
112
113 /* sw appends here */
114 int tx_tail;
115
116 struct ieee80211_tx_queue_stats tx_stats;
117 struct mwl8k_tx_desc *tx_desc_area;
118 dma_addr_t tx_desc_dma;
119 struct sk_buff **tx_skb;
120 };
121
122 /* Pointers to the firmware data and meta information about it. */
123 struct mwl8k_firmware {
124 /* Microcode */
125 struct firmware *ucode;
126
127 /* Boot helper code */
128 struct firmware *helper;
129 };
130
131 struct mwl8k_priv {
132 void __iomem *regs;
133 struct ieee80211_hw *hw;
134
135 struct pci_dev *pdev;
136
137 /* firmware files and meta data */
138 struct mwl8k_firmware fw;
139 u32 part_num;
140
141 /* firmware access */
142 struct mutex fw_mutex;
143 struct task_struct *fw_mutex_owner;
144 int fw_mutex_depth;
145 struct completion *hostcmd_wait;
146
147 /* lock held over TX and TX reap */
148 spinlock_t tx_lock;
149
150 /* TX quiesce completion, protected by fw_mutex and tx_lock */
151 struct completion *tx_wait;
152
153 struct ieee80211_vif *vif;
154
155 struct ieee80211_channel *current_channel;
156
157 /* power management status cookie from firmware */
158 u32 *cookie;
159 dma_addr_t cookie_dma;
160
161 u16 num_mcaddrs;
162 u8 hw_rev;
163 u32 fw_rev;
164
165 /*
166 * Running count of TX packets in flight, to avoid
167 * iterating over the transmit rings each time.
168 */
169 int pending_tx_pkts;
170
171 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
172 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
173
174 /* PHY parameters */
175 struct ieee80211_supported_band band;
176 struct ieee80211_channel channels[14];
177 struct ieee80211_rate rates[12];
178
179 bool radio_on;
180 bool radio_short_preamble;
181 bool wmm_enabled;
182
183 /* XXX need to convert this to handle multiple interfaces */
184 bool capture_beacon;
185 u8 capture_bssid[ETH_ALEN];
186 struct sk_buff *beacon_skb;
187
188 /*
189 * This FJ worker has to be global as it is scheduled from the
190 * RX handler. At this point we don't know which interface it
191 * belongs to until the list of bssids waiting to complete join
192 * is checked.
193 */
194 struct work_struct finalize_join_worker;
195
196 /* Tasklet to reclaim TX descriptors and buffers after tx */
197 struct tasklet_struct tx_reclaim_task;
198 };
199
200 /* Per interface specific private data */
201 struct mwl8k_vif {
202 /* backpointer to parent config block */
203 struct mwl8k_priv *priv;
204
205 /* BSS config of AP or IBSS from mac80211*/
206 struct ieee80211_bss_conf bss_info;
207
208 /* BSSID of AP or IBSS */
209 u8 bssid[ETH_ALEN];
210 u8 mac_addr[ETH_ALEN];
211
212 /*
213 * Subset of supported legacy rates.
214 * Intersection of AP and STA supported rates.
215 */
216 struct ieee80211_rate legacy_rates[12];
217
218 /* number of supported legacy rates */
219 u8 legacy_nrates;
220
221 /* Index into station database.Returned by update_sta_db call */
222 u8 peer_id;
223
224 /* Non AMPDU sequence number assigned by driver */
225 u16 seqno;
226 };
227
228 #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
229
230 static const struct ieee80211_channel mwl8k_channels[] = {
231 { .center_freq = 2412, .hw_value = 1, },
232 { .center_freq = 2417, .hw_value = 2, },
233 { .center_freq = 2422, .hw_value = 3, },
234 { .center_freq = 2427, .hw_value = 4, },
235 { .center_freq = 2432, .hw_value = 5, },
236 { .center_freq = 2437, .hw_value = 6, },
237 { .center_freq = 2442, .hw_value = 7, },
238 { .center_freq = 2447, .hw_value = 8, },
239 { .center_freq = 2452, .hw_value = 9, },
240 { .center_freq = 2457, .hw_value = 10, },
241 { .center_freq = 2462, .hw_value = 11, },
242 };
243
244 static const struct ieee80211_rate mwl8k_rates[] = {
245 { .bitrate = 10, .hw_value = 2, },
246 { .bitrate = 20, .hw_value = 4, },
247 { .bitrate = 55, .hw_value = 11, },
248 { .bitrate = 60, .hw_value = 12, },
249 { .bitrate = 90, .hw_value = 18, },
250 { .bitrate = 110, .hw_value = 22, },
251 { .bitrate = 120, .hw_value = 24, },
252 { .bitrate = 180, .hw_value = 36, },
253 { .bitrate = 240, .hw_value = 48, },
254 { .bitrate = 360, .hw_value = 72, },
255 { .bitrate = 480, .hw_value = 96, },
256 { .bitrate = 540, .hw_value = 108, },
257 };
258
259 /* Set or get info from Firmware */
260 #define MWL8K_CMD_SET 0x0001
261 #define MWL8K_CMD_GET 0x0000
262
263 /* Firmware command codes */
264 #define MWL8K_CMD_CODE_DNLD 0x0001
265 #define MWL8K_CMD_GET_HW_SPEC 0x0003
266 #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
267 #define MWL8K_CMD_GET_STAT 0x0014
268 #define MWL8K_CMD_RADIO_CONTROL 0x001c
269 #define MWL8K_CMD_RF_TX_POWER 0x001e
270 #define MWL8K_CMD_SET_PRE_SCAN 0x0107
271 #define MWL8K_CMD_SET_POST_SCAN 0x0108
272 #define MWL8K_CMD_SET_RF_CHANNEL 0x010a
273 #define MWL8K_CMD_SET_AID 0x010d
274 #define MWL8K_CMD_SET_RATE 0x0110
275 #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
276 #define MWL8K_CMD_RTS_THRESHOLD 0x0113
277 #define MWL8K_CMD_SET_SLOT 0x0114
278 #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
279 #define MWL8K_CMD_SET_WMM_MODE 0x0123
280 #define MWL8K_CMD_MIMO_CONFIG 0x0125
281 #define MWL8K_CMD_USE_FIXED_RATE 0x0126
282 #define MWL8K_CMD_ENABLE_SNIFFER 0x0150
283 #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
284 #define MWL8K_CMD_UPDATE_STADB 0x1123
285
286 static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
287 {
288 #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
289 snprintf(buf, bufsize, "%s", #x);\
290 return buf;\
291 } while (0)
292 switch (cmd & ~0x8000) {
293 MWL8K_CMDNAME(CODE_DNLD);
294 MWL8K_CMDNAME(GET_HW_SPEC);
295 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
296 MWL8K_CMDNAME(GET_STAT);
297 MWL8K_CMDNAME(RADIO_CONTROL);
298 MWL8K_CMDNAME(RF_TX_POWER);
299 MWL8K_CMDNAME(SET_PRE_SCAN);
300 MWL8K_CMDNAME(SET_POST_SCAN);
301 MWL8K_CMDNAME(SET_RF_CHANNEL);
302 MWL8K_CMDNAME(SET_AID);
303 MWL8K_CMDNAME(SET_RATE);
304 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
305 MWL8K_CMDNAME(RTS_THRESHOLD);
306 MWL8K_CMDNAME(SET_SLOT);
307 MWL8K_CMDNAME(SET_EDCA_PARAMS);
308 MWL8K_CMDNAME(SET_WMM_MODE);
309 MWL8K_CMDNAME(MIMO_CONFIG);
310 MWL8K_CMDNAME(USE_FIXED_RATE);
311 MWL8K_CMDNAME(ENABLE_SNIFFER);
312 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
313 MWL8K_CMDNAME(UPDATE_STADB);
314 default:
315 snprintf(buf, bufsize, "0x%x", cmd);
316 }
317 #undef MWL8K_CMDNAME
318
319 return buf;
320 }
321
322 /* Hardware and firmware reset */
323 static void mwl8k_hw_reset(struct mwl8k_priv *priv)
324 {
325 iowrite32(MWL8K_H2A_INT_RESET,
326 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
327 iowrite32(MWL8K_H2A_INT_RESET,
328 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
329 msleep(20);
330 }
331
332 /* Release fw image */
333 static void mwl8k_release_fw(struct firmware **fw)
334 {
335 if (*fw == NULL)
336 return;
337 release_firmware(*fw);
338 *fw = NULL;
339 }
340
341 static void mwl8k_release_firmware(struct mwl8k_priv *priv)
342 {
343 mwl8k_release_fw(&priv->fw.ucode);
344 mwl8k_release_fw(&priv->fw.helper);
345 }
346
347 /* Request fw image */
348 static int mwl8k_request_fw(struct mwl8k_priv *priv,
349 const char *fname, struct firmware **fw)
350 {
351 /* release current image */
352 if (*fw != NULL)
353 mwl8k_release_fw(fw);
354
355 return request_firmware((const struct firmware **)fw,
356 fname, &priv->pdev->dev);
357 }
358
359 static int mwl8k_request_firmware(struct mwl8k_priv *priv, u32 part_num)
360 {
361 u8 filename[64];
362 int rc;
363
364 priv->part_num = part_num;
365
366 snprintf(filename, sizeof(filename),
367 "mwl8k/helper_%u.fw", priv->part_num);
368
369 rc = mwl8k_request_fw(priv, filename, &priv->fw.helper);
370 if (rc) {
371 printk(KERN_ERR "%s: Error requesting helper firmware "
372 "file %s\n", pci_name(priv->pdev), filename);
373 return rc;
374 }
375
376 snprintf(filename, sizeof(filename),
377 "mwl8k/fmimage_%u.fw", priv->part_num);
378
379 rc = mwl8k_request_fw(priv, filename, &priv->fw.ucode);
380 if (rc) {
381 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
382 pci_name(priv->pdev), filename);
383 mwl8k_release_fw(&priv->fw.helper);
384 return rc;
385 }
386
387 return 0;
388 }
389
390 struct mwl8k_cmd_pkt {
391 __le16 code;
392 __le16 length;
393 __le16 seq_num;
394 __le16 result;
395 char payload[0];
396 } __attribute__((packed));
397
398 /*
399 * Firmware loading.
400 */
401 static int
402 mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
403 {
404 void __iomem *regs = priv->regs;
405 dma_addr_t dma_addr;
406 int loops;
407
408 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
409 if (pci_dma_mapping_error(priv->pdev, dma_addr))
410 return -ENOMEM;
411
412 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
413 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
414 iowrite32(MWL8K_H2A_INT_DOORBELL,
415 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
416 iowrite32(MWL8K_H2A_INT_DUMMY,
417 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
418
419 loops = 1000;
420 do {
421 u32 int_code;
422
423 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
424 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
425 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
426 break;
427 }
428
429 udelay(1);
430 } while (--loops);
431
432 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
433
434 return loops ? 0 : -ETIMEDOUT;
435 }
436
437 static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
438 const u8 *data, size_t length)
439 {
440 struct mwl8k_cmd_pkt *cmd;
441 int done;
442 int rc = 0;
443
444 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
445 if (cmd == NULL)
446 return -ENOMEM;
447
448 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
449 cmd->seq_num = 0;
450 cmd->result = 0;
451
452 done = 0;
453 while (length) {
454 int block_size = length > 256 ? 256 : length;
455
456 memcpy(cmd->payload, data + done, block_size);
457 cmd->length = cpu_to_le16(block_size);
458
459 rc = mwl8k_send_fw_load_cmd(priv, cmd,
460 sizeof(*cmd) + block_size);
461 if (rc)
462 break;
463
464 done += block_size;
465 length -= block_size;
466 }
467
468 if (!rc) {
469 cmd->length = 0;
470 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
471 }
472
473 kfree(cmd);
474
475 return rc;
476 }
477
478 static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
479 const u8 *data, size_t length)
480 {
481 unsigned char *buffer;
482 int may_continue, rc = 0;
483 u32 done, prev_block_size;
484
485 buffer = kmalloc(1024, GFP_KERNEL);
486 if (buffer == NULL)
487 return -ENOMEM;
488
489 done = 0;
490 prev_block_size = 0;
491 may_continue = 1000;
492 while (may_continue > 0) {
493 u32 block_size;
494
495 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
496 if (block_size & 1) {
497 block_size &= ~1;
498 may_continue--;
499 } else {
500 done += prev_block_size;
501 length -= prev_block_size;
502 }
503
504 if (block_size > 1024 || block_size > length) {
505 rc = -EOVERFLOW;
506 break;
507 }
508
509 if (length == 0) {
510 rc = 0;
511 break;
512 }
513
514 if (block_size == 0) {
515 rc = -EPROTO;
516 may_continue--;
517 udelay(1);
518 continue;
519 }
520
521 prev_block_size = block_size;
522 memcpy(buffer, data + done, block_size);
523
524 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
525 if (rc)
526 break;
527 }
528
529 if (!rc && length != 0)
530 rc = -EREMOTEIO;
531
532 kfree(buffer);
533
534 return rc;
535 }
536
537 static int mwl8k_load_firmware(struct ieee80211_hw *hw)
538 {
539 struct mwl8k_priv *priv = hw->priv;
540 struct firmware *fw = priv->fw.ucode;
541 int rc;
542 int loops;
543
544 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
545 struct firmware *helper = priv->fw.helper;
546
547 if (helper == NULL) {
548 printk(KERN_ERR "%s: helper image needed but none "
549 "given\n", pci_name(priv->pdev));
550 return -EINVAL;
551 }
552
553 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
554 if (rc) {
555 printk(KERN_ERR "%s: unable to load firmware "
556 "helper image\n", pci_name(priv->pdev));
557 return rc;
558 }
559 msleep(1);
560
561 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
562 } else {
563 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
564 }
565
566 if (rc) {
567 printk(KERN_ERR "%s: unable to load firmware image\n",
568 pci_name(priv->pdev));
569 return rc;
570 }
571
572 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
573 msleep(1);
574
575 loops = 200000;
576 do {
577 if (ioread32(priv->regs + MWL8K_HIU_INT_CODE)
578 == MWL8K_FWSTA_READY)
579 break;
580 udelay(1);
581 } while (--loops);
582
583 return loops ? 0 : -ETIMEDOUT;
584 }
585
586
587 /*
588 * Defines shared between transmission and reception.
589 */
590 /* HT control fields for firmware */
591 struct ewc_ht_info {
592 __le16 control1;
593 __le16 control2;
594 __le16 control3;
595 } __attribute__((packed));
596
597 /* Firmware Station database operations */
598 #define MWL8K_STA_DB_ADD_ENTRY 0
599 #define MWL8K_STA_DB_MODIFY_ENTRY 1
600 #define MWL8K_STA_DB_DEL_ENTRY 2
601 #define MWL8K_STA_DB_FLUSH 3
602
603 /* Peer Entry flags - used to define the type of the peer node */
604 #define MWL8K_PEER_TYPE_ACCESSPOINT 2
605
606 #define MWL8K_IEEE_LEGACY_DATA_RATES 12
607 #define MWL8K_MCS_BITMAP_SIZE 16
608
609 struct peer_capability_info {
610 /* Peer type - AP vs. STA. */
611 __u8 peer_type;
612
613 /* Basic 802.11 capabilities from assoc resp. */
614 __le16 basic_caps;
615
616 /* Set if peer supports 802.11n high throughput (HT). */
617 __u8 ht_support;
618
619 /* Valid if HT is supported. */
620 __le16 ht_caps;
621 __u8 extended_ht_caps;
622 struct ewc_ht_info ewc_info;
623
624 /* Legacy rate table. Intersection of our rates and peer rates. */
625 __u8 legacy_rates[MWL8K_IEEE_LEGACY_DATA_RATES];
626
627 /* HT rate table. Intersection of our rates and peer rates. */
628 __u8 ht_rates[MWL8K_MCS_BITMAP_SIZE];
629 __u8 pad[16];
630
631 /* If set, interoperability mode, no proprietary extensions. */
632 __u8 interop;
633 __u8 pad2;
634 __u8 station_id;
635 __le16 amsdu_enabled;
636 } __attribute__((packed));
637
638 /* Inline functions to manipulate QoS field in data descriptor. */
639 static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
640 {
641 u16 val_mask = 1 << 4;
642
643 /* End of Service Period Bit 4 */
644 return qos | val_mask;
645 }
646
647 static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
648 {
649 u16 val_mask = 0x3;
650 u8 shift = 5;
651 u16 qos_mask = ~(val_mask << shift);
652
653 /* Ack Policy Bit 5-6 */
654 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
655 }
656
657 static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
658 {
659 u16 val_mask = 1 << 7;
660
661 /* AMSDU present Bit 7 */
662 return qos | val_mask;
663 }
664
665 static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
666 {
667 u16 val_mask = 0xff;
668 u8 shift = 8;
669 u16 qos_mask = ~(val_mask << shift);
670
671 /* Queue Length Bits 8-15 */
672 return (qos & qos_mask) | ((len & val_mask) << shift);
673 }
674
675 /* DMA header used by firmware and hardware. */
676 struct mwl8k_dma_data {
677 __le16 fwlen;
678 struct ieee80211_hdr wh;
679 } __attribute__((packed));
680
681 /* Routines to add/remove DMA header from skb. */
682 static inline void mwl8k_remove_dma_header(struct sk_buff *skb)
683 {
684 struct mwl8k_dma_data *tr = (struct mwl8k_dma_data *)skb->data;
685 void *dst, *src = &tr->wh;
686 int hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
687 u16 space = sizeof(struct mwl8k_dma_data) - hdrlen;
688
689 dst = (void *)tr + space;
690 if (dst != src) {
691 memmove(dst, src, hdrlen);
692 skb_pull(skb, space);
693 }
694 }
695
696 static inline void mwl8k_add_dma_header(struct sk_buff *skb)
697 {
698 struct ieee80211_hdr *wh;
699 u32 hdrlen, pktlen;
700 struct mwl8k_dma_data *tr;
701
702 wh = (struct ieee80211_hdr *)skb->data;
703 hdrlen = ieee80211_hdrlen(wh->frame_control);
704 pktlen = skb->len;
705
706 /*
707 * Copy up/down the 802.11 header; the firmware requires
708 * we present a 2-byte payload length followed by a
709 * 4-address header (w/o QoS), followed (optionally) by
710 * any WEP/ExtIV header (but only filled in for CCMP).
711 */
712 if (hdrlen != sizeof(struct mwl8k_dma_data))
713 skb_push(skb, sizeof(struct mwl8k_dma_data) - hdrlen);
714
715 tr = (struct mwl8k_dma_data *)skb->data;
716 if (wh != &tr->wh)
717 memmove(&tr->wh, wh, hdrlen);
718
719 /* Clear addr4 */
720 memset(tr->wh.addr4, 0, ETH_ALEN);
721
722 /*
723 * Firmware length is the length of the fully formed "802.11
724 * payload". That is, everything except for the 802.11 header.
725 * This includes all crypto material including the MIC.
726 */
727 tr->fwlen = cpu_to_le16(pktlen - hdrlen);
728 }
729
730
731 /*
732 * Packet reception.
733 */
734 #define MWL8K_RX_CTRL_OWNED_BY_HOST 0x02
735
736 struct mwl8k_rx_desc {
737 __le16 pkt_len;
738 __u8 link_quality;
739 __u8 noise_level;
740 __le32 pkt_phys_addr;
741 __le32 next_rx_desc_phys_addr;
742 __le16 qos_control;
743 __le16 rate_info;
744 __le32 pad0[4];
745 __u8 rssi;
746 __u8 channel;
747 __le16 pad1;
748 __u8 rx_ctrl;
749 __u8 rx_status;
750 __u8 pad2[2];
751 } __attribute__((packed));
752
753 #define MWL8K_RX_DESCS 256
754 #define MWL8K_RX_MAXSZ 3800
755
756 static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
757 {
758 struct mwl8k_priv *priv = hw->priv;
759 struct mwl8k_rx_queue *rxq = priv->rxq + index;
760 int size;
761 int i;
762
763 rxq->rx_desc_count = 0;
764 rxq->rx_head = 0;
765 rxq->rx_tail = 0;
766
767 size = MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc);
768
769 rxq->rx_desc_area =
770 pci_alloc_consistent(priv->pdev, size, &rxq->rx_desc_dma);
771 if (rxq->rx_desc_area == NULL) {
772 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
773 wiphy_name(hw->wiphy));
774 return -ENOMEM;
775 }
776 memset(rxq->rx_desc_area, 0, size);
777
778 rxq->rx_skb = kmalloc(MWL8K_RX_DESCS *
779 sizeof(*rxq->rx_skb), GFP_KERNEL);
780 if (rxq->rx_skb == NULL) {
781 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
782 wiphy_name(hw->wiphy));
783 pci_free_consistent(priv->pdev, size,
784 rxq->rx_desc_area, rxq->rx_desc_dma);
785 return -ENOMEM;
786 }
787 memset(rxq->rx_skb, 0, MWL8K_RX_DESCS * sizeof(*rxq->rx_skb));
788
789 for (i = 0; i < MWL8K_RX_DESCS; i++) {
790 struct mwl8k_rx_desc *rx_desc;
791 int nexti;
792
793 rx_desc = rxq->rx_desc_area + i;
794 nexti = (i + 1) % MWL8K_RX_DESCS;
795
796 rx_desc->next_rx_desc_phys_addr =
797 cpu_to_le32(rxq->rx_desc_dma
798 + nexti * sizeof(*rx_desc));
799 rx_desc->rx_ctrl = MWL8K_RX_CTRL_OWNED_BY_HOST;
800 }
801
802 return 0;
803 }
804
805 static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
806 {
807 struct mwl8k_priv *priv = hw->priv;
808 struct mwl8k_rx_queue *rxq = priv->rxq + index;
809 int refilled;
810
811 refilled = 0;
812 while (rxq->rx_desc_count < MWL8K_RX_DESCS && limit--) {
813 struct sk_buff *skb;
814 int rx;
815
816 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
817 if (skb == NULL)
818 break;
819
820 rxq->rx_desc_count++;
821
822 rx = rxq->rx_tail;
823 rxq->rx_tail = (rx + 1) % MWL8K_RX_DESCS;
824
825 rxq->rx_desc_area[rx].pkt_phys_addr =
826 cpu_to_le32(pci_map_single(priv->pdev, skb->data,
827 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE));
828
829 rxq->rx_desc_area[rx].pkt_len = cpu_to_le16(MWL8K_RX_MAXSZ);
830 rxq->rx_skb[rx] = skb;
831 wmb();
832 rxq->rx_desc_area[rx].rx_ctrl = 0;
833
834 refilled++;
835 }
836
837 return refilled;
838 }
839
840 /* Must be called only when the card's reception is completely halted */
841 static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
842 {
843 struct mwl8k_priv *priv = hw->priv;
844 struct mwl8k_rx_queue *rxq = priv->rxq + index;
845 int i;
846
847 for (i = 0; i < MWL8K_RX_DESCS; i++) {
848 if (rxq->rx_skb[i] != NULL) {
849 unsigned long addr;
850
851 addr = le32_to_cpu(rxq->rx_desc_area[i].pkt_phys_addr);
852 pci_unmap_single(priv->pdev, addr, MWL8K_RX_MAXSZ,
853 PCI_DMA_FROMDEVICE);
854 kfree_skb(rxq->rx_skb[i]);
855 rxq->rx_skb[i] = NULL;
856 }
857 }
858
859 kfree(rxq->rx_skb);
860 rxq->rx_skb = NULL;
861
862 pci_free_consistent(priv->pdev,
863 MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc),
864 rxq->rx_desc_area, rxq->rx_desc_dma);
865 rxq->rx_desc_area = NULL;
866 }
867
868
869 /*
870 * Scan a list of BSSIDs to process for finalize join.
871 * Allows for extension to process multiple BSSIDs.
872 */
873 static inline int
874 mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
875 {
876 return priv->capture_beacon &&
877 ieee80211_is_beacon(wh->frame_control) &&
878 !compare_ether_addr(wh->addr3, priv->capture_bssid);
879 }
880
881 static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
882 struct sk_buff *skb)
883 {
884 struct mwl8k_priv *priv = hw->priv;
885
886 priv->capture_beacon = false;
887 memset(priv->capture_bssid, 0, ETH_ALEN);
888
889 /*
890 * Use GFP_ATOMIC as rxq_process is called from
891 * the primary interrupt handler, memory allocation call
892 * must not sleep.
893 */
894 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
895 if (priv->beacon_skb != NULL)
896 ieee80211_queue_work(hw, &priv->finalize_join_worker);
897 }
898
899 static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
900 {
901 struct mwl8k_priv *priv = hw->priv;
902 struct mwl8k_rx_queue *rxq = priv->rxq + index;
903 int processed;
904
905 processed = 0;
906 while (rxq->rx_desc_count && limit--) {
907 struct mwl8k_rx_desc *rx_desc;
908 struct sk_buff *skb;
909 struct ieee80211_rx_status status;
910 unsigned long addr;
911 struct ieee80211_hdr *wh;
912
913 rx_desc = rxq->rx_desc_area + rxq->rx_head;
914 if (!(rx_desc->rx_ctrl & MWL8K_RX_CTRL_OWNED_BY_HOST))
915 break;
916 rmb();
917
918 skb = rxq->rx_skb[rxq->rx_head];
919 if (skb == NULL)
920 break;
921 rxq->rx_skb[rxq->rx_head] = NULL;
922
923 rxq->rx_head = (rxq->rx_head + 1) % MWL8K_RX_DESCS;
924 rxq->rx_desc_count--;
925
926 addr = le32_to_cpu(rx_desc->pkt_phys_addr);
927 pci_unmap_single(priv->pdev, addr,
928 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
929
930 skb_put(skb, le16_to_cpu(rx_desc->pkt_len));
931 mwl8k_remove_dma_header(skb);
932
933 wh = (struct ieee80211_hdr *)skb->data;
934
935 /*
936 * Check for a pending join operation. Save a
937 * copy of the beacon and schedule a tasklet to
938 * send a FINALIZE_JOIN command to the firmware.
939 */
940 if (mwl8k_capture_bssid(priv, wh))
941 mwl8k_save_beacon(hw, skb);
942
943 memset(&status, 0, sizeof(status));
944 status.mactime = 0;
945 status.signal = -rx_desc->rssi;
946 status.noise = -rx_desc->noise_level;
947 status.qual = rx_desc->link_quality;
948 status.antenna = 1;
949 status.rate_idx = 1;
950 status.flag = 0;
951 status.band = IEEE80211_BAND_2GHZ;
952 status.freq = ieee80211_channel_to_frequency(rx_desc->channel);
953 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
954 ieee80211_rx_irqsafe(hw, skb);
955
956 processed++;
957 }
958
959 return processed;
960 }
961
962
963 /*
964 * Packet transmission.
965 */
966
967 /* Transmit queue assignment. */
968 enum {
969 MWL8K_WME_AC_BK = 0, /* background access */
970 MWL8K_WME_AC_BE = 1, /* best effort access */
971 MWL8K_WME_AC_VI = 2, /* video access */
972 MWL8K_WME_AC_VO = 3, /* voice access */
973 };
974
975 /* Transmit packet ACK policy */
976 #define MWL8K_TXD_ACK_POLICY_NORMAL 0
977 #define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
978
979 #define GET_TXQ(_ac) (\
980 ((_ac) == WME_AC_VO) ? MWL8K_WME_AC_VO : \
981 ((_ac) == WME_AC_VI) ? MWL8K_WME_AC_VI : \
982 ((_ac) == WME_AC_BK) ? MWL8K_WME_AC_BK : \
983 MWL8K_WME_AC_BE)
984
985 #define MWL8K_TXD_STATUS_OK 0x00000001
986 #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
987 #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
988 #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
989 #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
990
991 struct mwl8k_tx_desc {
992 __le32 status;
993 __u8 data_rate;
994 __u8 tx_priority;
995 __le16 qos_control;
996 __le32 pkt_phys_addr;
997 __le16 pkt_len;
998 __u8 dest_MAC_addr[ETH_ALEN];
999 __le32 next_tx_desc_phys_addr;
1000 __le32 reserved;
1001 __le16 rate_info;
1002 __u8 peer_id;
1003 __u8 tx_frag_cnt;
1004 } __attribute__((packed));
1005
1006 #define MWL8K_TX_DESCS 128
1007
1008 static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1009 {
1010 struct mwl8k_priv *priv = hw->priv;
1011 struct mwl8k_tx_queue *txq = priv->txq + index;
1012 int size;
1013 int i;
1014
1015 memset(&txq->tx_stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1016 txq->tx_stats.limit = MWL8K_TX_DESCS;
1017 txq->tx_head = 0;
1018 txq->tx_tail = 0;
1019
1020 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1021
1022 txq->tx_desc_area =
1023 pci_alloc_consistent(priv->pdev, size, &txq->tx_desc_dma);
1024 if (txq->tx_desc_area == NULL) {
1025 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
1026 wiphy_name(hw->wiphy));
1027 return -ENOMEM;
1028 }
1029 memset(txq->tx_desc_area, 0, size);
1030
1031 txq->tx_skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->tx_skb),
1032 GFP_KERNEL);
1033 if (txq->tx_skb == NULL) {
1034 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
1035 wiphy_name(hw->wiphy));
1036 pci_free_consistent(priv->pdev, size,
1037 txq->tx_desc_area, txq->tx_desc_dma);
1038 return -ENOMEM;
1039 }
1040 memset(txq->tx_skb, 0, MWL8K_TX_DESCS * sizeof(*txq->tx_skb));
1041
1042 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1043 struct mwl8k_tx_desc *tx_desc;
1044 int nexti;
1045
1046 tx_desc = txq->tx_desc_area + i;
1047 nexti = (i + 1) % MWL8K_TX_DESCS;
1048
1049 tx_desc->status = 0;
1050 tx_desc->next_tx_desc_phys_addr =
1051 cpu_to_le32(txq->tx_desc_dma +
1052 nexti * sizeof(*tx_desc));
1053 }
1054
1055 return 0;
1056 }
1057
1058 static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1059 {
1060 iowrite32(MWL8K_H2A_INT_PPA_READY,
1061 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1062 iowrite32(MWL8K_H2A_INT_DUMMY,
1063 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1064 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1065 }
1066
1067 struct mwl8k_txq_info {
1068 u32 fw_owned;
1069 u32 drv_owned;
1070 u32 unused;
1071 u32 len;
1072 u32 head;
1073 u32 tail;
1074 };
1075
1076 static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
1077 struct mwl8k_txq_info *txinfo)
1078 {
1079 int count, desc, status;
1080 struct mwl8k_tx_queue *txq;
1081 struct mwl8k_tx_desc *tx_desc;
1082 int ndescs = 0;
1083
1084 memset(txinfo, 0, MWL8K_TX_QUEUES * sizeof(struct mwl8k_txq_info));
1085
1086 for (count = 0; count < MWL8K_TX_QUEUES; count++) {
1087 txq = priv->txq + count;
1088 txinfo[count].len = txq->tx_stats.len;
1089 txinfo[count].head = txq->tx_head;
1090 txinfo[count].tail = txq->tx_tail;
1091 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1092 tx_desc = txq->tx_desc_area + desc;
1093 status = le32_to_cpu(tx_desc->status);
1094
1095 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1096 txinfo[count].fw_owned++;
1097 else
1098 txinfo[count].drv_owned++;
1099
1100 if (tx_desc->pkt_len == 0)
1101 txinfo[count].unused++;
1102 }
1103 }
1104
1105 return ndescs;
1106 }
1107
1108 /*
1109 * Must be called with priv->fw_mutex held and tx queues stopped.
1110 */
1111 static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
1112 {
1113 struct mwl8k_priv *priv = hw->priv;
1114 DECLARE_COMPLETION_ONSTACK(tx_wait);
1115 u32 count;
1116 unsigned long timeout;
1117
1118 might_sleep();
1119
1120 spin_lock_bh(&priv->tx_lock);
1121 count = priv->pending_tx_pkts;
1122 if (count)
1123 priv->tx_wait = &tx_wait;
1124 spin_unlock_bh(&priv->tx_lock);
1125
1126 if (count) {
1127 struct mwl8k_txq_info txinfo[MWL8K_TX_QUEUES];
1128 int index;
1129 int newcount;
1130
1131 timeout = wait_for_completion_timeout(&tx_wait,
1132 msecs_to_jiffies(5000));
1133 if (timeout)
1134 return 0;
1135
1136 spin_lock_bh(&priv->tx_lock);
1137 priv->tx_wait = NULL;
1138 newcount = priv->pending_tx_pkts;
1139 mwl8k_scan_tx_ring(priv, txinfo);
1140 spin_unlock_bh(&priv->tx_lock);
1141
1142 printk(KERN_ERR "%s(%u) TIMEDOUT:5000ms Pend:%u-->%u\n",
1143 __func__, __LINE__, count, newcount);
1144
1145 for (index = 0; index < MWL8K_TX_QUEUES; index++)
1146 printk(KERN_ERR "TXQ:%u L:%u H:%u T:%u FW:%u "
1147 "DRV:%u U:%u\n",
1148 index,
1149 txinfo[index].len,
1150 txinfo[index].head,
1151 txinfo[index].tail,
1152 txinfo[index].fw_owned,
1153 txinfo[index].drv_owned,
1154 txinfo[index].unused);
1155
1156 return -ETIMEDOUT;
1157 }
1158
1159 return 0;
1160 }
1161
1162 #define MWL8K_TXD_SUCCESS(status) \
1163 ((status) & (MWL8K_TXD_STATUS_OK | \
1164 MWL8K_TXD_STATUS_OK_RETRY | \
1165 MWL8K_TXD_STATUS_OK_MORE_RETRY))
1166
1167 static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1168 {
1169 struct mwl8k_priv *priv = hw->priv;
1170 struct mwl8k_tx_queue *txq = priv->txq + index;
1171 int wake = 0;
1172
1173 while (txq->tx_stats.len > 0) {
1174 int tx;
1175 struct mwl8k_tx_desc *tx_desc;
1176 unsigned long addr;
1177 int size;
1178 struct sk_buff *skb;
1179 struct ieee80211_tx_info *info;
1180 u32 status;
1181
1182 tx = txq->tx_head;
1183 tx_desc = txq->tx_desc_area + tx;
1184
1185 status = le32_to_cpu(tx_desc->status);
1186
1187 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1188 if (!force)
1189 break;
1190 tx_desc->status &=
1191 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1192 }
1193
1194 txq->tx_head = (tx + 1) % MWL8K_TX_DESCS;
1195 BUG_ON(txq->tx_stats.len == 0);
1196 txq->tx_stats.len--;
1197 priv->pending_tx_pkts--;
1198
1199 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
1200 size = le16_to_cpu(tx_desc->pkt_len);
1201 skb = txq->tx_skb[tx];
1202 txq->tx_skb[tx] = NULL;
1203
1204 BUG_ON(skb == NULL);
1205 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1206
1207 mwl8k_remove_dma_header(skb);
1208
1209 /* Mark descriptor as unused */
1210 tx_desc->pkt_phys_addr = 0;
1211 tx_desc->pkt_len = 0;
1212
1213 info = IEEE80211_SKB_CB(skb);
1214 ieee80211_tx_info_clear_status(info);
1215 if (MWL8K_TXD_SUCCESS(status))
1216 info->flags |= IEEE80211_TX_STAT_ACK;
1217
1218 ieee80211_tx_status_irqsafe(hw, skb);
1219
1220 wake = 1;
1221 }
1222
1223 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
1224 ieee80211_wake_queue(hw, index);
1225 }
1226
1227 /* must be called only when the card's transmit is completely halted */
1228 static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1229 {
1230 struct mwl8k_priv *priv = hw->priv;
1231 struct mwl8k_tx_queue *txq = priv->txq + index;
1232
1233 mwl8k_txq_reclaim(hw, index, 1);
1234
1235 kfree(txq->tx_skb);
1236 txq->tx_skb = NULL;
1237
1238 pci_free_consistent(priv->pdev,
1239 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1240 txq->tx_desc_area, txq->tx_desc_dma);
1241 txq->tx_desc_area = NULL;
1242 }
1243
1244 static int
1245 mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1246 {
1247 struct mwl8k_priv *priv = hw->priv;
1248 struct ieee80211_tx_info *tx_info;
1249 struct mwl8k_vif *mwl8k_vif;
1250 struct ieee80211_hdr *wh;
1251 struct mwl8k_tx_queue *txq;
1252 struct mwl8k_tx_desc *tx;
1253 dma_addr_t dma;
1254 u32 txstatus;
1255 u8 txdatarate;
1256 u16 qos;
1257
1258 wh = (struct ieee80211_hdr *)skb->data;
1259 if (ieee80211_is_data_qos(wh->frame_control))
1260 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1261 else
1262 qos = 0;
1263
1264 mwl8k_add_dma_header(skb);
1265 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
1266
1267 tx_info = IEEE80211_SKB_CB(skb);
1268 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
1269
1270 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1271 u16 seqno = mwl8k_vif->seqno;
1272
1273 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1274 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1275 mwl8k_vif->seqno = seqno++ % 4096;
1276 }
1277
1278 /* Setup firmware control bit fields for each frame type. */
1279 txstatus = 0;
1280 txdatarate = 0;
1281 if (ieee80211_is_mgmt(wh->frame_control) ||
1282 ieee80211_is_ctl(wh->frame_control)) {
1283 txdatarate = 0;
1284 qos = mwl8k_qos_setbit_eosp(qos);
1285 /* Set Queue size to unspecified */
1286 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1287 } else if (ieee80211_is_data(wh->frame_control)) {
1288 txdatarate = 1;
1289 if (is_multicast_ether_addr(wh->addr1))
1290 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1291
1292 /* Send pkt in an aggregate if AMPDU frame. */
1293 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1294 qos = mwl8k_qos_setbit_ack(qos,
1295 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1296 else
1297 qos = mwl8k_qos_setbit_ack(qos,
1298 MWL8K_TXD_ACK_POLICY_NORMAL);
1299
1300 if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
1301 qos = mwl8k_qos_setbit_amsdu(qos);
1302 }
1303
1304 dma = pci_map_single(priv->pdev, skb->data,
1305 skb->len, PCI_DMA_TODEVICE);
1306
1307 if (pci_dma_mapping_error(priv->pdev, dma)) {
1308 printk(KERN_DEBUG "%s: failed to dma map skb, "
1309 "dropping TX frame.\n", wiphy_name(hw->wiphy));
1310 dev_kfree_skb(skb);
1311 return NETDEV_TX_OK;
1312 }
1313
1314 spin_lock_bh(&priv->tx_lock);
1315
1316 txq = priv->txq + index;
1317
1318 BUG_ON(txq->tx_skb[txq->tx_tail] != NULL);
1319 txq->tx_skb[txq->tx_tail] = skb;
1320
1321 tx = txq->tx_desc_area + txq->tx_tail;
1322 tx->data_rate = txdatarate;
1323 tx->tx_priority = index;
1324 tx->qos_control = cpu_to_le16(qos);
1325 tx->pkt_phys_addr = cpu_to_le32(dma);
1326 tx->pkt_len = cpu_to_le16(skb->len);
1327 tx->rate_info = 0;
1328 tx->peer_id = mwl8k_vif->peer_id;
1329 wmb();
1330 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1331
1332 txq->tx_stats.count++;
1333 txq->tx_stats.len++;
1334 priv->pending_tx_pkts++;
1335
1336 txq->tx_tail++;
1337 if (txq->tx_tail == MWL8K_TX_DESCS)
1338 txq->tx_tail = 0;
1339
1340 if (txq->tx_head == txq->tx_tail)
1341 ieee80211_stop_queue(hw, index);
1342
1343 mwl8k_tx_start(priv);
1344
1345 spin_unlock_bh(&priv->tx_lock);
1346
1347 return NETDEV_TX_OK;
1348 }
1349
1350
1351 /*
1352 * Firmware access.
1353 *
1354 * We have the following requirements for issuing firmware commands:
1355 * - Some commands require that the packet transmit path is idle when
1356 * the command is issued. (For simplicity, we'll just quiesce the
1357 * transmit path for every command.)
1358 * - There are certain sequences of commands that need to be issued to
1359 * the hardware sequentially, with no other intervening commands.
1360 *
1361 * This leads to an implementation of a "firmware lock" as a mutex that
1362 * can be taken recursively, and which is taken by both the low-level
1363 * command submission function (mwl8k_post_cmd) as well as any users of
1364 * that function that require issuing of an atomic sequence of commands,
1365 * and quiesces the transmit path whenever it's taken.
1366 */
1367 static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1368 {
1369 struct mwl8k_priv *priv = hw->priv;
1370
1371 if (priv->fw_mutex_owner != current) {
1372 int rc;
1373
1374 mutex_lock(&priv->fw_mutex);
1375 ieee80211_stop_queues(hw);
1376
1377 rc = mwl8k_tx_wait_empty(hw);
1378 if (rc) {
1379 ieee80211_wake_queues(hw);
1380 mutex_unlock(&priv->fw_mutex);
1381
1382 return rc;
1383 }
1384
1385 priv->fw_mutex_owner = current;
1386 }
1387
1388 priv->fw_mutex_depth++;
1389
1390 return 0;
1391 }
1392
1393 static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1394 {
1395 struct mwl8k_priv *priv = hw->priv;
1396
1397 if (!--priv->fw_mutex_depth) {
1398 ieee80211_wake_queues(hw);
1399 priv->fw_mutex_owner = NULL;
1400 mutex_unlock(&priv->fw_mutex);
1401 }
1402 }
1403
1404
1405 /*
1406 * Command processing.
1407 */
1408
1409 /* Timeout firmware commands after 2000ms */
1410 #define MWL8K_CMD_TIMEOUT_MS 2000
1411
1412 static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1413 {
1414 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1415 struct mwl8k_priv *priv = hw->priv;
1416 void __iomem *regs = priv->regs;
1417 dma_addr_t dma_addr;
1418 unsigned int dma_size;
1419 int rc;
1420 unsigned long timeout = 0;
1421 u8 buf[32];
1422
1423 cmd->result = 0xffff;
1424 dma_size = le16_to_cpu(cmd->length);
1425 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1426 PCI_DMA_BIDIRECTIONAL);
1427 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1428 return -ENOMEM;
1429
1430 rc = mwl8k_fw_lock(hw);
1431 if (rc) {
1432 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1433 PCI_DMA_BIDIRECTIONAL);
1434 return rc;
1435 }
1436
1437 priv->hostcmd_wait = &cmd_wait;
1438 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1439 iowrite32(MWL8K_H2A_INT_DOORBELL,
1440 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1441 iowrite32(MWL8K_H2A_INT_DUMMY,
1442 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1443
1444 timeout = wait_for_completion_timeout(&cmd_wait,
1445 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1446
1447 priv->hostcmd_wait = NULL;
1448
1449 mwl8k_fw_unlock(hw);
1450
1451 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1452 PCI_DMA_BIDIRECTIONAL);
1453
1454 if (!timeout) {
1455 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
1456 wiphy_name(hw->wiphy),
1457 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1458 MWL8K_CMD_TIMEOUT_MS);
1459 rc = -ETIMEDOUT;
1460 } else {
1461 rc = cmd->result ? -EINVAL : 0;
1462 if (rc)
1463 printk(KERN_ERR "%s: Command %s error 0x%x\n",
1464 wiphy_name(hw->wiphy),
1465 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1466 le16_to_cpu(cmd->result));
1467 }
1468
1469 return rc;
1470 }
1471
1472 /*
1473 * GET_HW_SPEC.
1474 */
1475 struct mwl8k_cmd_get_hw_spec {
1476 struct mwl8k_cmd_pkt header;
1477 __u8 hw_rev;
1478 __u8 host_interface;
1479 __le16 num_mcaddrs;
1480 __u8 perm_addr[ETH_ALEN];
1481 __le16 region_code;
1482 __le32 fw_rev;
1483 __le32 ps_cookie;
1484 __le32 caps;
1485 __u8 mcs_bitmap[16];
1486 __le32 rx_queue_ptr;
1487 __le32 num_tx_queues;
1488 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1489 __le32 caps2;
1490 __le32 num_tx_desc_per_queue;
1491 __le32 total_rx_desc;
1492 } __attribute__((packed));
1493
1494 static int mwl8k_cmd_get_hw_spec(struct ieee80211_hw *hw)
1495 {
1496 struct mwl8k_priv *priv = hw->priv;
1497 struct mwl8k_cmd_get_hw_spec *cmd;
1498 int rc;
1499 int i;
1500
1501 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1502 if (cmd == NULL)
1503 return -ENOMEM;
1504
1505 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1506 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1507
1508 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1509 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1510 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rx_desc_dma);
1511 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1512 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1513 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].tx_desc_dma);
1514 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1515 cmd->total_rx_desc = cpu_to_le32(MWL8K_RX_DESCS);
1516
1517 rc = mwl8k_post_cmd(hw, &cmd->header);
1518
1519 if (!rc) {
1520 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1521 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1522 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1523 priv->hw_rev = cmd->hw_rev;
1524 }
1525
1526 kfree(cmd);
1527 return rc;
1528 }
1529
1530 /*
1531 * CMD_MAC_MULTICAST_ADR.
1532 */
1533 struct mwl8k_cmd_mac_multicast_adr {
1534 struct mwl8k_cmd_pkt header;
1535 __le16 action;
1536 __le16 numaddr;
1537 __u8 addr[0][ETH_ALEN];
1538 };
1539
1540 #define MWL8K_ENABLE_RX_DIRECTED 0x0001
1541 #define MWL8K_ENABLE_RX_MULTICAST 0x0002
1542 #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1543 #define MWL8K_ENABLE_RX_BROADCAST 0x0008
1544
1545 static struct mwl8k_cmd_pkt *
1546 __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
1547 int mc_count, struct dev_addr_list *mclist)
1548 {
1549 struct mwl8k_priv *priv = hw->priv;
1550 struct mwl8k_cmd_mac_multicast_adr *cmd;
1551 int size;
1552
1553 if (allmulti || mc_count > priv->num_mcaddrs) {
1554 allmulti = 1;
1555 mc_count = 0;
1556 }
1557
1558 size = sizeof(*cmd) + mc_count * ETH_ALEN;
1559
1560 cmd = kzalloc(size, GFP_ATOMIC);
1561 if (cmd == NULL)
1562 return NULL;
1563
1564 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1565 cmd->header.length = cpu_to_le16(size);
1566 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1567 MWL8K_ENABLE_RX_BROADCAST);
1568
1569 if (allmulti) {
1570 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1571 } else if (mc_count) {
1572 int i;
1573
1574 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1575 cmd->numaddr = cpu_to_le16(mc_count);
1576 for (i = 0; i < mc_count && mclist; i++) {
1577 if (mclist->da_addrlen != ETH_ALEN) {
1578 kfree(cmd);
1579 return NULL;
1580 }
1581 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1582 mclist = mclist->next;
1583 }
1584 }
1585
1586 return &cmd->header;
1587 }
1588
1589 /*
1590 * CMD_802_11_GET_STAT.
1591 */
1592 struct mwl8k_cmd_802_11_get_stat {
1593 struct mwl8k_cmd_pkt header;
1594 __le32 stats[64];
1595 } __attribute__((packed));
1596
1597 #define MWL8K_STAT_ACK_FAILURE 9
1598 #define MWL8K_STAT_RTS_FAILURE 12
1599 #define MWL8K_STAT_FCS_ERROR 24
1600 #define MWL8K_STAT_RTS_SUCCESS 11
1601
1602 static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1603 struct ieee80211_low_level_stats *stats)
1604 {
1605 struct mwl8k_cmd_802_11_get_stat *cmd;
1606 int rc;
1607
1608 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1609 if (cmd == NULL)
1610 return -ENOMEM;
1611
1612 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1613 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1614
1615 rc = mwl8k_post_cmd(hw, &cmd->header);
1616 if (!rc) {
1617 stats->dot11ACKFailureCount =
1618 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1619 stats->dot11RTSFailureCount =
1620 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1621 stats->dot11FCSErrorCount =
1622 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1623 stats->dot11RTSSuccessCount =
1624 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1625 }
1626 kfree(cmd);
1627
1628 return rc;
1629 }
1630
1631 /*
1632 * CMD_802_11_RADIO_CONTROL.
1633 */
1634 struct mwl8k_cmd_802_11_radio_control {
1635 struct mwl8k_cmd_pkt header;
1636 __le16 action;
1637 __le16 control;
1638 __le16 radio_on;
1639 } __attribute__((packed));
1640
1641 static int
1642 mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
1643 {
1644 struct mwl8k_priv *priv = hw->priv;
1645 struct mwl8k_cmd_802_11_radio_control *cmd;
1646 int rc;
1647
1648 if (enable == priv->radio_on && !force)
1649 return 0;
1650
1651 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1652 if (cmd == NULL)
1653 return -ENOMEM;
1654
1655 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1656 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1657 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1658 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
1659 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1660
1661 rc = mwl8k_post_cmd(hw, &cmd->header);
1662 kfree(cmd);
1663
1664 if (!rc)
1665 priv->radio_on = enable;
1666
1667 return rc;
1668 }
1669
1670 static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1671 {
1672 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1673 }
1674
1675 static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1676 {
1677 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1678 }
1679
1680 static int
1681 mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1682 {
1683 struct mwl8k_priv *priv;
1684
1685 if (hw == NULL || hw->priv == NULL)
1686 return -EINVAL;
1687 priv = hw->priv;
1688
1689 priv->radio_short_preamble = short_preamble;
1690
1691 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
1692 }
1693
1694 /*
1695 * CMD_802_11_RF_TX_POWER.
1696 */
1697 #define MWL8K_TX_POWER_LEVEL_TOTAL 8
1698
1699 struct mwl8k_cmd_802_11_rf_tx_power {
1700 struct mwl8k_cmd_pkt header;
1701 __le16 action;
1702 __le16 support_level;
1703 __le16 current_level;
1704 __le16 reserved;
1705 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1706 } __attribute__((packed));
1707
1708 static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1709 {
1710 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
1711 int rc;
1712
1713 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1714 if (cmd == NULL)
1715 return -ENOMEM;
1716
1717 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1718 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1719 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1720 cmd->support_level = cpu_to_le16(dBm);
1721
1722 rc = mwl8k_post_cmd(hw, &cmd->header);
1723 kfree(cmd);
1724
1725 return rc;
1726 }
1727
1728 /*
1729 * CMD_SET_PRE_SCAN.
1730 */
1731 struct mwl8k_cmd_set_pre_scan {
1732 struct mwl8k_cmd_pkt header;
1733 } __attribute__((packed));
1734
1735 static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
1736 {
1737 struct mwl8k_cmd_set_pre_scan *cmd;
1738 int rc;
1739
1740 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1741 if (cmd == NULL)
1742 return -ENOMEM;
1743
1744 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
1745 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1746
1747 rc = mwl8k_post_cmd(hw, &cmd->header);
1748 kfree(cmd);
1749
1750 return rc;
1751 }
1752
1753 /*
1754 * CMD_SET_POST_SCAN.
1755 */
1756 struct mwl8k_cmd_set_post_scan {
1757 struct mwl8k_cmd_pkt header;
1758 __le32 isibss;
1759 __u8 bssid[ETH_ALEN];
1760 } __attribute__((packed));
1761
1762 static int
1763 mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
1764 {
1765 struct mwl8k_cmd_set_post_scan *cmd;
1766 int rc;
1767
1768 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1769 if (cmd == NULL)
1770 return -ENOMEM;
1771
1772 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
1773 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1774 cmd->isibss = 0;
1775 memcpy(cmd->bssid, mac, ETH_ALEN);
1776
1777 rc = mwl8k_post_cmd(hw, &cmd->header);
1778 kfree(cmd);
1779
1780 return rc;
1781 }
1782
1783 /*
1784 * CMD_SET_RF_CHANNEL.
1785 */
1786 struct mwl8k_cmd_set_rf_channel {
1787 struct mwl8k_cmd_pkt header;
1788 __le16 action;
1789 __u8 current_channel;
1790 __le32 channel_flags;
1791 } __attribute__((packed));
1792
1793 static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
1794 struct ieee80211_channel *channel)
1795 {
1796 struct mwl8k_cmd_set_rf_channel *cmd;
1797 int rc;
1798
1799 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1800 if (cmd == NULL)
1801 return -ENOMEM;
1802
1803 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
1804 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1805 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1806 cmd->current_channel = channel->hw_value;
1807 if (channel->band == IEEE80211_BAND_2GHZ)
1808 cmd->channel_flags = cpu_to_le32(0x00000081);
1809 else
1810 cmd->channel_flags = cpu_to_le32(0x00000000);
1811
1812 rc = mwl8k_post_cmd(hw, &cmd->header);
1813 kfree(cmd);
1814
1815 return rc;
1816 }
1817
1818 /*
1819 * CMD_SET_SLOT.
1820 */
1821 struct mwl8k_cmd_set_slot {
1822 struct mwl8k_cmd_pkt header;
1823 __le16 action;
1824 __u8 short_slot;
1825 } __attribute__((packed));
1826
1827 static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
1828 {
1829 struct mwl8k_cmd_set_slot *cmd;
1830 int rc;
1831
1832 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1833 if (cmd == NULL)
1834 return -ENOMEM;
1835
1836 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
1837 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1838 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1839 cmd->short_slot = short_slot_time;
1840
1841 rc = mwl8k_post_cmd(hw, &cmd->header);
1842 kfree(cmd);
1843
1844 return rc;
1845 }
1846
1847 /*
1848 * CMD_MIMO_CONFIG.
1849 */
1850 struct mwl8k_cmd_mimo_config {
1851 struct mwl8k_cmd_pkt header;
1852 __le32 action;
1853 __u8 rx_antenna_map;
1854 __u8 tx_antenna_map;
1855 } __attribute__((packed));
1856
1857 static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
1858 {
1859 struct mwl8k_cmd_mimo_config *cmd;
1860 int rc;
1861
1862 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1863 if (cmd == NULL)
1864 return -ENOMEM;
1865
1866 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
1867 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1868 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
1869 cmd->rx_antenna_map = rx;
1870 cmd->tx_antenna_map = tx;
1871
1872 rc = mwl8k_post_cmd(hw, &cmd->header);
1873 kfree(cmd);
1874
1875 return rc;
1876 }
1877
1878 /*
1879 * CMD_ENABLE_SNIFFER.
1880 */
1881 struct mwl8k_cmd_enable_sniffer {
1882 struct mwl8k_cmd_pkt header;
1883 __le32 action;
1884 } __attribute__((packed));
1885
1886 static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
1887 {
1888 struct mwl8k_cmd_enable_sniffer *cmd;
1889 int rc;
1890
1891 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1892 if (cmd == NULL)
1893 return -ENOMEM;
1894
1895 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
1896 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1897 cmd->action = cpu_to_le32(!!enable);
1898
1899 rc = mwl8k_post_cmd(hw, &cmd->header);
1900 kfree(cmd);
1901
1902 return rc;
1903 }
1904
1905 /*
1906 * CMD_SET_RATEADAPT_MODE.
1907 */
1908 struct mwl8k_cmd_set_rate_adapt_mode {
1909 struct mwl8k_cmd_pkt header;
1910 __le16 action;
1911 __le16 mode;
1912 } __attribute__((packed));
1913
1914 static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
1915 {
1916 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
1917 int rc;
1918
1919 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1920 if (cmd == NULL)
1921 return -ENOMEM;
1922
1923 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
1924 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1925 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1926 cmd->mode = cpu_to_le16(mode);
1927
1928 rc = mwl8k_post_cmd(hw, &cmd->header);
1929 kfree(cmd);
1930
1931 return rc;
1932 }
1933
1934 /*
1935 * CMD_SET_WMM_MODE.
1936 */
1937 struct mwl8k_cmd_set_wmm {
1938 struct mwl8k_cmd_pkt header;
1939 __le16 action;
1940 } __attribute__((packed));
1941
1942 static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
1943 {
1944 struct mwl8k_priv *priv = hw->priv;
1945 struct mwl8k_cmd_set_wmm *cmd;
1946 int rc;
1947
1948 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1949 if (cmd == NULL)
1950 return -ENOMEM;
1951
1952 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
1953 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1954 cmd->action = cpu_to_le16(!!enable);
1955
1956 rc = mwl8k_post_cmd(hw, &cmd->header);
1957 kfree(cmd);
1958
1959 if (!rc)
1960 priv->wmm_enabled = enable;
1961
1962 return rc;
1963 }
1964
1965 /*
1966 * CMD_SET_RTS_THRESHOLD.
1967 */
1968 struct mwl8k_cmd_rts_threshold {
1969 struct mwl8k_cmd_pkt header;
1970 __le16 action;
1971 __le16 threshold;
1972 } __attribute__((packed));
1973
1974 static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
1975 u16 action, u16 threshold)
1976 {
1977 struct mwl8k_cmd_rts_threshold *cmd;
1978 int rc;
1979
1980 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1981 if (cmd == NULL)
1982 return -ENOMEM;
1983
1984 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
1985 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1986 cmd->action = cpu_to_le16(action);
1987 cmd->threshold = cpu_to_le16(threshold);
1988
1989 rc = mwl8k_post_cmd(hw, &cmd->header);
1990 kfree(cmd);
1991
1992 return rc;
1993 }
1994
1995 /*
1996 * CMD_SET_EDCA_PARAMS.
1997 */
1998 struct mwl8k_cmd_set_edca_params {
1999 struct mwl8k_cmd_pkt header;
2000
2001 /* See MWL8K_SET_EDCA_XXX below */
2002 __le16 action;
2003
2004 /* TX opportunity in units of 32 us */
2005 __le16 txop;
2006
2007 /* Log exponent of max contention period: 0...15*/
2008 __u8 log_cw_max;
2009
2010 /* Log exponent of min contention period: 0...15 */
2011 __u8 log_cw_min;
2012
2013 /* Adaptive interframe spacing in units of 32us */
2014 __u8 aifs;
2015
2016 /* TX queue to configure */
2017 __u8 txq;
2018 } __attribute__((packed));
2019
2020 #define MWL8K_SET_EDCA_CW 0x01
2021 #define MWL8K_SET_EDCA_TXOP 0x02
2022 #define MWL8K_SET_EDCA_AIFS 0x04
2023
2024 #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2025 MWL8K_SET_EDCA_TXOP | \
2026 MWL8K_SET_EDCA_AIFS)
2027
2028 static int
2029 mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2030 __u16 cw_min, __u16 cw_max,
2031 __u8 aifs, __u16 txop)
2032 {
2033 struct mwl8k_cmd_set_edca_params *cmd;
2034 int rc;
2035
2036 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2037 if (cmd == NULL)
2038 return -ENOMEM;
2039
2040 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2041 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2042 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2043 cmd->txop = cpu_to_le16(txop);
2044 cmd->log_cw_max = (u8)ilog2(cw_max + 1);
2045 cmd->log_cw_min = (u8)ilog2(cw_min + 1);
2046 cmd->aifs = aifs;
2047 cmd->txq = qnum;
2048
2049 rc = mwl8k_post_cmd(hw, &cmd->header);
2050 kfree(cmd);
2051
2052 return rc;
2053 }
2054
2055 /*
2056 * CMD_FINALIZE_JOIN.
2057 */
2058
2059 /* FJ beacon buffer size is compiled into the firmware. */
2060 #define MWL8K_FJ_BEACON_MAXLEN 128
2061
2062 struct mwl8k_cmd_finalize_join {
2063 struct mwl8k_cmd_pkt header;
2064 __le32 sleep_interval; /* Number of beacon periods to sleep */
2065 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2066 } __attribute__((packed));
2067
2068 static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2069 __u16 framelen, __u16 dtim)
2070 {
2071 struct mwl8k_cmd_finalize_join *cmd;
2072 struct ieee80211_mgmt *payload = frame;
2073 u16 hdrlen;
2074 u32 payload_len;
2075 int rc;
2076
2077 if (frame == NULL)
2078 return -EINVAL;
2079
2080 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2081 if (cmd == NULL)
2082 return -ENOMEM;
2083
2084 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2085 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2086 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2087
2088 hdrlen = ieee80211_hdrlen(payload->frame_control);
2089
2090 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2091
2092 /* XXX TBD Might just have to abort and return an error */
2093 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2094 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
2095 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2096 payload_len, MWL8K_FJ_BEACON_MAXLEN);
2097
2098 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2099 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2100
2101 if (payload && payload_len)
2102 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2103
2104 rc = mwl8k_post_cmd(hw, &cmd->header);
2105 kfree(cmd);
2106 return rc;
2107 }
2108
2109 /*
2110 * CMD_UPDATE_STADB.
2111 */
2112 struct mwl8k_cmd_update_sta_db {
2113 struct mwl8k_cmd_pkt header;
2114
2115 /* See STADB_ACTION_TYPE */
2116 __le32 action;
2117
2118 /* Peer MAC address */
2119 __u8 peer_addr[ETH_ALEN];
2120
2121 __le32 reserved;
2122
2123 /* Peer info - valid during add/update. */
2124 struct peer_capability_info peer_info;
2125 } __attribute__((packed));
2126
2127 static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2128 struct ieee80211_vif *vif, __u32 action)
2129 {
2130 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2131 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2132 struct mwl8k_cmd_update_sta_db *cmd;
2133 struct peer_capability_info *peer_info;
2134 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2135 int rc;
2136 __u8 count, *rates;
2137
2138 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2139 if (cmd == NULL)
2140 return -ENOMEM;
2141
2142 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2143 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2144
2145 cmd->action = cpu_to_le32(action);
2146 peer_info = &cmd->peer_info;
2147 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
2148
2149 switch (action) {
2150 case MWL8K_STA_DB_ADD_ENTRY:
2151 case MWL8K_STA_DB_MODIFY_ENTRY:
2152 /* Build peer_info block */
2153 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2154 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2155 peer_info->interop = 1;
2156 peer_info->amsdu_enabled = 0;
2157
2158 rates = peer_info->legacy_rates;
2159 for (count = 0; count < mv_vif->legacy_nrates; count++)
2160 rates[count] = bitrates[count].hw_value;
2161
2162 rc = mwl8k_post_cmd(hw, &cmd->header);
2163 if (rc == 0)
2164 mv_vif->peer_id = peer_info->station_id;
2165
2166 break;
2167
2168 case MWL8K_STA_DB_DEL_ENTRY:
2169 case MWL8K_STA_DB_FLUSH:
2170 default:
2171 rc = mwl8k_post_cmd(hw, &cmd->header);
2172 if (rc == 0)
2173 mv_vif->peer_id = 0;
2174 break;
2175 }
2176 kfree(cmd);
2177
2178 return rc;
2179 }
2180
2181 /*
2182 * CMD_SET_AID.
2183 */
2184 #define MWL8K_RATE_INDEX_MAX_ARRAY 14
2185
2186 #define MWL8K_FRAME_PROT_DISABLED 0x00
2187 #define MWL8K_FRAME_PROT_11G 0x07
2188 #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2189 #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
2190
2191 struct mwl8k_cmd_update_set_aid {
2192 struct mwl8k_cmd_pkt header;
2193 __le16 aid;
2194
2195 /* AP's MAC address (BSSID) */
2196 __u8 bssid[ETH_ALEN];
2197 __le16 protection_mode;
2198 __u8 supp_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2199 } __attribute__((packed));
2200
2201 static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2202 struct ieee80211_vif *vif)
2203 {
2204 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2205 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2206 struct mwl8k_cmd_update_set_aid *cmd;
2207 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2208 int count;
2209 u16 prot_mode;
2210 int rc;
2211
2212 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2213 if (cmd == NULL)
2214 return -ENOMEM;
2215
2216 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2217 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2218 cmd->aid = cpu_to_le16(info->aid);
2219
2220 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
2221
2222 if (info->use_cts_prot) {
2223 prot_mode = MWL8K_FRAME_PROT_11G;
2224 } else {
2225 switch (info->ht_operation_mode &
2226 IEEE80211_HT_OP_MODE_PROTECTION) {
2227 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2228 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2229 break;
2230 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2231 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2232 break;
2233 default:
2234 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2235 break;
2236 }
2237 }
2238 cmd->protection_mode = cpu_to_le16(prot_mode);
2239
2240 for (count = 0; count < mv_vif->legacy_nrates; count++)
2241 cmd->supp_rates[count] = bitrates[count].hw_value;
2242
2243 rc = mwl8k_post_cmd(hw, &cmd->header);
2244 kfree(cmd);
2245
2246 return rc;
2247 }
2248
2249 /*
2250 * CMD_SET_RATE.
2251 */
2252 struct mwl8k_cmd_update_rateset {
2253 struct mwl8k_cmd_pkt header;
2254 __u8 legacy_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2255
2256 /* Bitmap for supported MCS codes. */
2257 __u8 mcs_set[MWL8K_IEEE_LEGACY_DATA_RATES];
2258 __u8 reserved[MWL8K_IEEE_LEGACY_DATA_RATES];
2259 } __attribute__((packed));
2260
2261 static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2262 struct ieee80211_vif *vif)
2263 {
2264 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2265 struct mwl8k_cmd_update_rateset *cmd;
2266 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2267 int count;
2268 int rc;
2269
2270 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2271 if (cmd == NULL)
2272 return -ENOMEM;
2273
2274 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2275 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2276
2277 for (count = 0; count < mv_vif->legacy_nrates; count++)
2278 cmd->legacy_rates[count] = bitrates[count].hw_value;
2279
2280 rc = mwl8k_post_cmd(hw, &cmd->header);
2281 kfree(cmd);
2282
2283 return rc;
2284 }
2285
2286 /*
2287 * CMD_USE_FIXED_RATE.
2288 */
2289 #define MWL8K_RATE_TABLE_SIZE 8
2290 #define MWL8K_UCAST_RATE 0
2291 #define MWL8K_USE_AUTO_RATE 0x0002
2292
2293 struct mwl8k_rate_entry {
2294 /* Set to 1 if HT rate, 0 if legacy. */
2295 __le32 is_ht_rate;
2296
2297 /* Set to 1 to use retry_count field. */
2298 __le32 enable_retry;
2299
2300 /* Specified legacy rate or MCS. */
2301 __le32 rate;
2302
2303 /* Number of allowed retries. */
2304 __le32 retry_count;
2305 } __attribute__((packed));
2306
2307 struct mwl8k_rate_table {
2308 /* 1 to allow specified rate and below */
2309 __le32 allow_rate_drop;
2310 __le32 num_rates;
2311 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2312 } __attribute__((packed));
2313
2314 struct mwl8k_cmd_use_fixed_rate {
2315 struct mwl8k_cmd_pkt header;
2316 __le32 action;
2317 struct mwl8k_rate_table rate_table;
2318
2319 /* Unicast, Broadcast or Multicast */
2320 __le32 rate_type;
2321 __le32 reserved1;
2322 __le32 reserved2;
2323 } __attribute__((packed));
2324
2325 static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2326 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2327 {
2328 struct mwl8k_cmd_use_fixed_rate *cmd;
2329 int count;
2330 int rc;
2331
2332 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2333 if (cmd == NULL)
2334 return -ENOMEM;
2335
2336 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2337 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2338
2339 cmd->action = cpu_to_le32(action);
2340 cmd->rate_type = cpu_to_le32(rate_type);
2341
2342 if (rate_table != NULL) {
2343 /*
2344 * Copy over each field manually so that endian
2345 * conversion can be done.
2346 */
2347 cmd->rate_table.allow_rate_drop =
2348 cpu_to_le32(rate_table->allow_rate_drop);
2349 cmd->rate_table.num_rates =
2350 cpu_to_le32(rate_table->num_rates);
2351
2352 for (count = 0; count < rate_table->num_rates; count++) {
2353 struct mwl8k_rate_entry *dst =
2354 &cmd->rate_table.rate_entry[count];
2355 struct mwl8k_rate_entry *src =
2356 &rate_table->rate_entry[count];
2357
2358 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2359 dst->enable_retry = cpu_to_le32(src->enable_retry);
2360 dst->rate = cpu_to_le32(src->rate);
2361 dst->retry_count = cpu_to_le32(src->retry_count);
2362 }
2363 }
2364
2365 rc = mwl8k_post_cmd(hw, &cmd->header);
2366 kfree(cmd);
2367
2368 return rc;
2369 }
2370
2371
2372 /*
2373 * Interrupt handling.
2374 */
2375 static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2376 {
2377 struct ieee80211_hw *hw = dev_id;
2378 struct mwl8k_priv *priv = hw->priv;
2379 u32 status;
2380
2381 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2382 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2383
2384 if (!status)
2385 return IRQ_NONE;
2386
2387 if (status & MWL8K_A2H_INT_TX_DONE)
2388 tasklet_schedule(&priv->tx_reclaim_task);
2389
2390 if (status & MWL8K_A2H_INT_RX_READY) {
2391 while (rxq_process(hw, 0, 1))
2392 rxq_refill(hw, 0, 1);
2393 }
2394
2395 if (status & MWL8K_A2H_INT_OPC_DONE) {
2396 if (priv->hostcmd_wait != NULL)
2397 complete(priv->hostcmd_wait);
2398 }
2399
2400 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
2401 if (!mutex_is_locked(&priv->fw_mutex) &&
2402 priv->radio_on && priv->pending_tx_pkts)
2403 mwl8k_tx_start(priv);
2404 }
2405
2406 return IRQ_HANDLED;
2407 }
2408
2409
2410 /*
2411 * Core driver operations.
2412 */
2413 static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2414 {
2415 struct mwl8k_priv *priv = hw->priv;
2416 int index = skb_get_queue_mapping(skb);
2417 int rc;
2418
2419 if (priv->current_channel == NULL) {
2420 printk(KERN_DEBUG "%s: dropped TX frame since radio "
2421 "disabled\n", wiphy_name(hw->wiphy));
2422 dev_kfree_skb(skb);
2423 return NETDEV_TX_OK;
2424 }
2425
2426 rc = mwl8k_txq_xmit(hw, index, skb);
2427
2428 return rc;
2429 }
2430
2431 static int mwl8k_start(struct ieee80211_hw *hw)
2432 {
2433 struct mwl8k_priv *priv = hw->priv;
2434 int rc;
2435
2436 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
2437 IRQF_SHARED, MWL8K_NAME, hw);
2438 if (rc) {
2439 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2440 wiphy_name(hw->wiphy));
2441 return -EIO;
2442 }
2443
2444 /* Enable tx reclaim tasklet */
2445 tasklet_enable(&priv->tx_reclaim_task);
2446
2447 /* Enable interrupts */
2448 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2449
2450 rc = mwl8k_fw_lock(hw);
2451 if (!rc) {
2452 rc = mwl8k_cmd_802_11_radio_enable(hw);
2453
2454 if (!rc)
2455 rc = mwl8k_cmd_set_pre_scan(hw);
2456
2457 if (!rc)
2458 rc = mwl8k_cmd_set_post_scan(hw,
2459 "\x00\x00\x00\x00\x00\x00");
2460
2461 if (!rc)
2462 rc = mwl8k_cmd_setrateadaptmode(hw, 0);
2463
2464 if (!rc)
2465 rc = mwl8k_set_wmm(hw, 0);
2466
2467 if (!rc)
2468 rc = mwl8k_enable_sniffer(hw, 0);
2469
2470 mwl8k_fw_unlock(hw);
2471 }
2472
2473 if (rc) {
2474 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2475 free_irq(priv->pdev->irq, hw);
2476 tasklet_disable(&priv->tx_reclaim_task);
2477 }
2478
2479 return rc;
2480 }
2481
2482 static void mwl8k_stop(struct ieee80211_hw *hw)
2483 {
2484 struct mwl8k_priv *priv = hw->priv;
2485 int i;
2486
2487 mwl8k_cmd_802_11_radio_disable(hw);
2488
2489 ieee80211_stop_queues(hw);
2490
2491 /* Disable interrupts */
2492 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2493 free_irq(priv->pdev->irq, hw);
2494
2495 /* Stop finalize join worker */
2496 cancel_work_sync(&priv->finalize_join_worker);
2497 if (priv->beacon_skb != NULL)
2498 dev_kfree_skb(priv->beacon_skb);
2499
2500 /* Stop tx reclaim tasklet */
2501 tasklet_disable(&priv->tx_reclaim_task);
2502
2503 /* Return all skbs to mac80211 */
2504 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2505 mwl8k_txq_reclaim(hw, i, 1);
2506 }
2507
2508 static int mwl8k_add_interface(struct ieee80211_hw *hw,
2509 struct ieee80211_if_init_conf *conf)
2510 {
2511 struct mwl8k_priv *priv = hw->priv;
2512 struct mwl8k_vif *mwl8k_vif;
2513
2514 /*
2515 * We only support one active interface at a time.
2516 */
2517 if (priv->vif != NULL)
2518 return -EBUSY;
2519
2520 /*
2521 * We only support managed interfaces for now.
2522 */
2523 if (conf->type != NL80211_IFTYPE_STATION)
2524 return -EINVAL;
2525
2526 /* Clean out driver private area */
2527 mwl8k_vif = MWL8K_VIF(conf->vif);
2528 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2529
2530 /* Save the mac address */
2531 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
2532
2533 /* Back pointer to parent config block */
2534 mwl8k_vif->priv = priv;
2535
2536 /* Setup initial PHY parameters */
2537 memcpy(mwl8k_vif->legacy_rates,
2538 priv->rates, sizeof(mwl8k_vif->legacy_rates));
2539 mwl8k_vif->legacy_nrates = ARRAY_SIZE(priv->rates);
2540
2541 /* Set Initial sequence number to zero */
2542 mwl8k_vif->seqno = 0;
2543
2544 priv->vif = conf->vif;
2545 priv->current_channel = NULL;
2546
2547 return 0;
2548 }
2549
2550 static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2551 struct ieee80211_if_init_conf *conf)
2552 {
2553 struct mwl8k_priv *priv = hw->priv;
2554
2555 if (priv->vif == NULL)
2556 return;
2557
2558 priv->vif = NULL;
2559 }
2560
2561 static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
2562 {
2563 struct ieee80211_conf *conf = &hw->conf;
2564 struct mwl8k_priv *priv = hw->priv;
2565 int rc;
2566
2567 if (conf->flags & IEEE80211_CONF_IDLE) {
2568 mwl8k_cmd_802_11_radio_disable(hw);
2569 priv->current_channel = NULL;
2570 return 0;
2571 }
2572
2573 rc = mwl8k_fw_lock(hw);
2574 if (rc)
2575 return rc;
2576
2577 rc = mwl8k_cmd_802_11_radio_enable(hw);
2578 if (rc)
2579 goto out;
2580
2581 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2582 if (rc)
2583 goto out;
2584
2585 priv->current_channel = conf->channel;
2586
2587 if (conf->power_level > 18)
2588 conf->power_level = 18;
2589 rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level);
2590 if (rc)
2591 goto out;
2592
2593 if (mwl8k_cmd_mimo_config(hw, 0x7, 0x7))
2594 rc = -EINVAL;
2595
2596 out:
2597 mwl8k_fw_unlock(hw);
2598
2599 return rc;
2600 }
2601
2602 static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
2603 struct ieee80211_vif *vif,
2604 struct ieee80211_bss_conf *info,
2605 u32 changed)
2606 {
2607 struct mwl8k_priv *priv = hw->priv;
2608 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
2609 int rc;
2610
2611 if (changed & BSS_CHANGED_BSSID)
2612 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
2613
2614 if ((changed & BSS_CHANGED_ASSOC) == 0)
2615 return;
2616
2617 priv->capture_beacon = false;
2618
2619 rc = mwl8k_fw_lock(hw);
2620 if (rc)
2621 return;
2622
2623 if (info->assoc) {
2624 memcpy(&mwl8k_vif->bss_info, info,
2625 sizeof(struct ieee80211_bss_conf));
2626
2627 /* Install rates */
2628 rc = mwl8k_update_rateset(hw, vif);
2629 if (rc)
2630 goto out;
2631
2632 /* Turn on rate adaptation */
2633 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
2634 MWL8K_UCAST_RATE, NULL);
2635 if (rc)
2636 goto out;
2637
2638 /* Set radio preamble */
2639 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
2640 if (rc)
2641 goto out;
2642
2643 /* Set slot time */
2644 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
2645 if (rc)
2646 goto out;
2647
2648 /* Update peer rate info */
2649 rc = mwl8k_cmd_update_sta_db(hw, vif,
2650 MWL8K_STA_DB_MODIFY_ENTRY);
2651 if (rc)
2652 goto out;
2653
2654 /* Set AID */
2655 rc = mwl8k_cmd_set_aid(hw, vif);
2656 if (rc)
2657 goto out;
2658
2659 /*
2660 * Finalize the join. Tell rx handler to process
2661 * next beacon from our BSSID.
2662 */
2663 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
2664 priv->capture_beacon = true;
2665 } else {
2666 rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
2667 memset(&mwl8k_vif->bss_info, 0,
2668 sizeof(struct ieee80211_bss_conf));
2669 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
2670 }
2671
2672 out:
2673 mwl8k_fw_unlock(hw);
2674 }
2675
2676 static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
2677 int mc_count, struct dev_addr_list *mclist)
2678 {
2679 struct mwl8k_cmd_pkt *cmd;
2680
2681 /*
2682 * Synthesize and return a command packet that programs the
2683 * hardware multicast address filter. At this point we don't
2684 * know whether FIF_ALLMULTI is being requested, but if it is,
2685 * we'll end up throwing this packet away and creating a new
2686 * one in mwl8k_configure_filter().
2687 */
2688 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
2689
2690 return (unsigned long)cmd;
2691 }
2692
2693 static void mwl8k_configure_filter(struct ieee80211_hw *hw,
2694 unsigned int changed_flags,
2695 unsigned int *total_flags,
2696 u64 multicast)
2697 {
2698 struct mwl8k_priv *priv = hw->priv;
2699 struct mwl8k_cmd_pkt *cmd;
2700
2701 /* Clear unsupported feature flags */
2702 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
2703
2704 if (mwl8k_fw_lock(hw))
2705 return;
2706
2707 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2708 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
2709 /*
2710 * Disable the BSS filter.
2711 */
2712 mwl8k_cmd_set_pre_scan(hw);
2713 } else {
2714 u8 *bssid;
2715
2716 /*
2717 * Enable the BSS filter.
2718 *
2719 * If there is an active STA interface, use that
2720 * interface's BSSID, otherwise use a dummy one
2721 * (where the OUI part needs to be nonzero for
2722 * the BSSID to be accepted by POST_SCAN).
2723 */
2724 bssid = "\x01\x00\x00\x00\x00\x00";
2725 if (priv->vif != NULL)
2726 bssid = MWL8K_VIF(priv->vif)->bssid;
2727
2728 mwl8k_cmd_set_post_scan(hw, bssid);
2729 }
2730 }
2731
2732 cmd = (void *)(unsigned long)multicast;
2733
2734 /*
2735 * If FIF_ALLMULTI is being requested, throw away the command
2736 * packet that ->prepare_multicast() built and replace it with
2737 * a command packet that enables reception of all multicast
2738 * packets.
2739 */
2740 if (*total_flags & FIF_ALLMULTI) {
2741 kfree(cmd);
2742 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
2743 }
2744
2745 if (cmd != NULL) {
2746 mwl8k_post_cmd(hw, cmd);
2747 kfree(cmd);
2748 }
2749
2750 mwl8k_fw_unlock(hw);
2751 }
2752
2753 static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2754 {
2755 return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value);
2756 }
2757
2758 static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2759 const struct ieee80211_tx_queue_params *params)
2760 {
2761 struct mwl8k_priv *priv = hw->priv;
2762 int rc;
2763
2764 rc = mwl8k_fw_lock(hw);
2765 if (!rc) {
2766 if (!priv->wmm_enabled)
2767 rc = mwl8k_set_wmm(hw, 1);
2768
2769 if (!rc)
2770 rc = mwl8k_set_edca_params(hw, queue,
2771 params->cw_min,
2772 params->cw_max,
2773 params->aifs,
2774 params->txop);
2775
2776 mwl8k_fw_unlock(hw);
2777 }
2778
2779 return rc;
2780 }
2781
2782 static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
2783 struct ieee80211_tx_queue_stats *stats)
2784 {
2785 struct mwl8k_priv *priv = hw->priv;
2786 struct mwl8k_tx_queue *txq;
2787 int index;
2788
2789 spin_lock_bh(&priv->tx_lock);
2790 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
2791 txq = priv->txq + index;
2792 memcpy(&stats[index], &txq->tx_stats,
2793 sizeof(struct ieee80211_tx_queue_stats));
2794 }
2795 spin_unlock_bh(&priv->tx_lock);
2796
2797 return 0;
2798 }
2799
2800 static int mwl8k_get_stats(struct ieee80211_hw *hw,
2801 struct ieee80211_low_level_stats *stats)
2802 {
2803 return mwl8k_cmd_802_11_get_stat(hw, stats);
2804 }
2805
2806 static const struct ieee80211_ops mwl8k_ops = {
2807 .tx = mwl8k_tx,
2808 .start = mwl8k_start,
2809 .stop = mwl8k_stop,
2810 .add_interface = mwl8k_add_interface,
2811 .remove_interface = mwl8k_remove_interface,
2812 .config = mwl8k_config,
2813 .bss_info_changed = mwl8k_bss_info_changed,
2814 .prepare_multicast = mwl8k_prepare_multicast,
2815 .configure_filter = mwl8k_configure_filter,
2816 .set_rts_threshold = mwl8k_set_rts_threshold,
2817 .conf_tx = mwl8k_conf_tx,
2818 .get_tx_stats = mwl8k_get_tx_stats,
2819 .get_stats = mwl8k_get_stats,
2820 };
2821
2822 static void mwl8k_tx_reclaim_handler(unsigned long data)
2823 {
2824 int i;
2825 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
2826 struct mwl8k_priv *priv = hw->priv;
2827
2828 spin_lock_bh(&priv->tx_lock);
2829 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2830 mwl8k_txq_reclaim(hw, i, 0);
2831
2832 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
2833 complete(priv->tx_wait);
2834 priv->tx_wait = NULL;
2835 }
2836 spin_unlock_bh(&priv->tx_lock);
2837 }
2838
2839 static void mwl8k_finalize_join_worker(struct work_struct *work)
2840 {
2841 struct mwl8k_priv *priv =
2842 container_of(work, struct mwl8k_priv, finalize_join_worker);
2843 struct sk_buff *skb = priv->beacon_skb;
2844 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
2845
2846 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
2847 dev_kfree_skb(skb);
2848
2849 priv->beacon_skb = NULL;
2850 }
2851
2852 static int __devinit mwl8k_probe(struct pci_dev *pdev,
2853 const struct pci_device_id *id)
2854 {
2855 static int printed_version = 0;
2856 struct ieee80211_hw *hw;
2857 struct mwl8k_priv *priv;
2858 int rc;
2859 int i;
2860
2861 if (!printed_version) {
2862 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
2863 printed_version = 1;
2864 }
2865
2866 rc = pci_enable_device(pdev);
2867 if (rc) {
2868 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
2869 MWL8K_NAME);
2870 return rc;
2871 }
2872
2873 rc = pci_request_regions(pdev, MWL8K_NAME);
2874 if (rc) {
2875 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
2876 MWL8K_NAME);
2877 return rc;
2878 }
2879
2880 pci_set_master(pdev);
2881
2882 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
2883 if (hw == NULL) {
2884 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
2885 rc = -ENOMEM;
2886 goto err_free_reg;
2887 }
2888
2889 priv = hw->priv;
2890 priv->hw = hw;
2891 priv->pdev = pdev;
2892 priv->wmm_enabled = false;
2893 priv->pending_tx_pkts = 0;
2894
2895 SET_IEEE80211_DEV(hw, &pdev->dev);
2896 pci_set_drvdata(pdev, hw);
2897
2898 priv->regs = pci_iomap(pdev, 1, 0x10000);
2899 if (priv->regs == NULL) {
2900 printk(KERN_ERR "%s: Cannot map device memory\n",
2901 wiphy_name(hw->wiphy));
2902 goto err_iounmap;
2903 }
2904
2905 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
2906 priv->band.band = IEEE80211_BAND_2GHZ;
2907 priv->band.channels = priv->channels;
2908 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
2909 priv->band.bitrates = priv->rates;
2910 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
2911 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
2912
2913 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
2914 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
2915
2916 /*
2917 * Extra headroom is the size of the required DMA header
2918 * minus the size of the smallest 802.11 frame (CTS frame).
2919 */
2920 hw->extra_tx_headroom =
2921 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
2922
2923 hw->channel_change_time = 10;
2924
2925 hw->queues = MWL8K_TX_QUEUES;
2926
2927 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
2928
2929 /* Set rssi and noise values to dBm */
2930 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
2931 hw->vif_data_size = sizeof(struct mwl8k_vif);
2932 priv->vif = NULL;
2933
2934 /* Set default radio state and preamble */
2935 priv->radio_on = 0;
2936 priv->radio_short_preamble = 0;
2937
2938 /* Finalize join worker */
2939 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
2940
2941 /* TX reclaim tasklet */
2942 tasklet_init(&priv->tx_reclaim_task,
2943 mwl8k_tx_reclaim_handler, (unsigned long)hw);
2944 tasklet_disable(&priv->tx_reclaim_task);
2945
2946 /* Power management cookie */
2947 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
2948 if (priv->cookie == NULL)
2949 goto err_iounmap;
2950
2951 rc = mwl8k_rxq_init(hw, 0);
2952 if (rc)
2953 goto err_iounmap;
2954 rxq_refill(hw, 0, INT_MAX);
2955
2956 mutex_init(&priv->fw_mutex);
2957 priv->fw_mutex_owner = NULL;
2958 priv->fw_mutex_depth = 0;
2959 priv->hostcmd_wait = NULL;
2960
2961 spin_lock_init(&priv->tx_lock);
2962
2963 priv->tx_wait = NULL;
2964
2965 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
2966 rc = mwl8k_txq_init(hw, i);
2967 if (rc)
2968 goto err_free_queues;
2969 }
2970
2971 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2972 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2973 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
2974 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
2975
2976 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
2977 IRQF_SHARED, MWL8K_NAME, hw);
2978 if (rc) {
2979 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2980 wiphy_name(hw->wiphy));
2981 goto err_free_queues;
2982 }
2983
2984 /* Reset firmware and hardware */
2985 mwl8k_hw_reset(priv);
2986
2987 /* Ask userland hotplug daemon for the device firmware */
2988 rc = mwl8k_request_firmware(priv, (u32)id->driver_data);
2989 if (rc) {
2990 printk(KERN_ERR "%s: Firmware files not found\n",
2991 wiphy_name(hw->wiphy));
2992 goto err_free_irq;
2993 }
2994
2995 /* Load firmware into hardware */
2996 rc = mwl8k_load_firmware(hw);
2997 if (rc) {
2998 printk(KERN_ERR "%s: Cannot start firmware\n",
2999 wiphy_name(hw->wiphy));
3000 goto err_stop_firmware;
3001 }
3002
3003 /* Reclaim memory once firmware is successfully loaded */
3004 mwl8k_release_firmware(priv);
3005
3006 /*
3007 * Temporarily enable interrupts. Initial firmware host
3008 * commands use interrupts and avoids polling. Disable
3009 * interrupts when done.
3010 */
3011 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3012
3013 /* Get config data, mac addrs etc */
3014 rc = mwl8k_cmd_get_hw_spec(hw);
3015 if (rc) {
3016 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3017 wiphy_name(hw->wiphy));
3018 goto err_stop_firmware;
3019 }
3020
3021 /* Turn radio off */
3022 rc = mwl8k_cmd_802_11_radio_disable(hw);
3023 if (rc) {
3024 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
3025 goto err_stop_firmware;
3026 }
3027
3028 /* Disable interrupts */
3029 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3030 free_irq(priv->pdev->irq, hw);
3031
3032 rc = ieee80211_register_hw(hw);
3033 if (rc) {
3034 printk(KERN_ERR "%s: Cannot register device\n",
3035 wiphy_name(hw->wiphy));
3036 goto err_stop_firmware;
3037 }
3038
3039 printk(KERN_INFO "%s: 88w%u v%d, %pM, firmware version %u.%u.%u.%u\n",
3040 wiphy_name(hw->wiphy), priv->part_num, priv->hw_rev,
3041 hw->wiphy->perm_addr,
3042 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3043 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
3044
3045 return 0;
3046
3047 err_stop_firmware:
3048 mwl8k_hw_reset(priv);
3049 mwl8k_release_firmware(priv);
3050
3051 err_free_irq:
3052 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3053 free_irq(priv->pdev->irq, hw);
3054
3055 err_free_queues:
3056 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3057 mwl8k_txq_deinit(hw, i);
3058 mwl8k_rxq_deinit(hw, 0);
3059
3060 err_iounmap:
3061 if (priv->cookie != NULL)
3062 pci_free_consistent(priv->pdev, 4,
3063 priv->cookie, priv->cookie_dma);
3064
3065 if (priv->regs != NULL)
3066 pci_iounmap(pdev, priv->regs);
3067
3068 pci_set_drvdata(pdev, NULL);
3069 ieee80211_free_hw(hw);
3070
3071 err_free_reg:
3072 pci_release_regions(pdev);
3073 pci_disable_device(pdev);
3074
3075 return rc;
3076 }
3077
3078 static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
3079 {
3080 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3081 }
3082
3083 static void __devexit mwl8k_remove(struct pci_dev *pdev)
3084 {
3085 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3086 struct mwl8k_priv *priv;
3087 int i;
3088
3089 if (hw == NULL)
3090 return;
3091 priv = hw->priv;
3092
3093 ieee80211_stop_queues(hw);
3094
3095 ieee80211_unregister_hw(hw);
3096
3097 /* Remove tx reclaim tasklet */
3098 tasklet_kill(&priv->tx_reclaim_task);
3099
3100 /* Stop hardware */
3101 mwl8k_hw_reset(priv);
3102
3103 /* Return all skbs to mac80211 */
3104 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3105 mwl8k_txq_reclaim(hw, i, 1);
3106
3107 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3108 mwl8k_txq_deinit(hw, i);
3109
3110 mwl8k_rxq_deinit(hw, 0);
3111
3112 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
3113
3114 pci_iounmap(pdev, priv->regs);
3115 pci_set_drvdata(pdev, NULL);
3116 ieee80211_free_hw(hw);
3117 pci_release_regions(pdev);
3118 pci_disable_device(pdev);
3119 }
3120
3121 static struct pci_driver mwl8k_driver = {
3122 .name = MWL8K_NAME,
3123 .id_table = mwl8k_table,
3124 .probe = mwl8k_probe,
3125 .remove = __devexit_p(mwl8k_remove),
3126 .shutdown = __devexit_p(mwl8k_shutdown),
3127 };
3128
3129 static int __init mwl8k_init(void)
3130 {
3131 return pci_register_driver(&mwl8k_driver);
3132 }
3133
3134 static void __exit mwl8k_exit(void)
3135 {
3136 pci_unregister_driver(&mwl8k_driver);
3137 }
3138
3139 module_init(mwl8k_init);
3140 module_exit(mwl8k_exit);
3141
3142 MODULE_DESCRIPTION(MWL8K_DESC);
3143 MODULE_VERSION(MWL8K_VERSION);
3144 MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3145 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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