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mwl8k: spell out the names of firmware images in the pci driver data
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
1 /*
2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
4 *
5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/sched.h>
16 #include <linux/spinlock.h>
17 #include <linux/list.h>
18 #include <linux/pci.h>
19 #include <linux/delay.h>
20 #include <linux/completion.h>
21 #include <linux/etherdevice.h>
22 #include <net/mac80211.h>
23 #include <linux/moduleparam.h>
24 #include <linux/firmware.h>
25 #include <linux/workqueue.h>
26
27 #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28 #define MWL8K_NAME KBUILD_MODNAME
29 #define MWL8K_VERSION "0.10"
30
31 /* Register definitions */
32 #define MWL8K_HIU_GEN_PTR 0x00000c10
33 #define MWL8K_MODE_STA 0x0000005a
34 #define MWL8K_MODE_AP 0x000000a5
35 #define MWL8K_HIU_INT_CODE 0x00000c14
36 #define MWL8K_FWSTA_READY 0xf0f1f2f4
37 #define MWL8K_FWAP_READY 0xf1f2f4a5
38 #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
39 #define MWL8K_HIU_SCRATCH 0x00000c40
40
41 /* Host->device communications */
42 #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43 #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44 #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45 #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46 #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
47 #define MWL8K_H2A_INT_DUMMY (1 << 20)
48 #define MWL8K_H2A_INT_RESET (1 << 15)
49 #define MWL8K_H2A_INT_DOORBELL (1 << 1)
50 #define MWL8K_H2A_INT_PPA_READY (1 << 0)
51
52 /* Device->host communications */
53 #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54 #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55 #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56 #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57 #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
58 #define MWL8K_A2H_INT_DUMMY (1 << 20)
59 #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60 #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61 #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62 #define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63 #define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64 #define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65 #define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66 #define MWL8K_A2H_INT_RX_READY (1 << 1)
67 #define MWL8K_A2H_INT_TX_DONE (1 << 0)
68
69 #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
79
80 #define MWL8K_RX_QUEUES 1
81 #define MWL8K_TX_QUEUES 4
82
83 struct mwl8k_device_info {
84 char *part_name;
85 char *helper_image;
86 char *fw_image;
87 };
88
89 struct mwl8k_rx_queue {
90 int rxd_count;
91
92 /* hw receives here */
93 int head;
94
95 /* refill descs here */
96 int tail;
97
98 struct mwl8k_rx_desc *rxd;
99 dma_addr_t rxd_dma;
100 struct sk_buff **skb;
101 };
102
103 struct mwl8k_tx_queue {
104 /* hw transmits here */
105 int head;
106
107 /* sw appends here */
108 int tail;
109
110 struct ieee80211_tx_queue_stats stats;
111 struct mwl8k_tx_desc *txd;
112 dma_addr_t txd_dma;
113 struct sk_buff **skb;
114 };
115
116 /* Pointers to the firmware data and meta information about it. */
117 struct mwl8k_firmware {
118 /* Boot helper code */
119 struct firmware *helper;
120
121 /* Microcode */
122 struct firmware *ucode;
123 };
124
125 struct mwl8k_priv {
126 void __iomem *sram;
127 void __iomem *regs;
128 struct ieee80211_hw *hw;
129
130 struct pci_dev *pdev;
131
132 struct mwl8k_device_info *device_info;
133
134 /* firmware files and meta data */
135 struct mwl8k_firmware fw;
136
137 /* firmware access */
138 struct mutex fw_mutex;
139 struct task_struct *fw_mutex_owner;
140 int fw_mutex_depth;
141 struct completion *hostcmd_wait;
142
143 /* lock held over TX and TX reap */
144 spinlock_t tx_lock;
145
146 /* TX quiesce completion, protected by fw_mutex and tx_lock */
147 struct completion *tx_wait;
148
149 struct ieee80211_vif *vif;
150
151 struct ieee80211_channel *current_channel;
152
153 /* power management status cookie from firmware */
154 u32 *cookie;
155 dma_addr_t cookie_dma;
156
157 u16 num_mcaddrs;
158 u8 hw_rev;
159 u32 fw_rev;
160
161 /*
162 * Running count of TX packets in flight, to avoid
163 * iterating over the transmit rings each time.
164 */
165 int pending_tx_pkts;
166
167 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
168 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
169
170 /* PHY parameters */
171 struct ieee80211_supported_band band;
172 struct ieee80211_channel channels[14];
173 struct ieee80211_rate rates[13];
174
175 bool radio_on;
176 bool radio_short_preamble;
177 bool sniffer_enabled;
178 bool wmm_enabled;
179
180 /* XXX need to convert this to handle multiple interfaces */
181 bool capture_beacon;
182 u8 capture_bssid[ETH_ALEN];
183 struct sk_buff *beacon_skb;
184
185 /*
186 * This FJ worker has to be global as it is scheduled from the
187 * RX handler. At this point we don't know which interface it
188 * belongs to until the list of bssids waiting to complete join
189 * is checked.
190 */
191 struct work_struct finalize_join_worker;
192
193 /* Tasklet to reclaim TX descriptors and buffers after tx */
194 struct tasklet_struct tx_reclaim_task;
195 };
196
197 /* Per interface specific private data */
198 struct mwl8k_vif {
199 /* backpointer to parent config block */
200 struct mwl8k_priv *priv;
201
202 /* BSS config of AP or IBSS from mac80211*/
203 struct ieee80211_bss_conf bss_info;
204
205 /* BSSID of AP or IBSS */
206 u8 bssid[ETH_ALEN];
207 u8 mac_addr[ETH_ALEN];
208
209 /*
210 * Subset of supported legacy rates.
211 * Intersection of AP and STA supported rates.
212 */
213 struct ieee80211_rate legacy_rates[13];
214
215 /* number of supported legacy rates */
216 u8 legacy_nrates;
217
218 /* Index into station database.Returned by update_sta_db call */
219 u8 peer_id;
220
221 /* Non AMPDU sequence number assigned by driver */
222 u16 seqno;
223 };
224
225 #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
226
227 static const struct ieee80211_channel mwl8k_channels[] = {
228 { .center_freq = 2412, .hw_value = 1, },
229 { .center_freq = 2417, .hw_value = 2, },
230 { .center_freq = 2422, .hw_value = 3, },
231 { .center_freq = 2427, .hw_value = 4, },
232 { .center_freq = 2432, .hw_value = 5, },
233 { .center_freq = 2437, .hw_value = 6, },
234 { .center_freq = 2442, .hw_value = 7, },
235 { .center_freq = 2447, .hw_value = 8, },
236 { .center_freq = 2452, .hw_value = 9, },
237 { .center_freq = 2457, .hw_value = 10, },
238 { .center_freq = 2462, .hw_value = 11, },
239 };
240
241 static const struct ieee80211_rate mwl8k_rates[] = {
242 { .bitrate = 10, .hw_value = 2, },
243 { .bitrate = 20, .hw_value = 4, },
244 { .bitrate = 55, .hw_value = 11, },
245 { .bitrate = 110, .hw_value = 22, },
246 { .bitrate = 220, .hw_value = 44, },
247 { .bitrate = 60, .hw_value = 12, },
248 { .bitrate = 90, .hw_value = 18, },
249 { .bitrate = 120, .hw_value = 24, },
250 { .bitrate = 180, .hw_value = 36, },
251 { .bitrate = 240, .hw_value = 48, },
252 { .bitrate = 360, .hw_value = 72, },
253 { .bitrate = 480, .hw_value = 96, },
254 { .bitrate = 540, .hw_value = 108, },
255 };
256
257 /* Set or get info from Firmware */
258 #define MWL8K_CMD_SET 0x0001
259 #define MWL8K_CMD_GET 0x0000
260
261 /* Firmware command codes */
262 #define MWL8K_CMD_CODE_DNLD 0x0001
263 #define MWL8K_CMD_GET_HW_SPEC 0x0003
264 #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
265 #define MWL8K_CMD_GET_STAT 0x0014
266 #define MWL8K_CMD_RADIO_CONTROL 0x001c
267 #define MWL8K_CMD_RF_TX_POWER 0x001e
268 #define MWL8K_CMD_SET_PRE_SCAN 0x0107
269 #define MWL8K_CMD_SET_POST_SCAN 0x0108
270 #define MWL8K_CMD_SET_RF_CHANNEL 0x010a
271 #define MWL8K_CMD_SET_AID 0x010d
272 #define MWL8K_CMD_SET_RATE 0x0110
273 #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
274 #define MWL8K_CMD_RTS_THRESHOLD 0x0113
275 #define MWL8K_CMD_SET_SLOT 0x0114
276 #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
277 #define MWL8K_CMD_SET_WMM_MODE 0x0123
278 #define MWL8K_CMD_MIMO_CONFIG 0x0125
279 #define MWL8K_CMD_USE_FIXED_RATE 0x0126
280 #define MWL8K_CMD_ENABLE_SNIFFER 0x0150
281 #define MWL8K_CMD_SET_MAC_ADDR 0x0202
282 #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
283 #define MWL8K_CMD_UPDATE_STADB 0x1123
284
285 static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
286 {
287 #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
288 snprintf(buf, bufsize, "%s", #x);\
289 return buf;\
290 } while (0)
291 switch (cmd & ~0x8000) {
292 MWL8K_CMDNAME(CODE_DNLD);
293 MWL8K_CMDNAME(GET_HW_SPEC);
294 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
295 MWL8K_CMDNAME(GET_STAT);
296 MWL8K_CMDNAME(RADIO_CONTROL);
297 MWL8K_CMDNAME(RF_TX_POWER);
298 MWL8K_CMDNAME(SET_PRE_SCAN);
299 MWL8K_CMDNAME(SET_POST_SCAN);
300 MWL8K_CMDNAME(SET_RF_CHANNEL);
301 MWL8K_CMDNAME(SET_AID);
302 MWL8K_CMDNAME(SET_RATE);
303 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
304 MWL8K_CMDNAME(RTS_THRESHOLD);
305 MWL8K_CMDNAME(SET_SLOT);
306 MWL8K_CMDNAME(SET_EDCA_PARAMS);
307 MWL8K_CMDNAME(SET_WMM_MODE);
308 MWL8K_CMDNAME(MIMO_CONFIG);
309 MWL8K_CMDNAME(USE_FIXED_RATE);
310 MWL8K_CMDNAME(ENABLE_SNIFFER);
311 MWL8K_CMDNAME(SET_MAC_ADDR);
312 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
313 MWL8K_CMDNAME(UPDATE_STADB);
314 default:
315 snprintf(buf, bufsize, "0x%x", cmd);
316 }
317 #undef MWL8K_CMDNAME
318
319 return buf;
320 }
321
322 /* Hardware and firmware reset */
323 static void mwl8k_hw_reset(struct mwl8k_priv *priv)
324 {
325 iowrite32(MWL8K_H2A_INT_RESET,
326 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
327 iowrite32(MWL8K_H2A_INT_RESET,
328 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
329 msleep(20);
330 }
331
332 /* Release fw image */
333 static void mwl8k_release_fw(struct firmware **fw)
334 {
335 if (*fw == NULL)
336 return;
337 release_firmware(*fw);
338 *fw = NULL;
339 }
340
341 static void mwl8k_release_firmware(struct mwl8k_priv *priv)
342 {
343 mwl8k_release_fw(&priv->fw.ucode);
344 mwl8k_release_fw(&priv->fw.helper);
345 }
346
347 /* Request fw image */
348 static int mwl8k_request_fw(struct mwl8k_priv *priv,
349 const char *fname, struct firmware **fw)
350 {
351 /* release current image */
352 if (*fw != NULL)
353 mwl8k_release_fw(fw);
354
355 return request_firmware((const struct firmware **)fw,
356 fname, &priv->pdev->dev);
357 }
358
359 static int mwl8k_request_firmware(struct mwl8k_priv *priv)
360 {
361 struct mwl8k_device_info *di = priv->device_info;
362 int rc;
363
364 if (di->helper_image != NULL) {
365 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw.helper);
366 if (rc) {
367 printk(KERN_ERR "%s: Error requesting helper "
368 "firmware file %s\n", pci_name(priv->pdev),
369 di->helper_image);
370 return rc;
371 }
372 }
373
374 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw.ucode);
375 if (rc) {
376 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
377 pci_name(priv->pdev), di->fw_image);
378 mwl8k_release_fw(&priv->fw.helper);
379 return rc;
380 }
381
382 return 0;
383 }
384
385 struct mwl8k_cmd_pkt {
386 __le16 code;
387 __le16 length;
388 __le16 seq_num;
389 __le16 result;
390 char payload[0];
391 } __attribute__((packed));
392
393 /*
394 * Firmware loading.
395 */
396 static int
397 mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
398 {
399 void __iomem *regs = priv->regs;
400 dma_addr_t dma_addr;
401 int loops;
402
403 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
404 if (pci_dma_mapping_error(priv->pdev, dma_addr))
405 return -ENOMEM;
406
407 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
408 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
409 iowrite32(MWL8K_H2A_INT_DOORBELL,
410 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
411 iowrite32(MWL8K_H2A_INT_DUMMY,
412 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
413
414 loops = 1000;
415 do {
416 u32 int_code;
417
418 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
419 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
420 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
421 break;
422 }
423
424 cond_resched();
425 udelay(1);
426 } while (--loops);
427
428 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
429
430 return loops ? 0 : -ETIMEDOUT;
431 }
432
433 static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
434 const u8 *data, size_t length)
435 {
436 struct mwl8k_cmd_pkt *cmd;
437 int done;
438 int rc = 0;
439
440 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
441 if (cmd == NULL)
442 return -ENOMEM;
443
444 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
445 cmd->seq_num = 0;
446 cmd->result = 0;
447
448 done = 0;
449 while (length) {
450 int block_size = length > 256 ? 256 : length;
451
452 memcpy(cmd->payload, data + done, block_size);
453 cmd->length = cpu_to_le16(block_size);
454
455 rc = mwl8k_send_fw_load_cmd(priv, cmd,
456 sizeof(*cmd) + block_size);
457 if (rc)
458 break;
459
460 done += block_size;
461 length -= block_size;
462 }
463
464 if (!rc) {
465 cmd->length = 0;
466 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
467 }
468
469 kfree(cmd);
470
471 return rc;
472 }
473
474 static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
475 const u8 *data, size_t length)
476 {
477 unsigned char *buffer;
478 int may_continue, rc = 0;
479 u32 done, prev_block_size;
480
481 buffer = kmalloc(1024, GFP_KERNEL);
482 if (buffer == NULL)
483 return -ENOMEM;
484
485 done = 0;
486 prev_block_size = 0;
487 may_continue = 1000;
488 while (may_continue > 0) {
489 u32 block_size;
490
491 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
492 if (block_size & 1) {
493 block_size &= ~1;
494 may_continue--;
495 } else {
496 done += prev_block_size;
497 length -= prev_block_size;
498 }
499
500 if (block_size > 1024 || block_size > length) {
501 rc = -EOVERFLOW;
502 break;
503 }
504
505 if (length == 0) {
506 rc = 0;
507 break;
508 }
509
510 if (block_size == 0) {
511 rc = -EPROTO;
512 may_continue--;
513 udelay(1);
514 continue;
515 }
516
517 prev_block_size = block_size;
518 memcpy(buffer, data + done, block_size);
519
520 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
521 if (rc)
522 break;
523 }
524
525 if (!rc && length != 0)
526 rc = -EREMOTEIO;
527
528 kfree(buffer);
529
530 return rc;
531 }
532
533 static int mwl8k_load_firmware(struct ieee80211_hw *hw)
534 {
535 struct mwl8k_priv *priv = hw->priv;
536 struct firmware *fw = priv->fw.ucode;
537 int rc;
538 int loops;
539
540 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
541 struct firmware *helper = priv->fw.helper;
542
543 if (helper == NULL) {
544 printk(KERN_ERR "%s: helper image needed but none "
545 "given\n", pci_name(priv->pdev));
546 return -EINVAL;
547 }
548
549 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
550 if (rc) {
551 printk(KERN_ERR "%s: unable to load firmware "
552 "helper image\n", pci_name(priv->pdev));
553 return rc;
554 }
555 msleep(1);
556
557 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
558 } else {
559 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
560 }
561
562 if (rc) {
563 printk(KERN_ERR "%s: unable to load firmware image\n",
564 pci_name(priv->pdev));
565 return rc;
566 }
567
568 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
569 msleep(1);
570
571 loops = 200000;
572 do {
573 if (ioread32(priv->regs + MWL8K_HIU_INT_CODE)
574 == MWL8K_FWSTA_READY)
575 break;
576 udelay(1);
577 } while (--loops);
578
579 return loops ? 0 : -ETIMEDOUT;
580 }
581
582
583 /*
584 * Defines shared between transmission and reception.
585 */
586 /* HT control fields for firmware */
587 struct ewc_ht_info {
588 __le16 control1;
589 __le16 control2;
590 __le16 control3;
591 } __attribute__((packed));
592
593 /* Firmware Station database operations */
594 #define MWL8K_STA_DB_ADD_ENTRY 0
595 #define MWL8K_STA_DB_MODIFY_ENTRY 1
596 #define MWL8K_STA_DB_DEL_ENTRY 2
597 #define MWL8K_STA_DB_FLUSH 3
598
599 /* Peer Entry flags - used to define the type of the peer node */
600 #define MWL8K_PEER_TYPE_ACCESSPOINT 2
601
602 #define MWL8K_IEEE_LEGACY_DATA_RATES 13
603 #define MWL8K_MCS_BITMAP_SIZE 16
604
605 struct peer_capability_info {
606 /* Peer type - AP vs. STA. */
607 __u8 peer_type;
608
609 /* Basic 802.11 capabilities from assoc resp. */
610 __le16 basic_caps;
611
612 /* Set if peer supports 802.11n high throughput (HT). */
613 __u8 ht_support;
614
615 /* Valid if HT is supported. */
616 __le16 ht_caps;
617 __u8 extended_ht_caps;
618 struct ewc_ht_info ewc_info;
619
620 /* Legacy rate table. Intersection of our rates and peer rates. */
621 __u8 legacy_rates[MWL8K_IEEE_LEGACY_DATA_RATES];
622
623 /* HT rate table. Intersection of our rates and peer rates. */
624 __u8 ht_rates[MWL8K_MCS_BITMAP_SIZE];
625 __u8 pad[16];
626
627 /* If set, interoperability mode, no proprietary extensions. */
628 __u8 interop;
629 __u8 pad2;
630 __u8 station_id;
631 __le16 amsdu_enabled;
632 } __attribute__((packed));
633
634 /* Inline functions to manipulate QoS field in data descriptor. */
635 static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
636 {
637 u16 val_mask = 1 << 4;
638
639 /* End of Service Period Bit 4 */
640 return qos | val_mask;
641 }
642
643 static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
644 {
645 u16 val_mask = 0x3;
646 u8 shift = 5;
647 u16 qos_mask = ~(val_mask << shift);
648
649 /* Ack Policy Bit 5-6 */
650 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
651 }
652
653 static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
654 {
655 u16 val_mask = 1 << 7;
656
657 /* AMSDU present Bit 7 */
658 return qos | val_mask;
659 }
660
661 static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
662 {
663 u16 val_mask = 0xff;
664 u8 shift = 8;
665 u16 qos_mask = ~(val_mask << shift);
666
667 /* Queue Length Bits 8-15 */
668 return (qos & qos_mask) | ((len & val_mask) << shift);
669 }
670
671 /* DMA header used by firmware and hardware. */
672 struct mwl8k_dma_data {
673 __le16 fwlen;
674 struct ieee80211_hdr wh;
675 } __attribute__((packed));
676
677 /* Routines to add/remove DMA header from skb. */
678 static inline void mwl8k_remove_dma_header(struct sk_buff *skb)
679 {
680 struct mwl8k_dma_data *tr = (struct mwl8k_dma_data *)skb->data;
681 void *dst, *src = &tr->wh;
682 int hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
683 u16 space = sizeof(struct mwl8k_dma_data) - hdrlen;
684
685 dst = (void *)tr + space;
686 if (dst != src) {
687 memmove(dst, src, hdrlen);
688 skb_pull(skb, space);
689 }
690 }
691
692 static inline void mwl8k_add_dma_header(struct sk_buff *skb)
693 {
694 struct ieee80211_hdr *wh;
695 u32 hdrlen, pktlen;
696 struct mwl8k_dma_data *tr;
697
698 wh = (struct ieee80211_hdr *)skb->data;
699 hdrlen = ieee80211_hdrlen(wh->frame_control);
700 pktlen = skb->len;
701
702 /*
703 * Copy up/down the 802.11 header; the firmware requires
704 * we present a 2-byte payload length followed by a
705 * 4-address header (w/o QoS), followed (optionally) by
706 * any WEP/ExtIV header (but only filled in for CCMP).
707 */
708 if (hdrlen != sizeof(struct mwl8k_dma_data))
709 skb_push(skb, sizeof(struct mwl8k_dma_data) - hdrlen);
710
711 tr = (struct mwl8k_dma_data *)skb->data;
712 if (wh != &tr->wh)
713 memmove(&tr->wh, wh, hdrlen);
714
715 /* Clear addr4 */
716 memset(tr->wh.addr4, 0, ETH_ALEN);
717
718 /*
719 * Firmware length is the length of the fully formed "802.11
720 * payload". That is, everything except for the 802.11 header.
721 * This includes all crypto material including the MIC.
722 */
723 tr->fwlen = cpu_to_le16(pktlen - hdrlen);
724 }
725
726
727 /*
728 * Packet reception.
729 */
730 #define MWL8K_RX_CTRL_OWNED_BY_HOST 0x02
731
732 struct mwl8k_rx_desc {
733 __le16 pkt_len;
734 __u8 link_quality;
735 __u8 noise_level;
736 __le32 pkt_phys_addr;
737 __le32 next_rxd_phys_addr;
738 __le16 qos_control;
739 __le16 rate_info;
740 __le32 pad0[4];
741 __u8 rssi;
742 __u8 channel;
743 __le16 pad1;
744 __u8 rx_ctrl;
745 __u8 rx_status;
746 __u8 pad2[2];
747 } __attribute__((packed));
748
749 #define MWL8K_RX_DESCS 256
750 #define MWL8K_RX_MAXSZ 3800
751
752 #define RATE_INFO_SHORTPRE 0x8000
753 #define RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
754 #define RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
755 #define RATE_INFO_40MHZ 0x0004
756 #define RATE_INFO_SHORTGI 0x0002
757 #define RATE_INFO_MCS_FORMAT 0x0001
758
759 static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
760 {
761 struct mwl8k_priv *priv = hw->priv;
762 struct mwl8k_rx_queue *rxq = priv->rxq + index;
763 int size;
764 int i;
765
766 rxq->rxd_count = 0;
767 rxq->head = 0;
768 rxq->tail = 0;
769
770 size = MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc);
771
772 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
773 if (rxq->rxd == NULL) {
774 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
775 wiphy_name(hw->wiphy));
776 return -ENOMEM;
777 }
778 memset(rxq->rxd, 0, size);
779
780 rxq->skb = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->skb), GFP_KERNEL);
781 if (rxq->skb == NULL) {
782 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
783 wiphy_name(hw->wiphy));
784 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
785 return -ENOMEM;
786 }
787 memset(rxq->skb, 0, MWL8K_RX_DESCS * sizeof(*rxq->skb));
788
789 for (i = 0; i < MWL8K_RX_DESCS; i++) {
790 struct mwl8k_rx_desc *rx_desc;
791 int nexti;
792
793 rx_desc = rxq->rxd + i;
794 nexti = (i + 1) % MWL8K_RX_DESCS;
795
796 rx_desc->next_rxd_phys_addr =
797 cpu_to_le32(rxq->rxd_dma + nexti * sizeof(*rx_desc));
798 rx_desc->rx_ctrl = MWL8K_RX_CTRL_OWNED_BY_HOST;
799 }
800
801 return 0;
802 }
803
804 static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
805 {
806 struct mwl8k_priv *priv = hw->priv;
807 struct mwl8k_rx_queue *rxq = priv->rxq + index;
808 int refilled;
809
810 refilled = 0;
811 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
812 struct sk_buff *skb;
813 int rx;
814
815 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
816 if (skb == NULL)
817 break;
818
819 rxq->rxd_count++;
820
821 rx = rxq->tail;
822 rxq->tail = (rx + 1) % MWL8K_RX_DESCS;
823
824 rxq->rxd[rx].pkt_phys_addr =
825 cpu_to_le32(pci_map_single(priv->pdev, skb->data,
826 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE));
827
828 rxq->rxd[rx].pkt_len = cpu_to_le16(MWL8K_RX_MAXSZ);
829 rxq->skb[rx] = skb;
830 wmb();
831 rxq->rxd[rx].rx_ctrl = 0;
832
833 refilled++;
834 }
835
836 return refilled;
837 }
838
839 /* Must be called only when the card's reception is completely halted */
840 static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
841 {
842 struct mwl8k_priv *priv = hw->priv;
843 struct mwl8k_rx_queue *rxq = priv->rxq + index;
844 int i;
845
846 for (i = 0; i < MWL8K_RX_DESCS; i++) {
847 if (rxq->skb[i] != NULL) {
848 unsigned long addr;
849
850 addr = le32_to_cpu(rxq->rxd[i].pkt_phys_addr);
851 pci_unmap_single(priv->pdev, addr, MWL8K_RX_MAXSZ,
852 PCI_DMA_FROMDEVICE);
853 kfree_skb(rxq->skb[i]);
854 rxq->skb[i] = NULL;
855 }
856 }
857
858 kfree(rxq->skb);
859 rxq->skb = NULL;
860
861 pci_free_consistent(priv->pdev,
862 MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc),
863 rxq->rxd, rxq->rxd_dma);
864 rxq->rxd = NULL;
865 }
866
867
868 /*
869 * Scan a list of BSSIDs to process for finalize join.
870 * Allows for extension to process multiple BSSIDs.
871 */
872 static inline int
873 mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
874 {
875 return priv->capture_beacon &&
876 ieee80211_is_beacon(wh->frame_control) &&
877 !compare_ether_addr(wh->addr3, priv->capture_bssid);
878 }
879
880 static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
881 struct sk_buff *skb)
882 {
883 struct mwl8k_priv *priv = hw->priv;
884
885 priv->capture_beacon = false;
886 memset(priv->capture_bssid, 0, ETH_ALEN);
887
888 /*
889 * Use GFP_ATOMIC as rxq_process is called from
890 * the primary interrupt handler, memory allocation call
891 * must not sleep.
892 */
893 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
894 if (priv->beacon_skb != NULL)
895 ieee80211_queue_work(hw, &priv->finalize_join_worker);
896 }
897
898 static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
899 {
900 struct mwl8k_priv *priv = hw->priv;
901 struct mwl8k_rx_queue *rxq = priv->rxq + index;
902 int processed;
903
904 processed = 0;
905 while (rxq->rxd_count && limit--) {
906 struct mwl8k_rx_desc *rx_desc;
907 struct sk_buff *skb;
908 struct ieee80211_rx_status status;
909 unsigned long addr;
910 struct ieee80211_hdr *wh;
911 u16 rate_info;
912
913 rx_desc = rxq->rxd + rxq->head;
914 if (!(rx_desc->rx_ctrl & MWL8K_RX_CTRL_OWNED_BY_HOST))
915 break;
916 rmb();
917
918 skb = rxq->skb[rxq->head];
919 if (skb == NULL)
920 break;
921 rxq->skb[rxq->head] = NULL;
922
923 rxq->head = (rxq->head + 1) % MWL8K_RX_DESCS;
924 rxq->rxd_count--;
925
926 addr = le32_to_cpu(rx_desc->pkt_phys_addr);
927 pci_unmap_single(priv->pdev, addr,
928 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
929
930 skb_put(skb, le16_to_cpu(rx_desc->pkt_len));
931 mwl8k_remove_dma_header(skb);
932
933 wh = (struct ieee80211_hdr *)skb->data;
934
935 /*
936 * Check for a pending join operation. Save a
937 * copy of the beacon and schedule a tasklet to
938 * send a FINALIZE_JOIN command to the firmware.
939 */
940 if (mwl8k_capture_bssid(priv, wh))
941 mwl8k_save_beacon(hw, skb);
942
943 rate_info = le16_to_cpu(rx_desc->rate_info);
944
945 memset(&status, 0, sizeof(status));
946 status.mactime = 0;
947 status.signal = -rx_desc->rssi;
948 status.noise = -rx_desc->noise_level;
949 status.qual = rx_desc->link_quality;
950 status.antenna = RATE_INFO_ANTSELECT(rate_info);
951 status.rate_idx = RATE_INFO_RATEID(rate_info);
952 status.flag = 0;
953 if (rate_info & RATE_INFO_SHORTPRE)
954 status.flag |= RX_FLAG_SHORTPRE;
955 if (rate_info & RATE_INFO_40MHZ)
956 status.flag |= RX_FLAG_40MHZ;
957 if (rate_info & RATE_INFO_SHORTGI)
958 status.flag |= RX_FLAG_SHORT_GI;
959 if (rate_info & RATE_INFO_MCS_FORMAT)
960 status.flag |= RX_FLAG_HT;
961 status.band = IEEE80211_BAND_2GHZ;
962 status.freq = ieee80211_channel_to_frequency(rx_desc->channel);
963 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
964 ieee80211_rx_irqsafe(hw, skb);
965
966 processed++;
967 }
968
969 return processed;
970 }
971
972
973 /*
974 * Packet transmission.
975 */
976
977 /* Transmit packet ACK policy */
978 #define MWL8K_TXD_ACK_POLICY_NORMAL 0
979 #define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
980
981 #define MWL8K_TXD_STATUS_OK 0x00000001
982 #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
983 #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
984 #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
985 #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
986
987 struct mwl8k_tx_desc {
988 __le32 status;
989 __u8 data_rate;
990 __u8 tx_priority;
991 __le16 qos_control;
992 __le32 pkt_phys_addr;
993 __le16 pkt_len;
994 __u8 dest_MAC_addr[ETH_ALEN];
995 __le32 next_txd_phys_addr;
996 __le32 reserved;
997 __le16 rate_info;
998 __u8 peer_id;
999 __u8 tx_frag_cnt;
1000 } __attribute__((packed));
1001
1002 #define MWL8K_TX_DESCS 128
1003
1004 static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1005 {
1006 struct mwl8k_priv *priv = hw->priv;
1007 struct mwl8k_tx_queue *txq = priv->txq + index;
1008 int size;
1009 int i;
1010
1011 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1012 txq->stats.limit = MWL8K_TX_DESCS;
1013 txq->head = 0;
1014 txq->tail = 0;
1015
1016 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1017
1018 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1019 if (txq->txd == NULL) {
1020 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
1021 wiphy_name(hw->wiphy));
1022 return -ENOMEM;
1023 }
1024 memset(txq->txd, 0, size);
1025
1026 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1027 if (txq->skb == NULL) {
1028 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
1029 wiphy_name(hw->wiphy));
1030 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
1031 return -ENOMEM;
1032 }
1033 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
1034
1035 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1036 struct mwl8k_tx_desc *tx_desc;
1037 int nexti;
1038
1039 tx_desc = txq->txd + i;
1040 nexti = (i + 1) % MWL8K_TX_DESCS;
1041
1042 tx_desc->status = 0;
1043 tx_desc->next_txd_phys_addr =
1044 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
1045 }
1046
1047 return 0;
1048 }
1049
1050 static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1051 {
1052 iowrite32(MWL8K_H2A_INT_PPA_READY,
1053 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1054 iowrite32(MWL8K_H2A_INT_DUMMY,
1055 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1056 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1057 }
1058
1059 struct mwl8k_txq_info {
1060 u32 fw_owned;
1061 u32 drv_owned;
1062 u32 unused;
1063 u32 len;
1064 u32 head;
1065 u32 tail;
1066 };
1067
1068 static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
1069 struct mwl8k_txq_info *txinfo)
1070 {
1071 int count, desc, status;
1072 struct mwl8k_tx_queue *txq;
1073 struct mwl8k_tx_desc *tx_desc;
1074 int ndescs = 0;
1075
1076 memset(txinfo, 0, MWL8K_TX_QUEUES * sizeof(struct mwl8k_txq_info));
1077
1078 for (count = 0; count < MWL8K_TX_QUEUES; count++) {
1079 txq = priv->txq + count;
1080 txinfo[count].len = txq->stats.len;
1081 txinfo[count].head = txq->head;
1082 txinfo[count].tail = txq->tail;
1083 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1084 tx_desc = txq->txd + desc;
1085 status = le32_to_cpu(tx_desc->status);
1086
1087 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1088 txinfo[count].fw_owned++;
1089 else
1090 txinfo[count].drv_owned++;
1091
1092 if (tx_desc->pkt_len == 0)
1093 txinfo[count].unused++;
1094 }
1095 }
1096
1097 return ndescs;
1098 }
1099
1100 /*
1101 * Must be called with priv->fw_mutex held and tx queues stopped.
1102 */
1103 static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
1104 {
1105 struct mwl8k_priv *priv = hw->priv;
1106 DECLARE_COMPLETION_ONSTACK(tx_wait);
1107 u32 count;
1108 unsigned long timeout;
1109
1110 might_sleep();
1111
1112 spin_lock_bh(&priv->tx_lock);
1113 count = priv->pending_tx_pkts;
1114 if (count)
1115 priv->tx_wait = &tx_wait;
1116 spin_unlock_bh(&priv->tx_lock);
1117
1118 if (count) {
1119 struct mwl8k_txq_info txinfo[MWL8K_TX_QUEUES];
1120 int index;
1121 int newcount;
1122
1123 timeout = wait_for_completion_timeout(&tx_wait,
1124 msecs_to_jiffies(5000));
1125 if (timeout)
1126 return 0;
1127
1128 spin_lock_bh(&priv->tx_lock);
1129 priv->tx_wait = NULL;
1130 newcount = priv->pending_tx_pkts;
1131 mwl8k_scan_tx_ring(priv, txinfo);
1132 spin_unlock_bh(&priv->tx_lock);
1133
1134 printk(KERN_ERR "%s(%u) TIMEDOUT:5000ms Pend:%u-->%u\n",
1135 __func__, __LINE__, count, newcount);
1136
1137 for (index = 0; index < MWL8K_TX_QUEUES; index++)
1138 printk(KERN_ERR "TXQ:%u L:%u H:%u T:%u FW:%u "
1139 "DRV:%u U:%u\n",
1140 index,
1141 txinfo[index].len,
1142 txinfo[index].head,
1143 txinfo[index].tail,
1144 txinfo[index].fw_owned,
1145 txinfo[index].drv_owned,
1146 txinfo[index].unused);
1147
1148 return -ETIMEDOUT;
1149 }
1150
1151 return 0;
1152 }
1153
1154 #define MWL8K_TXD_SUCCESS(status) \
1155 ((status) & (MWL8K_TXD_STATUS_OK | \
1156 MWL8K_TXD_STATUS_OK_RETRY | \
1157 MWL8K_TXD_STATUS_OK_MORE_RETRY))
1158
1159 static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1160 {
1161 struct mwl8k_priv *priv = hw->priv;
1162 struct mwl8k_tx_queue *txq = priv->txq + index;
1163 int wake = 0;
1164
1165 while (txq->stats.len > 0) {
1166 int tx;
1167 struct mwl8k_tx_desc *tx_desc;
1168 unsigned long addr;
1169 int size;
1170 struct sk_buff *skb;
1171 struct ieee80211_tx_info *info;
1172 u32 status;
1173
1174 tx = txq->head;
1175 tx_desc = txq->txd + tx;
1176
1177 status = le32_to_cpu(tx_desc->status);
1178
1179 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1180 if (!force)
1181 break;
1182 tx_desc->status &=
1183 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1184 }
1185
1186 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1187 BUG_ON(txq->stats.len == 0);
1188 txq->stats.len--;
1189 priv->pending_tx_pkts--;
1190
1191 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
1192 size = le16_to_cpu(tx_desc->pkt_len);
1193 skb = txq->skb[tx];
1194 txq->skb[tx] = NULL;
1195
1196 BUG_ON(skb == NULL);
1197 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1198
1199 mwl8k_remove_dma_header(skb);
1200
1201 /* Mark descriptor as unused */
1202 tx_desc->pkt_phys_addr = 0;
1203 tx_desc->pkt_len = 0;
1204
1205 info = IEEE80211_SKB_CB(skb);
1206 ieee80211_tx_info_clear_status(info);
1207 if (MWL8K_TXD_SUCCESS(status))
1208 info->flags |= IEEE80211_TX_STAT_ACK;
1209
1210 ieee80211_tx_status_irqsafe(hw, skb);
1211
1212 wake = 1;
1213 }
1214
1215 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
1216 ieee80211_wake_queue(hw, index);
1217 }
1218
1219 /* must be called only when the card's transmit is completely halted */
1220 static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1221 {
1222 struct mwl8k_priv *priv = hw->priv;
1223 struct mwl8k_tx_queue *txq = priv->txq + index;
1224
1225 mwl8k_txq_reclaim(hw, index, 1);
1226
1227 kfree(txq->skb);
1228 txq->skb = NULL;
1229
1230 pci_free_consistent(priv->pdev,
1231 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1232 txq->txd, txq->txd_dma);
1233 txq->txd = NULL;
1234 }
1235
1236 static int
1237 mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1238 {
1239 struct mwl8k_priv *priv = hw->priv;
1240 struct ieee80211_tx_info *tx_info;
1241 struct mwl8k_vif *mwl8k_vif;
1242 struct ieee80211_hdr *wh;
1243 struct mwl8k_tx_queue *txq;
1244 struct mwl8k_tx_desc *tx;
1245 dma_addr_t dma;
1246 u32 txstatus;
1247 u8 txdatarate;
1248 u16 qos;
1249
1250 wh = (struct ieee80211_hdr *)skb->data;
1251 if (ieee80211_is_data_qos(wh->frame_control))
1252 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1253 else
1254 qos = 0;
1255
1256 mwl8k_add_dma_header(skb);
1257 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
1258
1259 tx_info = IEEE80211_SKB_CB(skb);
1260 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
1261
1262 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1263 u16 seqno = mwl8k_vif->seqno;
1264
1265 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1266 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1267 mwl8k_vif->seqno = seqno++ % 4096;
1268 }
1269
1270 /* Setup firmware control bit fields for each frame type. */
1271 txstatus = 0;
1272 txdatarate = 0;
1273 if (ieee80211_is_mgmt(wh->frame_control) ||
1274 ieee80211_is_ctl(wh->frame_control)) {
1275 txdatarate = 0;
1276 qos = mwl8k_qos_setbit_eosp(qos);
1277 /* Set Queue size to unspecified */
1278 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1279 } else if (ieee80211_is_data(wh->frame_control)) {
1280 txdatarate = 1;
1281 if (is_multicast_ether_addr(wh->addr1))
1282 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1283
1284 /* Send pkt in an aggregate if AMPDU frame. */
1285 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1286 qos = mwl8k_qos_setbit_ack(qos,
1287 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1288 else
1289 qos = mwl8k_qos_setbit_ack(qos,
1290 MWL8K_TXD_ACK_POLICY_NORMAL);
1291
1292 if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
1293 qos = mwl8k_qos_setbit_amsdu(qos);
1294 }
1295
1296 dma = pci_map_single(priv->pdev, skb->data,
1297 skb->len, PCI_DMA_TODEVICE);
1298
1299 if (pci_dma_mapping_error(priv->pdev, dma)) {
1300 printk(KERN_DEBUG "%s: failed to dma map skb, "
1301 "dropping TX frame.\n", wiphy_name(hw->wiphy));
1302 dev_kfree_skb(skb);
1303 return NETDEV_TX_OK;
1304 }
1305
1306 spin_lock_bh(&priv->tx_lock);
1307
1308 txq = priv->txq + index;
1309
1310 BUG_ON(txq->skb[txq->tail] != NULL);
1311 txq->skb[txq->tail] = skb;
1312
1313 tx = txq->txd + txq->tail;
1314 tx->data_rate = txdatarate;
1315 tx->tx_priority = index;
1316 tx->qos_control = cpu_to_le16(qos);
1317 tx->pkt_phys_addr = cpu_to_le32(dma);
1318 tx->pkt_len = cpu_to_le16(skb->len);
1319 tx->rate_info = 0;
1320 tx->peer_id = mwl8k_vif->peer_id;
1321 wmb();
1322 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1323
1324 txq->stats.count++;
1325 txq->stats.len++;
1326 priv->pending_tx_pkts++;
1327
1328 txq->tail++;
1329 if (txq->tail == MWL8K_TX_DESCS)
1330 txq->tail = 0;
1331
1332 if (txq->head == txq->tail)
1333 ieee80211_stop_queue(hw, index);
1334
1335 mwl8k_tx_start(priv);
1336
1337 spin_unlock_bh(&priv->tx_lock);
1338
1339 return NETDEV_TX_OK;
1340 }
1341
1342
1343 /*
1344 * Firmware access.
1345 *
1346 * We have the following requirements for issuing firmware commands:
1347 * - Some commands require that the packet transmit path is idle when
1348 * the command is issued. (For simplicity, we'll just quiesce the
1349 * transmit path for every command.)
1350 * - There are certain sequences of commands that need to be issued to
1351 * the hardware sequentially, with no other intervening commands.
1352 *
1353 * This leads to an implementation of a "firmware lock" as a mutex that
1354 * can be taken recursively, and which is taken by both the low-level
1355 * command submission function (mwl8k_post_cmd) as well as any users of
1356 * that function that require issuing of an atomic sequence of commands,
1357 * and quiesces the transmit path whenever it's taken.
1358 */
1359 static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1360 {
1361 struct mwl8k_priv *priv = hw->priv;
1362
1363 if (priv->fw_mutex_owner != current) {
1364 int rc;
1365
1366 mutex_lock(&priv->fw_mutex);
1367 ieee80211_stop_queues(hw);
1368
1369 rc = mwl8k_tx_wait_empty(hw);
1370 if (rc) {
1371 ieee80211_wake_queues(hw);
1372 mutex_unlock(&priv->fw_mutex);
1373
1374 return rc;
1375 }
1376
1377 priv->fw_mutex_owner = current;
1378 }
1379
1380 priv->fw_mutex_depth++;
1381
1382 return 0;
1383 }
1384
1385 static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1386 {
1387 struct mwl8k_priv *priv = hw->priv;
1388
1389 if (!--priv->fw_mutex_depth) {
1390 ieee80211_wake_queues(hw);
1391 priv->fw_mutex_owner = NULL;
1392 mutex_unlock(&priv->fw_mutex);
1393 }
1394 }
1395
1396
1397 /*
1398 * Command processing.
1399 */
1400
1401 /* Timeout firmware commands after 2000ms */
1402 #define MWL8K_CMD_TIMEOUT_MS 2000
1403
1404 static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1405 {
1406 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1407 struct mwl8k_priv *priv = hw->priv;
1408 void __iomem *regs = priv->regs;
1409 dma_addr_t dma_addr;
1410 unsigned int dma_size;
1411 int rc;
1412 unsigned long timeout = 0;
1413 u8 buf[32];
1414
1415 cmd->result = 0xffff;
1416 dma_size = le16_to_cpu(cmd->length);
1417 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1418 PCI_DMA_BIDIRECTIONAL);
1419 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1420 return -ENOMEM;
1421
1422 rc = mwl8k_fw_lock(hw);
1423 if (rc) {
1424 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1425 PCI_DMA_BIDIRECTIONAL);
1426 return rc;
1427 }
1428
1429 priv->hostcmd_wait = &cmd_wait;
1430 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1431 iowrite32(MWL8K_H2A_INT_DOORBELL,
1432 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1433 iowrite32(MWL8K_H2A_INT_DUMMY,
1434 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1435
1436 timeout = wait_for_completion_timeout(&cmd_wait,
1437 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1438
1439 priv->hostcmd_wait = NULL;
1440
1441 mwl8k_fw_unlock(hw);
1442
1443 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1444 PCI_DMA_BIDIRECTIONAL);
1445
1446 if (!timeout) {
1447 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
1448 wiphy_name(hw->wiphy),
1449 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1450 MWL8K_CMD_TIMEOUT_MS);
1451 rc = -ETIMEDOUT;
1452 } else {
1453 rc = cmd->result ? -EINVAL : 0;
1454 if (rc)
1455 printk(KERN_ERR "%s: Command %s error 0x%x\n",
1456 wiphy_name(hw->wiphy),
1457 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1458 le16_to_cpu(cmd->result));
1459 }
1460
1461 return rc;
1462 }
1463
1464 /*
1465 * GET_HW_SPEC.
1466 */
1467 struct mwl8k_cmd_get_hw_spec {
1468 struct mwl8k_cmd_pkt header;
1469 __u8 hw_rev;
1470 __u8 host_interface;
1471 __le16 num_mcaddrs;
1472 __u8 perm_addr[ETH_ALEN];
1473 __le16 region_code;
1474 __le32 fw_rev;
1475 __le32 ps_cookie;
1476 __le32 caps;
1477 __u8 mcs_bitmap[16];
1478 __le32 rx_queue_ptr;
1479 __le32 num_tx_queues;
1480 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1481 __le32 caps2;
1482 __le32 num_tx_desc_per_queue;
1483 __le32 total_rxd;
1484 } __attribute__((packed));
1485
1486 static int mwl8k_cmd_get_hw_spec(struct ieee80211_hw *hw)
1487 {
1488 struct mwl8k_priv *priv = hw->priv;
1489 struct mwl8k_cmd_get_hw_spec *cmd;
1490 int rc;
1491 int i;
1492
1493 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1494 if (cmd == NULL)
1495 return -ENOMEM;
1496
1497 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1498 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1499
1500 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1501 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1502 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1503 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1504 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1505 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1506 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1507 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1508
1509 rc = mwl8k_post_cmd(hw, &cmd->header);
1510
1511 if (!rc) {
1512 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1513 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1514 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1515 priv->hw_rev = cmd->hw_rev;
1516 }
1517
1518 kfree(cmd);
1519 return rc;
1520 }
1521
1522 /*
1523 * CMD_MAC_MULTICAST_ADR.
1524 */
1525 struct mwl8k_cmd_mac_multicast_adr {
1526 struct mwl8k_cmd_pkt header;
1527 __le16 action;
1528 __le16 numaddr;
1529 __u8 addr[0][ETH_ALEN];
1530 };
1531
1532 #define MWL8K_ENABLE_RX_DIRECTED 0x0001
1533 #define MWL8K_ENABLE_RX_MULTICAST 0x0002
1534 #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1535 #define MWL8K_ENABLE_RX_BROADCAST 0x0008
1536
1537 static struct mwl8k_cmd_pkt *
1538 __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
1539 int mc_count, struct dev_addr_list *mclist)
1540 {
1541 struct mwl8k_priv *priv = hw->priv;
1542 struct mwl8k_cmd_mac_multicast_adr *cmd;
1543 int size;
1544
1545 if (allmulti || mc_count > priv->num_mcaddrs) {
1546 allmulti = 1;
1547 mc_count = 0;
1548 }
1549
1550 size = sizeof(*cmd) + mc_count * ETH_ALEN;
1551
1552 cmd = kzalloc(size, GFP_ATOMIC);
1553 if (cmd == NULL)
1554 return NULL;
1555
1556 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1557 cmd->header.length = cpu_to_le16(size);
1558 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1559 MWL8K_ENABLE_RX_BROADCAST);
1560
1561 if (allmulti) {
1562 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1563 } else if (mc_count) {
1564 int i;
1565
1566 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1567 cmd->numaddr = cpu_to_le16(mc_count);
1568 for (i = 0; i < mc_count && mclist; i++) {
1569 if (mclist->da_addrlen != ETH_ALEN) {
1570 kfree(cmd);
1571 return NULL;
1572 }
1573 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1574 mclist = mclist->next;
1575 }
1576 }
1577
1578 return &cmd->header;
1579 }
1580
1581 /*
1582 * CMD_802_11_GET_STAT.
1583 */
1584 struct mwl8k_cmd_802_11_get_stat {
1585 struct mwl8k_cmd_pkt header;
1586 __le32 stats[64];
1587 } __attribute__((packed));
1588
1589 #define MWL8K_STAT_ACK_FAILURE 9
1590 #define MWL8K_STAT_RTS_FAILURE 12
1591 #define MWL8K_STAT_FCS_ERROR 24
1592 #define MWL8K_STAT_RTS_SUCCESS 11
1593
1594 static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1595 struct ieee80211_low_level_stats *stats)
1596 {
1597 struct mwl8k_cmd_802_11_get_stat *cmd;
1598 int rc;
1599
1600 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1601 if (cmd == NULL)
1602 return -ENOMEM;
1603
1604 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1605 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1606
1607 rc = mwl8k_post_cmd(hw, &cmd->header);
1608 if (!rc) {
1609 stats->dot11ACKFailureCount =
1610 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1611 stats->dot11RTSFailureCount =
1612 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1613 stats->dot11FCSErrorCount =
1614 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1615 stats->dot11RTSSuccessCount =
1616 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1617 }
1618 kfree(cmd);
1619
1620 return rc;
1621 }
1622
1623 /*
1624 * CMD_802_11_RADIO_CONTROL.
1625 */
1626 struct mwl8k_cmd_802_11_radio_control {
1627 struct mwl8k_cmd_pkt header;
1628 __le16 action;
1629 __le16 control;
1630 __le16 radio_on;
1631 } __attribute__((packed));
1632
1633 static int
1634 mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
1635 {
1636 struct mwl8k_priv *priv = hw->priv;
1637 struct mwl8k_cmd_802_11_radio_control *cmd;
1638 int rc;
1639
1640 if (enable == priv->radio_on && !force)
1641 return 0;
1642
1643 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1644 if (cmd == NULL)
1645 return -ENOMEM;
1646
1647 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1648 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1649 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1650 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
1651 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1652
1653 rc = mwl8k_post_cmd(hw, &cmd->header);
1654 kfree(cmd);
1655
1656 if (!rc)
1657 priv->radio_on = enable;
1658
1659 return rc;
1660 }
1661
1662 static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1663 {
1664 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1665 }
1666
1667 static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1668 {
1669 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1670 }
1671
1672 static int
1673 mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1674 {
1675 struct mwl8k_priv *priv;
1676
1677 if (hw == NULL || hw->priv == NULL)
1678 return -EINVAL;
1679 priv = hw->priv;
1680
1681 priv->radio_short_preamble = short_preamble;
1682
1683 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
1684 }
1685
1686 /*
1687 * CMD_802_11_RF_TX_POWER.
1688 */
1689 #define MWL8K_TX_POWER_LEVEL_TOTAL 8
1690
1691 struct mwl8k_cmd_802_11_rf_tx_power {
1692 struct mwl8k_cmd_pkt header;
1693 __le16 action;
1694 __le16 support_level;
1695 __le16 current_level;
1696 __le16 reserved;
1697 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1698 } __attribute__((packed));
1699
1700 static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1701 {
1702 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
1703 int rc;
1704
1705 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1706 if (cmd == NULL)
1707 return -ENOMEM;
1708
1709 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1710 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1711 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1712 cmd->support_level = cpu_to_le16(dBm);
1713
1714 rc = mwl8k_post_cmd(hw, &cmd->header);
1715 kfree(cmd);
1716
1717 return rc;
1718 }
1719
1720 /*
1721 * CMD_SET_PRE_SCAN.
1722 */
1723 struct mwl8k_cmd_set_pre_scan {
1724 struct mwl8k_cmd_pkt header;
1725 } __attribute__((packed));
1726
1727 static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
1728 {
1729 struct mwl8k_cmd_set_pre_scan *cmd;
1730 int rc;
1731
1732 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1733 if (cmd == NULL)
1734 return -ENOMEM;
1735
1736 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
1737 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1738
1739 rc = mwl8k_post_cmd(hw, &cmd->header);
1740 kfree(cmd);
1741
1742 return rc;
1743 }
1744
1745 /*
1746 * CMD_SET_POST_SCAN.
1747 */
1748 struct mwl8k_cmd_set_post_scan {
1749 struct mwl8k_cmd_pkt header;
1750 __le32 isibss;
1751 __u8 bssid[ETH_ALEN];
1752 } __attribute__((packed));
1753
1754 static int
1755 mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
1756 {
1757 struct mwl8k_cmd_set_post_scan *cmd;
1758 int rc;
1759
1760 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1761 if (cmd == NULL)
1762 return -ENOMEM;
1763
1764 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
1765 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1766 cmd->isibss = 0;
1767 memcpy(cmd->bssid, mac, ETH_ALEN);
1768
1769 rc = mwl8k_post_cmd(hw, &cmd->header);
1770 kfree(cmd);
1771
1772 return rc;
1773 }
1774
1775 /*
1776 * CMD_SET_RF_CHANNEL.
1777 */
1778 struct mwl8k_cmd_set_rf_channel {
1779 struct mwl8k_cmd_pkt header;
1780 __le16 action;
1781 __u8 current_channel;
1782 __le32 channel_flags;
1783 } __attribute__((packed));
1784
1785 static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
1786 struct ieee80211_channel *channel)
1787 {
1788 struct mwl8k_cmd_set_rf_channel *cmd;
1789 int rc;
1790
1791 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1792 if (cmd == NULL)
1793 return -ENOMEM;
1794
1795 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
1796 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1797 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1798 cmd->current_channel = channel->hw_value;
1799 if (channel->band == IEEE80211_BAND_2GHZ)
1800 cmd->channel_flags = cpu_to_le32(0x00000081);
1801 else
1802 cmd->channel_flags = cpu_to_le32(0x00000000);
1803
1804 rc = mwl8k_post_cmd(hw, &cmd->header);
1805 kfree(cmd);
1806
1807 return rc;
1808 }
1809
1810 /*
1811 * CMD_SET_SLOT.
1812 */
1813 struct mwl8k_cmd_set_slot {
1814 struct mwl8k_cmd_pkt header;
1815 __le16 action;
1816 __u8 short_slot;
1817 } __attribute__((packed));
1818
1819 static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
1820 {
1821 struct mwl8k_cmd_set_slot *cmd;
1822 int rc;
1823
1824 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1825 if (cmd == NULL)
1826 return -ENOMEM;
1827
1828 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
1829 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1830 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1831 cmd->short_slot = short_slot_time;
1832
1833 rc = mwl8k_post_cmd(hw, &cmd->header);
1834 kfree(cmd);
1835
1836 return rc;
1837 }
1838
1839 /*
1840 * CMD_MIMO_CONFIG.
1841 */
1842 struct mwl8k_cmd_mimo_config {
1843 struct mwl8k_cmd_pkt header;
1844 __le32 action;
1845 __u8 rx_antenna_map;
1846 __u8 tx_antenna_map;
1847 } __attribute__((packed));
1848
1849 static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
1850 {
1851 struct mwl8k_cmd_mimo_config *cmd;
1852 int rc;
1853
1854 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1855 if (cmd == NULL)
1856 return -ENOMEM;
1857
1858 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
1859 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1860 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
1861 cmd->rx_antenna_map = rx;
1862 cmd->tx_antenna_map = tx;
1863
1864 rc = mwl8k_post_cmd(hw, &cmd->header);
1865 kfree(cmd);
1866
1867 return rc;
1868 }
1869
1870 /*
1871 * CMD_ENABLE_SNIFFER.
1872 */
1873 struct mwl8k_cmd_enable_sniffer {
1874 struct mwl8k_cmd_pkt header;
1875 __le32 action;
1876 } __attribute__((packed));
1877
1878 static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
1879 {
1880 struct mwl8k_cmd_enable_sniffer *cmd;
1881 int rc;
1882
1883 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1884 if (cmd == NULL)
1885 return -ENOMEM;
1886
1887 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
1888 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1889 cmd->action = cpu_to_le32(!!enable);
1890
1891 rc = mwl8k_post_cmd(hw, &cmd->header);
1892 kfree(cmd);
1893
1894 return rc;
1895 }
1896
1897 /*
1898 * CMD_SET_MAC_ADDR.
1899 */
1900 struct mwl8k_cmd_set_mac_addr {
1901 struct mwl8k_cmd_pkt header;
1902 __u8 mac_addr[ETH_ALEN];
1903 } __attribute__((packed));
1904
1905 static int mwl8k_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
1906 {
1907 struct mwl8k_cmd_set_mac_addr *cmd;
1908 int rc;
1909
1910 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1911 if (cmd == NULL)
1912 return -ENOMEM;
1913
1914 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
1915 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1916 memcpy(cmd->mac_addr, mac, ETH_ALEN);
1917
1918 rc = mwl8k_post_cmd(hw, &cmd->header);
1919 kfree(cmd);
1920
1921 return rc;
1922 }
1923
1924
1925 /*
1926 * CMD_SET_RATEADAPT_MODE.
1927 */
1928 struct mwl8k_cmd_set_rate_adapt_mode {
1929 struct mwl8k_cmd_pkt header;
1930 __le16 action;
1931 __le16 mode;
1932 } __attribute__((packed));
1933
1934 static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
1935 {
1936 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
1937 int rc;
1938
1939 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1940 if (cmd == NULL)
1941 return -ENOMEM;
1942
1943 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
1944 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1945 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1946 cmd->mode = cpu_to_le16(mode);
1947
1948 rc = mwl8k_post_cmd(hw, &cmd->header);
1949 kfree(cmd);
1950
1951 return rc;
1952 }
1953
1954 /*
1955 * CMD_SET_WMM_MODE.
1956 */
1957 struct mwl8k_cmd_set_wmm {
1958 struct mwl8k_cmd_pkt header;
1959 __le16 action;
1960 } __attribute__((packed));
1961
1962 static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
1963 {
1964 struct mwl8k_priv *priv = hw->priv;
1965 struct mwl8k_cmd_set_wmm *cmd;
1966 int rc;
1967
1968 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1969 if (cmd == NULL)
1970 return -ENOMEM;
1971
1972 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
1973 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1974 cmd->action = cpu_to_le16(!!enable);
1975
1976 rc = mwl8k_post_cmd(hw, &cmd->header);
1977 kfree(cmd);
1978
1979 if (!rc)
1980 priv->wmm_enabled = enable;
1981
1982 return rc;
1983 }
1984
1985 /*
1986 * CMD_SET_RTS_THRESHOLD.
1987 */
1988 struct mwl8k_cmd_rts_threshold {
1989 struct mwl8k_cmd_pkt header;
1990 __le16 action;
1991 __le16 threshold;
1992 } __attribute__((packed));
1993
1994 static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
1995 u16 action, u16 threshold)
1996 {
1997 struct mwl8k_cmd_rts_threshold *cmd;
1998 int rc;
1999
2000 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2001 if (cmd == NULL)
2002 return -ENOMEM;
2003
2004 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2005 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2006 cmd->action = cpu_to_le16(action);
2007 cmd->threshold = cpu_to_le16(threshold);
2008
2009 rc = mwl8k_post_cmd(hw, &cmd->header);
2010 kfree(cmd);
2011
2012 return rc;
2013 }
2014
2015 /*
2016 * CMD_SET_EDCA_PARAMS.
2017 */
2018 struct mwl8k_cmd_set_edca_params {
2019 struct mwl8k_cmd_pkt header;
2020
2021 /* See MWL8K_SET_EDCA_XXX below */
2022 __le16 action;
2023
2024 /* TX opportunity in units of 32 us */
2025 __le16 txop;
2026
2027 /* Log exponent of max contention period: 0...15*/
2028 __u8 log_cw_max;
2029
2030 /* Log exponent of min contention period: 0...15 */
2031 __u8 log_cw_min;
2032
2033 /* Adaptive interframe spacing in units of 32us */
2034 __u8 aifs;
2035
2036 /* TX queue to configure */
2037 __u8 txq;
2038 } __attribute__((packed));
2039
2040 #define MWL8K_SET_EDCA_CW 0x01
2041 #define MWL8K_SET_EDCA_TXOP 0x02
2042 #define MWL8K_SET_EDCA_AIFS 0x04
2043
2044 #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2045 MWL8K_SET_EDCA_TXOP | \
2046 MWL8K_SET_EDCA_AIFS)
2047
2048 static int
2049 mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2050 __u16 cw_min, __u16 cw_max,
2051 __u8 aifs, __u16 txop)
2052 {
2053 struct mwl8k_cmd_set_edca_params *cmd;
2054 int rc;
2055
2056 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2057 if (cmd == NULL)
2058 return -ENOMEM;
2059
2060 /*
2061 * Queues 0 (BE) and 1 (BK) are swapped in hardware for
2062 * this call.
2063 */
2064 qnum ^= !(qnum >> 1);
2065
2066 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2067 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2068 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2069 cmd->txop = cpu_to_le16(txop);
2070 cmd->log_cw_max = (u8)ilog2(cw_max + 1);
2071 cmd->log_cw_min = (u8)ilog2(cw_min + 1);
2072 cmd->aifs = aifs;
2073 cmd->txq = qnum;
2074
2075 rc = mwl8k_post_cmd(hw, &cmd->header);
2076 kfree(cmd);
2077
2078 return rc;
2079 }
2080
2081 /*
2082 * CMD_FINALIZE_JOIN.
2083 */
2084
2085 /* FJ beacon buffer size is compiled into the firmware. */
2086 #define MWL8K_FJ_BEACON_MAXLEN 128
2087
2088 struct mwl8k_cmd_finalize_join {
2089 struct mwl8k_cmd_pkt header;
2090 __le32 sleep_interval; /* Number of beacon periods to sleep */
2091 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2092 } __attribute__((packed));
2093
2094 static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2095 __u16 framelen, __u16 dtim)
2096 {
2097 struct mwl8k_cmd_finalize_join *cmd;
2098 struct ieee80211_mgmt *payload = frame;
2099 u16 hdrlen;
2100 u32 payload_len;
2101 int rc;
2102
2103 if (frame == NULL)
2104 return -EINVAL;
2105
2106 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2107 if (cmd == NULL)
2108 return -ENOMEM;
2109
2110 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2111 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2112 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2113
2114 hdrlen = ieee80211_hdrlen(payload->frame_control);
2115
2116 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2117
2118 /* XXX TBD Might just have to abort and return an error */
2119 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2120 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
2121 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2122 payload_len, MWL8K_FJ_BEACON_MAXLEN);
2123
2124 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2125 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2126
2127 if (payload && payload_len)
2128 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2129
2130 rc = mwl8k_post_cmd(hw, &cmd->header);
2131 kfree(cmd);
2132 return rc;
2133 }
2134
2135 /*
2136 * CMD_UPDATE_STADB.
2137 */
2138 struct mwl8k_cmd_update_sta_db {
2139 struct mwl8k_cmd_pkt header;
2140
2141 /* See STADB_ACTION_TYPE */
2142 __le32 action;
2143
2144 /* Peer MAC address */
2145 __u8 peer_addr[ETH_ALEN];
2146
2147 __le32 reserved;
2148
2149 /* Peer info - valid during add/update. */
2150 struct peer_capability_info peer_info;
2151 } __attribute__((packed));
2152
2153 static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2154 struct ieee80211_vif *vif, __u32 action)
2155 {
2156 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2157 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2158 struct mwl8k_cmd_update_sta_db *cmd;
2159 struct peer_capability_info *peer_info;
2160 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2161 int rc;
2162 __u8 count, *rates;
2163
2164 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2165 if (cmd == NULL)
2166 return -ENOMEM;
2167
2168 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2169 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2170
2171 cmd->action = cpu_to_le32(action);
2172 peer_info = &cmd->peer_info;
2173 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
2174
2175 switch (action) {
2176 case MWL8K_STA_DB_ADD_ENTRY:
2177 case MWL8K_STA_DB_MODIFY_ENTRY:
2178 /* Build peer_info block */
2179 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2180 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2181 peer_info->interop = 1;
2182 peer_info->amsdu_enabled = 0;
2183
2184 rates = peer_info->legacy_rates;
2185 for (count = 0; count < mv_vif->legacy_nrates; count++)
2186 rates[count] = bitrates[count].hw_value;
2187
2188 rc = mwl8k_post_cmd(hw, &cmd->header);
2189 if (rc == 0)
2190 mv_vif->peer_id = peer_info->station_id;
2191
2192 break;
2193
2194 case MWL8K_STA_DB_DEL_ENTRY:
2195 case MWL8K_STA_DB_FLUSH:
2196 default:
2197 rc = mwl8k_post_cmd(hw, &cmd->header);
2198 if (rc == 0)
2199 mv_vif->peer_id = 0;
2200 break;
2201 }
2202 kfree(cmd);
2203
2204 return rc;
2205 }
2206
2207 /*
2208 * CMD_SET_AID.
2209 */
2210 #define MWL8K_RATE_INDEX_MAX_ARRAY 14
2211
2212 #define MWL8K_FRAME_PROT_DISABLED 0x00
2213 #define MWL8K_FRAME_PROT_11G 0x07
2214 #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2215 #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
2216
2217 struct mwl8k_cmd_update_set_aid {
2218 struct mwl8k_cmd_pkt header;
2219 __le16 aid;
2220
2221 /* AP's MAC address (BSSID) */
2222 __u8 bssid[ETH_ALEN];
2223 __le16 protection_mode;
2224 __u8 supp_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2225 } __attribute__((packed));
2226
2227 static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2228 struct ieee80211_vif *vif)
2229 {
2230 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2231 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2232 struct mwl8k_cmd_update_set_aid *cmd;
2233 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2234 int count;
2235 u16 prot_mode;
2236 int rc;
2237
2238 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2239 if (cmd == NULL)
2240 return -ENOMEM;
2241
2242 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2243 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2244 cmd->aid = cpu_to_le16(info->aid);
2245
2246 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
2247
2248 if (info->use_cts_prot) {
2249 prot_mode = MWL8K_FRAME_PROT_11G;
2250 } else {
2251 switch (info->ht_operation_mode &
2252 IEEE80211_HT_OP_MODE_PROTECTION) {
2253 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2254 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2255 break;
2256 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2257 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2258 break;
2259 default:
2260 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2261 break;
2262 }
2263 }
2264 cmd->protection_mode = cpu_to_le16(prot_mode);
2265
2266 for (count = 0; count < mv_vif->legacy_nrates; count++)
2267 cmd->supp_rates[count] = bitrates[count].hw_value;
2268
2269 rc = mwl8k_post_cmd(hw, &cmd->header);
2270 kfree(cmd);
2271
2272 return rc;
2273 }
2274
2275 /*
2276 * CMD_SET_RATE.
2277 */
2278 struct mwl8k_cmd_update_rateset {
2279 struct mwl8k_cmd_pkt header;
2280 __u8 legacy_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2281
2282 /* Bitmap for supported MCS codes. */
2283 __u8 mcs_set[MWL8K_IEEE_LEGACY_DATA_RATES];
2284 __u8 reserved[MWL8K_IEEE_LEGACY_DATA_RATES];
2285 } __attribute__((packed));
2286
2287 static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2288 struct ieee80211_vif *vif)
2289 {
2290 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2291 struct mwl8k_cmd_update_rateset *cmd;
2292 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2293 int count;
2294 int rc;
2295
2296 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2297 if (cmd == NULL)
2298 return -ENOMEM;
2299
2300 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2301 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2302
2303 for (count = 0; count < mv_vif->legacy_nrates; count++)
2304 cmd->legacy_rates[count] = bitrates[count].hw_value;
2305
2306 rc = mwl8k_post_cmd(hw, &cmd->header);
2307 kfree(cmd);
2308
2309 return rc;
2310 }
2311
2312 /*
2313 * CMD_USE_FIXED_RATE.
2314 */
2315 #define MWL8K_RATE_TABLE_SIZE 8
2316 #define MWL8K_UCAST_RATE 0
2317 #define MWL8K_USE_AUTO_RATE 0x0002
2318
2319 struct mwl8k_rate_entry {
2320 /* Set to 1 if HT rate, 0 if legacy. */
2321 __le32 is_ht_rate;
2322
2323 /* Set to 1 to use retry_count field. */
2324 __le32 enable_retry;
2325
2326 /* Specified legacy rate or MCS. */
2327 __le32 rate;
2328
2329 /* Number of allowed retries. */
2330 __le32 retry_count;
2331 } __attribute__((packed));
2332
2333 struct mwl8k_rate_table {
2334 /* 1 to allow specified rate and below */
2335 __le32 allow_rate_drop;
2336 __le32 num_rates;
2337 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2338 } __attribute__((packed));
2339
2340 struct mwl8k_cmd_use_fixed_rate {
2341 struct mwl8k_cmd_pkt header;
2342 __le32 action;
2343 struct mwl8k_rate_table rate_table;
2344
2345 /* Unicast, Broadcast or Multicast */
2346 __le32 rate_type;
2347 __le32 reserved1;
2348 __le32 reserved2;
2349 } __attribute__((packed));
2350
2351 static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2352 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2353 {
2354 struct mwl8k_cmd_use_fixed_rate *cmd;
2355 int count;
2356 int rc;
2357
2358 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2359 if (cmd == NULL)
2360 return -ENOMEM;
2361
2362 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2363 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2364
2365 cmd->action = cpu_to_le32(action);
2366 cmd->rate_type = cpu_to_le32(rate_type);
2367
2368 if (rate_table != NULL) {
2369 /*
2370 * Copy over each field manually so that endian
2371 * conversion can be done.
2372 */
2373 cmd->rate_table.allow_rate_drop =
2374 cpu_to_le32(rate_table->allow_rate_drop);
2375 cmd->rate_table.num_rates =
2376 cpu_to_le32(rate_table->num_rates);
2377
2378 for (count = 0; count < rate_table->num_rates; count++) {
2379 struct mwl8k_rate_entry *dst =
2380 &cmd->rate_table.rate_entry[count];
2381 struct mwl8k_rate_entry *src =
2382 &rate_table->rate_entry[count];
2383
2384 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2385 dst->enable_retry = cpu_to_le32(src->enable_retry);
2386 dst->rate = cpu_to_le32(src->rate);
2387 dst->retry_count = cpu_to_le32(src->retry_count);
2388 }
2389 }
2390
2391 rc = mwl8k_post_cmd(hw, &cmd->header);
2392 kfree(cmd);
2393
2394 return rc;
2395 }
2396
2397
2398 /*
2399 * Interrupt handling.
2400 */
2401 static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2402 {
2403 struct ieee80211_hw *hw = dev_id;
2404 struct mwl8k_priv *priv = hw->priv;
2405 u32 status;
2406
2407 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2408 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2409
2410 if (!status)
2411 return IRQ_NONE;
2412
2413 if (status & MWL8K_A2H_INT_TX_DONE)
2414 tasklet_schedule(&priv->tx_reclaim_task);
2415
2416 if (status & MWL8K_A2H_INT_RX_READY) {
2417 while (rxq_process(hw, 0, 1))
2418 rxq_refill(hw, 0, 1);
2419 }
2420
2421 if (status & MWL8K_A2H_INT_OPC_DONE) {
2422 if (priv->hostcmd_wait != NULL)
2423 complete(priv->hostcmd_wait);
2424 }
2425
2426 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
2427 if (!mutex_is_locked(&priv->fw_mutex) &&
2428 priv->radio_on && priv->pending_tx_pkts)
2429 mwl8k_tx_start(priv);
2430 }
2431
2432 return IRQ_HANDLED;
2433 }
2434
2435
2436 /*
2437 * Core driver operations.
2438 */
2439 static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2440 {
2441 struct mwl8k_priv *priv = hw->priv;
2442 int index = skb_get_queue_mapping(skb);
2443 int rc;
2444
2445 if (priv->current_channel == NULL) {
2446 printk(KERN_DEBUG "%s: dropped TX frame since radio "
2447 "disabled\n", wiphy_name(hw->wiphy));
2448 dev_kfree_skb(skb);
2449 return NETDEV_TX_OK;
2450 }
2451
2452 rc = mwl8k_txq_xmit(hw, index, skb);
2453
2454 return rc;
2455 }
2456
2457 static int mwl8k_start(struct ieee80211_hw *hw)
2458 {
2459 struct mwl8k_priv *priv = hw->priv;
2460 int rc;
2461
2462 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
2463 IRQF_SHARED, MWL8K_NAME, hw);
2464 if (rc) {
2465 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2466 wiphy_name(hw->wiphy));
2467 return -EIO;
2468 }
2469
2470 /* Enable tx reclaim tasklet */
2471 tasklet_enable(&priv->tx_reclaim_task);
2472
2473 /* Enable interrupts */
2474 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2475
2476 rc = mwl8k_fw_lock(hw);
2477 if (!rc) {
2478 rc = mwl8k_cmd_802_11_radio_enable(hw);
2479
2480 if (!rc)
2481 rc = mwl8k_cmd_set_pre_scan(hw);
2482
2483 if (!rc)
2484 rc = mwl8k_cmd_set_post_scan(hw,
2485 "\x00\x00\x00\x00\x00\x00");
2486
2487 if (!rc)
2488 rc = mwl8k_cmd_setrateadaptmode(hw, 0);
2489
2490 if (!rc)
2491 rc = mwl8k_set_wmm(hw, 0);
2492
2493 if (!rc)
2494 rc = mwl8k_enable_sniffer(hw, 0);
2495
2496 mwl8k_fw_unlock(hw);
2497 }
2498
2499 if (rc) {
2500 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2501 free_irq(priv->pdev->irq, hw);
2502 tasklet_disable(&priv->tx_reclaim_task);
2503 }
2504
2505 return rc;
2506 }
2507
2508 static void mwl8k_stop(struct ieee80211_hw *hw)
2509 {
2510 struct mwl8k_priv *priv = hw->priv;
2511 int i;
2512
2513 mwl8k_cmd_802_11_radio_disable(hw);
2514
2515 ieee80211_stop_queues(hw);
2516
2517 /* Disable interrupts */
2518 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2519 free_irq(priv->pdev->irq, hw);
2520
2521 /* Stop finalize join worker */
2522 cancel_work_sync(&priv->finalize_join_worker);
2523 if (priv->beacon_skb != NULL)
2524 dev_kfree_skb(priv->beacon_skb);
2525
2526 /* Stop tx reclaim tasklet */
2527 tasklet_disable(&priv->tx_reclaim_task);
2528
2529 /* Return all skbs to mac80211 */
2530 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2531 mwl8k_txq_reclaim(hw, i, 1);
2532 }
2533
2534 static int mwl8k_add_interface(struct ieee80211_hw *hw,
2535 struct ieee80211_if_init_conf *conf)
2536 {
2537 struct mwl8k_priv *priv = hw->priv;
2538 struct mwl8k_vif *mwl8k_vif;
2539
2540 /*
2541 * We only support one active interface at a time.
2542 */
2543 if (priv->vif != NULL)
2544 return -EBUSY;
2545
2546 /*
2547 * We only support managed interfaces for now.
2548 */
2549 if (conf->type != NL80211_IFTYPE_STATION)
2550 return -EINVAL;
2551
2552 /*
2553 * Reject interface creation if sniffer mode is active, as
2554 * STA operation is mutually exclusive with hardware sniffer
2555 * mode.
2556 */
2557 if (priv->sniffer_enabled) {
2558 printk(KERN_INFO "%s: unable to create STA "
2559 "interface due to sniffer mode being enabled\n",
2560 wiphy_name(hw->wiphy));
2561 return -EINVAL;
2562 }
2563
2564 /* Clean out driver private area */
2565 mwl8k_vif = MWL8K_VIF(conf->vif);
2566 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2567
2568 /* Set and save the mac address */
2569 mwl8k_set_mac_addr(hw, conf->mac_addr);
2570 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
2571
2572 /* Back pointer to parent config block */
2573 mwl8k_vif->priv = priv;
2574
2575 /* Setup initial PHY parameters */
2576 memcpy(mwl8k_vif->legacy_rates,
2577 priv->rates, sizeof(mwl8k_vif->legacy_rates));
2578 mwl8k_vif->legacy_nrates = ARRAY_SIZE(priv->rates);
2579
2580 /* Set Initial sequence number to zero */
2581 mwl8k_vif->seqno = 0;
2582
2583 priv->vif = conf->vif;
2584 priv->current_channel = NULL;
2585
2586 return 0;
2587 }
2588
2589 static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2590 struct ieee80211_if_init_conf *conf)
2591 {
2592 struct mwl8k_priv *priv = hw->priv;
2593
2594 if (priv->vif == NULL)
2595 return;
2596
2597 mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
2598
2599 priv->vif = NULL;
2600 }
2601
2602 static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
2603 {
2604 struct ieee80211_conf *conf = &hw->conf;
2605 struct mwl8k_priv *priv = hw->priv;
2606 int rc;
2607
2608 if (conf->flags & IEEE80211_CONF_IDLE) {
2609 mwl8k_cmd_802_11_radio_disable(hw);
2610 priv->current_channel = NULL;
2611 return 0;
2612 }
2613
2614 rc = mwl8k_fw_lock(hw);
2615 if (rc)
2616 return rc;
2617
2618 rc = mwl8k_cmd_802_11_radio_enable(hw);
2619 if (rc)
2620 goto out;
2621
2622 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2623 if (rc)
2624 goto out;
2625
2626 priv->current_channel = conf->channel;
2627
2628 if (conf->power_level > 18)
2629 conf->power_level = 18;
2630 rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level);
2631 if (rc)
2632 goto out;
2633
2634 if (mwl8k_cmd_mimo_config(hw, 0x7, 0x7))
2635 rc = -EINVAL;
2636
2637 out:
2638 mwl8k_fw_unlock(hw);
2639
2640 return rc;
2641 }
2642
2643 static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
2644 struct ieee80211_vif *vif,
2645 struct ieee80211_bss_conf *info,
2646 u32 changed)
2647 {
2648 struct mwl8k_priv *priv = hw->priv;
2649 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
2650 int rc;
2651
2652 if (changed & BSS_CHANGED_BSSID)
2653 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
2654
2655 if ((changed & BSS_CHANGED_ASSOC) == 0)
2656 return;
2657
2658 priv->capture_beacon = false;
2659
2660 rc = mwl8k_fw_lock(hw);
2661 if (rc)
2662 return;
2663
2664 if (info->assoc) {
2665 memcpy(&mwl8k_vif->bss_info, info,
2666 sizeof(struct ieee80211_bss_conf));
2667
2668 /* Install rates */
2669 rc = mwl8k_update_rateset(hw, vif);
2670 if (rc)
2671 goto out;
2672
2673 /* Turn on rate adaptation */
2674 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
2675 MWL8K_UCAST_RATE, NULL);
2676 if (rc)
2677 goto out;
2678
2679 /* Set radio preamble */
2680 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
2681 if (rc)
2682 goto out;
2683
2684 /* Set slot time */
2685 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
2686 if (rc)
2687 goto out;
2688
2689 /* Update peer rate info */
2690 rc = mwl8k_cmd_update_sta_db(hw, vif,
2691 MWL8K_STA_DB_MODIFY_ENTRY);
2692 if (rc)
2693 goto out;
2694
2695 /* Set AID */
2696 rc = mwl8k_cmd_set_aid(hw, vif);
2697 if (rc)
2698 goto out;
2699
2700 /*
2701 * Finalize the join. Tell rx handler to process
2702 * next beacon from our BSSID.
2703 */
2704 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
2705 priv->capture_beacon = true;
2706 } else {
2707 rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
2708 memset(&mwl8k_vif->bss_info, 0,
2709 sizeof(struct ieee80211_bss_conf));
2710 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
2711 }
2712
2713 out:
2714 mwl8k_fw_unlock(hw);
2715 }
2716
2717 static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
2718 int mc_count, struct dev_addr_list *mclist)
2719 {
2720 struct mwl8k_cmd_pkt *cmd;
2721
2722 /*
2723 * Synthesize and return a command packet that programs the
2724 * hardware multicast address filter. At this point we don't
2725 * know whether FIF_ALLMULTI is being requested, but if it is,
2726 * we'll end up throwing this packet away and creating a new
2727 * one in mwl8k_configure_filter().
2728 */
2729 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
2730
2731 return (unsigned long)cmd;
2732 }
2733
2734 static int
2735 mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
2736 unsigned int changed_flags,
2737 unsigned int *total_flags)
2738 {
2739 struct mwl8k_priv *priv = hw->priv;
2740
2741 /*
2742 * Hardware sniffer mode is mutually exclusive with STA
2743 * operation, so refuse to enable sniffer mode if a STA
2744 * interface is active.
2745 */
2746 if (priv->vif != NULL) {
2747 if (net_ratelimit())
2748 printk(KERN_INFO "%s: not enabling sniffer "
2749 "mode because STA interface is active\n",
2750 wiphy_name(hw->wiphy));
2751 return 0;
2752 }
2753
2754 if (!priv->sniffer_enabled) {
2755 if (mwl8k_enable_sniffer(hw, 1))
2756 return 0;
2757 priv->sniffer_enabled = true;
2758 }
2759
2760 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
2761 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
2762 FIF_OTHER_BSS;
2763
2764 return 1;
2765 }
2766
2767 static void mwl8k_configure_filter(struct ieee80211_hw *hw,
2768 unsigned int changed_flags,
2769 unsigned int *total_flags,
2770 u64 multicast)
2771 {
2772 struct mwl8k_priv *priv = hw->priv;
2773 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
2774
2775 /*
2776 * Enable hardware sniffer mode if FIF_CONTROL or
2777 * FIF_OTHER_BSS is requested.
2778 */
2779 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
2780 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
2781 kfree(cmd);
2782 return;
2783 }
2784
2785 /* Clear unsupported feature flags */
2786 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
2787
2788 if (mwl8k_fw_lock(hw))
2789 return;
2790
2791 if (priv->sniffer_enabled) {
2792 mwl8k_enable_sniffer(hw, 0);
2793 priv->sniffer_enabled = false;
2794 }
2795
2796 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2797 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
2798 /*
2799 * Disable the BSS filter.
2800 */
2801 mwl8k_cmd_set_pre_scan(hw);
2802 } else {
2803 u8 *bssid;
2804
2805 /*
2806 * Enable the BSS filter.
2807 *
2808 * If there is an active STA interface, use that
2809 * interface's BSSID, otherwise use a dummy one
2810 * (where the OUI part needs to be nonzero for
2811 * the BSSID to be accepted by POST_SCAN).
2812 */
2813 bssid = "\x01\x00\x00\x00\x00\x00";
2814 if (priv->vif != NULL)
2815 bssid = MWL8K_VIF(priv->vif)->bssid;
2816
2817 mwl8k_cmd_set_post_scan(hw, bssid);
2818 }
2819 }
2820
2821 /*
2822 * If FIF_ALLMULTI is being requested, throw away the command
2823 * packet that ->prepare_multicast() built and replace it with
2824 * a command packet that enables reception of all multicast
2825 * packets.
2826 */
2827 if (*total_flags & FIF_ALLMULTI) {
2828 kfree(cmd);
2829 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
2830 }
2831
2832 if (cmd != NULL) {
2833 mwl8k_post_cmd(hw, cmd);
2834 kfree(cmd);
2835 }
2836
2837 mwl8k_fw_unlock(hw);
2838 }
2839
2840 static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2841 {
2842 return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value);
2843 }
2844
2845 static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2846 const struct ieee80211_tx_queue_params *params)
2847 {
2848 struct mwl8k_priv *priv = hw->priv;
2849 int rc;
2850
2851 rc = mwl8k_fw_lock(hw);
2852 if (!rc) {
2853 if (!priv->wmm_enabled)
2854 rc = mwl8k_set_wmm(hw, 1);
2855
2856 if (!rc)
2857 rc = mwl8k_set_edca_params(hw, queue,
2858 params->cw_min,
2859 params->cw_max,
2860 params->aifs,
2861 params->txop);
2862
2863 mwl8k_fw_unlock(hw);
2864 }
2865
2866 return rc;
2867 }
2868
2869 static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
2870 struct ieee80211_tx_queue_stats *stats)
2871 {
2872 struct mwl8k_priv *priv = hw->priv;
2873 struct mwl8k_tx_queue *txq;
2874 int index;
2875
2876 spin_lock_bh(&priv->tx_lock);
2877 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
2878 txq = priv->txq + index;
2879 memcpy(&stats[index], &txq->stats,
2880 sizeof(struct ieee80211_tx_queue_stats));
2881 }
2882 spin_unlock_bh(&priv->tx_lock);
2883
2884 return 0;
2885 }
2886
2887 static int mwl8k_get_stats(struct ieee80211_hw *hw,
2888 struct ieee80211_low_level_stats *stats)
2889 {
2890 return mwl8k_cmd_802_11_get_stat(hw, stats);
2891 }
2892
2893 static const struct ieee80211_ops mwl8k_ops = {
2894 .tx = mwl8k_tx,
2895 .start = mwl8k_start,
2896 .stop = mwl8k_stop,
2897 .add_interface = mwl8k_add_interface,
2898 .remove_interface = mwl8k_remove_interface,
2899 .config = mwl8k_config,
2900 .bss_info_changed = mwl8k_bss_info_changed,
2901 .prepare_multicast = mwl8k_prepare_multicast,
2902 .configure_filter = mwl8k_configure_filter,
2903 .set_rts_threshold = mwl8k_set_rts_threshold,
2904 .conf_tx = mwl8k_conf_tx,
2905 .get_tx_stats = mwl8k_get_tx_stats,
2906 .get_stats = mwl8k_get_stats,
2907 };
2908
2909 static void mwl8k_tx_reclaim_handler(unsigned long data)
2910 {
2911 int i;
2912 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
2913 struct mwl8k_priv *priv = hw->priv;
2914
2915 spin_lock_bh(&priv->tx_lock);
2916 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2917 mwl8k_txq_reclaim(hw, i, 0);
2918
2919 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
2920 complete(priv->tx_wait);
2921 priv->tx_wait = NULL;
2922 }
2923 spin_unlock_bh(&priv->tx_lock);
2924 }
2925
2926 static void mwl8k_finalize_join_worker(struct work_struct *work)
2927 {
2928 struct mwl8k_priv *priv =
2929 container_of(work, struct mwl8k_priv, finalize_join_worker);
2930 struct sk_buff *skb = priv->beacon_skb;
2931 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
2932
2933 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
2934 dev_kfree_skb(skb);
2935
2936 priv->beacon_skb = NULL;
2937 }
2938
2939 static struct mwl8k_device_info di_8687 = {
2940 .part_name = "88w8687",
2941 .helper_image = "mwl8k/helper_8687.fw",
2942 .fw_image = "mwl8k/fmimage_8687.fw",
2943 };
2944
2945 static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
2946 {
2947 PCI_VDEVICE(MARVELL, 0x2a2b),
2948 .driver_data = (unsigned long)&di_8687,
2949 }, {
2950 PCI_VDEVICE(MARVELL, 0x2a30),
2951 .driver_data = (unsigned long)&di_8687,
2952 }, {
2953 },
2954 };
2955 MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
2956
2957 static int __devinit mwl8k_probe(struct pci_dev *pdev,
2958 const struct pci_device_id *id)
2959 {
2960 static int printed_version = 0;
2961 struct ieee80211_hw *hw;
2962 struct mwl8k_priv *priv;
2963 int rc;
2964 int i;
2965
2966 if (!printed_version) {
2967 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
2968 printed_version = 1;
2969 }
2970
2971 rc = pci_enable_device(pdev);
2972 if (rc) {
2973 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
2974 MWL8K_NAME);
2975 return rc;
2976 }
2977
2978 rc = pci_request_regions(pdev, MWL8K_NAME);
2979 if (rc) {
2980 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
2981 MWL8K_NAME);
2982 return rc;
2983 }
2984
2985 pci_set_master(pdev);
2986
2987 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
2988 if (hw == NULL) {
2989 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
2990 rc = -ENOMEM;
2991 goto err_free_reg;
2992 }
2993
2994 priv = hw->priv;
2995 priv->hw = hw;
2996 priv->pdev = pdev;
2997 priv->device_info = (void *)id->driver_data;
2998 priv->sniffer_enabled = false;
2999 priv->wmm_enabled = false;
3000 priv->pending_tx_pkts = 0;
3001
3002 SET_IEEE80211_DEV(hw, &pdev->dev);
3003 pci_set_drvdata(pdev, hw);
3004
3005 priv->sram = pci_iomap(pdev, 0, 0x10000);
3006 if (priv->sram == NULL) {
3007 printk(KERN_ERR "%s: Cannot map device SRAM\n",
3008 wiphy_name(hw->wiphy));
3009 goto err_iounmap;
3010 }
3011
3012 /*
3013 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3014 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3015 */
3016 priv->regs = pci_iomap(pdev, 1, 0x10000);
3017 if (priv->regs == NULL) {
3018 priv->regs = pci_iomap(pdev, 2, 0x10000);
3019 if (priv->regs == NULL) {
3020 printk(KERN_ERR "%s: Cannot map device registers\n",
3021 wiphy_name(hw->wiphy));
3022 goto err_iounmap;
3023 }
3024 }
3025
3026 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3027 priv->band.band = IEEE80211_BAND_2GHZ;
3028 priv->band.channels = priv->channels;
3029 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3030 priv->band.bitrates = priv->rates;
3031 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3032 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3033
3034 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3035 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3036
3037 /*
3038 * Extra headroom is the size of the required DMA header
3039 * minus the size of the smallest 802.11 frame (CTS frame).
3040 */
3041 hw->extra_tx_headroom =
3042 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3043
3044 hw->channel_change_time = 10;
3045
3046 hw->queues = MWL8K_TX_QUEUES;
3047
3048 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
3049
3050 /* Set rssi and noise values to dBm */
3051 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
3052 hw->vif_data_size = sizeof(struct mwl8k_vif);
3053 priv->vif = NULL;
3054
3055 /* Set default radio state and preamble */
3056 priv->radio_on = 0;
3057 priv->radio_short_preamble = 0;
3058
3059 /* Finalize join worker */
3060 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3061
3062 /* TX reclaim tasklet */
3063 tasklet_init(&priv->tx_reclaim_task,
3064 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3065 tasklet_disable(&priv->tx_reclaim_task);
3066
3067 /* Power management cookie */
3068 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3069 if (priv->cookie == NULL)
3070 goto err_iounmap;
3071
3072 rc = mwl8k_rxq_init(hw, 0);
3073 if (rc)
3074 goto err_iounmap;
3075 rxq_refill(hw, 0, INT_MAX);
3076
3077 mutex_init(&priv->fw_mutex);
3078 priv->fw_mutex_owner = NULL;
3079 priv->fw_mutex_depth = 0;
3080 priv->hostcmd_wait = NULL;
3081
3082 spin_lock_init(&priv->tx_lock);
3083
3084 priv->tx_wait = NULL;
3085
3086 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3087 rc = mwl8k_txq_init(hw, i);
3088 if (rc)
3089 goto err_free_queues;
3090 }
3091
3092 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3093 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3094 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3095 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3096
3097 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
3098 IRQF_SHARED, MWL8K_NAME, hw);
3099 if (rc) {
3100 printk(KERN_ERR "%s: failed to register IRQ handler\n",
3101 wiphy_name(hw->wiphy));
3102 goto err_free_queues;
3103 }
3104
3105 /* Reset firmware and hardware */
3106 mwl8k_hw_reset(priv);
3107
3108 /* Ask userland hotplug daemon for the device firmware */
3109 rc = mwl8k_request_firmware(priv);
3110 if (rc) {
3111 printk(KERN_ERR "%s: Firmware files not found\n",
3112 wiphy_name(hw->wiphy));
3113 goto err_free_irq;
3114 }
3115
3116 /* Load firmware into hardware */
3117 rc = mwl8k_load_firmware(hw);
3118 if (rc) {
3119 printk(KERN_ERR "%s: Cannot start firmware\n",
3120 wiphy_name(hw->wiphy));
3121 goto err_stop_firmware;
3122 }
3123
3124 /* Reclaim memory once firmware is successfully loaded */
3125 mwl8k_release_firmware(priv);
3126
3127 /*
3128 * Temporarily enable interrupts. Initial firmware host
3129 * commands use interrupts and avoids polling. Disable
3130 * interrupts when done.
3131 */
3132 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3133
3134 /* Get config data, mac addrs etc */
3135 rc = mwl8k_cmd_get_hw_spec(hw);
3136 if (rc) {
3137 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3138 wiphy_name(hw->wiphy));
3139 goto err_stop_firmware;
3140 }
3141
3142 /* Turn radio off */
3143 rc = mwl8k_cmd_802_11_radio_disable(hw);
3144 if (rc) {
3145 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
3146 goto err_stop_firmware;
3147 }
3148
3149 /* Clear MAC address */
3150 rc = mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
3151 if (rc) {
3152 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3153 wiphy_name(hw->wiphy));
3154 goto err_stop_firmware;
3155 }
3156
3157 /* Disable interrupts */
3158 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3159 free_irq(priv->pdev->irq, hw);
3160
3161 rc = ieee80211_register_hw(hw);
3162 if (rc) {
3163 printk(KERN_ERR "%s: Cannot register device\n",
3164 wiphy_name(hw->wiphy));
3165 goto err_stop_firmware;
3166 }
3167
3168 printk(KERN_INFO "%s: %s v%d, %pM, firmware version %u.%u.%u.%u\n",
3169 wiphy_name(hw->wiphy), priv->device_info->part_name,
3170 priv->hw_rev, hw->wiphy->perm_addr,
3171 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3172 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
3173
3174 return 0;
3175
3176 err_stop_firmware:
3177 mwl8k_hw_reset(priv);
3178 mwl8k_release_firmware(priv);
3179
3180 err_free_irq:
3181 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3182 free_irq(priv->pdev->irq, hw);
3183
3184 err_free_queues:
3185 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3186 mwl8k_txq_deinit(hw, i);
3187 mwl8k_rxq_deinit(hw, 0);
3188
3189 err_iounmap:
3190 if (priv->cookie != NULL)
3191 pci_free_consistent(priv->pdev, 4,
3192 priv->cookie, priv->cookie_dma);
3193
3194 if (priv->regs != NULL)
3195 pci_iounmap(pdev, priv->regs);
3196
3197 if (priv->sram != NULL)
3198 pci_iounmap(pdev, priv->sram);
3199
3200 pci_set_drvdata(pdev, NULL);
3201 ieee80211_free_hw(hw);
3202
3203 err_free_reg:
3204 pci_release_regions(pdev);
3205 pci_disable_device(pdev);
3206
3207 return rc;
3208 }
3209
3210 static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
3211 {
3212 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3213 }
3214
3215 static void __devexit mwl8k_remove(struct pci_dev *pdev)
3216 {
3217 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3218 struct mwl8k_priv *priv;
3219 int i;
3220
3221 if (hw == NULL)
3222 return;
3223 priv = hw->priv;
3224
3225 ieee80211_stop_queues(hw);
3226
3227 ieee80211_unregister_hw(hw);
3228
3229 /* Remove tx reclaim tasklet */
3230 tasklet_kill(&priv->tx_reclaim_task);
3231
3232 /* Stop hardware */
3233 mwl8k_hw_reset(priv);
3234
3235 /* Return all skbs to mac80211 */
3236 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3237 mwl8k_txq_reclaim(hw, i, 1);
3238
3239 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3240 mwl8k_txq_deinit(hw, i);
3241
3242 mwl8k_rxq_deinit(hw, 0);
3243
3244 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
3245
3246 pci_iounmap(pdev, priv->regs);
3247 pci_iounmap(pdev, priv->sram);
3248 pci_set_drvdata(pdev, NULL);
3249 ieee80211_free_hw(hw);
3250 pci_release_regions(pdev);
3251 pci_disable_device(pdev);
3252 }
3253
3254 static struct pci_driver mwl8k_driver = {
3255 .name = MWL8K_NAME,
3256 .id_table = mwl8k_pci_id_table,
3257 .probe = mwl8k_probe,
3258 .remove = __devexit_p(mwl8k_remove),
3259 .shutdown = __devexit_p(mwl8k_shutdown),
3260 };
3261
3262 static int __init mwl8k_init(void)
3263 {
3264 return pci_register_driver(&mwl8k_driver);
3265 }
3266
3267 static void __exit mwl8k_exit(void)
3268 {
3269 pci_unregister_driver(&mwl8k_driver);
3270 }
3271
3272 module_init(mwl8k_init);
3273 module_exit(mwl8k_exit);
3274
3275 MODULE_DESCRIPTION(MWL8K_DESC);
3276 MODULE_VERSION(MWL8K_VERSION);
3277 MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3278 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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