projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
rtl8xxxu: Add radio init tables for 8192eu
[deliverable/linux.git] / drivers / net / wireless / realtek / rtl8xxxu / rtl8xxxu.c
1 /*
2 * RTL8XXXU mac80211 USB driver
3 *
4 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
5 *
6 * Portions, notably calibration code:
7 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
8 *
9 * This driver was written as a replacement for the vendor provided
10 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
11 * their programming interface, I have started adding support for
12 * additional 8xxx chips like the 8192cu, 8188cus, etc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of version 2 of the GNU General Public License as
16 * published by the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * more details.
22 */
23
24 #include <linux/init.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/errno.h>
28 #include <linux/slab.h>
29 #include <linux/module.h>
30 #include <linux/spinlock.h>
31 #include <linux/list.h>
32 #include <linux/usb.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/wireless.h>
37 #include <linux/firmware.h>
38 #include <linux/moduleparam.h>
39 #include <net/mac80211.h>
40 #include "rtl8xxxu.h"
41 #include "rtl8xxxu_regs.h"
42
43 #define DRIVER_NAME "rtl8xxxu"
44
45 static int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
46 static bool rtl8xxxu_ht40_2g;
47
48 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
49 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
50 MODULE_LICENSE("GPL");
51 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
52 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
53 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
54 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
55 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
56 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
57 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
58 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
59 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
60
61 module_param_named(debug, rtl8xxxu_debug, int, 0600);
62 MODULE_PARM_DESC(debug, "Set debug mask");
63 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
64 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
65
66 #define USB_VENDOR_ID_REALTEK 0x0bda
67 /* Minimum IEEE80211_MAX_FRAME_LEN */
68 #define RTL_RX_BUFFER_SIZE IEEE80211_MAX_FRAME_LEN
69 #define RTL8XXXU_RX_URBS 32
70 #define RTL8XXXU_RX_URB_PENDING_WATER 8
71 #define RTL8XXXU_TX_URBS 64
72 #define RTL8XXXU_TX_URB_LOW_WATER 25
73 #define RTL8XXXU_TX_URB_HIGH_WATER 32
74
75 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
76 struct rtl8xxxu_rx_urb *rx_urb);
77
78 static struct ieee80211_rate rtl8xxxu_rates[] = {
79 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
80 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
81 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
82 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
83 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
84 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
85 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
86 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
87 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
88 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
89 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
90 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
91 };
92
93 static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
94 { .band = NL80211_BAND_2GHZ, .center_freq = 2412,
95 .hw_value = 1, .max_power = 30 },
96 { .band = NL80211_BAND_2GHZ, .center_freq = 2417,
97 .hw_value = 2, .max_power = 30 },
98 { .band = NL80211_BAND_2GHZ, .center_freq = 2422,
99 .hw_value = 3, .max_power = 30 },
100 { .band = NL80211_BAND_2GHZ, .center_freq = 2427,
101 .hw_value = 4, .max_power = 30 },
102 { .band = NL80211_BAND_2GHZ, .center_freq = 2432,
103 .hw_value = 5, .max_power = 30 },
104 { .band = NL80211_BAND_2GHZ, .center_freq = 2437,
105 .hw_value = 6, .max_power = 30 },
106 { .band = NL80211_BAND_2GHZ, .center_freq = 2442,
107 .hw_value = 7, .max_power = 30 },
108 { .band = NL80211_BAND_2GHZ, .center_freq = 2447,
109 .hw_value = 8, .max_power = 30 },
110 { .band = NL80211_BAND_2GHZ, .center_freq = 2452,
111 .hw_value = 9, .max_power = 30 },
112 { .band = NL80211_BAND_2GHZ, .center_freq = 2457,
113 .hw_value = 10, .max_power = 30 },
114 { .band = NL80211_BAND_2GHZ, .center_freq = 2462,
115 .hw_value = 11, .max_power = 30 },
116 { .band = NL80211_BAND_2GHZ, .center_freq = 2467,
117 .hw_value = 12, .max_power = 30 },
118 { .band = NL80211_BAND_2GHZ, .center_freq = 2472,
119 .hw_value = 13, .max_power = 30 },
120 { .band = NL80211_BAND_2GHZ, .center_freq = 2484,
121 .hw_value = 14, .max_power = 30 }
122 };
123
124 static struct ieee80211_supported_band rtl8xxxu_supported_band = {
125 .channels = rtl8xxxu_channels_2g,
126 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
127 .bitrates = rtl8xxxu_rates,
128 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
129 };
130
131 static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = {
132 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
133 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
134 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
135 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
136 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
137 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
138 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
139 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
140 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
141 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
142 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
143 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
144 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
145 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
146 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
147 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
148 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
149 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
150 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
151 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
152 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
153 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
154 };
155
156 static struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = {
157 {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0},
158 {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10},
159 {0x430, 0x00}, {0x431, 0x00},
160 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
161 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
162 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
163 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
164 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
165 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
166 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
167 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
168 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
169 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
170 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
171 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
172 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
173 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
174 {0x516, 0x0a}, {0x525, 0x4f},
175 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50},
176 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
177 {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff},
178 {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff},
179 {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
180 {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00},
181 {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
182 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
183 {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04},
184 {0xffff, 0xff},
185 };
186
187 static struct rtl8xxxu_reg8val rtl8192e_mac_init_table[] = {
188 {0x011, 0xeb}, {0x012, 0x07}, {0x014, 0x75}, {0x303, 0xa7},
189 {0x428, 0x0a}, {0x429, 0x10}, {0x430, 0x00}, {0x431, 0x00},
190 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
191 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
192 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
193 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
194 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
195 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
196 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
197 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
198 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, {0x4cd, 0xff},
199 {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, {0x502, 0x2f},
200 {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, {0x506, 0x5e},
201 {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, {0x50a, 0x5e},
202 {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, {0x50e, 0x00},
203 {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, {0x516, 0x0a},
204 {0x525, 0x4f}, {0x540, 0x12}, {0x541, 0x64}, {0x550, 0x10},
205 {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50}, {0x55d, 0xff},
206 {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, {0x620, 0xff},
207 {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff}, {0x624, 0xff},
208 {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff}, {0x638, 0x50},
209 {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, {0x63f, 0x0e},
210 {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xc8},
211 {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65},
212 {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, {0x70a, 0x65},
213 {0x70b, 0x87},
214 {0xffff, 0xff},
215 };
216
217 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
218 {0x800, 0x80040000}, {0x804, 0x00000003},
219 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
220 {0x810, 0x10001331}, {0x814, 0x020c3d10},
221 {0x818, 0x02200385}, {0x81c, 0x00000000},
222 {0x820, 0x01000100}, {0x824, 0x00390004},
223 {0x828, 0x00000000}, {0x82c, 0x00000000},
224 {0x830, 0x00000000}, {0x834, 0x00000000},
225 {0x838, 0x00000000}, {0x83c, 0x00000000},
226 {0x840, 0x00010000}, {0x844, 0x00000000},
227 {0x848, 0x00000000}, {0x84c, 0x00000000},
228 {0x850, 0x00000000}, {0x854, 0x00000000},
229 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
230 {0x860, 0x66f60110}, {0x864, 0x061f0130},
231 {0x868, 0x00000000}, {0x86c, 0x32323200},
232 {0x870, 0x07000760}, {0x874, 0x22004000},
233 {0x878, 0x00000808}, {0x87c, 0x00000000},
234 {0x880, 0xc0083070}, {0x884, 0x000004d5},
235 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
236 {0x890, 0x00000800}, {0x894, 0xfffffffe},
237 {0x898, 0x40302010}, {0x89c, 0x00706050},
238 {0x900, 0x00000000}, {0x904, 0x00000023},
239 {0x908, 0x00000000}, {0x90c, 0x81121111},
240 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
241 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
242 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
243 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
244 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
245 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
246 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
247 {0xa78, 0x00000900},
248 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
249 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
250 {0xc10, 0x08800000}, {0xc14, 0x40000100},
251 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
252 {0xc20, 0x00000000}, {0xc24, 0x00000000},
253 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
254 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
255 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
256 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
257 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
258 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
259 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
260 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
261 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
262 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
263 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
264 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
265 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
266 {0xc90, 0x00121820}, {0xc94, 0x00000000},
267 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
268 {0xca0, 0x00000000}, {0xca4, 0x00000080},
269 {0xca8, 0x00000000}, {0xcac, 0x00000000},
270 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
271 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
272 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
273 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
274 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
275 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
276 {0xce0, 0x00222222}, {0xce4, 0x00000000},
277 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
278 {0xd00, 0x00080740}, {0xd04, 0x00020401},
279 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
280 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
281 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
282 {0xd30, 0x00000000}, {0xd34, 0x80608000},
283 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
284 {0xd40, 0x00000000}, {0xd44, 0x00000000},
285 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
286 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
287 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
288 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
289 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
290 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
291 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
292 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
293 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
294 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
295 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
296 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
297 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
298 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
299 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
300 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
301 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
302 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
303 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
304 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
305 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
306 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
307 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
308 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
309 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
310 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
311 {0xf00, 0x00000300},
312 {0xffff, 0xffffffff},
313 };
314
315 static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = {
316 {0x800, 0x80040000}, {0x804, 0x00000003},
317 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
318 {0x810, 0x10001331}, {0x814, 0x020c3d10},
319 {0x818, 0x02200385}, {0x81c, 0x00000000},
320 {0x820, 0x01000100}, {0x824, 0x00190204},
321 {0x828, 0x00000000}, {0x82c, 0x00000000},
322 {0x830, 0x00000000}, {0x834, 0x00000000},
323 {0x838, 0x00000000}, {0x83c, 0x00000000},
324 {0x840, 0x00010000}, {0x844, 0x00000000},
325 {0x848, 0x00000000}, {0x84c, 0x00000000},
326 {0x850, 0x00000000}, {0x854, 0x00000000},
327 {0x858, 0x569a11a9}, {0x85c, 0x01000014},
328 {0x860, 0x66f60110}, {0x864, 0x061f0649},
329 {0x868, 0x00000000}, {0x86c, 0x27272700},
330 {0x870, 0x07000760}, {0x874, 0x25004000},
331 {0x878, 0x00000808}, {0x87c, 0x00000000},
332 {0x880, 0xb0000c1c}, {0x884, 0x00000001},
333 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
334 {0x890, 0x00000800}, {0x894, 0xfffffffe},
335 {0x898, 0x40302010}, {0x89c, 0x00706050},
336 {0x900, 0x00000000}, {0x904, 0x00000023},
337 {0x908, 0x00000000}, {0x90c, 0x81121111},
338 {0x910, 0x00000002}, {0x914, 0x00000201},
339 {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},
340 {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},
341 {0xa10, 0x9500bb78}, {0xa14, 0x1114d028},
342 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
343 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
344 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
345 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
346 {0xa78, 0x00000900}, {0xa7c, 0x225b0606},
347 {0xa80, 0x21806490}, {0xb2c, 0x00000000},
348 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
349 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
350 {0xc10, 0x08800000}, {0xc14, 0x40000100},
351 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
352 {0xc20, 0x00000000}, {0xc24, 0x00000000},
353 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
354 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
355 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
356 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
357 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
358 {0xc50, 0x69553420}, {0xc54, 0x43bc0094},
359 {0xc58, 0x00013149}, {0xc5c, 0x00250492},
360 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
361 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
362 {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},
363 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
364 {0xc80, 0x390000e4}, {0xc84, 0x20f60000},
365 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
366 {0xc90, 0x00020e1a}, {0xc94, 0x00000000},
367 {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f},
368 {0xca0, 0x00000000}, {0xca4, 0x000300a0},
369 {0xca8, 0x00000000}, {0xcac, 0x00000000},
370 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
371 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
372 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
373 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
374 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
375 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
376 {0xce0, 0x00222222}, {0xce4, 0x00000000},
377 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
378 {0xd00, 0x00000740}, {0xd04, 0x40020401},
379 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
380 {0xd10, 0xa0633333}, {0xd14, 0x3333bc53},
381 {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},
382 {0xd30, 0x00000000}, {0xd34, 0x80608000},
383 {0xd38, 0x00000000}, {0xd3c, 0x00127353},
384 {0xd40, 0x00000000}, {0xd44, 0x00000000},
385 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
386 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
387 {0xd58, 0x00000282}, {0xd5c, 0x30032064},
388 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
389 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
390 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
391 {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},
392 {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},
393 {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},
394 {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},
395 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
396 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
397 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
398 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
399 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
400 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
401 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
402 {0xe68, 0x001b2556}, {0xe6c, 0x00c00096},
403 {0xe70, 0x00c00096}, {0xe74, 0x01000056},
404 {0xe78, 0x01000014}, {0xe7c, 0x01000056},
405 {0xe80, 0x01000014}, {0xe84, 0x00c00096},
406 {0xe88, 0x01000056}, {0xe8c, 0x00c00096},
407 {0xed0, 0x00c00096}, {0xed4, 0x00c00096},
408 {0xed8, 0x00c00096}, {0xedc, 0x000000d6},
409 {0xee0, 0x000000d6}, {0xeec, 0x01c00016},
410 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
411 {0xf00, 0x00000300},
412 {0x820, 0x01000100}, {0x800, 0x83040000},
413 {0xffff, 0xffffffff},
414 };
415
416 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
417 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
418 {0x800, 0x80040002}, {0x804, 0x00000003},
419 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
420 {0x810, 0x10000330}, {0x814, 0x020c3d10},
421 {0x818, 0x02200385}, {0x81c, 0x00000000},
422 {0x820, 0x01000100}, {0x824, 0x00390004},
423 {0x828, 0x01000100}, {0x82c, 0x00390004},
424 {0x830, 0x27272727}, {0x834, 0x27272727},
425 {0x838, 0x27272727}, {0x83c, 0x27272727},
426 {0x840, 0x00010000}, {0x844, 0x00010000},
427 {0x848, 0x27272727}, {0x84c, 0x27272727},
428 {0x850, 0x00000000}, {0x854, 0x00000000},
429 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
430 {0x860, 0x66e60230}, {0x864, 0x061f0130},
431 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
432 {0x870, 0x07000700}, {0x874, 0x22184000},
433 {0x878, 0x08080808}, {0x87c, 0x00000000},
434 {0x880, 0xc0083070}, {0x884, 0x000004d5},
435 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
436 {0x890, 0x00000800}, {0x894, 0xfffffffe},
437 {0x898, 0x40302010}, {0x89c, 0x00706050},
438 {0x900, 0x00000000}, {0x904, 0x00000023},
439 {0x908, 0x00000000}, {0x90c, 0x81121313},
440 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
441 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
442 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
443 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
444 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
445 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
446 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
447 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
448 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
449 {0xc10, 0x08800000}, {0xc14, 0x40000100},
450 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
451 {0xc20, 0x00000000}, {0xc24, 0x00000000},
452 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
453 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
454 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
455 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
456 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
457 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
458 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
459 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
460 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
461 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
462 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
463 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
464 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
465 {0xc90, 0x00121820}, {0xc94, 0x00000000},
466 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
467 {0xca0, 0x00000000}, {0xca4, 0x00000080},
468 {0xca8, 0x00000000}, {0xcac, 0x00000000},
469 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
470 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
471 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
472 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
473 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
474 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
475 {0xce0, 0x00222222}, {0xce4, 0x00000000},
476 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
477 {0xd00, 0x00080740}, {0xd04, 0x00020403},
478 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
479 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
480 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
481 {0xd30, 0x00000000}, {0xd34, 0x80608000},
482 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
483 {0xd40, 0x00000000}, {0xd44, 0x00000000},
484 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
485 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
486 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
487 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
488 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
489 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
490 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
491 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
492 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
493 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
494 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
495 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
496 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
497 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
498 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
499 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
500 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
501 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
502 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
503 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
504 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
505 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
506 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
507 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
508 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
509 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
510 {0xf00, 0x00000300},
511 {0xffff, 0xffffffff},
512 };
513
514 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
515 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
516 {0x040, 0x000c0004}, {0x800, 0x80040000},
517 {0x804, 0x00000001}, {0x808, 0x0000fc00},
518 {0x80c, 0x0000000a}, {0x810, 0x10005388},
519 {0x814, 0x020c3d10}, {0x818, 0x02200385},
520 {0x81c, 0x00000000}, {0x820, 0x01000100},
521 {0x824, 0x00390204}, {0x828, 0x00000000},
522 {0x82c, 0x00000000}, {0x830, 0x00000000},
523 {0x834, 0x00000000}, {0x838, 0x00000000},
524 {0x83c, 0x00000000}, {0x840, 0x00010000},
525 {0x844, 0x00000000}, {0x848, 0x00000000},
526 {0x84c, 0x00000000}, {0x850, 0x00000000},
527 {0x854, 0x00000000}, {0x858, 0x569a569a},
528 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
529 {0x864, 0x061f0130}, {0x868, 0x00000000},
530 {0x86c, 0x20202000}, {0x870, 0x03000300},
531 {0x874, 0x22004000}, {0x878, 0x00000808},
532 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
533 {0x884, 0x000004d5}, {0x888, 0x00000000},
534 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
535 {0x894, 0xfffffffe}, {0x898, 0x40302010},
536 {0x89c, 0x00706050}, {0x900, 0x00000000},
537 {0x904, 0x00000023}, {0x908, 0x00000000},
538 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
539 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
540 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
541 {0xa14, 0x11144028}, {0xa18, 0x00881117},
542 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
543 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
544 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
545 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
546 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
547 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
548 {0xc14, 0x40000100}, {0xc18, 0x08800000},
549 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
550 {0xc24, 0x00000000}, {0xc28, 0x00000000},
551 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
552 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
553 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
554 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
555 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
556 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
557 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
558 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
559 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
560 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
561 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
562 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
563 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
564 {0xc94, 0x00000000}, {0xc98, 0x00121820},
565 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
566 {0xca4, 0x00000080}, {0xca8, 0x00000000},
567 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
568 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
569 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
570 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
571 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
572 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
573 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
574 {0xce4, 0x00000000}, {0xce8, 0x37644302},
575 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
576 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
577 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
578 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
579 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
580 {0xd34, 0x80608000}, {0xd38, 0x00000000},
581 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
582 {0xd44, 0x00000000}, {0xd48, 0x00000000},
583 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
584 {0xd54, 0x00000000}, {0xd58, 0x00000000},
585 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
586 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
587 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
588 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
589 {0xe00, 0x24242424}, {0xe04, 0x24242424},
590 {0xe08, 0x03902024}, {0xe10, 0x24242424},
591 {0xe14, 0x24242424}, {0xe18, 0x24242424},
592 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
593 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
594 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
595 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
596 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
597 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
598 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
599 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
600 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
601 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
602 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
603 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
604 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
605 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
606 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
607 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
608 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
609 {0xf00, 0x00000300},
610 {0xffff, 0xffffffff},
611 };
612
613 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
614 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
615 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
616 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
617 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
618 {0xc78, 0x78080001}, {0xc78, 0x77090001},
619 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
620 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
621 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
622 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
623 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
624 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
625 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
626 {0xc78, 0x68180001}, {0xc78, 0x67190001},
627 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
628 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
629 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
630 {0xc78, 0x60200001}, {0xc78, 0x49210001},
631 {0xc78, 0x48220001}, {0xc78, 0x47230001},
632 {0xc78, 0x46240001}, {0xc78, 0x45250001},
633 {0xc78, 0x44260001}, {0xc78, 0x43270001},
634 {0xc78, 0x42280001}, {0xc78, 0x41290001},
635 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
636 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
637 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
638 {0xc78, 0x21300001}, {0xc78, 0x20310001},
639 {0xc78, 0x06320001}, {0xc78, 0x05330001},
640 {0xc78, 0x04340001}, {0xc78, 0x03350001},
641 {0xc78, 0x02360001}, {0xc78, 0x01370001},
642 {0xc78, 0x00380001}, {0xc78, 0x00390001},
643 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
644 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
645 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
646 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
647 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
648 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
649 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
650 {0xc78, 0x78480001}, {0xc78, 0x77490001},
651 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
652 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
653 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
654 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
655 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
656 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
657 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
658 {0xc78, 0x68580001}, {0xc78, 0x67590001},
659 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
660 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
661 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
662 {0xc78, 0x60600001}, {0xc78, 0x49610001},
663 {0xc78, 0x48620001}, {0xc78, 0x47630001},
664 {0xc78, 0x46640001}, {0xc78, 0x45650001},
665 {0xc78, 0x44660001}, {0xc78, 0x43670001},
666 {0xc78, 0x42680001}, {0xc78, 0x41690001},
667 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
668 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
669 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
670 {0xc78, 0x21700001}, {0xc78, 0x20710001},
671 {0xc78, 0x06720001}, {0xc78, 0x05730001},
672 {0xc78, 0x04740001}, {0xc78, 0x03750001},
673 {0xc78, 0x02760001}, {0xc78, 0x01770001},
674 {0xc78, 0x00780001}, {0xc78, 0x00790001},
675 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
676 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
677 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
678 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
679 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
680 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
681 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
682 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
683 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
684 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
685 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
686 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
687 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
688 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
689 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
690 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
691 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
692 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
693 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
694 {0xffff, 0xffffffff}
695 };
696
697 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
698 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
699 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
700 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
701 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
702 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
703 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
704 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
705 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
706 {0xc78, 0x73100001}, {0xc78, 0x72110001},
707 {0xc78, 0x71120001}, {0xc78, 0x70130001},
708 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
709 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
710 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
711 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
712 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
713 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
714 {0xc78, 0x63200001}, {0xc78, 0x62210001},
715 {0xc78, 0x61220001}, {0xc78, 0x60230001},
716 {0xc78, 0x46240001}, {0xc78, 0x45250001},
717 {0xc78, 0x44260001}, {0xc78, 0x43270001},
718 {0xc78, 0x42280001}, {0xc78, 0x41290001},
719 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
720 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
721 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
722 {0xc78, 0x21300001}, {0xc78, 0x20310001},
723 {0xc78, 0x06320001}, {0xc78, 0x05330001},
724 {0xc78, 0x04340001}, {0xc78, 0x03350001},
725 {0xc78, 0x02360001}, {0xc78, 0x01370001},
726 {0xc78, 0x00380001}, {0xc78, 0x00390001},
727 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
728 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
729 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
730 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
731 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
732 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
733 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
734 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
735 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
736 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
737 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
738 {0xc78, 0x73500001}, {0xc78, 0x72510001},
739 {0xc78, 0x71520001}, {0xc78, 0x70530001},
740 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
741 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
742 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
743 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
744 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
745 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
746 {0xc78, 0x63600001}, {0xc78, 0x62610001},
747 {0xc78, 0x61620001}, {0xc78, 0x60630001},
748 {0xc78, 0x46640001}, {0xc78, 0x45650001},
749 {0xc78, 0x44660001}, {0xc78, 0x43670001},
750 {0xc78, 0x42680001}, {0xc78, 0x41690001},
751 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
752 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
753 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
754 {0xc78, 0x21700001}, {0xc78, 0x20710001},
755 {0xc78, 0x06720001}, {0xc78, 0x05730001},
756 {0xc78, 0x04740001}, {0xc78, 0x03750001},
757 {0xc78, 0x02760001}, {0xc78, 0x01770001},
758 {0xc78, 0x00780001}, {0xc78, 0x00790001},
759 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
760 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
761 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
762 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
763 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
764 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
765 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
766 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
767 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
768 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
769 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
770 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
771 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
772 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
773 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
774 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
775 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
776 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
777 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
778 {0xffff, 0xffffffff}
779 };
780
781 static struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = {
782 {0xc78, 0xfd000001}, {0xc78, 0xfc010001},
783 {0xc78, 0xfb020001}, {0xc78, 0xfa030001},
784 {0xc78, 0xf9040001}, {0xc78, 0xf8050001},
785 {0xc78, 0xf7060001}, {0xc78, 0xf6070001},
786 {0xc78, 0xf5080001}, {0xc78, 0xf4090001},
787 {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001},
788 {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001},
789 {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001},
790 {0xc78, 0xed100001}, {0xc78, 0xec110001},
791 {0xc78, 0xeb120001}, {0xc78, 0xea130001},
792 {0xc78, 0xe9140001}, {0xc78, 0xe8150001},
793 {0xc78, 0xe7160001}, {0xc78, 0xe6170001},
794 {0xc78, 0xe5180001}, {0xc78, 0xe4190001},
795 {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001},
796 {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001},
797 {0xc78, 0x671e0001}, {0xc78, 0x661f0001},
798 {0xc78, 0x65200001}, {0xc78, 0x64210001},
799 {0xc78, 0x63220001}, {0xc78, 0x4a230001},
800 {0xc78, 0x49240001}, {0xc78, 0x48250001},
801 {0xc78, 0x47260001}, {0xc78, 0x46270001},
802 {0xc78, 0x45280001}, {0xc78, 0x44290001},
803 {0xc78, 0x432a0001}, {0xc78, 0x422b0001},
804 {0xc78, 0x292c0001}, {0xc78, 0x282d0001},
805 {0xc78, 0x272e0001}, {0xc78, 0x262f0001},
806 {0xc78, 0x0a300001}, {0xc78, 0x09310001},
807 {0xc78, 0x08320001}, {0xc78, 0x07330001},
808 {0xc78, 0x06340001}, {0xc78, 0x05350001},
809 {0xc78, 0x04360001}, {0xc78, 0x03370001},
810 {0xc78, 0x02380001}, {0xc78, 0x01390001},
811 {0xc78, 0x013a0001}, {0xc78, 0x013b0001},
812 {0xc78, 0x013c0001}, {0xc78, 0x013d0001},
813 {0xc78, 0x013e0001}, {0xc78, 0x013f0001},
814 {0xc78, 0xfc400001}, {0xc78, 0xfb410001},
815 {0xc78, 0xfa420001}, {0xc78, 0xf9430001},
816 {0xc78, 0xf8440001}, {0xc78, 0xf7450001},
817 {0xc78, 0xf6460001}, {0xc78, 0xf5470001},
818 {0xc78, 0xf4480001}, {0xc78, 0xf3490001},
819 {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001},
820 {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001},
821 {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001},
822 {0xc78, 0xec500001}, {0xc78, 0xeb510001},
823 {0xc78, 0xea520001}, {0xc78, 0xe9530001},
824 {0xc78, 0xe8540001}, {0xc78, 0xe7550001},
825 {0xc78, 0xe6560001}, {0xc78, 0xe5570001},
826 {0xc78, 0xe4580001}, {0xc78, 0xe3590001},
827 {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001},
828 {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001},
829 {0xc78, 0x675e0001}, {0xc78, 0x665f0001},
830 {0xc78, 0x65600001}, {0xc78, 0x64610001},
831 {0xc78, 0x63620001}, {0xc78, 0x62630001},
832 {0xc78, 0x61640001}, {0xc78, 0x48650001},
833 {0xc78, 0x47660001}, {0xc78, 0x46670001},
834 {0xc78, 0x45680001}, {0xc78, 0x44690001},
835 {0xc78, 0x436a0001}, {0xc78, 0x426b0001},
836 {0xc78, 0x286c0001}, {0xc78, 0x276d0001},
837 {0xc78, 0x266e0001}, {0xc78, 0x256f0001},
838 {0xc78, 0x24700001}, {0xc78, 0x09710001},
839 {0xc78, 0x08720001}, {0xc78, 0x07730001},
840 {0xc78, 0x06740001}, {0xc78, 0x05750001},
841 {0xc78, 0x04760001}, {0xc78, 0x03770001},
842 {0xc78, 0x02780001}, {0xc78, 0x01790001},
843 {0xc78, 0x017a0001}, {0xc78, 0x017b0001},
844 {0xc78, 0x017c0001}, {0xc78, 0x017d0001},
845 {0xc78, 0x017e0001}, {0xc78, 0x017f0001},
846 {0xc50, 0x69553422},
847 {0xc50, 0x69553420},
848 {0x824, 0x00390204},
849 {0xffff, 0xffffffff}
850 };
851
852 static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
853 {0x00, 0x00030159}, {0x01, 0x00031284},
854 {0x02, 0x00098000}, {0x03, 0x00039c63},
855 {0x04, 0x000210e7}, {0x09, 0x0002044f},
856 {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
857 {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
858 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
859 {0x19, 0x00000000}, {0x1a, 0x00030355},
860 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
861 {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
862 {0x1f, 0x00000000}, {0x20, 0x0000b614},
863 {0x21, 0x0006c000}, {0x22, 0x00000000},
864 {0x23, 0x00001558}, {0x24, 0x00000060},
865 {0x25, 0x00000483}, {0x26, 0x0004f000},
866 {0x27, 0x000ec7d9}, {0x28, 0x00057730},
867 {0x29, 0x00004783}, {0x2a, 0x00000001},
868 {0x2b, 0x00021334}, {0x2a, 0x00000000},
869 {0x2b, 0x00000054}, {0x2a, 0x00000001},
870 {0x2b, 0x00000808}, {0x2b, 0x00053333},
871 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
872 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
873 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
874 {0x2b, 0x00000808}, {0x2b, 0x00063333},
875 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
876 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
877 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
878 {0x2b, 0x00000808}, {0x2b, 0x00073333},
879 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
880 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
881 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
882 {0x2b, 0x00000709}, {0x2b, 0x00063333},
883 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
884 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
885 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
886 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
887 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
888 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
889 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
890 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
891 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
892 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
893 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
894 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
895 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
896 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
897 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
898 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
899 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
900 {0x10, 0x0002000f}, {0x11, 0x000203f9},
901 {0x10, 0x0003000f}, {0x11, 0x000ff500},
902 {0x10, 0x00000000}, {0x11, 0x00000000},
903 {0x10, 0x0008000f}, {0x11, 0x0003f100},
904 {0x10, 0x0009000f}, {0x11, 0x00023100},
905 {0x12, 0x00032000}, {0x12, 0x00071000},
906 {0x12, 0x000b0000}, {0x12, 0x000fc000},
907 {0x13, 0x000287b3}, {0x13, 0x000244b7},
908 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
909 {0x13, 0x00018493}, {0x13, 0x0001429b},
910 {0x13, 0x00010299}, {0x13, 0x0000c29c},
911 {0x13, 0x000081a0}, {0x13, 0x000040ac},
912 {0x13, 0x00000020}, {0x14, 0x0001944c},
913 {0x14, 0x00059444}, {0x14, 0x0009944c},
914 {0x14, 0x000d9444}, {0x15, 0x0000f474},
915 {0x15, 0x0004f477}, {0x15, 0x0008f455},
916 {0x15, 0x000cf455}, {0x16, 0x00000339},
917 {0x16, 0x00040339}, {0x16, 0x00080339},
918 {0x16, 0x000c0366}, {0x00, 0x00010159},
919 {0x18, 0x0000f401}, {0xfe, 0x00000000},
920 {0xfe, 0x00000000}, {0x1f, 0x00000003},
921 {0xfe, 0x00000000}, {0xfe, 0x00000000},
922 {0x1e, 0x00000247}, {0x1f, 0x00000000},
923 {0x00, 0x00030159},
924 {0xff, 0xffffffff}
925 };
926
927 static struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = {
928 {0x00, 0x00010000}, {0xb0, 0x000dffe0},
929 {0xfe, 0x00000000}, {0xfe, 0x00000000},
930 {0xfe, 0x00000000}, {0xb1, 0x00000018},
931 {0xfe, 0x00000000}, {0xfe, 0x00000000},
932 {0xfe, 0x00000000}, {0xb2, 0x00084c00},
933 {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa},
934 {0xb7, 0x00000010}, {0xb8, 0x0000907f},
935 {0x5c, 0x00000002}, {0x7c, 0x00000002},
936 {0x7e, 0x00000005}, {0x8b, 0x0006fc00},
937 {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2},
938 {0x1e, 0x00000000}, {0xdf, 0x00000780},
939 {0x50, 0x00067435},
940 /*
941 * The 8723bu vendor driver indicates that bit 8 should be set in
942 * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However
943 * they never actually check the package type - and just default
944 * to not setting it.
945 */
946 {0x51, 0x0006b04e},
947 {0x52, 0x000007d2}, {0x53, 0x00000000},
948 {0x54, 0x00050400}, {0x55, 0x0004026e},
949 {0xdd, 0x0000004c}, {0x70, 0x00067435},
950 /*
951 * 0x71 has same package type condition as for register 0x51
952 */
953 {0x71, 0x0006b04e},
954 {0x72, 0x000007d2}, {0x73, 0x00000000},
955 {0x74, 0x00050400}, {0x75, 0x0004026e},
956 {0xef, 0x00000100}, {0x34, 0x0000add7},
957 {0x35, 0x00005c00}, {0x34, 0x00009dd4},
958 {0x35, 0x00005000}, {0x34, 0x00008dd1},
959 {0x35, 0x00004400}, {0x34, 0x00007dce},
960 {0x35, 0x00003800}, {0x34, 0x00006cd1},
961 {0x35, 0x00004400}, {0x34, 0x00005cce},
962 {0x35, 0x00003800}, {0x34, 0x000048ce},
963 {0x35, 0x00004400}, {0x34, 0x000034ce},
964 {0x35, 0x00003800}, {0x34, 0x00002451},
965 {0x35, 0x00004400}, {0x34, 0x0000144e},
966 {0x35, 0x00003800}, {0x34, 0x00000051},
967 {0x35, 0x00004400}, {0xef, 0x00000000},
968 {0xef, 0x00000100}, {0xed, 0x00000010},
969 {0x44, 0x0000add7}, {0x44, 0x00009dd4},
970 {0x44, 0x00008dd1}, {0x44, 0x00007dce},
971 {0x44, 0x00006cc1}, {0x44, 0x00005cce},
972 {0x44, 0x000044d1}, {0x44, 0x000034ce},
973 {0x44, 0x00002451}, {0x44, 0x0000144e},
974 {0x44, 0x00000051}, {0xef, 0x00000000},
975 {0xed, 0x00000000}, {0x7f, 0x00020080},
976 {0xef, 0x00002000}, {0x3b, 0x000380ef},
977 {0x3b, 0x000302fe}, {0x3b, 0x00028ce6},
978 {0x3b, 0x000200bc}, {0x3b, 0x000188a5},
979 {0x3b, 0x00010fbc}, {0x3b, 0x00008f71},
980 {0x3b, 0x00000900}, {0xef, 0x00000000},
981 {0xed, 0x00000001}, {0x40, 0x000380ef},
982 {0x40, 0x000302fe}, {0x40, 0x00028ce6},
983 {0x40, 0x000200bc}, {0x40, 0x000188a5},
984 {0x40, 0x00010fbc}, {0x40, 0x00008f71},
985 {0x40, 0x00000900}, {0xed, 0x00000000},
986 {0x82, 0x00080000}, {0x83, 0x00008000},
987 {0x84, 0x00048d80}, {0x85, 0x00068000},
988 {0xa2, 0x00080000}, {0xa3, 0x00008000},
989 {0xa4, 0x00048d80}, {0xa5, 0x00068000},
990 {0xed, 0x00000002}, {0xef, 0x00000002},
991 {0x56, 0x00000032}, {0x76, 0x00000032},
992 {0x01, 0x00000780},
993 {0xff, 0xffffffff}
994 };
995
996 static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
997 {0x00, 0x00030159}, {0x01, 0x00031284},
998 {0x02, 0x00098000}, {0x03, 0x00018c63},
999 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1000 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1001 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1002 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1003 {0x19, 0x00000000}, {0x1a, 0x00010255},
1004 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1005 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1006 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1007 {0x21, 0x0006c000}, {0x22, 0x00000000},
1008 {0x23, 0x00001558}, {0x24, 0x00000060},
1009 {0x25, 0x00000483}, {0x26, 0x0004f000},
1010 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1011 {0x29, 0x00004783}, {0x2a, 0x00000001},
1012 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1013 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1014 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1015 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1016 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1017 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1018 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1019 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1020 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1021 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1022 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1023 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1024 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1025 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1026 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1027 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1028 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1029 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1030 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1031 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1032 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1033 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1034 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1035 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1036 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1037 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1038 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1039 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1040 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1041 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1042 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1043 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1044 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1045 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1046 {0x10, 0x00000000}, {0x11, 0x00000000},
1047 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1048 {0x10, 0x0009000f}, {0x11, 0x00023100},
1049 {0x12, 0x00032000}, {0x12, 0x00071000},
1050 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1051 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1052 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1053 {0x13, 0x00018493}, {0x13, 0x0001429b},
1054 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1055 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1056 {0x13, 0x00000020}, {0x14, 0x0001944c},
1057 {0x14, 0x00059444}, {0x14, 0x0009944c},
1058 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1059 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1060 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1061 {0x16, 0x000a0330}, {0x16, 0x00060330},
1062 {0x16, 0x00020330}, {0x00, 0x00010159},
1063 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1064 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1065 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1066 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1067 {0x00, 0x00030159},
1068 {0xff, 0xffffffff}
1069 };
1070
1071 static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
1072 {0x00, 0x00030159}, {0x01, 0x00031284},
1073 {0x02, 0x00098000}, {0x03, 0x00018c63},
1074 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1075 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1076 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1077 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1078 {0x12, 0x00032000}, {0x12, 0x00071000},
1079 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1080 {0x13, 0x000287af}, {0x13, 0x000244b7},
1081 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1082 {0x13, 0x00018493}, {0x13, 0x00014297},
1083 {0x13, 0x00010295}, {0x13, 0x0000c298},
1084 {0x13, 0x0000819c}, {0x13, 0x000040a8},
1085 {0x13, 0x0000001c}, {0x14, 0x0001944c},
1086 {0x14, 0x00059444}, {0x14, 0x0009944c},
1087 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1088 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1089 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1090 {0x16, 0x000a0330}, {0x16, 0x00060330},
1091 {0x16, 0x00020330},
1092 {0xff, 0xffffffff}
1093 };
1094
1095 static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
1096 {0x00, 0x00030159}, {0x01, 0x00031284},
1097 {0x02, 0x00098000}, {0x03, 0x00018c63},
1098 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1099 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1100 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1101 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1102 {0x19, 0x00000000}, {0x1a, 0x00010255},
1103 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1104 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1105 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1106 {0x21, 0x0006c000}, {0x22, 0x00000000},
1107 {0x23, 0x00001558}, {0x24, 0x00000060},
1108 {0x25, 0x00000483}, {0x26, 0x0004f000},
1109 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1110 {0x29, 0x00004783}, {0x2a, 0x00000001},
1111 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1112 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1113 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1114 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1115 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1116 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1117 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1118 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1119 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1120 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1121 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1122 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1123 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1124 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1125 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1126 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1127 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1128 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1129 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1130 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1131 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1132 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1133 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1134 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1135 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1136 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1137 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1138 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1139 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1140 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1141 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1142 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1143 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1144 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1145 {0x10, 0x00000000}, {0x11, 0x00000000},
1146 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1147 {0x10, 0x0009000f}, {0x11, 0x00023100},
1148 {0x12, 0x00032000}, {0x12, 0x00071000},
1149 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1150 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1151 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1152 {0x13, 0x00018493}, {0x13, 0x0001429b},
1153 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1154 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1155 {0x13, 0x00000020}, {0x14, 0x0001944c},
1156 {0x14, 0x00059444}, {0x14, 0x0009944c},
1157 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1158 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1159 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1160 {0x16, 0x000a0330}, {0x16, 0x00060330},
1161 {0x16, 0x00020330}, {0x00, 0x00010159},
1162 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1163 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1164 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1165 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1166 {0x00, 0x00030159},
1167 {0xff, 0xffffffff}
1168 };
1169
1170 static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
1171 {0x00, 0x00030159}, {0x01, 0x00031284},
1172 {0x02, 0x00098000}, {0x03, 0x00018c63},
1173 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1174 {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
1175 {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
1176 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1177 {0x19, 0x00000000}, {0x1a, 0x00000255},
1178 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1179 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1180 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1181 {0x21, 0x0006c000}, {0x22, 0x0000083c},
1182 {0x23, 0x00001558}, {0x24, 0x00000060},
1183 {0x25, 0x00000483}, {0x26, 0x0004f000},
1184 {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
1185 {0x29, 0x00004783}, {0x2a, 0x00000001},
1186 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1187 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1188 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1189 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1190 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1191 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1192 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1193 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1194 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1195 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1196 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1197 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1198 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1199 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1200 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1201 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1202 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1203 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1204 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1205 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1206 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1207 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1208 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1209 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1210 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1211 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1212 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1213 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1214 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1215 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1216 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1217 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1218 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1219 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1220 {0x10, 0x00000000}, {0x11, 0x00000000},
1221 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1222 {0x10, 0x0009000f}, {0x11, 0x00023100},
1223 {0x12, 0x000d8000}, {0x12, 0x00090000},
1224 {0x12, 0x00051000}, {0x12, 0x00012000},
1225 {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
1226 {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
1227 {0x13, 0x000183a4}, {0x13, 0x00014398},
1228 {0x13, 0x000101a4}, {0x13, 0x0000c198},
1229 {0x13, 0x000080a4}, {0x13, 0x00004098},
1230 {0x13, 0x00000000}, {0x14, 0x0001944c},
1231 {0x14, 0x00059444}, {0x14, 0x0009944c},
1232 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1233 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1234 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1235 {0x16, 0x000a0330}, {0x16, 0x00060330},
1236 {0x16, 0x00020330}, {0x00, 0x00010159},
1237 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1238 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1239 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1240 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1241 {0x00, 0x00030159},
1242 {0xff, 0xffffffff}
1243 };
1244
1245 static struct rtl8xxxu_rfregval rtl8192eu_radioa_init_table[] = {
1246 {0x7f, 0x00000082}, {0x81, 0x0003fc00},
1247 {0x00, 0x00030000}, {0x08, 0x00008400},
1248 {0x18, 0x00000407}, {0x19, 0x00000012},
1249 {0x1b, 0x00000064}, {0x1e, 0x00080009},
1250 {0x1f, 0x00000880}, {0x2f, 0x0001a060},
1251 {0x3f, 0x00000000}, {0x42, 0x000060c0},
1252 {0x57, 0x000d0000}, {0x58, 0x000be180},
1253 {0x67, 0x00001552}, {0x83, 0x00000000},
1254 {0xb0, 0x000ff9f1}, {0xb1, 0x00055418},
1255 {0xb2, 0x0008cc00}, {0xb4, 0x00043083},
1256 {0xb5, 0x00008166}, {0xb6, 0x0000803e},
1257 {0xb7, 0x0001c69f}, {0xb8, 0x0000407f},
1258 {0xb9, 0x00080001}, {0xba, 0x00040001},
1259 {0xbb, 0x00000400}, {0xbf, 0x000c0000},
1260 {0xc2, 0x00002400}, {0xc3, 0x00000009},
1261 {0xc4, 0x00040c91}, {0xc5, 0x00099999},
1262 {0xc6, 0x000000a3}, {0xc7, 0x00088820},
1263 {0xc8, 0x00076c06}, {0xc9, 0x00000000},
1264 {0xca, 0x00080000}, {0xdf, 0x00000180},
1265 {0xef, 0x000001a0}, {0x51, 0x00069545},
1266 {0x52, 0x0007e45e}, {0x53, 0x00000071},
1267 {0x56, 0x00051ff3}, {0x35, 0x000000a8},
1268 {0x35, 0x000001e2}, {0x35, 0x000002a8},
1269 {0x36, 0x00001c24}, {0x36, 0x00009c24},
1270 {0x36, 0x00011c24}, {0x36, 0x00019c24},
1271 {0x18, 0x00000c07}, {0x5a, 0x00048000},
1272 {0x19, 0x000739d0},
1273 #ifdef EXT_PA_8192EU
1274 /* External PA or external LNA */
1275 {0x34, 0x0000a093}, {0x34, 0x0000908f},
1276 {0x34, 0x0000808c}, {0x34, 0x0000704d},
1277 {0x34, 0x0000604a}, {0x34, 0x00005047},
1278 {0x34, 0x0000400a}, {0x34, 0x00003007},
1279 {0x34, 0x00002004}, {0x34, 0x00001001},
1280 {0x34, 0x00000000},
1281 #else
1282 /* Regular */
1283 {0x34, 0x0000add7}, {0x34, 0x00009dd4},
1284 {0x34, 0x00008dd1}, {0x34, 0x00007dce},
1285 {0x34, 0x00006dcb}, {0x34, 0x00005dc8},
1286 {0x34, 0x00004dc5}, {0x34, 0x000034cc},
1287 {0x34, 0x0000244f}, {0x34, 0x0000144c},
1288 {0x34, 0x00000014},
1289 #endif
1290 {0x00, 0x00030159},
1291 {0x84, 0x00068180},
1292 {0x86, 0x0000014e},
1293 {0x87, 0x00048e00},
1294 {0x8e, 0x00065540},
1295 {0x8f, 0x00088000},
1296 {0xef, 0x000020a0},
1297 #ifdef EXT_PA_8192EU
1298 /* External PA or external LNA */
1299 {0x3b, 0x000f07b0},
1300 #else
1301 {0x3b, 0x000f02b0},
1302 #endif
1303 {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0},
1304 {0x3b, 0x000cf060}, {0x3b, 0x000b0090},
1305 {0x3b, 0x000a0080}, {0x3b, 0x00090080},
1306 {0x3b, 0x0008f780},
1307 #ifdef EXT_PA_8192EU
1308 /* External PA or external LNA */
1309 {0x3b, 0x000787b0},
1310 #else
1311 {0x3b, 0x00078730},
1312 #endif
1313 {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0},
1314 {0x3b, 0x00040620}, {0x3b, 0x00037090},
1315 {0x3b, 0x00020080}, {0x3b, 0x0001f060},
1316 {0x3b, 0x0000ffb0}, {0xef, 0x000000a0},
1317 {0xfe, 0x00000000}, {0x18, 0x0000fc07},
1318 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1319 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1320 {0x1e, 0x00000001}, {0x1f, 0x00080000},
1321 {0x00, 0x00033e70},
1322 {0xff, 0xffffffff}
1323 };
1324
1325 static struct rtl8xxxu_rfregval rtl8192eu_radiob_init_table[] = {
1326 {0x7f, 0x00000082}, {0x81, 0x0003fc00},
1327 {0x00, 0x00030000}, {0x08, 0x00008400},
1328 {0x18, 0x00000407}, {0x19, 0x00000012},
1329 {0x1b, 0x00000064}, {0x1e, 0x00080009},
1330 {0x1f, 0x00000880}, {0x2f, 0x0001a060},
1331 {0x3f, 0x00000000}, {0x42, 0x000060c0},
1332 {0x57, 0x000d0000}, {0x58, 0x000be180},
1333 {0x67, 0x00001552}, {0x7f, 0x00000082},
1334 {0x81, 0x0003f000}, {0x83, 0x00000000},
1335 {0xdf, 0x00000180}, {0xef, 0x000001a0},
1336 {0x51, 0x00069545}, {0x52, 0x0007e42e},
1337 {0x53, 0x00000071}, {0x56, 0x00051ff3},
1338 {0x35, 0x000000a8}, {0x35, 0x000001e0},
1339 {0x35, 0x000002a8}, {0x36, 0x00001ca8},
1340 {0x36, 0x00009c24}, {0x36, 0x00011c24},
1341 {0x36, 0x00019c24}, {0x18, 0x00000c07},
1342 {0x5a, 0x00048000}, {0x19, 0x000739d0},
1343 #ifdef EXT_PA_8192EU
1344 /* External PA or external LNA */
1345 {0x34, 0x0000a093}, {0x34, 0x0000908f},
1346 {0x34, 0x0000808c}, {0x34, 0x0000704d},
1347 {0x34, 0x0000604a}, {0x34, 0x00005047},
1348 {0x34, 0x0000400a}, {0x34, 0x00003007},
1349 {0x34, 0x00002004}, {0x34, 0x00001001},
1350 {0x34, 0x00000000},
1351 #else
1352 {0x34, 0x0000add7}, {0x34, 0x00009dd4},
1353 {0x34, 0x00008dd1}, {0x34, 0x00007dce},
1354 {0x34, 0x00006dcb}, {0x34, 0x00005dc8},
1355 {0x34, 0x00004dc5}, {0x34, 0x000034cc},
1356 {0x34, 0x0000244f}, {0x34, 0x0000144c},
1357 {0x34, 0x00000014},
1358 #endif
1359 {0x00, 0x00030159}, {0x84, 0x00068180},
1360 {0x86, 0x000000ce}, {0x87, 0x00048a00},
1361 {0x8e, 0x00065540}, {0x8f, 0x00088000},
1362 {0xef, 0x000020a0},
1363 #ifdef EXT_PA_8192EU
1364 /* External PA or external LNA */
1365 {0x3b, 0x000f07b0},
1366 #else
1367 {0x3b, 0x000f02b0},
1368 #endif
1369
1370 {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0},
1371 {0x3b, 0x000cf060}, {0x3b, 0x000b0090},
1372 {0x3b, 0x000a0080}, {0x3b, 0x00090080},
1373 {0x3b, 0x0008f780},
1374 #ifdef EXT_PA_8192EU
1375 /* External PA or external LNA */
1376 {0x3b, 0x000787b0},
1377 #else
1378 {0x3b, 0x00078730},
1379 #endif
1380 {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0},
1381 {0x3b, 0x00040620}, {0x3b, 0x00037090},
1382 {0x3b, 0x00020080}, {0x3b, 0x0001f060},
1383 {0x3b, 0x0000ffb0}, {0xef, 0x000000a0},
1384 {0x00, 0x00010159}, {0xfe, 0x00000000},
1385 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1386 {0xfe, 0x00000000}, {0x1e, 0x00000001},
1387 {0x1f, 0x00080000}, {0x00, 0x00033e70},
1388 {0xff, 0xffffffff}
1389 };
1390
1391 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
1392 { /* RF_A */
1393 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
1394 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
1395 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
1396 .hspiread = REG_HSPI_XA_READBACK,
1397 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
1398 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
1399 },
1400 { /* RF_B */
1401 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
1402 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
1403 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
1404 .hspiread = REG_HSPI_XB_READBACK,
1405 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
1406 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
1407 },
1408 };
1409
1410 static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
1411 REG_OFDM0_XA_RX_IQ_IMBALANCE,
1412 REG_OFDM0_XB_RX_IQ_IMBALANCE,
1413 REG_OFDM0_ENERGY_CCA_THRES,
1414 REG_OFDM0_AGCR_SSI_TABLE,
1415 REG_OFDM0_XA_TX_IQ_IMBALANCE,
1416 REG_OFDM0_XB_TX_IQ_IMBALANCE,
1417 REG_OFDM0_XC_TX_AFE,
1418 REG_OFDM0_XD_TX_AFE,
1419 REG_OFDM0_RX_IQ_EXT_ANTA
1420 };
1421
1422 static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
1423 {
1424 struct usb_device *udev = priv->udev;
1425 int len;
1426 u8 data;
1427
1428 mutex_lock(&priv->usb_buf_mutex);
1429 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1430 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1431 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1432 RTW_USB_CONTROL_MSG_TIMEOUT);
1433 data = priv->usb_buf.val8;
1434 mutex_unlock(&priv->usb_buf_mutex);
1435
1436 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1437 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n",
1438 __func__, addr, data, len);
1439 return data;
1440 }
1441
1442 static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
1443 {
1444 struct usb_device *udev = priv->udev;
1445 int len;
1446 u16 data;
1447
1448 mutex_lock(&priv->usb_buf_mutex);
1449 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1450 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1451 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1452 RTW_USB_CONTROL_MSG_TIMEOUT);
1453 data = le16_to_cpu(priv->usb_buf.val16);
1454 mutex_unlock(&priv->usb_buf_mutex);
1455
1456 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1457 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n",
1458 __func__, addr, data, len);
1459 return data;
1460 }
1461
1462 static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
1463 {
1464 struct usb_device *udev = priv->udev;
1465 int len;
1466 u32 data;
1467
1468 mutex_lock(&priv->usb_buf_mutex);
1469 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1470 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1471 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1472 RTW_USB_CONTROL_MSG_TIMEOUT);
1473 data = le32_to_cpu(priv->usb_buf.val32);
1474 mutex_unlock(&priv->usb_buf_mutex);
1475
1476 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1477 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n",
1478 __func__, addr, data, len);
1479 return data;
1480 }
1481
1482 static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
1483 {
1484 struct usb_device *udev = priv->udev;
1485 int ret;
1486
1487 mutex_lock(&priv->usb_buf_mutex);
1488 priv->usb_buf.val8 = val;
1489 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1490 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1491 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1492 RTW_USB_CONTROL_MSG_TIMEOUT);
1493
1494 mutex_unlock(&priv->usb_buf_mutex);
1495
1496 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1497 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1498 __func__, addr, val);
1499 return ret;
1500 }
1501
1502 static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
1503 {
1504 struct usb_device *udev = priv->udev;
1505 int ret;
1506
1507 mutex_lock(&priv->usb_buf_mutex);
1508 priv->usb_buf.val16 = cpu_to_le16(val);
1509 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1510 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1511 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1512 RTW_USB_CONTROL_MSG_TIMEOUT);
1513 mutex_unlock(&priv->usb_buf_mutex);
1514
1515 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1516 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1517 __func__, addr, val);
1518 return ret;
1519 }
1520
1521 static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
1522 {
1523 struct usb_device *udev = priv->udev;
1524 int ret;
1525
1526 mutex_lock(&priv->usb_buf_mutex);
1527 priv->usb_buf.val32 = cpu_to_le32(val);
1528 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1529 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1530 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1531 RTW_USB_CONTROL_MSG_TIMEOUT);
1532 mutex_unlock(&priv->usb_buf_mutex);
1533
1534 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1535 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1536 __func__, addr, val);
1537 return ret;
1538 }
1539
1540 static int
1541 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1542 {
1543 struct usb_device *udev = priv->udev;
1544 int blocksize = priv->fops->writeN_block_size;
1545 int ret, i, count, remainder;
1546
1547 count = len / blocksize;
1548 remainder = len % blocksize;
1549
1550 for (i = 0; i < count; i++) {
1551 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1552 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1553 addr, 0, buf, blocksize,
1554 RTW_USB_CONTROL_MSG_TIMEOUT);
1555 if (ret != blocksize)
1556 goto write_error;
1557
1558 addr += blocksize;
1559 buf += blocksize;
1560 }
1561
1562 if (remainder) {
1563 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1564 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1565 addr, 0, buf, remainder,
1566 RTW_USB_CONTROL_MSG_TIMEOUT);
1567 if (ret != remainder)
1568 goto write_error;
1569 }
1570
1571 return len;
1572
1573 write_error:
1574 dev_info(&udev->dev,
1575 "%s: Failed to write block at addr: %04x size: %04x\n",
1576 __func__, addr, blocksize);
1577 return -EAGAIN;
1578 }
1579
1580 static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1581 enum rtl8xxxu_rfpath path, u8 reg)
1582 {
1583 u32 hssia, val32, retval;
1584
1585 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1586 if (path != RF_A)
1587 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1588 else
1589 val32 = hssia;
1590
1591 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1592 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1593 val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1594 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1595 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1596
1597 udelay(10);
1598
1599 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1600 udelay(100);
1601
1602 hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1603 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1604 udelay(10);
1605
1606 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1607 if (val32 & FPGA0_HSSI_PARM1_PI)
1608 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1609 else
1610 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1611
1612 retval &= 0xfffff;
1613
1614 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1615 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1616 __func__, reg, retval);
1617 return retval;
1618 }
1619
1620 /*
1621 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
1622 * have write issues in high temperature conditions. We may have to
1623 * retry writing them.
1624 */
1625 static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1626 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
1627 {
1628 int ret, retval;
1629 u32 dataaddr;
1630
1631 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1632 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1633 __func__, reg, data);
1634
1635 data &= FPGA0_LSSI_PARM_DATA_MASK;
1636 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1637
1638 /* Use XB for path B */
1639 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1640 if (ret != sizeof(dataaddr))
1641 retval = -EIO;
1642 else
1643 retval = 0;
1644
1645 udelay(1);
1646
1647 return retval;
1648 }
1649
1650 static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv,
1651 struct h2c_cmd *h2c, int len)
1652 {
1653 struct device *dev = &priv->udev->dev;
1654 int mbox_nr, retry, retval = 0;
1655 int mbox_reg, mbox_ext_reg;
1656 u8 val8;
1657
1658 mutex_lock(&priv->h2c_mutex);
1659
1660 mbox_nr = priv->next_mbox;
1661 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1662 mbox_ext_reg = priv->fops->mbox_ext_reg +
1663 (mbox_nr * priv->fops->mbox_ext_width);
1664
1665 /*
1666 * MBOX ready?
1667 */
1668 retry = 100;
1669 do {
1670 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1671 if (!(val8 & BIT(mbox_nr)))
1672 break;
1673 } while (retry--);
1674
1675 if (!retry) {
1676 dev_info(dev, "%s: Mailbox busy\n", __func__);
1677 retval = -EBUSY;
1678 goto error;
1679 }
1680
1681 /*
1682 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1683 */
1684 if (len > sizeof(u32)) {
1685 if (priv->fops->mbox_ext_width == 4) {
1686 rtl8xxxu_write32(priv, mbox_ext_reg,
1687 le32_to_cpu(h2c->raw_wide.ext));
1688 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1689 dev_info(dev, "H2C_EXT %08x\n",
1690 le32_to_cpu(h2c->raw_wide.ext));
1691 } else {
1692 rtl8xxxu_write16(priv, mbox_ext_reg,
1693 le16_to_cpu(h2c->raw.ext));
1694 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1695 dev_info(dev, "H2C_EXT %04x\n",
1696 le16_to_cpu(h2c->raw.ext));
1697 }
1698 }
1699 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1700 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1701 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1702
1703 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1704
1705 error:
1706 mutex_unlock(&priv->h2c_mutex);
1707 return retval;
1708 }
1709
1710 static void rtl8723bu_write_btreg(struct rtl8xxxu_priv *priv, u8 reg, u8 data)
1711 {
1712 struct h2c_cmd h2c;
1713 int reqnum = 0;
1714
1715 memset(&h2c, 0, sizeof(struct h2c_cmd));
1716 h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
1717 h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
1718 h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
1719 h2c.bt_mp_oper.data = data;
1720 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
1721
1722 reqnum++;
1723 memset(&h2c, 0, sizeof(struct h2c_cmd));
1724 h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
1725 h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
1726 h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
1727 h2c.bt_mp_oper.addr = reg;
1728 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
1729 }
1730
1731 static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv)
1732 {
1733 u8 val8;
1734 u32 val32;
1735
1736 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1737 val8 |= BIT(0) | BIT(3);
1738 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1739
1740 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1741 val32 &= ~(BIT(4) | BIT(5));
1742 val32 |= BIT(3);
1743 if (priv->rf_paths == 2) {
1744 val32 &= ~(BIT(20) | BIT(21));
1745 val32 |= BIT(19);
1746 }
1747 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1748
1749 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1750 val32 &= ~OFDM_RF_PATH_TX_MASK;
1751 if (priv->tx_paths == 2)
1752 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1753 else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C)
1754 val32 |= OFDM_RF_PATH_TX_B;
1755 else
1756 val32 |= OFDM_RF_PATH_TX_A;
1757 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1758
1759 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1760 val32 &= ~FPGA_RF_MODE_JAPAN;
1761 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1762
1763 if (priv->rf_paths == 2)
1764 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1765 else
1766 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1767
1768 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1769 if (priv->rf_paths == 2)
1770 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1771
1772 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1773 }
1774
1775 static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv)
1776 {
1777 u8 sps0;
1778 u32 val32;
1779
1780 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1781
1782 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1783
1784 /* RF RX code for preamble power saving */
1785 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1786 val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1787 if (priv->rf_paths == 2)
1788 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1789 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1790
1791 /* Disable TX for four paths */
1792 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1793 val32 &= ~OFDM_RF_PATH_TX_MASK;
1794 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1795
1796 /* Enable power saving */
1797 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1798 val32 |= FPGA_RF_MODE_JAPAN;
1799 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1800
1801 /* AFE control register to power down bits [30:22] */
1802 if (priv->rf_paths == 2)
1803 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1804 else
1805 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1806
1807 /* Power down RF module */
1808 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1809 if (priv->rf_paths == 2)
1810 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1811
1812 sps0 &= ~(BIT(0) | BIT(3));
1813 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1814 }
1815
1816
1817 static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1818 {
1819 u8 val8;
1820
1821 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1822 val8 &= ~BIT(6);
1823 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1824
1825 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1826 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1827 val8 &= ~BIT(0);
1828 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1829 }
1830
1831
1832 /*
1833 * The rtl8723a has 3 channel groups for it's efuse settings. It only
1834 * supports the 2.4GHz band, so channels 1 - 14:
1835 * group 0: channels 1 - 3
1836 * group 1: channels 4 - 9
1837 * group 2: channels 10 - 14
1838 *
1839 * Note: We index from 0 in the code
1840 */
1841 static int rtl8723a_channel_to_group(int channel)
1842 {
1843 int group;
1844
1845 if (channel < 4)
1846 group = 0;
1847 else if (channel < 10)
1848 group = 1;
1849 else
1850 group = 2;
1851
1852 return group;
1853 }
1854
1855 static int rtl8723b_channel_to_group(int channel)
1856 {
1857 int group;
1858
1859 if (channel < 3)
1860 group = 0;
1861 else if (channel < 6)
1862 group = 1;
1863 else if (channel < 9)
1864 group = 2;
1865 else if (channel < 12)
1866 group = 3;
1867 else
1868 group = 4;
1869
1870 return group;
1871 }
1872
1873 static void rtl8723au_config_channel(struct ieee80211_hw *hw)
1874 {
1875 struct rtl8xxxu_priv *priv = hw->priv;
1876 u32 val32, rsr;
1877 u8 val8, opmode;
1878 bool ht = true;
1879 int sec_ch_above, channel;
1880 int i;
1881
1882 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1883 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1884 channel = hw->conf.chandef.chan->hw_value;
1885
1886 switch (hw->conf.chandef.width) {
1887 case NL80211_CHAN_WIDTH_20_NOHT:
1888 ht = false;
1889 case NL80211_CHAN_WIDTH_20:
1890 opmode |= BW_OPMODE_20MHZ;
1891 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1892
1893 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1894 val32 &= ~FPGA_RF_MODE;
1895 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1896
1897 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1898 val32 &= ~FPGA_RF_MODE;
1899 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1900
1901 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1902 val32 |= FPGA0_ANALOG2_20MHZ;
1903 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1904 break;
1905 case NL80211_CHAN_WIDTH_40:
1906 if (hw->conf.chandef.center_freq1 >
1907 hw->conf.chandef.chan->center_freq) {
1908 sec_ch_above = 1;
1909 channel += 2;
1910 } else {
1911 sec_ch_above = 0;
1912 channel -= 2;
1913 }
1914
1915 opmode &= ~BW_OPMODE_20MHZ;
1916 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1917 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1918 if (sec_ch_above)
1919 rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1920 else
1921 rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1922 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1923
1924 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1925 val32 |= FPGA_RF_MODE;
1926 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1927
1928 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1929 val32 |= FPGA_RF_MODE;
1930 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1931
1932 /*
1933 * Set Control channel to upper or lower. These settings
1934 * are required only for 40MHz
1935 */
1936 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1937 val32 &= ~CCK0_SIDEBAND;
1938 if (!sec_ch_above)
1939 val32 |= CCK0_SIDEBAND;
1940 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1941
1942 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1943 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1944 if (sec_ch_above)
1945 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1946 else
1947 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1948 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1949
1950 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1951 val32 &= ~FPGA0_ANALOG2_20MHZ;
1952 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1953
1954 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1955 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1956 if (sec_ch_above)
1957 val32 |= FPGA0_PS_UPPER_CHANNEL;
1958 else
1959 val32 |= FPGA0_PS_LOWER_CHANNEL;
1960 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1961 break;
1962
1963 default:
1964 break;
1965 }
1966
1967 for (i = RF_A; i < priv->rf_paths; i++) {
1968 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1969 val32 &= ~MODE_AG_CHANNEL_MASK;
1970 val32 |= channel;
1971 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1972 }
1973
1974 if (ht)
1975 val8 = 0x0e;
1976 else
1977 val8 = 0x0a;
1978
1979 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1980 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1981
1982 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1983 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1984
1985 for (i = RF_A; i < priv->rf_paths; i++) {
1986 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1987 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1988 val32 &= ~MODE_AG_CHANNEL_20MHZ;
1989 else
1990 val32 |= MODE_AG_CHANNEL_20MHZ;
1991 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1992 }
1993 }
1994
1995 static void rtl8723bu_config_channel(struct ieee80211_hw *hw)
1996 {
1997 struct rtl8xxxu_priv *priv = hw->priv;
1998 u32 val32, rsr;
1999 u8 val8, subchannel;
2000 u16 rf_mode_bw;
2001 bool ht = true;
2002 int sec_ch_above, channel;
2003 int i;
2004
2005 rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL);
2006 rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK;
2007 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
2008 channel = hw->conf.chandef.chan->hw_value;
2009
2010 /* Hack */
2011 subchannel = 0;
2012
2013 switch (hw->conf.chandef.width) {
2014 case NL80211_CHAN_WIDTH_20_NOHT:
2015 ht = false;
2016 case NL80211_CHAN_WIDTH_20:
2017 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20;
2018 subchannel = 0;
2019
2020 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
2021 val32 &= ~FPGA_RF_MODE;
2022 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
2023
2024 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
2025 val32 &= ~FPGA_RF_MODE;
2026 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
2027
2028 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
2029 val32 &= ~(BIT(30) | BIT(31));
2030 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);
2031
2032 break;
2033 case NL80211_CHAN_WIDTH_40:
2034 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40;
2035
2036 if (hw->conf.chandef.center_freq1 >
2037 hw->conf.chandef.chan->center_freq) {
2038 sec_ch_above = 1;
2039 channel += 2;
2040 } else {
2041 sec_ch_above = 0;
2042 channel -= 2;
2043 }
2044
2045 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
2046 val32 |= FPGA_RF_MODE;
2047 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
2048
2049 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
2050 val32 |= FPGA_RF_MODE;
2051 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
2052
2053 /*
2054 * Set Control channel to upper or lower. These settings
2055 * are required only for 40MHz
2056 */
2057 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
2058 val32 &= ~CCK0_SIDEBAND;
2059 if (!sec_ch_above)
2060 val32 |= CCK0_SIDEBAND;
2061 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
2062
2063 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
2064 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
2065 if (sec_ch_above)
2066 val32 |= OFDM_LSTF_PRIME_CH_LOW;
2067 else
2068 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
2069 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
2070
2071 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
2072 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
2073 if (sec_ch_above)
2074 val32 |= FPGA0_PS_UPPER_CHANNEL;
2075 else
2076 val32 |= FPGA0_PS_LOWER_CHANNEL;
2077 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
2078 break;
2079 case NL80211_CHAN_WIDTH_80:
2080 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80;
2081 break;
2082 default:
2083 break;
2084 }
2085
2086 for (i = RF_A; i < priv->rf_paths; i++) {
2087 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
2088 val32 &= ~MODE_AG_CHANNEL_MASK;
2089 val32 |= channel;
2090 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
2091 }
2092
2093 rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw);
2094 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel);
2095
2096 if (ht)
2097 val8 = 0x0e;
2098 else
2099 val8 = 0x0a;
2100
2101 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
2102 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
2103
2104 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
2105 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
2106
2107 for (i = RF_A; i < priv->rf_paths; i++) {
2108 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
2109 val32 &= ~MODE_AG_BW_MASK;
2110 switch(hw->conf.chandef.width) {
2111 case NL80211_CHAN_WIDTH_80:
2112 val32 |= MODE_AG_BW_80MHZ_8723B;
2113 break;
2114 case NL80211_CHAN_WIDTH_40:
2115 val32 |= MODE_AG_BW_40MHZ_8723B;
2116 break;
2117 default:
2118 val32 |= MODE_AG_BW_20MHZ_8723B;
2119 break;
2120 }
2121 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
2122 }
2123 }
2124
2125 static void
2126 rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
2127 {
2128 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
2129 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
2130 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
2131 u8 val8;
2132 int group, i;
2133
2134 group = rtl8723a_channel_to_group(channel);
2135
2136 cck[0] = priv->cck_tx_power_index_A[group];
2137 cck[1] = priv->cck_tx_power_index_B[group];
2138
2139 ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
2140 ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
2141
2142 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
2143 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
2144
2145 mcsbase[0] = ofdm[0];
2146 mcsbase[1] = ofdm[1];
2147 if (!ht40) {
2148 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
2149 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
2150 }
2151
2152 if (priv->tx_paths > 1) {
2153 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
2154 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a;
2155 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
2156 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b;
2157 }
2158
2159 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
2160 dev_info(&priv->udev->dev,
2161 "%s: Setting TX power CCK A: %02x, "
2162 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
2163 __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
2164
2165 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
2166 if (cck[i] > RF6052_MAX_TX_PWR)
2167 cck[i] = RF6052_MAX_TX_PWR;
2168 if (ofdm[i] > RF6052_MAX_TX_PWR)
2169 ofdm[i] = RF6052_MAX_TX_PWR;
2170 }
2171
2172 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
2173 val32 &= 0xffff00ff;
2174 val32 |= (cck[0] << 8);
2175 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
2176
2177 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2178 val32 &= 0xff;
2179 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
2180 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2181
2182 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2183 val32 &= 0xffffff00;
2184 val32 |= cck[1];
2185 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2186
2187 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
2188 val32 &= 0xff;
2189 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
2190 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
2191
2192 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
2193 ofdmbase[0] << 16 | ofdmbase[0] << 24;
2194 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
2195 ofdmbase[1] << 16 | ofdmbase[1] << 24;
2196 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a);
2197 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b);
2198
2199 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a);
2200 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b);
2201
2202 mcs_a = mcsbase[0] | mcsbase[0] << 8 |
2203 mcsbase[0] << 16 | mcsbase[0] << 24;
2204 mcs_b = mcsbase[1] | mcsbase[1] << 8 |
2205 mcsbase[1] << 16 | mcsbase[1] << 24;
2206
2207 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a);
2208 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b);
2209
2210 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a);
2211 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b);
2212
2213 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a);
2214 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b);
2215
2216 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a);
2217 for (i = 0; i < 3; i++) {
2218 if (i != 2)
2219 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
2220 else
2221 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
2222 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
2223 }
2224 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b);
2225 for (i = 0; i < 3; i++) {
2226 if (i != 2)
2227 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
2228 else
2229 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
2230 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
2231 }
2232 }
2233
2234 static void
2235 rtl8723b_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
2236 {
2237 u32 val32, ofdm, mcs;
2238 u8 cck, ofdmbase, mcsbase;
2239 int group, tx_idx;
2240
2241 tx_idx = 0;
2242 group = rtl8723b_channel_to_group(channel);
2243
2244 cck = priv->cck_tx_power_index_B[group];
2245 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
2246 val32 &= 0xffff00ff;
2247 val32 |= (cck << 8);
2248 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
2249
2250 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2251 val32 &= 0xff;
2252 val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
2253 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2254
2255 ofdmbase = priv->ht40_1s_tx_power_index_B[group];
2256 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b;
2257 ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24;
2258
2259 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm);
2260 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm);
2261
2262 mcsbase = priv->ht40_1s_tx_power_index_B[group];
2263 if (ht40)
2264 mcsbase += priv->ht40_tx_power_diff[tx_idx++].b;
2265 else
2266 mcsbase += priv->ht20_tx_power_diff[tx_idx++].b;
2267 mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
2268
2269 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs);
2270 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs);
2271 }
2272
2273 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
2274 enum nl80211_iftype linktype)
2275 {
2276 u8 val8;
2277
2278 val8 = rtl8xxxu_read8(priv, REG_MSR);
2279 val8 &= ~MSR_LINKTYPE_MASK;
2280
2281 switch (linktype) {
2282 case NL80211_IFTYPE_UNSPECIFIED:
2283 val8 |= MSR_LINKTYPE_NONE;
2284 break;
2285 case NL80211_IFTYPE_ADHOC:
2286 val8 |= MSR_LINKTYPE_ADHOC;
2287 break;
2288 case NL80211_IFTYPE_STATION:
2289 val8 |= MSR_LINKTYPE_STATION;
2290 break;
2291 case NL80211_IFTYPE_AP:
2292 val8 |= MSR_LINKTYPE_AP;
2293 break;
2294 default:
2295 goto out;
2296 }
2297
2298 rtl8xxxu_write8(priv, REG_MSR, val8);
2299 out:
2300 return;
2301 }
2302
2303 static void
2304 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
2305 {
2306 u16 val16;
2307
2308 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
2309 RETRY_LIMIT_SHORT_MASK) |
2310 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
2311 RETRY_LIMIT_LONG_MASK);
2312
2313 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
2314 }
2315
2316 static void
2317 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
2318 {
2319 u16 val16;
2320
2321 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
2322 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
2323
2324 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
2325 }
2326
2327 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
2328 {
2329 struct device *dev = &priv->udev->dev;
2330 char *cut;
2331
2332 switch (priv->chip_cut) {
2333 case 0:
2334 cut = "A";
2335 break;
2336 case 1:
2337 cut = "B";
2338 break;
2339 case 2:
2340 cut = "C";
2341 break;
2342 case 3:
2343 cut = "D";
2344 break;
2345 case 4:
2346 cut = "E";
2347 break;
2348 default:
2349 cut = "unknown";
2350 }
2351
2352 dev_info(dev,
2353 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
2354 priv->chip_name, cut, priv->chip_vendor, priv->tx_paths,
2355 priv->rx_paths, priv->ep_tx_count, priv->has_wifi,
2356 priv->has_bluetooth, priv->has_gps, priv->hi_pa);
2357
2358 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
2359 }
2360
2361 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
2362 {
2363 struct device *dev = &priv->udev->dev;
2364 u32 val32, bonding;
2365 u16 val16;
2366
2367 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
2368 priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
2369 SYS_CFG_CHIP_VERSION_SHIFT;
2370 if (val32 & SYS_CFG_TRP_VAUX_EN) {
2371 dev_info(dev, "Unsupported test chip\n");
2372 return -ENOTSUPP;
2373 }
2374
2375 if (val32 & SYS_CFG_BT_FUNC) {
2376 if (priv->chip_cut >= 3) {
2377 sprintf(priv->chip_name, "8723BU");
2378 priv->rtl_chip = RTL8723B;
2379 } else {
2380 sprintf(priv->chip_name, "8723AU");
2381 priv->usb_interrupts = 1;
2382 priv->rtl_chip = RTL8723A;
2383 }
2384
2385 priv->rf_paths = 1;
2386 priv->rx_paths = 1;
2387 priv->tx_paths = 1;
2388
2389 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
2390 if (val32 & MULTI_WIFI_FUNC_EN)
2391 priv->has_wifi = 1;
2392 if (val32 & MULTI_BT_FUNC_EN)
2393 priv->has_bluetooth = 1;
2394 if (val32 & MULTI_GPS_FUNC_EN)
2395 priv->has_gps = 1;
2396 priv->is_multi_func = 1;
2397 } else if (val32 & SYS_CFG_TYPE_ID) {
2398 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
2399 bonding &= HPON_FSM_BONDING_MASK;
2400 if (priv->fops->has_s0s1) {
2401 if (bonding == HPON_FSM_BONDING_1T2R) {
2402 sprintf(priv->chip_name, "8191EU");
2403 priv->rf_paths = 2;
2404 priv->rx_paths = 2;
2405 priv->tx_paths = 1;
2406 priv->rtl_chip = RTL8191E;
2407 } else {
2408 sprintf(priv->chip_name, "8192EU");
2409 priv->rf_paths = 2;
2410 priv->rx_paths = 2;
2411 priv->tx_paths = 2;
2412 priv->rtl_chip = RTL8192E;
2413 }
2414 } else if (bonding == HPON_FSM_BONDING_1T2R) {
2415 sprintf(priv->chip_name, "8191CU");
2416 priv->rf_paths = 2;
2417 priv->rx_paths = 2;
2418 priv->tx_paths = 1;
2419 priv->usb_interrupts = 1;
2420 priv->rtl_chip = RTL8191C;
2421 } else {
2422 sprintf(priv->chip_name, "8192CU");
2423 priv->rf_paths = 2;
2424 priv->rx_paths = 2;
2425 priv->tx_paths = 2;
2426 priv->usb_interrupts = 1;
2427 priv->rtl_chip = RTL8192C;
2428 }
2429 priv->has_wifi = 1;
2430 } else {
2431 sprintf(priv->chip_name, "8188CU");
2432 priv->rf_paths = 1;
2433 priv->rx_paths = 1;
2434 priv->tx_paths = 1;
2435 priv->rtl_chip = RTL8188C;
2436 priv->usb_interrupts = 1;
2437 priv->has_wifi = 1;
2438 }
2439
2440 switch (priv->rtl_chip) {
2441 case RTL8188E:
2442 case RTL8192E:
2443 case RTL8723B:
2444 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
2445 case SYS_CFG_VENDOR_ID_TSMC:
2446 sprintf(priv->chip_vendor, "TSMC");
2447 break;
2448 case SYS_CFG_VENDOR_ID_SMIC:
2449 sprintf(priv->chip_vendor, "SMIC");
2450 priv->vendor_smic = 1;
2451 break;
2452 case SYS_CFG_VENDOR_ID_UMC:
2453 sprintf(priv->chip_vendor, "UMC");
2454 priv->vendor_umc = 1;
2455 break;
2456 default:
2457 sprintf(priv->chip_vendor, "unknown");
2458 }
2459 break;
2460 default:
2461 if (val32 & SYS_CFG_VENDOR_ID) {
2462 sprintf(priv->chip_vendor, "UMC");
2463 priv->vendor_umc = 1;
2464 } else {
2465 sprintf(priv->chip_vendor, "TSMC");
2466 }
2467 }
2468
2469 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
2470 priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
2471
2472 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
2473 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
2474 priv->ep_tx_high_queue = 1;
2475 priv->ep_tx_count++;
2476 }
2477
2478 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
2479 priv->ep_tx_normal_queue = 1;
2480 priv->ep_tx_count++;
2481 }
2482
2483 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
2484 priv->ep_tx_low_queue = 1;
2485 priv->ep_tx_count++;
2486 }
2487
2488 /*
2489 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
2490 */
2491 if (!priv->ep_tx_count) {
2492 switch (priv->nr_out_eps) {
2493 case 4:
2494 case 3:
2495 priv->ep_tx_low_queue = 1;
2496 priv->ep_tx_count++;
2497 case 2:
2498 priv->ep_tx_normal_queue = 1;
2499 priv->ep_tx_count++;
2500 case 1:
2501 priv->ep_tx_high_queue = 1;
2502 priv->ep_tx_count++;
2503 break;
2504 default:
2505 dev_info(dev, "Unsupported USB TX end-points\n");
2506 return -ENOTSUPP;
2507 }
2508 }
2509
2510 return 0;
2511 }
2512
2513 static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
2514 {
2515 struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723;
2516
2517 if (efuse->rtl_id != cpu_to_le16(0x8129))
2518 return -EINVAL;
2519
2520 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2521
2522 memcpy(priv->cck_tx_power_index_A,
2523 efuse->cck_tx_power_index_A,
2524 sizeof(efuse->cck_tx_power_index_A));
2525 memcpy(priv->cck_tx_power_index_B,
2526 efuse->cck_tx_power_index_B,
2527 sizeof(efuse->cck_tx_power_index_B));
2528
2529 memcpy(priv->ht40_1s_tx_power_index_A,
2530 efuse->ht40_1s_tx_power_index_A,
2531 sizeof(efuse->ht40_1s_tx_power_index_A));
2532 memcpy(priv->ht40_1s_tx_power_index_B,
2533 efuse->ht40_1s_tx_power_index_B,
2534 sizeof(efuse->ht40_1s_tx_power_index_B));
2535
2536 memcpy(priv->ht20_tx_power_index_diff,
2537 efuse->ht20_tx_power_index_diff,
2538 sizeof(efuse->ht20_tx_power_index_diff));
2539 memcpy(priv->ofdm_tx_power_index_diff,
2540 efuse->ofdm_tx_power_index_diff,
2541 sizeof(efuse->ofdm_tx_power_index_diff));
2542
2543 memcpy(priv->ht40_max_power_offset,
2544 efuse->ht40_max_power_offset,
2545 sizeof(efuse->ht40_max_power_offset));
2546 memcpy(priv->ht20_max_power_offset,
2547 efuse->ht20_max_power_offset,
2548 sizeof(efuse->ht20_max_power_offset));
2549
2550 if (priv->efuse_wifi.efuse8723.version >= 0x01) {
2551 priv->has_xtalk = 1;
2552 priv->xtalk = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
2553 }
2554 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2555 efuse->vendor_name);
2556 dev_info(&priv->udev->dev, "Product: %.41s\n",
2557 efuse->device_name);
2558 return 0;
2559 }
2560
2561 static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv)
2562 {
2563 struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu;
2564 int i;
2565
2566 if (efuse->rtl_id != cpu_to_le16(0x8129))
2567 return -EINVAL;
2568
2569 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2570
2571 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base,
2572 sizeof(efuse->tx_power_index_A.cck_base));
2573 memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base,
2574 sizeof(efuse->tx_power_index_B.cck_base));
2575
2576 memcpy(priv->ht40_1s_tx_power_index_A,
2577 efuse->tx_power_index_A.ht40_base,
2578 sizeof(efuse->tx_power_index_A.ht40_base));
2579 memcpy(priv->ht40_1s_tx_power_index_B,
2580 efuse->tx_power_index_B.ht40_base,
2581 sizeof(efuse->tx_power_index_B.ht40_base));
2582
2583 priv->ofdm_tx_power_diff[0].a =
2584 efuse->tx_power_index_A.ht20_ofdm_1s_diff.a;
2585 priv->ofdm_tx_power_diff[0].b =
2586 efuse->tx_power_index_B.ht20_ofdm_1s_diff.a;
2587
2588 priv->ht20_tx_power_diff[0].a =
2589 efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;
2590 priv->ht20_tx_power_diff[0].b =
2591 efuse->tx_power_index_B.ht20_ofdm_1s_diff.b;
2592
2593 priv->ht40_tx_power_diff[0].a = 0;
2594 priv->ht40_tx_power_diff[0].b = 0;
2595
2596 for (i = 1; i < RTL8723B_TX_COUNT; i++) {
2597 priv->ofdm_tx_power_diff[i].a =
2598 efuse->tx_power_index_A.pwr_diff[i - 1].ofdm;
2599 priv->ofdm_tx_power_diff[i].b =
2600 efuse->tx_power_index_B.pwr_diff[i - 1].ofdm;
2601
2602 priv->ht20_tx_power_diff[i].a =
2603 efuse->tx_power_index_A.pwr_diff[i - 1].ht20;
2604 priv->ht20_tx_power_diff[i].b =
2605 efuse->tx_power_index_B.pwr_diff[i - 1].ht20;
2606
2607 priv->ht40_tx_power_diff[i].a =
2608 efuse->tx_power_index_A.pwr_diff[i - 1].ht40;
2609 priv->ht40_tx_power_diff[i].b =
2610 efuse->tx_power_index_B.pwr_diff[i - 1].ht40;
2611 }
2612
2613 priv->has_xtalk = 1;
2614 priv->xtalk = priv->efuse_wifi.efuse8723bu.xtal_k & 0x3f;
2615
2616 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
2617 dev_info(&priv->udev->dev, "Product: %.41s\n", efuse->device_name);
2618
2619 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2620 int i;
2621 unsigned char *raw = priv->efuse_wifi.raw;
2622
2623 dev_info(&priv->udev->dev,
2624 "%s: dumping efuse (0x%02zx bytes):\n",
2625 __func__, sizeof(struct rtl8723bu_efuse));
2626 for (i = 0; i < sizeof(struct rtl8723bu_efuse); i += 8) {
2627 dev_info(&priv->udev->dev, "%02x: "
2628 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2629 raw[i], raw[i + 1], raw[i + 2],
2630 raw[i + 3], raw[i + 4], raw[i + 5],
2631 raw[i + 6], raw[i + 7]);
2632 }
2633 }
2634
2635 return 0;
2636 }
2637
2638 #ifdef CONFIG_RTL8XXXU_UNTESTED
2639
2640 static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
2641 {
2642 struct rtl8192cu_efuse *efuse = &priv->efuse_wifi.efuse8192;
2643 int i;
2644
2645 if (efuse->rtl_id != cpu_to_le16(0x8129))
2646 return -EINVAL;
2647
2648 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2649
2650 memcpy(priv->cck_tx_power_index_A,
2651 efuse->cck_tx_power_index_A,
2652 sizeof(efuse->cck_tx_power_index_A));
2653 memcpy(priv->cck_tx_power_index_B,
2654 efuse->cck_tx_power_index_B,
2655 sizeof(efuse->cck_tx_power_index_B));
2656
2657 memcpy(priv->ht40_1s_tx_power_index_A,
2658 efuse->ht40_1s_tx_power_index_A,
2659 sizeof(efuse->ht40_1s_tx_power_index_A));
2660 memcpy(priv->ht40_1s_tx_power_index_B,
2661 efuse->ht40_1s_tx_power_index_B,
2662 sizeof(efuse->ht40_1s_tx_power_index_B));
2663 memcpy(priv->ht40_2s_tx_power_index_diff,
2664 efuse->ht40_2s_tx_power_index_diff,
2665 sizeof(efuse->ht40_2s_tx_power_index_diff));
2666
2667 memcpy(priv->ht20_tx_power_index_diff,
2668 efuse->ht20_tx_power_index_diff,
2669 sizeof(efuse->ht20_tx_power_index_diff));
2670 memcpy(priv->ofdm_tx_power_index_diff,
2671 efuse->ofdm_tx_power_index_diff,
2672 sizeof(efuse->ofdm_tx_power_index_diff));
2673
2674 memcpy(priv->ht40_max_power_offset,
2675 efuse->ht40_max_power_offset,
2676 sizeof(efuse->ht40_max_power_offset));
2677 memcpy(priv->ht20_max_power_offset,
2678 efuse->ht20_max_power_offset,
2679 sizeof(efuse->ht20_max_power_offset));
2680
2681 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2682 efuse->vendor_name);
2683 dev_info(&priv->udev->dev, "Product: %.20s\n",
2684 efuse->device_name);
2685
2686 if (efuse->rf_regulatory & 0x20) {
2687 sprintf(priv->chip_name, "8188RU");
2688 priv->hi_pa = 1;
2689 }
2690
2691 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2692 unsigned char *raw = priv->efuse_wifi.raw;
2693
2694 dev_info(&priv->udev->dev,
2695 "%s: dumping efuse (0x%02zx bytes):\n",
2696 __func__, sizeof(struct rtl8192cu_efuse));
2697 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
2698 dev_info(&priv->udev->dev, "%02x: "
2699 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2700 raw[i], raw[i + 1], raw[i + 2],
2701 raw[i + 3], raw[i + 4], raw[i + 5],
2702 raw[i + 6], raw[i + 7]);
2703 }
2704 }
2705 return 0;
2706 }
2707
2708 #endif
2709
2710 static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv)
2711 {
2712 struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu;
2713 int i;
2714
2715 if (efuse->rtl_id != cpu_to_le16(0x8129))
2716 return -EINVAL;
2717
2718 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2719
2720 priv->has_xtalk = 1;
2721 priv->xtalk = priv->efuse_wifi.efuse8192eu.xtal_k & 0x3f;
2722
2723 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
2724 dev_info(&priv->udev->dev, "Product: %.11s\n", efuse->device_name);
2725 dev_info(&priv->udev->dev, "Serial: %.11s\n", efuse->serial);
2726
2727 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2728 unsigned char *raw = priv->efuse_wifi.raw;
2729
2730 dev_info(&priv->udev->dev,
2731 "%s: dumping efuse (0x%02zx bytes):\n",
2732 __func__, sizeof(struct rtl8192eu_efuse));
2733 for (i = 0; i < sizeof(struct rtl8192eu_efuse); i += 8) {
2734 dev_info(&priv->udev->dev, "%02x: "
2735 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2736 raw[i], raw[i + 1], raw[i + 2],
2737 raw[i + 3], raw[i + 4], raw[i + 5],
2738 raw[i + 6], raw[i + 7]);
2739 }
2740 }
2741 /*
2742 * Temporarily disable 8192eu support
2743 */
2744 return -EINVAL;
2745 return 0;
2746 }
2747
2748 static int
2749 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
2750 {
2751 int i;
2752 u8 val8;
2753 u32 val32;
2754
2755 /* Write Address */
2756 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
2757 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
2758 val8 &= 0xfc;
2759 val8 |= (offset >> 8) & 0x03;
2760 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
2761
2762 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
2763 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
2764
2765 /* Poll for data read */
2766 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2767 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
2768 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2769 if (val32 & BIT(31))
2770 break;
2771 }
2772
2773 if (i == RTL8XXXU_MAX_REG_POLL)
2774 return -EIO;
2775
2776 udelay(50);
2777 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2778
2779 *data = val32 & 0xff;
2780 return 0;
2781 }
2782
2783 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
2784 {
2785 struct device *dev = &priv->udev->dev;
2786 int i, ret = 0;
2787 u8 val8, word_mask, header, extheader;
2788 u16 val16, efuse_addr, offset;
2789 u32 val32;
2790
2791 val16 = rtl8xxxu_read16(priv, REG_9346CR);
2792 if (val16 & EEPROM_ENABLE)
2793 priv->has_eeprom = 1;
2794 if (val16 & EEPROM_BOOT)
2795 priv->boot_eeprom = 1;
2796
2797 if (priv->is_multi_func) {
2798 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
2799 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
2800 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
2801 }
2802
2803 dev_dbg(dev, "Booting from %s\n",
2804 priv->boot_eeprom ? "EEPROM" : "EFUSE");
2805
2806 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
2807
2808 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
2809 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
2810 if (!(val16 & SYS_ISO_PWC_EV12V)) {
2811 val16 |= SYS_ISO_PWC_EV12V;
2812 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
2813 }
2814 /* Reset: 0x0000[28], default valid */
2815 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2816 if (!(val16 & SYS_FUNC_ELDR)) {
2817 val16 |= SYS_FUNC_ELDR;
2818 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2819 }
2820
2821 /*
2822 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
2823 */
2824 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
2825 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
2826 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
2827 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
2828 }
2829
2830 /* Default value is 0xff */
2831 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
2832
2833 efuse_addr = 0;
2834 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
2835 u16 map_addr;
2836
2837 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
2838 if (ret || header == 0xff)
2839 goto exit;
2840
2841 if ((header & 0x1f) == 0x0f) { /* extended header */
2842 offset = (header & 0xe0) >> 5;
2843
2844 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
2845 &extheader);
2846 if (ret)
2847 goto exit;
2848 /* All words disabled */
2849 if ((extheader & 0x0f) == 0x0f)
2850 continue;
2851
2852 offset |= ((extheader & 0xf0) >> 1);
2853 word_mask = extheader & 0x0f;
2854 } else {
2855 offset = (header >> 4) & 0x0f;
2856 word_mask = header & 0x0f;
2857 }
2858
2859 /* Get word enable value from PG header */
2860
2861 /* We have 8 bits to indicate validity */
2862 map_addr = offset * 8;
2863 if (map_addr >= EFUSE_MAP_LEN) {
2864 dev_warn(dev, "%s: Illegal map_addr (%04x), "
2865 "efuse corrupt!\n",
2866 __func__, map_addr);
2867 ret = -EINVAL;
2868 goto exit;
2869 }
2870 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
2871 /* Check word enable condition in the section */
2872 if (word_mask & BIT(i)) {
2873 map_addr += 2;
2874 continue;
2875 }
2876
2877 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2878 if (ret)
2879 goto exit;
2880 priv->efuse_wifi.raw[map_addr++] = val8;
2881
2882 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2883 if (ret)
2884 goto exit;
2885 priv->efuse_wifi.raw[map_addr++] = val8;
2886 }
2887 }
2888
2889 exit:
2890 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
2891
2892 return ret;
2893 }
2894
2895 static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
2896 {
2897 u8 val8;
2898 u16 sys_func;
2899
2900 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2901 val8 &= ~BIT(0);
2902 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2903
2904 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2905 sys_func &= ~SYS_FUNC_CPU_ENABLE;
2906 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2907
2908 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2909 val8 |= BIT(0);
2910 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2911
2912 sys_func |= SYS_FUNC_CPU_ENABLE;
2913 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2914 }
2915
2916 static void rtl8723bu_reset_8051(struct rtl8xxxu_priv *priv)
2917 {
2918 u8 val8;
2919 u16 sys_func;
2920
2921 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
2922 val8 &= ~BIT(1);
2923 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
2924
2925 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2926 val8 &= ~BIT(0);
2927 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2928
2929 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2930 sys_func &= ~SYS_FUNC_CPU_ENABLE;
2931 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2932
2933 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
2934 val8 &= ~BIT(1);
2935 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
2936
2937 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2938 val8 |= BIT(0);
2939 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2940
2941 sys_func |= SYS_FUNC_CPU_ENABLE;
2942 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2943 }
2944
2945 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
2946 {
2947 struct device *dev = &priv->udev->dev;
2948 int ret = 0, i;
2949 u32 val32;
2950
2951 /* Poll checksum report */
2952 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2953 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2954 if (val32 & MCU_FW_DL_CSUM_REPORT)
2955 break;
2956 }
2957
2958 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2959 dev_warn(dev, "Firmware checksum poll timed out\n");
2960 ret = -EAGAIN;
2961 goto exit;
2962 }
2963
2964 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2965 val32 |= MCU_FW_DL_READY;
2966 val32 &= ~MCU_WINT_INIT_READY;
2967 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2968
2969 /*
2970 * Reset the 8051 in order for the firmware to start running,
2971 * otherwise it won't come up on the 8192eu
2972 */
2973 priv->fops->reset_8051(priv);
2974
2975 /* Wait for firmware to become ready */
2976 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2977 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2978 if (val32 & MCU_WINT_INIT_READY)
2979 break;
2980
2981 udelay(100);
2982 }
2983
2984 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2985 dev_warn(dev, "Firmware failed to start\n");
2986 ret = -EAGAIN;
2987 goto exit;
2988 }
2989
2990 /*
2991 * Init H2C command
2992 */
2993 if (priv->rtl_chip == RTL8723B)
2994 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f);
2995 exit:
2996 return ret;
2997 }
2998
2999 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
3000 {
3001 int pages, remainder, i, ret;
3002 u8 val8;
3003 u16 val16;
3004 u32 val32;
3005 u8 *fwptr;
3006
3007 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
3008 val8 |= 4;
3009 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
3010
3011 /* 8051 enable */
3012 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3013 val16 |= SYS_FUNC_CPU_ENABLE;
3014 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3015
3016 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
3017 if (val8 & MCU_FW_RAM_SEL) {
3018 pr_info("do the RAM reset\n");
3019 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
3020 priv->fops->reset_8051(priv);
3021 }
3022
3023 /* MCU firmware download enable */
3024 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
3025 val8 |= MCU_FW_DL_ENABLE;
3026 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
3027
3028 /* 8051 reset */
3029 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
3030 val32 &= ~BIT(19);
3031 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
3032
3033 /* Reset firmware download checksum */
3034 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
3035 val8 |= MCU_FW_DL_CSUM_REPORT;
3036 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
3037
3038 pages = priv->fw_size / RTL_FW_PAGE_SIZE;
3039 remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
3040
3041 fwptr = priv->fw_data->data;
3042
3043 for (i = 0; i < pages; i++) {
3044 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
3045 val8 |= i;
3046 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
3047
3048 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
3049 fwptr, RTL_FW_PAGE_SIZE);
3050 if (ret != RTL_FW_PAGE_SIZE) {
3051 ret = -EAGAIN;
3052 goto fw_abort;
3053 }
3054
3055 fwptr += RTL_FW_PAGE_SIZE;
3056 }
3057
3058 if (remainder) {
3059 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
3060 val8 |= i;
3061 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
3062 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
3063 fwptr, remainder);
3064 if (ret != remainder) {
3065 ret = -EAGAIN;
3066 goto fw_abort;
3067 }
3068 }
3069
3070 ret = 0;
3071 fw_abort:
3072 /* MCU firmware download disable */
3073 val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
3074 val16 &= ~MCU_FW_DL_ENABLE;
3075 rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
3076
3077 return ret;
3078 }
3079
3080 static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
3081 {
3082 struct device *dev = &priv->udev->dev;
3083 const struct firmware *fw;
3084 int ret = 0;
3085 u16 signature;
3086
3087 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
3088 if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
3089 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
3090 ret = -EAGAIN;
3091 goto exit;
3092 }
3093 if (!fw) {
3094 dev_warn(dev, "Firmware data not available\n");
3095 ret = -EINVAL;
3096 goto exit;
3097 }
3098
3099 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
3100 if (!priv->fw_data) {
3101 ret = -ENOMEM;
3102 goto exit;
3103 }
3104 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
3105
3106 signature = le16_to_cpu(priv->fw_data->signature);
3107 switch (signature & 0xfff0) {
3108 case 0x92e0:
3109 case 0x92c0:
3110 case 0x88c0:
3111 case 0x5300:
3112 case 0x2300:
3113 break;
3114 default:
3115 ret = -EINVAL;
3116 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
3117 __func__, signature);
3118 }
3119
3120 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
3121 le16_to_cpu(priv->fw_data->major_version),
3122 priv->fw_data->minor_version, signature);
3123
3124 exit:
3125 release_firmware(fw);
3126 return ret;
3127 }
3128
3129 static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
3130 {
3131 char *fw_name;
3132 int ret;
3133
3134 switch (priv->chip_cut) {
3135 case 0:
3136 fw_name = "rtlwifi/rtl8723aufw_A.bin";
3137 break;
3138 case 1:
3139 if (priv->enable_bluetooth)
3140 fw_name = "rtlwifi/rtl8723aufw_B.bin";
3141 else
3142 fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
3143
3144 break;
3145 default:
3146 return -EINVAL;
3147 }
3148
3149 ret = rtl8xxxu_load_firmware(priv, fw_name);
3150 return ret;
3151 }
3152
3153 static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv)
3154 {
3155 char *fw_name;
3156 int ret;
3157
3158 if (priv->enable_bluetooth)
3159 fw_name = "rtlwifi/rtl8723bu_bt.bin";
3160 else
3161 fw_name = "rtlwifi/rtl8723bu_nic.bin";
3162
3163 ret = rtl8xxxu_load_firmware(priv, fw_name);
3164 return ret;
3165 }
3166
3167 #ifdef CONFIG_RTL8XXXU_UNTESTED
3168
3169 static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
3170 {
3171 char *fw_name;
3172 int ret;
3173
3174 if (!priv->vendor_umc)
3175 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
3176 else if (priv->chip_cut || priv->rtl_chip == RTL8192C)
3177 fw_name = "rtlwifi/rtl8192cufw_B.bin";
3178 else
3179 fw_name = "rtlwifi/rtl8192cufw_A.bin";
3180
3181 ret = rtl8xxxu_load_firmware(priv, fw_name);
3182
3183 return ret;
3184 }
3185
3186 #endif
3187
3188 static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv)
3189 {
3190 char *fw_name;
3191 int ret;
3192
3193 fw_name = "rtlwifi/rtl8192eu_nic.bin";
3194
3195 ret = rtl8xxxu_load_firmware(priv, fw_name);
3196
3197 return ret;
3198 }
3199
3200 static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
3201 {
3202 u16 val16;
3203 int i = 100;
3204
3205 /* Inform 8051 to perform reset */
3206 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
3207
3208 for (i = 100; i > 0; i--) {
3209 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3210
3211 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
3212 dev_dbg(&priv->udev->dev,
3213 "%s: Firmware self reset success!\n", __func__);
3214 break;
3215 }
3216 udelay(50);
3217 }
3218
3219 if (!i) {
3220 /* Force firmware reset */
3221 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3222 val16 &= ~SYS_FUNC_CPU_ENABLE;
3223 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3224 }
3225 }
3226
3227 static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv)
3228 {
3229 u32 val32;
3230
3231 val32 = rtl8xxxu_read32(priv, 0x64);
3232 val32 &= ~(BIT(20) | BIT(24));
3233 rtl8xxxu_write32(priv, 0x64, val32);
3234
3235 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
3236 val32 &= ~BIT(4);
3237 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
3238
3239 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
3240 val32 |= BIT(3);
3241 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
3242
3243 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
3244 val32 |= BIT(24);
3245 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
3246
3247 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
3248 val32 &= ~BIT(23);
3249 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
3250
3251 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
3252 val32 |= (BIT(0) | BIT(1));
3253 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
3254
3255 val32 = rtl8xxxu_read32(priv, REG_RFE_CTRL_ANTA_SRC);
3256 val32 &= 0xffffff00;
3257 val32 |= 0x77;
3258 rtl8xxxu_write32(priv, REG_RFE_CTRL_ANTA_SRC, val32);
3259
3260 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
3261 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
3262 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
3263 }
3264
3265 static int
3266 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv)
3267 {
3268 struct rtl8xxxu_reg8val *array = priv->fops->mactable;
3269 int i, ret;
3270 u16 reg;
3271 u8 val;
3272
3273 for (i = 0; ; i++) {
3274 reg = array[i].reg;
3275 val = array[i].val;
3276
3277 if (reg == 0xffff && val == 0xff)
3278 break;
3279
3280 ret = rtl8xxxu_write8(priv, reg, val);
3281 if (ret != 1) {
3282 dev_warn(&priv->udev->dev,
3283 "Failed to initialize MAC "
3284 "(reg: %04x, val %02x)\n", reg, val);
3285 return -EAGAIN;
3286 }
3287 }
3288
3289 if (priv->rtl_chip != RTL8723B)
3290 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
3291
3292 return 0;
3293 }
3294
3295 static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
3296 struct rtl8xxxu_reg32val *array)
3297 {
3298 int i, ret;
3299 u16 reg;
3300 u32 val;
3301
3302 for (i = 0; ; i++) {
3303 reg = array[i].reg;
3304 val = array[i].val;
3305
3306 if (reg == 0xffff && val == 0xffffffff)
3307 break;
3308
3309 ret = rtl8xxxu_write32(priv, reg, val);
3310 if (ret != sizeof(val)) {
3311 dev_warn(&priv->udev->dev,
3312 "Failed to initialize PHY\n");
3313 return -EAGAIN;
3314 }
3315 udelay(1);
3316 }
3317
3318 return 0;
3319 }
3320
3321 /*
3322 * Most of this is black magic retrieved from the old rtl8723au driver
3323 */
3324 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
3325 {
3326 u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
3327 u16 val16;
3328 u32 val32;
3329
3330 /*
3331 * Todo: The vendor driver maintains a table of PHY register
3332 * addresses, which is initialized here. Do we need this?
3333 */
3334
3335 if (priv->rtl_chip == RTL8723B) {
3336 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3337 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB |
3338 SYS_FUNC_DIO_RF;
3339 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3340
3341 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
3342 } else {
3343 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
3344 udelay(2);
3345 val8 |= AFE_PLL_320_ENABLE;
3346 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
3347 udelay(2);
3348
3349 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
3350 udelay(2);
3351
3352 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3353 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
3354 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3355 }
3356
3357 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E) {
3358 /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
3359 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
3360 val32 &= ~AFE_XTAL_RF_GATE;
3361 if (priv->has_bluetooth)
3362 val32 &= ~AFE_XTAL_BT_GATE;
3363 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
3364 }
3365
3366 /* 6. 0x1f[7:0] = 0x07 */
3367 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
3368 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
3369
3370 if (priv->hi_pa)
3371 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
3372 else if (priv->tx_paths == 2)
3373 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
3374 else if (priv->rtl_chip == RTL8723B) {
3375 /*
3376 * Why?
3377 */
3378 rtl8xxxu_write8(priv, REG_SYS_FUNC, 0xe3);
3379 rtl8xxxu_write8(priv, REG_AFE_XTAL_CTRL + 1, 0x80);
3380 rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table);
3381 } else
3382 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
3383
3384
3385 if (priv->rtl_chip == RTL8188C && priv->hi_pa &&
3386 priv->vendor_umc && priv->chip_cut == 1)
3387 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
3388
3389 if (priv->tx_paths == 1 && priv->rx_paths == 2) {
3390 /*
3391 * For 1T2R boards, patch the registers.
3392 *
3393 * It looks like 8191/2 1T2R boards use path B for TX
3394 */
3395 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
3396 val32 &= ~(BIT(0) | BIT(1));
3397 val32 |= BIT(1);
3398 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
3399
3400 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
3401 val32 &= ~0x300033;
3402 val32 |= 0x200022;
3403 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
3404
3405 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
3406 val32 &= 0xff000000;
3407 val32 |= 0x45000000;
3408 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
3409
3410 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
3411 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
3412 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
3413 OFDM_RF_PATH_TX_B);
3414 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
3415
3416 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
3417 val32 &= ~(BIT(4) | BIT(5));
3418 val32 |= BIT(4);
3419 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
3420
3421 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
3422 val32 &= ~(BIT(27) | BIT(26));
3423 val32 |= BIT(27);
3424 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
3425
3426 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
3427 val32 &= ~(BIT(27) | BIT(26));
3428 val32 |= BIT(27);
3429 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
3430
3431 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
3432 val32 &= ~(BIT(27) | BIT(26));
3433 val32 |= BIT(27);
3434 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
3435
3436 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
3437 val32 &= ~(BIT(27) | BIT(26));
3438 val32 |= BIT(27);
3439 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
3440
3441 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
3442 val32 &= ~(BIT(27) | BIT(26));
3443 val32 |= BIT(27);
3444 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
3445 }
3446
3447 if (priv->rtl_chip == RTL8723B)
3448 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table);
3449 else if (priv->hi_pa)
3450 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
3451 else
3452 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
3453
3454 if (priv->has_xtalk) {
3455 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
3456
3457 val8 = priv->xtalk;
3458 val32 &= 0xff000fff;
3459 val32 |= ((val8 | (val8 << 6)) << 12);
3460
3461 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
3462 }
3463
3464 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E) {
3465 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
3466 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
3467 ldohci12 = 0x57;
3468 lpldo = 1;
3469 val32 = (lpldo << 24) | (ldohci12 << 16) |
3470 (ldov12d << 8) | ldoa15;
3471
3472 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
3473 }
3474
3475 return 0;
3476 }
3477
3478 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
3479 struct rtl8xxxu_rfregval *array,
3480 enum rtl8xxxu_rfpath path)
3481 {
3482 int i, ret;
3483 u8 reg;
3484 u32 val;
3485
3486 for (i = 0; ; i++) {
3487 reg = array[i].reg;
3488 val = array[i].val;
3489
3490 if (reg == 0xff && val == 0xffffffff)
3491 break;
3492
3493 switch (reg) {
3494 case 0xfe:
3495 msleep(50);
3496 continue;
3497 case 0xfd:
3498 mdelay(5);
3499 continue;
3500 case 0xfc:
3501 mdelay(1);
3502 continue;
3503 case 0xfb:
3504 udelay(50);
3505 continue;
3506 case 0xfa:
3507 udelay(5);
3508 continue;
3509 case 0xf9:
3510 udelay(1);
3511 continue;
3512 }
3513
3514 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
3515 if (ret) {
3516 dev_warn(&priv->udev->dev,
3517 "Failed to initialize RF\n");
3518 return -EAGAIN;
3519 }
3520 udelay(1);
3521 }
3522
3523 return 0;
3524 }
3525
3526 static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
3527 struct rtl8xxxu_rfregval *table,
3528 enum rtl8xxxu_rfpath path)
3529 {
3530 u32 val32;
3531 u16 val16, rfsi_rfenv;
3532 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
3533
3534 switch (path) {
3535 case RF_A:
3536 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
3537 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
3538 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
3539 break;
3540 case RF_B:
3541 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
3542 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
3543 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
3544 break;
3545 default:
3546 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
3547 __func__, path + 'A');
3548 return -EINVAL;
3549 }
3550 /* For path B, use XB */
3551 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
3552 rfsi_rfenv &= FPGA0_RF_RFENV;
3553
3554 /*
3555 * These two we might be able to optimize into one
3556 */
3557 val32 = rtl8xxxu_read32(priv, reg_int_oe);
3558 val32 |= BIT(20); /* 0x10 << 16 */
3559 rtl8xxxu_write32(priv, reg_int_oe, val32);
3560 udelay(1);
3561
3562 val32 = rtl8xxxu_read32(priv, reg_int_oe);
3563 val32 |= BIT(4);
3564 rtl8xxxu_write32(priv, reg_int_oe, val32);
3565 udelay(1);
3566
3567 /*
3568 * These two we might be able to optimize into one
3569 */
3570 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3571 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
3572 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3573 udelay(1);
3574
3575 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3576 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
3577 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3578 udelay(1);
3579
3580 rtl8xxxu_init_rf_regs(priv, table, path);
3581
3582 /* For path B, use XB */
3583 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
3584 val16 &= ~FPGA0_RF_RFENV;
3585 val16 |= rfsi_rfenv;
3586 rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
3587
3588 return 0;
3589 }
3590
3591 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
3592 {
3593 int ret = -EBUSY;
3594 int count = 0;
3595 u32 value;
3596
3597 value = LLT_OP_WRITE | address << 8 | data;
3598
3599 rtl8xxxu_write32(priv, REG_LLT_INIT, value);
3600
3601 do {
3602 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
3603 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
3604 ret = 0;
3605 break;
3606 }
3607 } while (count++ < 20);
3608
3609 return ret;
3610 }
3611
3612 static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3613 {
3614 int ret;
3615 int i;
3616
3617 for (i = 0; i < last_tx_page; i++) {
3618 ret = rtl8xxxu_llt_write(priv, i, i + 1);
3619 if (ret)
3620 goto exit;
3621 }
3622
3623 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
3624 if (ret)
3625 goto exit;
3626
3627 /* Mark remaining pages as a ring buffer */
3628 for (i = last_tx_page + 1; i < 0xff; i++) {
3629 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
3630 if (ret)
3631 goto exit;
3632 }
3633
3634 /* Let last entry point to the start entry of ring buffer */
3635 ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
3636 if (ret)
3637 goto exit;
3638
3639 exit:
3640 return ret;
3641 }
3642
3643 static int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3644 {
3645 u32 val32;
3646 int ret = 0;
3647 int i;
3648
3649 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3650 val32 |= AUTO_LLT_INIT_LLT;
3651 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
3652
3653 for (i = 500; i; i--) {
3654 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3655 if (!(val32 & AUTO_LLT_INIT_LLT))
3656 break;
3657 usleep_range(2, 4);
3658 }
3659
3660 if (!i) {
3661 ret = -EBUSY;
3662 dev_warn(&priv->udev->dev, "LLT table init failed\n");
3663 }
3664
3665 return ret;
3666 }
3667
3668 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
3669 {
3670 u16 val16, hi, lo;
3671 u16 hiq, mgq, bkq, beq, viq, voq;
3672 int hip, mgp, bkp, bep, vip, vop;
3673 int ret = 0;
3674
3675 switch (priv->ep_tx_count) {
3676 case 1:
3677 if (priv->ep_tx_high_queue) {
3678 hi = TRXDMA_QUEUE_HIGH;
3679 } else if (priv->ep_tx_low_queue) {
3680 hi = TRXDMA_QUEUE_LOW;
3681 } else if (priv->ep_tx_normal_queue) {
3682 hi = TRXDMA_QUEUE_NORMAL;
3683 } else {
3684 hi = 0;
3685 ret = -EINVAL;
3686 }
3687
3688 hiq = hi;
3689 mgq = hi;
3690 bkq = hi;
3691 beq = hi;
3692 viq = hi;
3693 voq = hi;
3694
3695 hip = 0;
3696 mgp = 0;
3697 bkp = 0;
3698 bep = 0;
3699 vip = 0;
3700 vop = 0;
3701 break;
3702 case 2:
3703 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
3704 hi = TRXDMA_QUEUE_HIGH;
3705 lo = TRXDMA_QUEUE_LOW;
3706 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
3707 hi = TRXDMA_QUEUE_NORMAL;
3708 lo = TRXDMA_QUEUE_LOW;
3709 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
3710 hi = TRXDMA_QUEUE_HIGH;
3711 lo = TRXDMA_QUEUE_NORMAL;
3712 } else {
3713 ret = -EINVAL;
3714 hi = 0;
3715 lo = 0;
3716 }
3717
3718 hiq = hi;
3719 mgq = hi;
3720 bkq = lo;
3721 beq = lo;
3722 viq = hi;
3723 voq = hi;
3724
3725 hip = 0;
3726 mgp = 0;
3727 bkp = 1;
3728 bep = 1;
3729 vip = 0;
3730 vop = 0;
3731 break;
3732 case 3:
3733 beq = TRXDMA_QUEUE_LOW;
3734 bkq = TRXDMA_QUEUE_LOW;
3735 viq = TRXDMA_QUEUE_NORMAL;
3736 voq = TRXDMA_QUEUE_HIGH;
3737 mgq = TRXDMA_QUEUE_HIGH;
3738 hiq = TRXDMA_QUEUE_HIGH;
3739
3740 hip = hiq ^ 3;
3741 mgp = mgq ^ 3;
3742 bkp = bkq ^ 3;
3743 bep = beq ^ 3;
3744 vip = viq ^ 3;
3745 vop = viq ^ 3;
3746 break;
3747 default:
3748 ret = -EINVAL;
3749 }
3750
3751 /*
3752 * None of the vendor drivers are configuring the beacon
3753 * queue here .... why?
3754 */
3755 if (!ret) {
3756 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
3757 val16 &= 0x7;
3758 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
3759 (viq << TRXDMA_CTRL_VIQ_SHIFT) |
3760 (beq << TRXDMA_CTRL_BEQ_SHIFT) |
3761 (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
3762 (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
3763 (hiq << TRXDMA_CTRL_HIQ_SHIFT);
3764 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
3765
3766 priv->pipe_out[TXDESC_QUEUE_VO] =
3767 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
3768 priv->pipe_out[TXDESC_QUEUE_VI] =
3769 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
3770 priv->pipe_out[TXDESC_QUEUE_BE] =
3771 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
3772 priv->pipe_out[TXDESC_QUEUE_BK] =
3773 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
3774 priv->pipe_out[TXDESC_QUEUE_BEACON] =
3775 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3776 priv->pipe_out[TXDESC_QUEUE_MGNT] =
3777 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
3778 priv->pipe_out[TXDESC_QUEUE_HIGH] =
3779 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
3780 priv->pipe_out[TXDESC_QUEUE_CMD] =
3781 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3782 }
3783
3784 return ret;
3785 }
3786
3787 static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv,
3788 bool iqk_ok, int result[][8],
3789 int candidate, bool tx_only)
3790 {
3791 u32 oldval, x, tx0_a, reg;
3792 int y, tx0_c;
3793 u32 val32;
3794
3795 if (!iqk_ok)
3796 return;
3797
3798 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3799 oldval = val32 >> 22;
3800
3801 x = result[candidate][0];
3802 if ((x & 0x00000200) != 0)
3803 x = x | 0xfffffc00;
3804 tx0_a = (x * oldval) >> 8;
3805
3806 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3807 val32 &= ~0x3ff;
3808 val32 |= tx0_a;
3809 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3810
3811 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3812 val32 &= ~BIT(31);
3813 if ((x * oldval >> 7) & 0x1)
3814 val32 |= BIT(31);
3815 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3816
3817 y = result[candidate][1];
3818 if ((y & 0x00000200) != 0)
3819 y = y | 0xfffffc00;
3820 tx0_c = (y * oldval) >> 8;
3821
3822 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
3823 val32 &= ~0xf0000000;
3824 val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
3825 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
3826
3827 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3828 val32 &= ~0x003f0000;
3829 val32 |= ((tx0_c & 0x3f) << 16);
3830 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3831
3832 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3833 val32 &= ~BIT(29);
3834 if ((y * oldval >> 7) & 0x1)
3835 val32 |= BIT(29);
3836 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3837
3838 if (tx_only) {
3839 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3840 return;
3841 }
3842
3843 reg = result[candidate][2];
3844
3845 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3846 val32 &= ~0x3ff;
3847 val32 |= (reg & 0x3ff);
3848 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3849
3850 reg = result[candidate][3] & 0x3F;
3851
3852 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3853 val32 &= ~0xfc00;
3854 val32 |= ((reg << 10) & 0xfc00);
3855 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3856
3857 reg = (result[candidate][3] >> 6) & 0xF;
3858
3859 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
3860 val32 &= ~0xf0000000;
3861 val32 |= (reg << 28);
3862 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
3863 }
3864
3865 static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv,
3866 bool iqk_ok, int result[][8],
3867 int candidate, bool tx_only)
3868 {
3869 u32 oldval, x, tx1_a, reg;
3870 int y, tx1_c;
3871 u32 val32;
3872
3873 if (!iqk_ok)
3874 return;
3875
3876 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3877 oldval = val32 >> 22;
3878
3879 x = result[candidate][4];
3880 if ((x & 0x00000200) != 0)
3881 x = x | 0xfffffc00;
3882 tx1_a = (x * oldval) >> 8;
3883
3884 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3885 val32 &= ~0x3ff;
3886 val32 |= tx1_a;
3887 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3888
3889 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3890 val32 &= ~BIT(27);
3891 if ((x * oldval >> 7) & 0x1)
3892 val32 |= BIT(27);
3893 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3894
3895 y = result[candidate][5];
3896 if ((y & 0x00000200) != 0)
3897 y = y | 0xfffffc00;
3898 tx1_c = (y * oldval) >> 8;
3899
3900 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
3901 val32 &= ~0xf0000000;
3902 val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
3903 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
3904
3905 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3906 val32 &= ~0x003f0000;
3907 val32 |= ((tx1_c & 0x3f) << 16);
3908 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3909
3910 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3911 val32 &= ~BIT(25);
3912 if ((y * oldval >> 7) & 0x1)
3913 val32 |= BIT(25);
3914 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3915
3916 if (tx_only) {
3917 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3918 return;
3919 }
3920
3921 reg = result[candidate][6];
3922
3923 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3924 val32 &= ~0x3ff;
3925 val32 |= (reg & 0x3ff);
3926 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3927
3928 reg = result[candidate][7] & 0x3f;
3929
3930 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3931 val32 &= ~0xfc00;
3932 val32 |= ((reg << 10) & 0xfc00);
3933 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3934
3935 reg = (result[candidate][7] >> 6) & 0xf;
3936
3937 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
3938 val32 &= ~0x0000f000;
3939 val32 |= (reg << 12);
3940 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
3941 }
3942
3943 #define MAX_TOLERANCE 5
3944
3945 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
3946 int result[][8], int c1, int c2)
3947 {
3948 u32 i, j, diff, simubitmap, bound = 0;
3949 int candidate[2] = {-1, -1}; /* for path A and path B */
3950 bool retval = true;
3951
3952 if (priv->tx_paths > 1)
3953 bound = 8;
3954 else
3955 bound = 4;
3956
3957 simubitmap = 0;
3958
3959 for (i = 0; i < bound; i++) {
3960 diff = (result[c1][i] > result[c2][i]) ?
3961 (result[c1][i] - result[c2][i]) :
3962 (result[c2][i] - result[c1][i]);
3963 if (diff > MAX_TOLERANCE) {
3964 if ((i == 2 || i == 6) && !simubitmap) {
3965 if (result[c1][i] + result[c1][i + 1] == 0)
3966 candidate[(i / 4)] = c2;
3967 else if (result[c2][i] + result[c2][i + 1] == 0)
3968 candidate[(i / 4)] = c1;
3969 else
3970 simubitmap = simubitmap | (1 << i);
3971 } else {
3972 simubitmap = simubitmap | (1 << i);
3973 }
3974 }
3975 }
3976
3977 if (simubitmap == 0) {
3978 for (i = 0; i < (bound / 4); i++) {
3979 if (candidate[i] >= 0) {
3980 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3981 result[3][j] = result[candidate[i]][j];
3982 retval = false;
3983 }
3984 }
3985 return retval;
3986 } else if (!(simubitmap & 0x0f)) {
3987 /* path A OK */
3988 for (i = 0; i < 4; i++)
3989 result[3][i] = result[c1][i];
3990 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
3991 /* path B OK */
3992 for (i = 4; i < 8; i++)
3993 result[3][i] = result[c1][i];
3994 }
3995
3996 return false;
3997 }
3998
3999 static bool rtl8723bu_simularity_compare(struct rtl8xxxu_priv *priv,
4000 int result[][8], int c1, int c2)
4001 {
4002 u32 i, j, diff, simubitmap, bound = 0;
4003 int candidate[2] = {-1, -1}; /* for path A and path B */
4004 int tmp1, tmp2;
4005 bool retval = true;
4006
4007 if (priv->tx_paths > 1)
4008 bound = 8;
4009 else
4010 bound = 4;
4011
4012 simubitmap = 0;
4013
4014 for (i = 0; i < bound; i++) {
4015 if (i & 1) {
4016 if ((result[c1][i] & 0x00000200))
4017 tmp1 = result[c1][i] | 0xfffffc00;
4018 else
4019 tmp1 = result[c1][i];
4020
4021 if ((result[c2][i]& 0x00000200))
4022 tmp2 = result[c2][i] | 0xfffffc00;
4023 else
4024 tmp2 = result[c2][i];
4025 } else {
4026 tmp1 = result[c1][i];
4027 tmp2 = result[c2][i];
4028 }
4029
4030 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
4031
4032 if (diff > MAX_TOLERANCE) {
4033 if ((i == 2 || i == 6) && !simubitmap) {
4034 if (result[c1][i] + result[c1][i + 1] == 0)
4035 candidate[(i / 4)] = c2;
4036 else if (result[c2][i] + result[c2][i + 1] == 0)
4037 candidate[(i / 4)] = c1;
4038 else
4039 simubitmap = simubitmap | (1 << i);
4040 } else {
4041 simubitmap = simubitmap | (1 << i);
4042 }
4043 }
4044 }
4045
4046 if (simubitmap == 0) {
4047 for (i = 0; i < (bound / 4); i++) {
4048 if (candidate[i] >= 0) {
4049 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
4050 result[3][j] = result[candidate[i]][j];
4051 retval = false;
4052 }
4053 }
4054 return retval;
4055 } else {
4056 if (!(simubitmap & 0x03)) {
4057 /* path A TX OK */
4058 for (i = 0; i < 2; i++)
4059 result[3][i] = result[c1][i];
4060 }
4061
4062 if (!(simubitmap & 0x0c)) {
4063 /* path A RX OK */
4064 for (i = 2; i < 4; i++)
4065 result[3][i] = result[c1][i];
4066 }
4067
4068 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
4069 /* path B RX OK */
4070 for (i = 4; i < 6; i++)
4071 result[3][i] = result[c1][i];
4072 }
4073
4074 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
4075 /* path B RX OK */
4076 for (i = 6; i < 8; i++)
4077 result[3][i] = result[c1][i];
4078 }
4079 }
4080
4081 return false;
4082 }
4083
4084 static void
4085 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
4086 {
4087 int i;
4088
4089 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
4090 backup[i] = rtl8xxxu_read8(priv, reg[i]);
4091
4092 backup[i] = rtl8xxxu_read32(priv, reg[i]);
4093 }
4094
4095 static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
4096 const u32 *reg, u32 *backup)
4097 {
4098 int i;
4099
4100 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
4101 rtl8xxxu_write8(priv, reg[i], backup[i]);
4102
4103 rtl8xxxu_write32(priv, reg[i], backup[i]);
4104 }
4105
4106 static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
4107 u32 *backup, int count)
4108 {
4109 int i;
4110
4111 for (i = 0; i < count; i++)
4112 backup[i] = rtl8xxxu_read32(priv, regs[i]);
4113 }
4114
4115 static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
4116 u32 *backup, int count)
4117 {
4118 int i;
4119
4120 for (i = 0; i < count; i++)
4121 rtl8xxxu_write32(priv, regs[i], backup[i]);
4122 }
4123
4124
4125 static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
4126 bool path_a_on)
4127 {
4128 u32 path_on;
4129 int i;
4130
4131 if (priv->tx_paths == 1) {
4132 path_on = priv->fops->adda_1t_path_on;
4133 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init);
4134 } else {
4135 path_on = path_a_on ? priv->fops->adda_2t_path_on_a :
4136 priv->fops->adda_2t_path_on_b;
4137
4138 rtl8xxxu_write32(priv, regs[0], path_on);
4139 }
4140
4141 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
4142 rtl8xxxu_write32(priv, regs[i], path_on);
4143 }
4144
4145 static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
4146 const u32 *regs, u32 *backup)
4147 {
4148 int i = 0;
4149
4150 rtl8xxxu_write8(priv, regs[i], 0x3f);
4151
4152 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
4153 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
4154
4155 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
4156 }
4157
4158 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
4159 {
4160 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
4161 int result = 0;
4162
4163 /* path-A IQK setting */
4164 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
4165 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
4166 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
4167
4168 val32 = (priv->rf_paths > 1) ? 0x28160202 :
4169 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
4170 0x28160502;
4171 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
4172
4173 /* path-B IQK setting */
4174 if (priv->rf_paths > 1) {
4175 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
4176 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
4177 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
4178 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
4179 }
4180
4181 /* LO calibration setting */
4182 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
4183
4184 /* One shot, path A LOK & IQK */
4185 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4186 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4187
4188 mdelay(1);
4189
4190 /* Check failed */
4191 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4192 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4193 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4194 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
4195
4196 if (!(reg_eac & BIT(28)) &&
4197 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4198 ((reg_e9c & 0x03ff0000) != 0x00420000))
4199 result |= 0x01;
4200 else /* If TX not OK, ignore RX */
4201 goto out;
4202
4203 /* If TX is OK, check whether RX is OK */
4204 if (!(reg_eac & BIT(27)) &&
4205 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
4206 ((reg_eac & 0x03ff0000) != 0x00360000))
4207 result |= 0x02;
4208 else
4209 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
4210 __func__);
4211 out:
4212 return result;
4213 }
4214
4215 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
4216 {
4217 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4218 int result = 0;
4219
4220 /* One shot, path B LOK & IQK */
4221 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
4222 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
4223
4224 mdelay(1);
4225
4226 /* Check failed */
4227 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4228 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4229 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4230 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4231 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4232
4233 if (!(reg_eac & BIT(31)) &&
4234 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
4235 ((reg_ebc & 0x03ff0000) != 0x00420000))
4236 result |= 0x01;
4237 else
4238 goto out;
4239
4240 if (!(reg_eac & BIT(30)) &&
4241 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
4242 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
4243 result |= 0x02;
4244 else
4245 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
4246 __func__);
4247 out:
4248 return result;
4249 }
4250
4251 static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv)
4252 {
4253 u32 reg_eac, reg_e94, reg_e9c, path_sel, val32;
4254 int result = 0;
4255
4256 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4257
4258 /*
4259 * Leave IQK mode
4260 */
4261 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4262 val32 &= 0x000000ff;
4263 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4264
4265 /*
4266 * Enable path A PA in TX IQK mode
4267 */
4268 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4269 val32 |= 0x80000;
4270 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4271 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000);
4272 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f);
4273 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87);
4274
4275 /*
4276 * Tx IQK setting
4277 */
4278 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4279 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4280
4281 /* path-A IQK setting */
4282 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
4283 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
4284 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4285 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4286
4287 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea);
4288 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
4289 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4290 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4291
4292 /* LO calibration setting */
4293 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);
4294
4295 /*
4296 * Enter IQK mode
4297 */
4298 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4299 val32 &= 0x000000ff;
4300 val32 |= 0x80800000;
4301 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4302
4303 /*
4304 * The vendor driver indicates the USB module is always using
4305 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4306 */
4307 if (priv->rf_paths > 1)
4308 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4309 else
4310 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4311
4312 /*
4313 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4314 * No trace of this in the 8192eu or 8188eu vendor drivers.
4315 */
4316 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4317
4318 /* One shot, path A LOK & IQK */
4319 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4320 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4321
4322 mdelay(1);
4323
4324 /* Restore Ant Path */
4325 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4326 #ifdef RTL8723BU_BT
4327 /* GNT_BT = 1 */
4328 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4329 #endif
4330
4331 /*
4332 * Leave IQK mode
4333 */
4334 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4335 val32 &= 0x000000ff;
4336 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4337
4338 /* Check failed */
4339 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4340 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4341 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4342
4343 val32 = (reg_e9c >> 16) & 0x3ff;
4344 if (val32 & 0x200)
4345 val32 = 0x400 - val32;
4346
4347 if (!(reg_eac & BIT(28)) &&
4348 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4349 ((reg_e9c & 0x03ff0000) != 0x00420000) &&
4350 ((reg_e94 & 0x03ff0000) < 0x01100000) &&
4351 ((reg_e94 & 0x03ff0000) > 0x00f00000) &&
4352 val32 < 0xf)
4353 result |= 0x01;
4354 else /* If TX not OK, ignore RX */
4355 goto out;
4356
4357 out:
4358 return result;
4359 }
4360
4361 static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
4362 {
4363 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, path_sel, val32;
4364 int result = 0;
4365
4366 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4367
4368 /*
4369 * Leave IQK mode
4370 */
4371 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4372 val32 &= 0x000000ff;
4373 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4374
4375 /*
4376 * Enable path A PA in TX IQK mode
4377 */
4378 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4379 val32 |= 0x80000;
4380 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4381 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4382 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4383 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
4384
4385 /*
4386 * Tx IQK setting
4387 */
4388 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4389 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4390
4391 /* path-A IQK setting */
4392 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
4393 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
4394 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4395 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4396
4397 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0);
4398 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
4399 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4400 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4401
4402 /* LO calibration setting */
4403 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
4404
4405 /*
4406 * Enter IQK mode
4407 */
4408 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4409 val32 &= 0x000000ff;
4410 val32 |= 0x80800000;
4411 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4412
4413 /*
4414 * The vendor driver indicates the USB module is always using
4415 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4416 */
4417 if (priv->rf_paths > 1)
4418 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4419 else
4420 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4421
4422 /*
4423 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4424 * No trace of this in the 8192eu or 8188eu vendor drivers.
4425 */
4426 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4427
4428 /* One shot, path A LOK & IQK */
4429 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4430 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4431
4432 mdelay(1);
4433
4434 /* Restore Ant Path */
4435 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4436 #ifdef RTL8723BU_BT
4437 /* GNT_BT = 1 */
4438 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4439 #endif
4440
4441 /*
4442 * Leave IQK mode
4443 */
4444 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4445 val32 &= 0x000000ff;
4446 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4447
4448 /* Check failed */
4449 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4450 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4451 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4452
4453 val32 = (reg_e9c >> 16) & 0x3ff;
4454 if (val32 & 0x200)
4455 val32 = 0x400 - val32;
4456
4457 if (!(reg_eac & BIT(28)) &&
4458 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4459 ((reg_e9c & 0x03ff0000) != 0x00420000) &&
4460 ((reg_e94 & 0x03ff0000) < 0x01100000) &&
4461 ((reg_e94 & 0x03ff0000) > 0x00f00000) &&
4462 val32 < 0xf)
4463 result |= 0x01;
4464 else /* If TX not OK, ignore RX */
4465 goto out;
4466
4467 val32 = 0x80007c00 | (reg_e94 &0x3ff0000) |
4468 ((reg_e9c & 0x3ff0000) >> 16);
4469 rtl8xxxu_write32(priv, REG_TX_IQK, val32);
4470
4471 /*
4472 * Modify RX IQK mode
4473 */
4474 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4475 val32 &= 0x000000ff;
4476 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4477 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4478 val32 |= 0x80000;
4479 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4480 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4481 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4482 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77);
4483
4484 /*
4485 * PA, PAD setting
4486 */
4487 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0xf80);
4488 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f);
4489
4490 /*
4491 * RX IQK setting
4492 */
4493 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4494
4495 /* path-A IQK setting */
4496 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
4497 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
4498 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4499 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4500
4501 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000);
4502 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f);
4503 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4504 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4505
4506 /* LO calibration setting */
4507 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1);
4508
4509 /*
4510 * Enter IQK mode
4511 */
4512 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4513 val32 &= 0x000000ff;
4514 val32 |= 0x80800000;
4515 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4516
4517 if (priv->rf_paths > 1)
4518 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4519 else
4520 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4521
4522 /*
4523 * Disable BT
4524 */
4525 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4526
4527 /* One shot, path A LOK & IQK */
4528 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4529 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4530
4531 mdelay(1);
4532
4533 /* Restore Ant Path */
4534 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4535 #ifdef RTL8723BU_BT
4536 /* GNT_BT = 1 */
4537 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4538 #endif
4539
4540 /*
4541 * Leave IQK mode
4542 */
4543 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4544 val32 &= 0x000000ff;
4545 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4546
4547 /* Check failed */
4548 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4549 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
4550
4551 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x780);
4552
4553 val32 = (reg_eac >> 16) & 0x3ff;
4554 if (val32 & 0x200)
4555 val32 = 0x400 - val32;
4556
4557 if (!(reg_eac & BIT(27)) &&
4558 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
4559 ((reg_eac & 0x03ff0000) != 0x00360000) &&
4560 ((reg_ea4 & 0x03ff0000) < 0x01100000) &&
4561 ((reg_ea4 & 0x03ff0000) > 0x00f00000) &&
4562 val32 < 0xf)
4563 result |= 0x02;
4564 else /* If TX not OK, ignore RX */
4565 goto out;
4566 out:
4567 return result;
4568 }
4569
4570 #ifdef RTL8723BU_PATH_B
4571 static int rtl8723bu_iqk_path_b(struct rtl8xxxu_priv *priv)
4572 {
4573 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, path_sel;
4574 int result = 0;
4575
4576 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4577
4578 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4579 val32 &= 0x000000ff;
4580 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4581
4582 /* One shot, path B LOK & IQK */
4583 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
4584 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
4585
4586 mdelay(1);
4587
4588 /* Check failed */
4589 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4590 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4591 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4592 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4593 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4594
4595 if (!(reg_eac & BIT(31)) &&
4596 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
4597 ((reg_ebc & 0x03ff0000) != 0x00420000))
4598 result |= 0x01;
4599 else
4600 goto out;
4601
4602 if (!(reg_eac & BIT(30)) &&
4603 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
4604 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
4605 result |= 0x02;
4606 else
4607 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
4608 __func__);
4609 out:
4610 return result;
4611 }
4612 #endif
4613
4614 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
4615 int result[][8], int t)
4616 {
4617 struct device *dev = &priv->udev->dev;
4618 u32 i, val32;
4619 int path_a_ok, path_b_ok;
4620 int retry = 2;
4621 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
4622 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
4623 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
4624 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
4625 REG_TX_OFDM_BBON, REG_TX_TO_RX,
4626 REG_TX_TO_TX, REG_RX_CCK,
4627 REG_RX_OFDM, REG_RX_WAIT_RIFS,
4628 REG_RX_TO_RX, REG_STANDBY,
4629 REG_SLEEP, REG_PMPD_ANAEN
4630 };
4631 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
4632 REG_TXPAUSE, REG_BEACON_CTRL,
4633 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
4634 };
4635 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
4636 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
4637 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
4638 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
4639 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
4640 };
4641
4642 /*
4643 * Note: IQ calibration must be performed after loading
4644 * PHY_REG.txt , and radio_a, radio_b.txt
4645 */
4646
4647 if (t == 0) {
4648 /* Save ADDA parameters, turn Path A ADDA on */
4649 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
4650 RTL8XXXU_ADDA_REGS);
4651 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4652 rtl8xxxu_save_regs(priv, iqk_bb_regs,
4653 priv->bb_backup, RTL8XXXU_BB_REGS);
4654 }
4655
4656 rtl8xxxu_path_adda_on(priv, adda_regs, true);
4657
4658 if (t == 0) {
4659 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
4660 if (val32 & FPGA0_HSSI_PARM1_PI)
4661 priv->pi_enabled = 1;
4662 }
4663
4664 if (!priv->pi_enabled) {
4665 /* Switch BB to PI mode to do IQ Calibration. */
4666 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
4667 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
4668 }
4669
4670 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4671 val32 &= ~FPGA_RF_MODE_CCK;
4672 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4673
4674 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
4675 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
4676 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
4677
4678 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
4679 val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
4680 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4681
4682 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
4683 val32 &= ~BIT(10);
4684 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
4685 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
4686 val32 &= ~BIT(10);
4687 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
4688
4689 if (priv->tx_paths > 1) {
4690 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
4691 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
4692 }
4693
4694 /* MAC settings */
4695 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
4696
4697 /* Page B init */
4698 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
4699
4700 if (priv->tx_paths > 1)
4701 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
4702
4703 /* IQ calibration setting */
4704 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
4705 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4706 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4707
4708 for (i = 0; i < retry; i++) {
4709 path_a_ok = rtl8xxxu_iqk_path_a(priv);
4710 if (path_a_ok == 0x03) {
4711 val32 = rtl8xxxu_read32(priv,
4712 REG_TX_POWER_BEFORE_IQK_A);
4713 result[t][0] = (val32 >> 16) & 0x3ff;
4714 val32 = rtl8xxxu_read32(priv,
4715 REG_TX_POWER_AFTER_IQK_A);
4716 result[t][1] = (val32 >> 16) & 0x3ff;
4717 val32 = rtl8xxxu_read32(priv,
4718 REG_RX_POWER_BEFORE_IQK_A_2);
4719 result[t][2] = (val32 >> 16) & 0x3ff;
4720 val32 = rtl8xxxu_read32(priv,
4721 REG_RX_POWER_AFTER_IQK_A_2);
4722 result[t][3] = (val32 >> 16) & 0x3ff;
4723 break;
4724 } else if (i == (retry - 1) && path_a_ok == 0x01) {
4725 /* TX IQK OK */
4726 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
4727 __func__);
4728
4729 val32 = rtl8xxxu_read32(priv,
4730 REG_TX_POWER_BEFORE_IQK_A);
4731 result[t][0] = (val32 >> 16) & 0x3ff;
4732 val32 = rtl8xxxu_read32(priv,
4733 REG_TX_POWER_AFTER_IQK_A);
4734 result[t][1] = (val32 >> 16) & 0x3ff;
4735 }
4736 }
4737
4738 if (!path_a_ok)
4739 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
4740
4741 if (priv->tx_paths > 1) {
4742 /*
4743 * Path A into standby
4744 */
4745 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
4746 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
4747 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
4748
4749 /* Turn Path B ADDA on */
4750 rtl8xxxu_path_adda_on(priv, adda_regs, false);
4751
4752 for (i = 0; i < retry; i++) {
4753 path_b_ok = rtl8xxxu_iqk_path_b(priv);
4754 if (path_b_ok == 0x03) {
4755 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4756 result[t][4] = (val32 >> 16) & 0x3ff;
4757 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4758 result[t][5] = (val32 >> 16) & 0x3ff;
4759 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4760 result[t][6] = (val32 >> 16) & 0x3ff;
4761 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4762 result[t][7] = (val32 >> 16) & 0x3ff;
4763 break;
4764 } else if (i == (retry - 1) && path_b_ok == 0x01) {
4765 /* TX IQK OK */
4766 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4767 result[t][4] = (val32 >> 16) & 0x3ff;
4768 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4769 result[t][5] = (val32 >> 16) & 0x3ff;
4770 }
4771 }
4772
4773 if (!path_b_ok)
4774 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
4775 }
4776
4777 /* Back to BB mode, load original value */
4778 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
4779
4780 if (t) {
4781 if (!priv->pi_enabled) {
4782 /*
4783 * Switch back BB to SI mode after finishing
4784 * IQ Calibration
4785 */
4786 val32 = 0x01000000;
4787 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
4788 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
4789 }
4790
4791 /* Reload ADDA power saving parameters */
4792 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
4793 RTL8XXXU_ADDA_REGS);
4794
4795 /* Reload MAC parameters */
4796 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4797
4798 /* Reload BB parameters */
4799 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
4800 priv->bb_backup, RTL8XXXU_BB_REGS);
4801
4802 /* Restore RX initial gain */
4803 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
4804
4805 if (priv->tx_paths > 1) {
4806 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
4807 0x00032ed3);
4808 }
4809
4810 /* Load 0xe30 IQC default value */
4811 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
4812 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
4813 }
4814 }
4815
4816 static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
4817 int result[][8], int t)
4818 {
4819 struct device *dev = &priv->udev->dev;
4820 u32 i, val32;
4821 int path_a_ok /*, path_b_ok */;
4822 int retry = 2;
4823 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
4824 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
4825 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
4826 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
4827 REG_TX_OFDM_BBON, REG_TX_TO_RX,
4828 REG_TX_TO_TX, REG_RX_CCK,
4829 REG_RX_OFDM, REG_RX_WAIT_RIFS,
4830 REG_RX_TO_RX, REG_STANDBY,
4831 REG_SLEEP, REG_PMPD_ANAEN
4832 };
4833 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
4834 REG_TXPAUSE, REG_BEACON_CTRL,
4835 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
4836 };
4837 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
4838 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
4839 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
4840 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
4841 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
4842 };
4843 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff;
4844 u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff;
4845
4846 /*
4847 * Note: IQ calibration must be performed after loading
4848 * PHY_REG.txt , and radio_a, radio_b.txt
4849 */
4850
4851 if (t == 0) {
4852 /* Save ADDA parameters, turn Path A ADDA on */
4853 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
4854 RTL8XXXU_ADDA_REGS);
4855 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4856 rtl8xxxu_save_regs(priv, iqk_bb_regs,
4857 priv->bb_backup, RTL8XXXU_BB_REGS);
4858 }
4859
4860 rtl8xxxu_path_adda_on(priv, adda_regs, true);
4861
4862 /* MAC settings */
4863 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
4864
4865 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
4866 val32 |= 0x0f000000;
4867 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
4868
4869 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
4870 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
4871 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
4872
4873 #ifdef RTL8723BU_PATH_B
4874 /* Set RF mode to standby Path B */
4875 if (priv->tx_paths > 1)
4876 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x10000);
4877 #endif
4878
4879 #if 0
4880 /* Page B init */
4881 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x0f600000);
4882
4883 if (priv->tx_paths > 1)
4884 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x0f600000);
4885 #endif
4886
4887 /*
4888 * RX IQ calibration setting for 8723B D cut large current issue
4889 * when leaving IPS
4890 */
4891 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4892 val32 &= 0x000000ff;
4893 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4894
4895 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4896 val32 |= 0x80000;
4897 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4898
4899 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4900 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4901 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
4902
4903 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
4904 val32 |= 0x20;
4905 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
4906
4907 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd);
4908
4909 for (i = 0; i < retry; i++) {
4910 path_a_ok = rtl8723bu_iqk_path_a(priv);
4911 if (path_a_ok == 0x01) {
4912 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4913 val32 &= 0x000000ff;
4914 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4915
4916 #if 0 /* Only needed in restore case, we may need this when going to suspend */
4917 priv->RFCalibrateInfo.TxLOK[RF_A] =
4918 rtl8xxxu_read_rfreg(priv, RF_A,
4919 RF6052_REG_TXM_IDAC);
4920 #endif
4921
4922 val32 = rtl8xxxu_read32(priv,
4923 REG_TX_POWER_BEFORE_IQK_A);
4924 result[t][0] = (val32 >> 16) & 0x3ff;
4925 val32 = rtl8xxxu_read32(priv,
4926 REG_TX_POWER_AFTER_IQK_A);
4927 result[t][1] = (val32 >> 16) & 0x3ff;
4928
4929 break;
4930 }
4931 }
4932
4933 if (!path_a_ok)
4934 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);
4935
4936 for (i = 0; i < retry; i++) {
4937 path_a_ok = rtl8723bu_rx_iqk_path_a(priv);
4938 if (path_a_ok == 0x03) {
4939 val32 = rtl8xxxu_read32(priv,
4940 REG_RX_POWER_BEFORE_IQK_A_2);
4941 result[t][2] = (val32 >> 16) & 0x3ff;
4942 val32 = rtl8xxxu_read32(priv,
4943 REG_RX_POWER_AFTER_IQK_A_2);
4944 result[t][3] = (val32 >> 16) & 0x3ff;
4945
4946 break;
4947 }
4948 }
4949
4950 if (!path_a_ok)
4951 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);
4952
4953 if (priv->tx_paths > 1) {
4954 #if 1
4955 dev_warn(dev, "%s: Path B not supported\n", __func__);
4956 #else
4957
4958 /*
4959 * Path A into standby
4960 */
4961 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4962 val32 &= 0x000000ff;
4963 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4964 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000);
4965
4966 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4967 val32 &= 0x000000ff;
4968 val32 |= 0x80800000;
4969 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4970
4971 /* Turn Path B ADDA on */
4972 rtl8xxxu_path_adda_on(priv, adda_regs, false);
4973
4974 for (i = 0; i < retry; i++) {
4975 path_b_ok = rtl8xxxu_iqk_path_b(priv);
4976 if (path_b_ok == 0x03) {
4977 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4978 result[t][4] = (val32 >> 16) & 0x3ff;
4979 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4980 result[t][5] = (val32 >> 16) & 0x3ff;
4981 break;
4982 }
4983 }
4984
4985 if (!path_b_ok)
4986 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
4987
4988 for (i = 0; i < retry; i++) {
4989 path_b_ok = rtl8723bu_rx_iqk_path_b(priv);
4990 if (path_a_ok == 0x03) {
4991 val32 = rtl8xxxu_read32(priv,
4992 REG_RX_POWER_BEFORE_IQK_B_2);
4993 result[t][6] = (val32 >> 16) & 0x3ff;
4994 val32 = rtl8xxxu_read32(priv,
4995 REG_RX_POWER_AFTER_IQK_B_2);
4996 result[t][7] = (val32 >> 16) & 0x3ff;
4997 break;
4998 }
4999 }
5000
5001 if (!path_b_ok)
5002 dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__);
5003 #endif
5004 }
5005
5006 /* Back to BB mode, load original value */
5007 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
5008 val32 &= 0x000000ff;
5009 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
5010
5011 if (t) {
5012 /* Reload ADDA power saving parameters */
5013 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
5014 RTL8XXXU_ADDA_REGS);
5015
5016 /* Reload MAC parameters */
5017 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
5018
5019 /* Reload BB parameters */
5020 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
5021 priv->bb_backup, RTL8XXXU_BB_REGS);
5022
5023 /* Restore RX initial gain */
5024 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
5025 val32 &= 0xffffff00;
5026 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50);
5027 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc);
5028
5029 if (priv->tx_paths > 1) {
5030 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);
5031 val32 &= 0xffffff00;
5032 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
5033 val32 | 0x50);
5034 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
5035 val32 | xb_agc);
5036 }
5037
5038 /* Load 0xe30 IQC default value */
5039 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
5040 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
5041 }
5042 }
5043
5044 static void rtl8xxxu_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start)
5045 {
5046 struct h2c_cmd h2c;
5047
5048 if (priv->fops->mbox_ext_width < 4)
5049 return;
5050
5051 memset(&h2c, 0, sizeof(struct h2c_cmd));
5052 h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION;
5053 h2c.bt_wlan_calibration.data = start;
5054
5055 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration));
5056 }
5057
5058 static void rtl8723au_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
5059 {
5060 struct device *dev = &priv->udev->dev;
5061 int result[4][8]; /* last is final result */
5062 int i, candidate;
5063 bool path_a_ok, path_b_ok;
5064 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
5065 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
5066 s32 reg_tmp = 0;
5067 bool simu;
5068
5069 rtl8xxxu_prepare_calibrate(priv, 1);
5070
5071 memset(result, 0, sizeof(result));
5072 candidate = -1;
5073
5074 path_a_ok = false;
5075 path_b_ok = false;
5076
5077 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
5078
5079 for (i = 0; i < 3; i++) {
5080 rtl8xxxu_phy_iqcalibrate(priv, result, i);
5081
5082 if (i == 1) {
5083 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
5084 if (simu) {
5085 candidate = 0;
5086 break;
5087 }
5088 }
5089
5090 if (i == 2) {
5091 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
5092 if (simu) {
5093 candidate = 0;
5094 break;
5095 }
5096
5097 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
5098 if (simu) {
5099 candidate = 1;
5100 } else {
5101 for (i = 0; i < 8; i++)
5102 reg_tmp += result[3][i];
5103
5104 if (reg_tmp)
5105 candidate = 3;
5106 else
5107 candidate = -1;
5108 }
5109 }
5110 }
5111
5112 for (i = 0; i < 4; i++) {
5113 reg_e94 = result[i][0];
5114 reg_e9c = result[i][1];
5115 reg_ea4 = result[i][2];
5116 reg_eac = result[i][3];
5117 reg_eb4 = result[i][4];
5118 reg_ebc = result[i][5];
5119 reg_ec4 = result[i][6];
5120 reg_ecc = result[i][7];
5121 }
5122
5123 if (candidate >= 0) {
5124 reg_e94 = result[candidate][0];
5125 priv->rege94 = reg_e94;
5126 reg_e9c = result[candidate][1];
5127 priv->rege9c = reg_e9c;
5128 reg_ea4 = result[candidate][2];
5129 reg_eac = result[candidate][3];
5130 reg_eb4 = result[candidate][4];
5131 priv->regeb4 = reg_eb4;
5132 reg_ebc = result[candidate][5];
5133 priv->regebc = reg_ebc;
5134 reg_ec4 = result[candidate][6];
5135 reg_ecc = result[candidate][7];
5136 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
5137 dev_dbg(dev,
5138 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
5139 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
5140 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
5141 path_a_ok = true;
5142 path_b_ok = true;
5143 } else {
5144 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
5145 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
5146 }
5147
5148 if (reg_e94 && candidate >= 0)
5149 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
5150 candidate, (reg_ea4 == 0));
5151
5152 if (priv->tx_paths > 1 && reg_eb4)
5153 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
5154 candidate, (reg_ec4 == 0));
5155
5156 rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
5157 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
5158
5159 rtl8xxxu_prepare_calibrate(priv, 0);
5160 }
5161
5162 static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
5163 {
5164 struct device *dev = &priv->udev->dev;
5165 int result[4][8]; /* last is final result */
5166 int i, candidate;
5167 bool path_a_ok, path_b_ok;
5168 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
5169 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
5170 u32 val32, bt_control;
5171 s32 reg_tmp = 0;
5172 bool simu;
5173
5174 rtl8xxxu_prepare_calibrate(priv, 1);
5175
5176 memset(result, 0, sizeof(result));
5177 candidate = -1;
5178
5179 path_a_ok = false;
5180 path_b_ok = false;
5181
5182 bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU);
5183
5184 for (i = 0; i < 3; i++) {
5185 rtl8723bu_phy_iqcalibrate(priv, result, i);
5186
5187 if (i == 1) {
5188 simu = rtl8723bu_simularity_compare(priv, result, 0, 1);
5189 if (simu) {
5190 candidate = 0;
5191 break;
5192 }
5193 }
5194
5195 if (i == 2) {
5196 simu = rtl8723bu_simularity_compare(priv, result, 0, 2);
5197 if (simu) {
5198 candidate = 0;
5199 break;
5200 }
5201
5202 simu = rtl8723bu_simularity_compare(priv, result, 1, 2);
5203 if (simu) {
5204 candidate = 1;
5205 } else {
5206 for (i = 0; i < 8; i++)
5207 reg_tmp += result[3][i];
5208
5209 if (reg_tmp)
5210 candidate = 3;
5211 else
5212 candidate = -1;
5213 }
5214 }
5215 }
5216
5217 for (i = 0; i < 4; i++) {
5218 reg_e94 = result[i][0];
5219 reg_e9c = result[i][1];
5220 reg_ea4 = result[i][2];
5221 reg_eac = result[i][3];
5222 reg_eb4 = result[i][4];
5223 reg_ebc = result[i][5];
5224 reg_ec4 = result[i][6];
5225 reg_ecc = result[i][7];
5226 }
5227
5228 if (candidate >= 0) {
5229 reg_e94 = result[candidate][0];
5230 priv->rege94 = reg_e94;
5231 reg_e9c = result[candidate][1];
5232 priv->rege9c = reg_e9c;
5233 reg_ea4 = result[candidate][2];
5234 reg_eac = result[candidate][3];
5235 reg_eb4 = result[candidate][4];
5236 priv->regeb4 = reg_eb4;
5237 reg_ebc = result[candidate][5];
5238 priv->regebc = reg_ebc;
5239 reg_ec4 = result[candidate][6];
5240 reg_ecc = result[candidate][7];
5241 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
5242 dev_dbg(dev,
5243 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
5244 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
5245 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
5246 path_a_ok = true;
5247 path_b_ok = true;
5248 } else {
5249 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
5250 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
5251 }
5252
5253 if (reg_e94 && candidate >= 0)
5254 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
5255 candidate, (reg_ea4 == 0));
5256
5257 if (priv->tx_paths > 1 && reg_eb4)
5258 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
5259 candidate, (reg_ec4 == 0));
5260
5261 rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
5262 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
5263
5264 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control);
5265
5266 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
5267 val32 |= 0x80000;
5268 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
5269 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000);
5270 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
5271 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177);
5272 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
5273 val32 |= 0x20;
5274 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
5275 rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd);
5276
5277 if (priv->rf_paths > 1) {
5278 dev_dbg(dev, "%s: beware 2T not yet supported\n", __func__);
5279 #ifdef RTL8723BU_PATH_B
5280 if (RF_Path == 0x0) //S1
5281 ODM_SetIQCbyRFpath(pDM_Odm, 0);
5282 else //S0
5283 ODM_SetIQCbyRFpath(pDM_Odm, 1);
5284 #endif
5285 }
5286 rtl8xxxu_prepare_calibrate(priv, 0);
5287 }
5288
5289 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
5290 {
5291 u32 val32;
5292 u32 rf_amode, rf_bmode = 0, lstf;
5293
5294 /* Check continuous TX and Packet TX */
5295 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
5296
5297 if (lstf & OFDM_LSTF_MASK) {
5298 /* Disable all continuous TX */
5299 val32 = lstf & ~OFDM_LSTF_MASK;
5300 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
5301
5302 /* Read original RF mode Path A */
5303 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
5304
5305 /* Set RF mode to standby Path A */
5306 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
5307 (rf_amode & 0x8ffff) | 0x10000);
5308
5309 /* Path-B */
5310 if (priv->tx_paths > 1) {
5311 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
5312 RF6052_REG_AC);
5313
5314 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
5315 (rf_bmode & 0x8ffff) | 0x10000);
5316 }
5317 } else {
5318 /* Deal with Packet TX case */
5319 /* block all queues */
5320 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5321 }
5322
5323 /* Start LC calibration */
5324 if (priv->fops->has_s0s1)
5325 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0);
5326 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
5327 val32 |= 0x08000;
5328 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
5329
5330 msleep(100);
5331
5332 if (priv->fops->has_s0s1)
5333 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0);
5334
5335 /* Restore original parameters */
5336 if (lstf & OFDM_LSTF_MASK) {
5337 /* Path-A */
5338 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
5339 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
5340
5341 /* Path-B */
5342 if (priv->tx_paths > 1)
5343 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
5344 rf_bmode);
5345 } else /* Deal with Packet TX case */
5346 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
5347 }
5348
5349 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
5350 {
5351 int i;
5352 u16 reg;
5353
5354 reg = REG_MACID;
5355
5356 for (i = 0; i < ETH_ALEN; i++)
5357 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
5358
5359 return 0;
5360 }
5361
5362 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
5363 {
5364 int i;
5365 u16 reg;
5366
5367 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
5368
5369 reg = REG_BSSID;
5370
5371 for (i = 0; i < ETH_ALEN; i++)
5372 rtl8xxxu_write8(priv, reg + i, bssid[i]);
5373
5374 return 0;
5375 }
5376
5377 static void
5378 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
5379 {
5380 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
5381 u8 max_agg = 0xf;
5382 int i;
5383
5384 ampdu_factor = 1 << (ampdu_factor + 2);
5385 if (ampdu_factor > max_agg)
5386 ampdu_factor = max_agg;
5387
5388 for (i = 0; i < 4; i++) {
5389 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
5390 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
5391
5392 if ((vals[i] & 0x0f) > ampdu_factor)
5393 vals[i] = (vals[i] & 0xf0) | ampdu_factor;
5394
5395 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
5396 }
5397 }
5398
5399 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
5400 {
5401 u8 val8;
5402
5403 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
5404 val8 &= 0xf8;
5405 val8 |= density;
5406 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
5407 }
5408
5409 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
5410 {
5411 u8 val8;
5412 int count, ret;
5413
5414 /* Start of rtl8723AU_card_enable_flow */
5415 /* Act to Cardemu sequence*/
5416 /* Turn off RF */
5417 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
5418
5419 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
5420 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
5421 val8 &= ~LEDCFG2_DPDT_SELECT;
5422 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
5423
5424 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
5425 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5426 val8 |= BIT(1);
5427 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5428
5429 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5430 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5431 if ((val8 & BIT(1)) == 0)
5432 break;
5433 udelay(10);
5434 }
5435
5436 if (!count) {
5437 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
5438 __func__);
5439 ret = -EBUSY;
5440 goto exit;
5441 }
5442
5443 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
5444 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5445 val8 |= SYS_ISO_ANALOG_IPS;
5446 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5447
5448 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
5449 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5450 val8 &= ~LDOA15_ENABLE;
5451 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5452
5453 exit:
5454 return ret;
5455 }
5456
5457 static int rtl8723bu_active_to_emu(struct rtl8xxxu_priv *priv)
5458 {
5459 u8 val8;
5460 u16 val16;
5461 u32 val32;
5462 int count, ret;
5463
5464 /* Turn off RF */
5465 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
5466
5467 /* Enable rising edge triggering interrupt */
5468 val16 = rtl8xxxu_read16(priv, REG_GPIO_INTM);
5469 val16 &= ~GPIO_INTM_EDGE_TRIG_IRQ;
5470 rtl8xxxu_write16(priv, REG_GPIO_INTM, val16);
5471
5472 /* Release WLON reset 0x04[16]= 1*/
5473 val32 = rtl8xxxu_read32(priv, REG_GPIO_INTM);
5474 val32 |= APS_FSMCO_WLON_RESET;
5475 rtl8xxxu_write32(priv, REG_GPIO_INTM, val32);
5476
5477 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
5478 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5479 val8 |= BIT(1);
5480 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5481
5482 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5483 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5484 if ((val8 & BIT(1)) == 0)
5485 break;
5486 udelay(10);
5487 }
5488
5489 if (!count) {
5490 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
5491 __func__);
5492 ret = -EBUSY;
5493 goto exit;
5494 }
5495
5496 /* Enable BT control XTAL setting */
5497 val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
5498 val8 &= ~AFE_MISC_WL_XTAL_CTRL;
5499 rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
5500
5501 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
5502 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5503 val8 |= SYS_ISO_ANALOG_IPS;
5504 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5505
5506 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
5507 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5508 val8 &= ~LDOA15_ENABLE;
5509 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5510
5511 exit:
5512 return ret;
5513 }
5514
5515 static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
5516 {
5517 u8 val8;
5518 u8 val32;
5519 int count, ret;
5520
5521 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5522
5523 /*
5524 * Poll - wait for RX packet to complete
5525 */
5526 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5527 val32 = rtl8xxxu_read32(priv, 0x5f8);
5528 if (!val32)
5529 break;
5530 udelay(10);
5531 }
5532
5533 if (!count) {
5534 dev_warn(&priv->udev->dev,
5535 "%s: RX poll timed out (0x05f8)\n", __func__);
5536 ret = -EBUSY;
5537 goto exit;
5538 }
5539
5540 /* Disable CCK and OFDM, clock gated */
5541 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
5542 val8 &= ~SYS_FUNC_BBRSTB;
5543 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
5544
5545 udelay(2);
5546
5547 /* Reset baseband */
5548 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
5549 val8 &= ~SYS_FUNC_BB_GLB_RSTN;
5550 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
5551
5552 /* Reset MAC TRX */
5553 val8 = rtl8xxxu_read8(priv, REG_CR);
5554 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
5555 rtl8xxxu_write8(priv, REG_CR, val8);
5556
5557 /* Reset MAC TRX */
5558 val8 = rtl8xxxu_read8(priv, REG_CR + 1);
5559 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
5560 rtl8xxxu_write8(priv, REG_CR + 1, val8);
5561
5562 /* Respond TX OK to scheduler */
5563 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
5564 val8 |= DUAL_TSF_TX_OK;
5565 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
5566
5567 exit:
5568 return ret;
5569 }
5570
5571 static void rtl8723a_disabled_to_emu(struct rtl8xxxu_priv *priv)
5572 {
5573 u8 val8;
5574
5575 /* Clear suspend enable and power down enable*/
5576 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5577 val8 &= ~(BIT(3) | BIT(7));
5578 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5579
5580 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
5581 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
5582 val8 &= ~BIT(0);
5583 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
5584
5585 /* 0x04[12:11] = 11 enable WL suspend*/
5586 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5587 val8 &= ~(BIT(3) | BIT(4));
5588 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5589 }
5590
5591 static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv)
5592 {
5593 u8 val8;
5594
5595 /* Clear suspend enable and power down enable*/
5596 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5597 val8 &= ~(BIT(3) | BIT(4));
5598 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5599 }
5600
5601 static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv)
5602 {
5603 u8 val8;
5604 u32 val32;
5605 int count, ret = 0;
5606
5607 /* disable HWPDN 0x04[15]=0*/
5608 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5609 val8 &= ~BIT(7);
5610 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5611
5612 /* disable SW LPS 0x04[10]= 0 */
5613 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5614 val8 &= ~BIT(2);
5615 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5616
5617 /* disable WL suspend*/
5618 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5619 val8 &= ~(BIT(3) | BIT(4));
5620 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5621
5622 /* wait till 0x04[17] = 1 power ready*/
5623 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5624 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5625 if (val32 & BIT(17))
5626 break;
5627
5628 udelay(10);
5629 }
5630
5631 if (!count) {
5632 ret = -EBUSY;
5633 goto exit;
5634 }
5635
5636 /* We should be able to optimize the following three entries into one */
5637
5638 /* release WLON reset 0x04[16]= 1*/
5639 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5640 val8 |= BIT(0);
5641 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5642
5643 /* set, then poll until 0 */
5644 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5645 val32 |= APS_FSMCO_MAC_ENABLE;
5646 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5647
5648 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5649 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5650 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5651 ret = 0;
5652 break;
5653 }
5654 udelay(10);
5655 }
5656
5657 if (!count) {
5658 ret = -EBUSY;
5659 goto exit;
5660 }
5661
5662 exit:
5663 return ret;
5664 }
5665
5666 static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv)
5667 {
5668 u8 val8;
5669 u32 val32;
5670 int count, ret = 0;
5671
5672 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
5673 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5674 val8 |= LDOA15_ENABLE;
5675 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5676
5677 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
5678 val8 = rtl8xxxu_read8(priv, 0x0067);
5679 val8 &= ~BIT(4);
5680 rtl8xxxu_write8(priv, 0x0067, val8);
5681
5682 mdelay(1);
5683
5684 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
5685 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5686 val8 &= ~SYS_ISO_ANALOG_IPS;
5687 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5688
5689 /* disable SW LPS 0x04[10]= 0 */
5690 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5691 val8 &= ~BIT(2);
5692 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5693
5694 /* wait till 0x04[17] = 1 power ready*/
5695 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5696 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5697 if (val32 & BIT(17))
5698 break;
5699
5700 udelay(10);
5701 }
5702
5703 if (!count) {
5704 ret = -EBUSY;
5705 goto exit;
5706 }
5707
5708 /* We should be able to optimize the following three entries into one */
5709
5710 /* release WLON reset 0x04[16]= 1*/
5711 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5712 val8 |= BIT(0);
5713 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5714
5715 /* disable HWPDN 0x04[15]= 0*/
5716 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5717 val8 &= ~BIT(7);
5718 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5719
5720 /* disable WL suspend*/
5721 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5722 val8 &= ~(BIT(3) | BIT(4));
5723 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5724
5725 /* set, then poll until 0 */
5726 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5727 val32 |= APS_FSMCO_MAC_ENABLE;
5728 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5729
5730 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5731 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5732 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5733 ret = 0;
5734 break;
5735 }
5736 udelay(10);
5737 }
5738
5739 if (!count) {
5740 ret = -EBUSY;
5741 goto exit;
5742 }
5743
5744 /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
5745 /*
5746 * Note: Vendor driver actually clears this bit, despite the
5747 * documentation claims it's being set!
5748 */
5749 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
5750 val8 |= LEDCFG2_DPDT_SELECT;
5751 val8 &= ~LEDCFG2_DPDT_SELECT;
5752 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
5753
5754 exit:
5755 return ret;
5756 }
5757
5758 static int rtl8723b_emu_to_active(struct rtl8xxxu_priv *priv)
5759 {
5760 u8 val8;
5761 u32 val32;
5762 int count, ret = 0;
5763
5764 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface */
5765 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5766 val8 |= LDOA15_ENABLE;
5767 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5768
5769 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
5770 val8 = rtl8xxxu_read8(priv, 0x0067);
5771 val8 &= ~BIT(4);
5772 rtl8xxxu_write8(priv, 0x0067, val8);
5773
5774 mdelay(1);
5775
5776 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
5777 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5778 val8 &= ~SYS_ISO_ANALOG_IPS;
5779 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5780
5781 /* Disable SW LPS 0x04[10]= 0 */
5782 val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
5783 val32 &= ~APS_FSMCO_SW_LPS;
5784 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5785
5786 /* Wait until 0x04[17] = 1 power ready */
5787 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5788 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5789 if (val32 & BIT(17))
5790 break;
5791
5792 udelay(10);
5793 }
5794
5795 if (!count) {
5796 ret = -EBUSY;
5797 goto exit;
5798 }
5799
5800 /* We should be able to optimize the following three entries into one */
5801
5802 /* Release WLON reset 0x04[16]= 1*/
5803 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5804 val32 |= APS_FSMCO_WLON_RESET;
5805 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5806
5807 /* Disable HWPDN 0x04[15]= 0*/
5808 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5809 val32 &= ~APS_FSMCO_HW_POWERDOWN;
5810 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5811
5812 /* Disable WL suspend*/
5813 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5814 val32 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE);
5815 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5816
5817 /* Set, then poll until 0 */
5818 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5819 val32 |= APS_FSMCO_MAC_ENABLE;
5820 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5821
5822 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5823 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5824 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5825 ret = 0;
5826 break;
5827 }
5828 udelay(10);
5829 }
5830
5831 if (!count) {
5832 ret = -EBUSY;
5833 goto exit;
5834 }
5835
5836 /* Enable WL control XTAL setting */
5837 val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
5838 val8 |= AFE_MISC_WL_XTAL_CTRL;
5839 rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
5840
5841 /* Enable falling edge triggering interrupt */
5842 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 1);
5843 val8 |= BIT(1);
5844 rtl8xxxu_write8(priv, REG_GPIO_INTM + 1, val8);
5845
5846 /* Enable GPIO9 interrupt mode */
5847 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2 + 1);
5848 val8 |= BIT(1);
5849 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2 + 1, val8);
5850
5851 /* Enable GPIO9 input mode */
5852 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2);
5853 val8 &= ~BIT(1);
5854 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2, val8);
5855
5856 /* Enable HSISR GPIO[C:0] interrupt */
5857 val8 = rtl8xxxu_read8(priv, REG_HSIMR);
5858 val8 |= BIT(0);
5859 rtl8xxxu_write8(priv, REG_HSIMR, val8);
5860
5861 /* Enable HSISR GPIO9 interrupt */
5862 val8 = rtl8xxxu_read8(priv, REG_HSIMR + 2);
5863 val8 |= BIT(1);
5864 rtl8xxxu_write8(priv, REG_HSIMR + 2, val8);
5865
5866 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL);
5867 val8 |= MULTI_WIFI_HW_ROF_EN;
5868 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL, val8);
5869
5870 /* For GPIO9 internal pull high setting BIT(14) */
5871 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL + 1);
5872 val8 |= BIT(6);
5873 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL + 1, val8);
5874
5875 exit:
5876 return ret;
5877 }
5878
5879 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
5880 {
5881 u8 val8;
5882
5883 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
5884 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
5885
5886 /* 0x04[12:11] = 01 enable WL suspend */
5887 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5888 val8 &= ~BIT(4);
5889 val8 |= BIT(3);
5890 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5891
5892 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5893 val8 |= BIT(7);
5894 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5895
5896 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
5897 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
5898 val8 |= BIT(0);
5899 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
5900
5901 return 0;
5902 }
5903
5904 static int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv)
5905 {
5906 struct device *dev = &priv->udev->dev;
5907 u32 val32;
5908 int retry, retval;
5909
5910 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5911
5912 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
5913 val32 |= RXPKT_NUM_RW_RELEASE_EN;
5914 rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32);
5915
5916 retry = 100;
5917 retval = -EBUSY;
5918
5919 do {
5920 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
5921 if (val32 & RXPKT_NUM_RXDMA_IDLE) {
5922 retval = 0;
5923 break;
5924 }
5925 } while (retry--);
5926
5927 rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0);
5928 rtl8xxxu_write32(priv, REG_RQPN, 0x80000000);
5929 mdelay(2);
5930
5931 if (!retry)
5932 dev_warn(dev, "Failed to flush FIFO\n");
5933
5934 return retval;
5935 }
5936
5937 static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
5938 {
5939 u8 val8;
5940 u16 val16;
5941 u32 val32;
5942 int ret;
5943
5944 /*
5945 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5946 */
5947 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
5948
5949 rtl8723a_disabled_to_emu(priv);
5950
5951 ret = rtl8723a_emu_to_active(priv);
5952 if (ret)
5953 goto exit;
5954
5955 /*
5956 * 0x0004[19] = 1, reset 8051
5957 */
5958 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5959 val8 |= BIT(3);
5960 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5961
5962 /*
5963 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5964 * Set CR bit10 to enable 32k calibration.
5965 */
5966 val16 = rtl8xxxu_read16(priv, REG_CR);
5967 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5968 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5969 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5970 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5971 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5972 rtl8xxxu_write16(priv, REG_CR, val16);
5973
5974 /* For EFuse PG */
5975 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
5976 val32 &= ~(BIT(28) | BIT(29) | BIT(30));
5977 val32 |= (0x06 << 28);
5978 rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
5979 exit:
5980 return ret;
5981 }
5982
5983 static int rtl8723bu_power_on(struct rtl8xxxu_priv *priv)
5984 {
5985 u8 val8;
5986 u16 val16;
5987 u32 val32;
5988 int ret;
5989
5990 rtl8723a_disabled_to_emu(priv);
5991
5992 ret = rtl8723b_emu_to_active(priv);
5993 if (ret)
5994 goto exit;
5995
5996 /*
5997 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5998 * Set CR bit10 to enable 32k calibration.
5999 */
6000 val16 = rtl8xxxu_read16(priv, REG_CR);
6001 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
6002 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
6003 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
6004 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
6005 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
6006 rtl8xxxu_write16(priv, REG_CR, val16);
6007
6008 /*
6009 * BT coexist power on settings. This is identical for 1 and 2
6010 * antenna parts.
6011 */
6012 rtl8xxxu_write8(priv, REG_PAD_CTRL1 + 3, 0x20);
6013
6014 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
6015 val16 |= SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN;
6016 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
6017
6018 rtl8xxxu_write8(priv, REG_BT_CONTROL_8723BU + 1, 0x18);
6019 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
6020 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
6021 /* Antenna inverse */
6022 rtl8xxxu_write8(priv, 0xfe08, 0x01);
6023
6024 val16 = rtl8xxxu_read16(priv, REG_PWR_DATA);
6025 val16 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
6026 rtl8xxxu_write16(priv, REG_PWR_DATA, val16);
6027
6028 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
6029 val32 |= LEDCFG0_DPDT_SELECT;
6030 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
6031
6032 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
6033 val8 &= ~PAD_CTRL1_SW_DPDT_SEL_DATA;
6034 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
6035 exit:
6036 return ret;
6037 }
6038
6039 #ifdef CONFIG_RTL8XXXU_UNTESTED
6040
6041 static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
6042 {
6043 u8 val8;
6044 u16 val16;
6045 u32 val32;
6046 int i;
6047
6048 for (i = 100; i; i--) {
6049 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
6050 if (val8 & APS_FSMCO_PFM_ALDN)
6051 break;
6052 }
6053
6054 if (!i) {
6055 pr_info("%s: Poll failed\n", __func__);
6056 return -ENODEV;
6057 }
6058
6059 /*
6060 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
6061 */
6062 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
6063 rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
6064 udelay(100);
6065
6066 val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
6067 if (!(val8 & LDOV12D_ENABLE)) {
6068 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
6069 val8 |= LDOV12D_ENABLE;
6070 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
6071
6072 udelay(100);
6073
6074 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
6075 val8 &= ~SYS_ISO_MD2PP;
6076 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
6077 }
6078
6079 /*
6080 * Auto enable WLAN
6081 */
6082 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
6083 val16 |= APS_FSMCO_MAC_ENABLE;
6084 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
6085
6086 for (i = 1000; i; i--) {
6087 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
6088 if (!(val16 & APS_FSMCO_MAC_ENABLE))
6089 break;
6090 }
6091 if (!i) {
6092 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
6093 return -EBUSY;
6094 }
6095
6096 /*
6097 * Enable radio, GPIO, LED
6098 */
6099 val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
6100 APS_FSMCO_PFM_ALDN;
6101 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
6102
6103 /*
6104 * Release RF digital isolation
6105 */
6106 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
6107 val16 &= ~SYS_ISO_DIOR;
6108 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
6109
6110 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
6111 val8 &= ~APSD_CTRL_OFF;
6112 rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
6113 for (i = 200; i; i--) {
6114 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
6115 if (!(val8 & APSD_CTRL_OFF_STATUS))
6116 break;
6117 }
6118
6119 if (!i) {
6120 pr_info("%s: APSD_CTRL poll failed\n", __func__);
6121 return -EBUSY;
6122 }
6123
6124 /*
6125 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
6126 */
6127 val16 = rtl8xxxu_read16(priv, REG_CR);
6128 val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
6129 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
6130 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
6131 rtl8xxxu_write16(priv, REG_CR, val16);
6132
6133 /*
6134 * Workaround for 8188RU LNA power leakage problem.
6135 */
6136 if (priv->rtl_chip == RTL8188C && priv->hi_pa) {
6137 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
6138 val32 &= ~BIT(1);
6139 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
6140 }
6141 return 0;
6142 }
6143
6144 #endif
6145
6146 static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv)
6147 {
6148 u16 val16;
6149 u32 val32;
6150 int ret;
6151
6152 ret = 0;
6153
6154 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
6155 if (val32 & SYS_CFG_SPS_LDO_SEL) {
6156 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3);
6157 } else {
6158 /*
6159 * Raise 1.2V voltage
6160 */
6161 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL);
6162 val32 &= 0xff0fffff;
6163 val32 |= 0x00500000;
6164 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32);
6165 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83);
6166 }
6167
6168 rtl8192e_disabled_to_emu(priv);
6169
6170 ret = rtl8192e_emu_to_active(priv);
6171 if (ret)
6172 goto exit;
6173
6174 rtl8xxxu_write16(priv, REG_CR, 0x0000);
6175
6176 /*
6177 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
6178 * Set CR bit10 to enable 32k calibration.
6179 */
6180 val16 = rtl8xxxu_read16(priv, REG_CR);
6181 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
6182 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
6183 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
6184 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
6185 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
6186 rtl8xxxu_write16(priv, REG_CR, val16);
6187
6188 exit:
6189 return ret;
6190 }
6191
6192 static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
6193 {
6194 u8 val8;
6195 u16 val16;
6196 u32 val32;
6197
6198 /*
6199 * Workaround for 8188RU LNA power leakage problem.
6200 */
6201 if (priv->rtl_chip == RTL8188C && priv->hi_pa) {
6202 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
6203 val32 |= BIT(1);
6204 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
6205 }
6206
6207 rtl8xxxu_flush_fifo(priv);
6208
6209 rtl8xxxu_active_to_lps(priv);
6210
6211 /* Turn off RF */
6212 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
6213
6214 /* Reset Firmware if running in RAM */
6215 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
6216 rtl8xxxu_firmware_self_reset(priv);
6217
6218 /* Reset MCU */
6219 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
6220 val16 &= ~SYS_FUNC_CPU_ENABLE;
6221 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
6222
6223 /* Reset MCU ready status */
6224 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
6225
6226 rtl8xxxu_active_to_emu(priv);
6227 rtl8xxxu_emu_to_disabled(priv);
6228
6229 /* Reset MCU IO Wrapper */
6230 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
6231 val8 &= ~BIT(0);
6232 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
6233
6234 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
6235 val8 |= BIT(0);
6236 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
6237
6238 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
6239 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
6240 }
6241
6242 static void rtl8723bu_power_off(struct rtl8xxxu_priv *priv)
6243 {
6244 u8 val8;
6245 u16 val16;
6246
6247 rtl8xxxu_flush_fifo(priv);
6248
6249 /*
6250 * Disable TX report timer
6251 */
6252 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
6253 val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE;
6254 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
6255
6256 rtl8xxxu_write16(priv, REG_CR, 0x0000);
6257
6258 rtl8xxxu_active_to_lps(priv);
6259
6260 /* Reset Firmware if running in RAM */
6261 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
6262 rtl8xxxu_firmware_self_reset(priv);
6263
6264 /* Reset MCU */
6265 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
6266 val16 &= ~SYS_FUNC_CPU_ENABLE;
6267 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
6268
6269 /* Reset MCU ready status */
6270 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
6271
6272 rtl8723bu_active_to_emu(priv);
6273 rtl8xxxu_emu_to_disabled(priv);
6274 }
6275
6276 #ifdef NEED_PS_TDMA
6277 static void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
6278 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5)
6279 {
6280 struct h2c_cmd h2c;
6281
6282 memset(&h2c, 0, sizeof(struct h2c_cmd));
6283 h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA;
6284 h2c.b_type_dma.data1 = arg1;
6285 h2c.b_type_dma.data2 = arg2;
6286 h2c.b_type_dma.data3 = arg3;
6287 h2c.b_type_dma.data4 = arg4;
6288 h2c.b_type_dma.data5 = arg5;
6289 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma));
6290 }
6291 #endif
6292
6293 static void rtl8723b_enable_rf(struct rtl8xxxu_priv *priv)
6294 {
6295 struct h2c_cmd h2c;
6296 u32 val32;
6297 u8 val8;
6298
6299 /*
6300 * No indication anywhere as to what 0x0790 does. The 2 antenna
6301 * vendor code preserves bits 6-7 here.
6302 */
6303 rtl8xxxu_write8(priv, 0x0790, 0x05);
6304 /*
6305 * 0x0778 seems to be related to enabling the number of antennas
6306 * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it
6307 * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01
6308 */
6309 rtl8xxxu_write8(priv, 0x0778, 0x01);
6310
6311 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
6312 val8 |= BIT(5);
6313 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
6314
6315 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780);
6316
6317 rtl8723bu_write_btreg(priv, 0x3c, 0x15); /* BT TRx Mask on */
6318
6319 /*
6320 * Set BT grant to low
6321 */
6322 memset(&h2c, 0, sizeof(struct h2c_cmd));
6323 h2c.bt_grant.cmd = H2C_8723B_BT_GRANT;
6324 h2c.bt_grant.data = 0;
6325 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_grant));
6326
6327 /*
6328 * WLAN action by PTA
6329 */
6330 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
6331
6332 /*
6333 * BT select S0/S1 controlled by WiFi
6334 */
6335 val8 = rtl8xxxu_read8(priv, 0x0067);
6336 val8 |= BIT(5);
6337 rtl8xxxu_write8(priv, 0x0067, val8);
6338
6339 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
6340 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
6341 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
6342
6343 /*
6344 * Bits 6/7 are marked in/out ... but for what?
6345 */
6346 rtl8xxxu_write8(priv, 0x0974, 0xff);
6347
6348 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
6349 val32 |= (BIT(0) | BIT(1));
6350 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
6351
6352 rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77);
6353
6354 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
6355 val32 &= ~BIT(24);
6356 val32 |= BIT(23);
6357 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
6358
6359 /*
6360 * Fix external switch Main->S1, Aux->S0
6361 */
6362 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
6363 val8 &= ~BIT(0);
6364 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
6365
6366 memset(&h2c, 0, sizeof(struct h2c_cmd));
6367 h2c.ant_sel_rsv.cmd = H2C_8723B_ANT_SEL_RSV;
6368 h2c.ant_sel_rsv.ant_inverse = 1;
6369 h2c.ant_sel_rsv.int_switch_type = 0;
6370 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv));
6371
6372 /*
6373 * 0x280, 0x00, 0x200, 0x80 - not clear
6374 */
6375 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
6376
6377 /*
6378 * Software control, antenna at WiFi side
6379 */
6380 #ifdef NEED_PS_TDMA
6381 rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00);
6382 #endif
6383
6384 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
6385 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555);
6386 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
6387 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
6388
6389 memset(&h2c, 0, sizeof(struct h2c_cmd));
6390 h2c.bt_info.cmd = H2C_8723B_BT_INFO;
6391 h2c.bt_info.data = BIT(0);
6392 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_info));
6393
6394 memset(&h2c, 0, sizeof(struct h2c_cmd));
6395 h2c.ignore_wlan.cmd = H2C_8723B_BT_IGNORE_WLANACT;
6396 h2c.ignore_wlan.data = 0;
6397 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ignore_wlan));
6398 }
6399
6400 static void rtl8723b_disable_rf(struct rtl8xxxu_priv *priv)
6401 {
6402 u32 val32;
6403
6404 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
6405
6406 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA);
6407 val32 &= ~(BIT(22) | BIT(23));
6408 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32);
6409 }
6410
6411 static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv *priv)
6412 {
6413 u32 agg_rx;
6414 u8 agg_ctrl;
6415
6416 /*
6417 * For now simply disable RX aggregation
6418 */
6419 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
6420 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
6421
6422 agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH);
6423 agg_rx &= ~RXDMA_USB_AGG_ENABLE;
6424 agg_rx &= ~0xff0f;
6425
6426 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
6427 rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx);
6428 }
6429
6430 static void rtl8723bu_init_statistics(struct rtl8xxxu_priv *priv)
6431 {
6432 u32 val32;
6433
6434 /* Time duration for NHM unit: 4us, 0x2710=40ms */
6435 rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0x2710);
6436 rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff);
6437 rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52);
6438 rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff);
6439 /* TH8 */
6440 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
6441 val32 |= 0xff;
6442 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
6443 /* Enable CCK */
6444 val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B);
6445 val32 |= BIT(8) | BIT(9) | BIT(10);
6446 rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32);
6447 /* Max power amongst all RX antennas */
6448 val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC);
6449 val32 |= BIT(7);
6450 rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32);
6451 }
6452
6453 static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
6454 {
6455 struct rtl8xxxu_priv *priv = hw->priv;
6456 struct device *dev = &priv->udev->dev;
6457 struct rtl8xxxu_rfregval *rftable;
6458 bool macpower;
6459 int ret;
6460 u8 val8;
6461 u16 val16;
6462 u32 val32;
6463
6464 /* Check if MAC is already powered on */
6465 val8 = rtl8xxxu_read8(priv, REG_CR);
6466
6467 /*
6468 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
6469 * initialized. First MAC returns 0xea, second MAC returns 0x00
6470 */
6471 if (val8 == 0xea)
6472 macpower = false;
6473 else
6474 macpower = true;
6475
6476 ret = priv->fops->power_on(priv);
6477 if (ret < 0) {
6478 dev_warn(dev, "%s: Failed power on\n", __func__);
6479 goto exit;
6480 }
6481
6482 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
6483 if (!macpower) {
6484 ret = priv->fops->llt_init(priv, TX_TOTAL_PAGE_NUM);
6485 if (ret) {
6486 dev_warn(dev, "%s: LLT table init failed\n", __func__);
6487 goto exit;
6488 }
6489
6490 /*
6491 * Presumably this is for 8188EU as well
6492 * Enable TX report and TX report timer
6493 */
6494 if (priv->rtl_chip == RTL8723B) {
6495 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
6496 val8 |= TX_REPORT_CTRL_TIMER_ENABLE;
6497 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
6498 /* Set MAX RPT MACID */
6499 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02);
6500 /* TX report Timer. Unit: 32us */
6501 rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0);
6502
6503 /* tmp ps ? */
6504 val8 = rtl8xxxu_read8(priv, 0xa3);
6505 val8 &= 0xf8;
6506 rtl8xxxu_write8(priv, 0xa3, val8);
6507 }
6508 }
6509
6510 ret = rtl8xxxu_download_firmware(priv);
6511 dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
6512 if (ret)
6513 goto exit;
6514 ret = rtl8xxxu_start_firmware(priv);
6515 dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
6516 if (ret)
6517 goto exit;
6518
6519 /* Solve too many protocol error on USB bus */
6520 /* Can't do this for 8188/8192 UMC A cut parts */
6521 if (priv->rtl_chip == RTL8723A ||
6522 ((priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C ||
6523 priv->rtl_chip == RTL8188C) &&
6524 (priv->chip_cut || !priv->vendor_umc))) {
6525 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
6526 rtl8xxxu_write8(priv, 0xfe41, 0x94);
6527 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6528
6529 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
6530 rtl8xxxu_write8(priv, 0xfe41, 0x19);
6531 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6532
6533 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
6534 rtl8xxxu_write8(priv, 0xfe41, 0x91);
6535 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6536
6537 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
6538 rtl8xxxu_write8(priv, 0xfe41, 0x81);
6539 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6540 }
6541
6542 if (priv->rtl_chip == RTL8192E) {
6543 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
6544 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
6545 }
6546
6547 if (priv->fops->phy_init_antenna_selection)
6548 priv->fops->phy_init_antenna_selection(priv);
6549
6550 ret = rtl8xxxu_init_mac(priv);
6551
6552 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
6553 if (ret)
6554 goto exit;
6555
6556 ret = rtl8xxxu_init_phy_bb(priv);
6557 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
6558 if (ret)
6559 goto exit;
6560
6561 switch(priv->rtl_chip) {
6562 case RTL8723A:
6563 rftable = rtl8723au_radioa_1t_init_table;
6564 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6565 break;
6566 case RTL8723B:
6567 rftable = rtl8723bu_radioa_1t_init_table;
6568 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6569 /*
6570 * PHY LCK
6571 */
6572 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdfbe0);
6573 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, 0x8c01);
6574 msleep(200);
6575 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdffe0);
6576 break;
6577 case RTL8188C:
6578 if (priv->hi_pa)
6579 rftable = rtl8188ru_radioa_1t_highpa_table;
6580 else
6581 rftable = rtl8192cu_radioa_1t_init_table;
6582 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6583 break;
6584 case RTL8191C:
6585 rftable = rtl8192cu_radioa_1t_init_table;
6586 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6587 break;
6588 case RTL8192C:
6589 rftable = rtl8192cu_radioa_2t_init_table;
6590 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6591 if (ret)
6592 break;
6593 rftable = rtl8192cu_radiob_2t_init_table;
6594 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
6595 break;
6596 case RTL8192E:
6597 rftable = rtl8192eu_radioa_init_table;
6598 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6599 if (ret)
6600 break;
6601 rftable = rtl8192eu_radiob_init_table;
6602 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
6603 break;
6604 default:
6605 ret = -EINVAL;
6606 }
6607
6608 if (ret)
6609 goto exit;
6610
6611 /*
6612 * Chip specific quirks
6613 */
6614 if (priv->rtl_chip == RTL8723A) {
6615 /* Fix USB interface interference issue */
6616 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
6617 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
6618 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6619 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
6620
6621 /* Reduce 80M spur */
6622 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
6623 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
6624 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
6625 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
6626 } else {
6627 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
6628 val32 |= TXDMA_OFFSET_DROP_DATA_EN;
6629 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
6630 }
6631
6632 if (!macpower) {
6633 if (priv->ep_tx_normal_queue)
6634 val8 = TX_PAGE_NUM_NORM_PQ;
6635 else
6636 val8 = 0;
6637
6638 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
6639
6640 val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD;
6641
6642 if (priv->ep_tx_high_queue)
6643 val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
6644 if (priv->ep_tx_low_queue)
6645 val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
6646
6647 rtl8xxxu_write32(priv, REG_RQPN, val32);
6648
6649 /*
6650 * Set TX buffer boundary
6651 */
6652 if (priv->rtl_chip == RTL8192E)
6653 val8 = TX_TOTAL_PAGE_NUM_8192E + 1;
6654 else
6655 val8 = TX_TOTAL_PAGE_NUM + 1;
6656
6657 if (priv->rtl_chip == RTL8723B)
6658 val8 -= 1;
6659
6660 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
6661 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
6662 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
6663 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
6664 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
6665 }
6666
6667 ret = rtl8xxxu_init_queue_priority(priv);
6668 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
6669 if (ret)
6670 goto exit;
6671
6672 /* RFSW Control - clear bit 14 ?? */
6673 if (priv->rtl_chip != RTL8723B)
6674 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
6675 /* 0x07000760 */
6676 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
6677 FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
6678 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
6679 FPGA0_RF_BD_CTRL_SHIFT);
6680 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
6681 /* 0x860[6:5]= 00 - why? - this sets antenna B */
6682 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210);
6683
6684 priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
6685 RF6052_REG_MODE_AG);
6686
6687 /*
6688 * Set RX page boundary
6689 */
6690 if (priv->rtl_chip == RTL8723B)
6691 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x3f7f);
6692 else if (priv->rtl_chip == RTL8192E)
6693 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x3cff);
6694 else
6695 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x27ff);
6696 /*
6697 * Transfer page size is always 128
6698 */
6699 if (priv->rtl_chip == RTL8723B)
6700 val8 = (PBP_PAGE_SIZE_256 << PBP_PAGE_SIZE_RX_SHIFT) |
6701 (PBP_PAGE_SIZE_256 << PBP_PAGE_SIZE_TX_SHIFT);
6702 else
6703 val8 = (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_RX_SHIFT) |
6704 (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_TX_SHIFT);
6705 rtl8xxxu_write8(priv, REG_PBP, val8);
6706
6707 /*
6708 * Unit in 8 bytes, not obvious what it is used for
6709 */
6710 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
6711
6712 /*
6713 * Enable all interrupts - not obvious USB needs to do this
6714 */
6715 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
6716 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
6717
6718 rtl8xxxu_set_mac(priv);
6719 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
6720
6721 /*
6722 * Configure initial WMAC settings
6723 */
6724 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
6725 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
6726 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
6727 rtl8xxxu_write32(priv, REG_RCR, val32);
6728
6729 /*
6730 * Accept all multicast
6731 */
6732 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
6733 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
6734
6735 /*
6736 * Init adaptive controls
6737 */
6738 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6739 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
6740 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
6741 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6742
6743 /* CCK = 0x0a, OFDM = 0x10 */
6744 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
6745 rtl8xxxu_set_retry(priv, 0x30, 0x30);
6746 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
6747
6748 /*
6749 * Init EDCA
6750 */
6751 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
6752
6753 /* Set CCK SIFS */
6754 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
6755
6756 /* Set OFDM SIFS */
6757 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
6758
6759 /* TXOP */
6760 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
6761 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
6762 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
6763 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
6764
6765 /* Set data auto rate fallback retry count */
6766 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
6767 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
6768 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
6769 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
6770
6771 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
6772 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
6773 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
6774
6775 /* Set ACK timeout */
6776 rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
6777
6778 /*
6779 * Initialize beacon parameters
6780 */
6781 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
6782 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
6783 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
6784 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
6785 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
6786 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
6787
6788 /*
6789 * Initialize burst parameters
6790 */
6791 if (priv->rtl_chip == RTL8723B) {
6792 /*
6793 * For USB high speed set 512B packets
6794 */
6795 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B);
6796 val8 &= ~(BIT(4) | BIT(5));
6797 val8 |= BIT(4);
6798 val8 |= BIT(1) | BIT(2) | BIT(3);
6799 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8);
6800
6801 /*
6802 * For USB high speed set 512B packets
6803 */
6804 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B);
6805 val8 |= BIT(7);
6806 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8);
6807
6808 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14);
6809 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 0x5e);
6810 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff);
6811 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18);
6812 rtl8xxxu_write8(priv, REG_PIFS, 0x00);
6813 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, 0x50);
6814 rtl8xxxu_write8(priv, REG_USTIME_EDCA, 0x50);
6815
6816 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
6817 val8 |= BIT(5) | BIT(6);
6818 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
6819 }
6820
6821 if (priv->fops->init_aggregation)
6822 priv->fops->init_aggregation(priv);
6823
6824 /*
6825 * Enable CCK and OFDM block
6826 */
6827 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
6828 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
6829 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
6830
6831 /*
6832 * Invalidate all CAM entries - bit 30 is undocumented
6833 */
6834 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
6835
6836 /*
6837 * Start out with default power levels for channel 6, 20MHz
6838 */
6839 priv->fops->set_tx_power(priv, 1, false);
6840
6841 /* Let the 8051 take control of antenna setting */
6842 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
6843 val8 |= LEDCFG2_DPDT_SELECT;
6844 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
6845
6846 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
6847
6848 /* Disable BAR - not sure if this has any effect on USB */
6849 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
6850
6851 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
6852
6853 if (priv->fops->init_statistics)
6854 priv->fops->init_statistics(priv);
6855
6856 rtl8723a_phy_lc_calibrate(priv);
6857
6858 priv->fops->phy_iq_calibrate(priv);
6859
6860 /*
6861 * This should enable thermal meter
6862 */
6863 if (priv->fops->has_s0s1)
6864 rtl8xxxu_write_rfreg(priv,
6865 RF_A, RF6052_REG_T_METER_8723B, 0x37cf8);
6866 else
6867 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
6868
6869 /* Set NAV_UPPER to 30000us */
6870 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
6871 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
6872
6873 if (priv->rtl_chip == RTL8723A) {
6874 /*
6875 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
6876 * but we need to find root cause.
6877 * This is 8723au only.
6878 */
6879 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
6880 if ((val32 & 0xff000000) != 0x83000000) {
6881 val32 |= FPGA_RF_MODE_CCK;
6882 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
6883 }
6884 }
6885
6886 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
6887 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
6888 /* ack for xmit mgmt frames. */
6889 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
6890
6891 exit:
6892 return ret;
6893 }
6894
6895 static void rtl8xxxu_disable_device(struct ieee80211_hw *hw)
6896 {
6897 struct rtl8xxxu_priv *priv = hw->priv;
6898
6899 priv->fops->power_off(priv);
6900 }
6901
6902 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
6903 struct ieee80211_key_conf *key, const u8 *mac)
6904 {
6905 u32 cmd, val32, addr, ctrl;
6906 int j, i, tmp_debug;
6907
6908 tmp_debug = rtl8xxxu_debug;
6909 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
6910 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
6911
6912 /*
6913 * This is a bit of a hack - the lower bits of the cipher
6914 * suite selector happens to match the cipher index in the CAM
6915 */
6916 addr = key->keyidx << CAM_CMD_KEY_SHIFT;
6917 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
6918
6919 for (j = 5; j >= 0; j--) {
6920 switch (j) {
6921 case 0:
6922 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
6923 break;
6924 case 1:
6925 val32 = mac[2] | (mac[3] << 8) |
6926 (mac[4] << 16) | (mac[5] << 24);
6927 break;
6928 default:
6929 i = (j - 2) << 2;
6930 val32 = key->key[i] | (key->key[i + 1] << 8) |
6931 key->key[i + 2] << 16 | key->key[i + 3] << 24;
6932 break;
6933 }
6934
6935 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
6936 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
6937 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
6938 udelay(100);
6939 }
6940
6941 rtl8xxxu_debug = tmp_debug;
6942 }
6943
6944 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
6945 struct ieee80211_vif *vif, const u8 *mac)
6946 {
6947 struct rtl8xxxu_priv *priv = hw->priv;
6948 u8 val8;
6949
6950 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6951 val8 |= BEACON_DISABLE_TSF_UPDATE;
6952 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6953 }
6954
6955 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
6956 struct ieee80211_vif *vif)
6957 {
6958 struct rtl8xxxu_priv *priv = hw->priv;
6959 u8 val8;
6960
6961 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6962 val8 &= ~BEACON_DISABLE_TSF_UPDATE;
6963 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6964 }
6965
6966 static void rtl8723au_update_rate_mask(struct rtl8xxxu_priv *priv,
6967 u32 ramask, int sgi)
6968 {
6969 struct h2c_cmd h2c;
6970
6971 memset(&h2c, 0, sizeof(struct h2c_cmd));
6972
6973 h2c.ramask.cmd = H2C_SET_RATE_MASK;
6974 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
6975 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
6976
6977 h2c.ramask.arg = 0x80;
6978 if (sgi)
6979 h2c.ramask.arg |= 0x20;
6980
6981 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
6982 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask));
6983 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ramask));
6984 }
6985
6986 static void rtl8723bu_update_rate_mask(struct rtl8xxxu_priv *priv,
6987 u32 ramask, int sgi)
6988 {
6989 struct h2c_cmd h2c;
6990 u8 bw = 0;
6991
6992 memset(&h2c, 0, sizeof(struct h2c_cmd));
6993
6994 h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID;
6995 h2c.b_macid_cfg.ramask0 = ramask & 0xff;
6996 h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff;
6997 h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff;
6998 h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff;
6999
7000 h2c.ramask.arg = 0x80;
7001 h2c.b_macid_cfg.data1 = 0;
7002 if (sgi)
7003 h2c.b_macid_cfg.data1 |= BIT(7);
7004
7005 h2c.b_macid_cfg.data2 = bw;
7006
7007 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
7008 __func__, ramask, h2c.ramask.arg, sizeof(h2c.b_macid_cfg));
7009 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg));
7010 }
7011
7012 static void rtl8723au_report_connect(struct rtl8xxxu_priv *priv,
7013 u8 macid, bool connect)
7014 {
7015 struct h2c_cmd h2c;
7016
7017 memset(&h2c, 0, sizeof(struct h2c_cmd));
7018
7019 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
7020
7021 if (connect)
7022 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
7023 else
7024 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
7025
7026 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss));
7027 }
7028
7029 static void rtl8723bu_report_connect(struct rtl8xxxu_priv *priv,
7030 u8 macid, bool connect)
7031 {
7032 struct h2c_cmd h2c;
7033
7034 memset(&h2c, 0, sizeof(struct h2c_cmd));
7035
7036 h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT;
7037 if (connect)
7038 h2c.media_status_rpt.parm |= BIT(0);
7039 else
7040 h2c.media_status_rpt.parm &= ~BIT(0);
7041
7042 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt));
7043 }
7044
7045 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
7046 {
7047 u32 val32;
7048 u8 rate_idx = 0;
7049
7050 rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
7051
7052 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
7053 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
7054 val32 |= rate_cfg;
7055 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
7056
7057 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
7058
7059 while (rate_cfg) {
7060 rate_cfg = (rate_cfg >> 1);
7061 rate_idx++;
7062 }
7063 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
7064 }
7065
7066 static void
7067 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
7068 struct ieee80211_bss_conf *bss_conf, u32 changed)
7069 {
7070 struct rtl8xxxu_priv *priv = hw->priv;
7071 struct device *dev = &priv->udev->dev;
7072 struct ieee80211_sta *sta;
7073 u32 val32;
7074 u8 val8;
7075
7076 if (changed & BSS_CHANGED_ASSOC) {
7077 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
7078
7079 rtl8xxxu_set_linktype(priv, vif->type);
7080
7081 if (bss_conf->assoc) {
7082 u32 ramask;
7083 int sgi = 0;
7084
7085 rcu_read_lock();
7086 sta = ieee80211_find_sta(vif, bss_conf->bssid);
7087 if (!sta) {
7088 dev_info(dev, "%s: ASSOC no sta found\n",
7089 __func__);
7090 rcu_read_unlock();
7091 goto error;
7092 }
7093
7094 if (sta->ht_cap.ht_supported)
7095 dev_info(dev, "%s: HT supported\n", __func__);
7096 if (sta->vht_cap.vht_supported)
7097 dev_info(dev, "%s: VHT supported\n", __func__);
7098
7099 /* TODO: Set bits 28-31 for rate adaptive id */
7100 ramask = (sta->supp_rates[0] & 0xfff) |
7101 sta->ht_cap.mcs.rx_mask[0] << 12 |
7102 sta->ht_cap.mcs.rx_mask[1] << 20;
7103 if (sta->ht_cap.cap &
7104 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
7105 sgi = 1;
7106 rcu_read_unlock();
7107
7108 priv->fops->update_rate_mask(priv, ramask, sgi);
7109
7110 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
7111
7112 rtl8723a_stop_tx_beacon(priv);
7113
7114 /* joinbss sequence */
7115 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
7116 0xc000 | bss_conf->aid);
7117
7118 priv->fops->report_connect(priv, 0, true);
7119 } else {
7120 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
7121 val8 |= BEACON_DISABLE_TSF_UPDATE;
7122 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
7123
7124 priv->fops->report_connect(priv, 0, false);
7125 }
7126 }
7127
7128 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
7129 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
7130 bss_conf->use_short_preamble);
7131 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
7132 if (bss_conf->use_short_preamble)
7133 val32 |= RSR_ACK_SHORT_PREAMBLE;
7134 else
7135 val32 &= ~RSR_ACK_SHORT_PREAMBLE;
7136 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
7137 }
7138
7139 if (changed & BSS_CHANGED_ERP_SLOT) {
7140 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
7141 bss_conf->use_short_slot);
7142
7143 if (bss_conf->use_short_slot)
7144 val8 = 9;
7145 else
7146 val8 = 20;
7147 rtl8xxxu_write8(priv, REG_SLOT, val8);
7148 }
7149
7150 if (changed & BSS_CHANGED_BSSID) {
7151 dev_dbg(dev, "Changed BSSID!\n");
7152 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
7153 }
7154
7155 if (changed & BSS_CHANGED_BASIC_RATES) {
7156 dev_dbg(dev, "Changed BASIC_RATES!\n");
7157 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
7158 }
7159 error:
7160 return;
7161 }
7162
7163 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
7164 {
7165 u32 rtlqueue;
7166
7167 switch (queue) {
7168 case IEEE80211_AC_VO:
7169 rtlqueue = TXDESC_QUEUE_VO;
7170 break;
7171 case IEEE80211_AC_VI:
7172 rtlqueue = TXDESC_QUEUE_VI;
7173 break;
7174 case IEEE80211_AC_BE:
7175 rtlqueue = TXDESC_QUEUE_BE;
7176 break;
7177 case IEEE80211_AC_BK:
7178 rtlqueue = TXDESC_QUEUE_BK;
7179 break;
7180 default:
7181 rtlqueue = TXDESC_QUEUE_BE;
7182 }
7183
7184 return rtlqueue;
7185 }
7186
7187 static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
7188 {
7189 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
7190 u32 queue;
7191
7192 if (ieee80211_is_mgmt(hdr->frame_control))
7193 queue = TXDESC_QUEUE_MGNT;
7194 else
7195 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
7196
7197 return queue;
7198 }
7199
7200 /*
7201 * Despite newer chips 8723b/8812/8821 having a larger TX descriptor
7202 * format. The descriptor checksum is still only calculated over the
7203 * initial 32 bytes of the descriptor!
7204 */
7205 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc)
7206 {
7207 __le16 *ptr = (__le16 *)tx_desc;
7208 u16 csum = 0;
7209 int i;
7210
7211 /*
7212 * Clear csum field before calculation, as the csum field is
7213 * in the middle of the struct.
7214 */
7215 tx_desc->csum = cpu_to_le16(0);
7216
7217 for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++)
7218 csum = csum ^ le16_to_cpu(ptr[i]);
7219
7220 tx_desc->csum |= cpu_to_le16(csum);
7221 }
7222
7223 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
7224 {
7225 struct rtl8xxxu_tx_urb *tx_urb, *tmp;
7226 unsigned long flags;
7227
7228 spin_lock_irqsave(&priv->tx_urb_lock, flags);
7229 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
7230 list_del(&tx_urb->list);
7231 priv->tx_urb_free_count--;
7232 usb_free_urb(&tx_urb->urb);
7233 }
7234 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
7235 }
7236
7237 static struct rtl8xxxu_tx_urb *
7238 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
7239 {
7240 struct rtl8xxxu_tx_urb *tx_urb;
7241 unsigned long flags;
7242
7243 spin_lock_irqsave(&priv->tx_urb_lock, flags);
7244 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
7245 struct rtl8xxxu_tx_urb, list);
7246 if (tx_urb) {
7247 list_del(&tx_urb->list);
7248 priv->tx_urb_free_count--;
7249 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
7250 !priv->tx_stopped) {
7251 priv->tx_stopped = true;
7252 ieee80211_stop_queues(priv->hw);
7253 }
7254 }
7255
7256 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
7257
7258 return tx_urb;
7259 }
7260
7261 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
7262 struct rtl8xxxu_tx_urb *tx_urb)
7263 {
7264 unsigned long flags;
7265
7266 INIT_LIST_HEAD(&tx_urb->list);
7267
7268 spin_lock_irqsave(&priv->tx_urb_lock, flags);
7269
7270 list_add(&tx_urb->list, &priv->tx_urb_free_list);
7271 priv->tx_urb_free_count++;
7272 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
7273 priv->tx_stopped) {
7274 priv->tx_stopped = false;
7275 ieee80211_wake_queues(priv->hw);
7276 }
7277
7278 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
7279 }
7280
7281 static void rtl8xxxu_tx_complete(struct urb *urb)
7282 {
7283 struct sk_buff *skb = (struct sk_buff *)urb->context;
7284 struct ieee80211_tx_info *tx_info;
7285 struct ieee80211_hw *hw;
7286 struct rtl8xxxu_priv *priv;
7287 struct rtl8xxxu_tx_urb *tx_urb =
7288 container_of(urb, struct rtl8xxxu_tx_urb, urb);
7289
7290 tx_info = IEEE80211_SKB_CB(skb);
7291 hw = tx_info->rate_driver_data[0];
7292 priv = hw->priv;
7293
7294 skb_pull(skb, priv->fops->tx_desc_size);
7295
7296 ieee80211_tx_info_clear_status(tx_info);
7297 tx_info->status.rates[0].idx = -1;
7298 tx_info->status.rates[0].count = 0;
7299
7300 if (!urb->status)
7301 tx_info->flags |= IEEE80211_TX_STAT_ACK;
7302
7303 ieee80211_tx_status_irqsafe(hw, skb);
7304
7305 rtl8xxxu_free_tx_urb(priv, tx_urb);
7306 }
7307
7308 static void rtl8xxxu_dump_action(struct device *dev,
7309 struct ieee80211_hdr *hdr)
7310 {
7311 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
7312 u16 cap, timeout;
7313
7314 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
7315 return;
7316
7317 switch (mgmt->u.action.u.addba_resp.action_code) {
7318 case WLAN_ACTION_ADDBA_RESP:
7319 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
7320 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
7321 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
7322 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
7323 "status %02x\n",
7324 timeout,
7325 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
7326 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
7327 (cap >> 1) & 0x1,
7328 le16_to_cpu(mgmt->u.action.u.addba_resp.status));
7329 break;
7330 case WLAN_ACTION_ADDBA_REQ:
7331 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
7332 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
7333 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
7334 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
7335 timeout,
7336 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
7337 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
7338 (cap >> 1) & 0x1);
7339 break;
7340 default:
7341 dev_info(dev, "action frame %02x\n",
7342 mgmt->u.action.u.addba_resp.action_code);
7343 break;
7344 }
7345 }
7346
7347 static void rtl8xxxu_tx(struct ieee80211_hw *hw,
7348 struct ieee80211_tx_control *control,
7349 struct sk_buff *skb)
7350 {
7351 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
7352 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
7353 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
7354 struct rtl8xxxu_priv *priv = hw->priv;
7355 struct rtl8xxxu_txdesc32 *tx_desc;
7356 struct rtl8xxxu_txdesc40 *tx_desc40;
7357 struct rtl8xxxu_tx_urb *tx_urb;
7358 struct ieee80211_sta *sta = NULL;
7359 struct ieee80211_vif *vif = tx_info->control.vif;
7360 struct device *dev = &priv->udev->dev;
7361 u32 queue, rate;
7362 u16 pktlen = skb->len;
7363 u16 seq_number;
7364 u16 rate_flag = tx_info->control.rates[0].flags;
7365 int tx_desc_size = priv->fops->tx_desc_size;
7366 int ret;
7367 bool usedesc40, ampdu_enable;
7368
7369 if (skb_headroom(skb) < tx_desc_size) {
7370 dev_warn(dev,
7371 "%s: Not enough headroom (%i) for tx descriptor\n",
7372 __func__, skb_headroom(skb));
7373 goto error;
7374 }
7375
7376 if (unlikely(skb->len > (65535 - tx_desc_size))) {
7377 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
7378 __func__, skb->len);
7379 goto error;
7380 }
7381
7382 tx_urb = rtl8xxxu_alloc_tx_urb(priv);
7383 if (!tx_urb) {
7384 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
7385 goto error;
7386 }
7387
7388 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
7389 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
7390 __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
7391
7392 if (ieee80211_is_action(hdr->frame_control))
7393 rtl8xxxu_dump_action(dev, hdr);
7394
7395 usedesc40 = (tx_desc_size == 40);
7396 tx_info->rate_driver_data[0] = hw;
7397
7398 if (control && control->sta)
7399 sta = control->sta;
7400
7401 tx_desc = (struct rtl8xxxu_txdesc32 *)skb_push(skb, tx_desc_size);
7402
7403 memset(tx_desc, 0, tx_desc_size);
7404 tx_desc->pkt_size = cpu_to_le16(pktlen);
7405 tx_desc->pkt_offset = tx_desc_size;
7406
7407 tx_desc->txdw0 =
7408 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
7409 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
7410 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
7411 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
7412
7413 queue = rtl8xxxu_queue_select(hw, skb);
7414 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
7415
7416 if (tx_info->control.hw_key) {
7417 switch (tx_info->control.hw_key->cipher) {
7418 case WLAN_CIPHER_SUITE_WEP40:
7419 case WLAN_CIPHER_SUITE_WEP104:
7420 case WLAN_CIPHER_SUITE_TKIP:
7421 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
7422 break;
7423 case WLAN_CIPHER_SUITE_CCMP:
7424 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
7425 break;
7426 default:
7427 break;
7428 }
7429 }
7430
7431 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
7432 ampdu_enable = false;
7433 if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
7434 if (sta->ht_cap.ht_supported) {
7435 u32 ampdu, val32;
7436
7437 ampdu = (u32)sta->ht_cap.ampdu_density;
7438 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
7439 tx_desc->txdw2 |= cpu_to_le32(val32);
7440
7441 ampdu_enable = true;
7442 }
7443 }
7444
7445 if (rate_flag & IEEE80211_TX_RC_MCS)
7446 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
7447 else
7448 rate = tx_rate->hw_value;
7449
7450 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
7451 if (!usedesc40) {
7452 tx_desc->txdw5 = cpu_to_le32(rate);
7453
7454 if (ieee80211_is_data(hdr->frame_control))
7455 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
7456
7457 tx_desc->txdw3 =
7458 cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT);
7459
7460 if (ampdu_enable)
7461 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE);
7462 else
7463 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK);
7464
7465 if (ieee80211_is_mgmt(hdr->frame_control)) {
7466 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
7467 tx_desc->txdw4 |=
7468 cpu_to_le32(TXDESC32_USE_DRIVER_RATE);
7469 tx_desc->txdw5 |=
7470 cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT);
7471 tx_desc->txdw5 |=
7472 cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE);
7473 }
7474
7475 if (ieee80211_is_data_qos(hdr->frame_control))
7476 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS);
7477
7478 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
7479 (sta && vif && vif->bss_conf.use_short_preamble))
7480 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE);
7481
7482 if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
7483 (ieee80211_is_data_qos(hdr->frame_control) &&
7484 sta && sta->ht_cap.cap &
7485 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
7486 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI);
7487 }
7488
7489 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
7490 /*
7491 * Use RTS rate 24M - does the mac80211 tell
7492 * us which to use?
7493 */
7494 tx_desc->txdw4 |=
7495 cpu_to_le32(DESC_RATE_24M <<
7496 TXDESC32_RTS_RATE_SHIFT);
7497 tx_desc->txdw4 |=
7498 cpu_to_le32(TXDESC32_RTS_CTS_ENABLE);
7499 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
7500 }
7501 } else {
7502 tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc;
7503
7504 tx_desc40->txdw4 = cpu_to_le32(rate);
7505 if (ieee80211_is_data(hdr->frame_control)) {
7506 tx_desc->txdw4 |=
7507 cpu_to_le32(0x1f <<
7508 TXDESC40_DATA_RATE_FB_SHIFT);
7509 }
7510
7511 tx_desc40->txdw9 =
7512 cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT);
7513
7514 if (ampdu_enable)
7515 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE);
7516 else
7517 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK);
7518
7519 if (ieee80211_is_mgmt(hdr->frame_control)) {
7520 tx_desc40->txdw4 = cpu_to_le32(tx_rate->hw_value);
7521 tx_desc40->txdw3 |=
7522 cpu_to_le32(TXDESC40_USE_DRIVER_RATE);
7523 tx_desc40->txdw4 |=
7524 cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT);
7525 tx_desc40->txdw4 |=
7526 cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE);
7527 }
7528
7529 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
7530 (sta && vif && vif->bss_conf.use_short_preamble))
7531 tx_desc40->txdw5 |=
7532 cpu_to_le32(TXDESC40_SHORT_PREAMBLE);
7533
7534 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
7535 /*
7536 * Use RTS rate 24M - does the mac80211 tell
7537 * us which to use?
7538 */
7539 tx_desc->txdw4 |=
7540 cpu_to_le32(DESC_RATE_24M <<
7541 TXDESC40_RTS_RATE_SHIFT);
7542 tx_desc->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE);
7543 tx_desc->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE);
7544 }
7545 }
7546
7547 rtl8xxxu_calc_tx_desc_csum(tx_desc);
7548
7549 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
7550 skb->data, skb->len, rtl8xxxu_tx_complete, skb);
7551
7552 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
7553 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
7554 if (ret) {
7555 usb_unanchor_urb(&tx_urb->urb);
7556 rtl8xxxu_free_tx_urb(priv, tx_urb);
7557 goto error;
7558 }
7559 return;
7560 error:
7561 dev_kfree_skb(skb);
7562 }
7563
7564 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
7565 struct ieee80211_rx_status *rx_status,
7566 struct rtl8723au_phy_stats *phy_stats,
7567 u32 rxmcs)
7568 {
7569 if (phy_stats->sgi_en)
7570 rx_status->flag |= RX_FLAG_SHORT_GI;
7571
7572 if (rxmcs < DESC_RATE_6M) {
7573 /*
7574 * Handle PHY stats for CCK rates
7575 */
7576 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
7577
7578 switch (cck_agc_rpt & 0xc0) {
7579 case 0xc0:
7580 rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
7581 break;
7582 case 0x80:
7583 rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
7584 break;
7585 case 0x40:
7586 rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
7587 break;
7588 case 0x00:
7589 rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
7590 break;
7591 }
7592 } else {
7593 rx_status->signal =
7594 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
7595 }
7596 }
7597
7598 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
7599 {
7600 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
7601 unsigned long flags;
7602
7603 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7604
7605 list_for_each_entry_safe(rx_urb, tmp,
7606 &priv->rx_urb_pending_list, list) {
7607 list_del(&rx_urb->list);
7608 priv->rx_urb_pending_count--;
7609 usb_free_urb(&rx_urb->urb);
7610 }
7611
7612 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7613 }
7614
7615 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
7616 struct rtl8xxxu_rx_urb *rx_urb)
7617 {
7618 struct sk_buff *skb;
7619 unsigned long flags;
7620 int pending = 0;
7621
7622 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7623
7624 if (!priv->shutdown) {
7625 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
7626 priv->rx_urb_pending_count++;
7627 pending = priv->rx_urb_pending_count;
7628 } else {
7629 skb = (struct sk_buff *)rx_urb->urb.context;
7630 dev_kfree_skb(skb);
7631 usb_free_urb(&rx_urb->urb);
7632 }
7633
7634 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7635
7636 if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
7637 schedule_work(&priv->rx_urb_wq);
7638 }
7639
7640 static void rtl8xxxu_rx_urb_work(struct work_struct *work)
7641 {
7642 struct rtl8xxxu_priv *priv;
7643 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
7644 struct list_head local;
7645 struct sk_buff *skb;
7646 unsigned long flags;
7647 int ret;
7648
7649 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
7650 INIT_LIST_HEAD(&local);
7651
7652 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7653
7654 list_splice_init(&priv->rx_urb_pending_list, &local);
7655 priv->rx_urb_pending_count = 0;
7656
7657 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7658
7659 list_for_each_entry_safe(rx_urb, tmp, &local, list) {
7660 list_del_init(&rx_urb->list);
7661 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
7662 /*
7663 * If out of memory or temporary error, put it back on the
7664 * queue and try again. Otherwise the device is dead/gone
7665 * and we should drop it.
7666 */
7667 switch (ret) {
7668 case 0:
7669 break;
7670 case -ENOMEM:
7671 case -EAGAIN:
7672 rtl8xxxu_queue_rx_urb(priv, rx_urb);
7673 break;
7674 default:
7675 pr_info("failed to requeue urb %i\n", ret);
7676 skb = (struct sk_buff *)rx_urb->urb.context;
7677 dev_kfree_skb(skb);
7678 usb_free_urb(&rx_urb->urb);
7679 }
7680 }
7681 }
7682
7683 static int rtl8723au_parse_rx_desc(struct rtl8xxxu_priv *priv,
7684 struct sk_buff *skb,
7685 struct ieee80211_rx_status *rx_status)
7686 {
7687 struct rtl8xxxu_rx_desc *rx_desc = (struct rtl8xxxu_rx_desc *)skb->data;
7688 struct rtl8723au_phy_stats *phy_stats;
7689 int drvinfo_sz, desc_shift;
7690
7691 skb_pull(skb, sizeof(struct rtl8xxxu_rx_desc));
7692
7693 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
7694
7695 drvinfo_sz = rx_desc->drvinfo_sz * 8;
7696 desc_shift = rx_desc->shift;
7697 skb_pull(skb, drvinfo_sz + desc_shift);
7698
7699 if (rx_desc->phy_stats)
7700 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats,
7701 rx_desc->rxmcs);
7702
7703 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
7704 rx_status->flag |= RX_FLAG_MACTIME_START;
7705
7706 if (!rx_desc->swdec)
7707 rx_status->flag |= RX_FLAG_DECRYPTED;
7708 if (rx_desc->crc32)
7709 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7710 if (rx_desc->bw)
7711 rx_status->flag |= RX_FLAG_40MHZ;
7712
7713 if (rx_desc->rxht) {
7714 rx_status->flag |= RX_FLAG_HT;
7715 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
7716 } else {
7717 rx_status->rate_idx = rx_desc->rxmcs;
7718 }
7719
7720 return RX_TYPE_DATA_PKT;
7721 }
7722
7723 static int rtl8723bu_parse_rx_desc(struct rtl8xxxu_priv *priv,
7724 struct sk_buff *skb,
7725 struct ieee80211_rx_status *rx_status)
7726 {
7727 struct rtl8723bu_rx_desc *rx_desc =
7728 (struct rtl8723bu_rx_desc *)skb->data;
7729 struct rtl8723au_phy_stats *phy_stats;
7730 int drvinfo_sz, desc_shift;
7731
7732 skb_pull(skb, sizeof(struct rtl8723bu_rx_desc));
7733
7734 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
7735
7736 drvinfo_sz = rx_desc->drvinfo_sz * 8;
7737 desc_shift = rx_desc->shift;
7738 skb_pull(skb, drvinfo_sz + desc_shift);
7739
7740 if (rx_desc->rpt_sel) {
7741 struct device *dev = &priv->udev->dev;
7742 dev_dbg(dev, "%s: C2H packet\n", __func__);
7743 return RX_TYPE_C2H;
7744 }
7745
7746 if (rx_desc->phy_stats)
7747 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats,
7748 rx_desc->rxmcs);
7749
7750 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
7751 rx_status->flag |= RX_FLAG_MACTIME_START;
7752
7753 if (!rx_desc->swdec)
7754 rx_status->flag |= RX_FLAG_DECRYPTED;
7755 if (rx_desc->crc32)
7756 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7757 if (rx_desc->bw)
7758 rx_status->flag |= RX_FLAG_40MHZ;
7759
7760 if (rx_desc->rxmcs >= DESC_RATE_MCS0) {
7761 rx_status->flag |= RX_FLAG_HT;
7762 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
7763 } else {
7764 rx_status->rate_idx = rx_desc->rxmcs;
7765 }
7766
7767 return RX_TYPE_DATA_PKT;
7768 }
7769
7770 static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv,
7771 struct sk_buff *skb)
7772 {
7773 struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data;
7774 struct device *dev = &priv->udev->dev;
7775 int len;
7776
7777 len = skb->len - 2;
7778
7779 dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n",
7780 c2h->id, c2h->seq, len, c2h->bt_info.response_source);
7781
7782 switch(c2h->id) {
7783 case C2H_8723B_BT_INFO:
7784 if (c2h->bt_info.response_source >
7785 BT_INFO_SRC_8723B_BT_ACTIVE_SEND)
7786 dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n");
7787 else
7788 dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n");
7789
7790 if (c2h->bt_info.bt_has_reset)
7791 dev_dbg(dev, "BT has been reset\n");
7792 if (c2h->bt_info.tx_rx_mask)
7793 dev_dbg(dev, "BT TRx mask\n");
7794
7795 break;
7796 case C2H_8723B_BT_MP_INFO:
7797 dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n",
7798 c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status);
7799 break;
7800 case C2H_8723B_RA_REPORT:
7801 dev_dbg(dev,
7802 "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n",
7803 c2h->ra_report.rate, c2h->ra_report.dummy0_0,
7804 c2h->ra_report.macid, c2h->ra_report.noisy_state);
7805 break;
7806 default:
7807 dev_info(dev, "Unhandled C2H event %02x seq %02x\n",
7808 c2h->id, c2h->seq);
7809 print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE,
7810 16, 1, c2h->raw.payload, len, false);
7811 break;
7812 }
7813 }
7814
7815 static void rtl8xxxu_rx_complete(struct urb *urb)
7816 {
7817 struct rtl8xxxu_rx_urb *rx_urb =
7818 container_of(urb, struct rtl8xxxu_rx_urb, urb);
7819 struct ieee80211_hw *hw = rx_urb->hw;
7820 struct rtl8xxxu_priv *priv = hw->priv;
7821 struct sk_buff *skb = (struct sk_buff *)urb->context;
7822 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
7823 struct device *dev = &priv->udev->dev;
7824 __le32 *_rx_desc_le = (__le32 *)skb->data;
7825 u32 *_rx_desc = (u32 *)skb->data;
7826 int rx_type, i;
7827
7828 for (i = 0; i < (sizeof(struct rtl8xxxu_rx_desc) / sizeof(u32)); i++)
7829 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
7830
7831 skb_put(skb, urb->actual_length);
7832
7833 if (urb->status == 0) {
7834 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
7835
7836 rx_type = priv->fops->parse_rx_desc(priv, skb, rx_status);
7837
7838 rx_status->freq = hw->conf.chandef.chan->center_freq;
7839 rx_status->band = hw->conf.chandef.chan->band;
7840
7841 if (rx_type == RX_TYPE_DATA_PKT)
7842 ieee80211_rx_irqsafe(hw, skb);
7843 else {
7844 rtl8723bu_handle_c2h(priv, skb);
7845 dev_kfree_skb(skb);
7846 }
7847
7848 skb = NULL;
7849 rx_urb->urb.context = NULL;
7850 rtl8xxxu_queue_rx_urb(priv, rx_urb);
7851 } else {
7852 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
7853 goto cleanup;
7854 }
7855 return;
7856
7857 cleanup:
7858 usb_free_urb(urb);
7859 dev_kfree_skb(skb);
7860 return;
7861 }
7862
7863 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
7864 struct rtl8xxxu_rx_urb *rx_urb)
7865 {
7866 struct sk_buff *skb;
7867 int skb_size;
7868 int ret;
7869
7870 skb_size = sizeof(struct rtl8xxxu_rx_desc) + RTL_RX_BUFFER_SIZE;
7871 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
7872 if (!skb)
7873 return -ENOMEM;
7874
7875 memset(skb->data, 0, sizeof(struct rtl8xxxu_rx_desc));
7876 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
7877 skb_size, rtl8xxxu_rx_complete, skb);
7878 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
7879 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
7880 if (ret)
7881 usb_unanchor_urb(&rx_urb->urb);
7882 return ret;
7883 }
7884
7885 static void rtl8xxxu_int_complete(struct urb *urb)
7886 {
7887 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
7888 struct device *dev = &priv->udev->dev;
7889 int ret;
7890
7891 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
7892 if (urb->status == 0) {
7893 usb_anchor_urb(urb, &priv->int_anchor);
7894 ret = usb_submit_urb(urb, GFP_ATOMIC);
7895 if (ret)
7896 usb_unanchor_urb(urb);
7897 } else {
7898 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
7899 }
7900 }
7901
7902
7903 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
7904 {
7905 struct rtl8xxxu_priv *priv = hw->priv;
7906 struct urb *urb;
7907 u32 val32;
7908 int ret;
7909
7910 urb = usb_alloc_urb(0, GFP_KERNEL);
7911 if (!urb)
7912 return -ENOMEM;
7913
7914 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
7915 priv->int_buf, USB_INTR_CONTENT_LENGTH,
7916 rtl8xxxu_int_complete, priv, 1);
7917 usb_anchor_urb(urb, &priv->int_anchor);
7918 ret = usb_submit_urb(urb, GFP_KERNEL);
7919 if (ret) {
7920 usb_unanchor_urb(urb);
7921 goto error;
7922 }
7923
7924 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
7925 val32 |= USB_HIMR_CPWM;
7926 rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
7927
7928 error:
7929 return ret;
7930 }
7931
7932 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
7933 struct ieee80211_vif *vif)
7934 {
7935 struct rtl8xxxu_priv *priv = hw->priv;
7936 int ret;
7937 u8 val8;
7938
7939 switch (vif->type) {
7940 case NL80211_IFTYPE_STATION:
7941 rtl8723a_stop_tx_beacon(priv);
7942
7943 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
7944 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
7945 BEACON_DISABLE_TSF_UPDATE;
7946 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
7947 ret = 0;
7948 break;
7949 default:
7950 ret = -EOPNOTSUPP;
7951 }
7952
7953 rtl8xxxu_set_linktype(priv, vif->type);
7954
7955 return ret;
7956 }
7957
7958 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
7959 struct ieee80211_vif *vif)
7960 {
7961 struct rtl8xxxu_priv *priv = hw->priv;
7962
7963 dev_dbg(&priv->udev->dev, "%s\n", __func__);
7964 }
7965
7966 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
7967 {
7968 struct rtl8xxxu_priv *priv = hw->priv;
7969 struct device *dev = &priv->udev->dev;
7970 u16 val16;
7971 int ret = 0, channel;
7972 bool ht40;
7973
7974 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
7975 dev_info(dev,
7976 "%s: channel: %i (changed %08x chandef.width %02x)\n",
7977 __func__, hw->conf.chandef.chan->hw_value,
7978 changed, hw->conf.chandef.width);
7979
7980 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
7981 val16 = ((hw->conf.long_frame_max_tx_count <<
7982 RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
7983 ((hw->conf.short_frame_max_tx_count <<
7984 RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
7985 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
7986 }
7987
7988 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
7989 switch (hw->conf.chandef.width) {
7990 case NL80211_CHAN_WIDTH_20_NOHT:
7991 case NL80211_CHAN_WIDTH_20:
7992 ht40 = false;
7993 break;
7994 case NL80211_CHAN_WIDTH_40:
7995 ht40 = true;
7996 break;
7997 default:
7998 ret = -ENOTSUPP;
7999 goto exit;
8000 }
8001
8002 channel = hw->conf.chandef.chan->hw_value;
8003
8004 priv->fops->set_tx_power(priv, channel, ht40);
8005
8006 priv->fops->config_channel(hw);
8007 }
8008
8009 exit:
8010 return ret;
8011 }
8012
8013 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
8014 struct ieee80211_vif *vif, u16 queue,
8015 const struct ieee80211_tx_queue_params *param)
8016 {
8017 struct rtl8xxxu_priv *priv = hw->priv;
8018 struct device *dev = &priv->udev->dev;
8019 u32 val32;
8020 u8 aifs, acm_ctrl, acm_bit;
8021
8022 aifs = param->aifs;
8023
8024 val32 = aifs |
8025 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
8026 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
8027 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
8028
8029 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
8030 dev_dbg(dev,
8031 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
8032 __func__, queue, val32, param->acm, acm_ctrl);
8033
8034 switch (queue) {
8035 case IEEE80211_AC_VO:
8036 acm_bit = ACM_HW_CTRL_VO;
8037 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
8038 break;
8039 case IEEE80211_AC_VI:
8040 acm_bit = ACM_HW_CTRL_VI;
8041 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
8042 break;
8043 case IEEE80211_AC_BE:
8044 acm_bit = ACM_HW_CTRL_BE;
8045 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
8046 break;
8047 case IEEE80211_AC_BK:
8048 acm_bit = ACM_HW_CTRL_BK;
8049 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
8050 break;
8051 default:
8052 acm_bit = 0;
8053 break;
8054 }
8055
8056 if (param->acm)
8057 acm_ctrl |= acm_bit;
8058 else
8059 acm_ctrl &= ~acm_bit;
8060 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
8061
8062 return 0;
8063 }
8064
8065 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
8066 unsigned int changed_flags,
8067 unsigned int *total_flags, u64 multicast)
8068 {
8069 struct rtl8xxxu_priv *priv = hw->priv;
8070 u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
8071
8072 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
8073 __func__, changed_flags, *total_flags);
8074
8075 /*
8076 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
8077 */
8078
8079 if (*total_flags & FIF_FCSFAIL)
8080 rcr |= RCR_ACCEPT_CRC32;
8081 else
8082 rcr &= ~RCR_ACCEPT_CRC32;
8083
8084 /*
8085 * FIF_PLCPFAIL not supported?
8086 */
8087
8088 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
8089 rcr &= ~RCR_CHECK_BSSID_BEACON;
8090 else
8091 rcr |= RCR_CHECK_BSSID_BEACON;
8092
8093 if (*total_flags & FIF_CONTROL)
8094 rcr |= RCR_ACCEPT_CTRL_FRAME;
8095 else
8096 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
8097
8098 if (*total_flags & FIF_OTHER_BSS) {
8099 rcr |= RCR_ACCEPT_AP;
8100 rcr &= ~RCR_CHECK_BSSID_MATCH;
8101 } else {
8102 rcr &= ~RCR_ACCEPT_AP;
8103 rcr |= RCR_CHECK_BSSID_MATCH;
8104 }
8105
8106 if (*total_flags & FIF_PSPOLL)
8107 rcr |= RCR_ACCEPT_PM;
8108 else
8109 rcr &= ~RCR_ACCEPT_PM;
8110
8111 /*
8112 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
8113 */
8114
8115 rtl8xxxu_write32(priv, REG_RCR, rcr);
8116
8117 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
8118 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
8119 FIF_PROBE_REQ);
8120 }
8121
8122 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
8123 {
8124 if (rts > 2347)
8125 return -EINVAL;
8126
8127 return 0;
8128 }
8129
8130 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
8131 struct ieee80211_vif *vif,
8132 struct ieee80211_sta *sta,
8133 struct ieee80211_key_conf *key)
8134 {
8135 struct rtl8xxxu_priv *priv = hw->priv;
8136 struct device *dev = &priv->udev->dev;
8137 u8 mac_addr[ETH_ALEN];
8138 u8 val8;
8139 u16 val16;
8140 u32 val32;
8141 int retval = -EOPNOTSUPP;
8142
8143 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
8144 __func__, cmd, key->cipher, key->keyidx);
8145
8146 if (vif->type != NL80211_IFTYPE_STATION)
8147 return -EOPNOTSUPP;
8148
8149 if (key->keyidx > 3)
8150 return -EOPNOTSUPP;
8151
8152 switch (key->cipher) {
8153 case WLAN_CIPHER_SUITE_WEP40:
8154 case WLAN_CIPHER_SUITE_WEP104:
8155
8156 break;
8157 case WLAN_CIPHER_SUITE_CCMP:
8158 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
8159 break;
8160 case WLAN_CIPHER_SUITE_TKIP:
8161 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
8162 default:
8163 return -EOPNOTSUPP;
8164 }
8165
8166 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
8167 dev_dbg(dev, "%s: pairwise key\n", __func__);
8168 ether_addr_copy(mac_addr, sta->addr);
8169 } else {
8170 dev_dbg(dev, "%s: group key\n", __func__);
8171 eth_broadcast_addr(mac_addr);
8172 }
8173
8174 val16 = rtl8xxxu_read16(priv, REG_CR);
8175 val16 |= CR_SECURITY_ENABLE;
8176 rtl8xxxu_write16(priv, REG_CR, val16);
8177
8178 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
8179 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
8180 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
8181 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
8182
8183 switch (cmd) {
8184 case SET_KEY:
8185 key->hw_key_idx = key->keyidx;
8186 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
8187 rtl8xxxu_cam_write(priv, key, mac_addr);
8188 retval = 0;
8189 break;
8190 case DISABLE_KEY:
8191 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
8192 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
8193 key->keyidx << CAM_CMD_KEY_SHIFT;
8194 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
8195 retval = 0;
8196 break;
8197 default:
8198 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
8199 }
8200
8201 return retval;
8202 }
8203
8204 static int
8205 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
8206 struct ieee80211_ampdu_params *params)
8207 {
8208 struct rtl8xxxu_priv *priv = hw->priv;
8209 struct device *dev = &priv->udev->dev;
8210 u8 ampdu_factor, ampdu_density;
8211 struct ieee80211_sta *sta = params->sta;
8212 enum ieee80211_ampdu_mlme_action action = params->action;
8213
8214 switch (action) {
8215 case IEEE80211_AMPDU_TX_START:
8216 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
8217 ampdu_factor = sta->ht_cap.ampdu_factor;
8218 ampdu_density = sta->ht_cap.ampdu_density;
8219 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
8220 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
8221 dev_dbg(dev,
8222 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
8223 ampdu_factor, ampdu_density);
8224 break;
8225 case IEEE80211_AMPDU_TX_STOP_FLUSH:
8226 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
8227 rtl8xxxu_set_ampdu_factor(priv, 0);
8228 rtl8xxxu_set_ampdu_min_space(priv, 0);
8229 break;
8230 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
8231 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
8232 __func__);
8233 rtl8xxxu_set_ampdu_factor(priv, 0);
8234 rtl8xxxu_set_ampdu_min_space(priv, 0);
8235 break;
8236 case IEEE80211_AMPDU_RX_START:
8237 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
8238 break;
8239 case IEEE80211_AMPDU_RX_STOP:
8240 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
8241 break;
8242 default:
8243 break;
8244 }
8245 return 0;
8246 }
8247
8248 static int rtl8xxxu_start(struct ieee80211_hw *hw)
8249 {
8250 struct rtl8xxxu_priv *priv = hw->priv;
8251 struct rtl8xxxu_rx_urb *rx_urb;
8252 struct rtl8xxxu_tx_urb *tx_urb;
8253 unsigned long flags;
8254 int ret, i;
8255
8256 ret = 0;
8257
8258 init_usb_anchor(&priv->rx_anchor);
8259 init_usb_anchor(&priv->tx_anchor);
8260 init_usb_anchor(&priv->int_anchor);
8261
8262 priv->fops->enable_rf(priv);
8263 if (priv->usb_interrupts) {
8264 ret = rtl8xxxu_submit_int_urb(hw);
8265 if (ret)
8266 goto exit;
8267 }
8268
8269 for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
8270 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
8271 if (!tx_urb) {
8272 if (!i)
8273 ret = -ENOMEM;
8274
8275 goto error_out;
8276 }
8277 usb_init_urb(&tx_urb->urb);
8278 INIT_LIST_HEAD(&tx_urb->list);
8279 tx_urb->hw = hw;
8280 list_add(&tx_urb->list, &priv->tx_urb_free_list);
8281 priv->tx_urb_free_count++;
8282 }
8283
8284 priv->tx_stopped = false;
8285
8286 spin_lock_irqsave(&priv->rx_urb_lock, flags);
8287 priv->shutdown = false;
8288 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
8289
8290 for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
8291 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
8292 if (!rx_urb) {
8293 if (!i)
8294 ret = -ENOMEM;
8295
8296 goto error_out;
8297 }
8298 usb_init_urb(&rx_urb->urb);
8299 INIT_LIST_HEAD(&rx_urb->list);
8300 rx_urb->hw = hw;
8301
8302 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
8303 }
8304 exit:
8305 /*
8306 * Accept all data and mgmt frames
8307 */
8308 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
8309 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
8310
8311 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
8312
8313 return ret;
8314
8315 error_out:
8316 rtl8xxxu_free_tx_resources(priv);
8317 /*
8318 * Disable all data and mgmt frames
8319 */
8320 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
8321 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
8322
8323 return ret;
8324 }
8325
8326 static void rtl8xxxu_stop(struct ieee80211_hw *hw)
8327 {
8328 struct rtl8xxxu_priv *priv = hw->priv;
8329 unsigned long flags;
8330
8331 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
8332
8333 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
8334 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
8335
8336 spin_lock_irqsave(&priv->rx_urb_lock, flags);
8337 priv->shutdown = true;
8338 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
8339
8340 usb_kill_anchored_urbs(&priv->rx_anchor);
8341 usb_kill_anchored_urbs(&priv->tx_anchor);
8342 if (priv->usb_interrupts)
8343 usb_kill_anchored_urbs(&priv->int_anchor);
8344
8345 priv->fops->disable_rf(priv);
8346
8347 /*
8348 * Disable interrupts
8349 */
8350 if (priv->usb_interrupts)
8351 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
8352
8353 rtl8xxxu_free_rx_resources(priv);
8354 rtl8xxxu_free_tx_resources(priv);
8355 }
8356
8357 static const struct ieee80211_ops rtl8xxxu_ops = {
8358 .tx = rtl8xxxu_tx,
8359 .add_interface = rtl8xxxu_add_interface,
8360 .remove_interface = rtl8xxxu_remove_interface,
8361 .config = rtl8xxxu_config,
8362 .conf_tx = rtl8xxxu_conf_tx,
8363 .bss_info_changed = rtl8xxxu_bss_info_changed,
8364 .configure_filter = rtl8xxxu_configure_filter,
8365 .set_rts_threshold = rtl8xxxu_set_rts_threshold,
8366 .start = rtl8xxxu_start,
8367 .stop = rtl8xxxu_stop,
8368 .sw_scan_start = rtl8xxxu_sw_scan_start,
8369 .sw_scan_complete = rtl8xxxu_sw_scan_complete,
8370 .set_key = rtl8xxxu_set_key,
8371 .ampdu_action = rtl8xxxu_ampdu_action,
8372 };
8373
8374 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
8375 struct usb_interface *interface)
8376 {
8377 struct usb_interface_descriptor *interface_desc;
8378 struct usb_host_interface *host_interface;
8379 struct usb_endpoint_descriptor *endpoint;
8380 struct device *dev = &priv->udev->dev;
8381 int i, j = 0, endpoints;
8382 u8 dir, xtype, num;
8383 int ret = 0;
8384
8385 host_interface = &interface->altsetting[0];
8386 interface_desc = &host_interface->desc;
8387 endpoints = interface_desc->bNumEndpoints;
8388
8389 for (i = 0; i < endpoints; i++) {
8390 endpoint = &host_interface->endpoint[i].desc;
8391
8392 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
8393 num = usb_endpoint_num(endpoint);
8394 xtype = usb_endpoint_type(endpoint);
8395 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
8396 dev_dbg(dev,
8397 "%s: endpoint: dir %02x, # %02x, type %02x\n",
8398 __func__, dir, num, xtype);
8399 if (usb_endpoint_dir_in(endpoint) &&
8400 usb_endpoint_xfer_bulk(endpoint)) {
8401 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
8402 dev_dbg(dev, "%s: in endpoint num %i\n",
8403 __func__, num);
8404
8405 if (priv->pipe_in) {
8406 dev_warn(dev,
8407 "%s: Too many IN pipes\n", __func__);
8408 ret = -EINVAL;
8409 goto exit;
8410 }
8411
8412 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
8413 }
8414
8415 if (usb_endpoint_dir_in(endpoint) &&
8416 usb_endpoint_xfer_int(endpoint)) {
8417 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
8418 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
8419 __func__, num);
8420
8421 if (priv->pipe_interrupt) {
8422 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
8423 __func__);
8424 ret = -EINVAL;
8425 goto exit;
8426 }
8427
8428 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
8429 }
8430
8431 if (usb_endpoint_dir_out(endpoint) &&
8432 usb_endpoint_xfer_bulk(endpoint)) {
8433 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
8434 dev_dbg(dev, "%s: out endpoint num %i\n",
8435 __func__, num);
8436 if (j >= RTL8XXXU_OUT_ENDPOINTS) {
8437 dev_warn(dev,
8438 "%s: Too many OUT pipes\n", __func__);
8439 ret = -EINVAL;
8440 goto exit;
8441 }
8442 priv->out_ep[j++] = num;
8443 }
8444 }
8445 exit:
8446 priv->nr_out_eps = j;
8447 return ret;
8448 }
8449
8450 static int rtl8xxxu_probe(struct usb_interface *interface,
8451 const struct usb_device_id *id)
8452 {
8453 struct rtl8xxxu_priv *priv;
8454 struct ieee80211_hw *hw;
8455 struct usb_device *udev;
8456 struct ieee80211_supported_band *sband;
8457 int ret = 0;
8458 int untested = 1;
8459
8460 udev = usb_get_dev(interface_to_usbdev(interface));
8461
8462 switch (id->idVendor) {
8463 case USB_VENDOR_ID_REALTEK:
8464 switch(id->idProduct) {
8465 case 0x1724:
8466 case 0x8176:
8467 case 0x8178:
8468 case 0x817f:
8469 untested = 0;
8470 break;
8471 }
8472 break;
8473 case 0x7392:
8474 if (id->idProduct == 0x7811)
8475 untested = 0;
8476 break;
8477 default:
8478 break;
8479 }
8480
8481 if (untested) {
8482 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE;
8483 dev_info(&udev->dev,
8484 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
8485 id->idVendor, id->idProduct);
8486 dev_info(&udev->dev,
8487 "Please report results to Jes.Sorensen@gmail.com\n");
8488 }
8489
8490 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
8491 if (!hw) {
8492 ret = -ENOMEM;
8493 goto exit;
8494 }
8495
8496 priv = hw->priv;
8497 priv->hw = hw;
8498 priv->udev = udev;
8499 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
8500 mutex_init(&priv->usb_buf_mutex);
8501 mutex_init(&priv->h2c_mutex);
8502 INIT_LIST_HEAD(&priv->tx_urb_free_list);
8503 spin_lock_init(&priv->tx_urb_lock);
8504 INIT_LIST_HEAD(&priv->rx_urb_pending_list);
8505 spin_lock_init(&priv->rx_urb_lock);
8506 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
8507
8508 usb_set_intfdata(interface, hw);
8509
8510 ret = rtl8xxxu_parse_usb(priv, interface);
8511 if (ret)
8512 goto exit;
8513
8514 ret = rtl8xxxu_identify_chip(priv);
8515 if (ret) {
8516 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
8517 goto exit;
8518 }
8519
8520 ret = rtl8xxxu_read_efuse(priv);
8521 if (ret) {
8522 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
8523 goto exit;
8524 }
8525
8526 ret = priv->fops->parse_efuse(priv);
8527 if (ret) {
8528 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
8529 goto exit;
8530 }
8531
8532 rtl8xxxu_print_chipinfo(priv);
8533
8534 ret = priv->fops->load_firmware(priv);
8535 if (ret) {
8536 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
8537 goto exit;
8538 }
8539
8540 ret = rtl8xxxu_init_device(hw);
8541
8542 hw->wiphy->max_scan_ssids = 1;
8543 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
8544 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
8545 hw->queues = 4;
8546
8547 sband = &rtl8xxxu_supported_band;
8548 sband->ht_cap.ht_supported = true;
8549 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
8550 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
8551 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
8552 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
8553 sband->ht_cap.mcs.rx_mask[0] = 0xff;
8554 sband->ht_cap.mcs.rx_mask[4] = 0x01;
8555 if (priv->rf_paths > 1) {
8556 sband->ht_cap.mcs.rx_mask[1] = 0xff;
8557 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
8558 }
8559 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
8560 /*
8561 * Some APs will negotiate HT20_40 in a noisy environment leading
8562 * to miserable performance. Rather than defaulting to this, only
8563 * enable it if explicitly requested at module load time.
8564 */
8565 if (rtl8xxxu_ht40_2g) {
8566 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
8567 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
8568 }
8569 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
8570
8571 hw->wiphy->rts_threshold = 2347;
8572
8573 SET_IEEE80211_DEV(priv->hw, &interface->dev);
8574 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
8575
8576 hw->extra_tx_headroom = priv->fops->tx_desc_size;
8577 ieee80211_hw_set(hw, SIGNAL_DBM);
8578 /*
8579 * The firmware handles rate control
8580 */
8581 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
8582 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
8583
8584 ret = ieee80211_register_hw(priv->hw);
8585 if (ret) {
8586 dev_err(&udev->dev, "%s: Failed to register: %i\n",
8587 __func__, ret);
8588 goto exit;
8589 }
8590
8591 exit:
8592 if (ret < 0)
8593 usb_put_dev(udev);
8594 return ret;
8595 }
8596
8597 static void rtl8xxxu_disconnect(struct usb_interface *interface)
8598 {
8599 struct rtl8xxxu_priv *priv;
8600 struct ieee80211_hw *hw;
8601
8602 hw = usb_get_intfdata(interface);
8603 priv = hw->priv;
8604
8605 rtl8xxxu_disable_device(hw);
8606 usb_set_intfdata(interface, NULL);
8607
8608 dev_info(&priv->udev->dev, "disconnecting\n");
8609
8610 ieee80211_unregister_hw(hw);
8611
8612 kfree(priv->fw_data);
8613 mutex_destroy(&priv->usb_buf_mutex);
8614 mutex_destroy(&priv->h2c_mutex);
8615
8616 usb_put_dev(priv->udev);
8617 ieee80211_free_hw(hw);
8618 }
8619
8620 static struct rtl8xxxu_fileops rtl8723au_fops = {
8621 .parse_efuse = rtl8723au_parse_efuse,
8622 .load_firmware = rtl8723au_load_firmware,
8623 .power_on = rtl8723au_power_on,
8624 .power_off = rtl8xxxu_power_off,
8625 .reset_8051 = rtl8xxxu_reset_8051,
8626 .llt_init = rtl8xxxu_init_llt_table,
8627 .phy_iq_calibrate = rtl8723au_phy_iq_calibrate,
8628 .config_channel = rtl8723au_config_channel,
8629 .parse_rx_desc = rtl8723au_parse_rx_desc,
8630 .enable_rf = rtl8723a_enable_rf,
8631 .disable_rf = rtl8723a_disable_rf,
8632 .set_tx_power = rtl8723a_set_tx_power,
8633 .update_rate_mask = rtl8723au_update_rate_mask,
8634 .report_connect = rtl8723au_report_connect,
8635 .writeN_block_size = 1024,
8636 .mbox_ext_reg = REG_HMBOX_EXT_0,
8637 .mbox_ext_width = 2,
8638 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32),
8639 .adda_1t_init = 0x0b1b25a0,
8640 .adda_1t_path_on = 0x0bdb25a0,
8641 .adda_2t_path_on_a = 0x04db25a4,
8642 .adda_2t_path_on_b = 0x0b1b25a4,
8643 .mactable = rtl8723a_mac_init_table,
8644 };
8645
8646 static struct rtl8xxxu_fileops rtl8723bu_fops = {
8647 .parse_efuse = rtl8723bu_parse_efuse,
8648 .load_firmware = rtl8723bu_load_firmware,
8649 .power_on = rtl8723bu_power_on,
8650 .power_off = rtl8723bu_power_off,
8651 .reset_8051 = rtl8723bu_reset_8051,
8652 .llt_init = rtl8xxxu_auto_llt_table,
8653 .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection,
8654 .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
8655 .config_channel = rtl8723bu_config_channel,
8656 .parse_rx_desc = rtl8723bu_parse_rx_desc,
8657 .init_aggregation = rtl8723bu_init_aggregation,
8658 .init_statistics = rtl8723bu_init_statistics,
8659 .enable_rf = rtl8723b_enable_rf,
8660 .disable_rf = rtl8723b_disable_rf,
8661 .set_tx_power = rtl8723b_set_tx_power,
8662 .update_rate_mask = rtl8723bu_update_rate_mask,
8663 .report_connect = rtl8723bu_report_connect,
8664 .writeN_block_size = 1024,
8665 .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
8666 .mbox_ext_width = 4,
8667 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40),
8668 .has_s0s1 = 1,
8669 .adda_1t_init = 0x01c00014,
8670 .adda_1t_path_on = 0x01c00014,
8671 .adda_2t_path_on_a = 0x01c00014,
8672 .adda_2t_path_on_b = 0x01c00014,
8673 .mactable = rtl8723b_mac_init_table,
8674 };
8675
8676 #ifdef CONFIG_RTL8XXXU_UNTESTED
8677
8678 static struct rtl8xxxu_fileops rtl8192cu_fops = {
8679 .parse_efuse = rtl8192cu_parse_efuse,
8680 .load_firmware = rtl8192cu_load_firmware,
8681 .power_on = rtl8192cu_power_on,
8682 .power_off = rtl8xxxu_power_off,
8683 .reset_8051 = rtl8xxxu_reset_8051,
8684 .llt_init = rtl8xxxu_init_llt_table,
8685 .phy_iq_calibrate = rtl8723au_phy_iq_calibrate,
8686 .config_channel = rtl8723au_config_channel,
8687 .parse_rx_desc = rtl8723au_parse_rx_desc,
8688 .enable_rf = rtl8723a_enable_rf,
8689 .disable_rf = rtl8723a_disable_rf,
8690 .set_tx_power = rtl8723a_set_tx_power,
8691 .update_rate_mask = rtl8723au_update_rate_mask,
8692 .report_connect = rtl8723au_report_connect,
8693 .writeN_block_size = 128,
8694 .mbox_ext_reg = REG_HMBOX_EXT_0,
8695 .mbox_ext_width = 2,
8696 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32),
8697 .adda_1t_init = 0x0b1b25a0,
8698 .adda_1t_path_on = 0x0bdb25a0,
8699 .adda_2t_path_on_a = 0x04db25a4,
8700 .adda_2t_path_on_b = 0x0b1b25a4,
8701 .mactable = rtl8723a_mac_init_table,
8702 };
8703
8704 #endif
8705
8706 static struct rtl8xxxu_fileops rtl8192eu_fops = {
8707 .parse_efuse = rtl8192eu_parse_efuse,
8708 .load_firmware = rtl8192eu_load_firmware,
8709 .power_on = rtl8192eu_power_on,
8710 .power_off = rtl8xxxu_power_off,
8711 .reset_8051 = rtl8xxxu_reset_8051,
8712 .llt_init = rtl8xxxu_auto_llt_table,
8713 .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
8714 .config_channel = rtl8723bu_config_channel,
8715 .parse_rx_desc = rtl8723bu_parse_rx_desc,
8716 .enable_rf = rtl8723b_enable_rf,
8717 .disable_rf = rtl8723b_disable_rf,
8718 .set_tx_power = rtl8723b_set_tx_power,
8719 .update_rate_mask = rtl8723bu_update_rate_mask,
8720 .report_connect = rtl8723bu_report_connect,
8721 .writeN_block_size = 128,
8722 .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
8723 .mbox_ext_width = 4,
8724 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40),
8725 .has_s0s1 = 1,
8726 .adda_1t_init = 0x0fc01616,
8727 .adda_1t_path_on = 0x0fc01616,
8728 .adda_2t_path_on_a = 0x0fc01616,
8729 .adda_2t_path_on_b = 0x0fc01616,
8730 .mactable = rtl8192e_mac_init_table,
8731 };
8732
8733 static struct usb_device_id dev_table[] = {
8734 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
8735 .driver_info = (unsigned long)&rtl8723au_fops},
8736 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
8737 .driver_info = (unsigned long)&rtl8723au_fops},
8738 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
8739 .driver_info = (unsigned long)&rtl8723au_fops},
8740 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
8741 .driver_info = (unsigned long)&rtl8192eu_fops},
8742 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
8743 .driver_info = (unsigned long)&rtl8723bu_fops},
8744 #ifdef CONFIG_RTL8XXXU_UNTESTED
8745 /* Still supported by rtlwifi */
8746 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
8747 .driver_info = (unsigned long)&rtl8192cu_fops},
8748 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
8749 .driver_info = (unsigned long)&rtl8192cu_fops},
8750 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
8751 .driver_info = (unsigned long)&rtl8192cu_fops},
8752 /* Tested by Larry Finger */
8753 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
8754 .driver_info = (unsigned long)&rtl8192cu_fops},
8755 /* Currently untested 8188 series devices */
8756 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
8757 .driver_info = (unsigned long)&rtl8192cu_fops},
8758 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
8759 .driver_info = (unsigned long)&rtl8192cu_fops},
8760 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
8761 .driver_info = (unsigned long)&rtl8192cu_fops},
8762 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
8763 .driver_info = (unsigned long)&rtl8192cu_fops},
8764 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
8765 .driver_info = (unsigned long)&rtl8192cu_fops},
8766 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
8767 .driver_info = (unsigned long)&rtl8192cu_fops},
8768 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
8769 .driver_info = (unsigned long)&rtl8192cu_fops},
8770 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
8771 .driver_info = (unsigned long)&rtl8192cu_fops},
8772 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
8773 .driver_info = (unsigned long)&rtl8192cu_fops},
8774 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
8775 .driver_info = (unsigned long)&rtl8192cu_fops},
8776 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
8777 .driver_info = (unsigned long)&rtl8192cu_fops},
8778 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
8779 .driver_info = (unsigned long)&rtl8192cu_fops},
8780 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
8781 .driver_info = (unsigned long)&rtl8192cu_fops},
8782 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
8783 .driver_info = (unsigned long)&rtl8192cu_fops},
8784 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
8785 .driver_info = (unsigned long)&rtl8192cu_fops},
8786 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
8787 .driver_info = (unsigned long)&rtl8192cu_fops},
8788 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
8789 .driver_info = (unsigned long)&rtl8192cu_fops},
8790 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
8791 .driver_info = (unsigned long)&rtl8192cu_fops},
8792 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
8793 .driver_info = (unsigned long)&rtl8192cu_fops},
8794 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
8795 .driver_info = (unsigned long)&rtl8192cu_fops},
8796 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
8797 .driver_info = (unsigned long)&rtl8192cu_fops},
8798 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
8799 .driver_info = (unsigned long)&rtl8192cu_fops},
8800 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
8801 .driver_info = (unsigned long)&rtl8192cu_fops},
8802 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
8803 .driver_info = (unsigned long)&rtl8192cu_fops},
8804 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
8805 .driver_info = (unsigned long)&rtl8192cu_fops},
8806 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
8807 .driver_info = (unsigned long)&rtl8192cu_fops},
8808 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
8809 .driver_info = (unsigned long)&rtl8192cu_fops},
8810 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
8811 .driver_info = (unsigned long)&rtl8192cu_fops},
8812 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
8813 .driver_info = (unsigned long)&rtl8192cu_fops},
8814 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
8815 .driver_info = (unsigned long)&rtl8192cu_fops},
8816 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
8817 .driver_info = (unsigned long)&rtl8192cu_fops},
8818 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
8819 .driver_info = (unsigned long)&rtl8192cu_fops},
8820 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
8821 .driver_info = (unsigned long)&rtl8192cu_fops},
8822 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
8823 .driver_info = (unsigned long)&rtl8192cu_fops},
8824 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
8825 .driver_info = (unsigned long)&rtl8192cu_fops},
8826 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
8827 .driver_info = (unsigned long)&rtl8192cu_fops},
8828 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
8829 .driver_info = (unsigned long)&rtl8192cu_fops},
8830 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
8831 .driver_info = (unsigned long)&rtl8192cu_fops},
8832 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
8833 .driver_info = (unsigned long)&rtl8192cu_fops},
8834 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
8835 .driver_info = (unsigned long)&rtl8192cu_fops},
8836 /* Currently untested 8192 series devices */
8837 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
8838 .driver_info = (unsigned long)&rtl8192cu_fops},
8839 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
8840 .driver_info = (unsigned long)&rtl8192cu_fops},
8841 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
8842 .driver_info = (unsigned long)&rtl8192cu_fops},
8843 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
8844 .driver_info = (unsigned long)&rtl8192cu_fops},
8845 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
8846 .driver_info = (unsigned long)&rtl8192cu_fops},
8847 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
8848 .driver_info = (unsigned long)&rtl8192cu_fops},
8849 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
8850 .driver_info = (unsigned long)&rtl8192cu_fops},
8851 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
8852 .driver_info = (unsigned long)&rtl8192cu_fops},
8853 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
8854 .driver_info = (unsigned long)&rtl8192cu_fops},
8855 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
8856 .driver_info = (unsigned long)&rtl8192cu_fops},
8857 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
8858 .driver_info = (unsigned long)&rtl8192cu_fops},
8859 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
8860 .driver_info = (unsigned long)&rtl8192cu_fops},
8861 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
8862 .driver_info = (unsigned long)&rtl8192cu_fops},
8863 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
8864 .driver_info = (unsigned long)&rtl8192cu_fops},
8865 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
8866 .driver_info = (unsigned long)&rtl8192cu_fops},
8867 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
8868 .driver_info = (unsigned long)&rtl8192cu_fops},
8869 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
8870 .driver_info = (unsigned long)&rtl8192cu_fops},
8871 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
8872 .driver_info = (unsigned long)&rtl8192cu_fops},
8873 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
8874 .driver_info = (unsigned long)&rtl8192cu_fops},
8875 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
8876 .driver_info = (unsigned long)&rtl8192cu_fops},
8877 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
8878 .driver_info = (unsigned long)&rtl8192cu_fops},
8879 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
8880 .driver_info = (unsigned long)&rtl8192cu_fops},
8881 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
8882 .driver_info = (unsigned long)&rtl8192cu_fops},
8883 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
8884 .driver_info = (unsigned long)&rtl8192cu_fops},
8885 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
8886 .driver_info = (unsigned long)&rtl8192cu_fops},
8887 #endif
8888 { }
8889 };
8890
8891 static struct usb_driver rtl8xxxu_driver = {
8892 .name = DRIVER_NAME,
8893 .probe = rtl8xxxu_probe,
8894 .disconnect = rtl8xxxu_disconnect,
8895 .id_table = dev_table,
8896 .disable_hub_initiated_lpm = 1,
8897 };
8898
8899 static int __init rtl8xxxu_module_init(void)
8900 {
8901 int res;
8902
8903 res = usb_register(&rtl8xxxu_driver);
8904 if (res < 0)
8905 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
8906
8907 return res;
8908 }
8909
8910 static void __exit rtl8xxxu_module_exit(void)
8911 {
8912 usb_deregister(&rtl8xxxu_driver);
8913 }
8914
8915
8916 MODULE_DEVICE_TABLE(usb, dev_table);
8917
8918 module_init(rtl8xxxu_module_init);
8919 module_exit(rtl8xxxu_module_exit);
Linux kernel - Deliverables
This page took 0.279709 seconds and 5 git commands to generate.