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rtl8xxxu: Parse efuse power indices for 8723bu
[deliverable/linux.git] / drivers / net / wireless / realtek / rtl8xxxu / rtl8xxxu.c
1 /*
2 * RTL8XXXU mac80211 USB driver
3 *
4 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
5 *
6 * Portions, notably calibration code:
7 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
8 *
9 * This driver was written as a replacement for the vendor provided
10 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
11 * their programming interface, I have started adding support for
12 * additional 8xxx chips like the 8192cu, 8188cus, etc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of version 2 of the GNU General Public License as
16 * published by the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * more details.
22 */
23
24 #include <linux/init.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/errno.h>
28 #include <linux/slab.h>
29 #include <linux/module.h>
30 #include <linux/spinlock.h>
31 #include <linux/list.h>
32 #include <linux/usb.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/wireless.h>
37 #include <linux/firmware.h>
38 #include <linux/moduleparam.h>
39 #include <net/mac80211.h>
40 #include "rtl8xxxu.h"
41 #include "rtl8xxxu_regs.h"
42
43 #define DRIVER_NAME "rtl8xxxu"
44
45 static int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
46 static bool rtl8xxxu_ht40_2g;
47
48 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
49 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
50 MODULE_LICENSE("GPL");
51 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
52 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
53 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
54 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
55 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
56 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
57 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
58 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
59 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
60
61 module_param_named(debug, rtl8xxxu_debug, int, 0600);
62 MODULE_PARM_DESC(debug, "Set debug mask");
63 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
64 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
65
66 #define USB_VENDOR_ID_REALTEK 0x0bda
67 /* Minimum IEEE80211_MAX_FRAME_LEN */
68 #define RTL_RX_BUFFER_SIZE IEEE80211_MAX_FRAME_LEN
69 #define RTL8XXXU_RX_URBS 32
70 #define RTL8XXXU_RX_URB_PENDING_WATER 8
71 #define RTL8XXXU_TX_URBS 64
72 #define RTL8XXXU_TX_URB_LOW_WATER 25
73 #define RTL8XXXU_TX_URB_HIGH_WATER 32
74
75 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
76 struct rtl8xxxu_rx_urb *rx_urb);
77
78 static struct ieee80211_rate rtl8xxxu_rates[] = {
79 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
80 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
81 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
82 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
83 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
84 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
85 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
86 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
87 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
88 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
89 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
90 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
91 };
92
93 static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
94 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412,
95 .hw_value = 1, .max_power = 30 },
96 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417,
97 .hw_value = 2, .max_power = 30 },
98 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422,
99 .hw_value = 3, .max_power = 30 },
100 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427,
101 .hw_value = 4, .max_power = 30 },
102 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432,
103 .hw_value = 5, .max_power = 30 },
104 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437,
105 .hw_value = 6, .max_power = 30 },
106 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442,
107 .hw_value = 7, .max_power = 30 },
108 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447,
109 .hw_value = 8, .max_power = 30 },
110 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452,
111 .hw_value = 9, .max_power = 30 },
112 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457,
113 .hw_value = 10, .max_power = 30 },
114 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462,
115 .hw_value = 11, .max_power = 30 },
116 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467,
117 .hw_value = 12, .max_power = 30 },
118 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472,
119 .hw_value = 13, .max_power = 30 },
120 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484,
121 .hw_value = 14, .max_power = 30 }
122 };
123
124 static struct ieee80211_supported_band rtl8xxxu_supported_band = {
125 .channels = rtl8xxxu_channels_2g,
126 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
127 .bitrates = rtl8xxxu_rates,
128 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
129 };
130
131 static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = {
132 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
133 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
134 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
135 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
136 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
137 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
138 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
139 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
140 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
141 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
142 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
143 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
144 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
145 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
146 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
147 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
148 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
149 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
150 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
151 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
152 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
153 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
154 };
155
156 static struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = {
157 {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0},
158 {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10},
159 {0x430, 0x00}, {0x431, 0x00},
160 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
161 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
162 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
163 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
164 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
165 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
166 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
167 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
168 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
169 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
170 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
171 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
172 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
173 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
174 {0x516, 0x0a}, {0x525, 0x4f},
175 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50},
176 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
177 {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff},
178 {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff},
179 {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
180 {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00},
181 {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
182 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
183 {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04},
184 {0xffff, 0xff},
185 };
186
187 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
188 {0x800, 0x80040000}, {0x804, 0x00000003},
189 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
190 {0x810, 0x10001331}, {0x814, 0x020c3d10},
191 {0x818, 0x02200385}, {0x81c, 0x00000000},
192 {0x820, 0x01000100}, {0x824, 0x00390004},
193 {0x828, 0x00000000}, {0x82c, 0x00000000},
194 {0x830, 0x00000000}, {0x834, 0x00000000},
195 {0x838, 0x00000000}, {0x83c, 0x00000000},
196 {0x840, 0x00010000}, {0x844, 0x00000000},
197 {0x848, 0x00000000}, {0x84c, 0x00000000},
198 {0x850, 0x00000000}, {0x854, 0x00000000},
199 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
200 {0x860, 0x66f60110}, {0x864, 0x061f0130},
201 {0x868, 0x00000000}, {0x86c, 0x32323200},
202 {0x870, 0x07000760}, {0x874, 0x22004000},
203 {0x878, 0x00000808}, {0x87c, 0x00000000},
204 {0x880, 0xc0083070}, {0x884, 0x000004d5},
205 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
206 {0x890, 0x00000800}, {0x894, 0xfffffffe},
207 {0x898, 0x40302010}, {0x89c, 0x00706050},
208 {0x900, 0x00000000}, {0x904, 0x00000023},
209 {0x908, 0x00000000}, {0x90c, 0x81121111},
210 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
211 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
212 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
213 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
214 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
215 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
216 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
217 {0xa78, 0x00000900},
218 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
219 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
220 {0xc10, 0x08800000}, {0xc14, 0x40000100},
221 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
222 {0xc20, 0x00000000}, {0xc24, 0x00000000},
223 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
224 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
225 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
226 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
227 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
228 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
229 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
230 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
231 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
232 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
233 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
234 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
235 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
236 {0xc90, 0x00121820}, {0xc94, 0x00000000},
237 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
238 {0xca0, 0x00000000}, {0xca4, 0x00000080},
239 {0xca8, 0x00000000}, {0xcac, 0x00000000},
240 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
241 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
242 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
243 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
244 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
245 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
246 {0xce0, 0x00222222}, {0xce4, 0x00000000},
247 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
248 {0xd00, 0x00080740}, {0xd04, 0x00020401},
249 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
250 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
251 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
252 {0xd30, 0x00000000}, {0xd34, 0x80608000},
253 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
254 {0xd40, 0x00000000}, {0xd44, 0x00000000},
255 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
256 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
257 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
258 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
259 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
260 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
261 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
262 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
263 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
264 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
265 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
266 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
267 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
268 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
269 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
270 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
271 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
272 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
273 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
274 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
275 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
276 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
277 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
278 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
279 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
280 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
281 {0xf00, 0x00000300},
282 {0xffff, 0xffffffff},
283 };
284
285 static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = {
286 {0x800, 0x80040000}, {0x804, 0x00000003},
287 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
288 {0x810, 0x10001331}, {0x814, 0x020c3d10},
289 {0x818, 0x02200385}, {0x81c, 0x00000000},
290 {0x820, 0x01000100}, {0x824, 0x00190204},
291 {0x828, 0x00000000}, {0x82c, 0x00000000},
292 {0x830, 0x00000000}, {0x834, 0x00000000},
293 {0x838, 0x00000000}, {0x83c, 0x00000000},
294 {0x840, 0x00010000}, {0x844, 0x00000000},
295 {0x848, 0x00000000}, {0x84c, 0x00000000},
296 {0x850, 0x00000000}, {0x854, 0x00000000},
297 {0x858, 0x569a11a9}, {0x85c, 0x01000014},
298 {0x860, 0x66f60110}, {0x864, 0x061f0649},
299 {0x868, 0x00000000}, {0x86c, 0x27272700},
300 {0x870, 0x07000760}, {0x874, 0x25004000},
301 {0x878, 0x00000808}, {0x87c, 0x00000000},
302 {0x880, 0xb0000c1c}, {0x884, 0x00000001},
303 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
304 {0x890, 0x00000800}, {0x894, 0xfffffffe},
305 {0x898, 0x40302010}, {0x89c, 0x00706050},
306 {0x900, 0x00000000}, {0x904, 0x00000023},
307 {0x908, 0x00000000}, {0x90c, 0x81121111},
308 {0x910, 0x00000002}, {0x914, 0x00000201},
309 {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},
310 {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},
311 {0xa10, 0x9500bb78}, {0xa14, 0x1114d028},
312 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
313 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
314 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
315 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
316 {0xa78, 0x00000900}, {0xa7c, 0x225b0606},
317 {0xa80, 0x21806490}, {0xb2c, 0x00000000},
318 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
319 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
320 {0xc10, 0x08800000}, {0xc14, 0x40000100},
321 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
322 {0xc20, 0x00000000}, {0xc24, 0x00000000},
323 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
324 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
325 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
326 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
327 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
328 {0xc50, 0x69553420}, {0xc54, 0x43bc0094},
329 {0xc58, 0x00013149}, {0xc5c, 0x00250492},
330 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
331 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
332 {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},
333 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
334 {0xc80, 0x390000e4}, {0xc84, 0x20f60000},
335 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
336 {0xc90, 0x00020e1a}, {0xc94, 0x00000000},
337 {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f},
338 {0xca0, 0x00000000}, {0xca4, 0x000300a0},
339 {0xca8, 0x00000000}, {0xcac, 0x00000000},
340 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
341 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
342 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
343 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
344 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
345 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
346 {0xce0, 0x00222222}, {0xce4, 0x00000000},
347 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
348 {0xd00, 0x00000740}, {0xd04, 0x40020401},
349 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
350 {0xd10, 0xa0633333}, {0xd14, 0x3333bc53},
351 {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},
352 {0xd30, 0x00000000}, {0xd34, 0x80608000},
353 {0xd38, 0x00000000}, {0xd3c, 0x00127353},
354 {0xd40, 0x00000000}, {0xd44, 0x00000000},
355 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
356 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
357 {0xd58, 0x00000282}, {0xd5c, 0x30032064},
358 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
359 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
360 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
361 {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},
362 {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},
363 {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},
364 {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},
365 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
366 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
367 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
368 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
369 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
370 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
371 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
372 {0xe68, 0x001b2556}, {0xe6c, 0x00c00096},
373 {0xe70, 0x00c00096}, {0xe74, 0x01000056},
374 {0xe78, 0x01000014}, {0xe7c, 0x01000056},
375 {0xe80, 0x01000014}, {0xe84, 0x00c00096},
376 {0xe88, 0x01000056}, {0xe8c, 0x00c00096},
377 {0xed0, 0x00c00096}, {0xed4, 0x00c00096},
378 {0xed8, 0x00c00096}, {0xedc, 0x000000d6},
379 {0xee0, 0x000000d6}, {0xeec, 0x01c00016},
380 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
381 {0xf00, 0x00000300},
382 {0x820, 0x01000100}, {0x800, 0x83040000},
383 {0xffff, 0xffffffff},
384 };
385
386 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
387 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
388 {0x800, 0x80040002}, {0x804, 0x00000003},
389 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
390 {0x810, 0x10000330}, {0x814, 0x020c3d10},
391 {0x818, 0x02200385}, {0x81c, 0x00000000},
392 {0x820, 0x01000100}, {0x824, 0x00390004},
393 {0x828, 0x01000100}, {0x82c, 0x00390004},
394 {0x830, 0x27272727}, {0x834, 0x27272727},
395 {0x838, 0x27272727}, {0x83c, 0x27272727},
396 {0x840, 0x00010000}, {0x844, 0x00010000},
397 {0x848, 0x27272727}, {0x84c, 0x27272727},
398 {0x850, 0x00000000}, {0x854, 0x00000000},
399 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
400 {0x860, 0x66e60230}, {0x864, 0x061f0130},
401 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
402 {0x870, 0x07000700}, {0x874, 0x22184000},
403 {0x878, 0x08080808}, {0x87c, 0x00000000},
404 {0x880, 0xc0083070}, {0x884, 0x000004d5},
405 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
406 {0x890, 0x00000800}, {0x894, 0xfffffffe},
407 {0x898, 0x40302010}, {0x89c, 0x00706050},
408 {0x900, 0x00000000}, {0x904, 0x00000023},
409 {0x908, 0x00000000}, {0x90c, 0x81121313},
410 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
411 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
412 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
413 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
414 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
415 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
416 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
417 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
418 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
419 {0xc10, 0x08800000}, {0xc14, 0x40000100},
420 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
421 {0xc20, 0x00000000}, {0xc24, 0x00000000},
422 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
423 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
424 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
425 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
426 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
427 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
428 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
429 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
430 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
431 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
432 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
433 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
434 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
435 {0xc90, 0x00121820}, {0xc94, 0x00000000},
436 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
437 {0xca0, 0x00000000}, {0xca4, 0x00000080},
438 {0xca8, 0x00000000}, {0xcac, 0x00000000},
439 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
440 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
441 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
442 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
443 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
444 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
445 {0xce0, 0x00222222}, {0xce4, 0x00000000},
446 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
447 {0xd00, 0x00080740}, {0xd04, 0x00020403},
448 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
449 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
450 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
451 {0xd30, 0x00000000}, {0xd34, 0x80608000},
452 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
453 {0xd40, 0x00000000}, {0xd44, 0x00000000},
454 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
455 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
456 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
457 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
458 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
459 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
460 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
461 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
462 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
463 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
464 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
465 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
466 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
467 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
468 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
469 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
470 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
471 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
472 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
473 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
474 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
475 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
476 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
477 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
478 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
479 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
480 {0xf00, 0x00000300},
481 {0xffff, 0xffffffff},
482 };
483
484 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
485 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
486 {0x040, 0x000c0004}, {0x800, 0x80040000},
487 {0x804, 0x00000001}, {0x808, 0x0000fc00},
488 {0x80c, 0x0000000a}, {0x810, 0x10005388},
489 {0x814, 0x020c3d10}, {0x818, 0x02200385},
490 {0x81c, 0x00000000}, {0x820, 0x01000100},
491 {0x824, 0x00390204}, {0x828, 0x00000000},
492 {0x82c, 0x00000000}, {0x830, 0x00000000},
493 {0x834, 0x00000000}, {0x838, 0x00000000},
494 {0x83c, 0x00000000}, {0x840, 0x00010000},
495 {0x844, 0x00000000}, {0x848, 0x00000000},
496 {0x84c, 0x00000000}, {0x850, 0x00000000},
497 {0x854, 0x00000000}, {0x858, 0x569a569a},
498 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
499 {0x864, 0x061f0130}, {0x868, 0x00000000},
500 {0x86c, 0x20202000}, {0x870, 0x03000300},
501 {0x874, 0x22004000}, {0x878, 0x00000808},
502 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
503 {0x884, 0x000004d5}, {0x888, 0x00000000},
504 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
505 {0x894, 0xfffffffe}, {0x898, 0x40302010},
506 {0x89c, 0x00706050}, {0x900, 0x00000000},
507 {0x904, 0x00000023}, {0x908, 0x00000000},
508 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
509 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
510 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
511 {0xa14, 0x11144028}, {0xa18, 0x00881117},
512 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
513 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
514 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
515 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
516 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
517 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
518 {0xc14, 0x40000100}, {0xc18, 0x08800000},
519 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
520 {0xc24, 0x00000000}, {0xc28, 0x00000000},
521 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
522 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
523 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
524 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
525 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
526 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
527 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
528 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
529 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
530 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
531 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
532 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
533 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
534 {0xc94, 0x00000000}, {0xc98, 0x00121820},
535 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
536 {0xca4, 0x00000080}, {0xca8, 0x00000000},
537 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
538 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
539 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
540 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
541 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
542 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
543 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
544 {0xce4, 0x00000000}, {0xce8, 0x37644302},
545 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
546 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
547 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
548 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
549 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
550 {0xd34, 0x80608000}, {0xd38, 0x00000000},
551 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
552 {0xd44, 0x00000000}, {0xd48, 0x00000000},
553 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
554 {0xd54, 0x00000000}, {0xd58, 0x00000000},
555 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
556 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
557 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
558 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
559 {0xe00, 0x24242424}, {0xe04, 0x24242424},
560 {0xe08, 0x03902024}, {0xe10, 0x24242424},
561 {0xe14, 0x24242424}, {0xe18, 0x24242424},
562 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
563 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
564 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
565 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
566 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
567 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
568 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
569 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
570 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
571 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
572 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
573 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
574 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
575 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
576 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
577 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
578 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
579 {0xf00, 0x00000300},
580 {0xffff, 0xffffffff},
581 };
582
583 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
584 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
585 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
586 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
587 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
588 {0xc78, 0x78080001}, {0xc78, 0x77090001},
589 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
590 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
591 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
592 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
593 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
594 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
595 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
596 {0xc78, 0x68180001}, {0xc78, 0x67190001},
597 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
598 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
599 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
600 {0xc78, 0x60200001}, {0xc78, 0x49210001},
601 {0xc78, 0x48220001}, {0xc78, 0x47230001},
602 {0xc78, 0x46240001}, {0xc78, 0x45250001},
603 {0xc78, 0x44260001}, {0xc78, 0x43270001},
604 {0xc78, 0x42280001}, {0xc78, 0x41290001},
605 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
606 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
607 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
608 {0xc78, 0x21300001}, {0xc78, 0x20310001},
609 {0xc78, 0x06320001}, {0xc78, 0x05330001},
610 {0xc78, 0x04340001}, {0xc78, 0x03350001},
611 {0xc78, 0x02360001}, {0xc78, 0x01370001},
612 {0xc78, 0x00380001}, {0xc78, 0x00390001},
613 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
614 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
615 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
616 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
617 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
618 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
619 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
620 {0xc78, 0x78480001}, {0xc78, 0x77490001},
621 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
622 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
623 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
624 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
625 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
626 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
627 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
628 {0xc78, 0x68580001}, {0xc78, 0x67590001},
629 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
630 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
631 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
632 {0xc78, 0x60600001}, {0xc78, 0x49610001},
633 {0xc78, 0x48620001}, {0xc78, 0x47630001},
634 {0xc78, 0x46640001}, {0xc78, 0x45650001},
635 {0xc78, 0x44660001}, {0xc78, 0x43670001},
636 {0xc78, 0x42680001}, {0xc78, 0x41690001},
637 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
638 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
639 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
640 {0xc78, 0x21700001}, {0xc78, 0x20710001},
641 {0xc78, 0x06720001}, {0xc78, 0x05730001},
642 {0xc78, 0x04740001}, {0xc78, 0x03750001},
643 {0xc78, 0x02760001}, {0xc78, 0x01770001},
644 {0xc78, 0x00780001}, {0xc78, 0x00790001},
645 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
646 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
647 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
648 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
649 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
650 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
651 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
652 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
653 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
654 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
655 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
656 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
657 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
658 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
659 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
660 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
661 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
662 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
663 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
664 {0xffff, 0xffffffff}
665 };
666
667 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
668 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
669 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
670 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
671 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
672 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
673 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
674 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
675 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
676 {0xc78, 0x73100001}, {0xc78, 0x72110001},
677 {0xc78, 0x71120001}, {0xc78, 0x70130001},
678 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
679 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
680 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
681 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
682 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
683 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
684 {0xc78, 0x63200001}, {0xc78, 0x62210001},
685 {0xc78, 0x61220001}, {0xc78, 0x60230001},
686 {0xc78, 0x46240001}, {0xc78, 0x45250001},
687 {0xc78, 0x44260001}, {0xc78, 0x43270001},
688 {0xc78, 0x42280001}, {0xc78, 0x41290001},
689 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
690 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
691 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
692 {0xc78, 0x21300001}, {0xc78, 0x20310001},
693 {0xc78, 0x06320001}, {0xc78, 0x05330001},
694 {0xc78, 0x04340001}, {0xc78, 0x03350001},
695 {0xc78, 0x02360001}, {0xc78, 0x01370001},
696 {0xc78, 0x00380001}, {0xc78, 0x00390001},
697 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
698 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
699 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
700 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
701 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
702 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
703 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
704 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
705 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
706 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
707 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
708 {0xc78, 0x73500001}, {0xc78, 0x72510001},
709 {0xc78, 0x71520001}, {0xc78, 0x70530001},
710 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
711 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
712 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
713 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
714 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
715 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
716 {0xc78, 0x63600001}, {0xc78, 0x62610001},
717 {0xc78, 0x61620001}, {0xc78, 0x60630001},
718 {0xc78, 0x46640001}, {0xc78, 0x45650001},
719 {0xc78, 0x44660001}, {0xc78, 0x43670001},
720 {0xc78, 0x42680001}, {0xc78, 0x41690001},
721 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
722 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
723 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
724 {0xc78, 0x21700001}, {0xc78, 0x20710001},
725 {0xc78, 0x06720001}, {0xc78, 0x05730001},
726 {0xc78, 0x04740001}, {0xc78, 0x03750001},
727 {0xc78, 0x02760001}, {0xc78, 0x01770001},
728 {0xc78, 0x00780001}, {0xc78, 0x00790001},
729 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
730 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
731 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
732 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
733 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
734 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
735 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
736 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
737 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
738 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
739 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
740 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
741 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
742 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
743 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
744 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
745 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
746 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
747 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
748 {0xffff, 0xffffffff}
749 };
750
751 static struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = {
752 {0xc78, 0xfd000001}, {0xc78, 0xfc010001},
753 {0xc78, 0xfb020001}, {0xc78, 0xfa030001},
754 {0xc78, 0xf9040001}, {0xc78, 0xf8050001},
755 {0xc78, 0xf7060001}, {0xc78, 0xf6070001},
756 {0xc78, 0xf5080001}, {0xc78, 0xf4090001},
757 {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001},
758 {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001},
759 {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001},
760 {0xc78, 0xed100001}, {0xc78, 0xec110001},
761 {0xc78, 0xeb120001}, {0xc78, 0xea130001},
762 {0xc78, 0xe9140001}, {0xc78, 0xe8150001},
763 {0xc78, 0xe7160001}, {0xc78, 0xe6170001},
764 {0xc78, 0xe5180001}, {0xc78, 0xe4190001},
765 {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001},
766 {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001},
767 {0xc78, 0x671e0001}, {0xc78, 0x661f0001},
768 {0xc78, 0x65200001}, {0xc78, 0x64210001},
769 {0xc78, 0x63220001}, {0xc78, 0x4a230001},
770 {0xc78, 0x49240001}, {0xc78, 0x48250001},
771 {0xc78, 0x47260001}, {0xc78, 0x46270001},
772 {0xc78, 0x45280001}, {0xc78, 0x44290001},
773 {0xc78, 0x432a0001}, {0xc78, 0x422b0001},
774 {0xc78, 0x292c0001}, {0xc78, 0x282d0001},
775 {0xc78, 0x272e0001}, {0xc78, 0x262f0001},
776 {0xc78, 0x0a300001}, {0xc78, 0x09310001},
777 {0xc78, 0x08320001}, {0xc78, 0x07330001},
778 {0xc78, 0x06340001}, {0xc78, 0x05350001},
779 {0xc78, 0x04360001}, {0xc78, 0x03370001},
780 {0xc78, 0x02380001}, {0xc78, 0x01390001},
781 {0xc78, 0x013a0001}, {0xc78, 0x013b0001},
782 {0xc78, 0x013c0001}, {0xc78, 0x013d0001},
783 {0xc78, 0x013e0001}, {0xc78, 0x013f0001},
784 {0xc78, 0xfc400001}, {0xc78, 0xfb410001},
785 {0xc78, 0xfa420001}, {0xc78, 0xf9430001},
786 {0xc78, 0xf8440001}, {0xc78, 0xf7450001},
787 {0xc78, 0xf6460001}, {0xc78, 0xf5470001},
788 {0xc78, 0xf4480001}, {0xc78, 0xf3490001},
789 {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001},
790 {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001},
791 {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001},
792 {0xc78, 0xec500001}, {0xc78, 0xeb510001},
793 {0xc78, 0xea520001}, {0xc78, 0xe9530001},
794 {0xc78, 0xe8540001}, {0xc78, 0xe7550001},
795 {0xc78, 0xe6560001}, {0xc78, 0xe5570001},
796 {0xc78, 0xe4580001}, {0xc78, 0xe3590001},
797 {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001},
798 {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001},
799 {0xc78, 0x675e0001}, {0xc78, 0x665f0001},
800 {0xc78, 0x65600001}, {0xc78, 0x64610001},
801 {0xc78, 0x63620001}, {0xc78, 0x62630001},
802 {0xc78, 0x61640001}, {0xc78, 0x48650001},
803 {0xc78, 0x47660001}, {0xc78, 0x46670001},
804 {0xc78, 0x45680001}, {0xc78, 0x44690001},
805 {0xc78, 0x436a0001}, {0xc78, 0x426b0001},
806 {0xc78, 0x286c0001}, {0xc78, 0x276d0001},
807 {0xc78, 0x266e0001}, {0xc78, 0x256f0001},
808 {0xc78, 0x24700001}, {0xc78, 0x09710001},
809 {0xc78, 0x08720001}, {0xc78, 0x07730001},
810 {0xc78, 0x06740001}, {0xc78, 0x05750001},
811 {0xc78, 0x04760001}, {0xc78, 0x03770001},
812 {0xc78, 0x02780001}, {0xc78, 0x01790001},
813 {0xc78, 0x017a0001}, {0xc78, 0x017b0001},
814 {0xc78, 0x017c0001}, {0xc78, 0x017d0001},
815 {0xc78, 0x017e0001}, {0xc78, 0x017f0001},
816 {0xc50, 0x69553422},
817 {0xc50, 0x69553420},
818 {0x824, 0x00390204},
819 {0xffff, 0xffffffff}
820 };
821
822 static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
823 {0x00, 0x00030159}, {0x01, 0x00031284},
824 {0x02, 0x00098000}, {0x03, 0x00039c63},
825 {0x04, 0x000210e7}, {0x09, 0x0002044f},
826 {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
827 {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
828 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
829 {0x19, 0x00000000}, {0x1a, 0x00030355},
830 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
831 {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
832 {0x1f, 0x00000000}, {0x20, 0x0000b614},
833 {0x21, 0x0006c000}, {0x22, 0x00000000},
834 {0x23, 0x00001558}, {0x24, 0x00000060},
835 {0x25, 0x00000483}, {0x26, 0x0004f000},
836 {0x27, 0x000ec7d9}, {0x28, 0x00057730},
837 {0x29, 0x00004783}, {0x2a, 0x00000001},
838 {0x2b, 0x00021334}, {0x2a, 0x00000000},
839 {0x2b, 0x00000054}, {0x2a, 0x00000001},
840 {0x2b, 0x00000808}, {0x2b, 0x00053333},
841 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
842 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
843 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
844 {0x2b, 0x00000808}, {0x2b, 0x00063333},
845 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
846 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
847 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
848 {0x2b, 0x00000808}, {0x2b, 0x00073333},
849 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
850 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
851 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
852 {0x2b, 0x00000709}, {0x2b, 0x00063333},
853 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
854 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
855 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
856 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
857 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
858 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
859 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
860 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
861 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
862 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
863 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
864 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
865 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
866 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
867 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
868 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
869 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
870 {0x10, 0x0002000f}, {0x11, 0x000203f9},
871 {0x10, 0x0003000f}, {0x11, 0x000ff500},
872 {0x10, 0x00000000}, {0x11, 0x00000000},
873 {0x10, 0x0008000f}, {0x11, 0x0003f100},
874 {0x10, 0x0009000f}, {0x11, 0x00023100},
875 {0x12, 0x00032000}, {0x12, 0x00071000},
876 {0x12, 0x000b0000}, {0x12, 0x000fc000},
877 {0x13, 0x000287b3}, {0x13, 0x000244b7},
878 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
879 {0x13, 0x00018493}, {0x13, 0x0001429b},
880 {0x13, 0x00010299}, {0x13, 0x0000c29c},
881 {0x13, 0x000081a0}, {0x13, 0x000040ac},
882 {0x13, 0x00000020}, {0x14, 0x0001944c},
883 {0x14, 0x00059444}, {0x14, 0x0009944c},
884 {0x14, 0x000d9444}, {0x15, 0x0000f474},
885 {0x15, 0x0004f477}, {0x15, 0x0008f455},
886 {0x15, 0x000cf455}, {0x16, 0x00000339},
887 {0x16, 0x00040339}, {0x16, 0x00080339},
888 {0x16, 0x000c0366}, {0x00, 0x00010159},
889 {0x18, 0x0000f401}, {0xfe, 0x00000000},
890 {0xfe, 0x00000000}, {0x1f, 0x00000003},
891 {0xfe, 0x00000000}, {0xfe, 0x00000000},
892 {0x1e, 0x00000247}, {0x1f, 0x00000000},
893 {0x00, 0x00030159},
894 {0xff, 0xffffffff}
895 };
896
897 static struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = {
898 {0x00, 0x00010000}, {0xb0, 0x000dffe0},
899 {0xfe, 0x00000000}, {0xfe, 0x00000000},
900 {0xfe, 0x00000000}, {0xb1, 0x00000018},
901 {0xfe, 0x00000000}, {0xfe, 0x00000000},
902 {0xfe, 0x00000000}, {0xb2, 0x00084c00},
903 {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa},
904 {0xb7, 0x00000010}, {0xb8, 0x0000907f},
905 {0x5c, 0x00000002}, {0x7c, 0x00000002},
906 {0x7e, 0x00000005}, {0x8b, 0x0006fc00},
907 {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2},
908 {0x1e, 0x00000000}, {0xdf, 0x00000780},
909 {0x50, 0x00067435},
910 /*
911 * The 8723bu vendor driver indicates that bit 8 should be set in
912 * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However
913 * they never actually check the package type - and just default
914 * to not setting it.
915 */
916 {0x51, 0x0006b04e},
917 {0x52, 0x000007d2}, {0x53, 0x00000000},
918 {0x54, 0x00050400}, {0x55, 0x0004026e},
919 {0xdd, 0x0000004c}, {0x70, 0x00067435},
920 /*
921 * 0x71 has same package type condition as for register 0x51
922 */
923 {0x71, 0x0006b04e},
924 {0x72, 0x000007d2}, {0x73, 0x00000000},
925 {0x74, 0x00050400}, {0x75, 0x0004026e},
926 {0xef, 0x00000100}, {0x34, 0x0000add7},
927 {0x35, 0x00005c00}, {0x34, 0x00009dd4},
928 {0x35, 0x00005000}, {0x34, 0x00008dd1},
929 {0x35, 0x00004400}, {0x34, 0x00007dce},
930 {0x35, 0x00003800}, {0x34, 0x00006cd1},
931 {0x35, 0x00004400}, {0x34, 0x00005cce},
932 {0x35, 0x00003800}, {0x34, 0x000048ce},
933 {0x35, 0x00004400}, {0x34, 0x000034ce},
934 {0x35, 0x00003800}, {0x34, 0x00002451},
935 {0x35, 0x00004400}, {0x34, 0x0000144e},
936 {0x35, 0x00003800}, {0x34, 0x00000051},
937 {0x35, 0x00004400}, {0xef, 0x00000000},
938 {0xef, 0x00000100}, {0xed, 0x00000010},
939 {0x44, 0x0000add7}, {0x44, 0x00009dd4},
940 {0x44, 0x00008dd1}, {0x44, 0x00007dce},
941 {0x44, 0x00006cc1}, {0x44, 0x00005cce},
942 {0x44, 0x000044d1}, {0x44, 0x000034ce},
943 {0x44, 0x00002451}, {0x44, 0x0000144e},
944 {0x44, 0x00000051}, {0xef, 0x00000000},
945 {0xed, 0x00000000}, {0x7f, 0x00020080},
946 {0xef, 0x00002000}, {0x3b, 0x000380ef},
947 {0x3b, 0x000302fe}, {0x3b, 0x00028ce6},
948 {0x3b, 0x000200bc}, {0x3b, 0x000188a5},
949 {0x3b, 0x00010fbc}, {0x3b, 0x00008f71},
950 {0x3b, 0x00000900}, {0xef, 0x00000000},
951 {0xed, 0x00000001}, {0x40, 0x000380ef},
952 {0x40, 0x000302fe}, {0x40, 0x00028ce6},
953 {0x40, 0x000200bc}, {0x40, 0x000188a5},
954 {0x40, 0x00010fbc}, {0x40, 0x00008f71},
955 {0x40, 0x00000900}, {0xed, 0x00000000},
956 {0x82, 0x00080000}, {0x83, 0x00008000},
957 {0x84, 0x00048d80}, {0x85, 0x00068000},
958 {0xa2, 0x00080000}, {0xa3, 0x00008000},
959 {0xa4, 0x00048d80}, {0xa5, 0x00068000},
960 {0xed, 0x00000002}, {0xef, 0x00000002},
961 {0x56, 0x00000032}, {0x76, 0x00000032},
962 {0x01, 0x00000780},
963 {0xff, 0xffffffff}
964 };
965
966 static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
967 {0x00, 0x00030159}, {0x01, 0x00031284},
968 {0x02, 0x00098000}, {0x03, 0x00018c63},
969 {0x04, 0x000210e7}, {0x09, 0x0002044f},
970 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
971 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
972 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
973 {0x19, 0x00000000}, {0x1a, 0x00010255},
974 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
975 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
976 {0x1f, 0x00080001}, {0x20, 0x0000b614},
977 {0x21, 0x0006c000}, {0x22, 0x00000000},
978 {0x23, 0x00001558}, {0x24, 0x00000060},
979 {0x25, 0x00000483}, {0x26, 0x0004f000},
980 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
981 {0x29, 0x00004783}, {0x2a, 0x00000001},
982 {0x2b, 0x00021334}, {0x2a, 0x00000000},
983 {0x2b, 0x00000054}, {0x2a, 0x00000001},
984 {0x2b, 0x00000808}, {0x2b, 0x00053333},
985 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
986 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
987 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
988 {0x2b, 0x00000808}, {0x2b, 0x00063333},
989 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
990 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
991 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
992 {0x2b, 0x00000808}, {0x2b, 0x00073333},
993 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
994 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
995 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
996 {0x2b, 0x00000709}, {0x2b, 0x00063333},
997 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
998 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
999 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1000 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1001 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1002 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1003 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1004 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1005 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1006 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1007 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1008 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1009 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1010 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1011 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1012 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1013 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1014 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1015 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1016 {0x10, 0x00000000}, {0x11, 0x00000000},
1017 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1018 {0x10, 0x0009000f}, {0x11, 0x00023100},
1019 {0x12, 0x00032000}, {0x12, 0x00071000},
1020 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1021 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1022 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1023 {0x13, 0x00018493}, {0x13, 0x0001429b},
1024 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1025 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1026 {0x13, 0x00000020}, {0x14, 0x0001944c},
1027 {0x14, 0x00059444}, {0x14, 0x0009944c},
1028 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1029 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1030 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1031 {0x16, 0x000a0330}, {0x16, 0x00060330},
1032 {0x16, 0x00020330}, {0x00, 0x00010159},
1033 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1034 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1035 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1036 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1037 {0x00, 0x00030159},
1038 {0xff, 0xffffffff}
1039 };
1040
1041 static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
1042 {0x00, 0x00030159}, {0x01, 0x00031284},
1043 {0x02, 0x00098000}, {0x03, 0x00018c63},
1044 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1045 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1046 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1047 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1048 {0x12, 0x00032000}, {0x12, 0x00071000},
1049 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1050 {0x13, 0x000287af}, {0x13, 0x000244b7},
1051 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1052 {0x13, 0x00018493}, {0x13, 0x00014297},
1053 {0x13, 0x00010295}, {0x13, 0x0000c298},
1054 {0x13, 0x0000819c}, {0x13, 0x000040a8},
1055 {0x13, 0x0000001c}, {0x14, 0x0001944c},
1056 {0x14, 0x00059444}, {0x14, 0x0009944c},
1057 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1058 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1059 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1060 {0x16, 0x000a0330}, {0x16, 0x00060330},
1061 {0x16, 0x00020330},
1062 {0xff, 0xffffffff}
1063 };
1064
1065 static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
1066 {0x00, 0x00030159}, {0x01, 0x00031284},
1067 {0x02, 0x00098000}, {0x03, 0x00018c63},
1068 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1069 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1070 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1071 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1072 {0x19, 0x00000000}, {0x1a, 0x00010255},
1073 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1074 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1075 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1076 {0x21, 0x0006c000}, {0x22, 0x00000000},
1077 {0x23, 0x00001558}, {0x24, 0x00000060},
1078 {0x25, 0x00000483}, {0x26, 0x0004f000},
1079 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1080 {0x29, 0x00004783}, {0x2a, 0x00000001},
1081 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1082 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1083 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1084 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1085 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1086 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1087 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1088 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1089 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1090 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1091 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1092 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1093 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1094 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1095 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1096 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1097 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1098 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1099 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1100 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1101 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1102 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1103 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1104 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1105 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1106 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1107 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1108 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1109 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1110 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1111 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1112 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1113 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1114 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1115 {0x10, 0x00000000}, {0x11, 0x00000000},
1116 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1117 {0x10, 0x0009000f}, {0x11, 0x00023100},
1118 {0x12, 0x00032000}, {0x12, 0x00071000},
1119 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1120 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1121 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1122 {0x13, 0x00018493}, {0x13, 0x0001429b},
1123 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1124 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1125 {0x13, 0x00000020}, {0x14, 0x0001944c},
1126 {0x14, 0x00059444}, {0x14, 0x0009944c},
1127 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1128 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1129 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1130 {0x16, 0x000a0330}, {0x16, 0x00060330},
1131 {0x16, 0x00020330}, {0x00, 0x00010159},
1132 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1133 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1134 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1135 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1136 {0x00, 0x00030159},
1137 {0xff, 0xffffffff}
1138 };
1139
1140 static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
1141 {0x00, 0x00030159}, {0x01, 0x00031284},
1142 {0x02, 0x00098000}, {0x03, 0x00018c63},
1143 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1144 {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
1145 {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
1146 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1147 {0x19, 0x00000000}, {0x1a, 0x00000255},
1148 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1149 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1150 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1151 {0x21, 0x0006c000}, {0x22, 0x0000083c},
1152 {0x23, 0x00001558}, {0x24, 0x00000060},
1153 {0x25, 0x00000483}, {0x26, 0x0004f000},
1154 {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
1155 {0x29, 0x00004783}, {0x2a, 0x00000001},
1156 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1157 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1158 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1159 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1160 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1161 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1162 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1163 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1164 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1165 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1166 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1167 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1168 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1169 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1170 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1171 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1172 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1173 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1174 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1175 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1176 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1177 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1178 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1179 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1180 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1181 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1182 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1183 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1184 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1185 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1186 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1187 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1188 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1189 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1190 {0x10, 0x00000000}, {0x11, 0x00000000},
1191 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1192 {0x10, 0x0009000f}, {0x11, 0x00023100},
1193 {0x12, 0x000d8000}, {0x12, 0x00090000},
1194 {0x12, 0x00051000}, {0x12, 0x00012000},
1195 {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
1196 {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
1197 {0x13, 0x000183a4}, {0x13, 0x00014398},
1198 {0x13, 0x000101a4}, {0x13, 0x0000c198},
1199 {0x13, 0x000080a4}, {0x13, 0x00004098},
1200 {0x13, 0x00000000}, {0x14, 0x0001944c},
1201 {0x14, 0x00059444}, {0x14, 0x0009944c},
1202 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1203 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1204 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1205 {0x16, 0x000a0330}, {0x16, 0x00060330},
1206 {0x16, 0x00020330}, {0x00, 0x00010159},
1207 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1208 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1209 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1210 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1211 {0x00, 0x00030159},
1212 {0xff, 0xffffffff}
1213 };
1214
1215 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
1216 { /* RF_A */
1217 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
1218 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
1219 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
1220 .hspiread = REG_HSPI_XA_READBACK,
1221 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
1222 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
1223 },
1224 { /* RF_B */
1225 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
1226 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
1227 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
1228 .hspiread = REG_HSPI_XB_READBACK,
1229 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
1230 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
1231 },
1232 };
1233
1234 static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
1235 REG_OFDM0_XA_RX_IQ_IMBALANCE,
1236 REG_OFDM0_XB_RX_IQ_IMBALANCE,
1237 REG_OFDM0_ENERGY_CCA_THRES,
1238 REG_OFDM0_AGCR_SSI_TABLE,
1239 REG_OFDM0_XA_TX_IQ_IMBALANCE,
1240 REG_OFDM0_XB_TX_IQ_IMBALANCE,
1241 REG_OFDM0_XC_TX_AFE,
1242 REG_OFDM0_XD_TX_AFE,
1243 REG_OFDM0_RX_IQ_EXT_ANTA
1244 };
1245
1246 static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
1247 {
1248 struct usb_device *udev = priv->udev;
1249 int len;
1250 u8 data;
1251
1252 mutex_lock(&priv->usb_buf_mutex);
1253 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1254 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1255 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1256 RTW_USB_CONTROL_MSG_TIMEOUT);
1257 data = priv->usb_buf.val8;
1258 mutex_unlock(&priv->usb_buf_mutex);
1259
1260 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1261 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n",
1262 __func__, addr, data, len);
1263 return data;
1264 }
1265
1266 static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
1267 {
1268 struct usb_device *udev = priv->udev;
1269 int len;
1270 u16 data;
1271
1272 mutex_lock(&priv->usb_buf_mutex);
1273 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1274 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1275 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1276 RTW_USB_CONTROL_MSG_TIMEOUT);
1277 data = le16_to_cpu(priv->usb_buf.val16);
1278 mutex_unlock(&priv->usb_buf_mutex);
1279
1280 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1281 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n",
1282 __func__, addr, data, len);
1283 return data;
1284 }
1285
1286 static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
1287 {
1288 struct usb_device *udev = priv->udev;
1289 int len;
1290 u32 data;
1291
1292 mutex_lock(&priv->usb_buf_mutex);
1293 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1294 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1295 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1296 RTW_USB_CONTROL_MSG_TIMEOUT);
1297 data = le32_to_cpu(priv->usb_buf.val32);
1298 mutex_unlock(&priv->usb_buf_mutex);
1299
1300 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1301 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n",
1302 __func__, addr, data, len);
1303 return data;
1304 }
1305
1306 static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
1307 {
1308 struct usb_device *udev = priv->udev;
1309 int ret;
1310
1311 mutex_lock(&priv->usb_buf_mutex);
1312 priv->usb_buf.val8 = val;
1313 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1314 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1315 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1316 RTW_USB_CONTROL_MSG_TIMEOUT);
1317
1318 mutex_unlock(&priv->usb_buf_mutex);
1319
1320 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1321 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1322 __func__, addr, val);
1323 return ret;
1324 }
1325
1326 static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
1327 {
1328 struct usb_device *udev = priv->udev;
1329 int ret;
1330
1331 mutex_lock(&priv->usb_buf_mutex);
1332 priv->usb_buf.val16 = cpu_to_le16(val);
1333 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1334 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1335 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1336 RTW_USB_CONTROL_MSG_TIMEOUT);
1337 mutex_unlock(&priv->usb_buf_mutex);
1338
1339 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1340 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1341 __func__, addr, val);
1342 return ret;
1343 }
1344
1345 static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
1346 {
1347 struct usb_device *udev = priv->udev;
1348 int ret;
1349
1350 mutex_lock(&priv->usb_buf_mutex);
1351 priv->usb_buf.val32 = cpu_to_le32(val);
1352 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1353 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1354 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1355 RTW_USB_CONTROL_MSG_TIMEOUT);
1356 mutex_unlock(&priv->usb_buf_mutex);
1357
1358 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1359 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1360 __func__, addr, val);
1361 return ret;
1362 }
1363
1364 static int
1365 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1366 {
1367 struct usb_device *udev = priv->udev;
1368 int blocksize = priv->fops->writeN_block_size;
1369 int ret, i, count, remainder;
1370
1371 count = len / blocksize;
1372 remainder = len % blocksize;
1373
1374 for (i = 0; i < count; i++) {
1375 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1376 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1377 addr, 0, buf, blocksize,
1378 RTW_USB_CONTROL_MSG_TIMEOUT);
1379 if (ret != blocksize)
1380 goto write_error;
1381
1382 addr += blocksize;
1383 buf += blocksize;
1384 }
1385
1386 if (remainder) {
1387 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1388 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1389 addr, 0, buf, remainder,
1390 RTW_USB_CONTROL_MSG_TIMEOUT);
1391 if (ret != remainder)
1392 goto write_error;
1393 }
1394
1395 return len;
1396
1397 write_error:
1398 dev_info(&udev->dev,
1399 "%s: Failed to write block at addr: %04x size: %04x\n",
1400 __func__, addr, blocksize);
1401 return -EAGAIN;
1402 }
1403
1404 static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1405 enum rtl8xxxu_rfpath path, u8 reg)
1406 {
1407 u32 hssia, val32, retval;
1408
1409 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1410 if (path != RF_A)
1411 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1412 else
1413 val32 = hssia;
1414
1415 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1416 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1417 val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1418 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1419 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1420
1421 udelay(10);
1422
1423 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1424 udelay(100);
1425
1426 hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1427 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1428 udelay(10);
1429
1430 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1431 if (val32 & FPGA0_HSSI_PARM1_PI)
1432 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1433 else
1434 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1435
1436 retval &= 0xfffff;
1437
1438 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1439 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1440 __func__, reg, retval);
1441 return retval;
1442 }
1443
1444 /*
1445 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
1446 * have write issues in high temperature conditions. We may have to
1447 * retry writing them.
1448 */
1449 static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1450 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
1451 {
1452 int ret, retval;
1453 u32 dataaddr;
1454
1455 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1456 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1457 __func__, reg, data);
1458
1459 data &= FPGA0_LSSI_PARM_DATA_MASK;
1460 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1461
1462 /* Use XB for path B */
1463 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1464 if (ret != sizeof(dataaddr))
1465 retval = -EIO;
1466 else
1467 retval = 0;
1468
1469 udelay(1);
1470
1471 return retval;
1472 }
1473
1474 static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv,
1475 struct h2c_cmd *h2c, int len)
1476 {
1477 struct device *dev = &priv->udev->dev;
1478 int mbox_nr, retry, retval = 0;
1479 int mbox_reg, mbox_ext_reg;
1480 u8 val8;
1481
1482 mutex_lock(&priv->h2c_mutex);
1483
1484 mbox_nr = priv->next_mbox;
1485 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1486 mbox_ext_reg = priv->fops->mbox_ext_reg +
1487 (mbox_nr * priv->fops->mbox_ext_width);
1488
1489 /*
1490 * MBOX ready?
1491 */
1492 retry = 100;
1493 do {
1494 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1495 if (!(val8 & BIT(mbox_nr)))
1496 break;
1497 } while (retry--);
1498
1499 if (!retry) {
1500 dev_info(dev, "%s: Mailbox busy\n", __func__);
1501 retval = -EBUSY;
1502 goto error;
1503 }
1504
1505 /*
1506 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1507 */
1508 if (len > sizeof(u32)) {
1509 if (priv->fops->mbox_ext_width == 4) {
1510 rtl8xxxu_write32(priv, mbox_ext_reg,
1511 le32_to_cpu(h2c->raw_wide.ext));
1512 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1513 dev_info(dev, "H2C_EXT %08x\n",
1514 le32_to_cpu(h2c->raw_wide.ext));
1515 } else {
1516 rtl8xxxu_write16(priv, mbox_ext_reg,
1517 le16_to_cpu(h2c->raw.ext));
1518 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1519 dev_info(dev, "H2C_EXT %04x\n",
1520 le16_to_cpu(h2c->raw.ext));
1521 }
1522 }
1523 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1524 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1525 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1526
1527 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1528
1529 error:
1530 mutex_unlock(&priv->h2c_mutex);
1531 return retval;
1532 }
1533
1534 static void rtl8723bu_write_btreg(struct rtl8xxxu_priv *priv, u8 reg, u8 data)
1535 {
1536 struct h2c_cmd h2c;
1537 int reqnum = 0;
1538
1539 memset(&h2c, 0, sizeof(struct h2c_cmd));
1540 h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
1541 h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
1542 h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
1543 h2c.bt_mp_oper.data = data;
1544 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
1545
1546 reqnum++;
1547 memset(&h2c, 0, sizeof(struct h2c_cmd));
1548 h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
1549 h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
1550 h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
1551 h2c.bt_mp_oper.addr = reg;
1552 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
1553 }
1554
1555 static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv)
1556 {
1557 u8 val8;
1558 u32 val32;
1559
1560 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1561 val8 |= BIT(0) | BIT(3);
1562 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1563
1564 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1565 val32 &= ~(BIT(4) | BIT(5));
1566 val32 |= BIT(3);
1567 if (priv->rf_paths == 2) {
1568 val32 &= ~(BIT(20) | BIT(21));
1569 val32 |= BIT(19);
1570 }
1571 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1572
1573 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1574 val32 &= ~OFDM_RF_PATH_TX_MASK;
1575 if (priv->tx_paths == 2)
1576 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1577 else if (priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c)
1578 val32 |= OFDM_RF_PATH_TX_B;
1579 else
1580 val32 |= OFDM_RF_PATH_TX_A;
1581 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1582
1583 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1584 val32 &= ~FPGA_RF_MODE_JAPAN;
1585 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1586
1587 if (priv->rf_paths == 2)
1588 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1589 else
1590 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1591
1592 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1593 if (priv->rf_paths == 2)
1594 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1595
1596 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1597 }
1598
1599 static void rtl8723b_enable_rf(struct rtl8xxxu_priv *priv)
1600 {
1601 }
1602
1603 static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv)
1604 {
1605 u8 sps0;
1606 u32 val32;
1607
1608 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1609
1610 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1611
1612 /* RF RX code for preamble power saving */
1613 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1614 val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1615 if (priv->rf_paths == 2)
1616 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1617 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1618
1619 /* Disable TX for four paths */
1620 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1621 val32 &= ~OFDM_RF_PATH_TX_MASK;
1622 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1623
1624 /* Enable power saving */
1625 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1626 val32 |= FPGA_RF_MODE_JAPAN;
1627 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1628
1629 /* AFE control register to power down bits [30:22] */
1630 if (priv->rf_paths == 2)
1631 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1632 else
1633 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1634
1635 /* Power down RF module */
1636 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1637 if (priv->rf_paths == 2)
1638 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1639
1640 sps0 &= ~(BIT(0) | BIT(3));
1641 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1642 }
1643
1644
1645 static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1646 {
1647 u8 val8;
1648
1649 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1650 val8 &= ~BIT(6);
1651 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1652
1653 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1654 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1655 val8 &= ~BIT(0);
1656 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1657 }
1658
1659
1660 /*
1661 * The rtl8723a has 3 channel groups for it's efuse settings. It only
1662 * supports the 2.4GHz band, so channels 1 - 14:
1663 * group 0: channels 1 - 3
1664 * group 1: channels 4 - 9
1665 * group 2: channels 10 - 14
1666 *
1667 * Note: We index from 0 in the code
1668 */
1669 static int rtl8723a_channel_to_group(int channel)
1670 {
1671 int group;
1672
1673 if (channel < 4)
1674 group = 0;
1675 else if (channel < 10)
1676 group = 1;
1677 else
1678 group = 2;
1679
1680 return group;
1681 }
1682
1683 static int rtl8723b_channel_to_group(int channel)
1684 {
1685 int group;
1686
1687 if (channel < 3)
1688 group = 0;
1689 else if (channel < 6)
1690 group = 1;
1691 else if (channel < 9)
1692 group = 2;
1693 else if (channel < 12)
1694 group = 3;
1695 else
1696 group = 4;
1697
1698 return group;
1699 }
1700
1701 static void rtl8723au_config_channel(struct ieee80211_hw *hw)
1702 {
1703 struct rtl8xxxu_priv *priv = hw->priv;
1704 u32 val32, rsr;
1705 u8 val8, opmode;
1706 bool ht = true;
1707 int sec_ch_above, channel;
1708 int i;
1709
1710 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1711 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1712 channel = hw->conf.chandef.chan->hw_value;
1713
1714 switch (hw->conf.chandef.width) {
1715 case NL80211_CHAN_WIDTH_20_NOHT:
1716 ht = false;
1717 case NL80211_CHAN_WIDTH_20:
1718 opmode |= BW_OPMODE_20MHZ;
1719 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1720
1721 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1722 val32 &= ~FPGA_RF_MODE;
1723 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1724
1725 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1726 val32 &= ~FPGA_RF_MODE;
1727 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1728
1729 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1730 val32 |= FPGA0_ANALOG2_20MHZ;
1731 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1732 break;
1733 case NL80211_CHAN_WIDTH_40:
1734 if (hw->conf.chandef.center_freq1 >
1735 hw->conf.chandef.chan->center_freq) {
1736 sec_ch_above = 1;
1737 channel += 2;
1738 } else {
1739 sec_ch_above = 0;
1740 channel -= 2;
1741 }
1742
1743 opmode &= ~BW_OPMODE_20MHZ;
1744 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1745 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1746 if (sec_ch_above)
1747 rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1748 else
1749 rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1750 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1751
1752 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1753 val32 |= FPGA_RF_MODE;
1754 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1755
1756 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1757 val32 |= FPGA_RF_MODE;
1758 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1759
1760 /*
1761 * Set Control channel to upper or lower. These settings
1762 * are required only for 40MHz
1763 */
1764 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1765 val32 &= ~CCK0_SIDEBAND;
1766 if (!sec_ch_above)
1767 val32 |= CCK0_SIDEBAND;
1768 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1769
1770 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1771 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1772 if (sec_ch_above)
1773 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1774 else
1775 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1776 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1777
1778 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1779 val32 &= ~FPGA0_ANALOG2_20MHZ;
1780 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1781
1782 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1783 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1784 if (sec_ch_above)
1785 val32 |= FPGA0_PS_UPPER_CHANNEL;
1786 else
1787 val32 |= FPGA0_PS_LOWER_CHANNEL;
1788 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1789 break;
1790
1791 default:
1792 break;
1793 }
1794
1795 for (i = RF_A; i < priv->rf_paths; i++) {
1796 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1797 val32 &= ~MODE_AG_CHANNEL_MASK;
1798 val32 |= channel;
1799 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1800 }
1801
1802 if (ht)
1803 val8 = 0x0e;
1804 else
1805 val8 = 0x0a;
1806
1807 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1808 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1809
1810 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1811 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1812
1813 for (i = RF_A; i < priv->rf_paths; i++) {
1814 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1815 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1816 val32 &= ~MODE_AG_CHANNEL_20MHZ;
1817 else
1818 val32 |= MODE_AG_CHANNEL_20MHZ;
1819 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1820 }
1821 }
1822
1823 static void rtl8723bu_config_channel(struct ieee80211_hw *hw)
1824 {
1825 struct rtl8xxxu_priv *priv = hw->priv;
1826 u32 val32, rsr;
1827 u8 val8, subchannel;
1828 u16 rf_mode_bw;
1829 bool ht = true;
1830 int sec_ch_above, channel;
1831 int i;
1832
1833 rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL);
1834 rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK;
1835 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1836 channel = hw->conf.chandef.chan->hw_value;
1837
1838 /* Hack */
1839 subchannel = 0;
1840
1841 switch (hw->conf.chandef.width) {
1842 case NL80211_CHAN_WIDTH_20_NOHT:
1843 ht = false;
1844 case NL80211_CHAN_WIDTH_20:
1845 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20;
1846 subchannel = 0;
1847
1848 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1849 val32 &= ~FPGA_RF_MODE;
1850 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1851
1852 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1853 val32 &= ~FPGA_RF_MODE;
1854 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1855
1856 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
1857 val32 &= ~(BIT(30) | BIT(31));
1858 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);
1859
1860 break;
1861 case NL80211_CHAN_WIDTH_40:
1862 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40;
1863
1864 if (hw->conf.chandef.center_freq1 >
1865 hw->conf.chandef.chan->center_freq) {
1866 sec_ch_above = 1;
1867 channel += 2;
1868 } else {
1869 sec_ch_above = 0;
1870 channel -= 2;
1871 }
1872
1873 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1874 val32 |= FPGA_RF_MODE;
1875 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1876
1877 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1878 val32 |= FPGA_RF_MODE;
1879 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1880
1881 /*
1882 * Set Control channel to upper or lower. These settings
1883 * are required only for 40MHz
1884 */
1885 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1886 val32 &= ~CCK0_SIDEBAND;
1887 if (!sec_ch_above)
1888 val32 |= CCK0_SIDEBAND;
1889 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1890
1891 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1892 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1893 if (sec_ch_above)
1894 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1895 else
1896 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1897 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1898
1899 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1900 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1901 if (sec_ch_above)
1902 val32 |= FPGA0_PS_UPPER_CHANNEL;
1903 else
1904 val32 |= FPGA0_PS_LOWER_CHANNEL;
1905 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1906 break;
1907 case NL80211_CHAN_WIDTH_80:
1908 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80;
1909 break;
1910 default:
1911 break;
1912 }
1913
1914 for (i = RF_A; i < priv->rf_paths; i++) {
1915 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1916 val32 &= ~MODE_AG_CHANNEL_MASK;
1917 val32 |= channel;
1918 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1919 }
1920
1921 rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw);
1922 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel);
1923
1924 if (ht)
1925 val8 = 0x0e;
1926 else
1927 val8 = 0x0a;
1928
1929 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1930 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1931
1932 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1933 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1934
1935 for (i = RF_A; i < priv->rf_paths; i++) {
1936 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1937 val32 &= ~MODE_AG_BW_MASK;
1938 switch(hw->conf.chandef.width) {
1939 case NL80211_CHAN_WIDTH_80:
1940 val32 |= MODE_AG_BW_80MHZ_8723B;
1941 break;
1942 case NL80211_CHAN_WIDTH_40:
1943 val32 |= MODE_AG_BW_40MHZ_8723B;
1944 break;
1945 default:
1946 val32 |= MODE_AG_BW_20MHZ_8723B;
1947 break;
1948 }
1949 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1950 }
1951 }
1952
1953 static void
1954 rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1955 {
1956 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1957 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1958 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1959 u8 val8;
1960 int group, i;
1961
1962 group = rtl8723a_channel_to_group(channel);
1963
1964 cck[0] = priv->cck_tx_power_index_A[group];
1965 cck[1] = priv->cck_tx_power_index_B[group];
1966
1967 ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1968 ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1969
1970 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1971 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1972
1973 mcsbase[0] = ofdm[0];
1974 mcsbase[1] = ofdm[1];
1975 if (!ht40) {
1976 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1977 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1978 }
1979
1980 if (priv->tx_paths > 1) {
1981 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1982 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a;
1983 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1984 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b;
1985 }
1986
1987 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1988 dev_info(&priv->udev->dev,
1989 "%s: Setting TX power CCK A: %02x, "
1990 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1991 __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1992
1993 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1994 if (cck[i] > RF6052_MAX_TX_PWR)
1995 cck[i] = RF6052_MAX_TX_PWR;
1996 if (ofdm[i] > RF6052_MAX_TX_PWR)
1997 ofdm[i] = RF6052_MAX_TX_PWR;
1998 }
1999
2000 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
2001 val32 &= 0xffff00ff;
2002 val32 |= (cck[0] << 8);
2003 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
2004
2005 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2006 val32 &= 0xff;
2007 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
2008 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2009
2010 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2011 val32 &= 0xffffff00;
2012 val32 |= cck[1];
2013 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2014
2015 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
2016 val32 &= 0xff;
2017 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
2018 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
2019
2020 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
2021 ofdmbase[0] << 16 | ofdmbase[0] << 24;
2022 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
2023 ofdmbase[1] << 16 | ofdmbase[1] << 24;
2024 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a);
2025 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b);
2026
2027 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a);
2028 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b);
2029
2030 mcs_a = mcsbase[0] | mcsbase[0] << 8 |
2031 mcsbase[0] << 16 | mcsbase[0] << 24;
2032 mcs_b = mcsbase[1] | mcsbase[1] << 8 |
2033 mcsbase[1] << 16 | mcsbase[1] << 24;
2034
2035 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a);
2036 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b);
2037
2038 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a);
2039 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b);
2040
2041 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a);
2042 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b);
2043
2044 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a);
2045 for (i = 0; i < 3; i++) {
2046 if (i != 2)
2047 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
2048 else
2049 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
2050 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
2051 }
2052 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b);
2053 for (i = 0; i < 3; i++) {
2054 if (i != 2)
2055 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
2056 else
2057 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
2058 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
2059 }
2060 }
2061
2062 static void
2063 rtl8723b_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
2064 {
2065 int group;
2066
2067 group = rtl8723b_channel_to_group(channel);
2068 }
2069
2070 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
2071 enum nl80211_iftype linktype)
2072 {
2073 u8 val8;
2074
2075 val8 = rtl8xxxu_read8(priv, REG_MSR);
2076 val8 &= ~MSR_LINKTYPE_MASK;
2077
2078 switch (linktype) {
2079 case NL80211_IFTYPE_UNSPECIFIED:
2080 val8 |= MSR_LINKTYPE_NONE;
2081 break;
2082 case NL80211_IFTYPE_ADHOC:
2083 val8 |= MSR_LINKTYPE_ADHOC;
2084 break;
2085 case NL80211_IFTYPE_STATION:
2086 val8 |= MSR_LINKTYPE_STATION;
2087 break;
2088 case NL80211_IFTYPE_AP:
2089 val8 |= MSR_LINKTYPE_AP;
2090 break;
2091 default:
2092 goto out;
2093 }
2094
2095 rtl8xxxu_write8(priv, REG_MSR, val8);
2096 out:
2097 return;
2098 }
2099
2100 static void
2101 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
2102 {
2103 u16 val16;
2104
2105 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
2106 RETRY_LIMIT_SHORT_MASK) |
2107 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
2108 RETRY_LIMIT_LONG_MASK);
2109
2110 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
2111 }
2112
2113 static void
2114 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
2115 {
2116 u16 val16;
2117
2118 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
2119 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
2120
2121 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
2122 }
2123
2124 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
2125 {
2126 struct device *dev = &priv->udev->dev;
2127 char *cut;
2128
2129 switch (priv->chip_cut) {
2130 case 0:
2131 cut = "A";
2132 break;
2133 case 1:
2134 cut = "B";
2135 break;
2136 case 2:
2137 cut = "C";
2138 break;
2139 case 3:
2140 cut = "D";
2141 break;
2142 case 4:
2143 cut = "E";
2144 break;
2145 default:
2146 cut = "unknown";
2147 }
2148
2149 dev_info(dev,
2150 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
2151 priv->chip_name, cut, priv->chip_vendor, priv->tx_paths,
2152 priv->rx_paths, priv->ep_tx_count, priv->has_wifi,
2153 priv->has_bluetooth, priv->has_gps, priv->hi_pa);
2154
2155 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
2156 }
2157
2158 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
2159 {
2160 struct device *dev = &priv->udev->dev;
2161 u32 val32, bonding;
2162 u16 val16;
2163
2164 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
2165 priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
2166 SYS_CFG_CHIP_VERSION_SHIFT;
2167 if (val32 & SYS_CFG_TRP_VAUX_EN) {
2168 dev_info(dev, "Unsupported test chip\n");
2169 return -ENOTSUPP;
2170 }
2171
2172 if (val32 & SYS_CFG_BT_FUNC) {
2173 if (priv->chip_cut >= 3) {
2174 sprintf(priv->chip_name, "8723BU");
2175 priv->rtlchip = 0x8723b;
2176 } else {
2177 sprintf(priv->chip_name, "8723AU");
2178 priv->usb_interrupts = 1;
2179 priv->rtlchip = 0x8723a;
2180 }
2181
2182 priv->rf_paths = 1;
2183 priv->rx_paths = 1;
2184 priv->tx_paths = 1;
2185
2186 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
2187 if (val32 & MULTI_WIFI_FUNC_EN)
2188 priv->has_wifi = 1;
2189 if (val32 & MULTI_BT_FUNC_EN)
2190 priv->has_bluetooth = 1;
2191 if (val32 & MULTI_GPS_FUNC_EN)
2192 priv->has_gps = 1;
2193 priv->is_multi_func = 1;
2194 } else if (val32 & SYS_CFG_TYPE_ID) {
2195 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
2196 bonding &= HPON_FSM_BONDING_MASK;
2197 if (priv->chip_cut >= 3) {
2198 if (bonding == HPON_FSM_BONDING_1T2R) {
2199 sprintf(priv->chip_name, "8191EU");
2200 priv->rf_paths = 2;
2201 priv->rx_paths = 2;
2202 priv->tx_paths = 1;
2203 priv->rtlchip = 0x8191e;
2204 } else {
2205 sprintf(priv->chip_name, "8192EU");
2206 priv->rf_paths = 2;
2207 priv->rx_paths = 2;
2208 priv->tx_paths = 2;
2209 priv->rtlchip = 0x8192e;
2210 }
2211 } else if (bonding == HPON_FSM_BONDING_1T2R) {
2212 sprintf(priv->chip_name, "8191CU");
2213 priv->rf_paths = 2;
2214 priv->rx_paths = 2;
2215 priv->tx_paths = 1;
2216 priv->usb_interrupts = 1;
2217 priv->rtlchip = 0x8191c;
2218 } else {
2219 sprintf(priv->chip_name, "8192CU");
2220 priv->rf_paths = 2;
2221 priv->rx_paths = 2;
2222 priv->tx_paths = 2;
2223 priv->usb_interrupts = 1;
2224 priv->rtlchip = 0x8192c;
2225 }
2226 priv->has_wifi = 1;
2227 } else {
2228 sprintf(priv->chip_name, "8188CU");
2229 priv->rf_paths = 1;
2230 priv->rx_paths = 1;
2231 priv->tx_paths = 1;
2232 priv->rtlchip = 0x8188c;
2233 priv->usb_interrupts = 1;
2234 priv->has_wifi = 1;
2235 }
2236
2237 switch (priv->rtlchip) {
2238 case 0x8188e:
2239 case 0x8192e:
2240 case 0x8723b:
2241 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
2242 case SYS_CFG_VENDOR_ID_TSMC:
2243 sprintf(priv->chip_vendor, "TSMC");
2244 break;
2245 case SYS_CFG_VENDOR_ID_SMIC:
2246 sprintf(priv->chip_vendor, "SMIC");
2247 priv->vendor_smic = 1;
2248 break;
2249 case SYS_CFG_VENDOR_ID_UMC:
2250 sprintf(priv->chip_vendor, "UMC");
2251 priv->vendor_umc = 1;
2252 break;
2253 default:
2254 sprintf(priv->chip_vendor, "unknown");
2255 }
2256 break;
2257 default:
2258 if (val32 & SYS_CFG_VENDOR_ID) {
2259 sprintf(priv->chip_vendor, "UMC");
2260 priv->vendor_umc = 1;
2261 } else {
2262 sprintf(priv->chip_vendor, "TSMC");
2263 }
2264 }
2265
2266 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
2267 priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
2268
2269 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
2270 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
2271 priv->ep_tx_high_queue = 1;
2272 priv->ep_tx_count++;
2273 }
2274
2275 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
2276 priv->ep_tx_normal_queue = 1;
2277 priv->ep_tx_count++;
2278 }
2279
2280 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
2281 priv->ep_tx_low_queue = 1;
2282 priv->ep_tx_count++;
2283 }
2284
2285 /*
2286 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
2287 */
2288 if (!priv->ep_tx_count) {
2289 switch (priv->nr_out_eps) {
2290 case 4:
2291 case 3:
2292 priv->ep_tx_low_queue = 1;
2293 priv->ep_tx_count++;
2294 case 2:
2295 priv->ep_tx_normal_queue = 1;
2296 priv->ep_tx_count++;
2297 case 1:
2298 priv->ep_tx_high_queue = 1;
2299 priv->ep_tx_count++;
2300 break;
2301 default:
2302 dev_info(dev, "Unsupported USB TX end-points\n");
2303 return -ENOTSUPP;
2304 }
2305 }
2306
2307 return 0;
2308 }
2309
2310 static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
2311 {
2312 struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723;
2313
2314 if (efuse->rtl_id != cpu_to_le16(0x8129))
2315 return -EINVAL;
2316
2317 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2318
2319 memcpy(priv->cck_tx_power_index_A,
2320 efuse->cck_tx_power_index_A,
2321 sizeof(efuse->cck_tx_power_index_A));
2322 memcpy(priv->cck_tx_power_index_B,
2323 efuse->cck_tx_power_index_B,
2324 sizeof(efuse->cck_tx_power_index_B));
2325
2326 memcpy(priv->ht40_1s_tx_power_index_A,
2327 efuse->ht40_1s_tx_power_index_A,
2328 sizeof(efuse->ht40_1s_tx_power_index_A));
2329 memcpy(priv->ht40_1s_tx_power_index_B,
2330 efuse->ht40_1s_tx_power_index_B,
2331 sizeof(efuse->ht40_1s_tx_power_index_B));
2332
2333 memcpy(priv->ht20_tx_power_index_diff,
2334 efuse->ht20_tx_power_index_diff,
2335 sizeof(efuse->ht20_tx_power_index_diff));
2336 memcpy(priv->ofdm_tx_power_index_diff,
2337 efuse->ofdm_tx_power_index_diff,
2338 sizeof(efuse->ofdm_tx_power_index_diff));
2339
2340 memcpy(priv->ht40_max_power_offset,
2341 efuse->ht40_max_power_offset,
2342 sizeof(efuse->ht40_max_power_offset));
2343 memcpy(priv->ht20_max_power_offset,
2344 efuse->ht20_max_power_offset,
2345 sizeof(efuse->ht20_max_power_offset));
2346
2347 if (priv->efuse_wifi.efuse8723.version >= 0x01) {
2348 priv->has_xtalk = 1;
2349 priv->xtalk = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
2350 }
2351 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2352 efuse->vendor_name);
2353 dev_info(&priv->udev->dev, "Product: %.41s\n",
2354 efuse->device_name);
2355 return 0;
2356 }
2357
2358 static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv)
2359 {
2360 struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu;
2361 int i;
2362
2363 if (efuse->rtl_id != cpu_to_le16(0x8129))
2364 return -EINVAL;
2365
2366 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2367
2368 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base,
2369 sizeof(efuse->tx_power_index_A.cck_base));
2370 memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base,
2371 sizeof(efuse->tx_power_index_B.cck_base));
2372
2373 memcpy(priv->ht40_1s_tx_power_index_A,
2374 efuse->tx_power_index_A.ht40_base,
2375 sizeof(efuse->tx_power_index_A.ht40_base));
2376 memcpy(priv->ht40_1s_tx_power_index_B,
2377 efuse->tx_power_index_B.ht40_base,
2378 sizeof(efuse->tx_power_index_B.ht40_base));
2379
2380 priv->ofdm_tx_power_diff[0].a =
2381 efuse->tx_power_index_A.ht20_ofdm_1s_diff.a;
2382 priv->ofdm_tx_power_diff[0].b =
2383 efuse->tx_power_index_B.ht20_ofdm_1s_diff.a;
2384
2385 priv->ht20_tx_power_diff[0].a =
2386 efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;
2387 priv->ht20_tx_power_diff[0].b =
2388 efuse->tx_power_index_B.ht20_ofdm_1s_diff.b;
2389
2390 priv->ht40_tx_power_diff[0].a = 0;
2391 priv->ht40_tx_power_diff[0].b = 0;
2392
2393 for (i = 1; i < RTL8723B_TX_COUNT; i++) {
2394 priv->ofdm_tx_power_diff[i].a =
2395 efuse->tx_power_index_A.pwr_diff[i - 1].ofdm;
2396 priv->ofdm_tx_power_diff[i].b =
2397 efuse->tx_power_index_B.pwr_diff[i - 1].ofdm;
2398
2399 priv->ht20_tx_power_diff[i].a =
2400 efuse->tx_power_index_A.pwr_diff[i - 1].ht20;
2401 priv->ht20_tx_power_diff[i].b =
2402 efuse->tx_power_index_B.pwr_diff[i - 1].ht20;
2403
2404 priv->ht40_tx_power_diff[i].a =
2405 efuse->tx_power_index_A.pwr_diff[i - 1].ht40;
2406 priv->ht40_tx_power_diff[i].b =
2407 efuse->tx_power_index_B.pwr_diff[i - 1].ht40;
2408 }
2409
2410 priv->has_xtalk = 1;
2411 priv->xtalk = priv->efuse_wifi.efuse8723bu.xtal_k & 0x3f;
2412
2413 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
2414 dev_info(&priv->udev->dev, "Product: %.41s\n", efuse->device_name);
2415
2416 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2417 int i;
2418 unsigned char *raw = priv->efuse_wifi.raw;
2419
2420 dev_info(&priv->udev->dev,
2421 "%s: dumping efuse (0x%02zx bytes):\n",
2422 __func__, sizeof(struct rtl8723bu_efuse));
2423 for (i = 0; i < sizeof(struct rtl8723bu_efuse); i += 8) {
2424 dev_info(&priv->udev->dev, "%02x: "
2425 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2426 raw[i], raw[i + 1], raw[i + 2],
2427 raw[i + 3], raw[i + 4], raw[i + 5],
2428 raw[i + 6], raw[i + 7]);
2429 }
2430 }
2431
2432 return 0;
2433 }
2434
2435 #ifdef CONFIG_RTL8XXXU_UNTESTED
2436
2437 static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
2438 {
2439 struct rtl8192cu_efuse *efuse = &priv->efuse_wifi.efuse8192;
2440 int i;
2441
2442 if (efuse->rtl_id != cpu_to_le16(0x8129))
2443 return -EINVAL;
2444
2445 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2446
2447 memcpy(priv->cck_tx_power_index_A,
2448 efuse->cck_tx_power_index_A,
2449 sizeof(efuse->cck_tx_power_index_A));
2450 memcpy(priv->cck_tx_power_index_B,
2451 efuse->cck_tx_power_index_B,
2452 sizeof(efuse->cck_tx_power_index_B));
2453
2454 memcpy(priv->ht40_1s_tx_power_index_A,
2455 efuse->ht40_1s_tx_power_index_A,
2456 sizeof(efuse->ht40_1s_tx_power_index_A));
2457 memcpy(priv->ht40_1s_tx_power_index_B,
2458 efuse->ht40_1s_tx_power_index_B,
2459 sizeof(efuse->ht40_1s_tx_power_index_B));
2460 memcpy(priv->ht40_2s_tx_power_index_diff,
2461 efuse->ht40_2s_tx_power_index_diff,
2462 sizeof(efuse->ht40_2s_tx_power_index_diff));
2463
2464 memcpy(priv->ht20_tx_power_index_diff,
2465 efuse->ht20_tx_power_index_diff,
2466 sizeof(efuse->ht20_tx_power_index_diff));
2467 memcpy(priv->ofdm_tx_power_index_diff,
2468 efuse->ofdm_tx_power_index_diff,
2469 sizeof(efuse->ofdm_tx_power_index_diff));
2470
2471 memcpy(priv->ht40_max_power_offset,
2472 efuse->ht40_max_power_offset,
2473 sizeof(efuse->ht40_max_power_offset));
2474 memcpy(priv->ht20_max_power_offset,
2475 efuse->ht20_max_power_offset,
2476 sizeof(efuse->ht20_max_power_offset));
2477
2478 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2479 efuse->vendor_name);
2480 dev_info(&priv->udev->dev, "Product: %.20s\n",
2481 efuse->device_name);
2482
2483 if (efuse->rf_regulatory & 0x20) {
2484 sprintf(priv->chip_name, "8188RU");
2485 priv->hi_pa = 1;
2486 }
2487
2488 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2489 unsigned char *raw = priv->efuse_wifi.raw;
2490
2491 dev_info(&priv->udev->dev,
2492 "%s: dumping efuse (0x%02zx bytes):\n",
2493 __func__, sizeof(struct rtl8192cu_efuse));
2494 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
2495 dev_info(&priv->udev->dev, "%02x: "
2496 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2497 raw[i], raw[i + 1], raw[i + 2],
2498 raw[i + 3], raw[i + 4], raw[i + 5],
2499 raw[i + 6], raw[i + 7]);
2500 }
2501 }
2502 return 0;
2503 }
2504
2505 #endif
2506
2507 static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv)
2508 {
2509 struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu;
2510 int i;
2511
2512 if (efuse->rtl_id != cpu_to_le16(0x8129))
2513 return -EINVAL;
2514
2515 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2516
2517 priv->has_xtalk = 1;
2518 priv->xtalk = priv->efuse_wifi.efuse8192eu.xtal_k & 0x3f;
2519
2520 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
2521 dev_info(&priv->udev->dev, "Product: %.11s\n", efuse->device_name);
2522 dev_info(&priv->udev->dev, "Serial: %.11s\n", efuse->serial);
2523
2524 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2525 unsigned char *raw = priv->efuse_wifi.raw;
2526
2527 dev_info(&priv->udev->dev,
2528 "%s: dumping efuse (0x%02zx bytes):\n",
2529 __func__, sizeof(struct rtl8192eu_efuse));
2530 for (i = 0; i < sizeof(struct rtl8192eu_efuse); i += 8) {
2531 dev_info(&priv->udev->dev, "%02x: "
2532 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2533 raw[i], raw[i + 1], raw[i + 2],
2534 raw[i + 3], raw[i + 4], raw[i + 5],
2535 raw[i + 6], raw[i + 7]);
2536 }
2537 }
2538 return 0;
2539 }
2540
2541 static int
2542 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
2543 {
2544 int i;
2545 u8 val8;
2546 u32 val32;
2547
2548 /* Write Address */
2549 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
2550 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
2551 val8 &= 0xfc;
2552 val8 |= (offset >> 8) & 0x03;
2553 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
2554
2555 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
2556 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
2557
2558 /* Poll for data read */
2559 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2560 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
2561 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2562 if (val32 & BIT(31))
2563 break;
2564 }
2565
2566 if (i == RTL8XXXU_MAX_REG_POLL)
2567 return -EIO;
2568
2569 udelay(50);
2570 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2571
2572 *data = val32 & 0xff;
2573 return 0;
2574 }
2575
2576 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
2577 {
2578 struct device *dev = &priv->udev->dev;
2579 int i, ret = 0;
2580 u8 val8, word_mask, header, extheader;
2581 u16 val16, efuse_addr, offset;
2582 u32 val32;
2583
2584 val16 = rtl8xxxu_read16(priv, REG_9346CR);
2585 if (val16 & EEPROM_ENABLE)
2586 priv->has_eeprom = 1;
2587 if (val16 & EEPROM_BOOT)
2588 priv->boot_eeprom = 1;
2589
2590 if (priv->is_multi_func) {
2591 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
2592 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
2593 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
2594 }
2595
2596 dev_dbg(dev, "Booting from %s\n",
2597 priv->boot_eeprom ? "EEPROM" : "EFUSE");
2598
2599 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
2600
2601 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
2602 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
2603 if (!(val16 & SYS_ISO_PWC_EV12V)) {
2604 val16 |= SYS_ISO_PWC_EV12V;
2605 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
2606 }
2607 /* Reset: 0x0000[28], default valid */
2608 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2609 if (!(val16 & SYS_FUNC_ELDR)) {
2610 val16 |= SYS_FUNC_ELDR;
2611 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2612 }
2613
2614 /*
2615 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
2616 */
2617 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
2618 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
2619 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
2620 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
2621 }
2622
2623 /* Default value is 0xff */
2624 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
2625
2626 efuse_addr = 0;
2627 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
2628 u16 map_addr;
2629
2630 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
2631 if (ret || header == 0xff)
2632 goto exit;
2633
2634 if ((header & 0x1f) == 0x0f) { /* extended header */
2635 offset = (header & 0xe0) >> 5;
2636
2637 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
2638 &extheader);
2639 if (ret)
2640 goto exit;
2641 /* All words disabled */
2642 if ((extheader & 0x0f) == 0x0f)
2643 continue;
2644
2645 offset |= ((extheader & 0xf0) >> 1);
2646 word_mask = extheader & 0x0f;
2647 } else {
2648 offset = (header >> 4) & 0x0f;
2649 word_mask = header & 0x0f;
2650 }
2651
2652 /* Get word enable value from PG header */
2653
2654 /* We have 8 bits to indicate validity */
2655 map_addr = offset * 8;
2656 if (map_addr >= EFUSE_MAP_LEN) {
2657 dev_warn(dev, "%s: Illegal map_addr (%04x), "
2658 "efuse corrupt!\n",
2659 __func__, map_addr);
2660 ret = -EINVAL;
2661 goto exit;
2662 }
2663 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
2664 /* Check word enable condition in the section */
2665 if (word_mask & BIT(i)) {
2666 map_addr += 2;
2667 continue;
2668 }
2669
2670 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2671 if (ret)
2672 goto exit;
2673 priv->efuse_wifi.raw[map_addr++] = val8;
2674
2675 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2676 if (ret)
2677 goto exit;
2678 priv->efuse_wifi.raw[map_addr++] = val8;
2679 }
2680 }
2681
2682 exit:
2683 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
2684
2685 return ret;
2686 }
2687
2688 static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
2689 {
2690 u8 val8;
2691 u16 sys_func;
2692
2693 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2694 val8 &= ~BIT(0);
2695 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2696 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2697 sys_func &= ~SYS_FUNC_CPU_ENABLE;
2698 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2699 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2700 val8 |= BIT(0);
2701 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2702 sys_func |= SYS_FUNC_CPU_ENABLE;
2703 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2704 }
2705
2706 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
2707 {
2708 struct device *dev = &priv->udev->dev;
2709 int ret = 0, i;
2710 u32 val32;
2711
2712 /* Poll checksum report */
2713 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2714 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2715 if (val32 & MCU_FW_DL_CSUM_REPORT)
2716 break;
2717 }
2718
2719 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2720 dev_warn(dev, "Firmware checksum poll timed out\n");
2721 ret = -EAGAIN;
2722 goto exit;
2723 }
2724
2725 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2726 val32 |= MCU_FW_DL_READY;
2727 val32 &= ~MCU_WINT_INIT_READY;
2728 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2729
2730 /*
2731 * Reset the 8051 in order for the firmware to start running,
2732 * otherwise it won't come up on the 8192eu
2733 */
2734 rtl8xxxu_reset_8051(priv);
2735
2736 /* Wait for firmware to become ready */
2737 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2738 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2739 if (val32 & MCU_WINT_INIT_READY)
2740 break;
2741
2742 udelay(100);
2743 }
2744
2745 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2746 dev_warn(dev, "Firmware failed to start\n");
2747 ret = -EAGAIN;
2748 goto exit;
2749 }
2750
2751 /*
2752 * Init H2C command
2753 */
2754 if (priv->rtlchip == 0x8723b)
2755 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f);
2756 exit:
2757 return ret;
2758 }
2759
2760 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
2761 {
2762 int pages, remainder, i, ret;
2763 u8 val8;
2764 u16 val16;
2765 u32 val32;
2766 u8 *fwptr;
2767
2768 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2769 val8 |= 4;
2770 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2771
2772 /* 8051 enable */
2773 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2774 val16 |= SYS_FUNC_CPU_ENABLE;
2775 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2776
2777 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2778 if (val8 & MCU_FW_RAM_SEL) {
2779 pr_info("do the RAM reset\n");
2780 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
2781 rtl8xxxu_reset_8051(priv);
2782 }
2783
2784 /* MCU firmware download enable */
2785 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2786 val8 |= MCU_FW_DL_ENABLE;
2787 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2788
2789 /* 8051 reset */
2790 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2791 val32 &= ~BIT(19);
2792 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2793
2794 /* Reset firmware download checksum */
2795 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2796 val8 |= MCU_FW_DL_CSUM_REPORT;
2797 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2798
2799 pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2800 remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2801
2802 fwptr = priv->fw_data->data;
2803
2804 for (i = 0; i < pages; i++) {
2805 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2806 val8 |= i;
2807 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2808
2809 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2810 fwptr, RTL_FW_PAGE_SIZE);
2811 if (ret != RTL_FW_PAGE_SIZE) {
2812 ret = -EAGAIN;
2813 goto fw_abort;
2814 }
2815
2816 fwptr += RTL_FW_PAGE_SIZE;
2817 }
2818
2819 if (remainder) {
2820 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2821 val8 |= i;
2822 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2823 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2824 fwptr, remainder);
2825 if (ret != remainder) {
2826 ret = -EAGAIN;
2827 goto fw_abort;
2828 }
2829 }
2830
2831 ret = 0;
2832 fw_abort:
2833 /* MCU firmware download disable */
2834 val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
2835 val16 &= ~MCU_FW_DL_ENABLE;
2836 rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
2837
2838 return ret;
2839 }
2840
2841 static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2842 {
2843 struct device *dev = &priv->udev->dev;
2844 const struct firmware *fw;
2845 int ret = 0;
2846 u16 signature;
2847
2848 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2849 if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2850 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2851 ret = -EAGAIN;
2852 goto exit;
2853 }
2854 if (!fw) {
2855 dev_warn(dev, "Firmware data not available\n");
2856 ret = -EINVAL;
2857 goto exit;
2858 }
2859
2860 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
2861 if (!priv->fw_data) {
2862 ret = -ENOMEM;
2863 goto exit;
2864 }
2865 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2866
2867 signature = le16_to_cpu(priv->fw_data->signature);
2868 switch (signature & 0xfff0) {
2869 case 0x92e0:
2870 case 0x92c0:
2871 case 0x88c0:
2872 case 0x5300:
2873 case 0x2300:
2874 break;
2875 default:
2876 ret = -EINVAL;
2877 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2878 __func__, signature);
2879 }
2880
2881 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2882 le16_to_cpu(priv->fw_data->major_version),
2883 priv->fw_data->minor_version, signature);
2884
2885 exit:
2886 release_firmware(fw);
2887 return ret;
2888 }
2889
2890 static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
2891 {
2892 char *fw_name;
2893 int ret;
2894
2895 switch (priv->chip_cut) {
2896 case 0:
2897 fw_name = "rtlwifi/rtl8723aufw_A.bin";
2898 break;
2899 case 1:
2900 if (priv->enable_bluetooth)
2901 fw_name = "rtlwifi/rtl8723aufw_B.bin";
2902 else
2903 fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
2904
2905 break;
2906 default:
2907 return -EINVAL;
2908 }
2909
2910 ret = rtl8xxxu_load_firmware(priv, fw_name);
2911 return ret;
2912 }
2913
2914 static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv)
2915 {
2916 char *fw_name;
2917 int ret;
2918
2919 if (priv->enable_bluetooth)
2920 fw_name = "rtlwifi/rtl8723bu_bt.bin";
2921 else
2922 fw_name = "rtlwifi/rtl8723bu_nic.bin";
2923
2924 ret = rtl8xxxu_load_firmware(priv, fw_name);
2925 return ret;
2926 }
2927
2928 #ifdef CONFIG_RTL8XXXU_UNTESTED
2929
2930 static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
2931 {
2932 char *fw_name;
2933 int ret;
2934
2935 if (!priv->vendor_umc)
2936 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
2937 else if (priv->chip_cut || priv->rtlchip == 0x8192c)
2938 fw_name = "rtlwifi/rtl8192cufw_B.bin";
2939 else
2940 fw_name = "rtlwifi/rtl8192cufw_A.bin";
2941
2942 ret = rtl8xxxu_load_firmware(priv, fw_name);
2943
2944 return ret;
2945 }
2946
2947 #endif
2948
2949 static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv)
2950 {
2951 char *fw_name;
2952 int ret;
2953
2954 fw_name = "rtlwifi/rtl8192eu_nic.bin";
2955
2956 ret = rtl8xxxu_load_firmware(priv, fw_name);
2957
2958 return ret;
2959 }
2960
2961 static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2962 {
2963 u16 val16;
2964 int i = 100;
2965
2966 /* Inform 8051 to perform reset */
2967 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2968
2969 for (i = 100; i > 0; i--) {
2970 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2971
2972 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2973 dev_dbg(&priv->udev->dev,
2974 "%s: Firmware self reset success!\n", __func__);
2975 break;
2976 }
2977 udelay(50);
2978 }
2979
2980 if (!i) {
2981 /* Force firmware reset */
2982 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2983 val16 &= ~SYS_FUNC_CPU_ENABLE;
2984 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2985 }
2986 }
2987
2988 static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv)
2989 {
2990 u32 val32;
2991
2992 val32 = rtl8xxxu_read32(priv, 0x64);
2993 val32 &= ~(BIT(20) | BIT(24));
2994 rtl8xxxu_write32(priv, 0x64, val32);
2995
2996 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
2997 val32 &= ~BIT(4);
2998 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
2999
3000 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
3001 val32 |= BIT(3);
3002 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
3003
3004 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
3005 val32 |= BIT(24);
3006 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
3007
3008 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
3009 val32 &= ~BIT(23);
3010 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
3011
3012 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
3013 val32 |= (BIT(0) | BIT(1));
3014 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
3015
3016 val32 = rtl8xxxu_read32(priv, REG_RFE_CTRL_ANTA_SRC);
3017 val32 &= 0xffffff00;
3018 val32 |= 0x77;
3019 rtl8xxxu_write32(priv, REG_RFE_CTRL_ANTA_SRC, val32);
3020
3021 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
3022 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
3023 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
3024 }
3025
3026 static int
3027 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv, struct rtl8xxxu_reg8val *array)
3028 {
3029 int i, ret;
3030 u16 reg;
3031 u8 val;
3032
3033 for (i = 0; ; i++) {
3034 reg = array[i].reg;
3035 val = array[i].val;
3036
3037 if (reg == 0xffff && val == 0xff)
3038 break;
3039
3040 ret = rtl8xxxu_write8(priv, reg, val);
3041 if (ret != 1) {
3042 dev_warn(&priv->udev->dev,
3043 "Failed to initialize MAC\n");
3044 return -EAGAIN;
3045 }
3046 }
3047
3048 if (priv->rtlchip != 0x8723b)
3049 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
3050
3051 return 0;
3052 }
3053
3054 static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
3055 struct rtl8xxxu_reg32val *array)
3056 {
3057 int i, ret;
3058 u16 reg;
3059 u32 val;
3060
3061 for (i = 0; ; i++) {
3062 reg = array[i].reg;
3063 val = array[i].val;
3064
3065 if (reg == 0xffff && val == 0xffffffff)
3066 break;
3067
3068 ret = rtl8xxxu_write32(priv, reg, val);
3069 if (ret != sizeof(val)) {
3070 dev_warn(&priv->udev->dev,
3071 "Failed to initialize PHY\n");
3072 return -EAGAIN;
3073 }
3074 udelay(1);
3075 }
3076
3077 return 0;
3078 }
3079
3080 /*
3081 * Most of this is black magic retrieved from the old rtl8723au driver
3082 */
3083 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
3084 {
3085 u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
3086 u16 val16;
3087 u32 val32;
3088
3089 /*
3090 * Todo: The vendor driver maintains a table of PHY register
3091 * addresses, which is initialized here. Do we need this?
3092 */
3093
3094 if (priv->rtlchip == 0x8723b) {
3095 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3096 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB |
3097 SYS_FUNC_DIO_RF;
3098 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3099
3100 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
3101 } else {
3102 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
3103 udelay(2);
3104 val8 |= AFE_PLL_320_ENABLE;
3105 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
3106 udelay(2);
3107
3108 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
3109 udelay(2);
3110
3111 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3112 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
3113 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3114 }
3115
3116 if (priv->rtlchip != 0x8723b) {
3117 /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
3118 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
3119 val32 &= ~AFE_XTAL_RF_GATE;
3120 if (priv->has_bluetooth)
3121 val32 &= ~AFE_XTAL_BT_GATE;
3122 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
3123 }
3124
3125 /* 6. 0x1f[7:0] = 0x07 */
3126 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
3127 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
3128
3129 if (priv->hi_pa)
3130 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
3131 else if (priv->tx_paths == 2)
3132 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
3133 else if (priv->rtlchip == 0x8723b) {
3134 /*
3135 * Why?
3136 */
3137 rtl8xxxu_write8(priv, REG_SYS_FUNC, 0xe3);
3138 rtl8xxxu_write8(priv, REG_AFE_XTAL_CTRL + 1, 0x80);
3139 rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table);
3140 } else
3141 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
3142
3143
3144 if (priv->rtlchip == 0x8188c && priv->hi_pa &&
3145 priv->vendor_umc && priv->chip_cut == 1)
3146 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
3147
3148 if (priv->tx_paths == 1 && priv->rx_paths == 2) {
3149 /*
3150 * For 1T2R boards, patch the registers.
3151 *
3152 * It looks like 8191/2 1T2R boards use path B for TX
3153 */
3154 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
3155 val32 &= ~(BIT(0) | BIT(1));
3156 val32 |= BIT(1);
3157 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
3158
3159 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
3160 val32 &= ~0x300033;
3161 val32 |= 0x200022;
3162 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
3163
3164 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
3165 val32 &= 0xff000000;
3166 val32 |= 0x45000000;
3167 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
3168
3169 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
3170 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
3171 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
3172 OFDM_RF_PATH_TX_B);
3173 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
3174
3175 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
3176 val32 &= ~(BIT(4) | BIT(5));
3177 val32 |= BIT(4);
3178 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
3179
3180 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
3181 val32 &= ~(BIT(27) | BIT(26));
3182 val32 |= BIT(27);
3183 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
3184
3185 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
3186 val32 &= ~(BIT(27) | BIT(26));
3187 val32 |= BIT(27);
3188 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
3189
3190 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
3191 val32 &= ~(BIT(27) | BIT(26));
3192 val32 |= BIT(27);
3193 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
3194
3195 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
3196 val32 &= ~(BIT(27) | BIT(26));
3197 val32 |= BIT(27);
3198 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
3199
3200 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
3201 val32 &= ~(BIT(27) | BIT(26));
3202 val32 |= BIT(27);
3203 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
3204 }
3205
3206 if (priv->rtlchip == 0x8723b)
3207 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table);
3208 else if (priv->hi_pa)
3209 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
3210 else
3211 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
3212
3213 if (priv->has_xtalk) {
3214 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
3215
3216 val8 = priv->xtalk;
3217 val32 &= 0xff000fff;
3218 val32 |= ((val8 | (val8 << 6)) << 12);
3219
3220 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
3221 }
3222
3223 if (priv->rtlchip != 0x8723bu) {
3224 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
3225 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
3226 ldohci12 = 0x57;
3227 lpldo = 1;
3228 val32 = (lpldo << 24) | (ldohci12 << 16) |
3229 (ldov12d << 8) | ldoa15;
3230
3231 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
3232 }
3233
3234 return 0;
3235 }
3236
3237 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
3238 struct rtl8xxxu_rfregval *array,
3239 enum rtl8xxxu_rfpath path)
3240 {
3241 int i, ret;
3242 u8 reg;
3243 u32 val;
3244
3245 for (i = 0; ; i++) {
3246 reg = array[i].reg;
3247 val = array[i].val;
3248
3249 if (reg == 0xff && val == 0xffffffff)
3250 break;
3251
3252 switch (reg) {
3253 case 0xfe:
3254 msleep(50);
3255 continue;
3256 case 0xfd:
3257 mdelay(5);
3258 continue;
3259 case 0xfc:
3260 mdelay(1);
3261 continue;
3262 case 0xfb:
3263 udelay(50);
3264 continue;
3265 case 0xfa:
3266 udelay(5);
3267 continue;
3268 case 0xf9:
3269 udelay(1);
3270 continue;
3271 }
3272
3273 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
3274 if (ret) {
3275 dev_warn(&priv->udev->dev,
3276 "Failed to initialize RF\n");
3277 return -EAGAIN;
3278 }
3279 udelay(1);
3280 }
3281
3282 return 0;
3283 }
3284
3285 static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
3286 struct rtl8xxxu_rfregval *table,
3287 enum rtl8xxxu_rfpath path)
3288 {
3289 u32 val32;
3290 u16 val16, rfsi_rfenv;
3291 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
3292
3293 switch (path) {
3294 case RF_A:
3295 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
3296 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
3297 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
3298 break;
3299 case RF_B:
3300 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
3301 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
3302 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
3303 break;
3304 default:
3305 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
3306 __func__, path + 'A');
3307 return -EINVAL;
3308 }
3309 /* For path B, use XB */
3310 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
3311 rfsi_rfenv &= FPGA0_RF_RFENV;
3312
3313 /*
3314 * These two we might be able to optimize into one
3315 */
3316 val32 = rtl8xxxu_read32(priv, reg_int_oe);
3317 val32 |= BIT(20); /* 0x10 << 16 */
3318 rtl8xxxu_write32(priv, reg_int_oe, val32);
3319 udelay(1);
3320
3321 val32 = rtl8xxxu_read32(priv, reg_int_oe);
3322 val32 |= BIT(4);
3323 rtl8xxxu_write32(priv, reg_int_oe, val32);
3324 udelay(1);
3325
3326 /*
3327 * These two we might be able to optimize into one
3328 */
3329 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3330 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
3331 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3332 udelay(1);
3333
3334 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3335 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
3336 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3337 udelay(1);
3338
3339 rtl8xxxu_init_rf_regs(priv, table, path);
3340
3341 /* For path B, use XB */
3342 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
3343 val16 &= ~FPGA0_RF_RFENV;
3344 val16 |= rfsi_rfenv;
3345 rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
3346
3347 return 0;
3348 }
3349
3350 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
3351 {
3352 int ret = -EBUSY;
3353 int count = 0;
3354 u32 value;
3355
3356 value = LLT_OP_WRITE | address << 8 | data;
3357
3358 rtl8xxxu_write32(priv, REG_LLT_INIT, value);
3359
3360 do {
3361 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
3362 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
3363 ret = 0;
3364 break;
3365 }
3366 } while (count++ < 20);
3367
3368 return ret;
3369 }
3370
3371 static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3372 {
3373 int ret;
3374 int i;
3375
3376 for (i = 0; i < last_tx_page; i++) {
3377 ret = rtl8xxxu_llt_write(priv, i, i + 1);
3378 if (ret)
3379 goto exit;
3380 }
3381
3382 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
3383 if (ret)
3384 goto exit;
3385
3386 /* Mark remaining pages as a ring buffer */
3387 for (i = last_tx_page + 1; i < 0xff; i++) {
3388 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
3389 if (ret)
3390 goto exit;
3391 }
3392
3393 /* Let last entry point to the start entry of ring buffer */
3394 ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
3395 if (ret)
3396 goto exit;
3397
3398 exit:
3399 return ret;
3400 }
3401
3402 static int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3403 {
3404 u32 val32;
3405 int ret = 0;
3406 int i;
3407
3408 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3409 val32 |= AUTO_LLT_INIT_LLT;
3410 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
3411
3412 for (i = 500; i; i--) {
3413 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3414 if (!(val32 & AUTO_LLT_INIT_LLT))
3415 break;
3416 usleep_range(2, 4);
3417 }
3418
3419 if (!i) {
3420 ret = -EBUSY;
3421 dev_warn(&priv->udev->dev, "LLT table init failed\n");
3422 }
3423
3424 return ret;
3425 }
3426
3427 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
3428 {
3429 u16 val16, hi, lo;
3430 u16 hiq, mgq, bkq, beq, viq, voq;
3431 int hip, mgp, bkp, bep, vip, vop;
3432 int ret = 0;
3433
3434 switch (priv->ep_tx_count) {
3435 case 1:
3436 if (priv->ep_tx_high_queue) {
3437 hi = TRXDMA_QUEUE_HIGH;
3438 } else if (priv->ep_tx_low_queue) {
3439 hi = TRXDMA_QUEUE_LOW;
3440 } else if (priv->ep_tx_normal_queue) {
3441 hi = TRXDMA_QUEUE_NORMAL;
3442 } else {
3443 hi = 0;
3444 ret = -EINVAL;
3445 }
3446
3447 hiq = hi;
3448 mgq = hi;
3449 bkq = hi;
3450 beq = hi;
3451 viq = hi;
3452 voq = hi;
3453
3454 hip = 0;
3455 mgp = 0;
3456 bkp = 0;
3457 bep = 0;
3458 vip = 0;
3459 vop = 0;
3460 break;
3461 case 2:
3462 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
3463 hi = TRXDMA_QUEUE_HIGH;
3464 lo = TRXDMA_QUEUE_LOW;
3465 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
3466 hi = TRXDMA_QUEUE_NORMAL;
3467 lo = TRXDMA_QUEUE_LOW;
3468 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
3469 hi = TRXDMA_QUEUE_HIGH;
3470 lo = TRXDMA_QUEUE_NORMAL;
3471 } else {
3472 ret = -EINVAL;
3473 hi = 0;
3474 lo = 0;
3475 }
3476
3477 hiq = hi;
3478 mgq = hi;
3479 bkq = lo;
3480 beq = lo;
3481 viq = hi;
3482 voq = hi;
3483
3484 hip = 0;
3485 mgp = 0;
3486 bkp = 1;
3487 bep = 1;
3488 vip = 0;
3489 vop = 0;
3490 break;
3491 case 3:
3492 beq = TRXDMA_QUEUE_LOW;
3493 bkq = TRXDMA_QUEUE_LOW;
3494 viq = TRXDMA_QUEUE_NORMAL;
3495 voq = TRXDMA_QUEUE_HIGH;
3496 mgq = TRXDMA_QUEUE_HIGH;
3497 hiq = TRXDMA_QUEUE_HIGH;
3498
3499 hip = hiq ^ 3;
3500 mgp = mgq ^ 3;
3501 bkp = bkq ^ 3;
3502 bep = beq ^ 3;
3503 vip = viq ^ 3;
3504 vop = viq ^ 3;
3505 break;
3506 default:
3507 ret = -EINVAL;
3508 }
3509
3510 /*
3511 * None of the vendor drivers are configuring the beacon
3512 * queue here .... why?
3513 */
3514 if (!ret) {
3515 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
3516 val16 &= 0x7;
3517 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
3518 (viq << TRXDMA_CTRL_VIQ_SHIFT) |
3519 (beq << TRXDMA_CTRL_BEQ_SHIFT) |
3520 (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
3521 (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
3522 (hiq << TRXDMA_CTRL_HIQ_SHIFT);
3523 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
3524
3525 priv->pipe_out[TXDESC_QUEUE_VO] =
3526 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
3527 priv->pipe_out[TXDESC_QUEUE_VI] =
3528 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
3529 priv->pipe_out[TXDESC_QUEUE_BE] =
3530 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
3531 priv->pipe_out[TXDESC_QUEUE_BK] =
3532 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
3533 priv->pipe_out[TXDESC_QUEUE_BEACON] =
3534 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3535 priv->pipe_out[TXDESC_QUEUE_MGNT] =
3536 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
3537 priv->pipe_out[TXDESC_QUEUE_HIGH] =
3538 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
3539 priv->pipe_out[TXDESC_QUEUE_CMD] =
3540 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3541 }
3542
3543 return ret;
3544 }
3545
3546 static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv,
3547 bool iqk_ok, int result[][8],
3548 int candidate, bool tx_only)
3549 {
3550 u32 oldval, x, tx0_a, reg;
3551 int y, tx0_c;
3552 u32 val32;
3553
3554 if (!iqk_ok)
3555 return;
3556
3557 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3558 oldval = val32 >> 22;
3559
3560 x = result[candidate][0];
3561 if ((x & 0x00000200) != 0)
3562 x = x | 0xfffffc00;
3563 tx0_a = (x * oldval) >> 8;
3564
3565 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3566 val32 &= ~0x3ff;
3567 val32 |= tx0_a;
3568 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3569
3570 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3571 val32 &= ~BIT(31);
3572 if ((x * oldval >> 7) & 0x1)
3573 val32 |= BIT(31);
3574 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3575
3576 y = result[candidate][1];
3577 if ((y & 0x00000200) != 0)
3578 y = y | 0xfffffc00;
3579 tx0_c = (y * oldval) >> 8;
3580
3581 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
3582 val32 &= ~0xf0000000;
3583 val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
3584 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
3585
3586 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3587 val32 &= ~0x003f0000;
3588 val32 |= ((tx0_c & 0x3f) << 16);
3589 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3590
3591 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3592 val32 &= ~BIT(29);
3593 if ((y * oldval >> 7) & 0x1)
3594 val32 |= BIT(29);
3595 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3596
3597 if (tx_only) {
3598 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3599 return;
3600 }
3601
3602 reg = result[candidate][2];
3603
3604 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3605 val32 &= ~0x3ff;
3606 val32 |= (reg & 0x3ff);
3607 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3608
3609 reg = result[candidate][3] & 0x3F;
3610
3611 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3612 val32 &= ~0xfc00;
3613 val32 |= ((reg << 10) & 0xfc00);
3614 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3615
3616 reg = (result[candidate][3] >> 6) & 0xF;
3617
3618 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
3619 val32 &= ~0xf0000000;
3620 val32 |= (reg << 28);
3621 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
3622 }
3623
3624 static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv,
3625 bool iqk_ok, int result[][8],
3626 int candidate, bool tx_only)
3627 {
3628 u32 oldval, x, tx1_a, reg;
3629 int y, tx1_c;
3630 u32 val32;
3631
3632 if (!iqk_ok)
3633 return;
3634
3635 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3636 oldval = val32 >> 22;
3637
3638 x = result[candidate][4];
3639 if ((x & 0x00000200) != 0)
3640 x = x | 0xfffffc00;
3641 tx1_a = (x * oldval) >> 8;
3642
3643 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3644 val32 &= ~0x3ff;
3645 val32 |= tx1_a;
3646 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3647
3648 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3649 val32 &= ~BIT(27);
3650 if ((x * oldval >> 7) & 0x1)
3651 val32 |= BIT(27);
3652 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3653
3654 y = result[candidate][5];
3655 if ((y & 0x00000200) != 0)
3656 y = y | 0xfffffc00;
3657 tx1_c = (y * oldval) >> 8;
3658
3659 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
3660 val32 &= ~0xf0000000;
3661 val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
3662 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
3663
3664 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3665 val32 &= ~0x003f0000;
3666 val32 |= ((tx1_c & 0x3f) << 16);
3667 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3668
3669 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3670 val32 &= ~BIT(25);
3671 if ((y * oldval >> 7) & 0x1)
3672 val32 |= BIT(25);
3673 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3674
3675 if (tx_only) {
3676 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3677 return;
3678 }
3679
3680 reg = result[candidate][6];
3681
3682 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3683 val32 &= ~0x3ff;
3684 val32 |= (reg & 0x3ff);
3685 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3686
3687 reg = result[candidate][7] & 0x3f;
3688
3689 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3690 val32 &= ~0xfc00;
3691 val32 |= ((reg << 10) & 0xfc00);
3692 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3693
3694 reg = (result[candidate][7] >> 6) & 0xf;
3695
3696 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
3697 val32 &= ~0x0000f000;
3698 val32 |= (reg << 12);
3699 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
3700 }
3701
3702 #define MAX_TOLERANCE 5
3703
3704 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
3705 int result[][8], int c1, int c2)
3706 {
3707 u32 i, j, diff, simubitmap, bound = 0;
3708 int candidate[2] = {-1, -1}; /* for path A and path B */
3709 bool retval = true;
3710
3711 if (priv->tx_paths > 1)
3712 bound = 8;
3713 else
3714 bound = 4;
3715
3716 simubitmap = 0;
3717
3718 for (i = 0; i < bound; i++) {
3719 diff = (result[c1][i] > result[c2][i]) ?
3720 (result[c1][i] - result[c2][i]) :
3721 (result[c2][i] - result[c1][i]);
3722 if (diff > MAX_TOLERANCE) {
3723 if ((i == 2 || i == 6) && !simubitmap) {
3724 if (result[c1][i] + result[c1][i + 1] == 0)
3725 candidate[(i / 4)] = c2;
3726 else if (result[c2][i] + result[c2][i + 1] == 0)
3727 candidate[(i / 4)] = c1;
3728 else
3729 simubitmap = simubitmap | (1 << i);
3730 } else {
3731 simubitmap = simubitmap | (1 << i);
3732 }
3733 }
3734 }
3735
3736 if (simubitmap == 0) {
3737 for (i = 0; i < (bound / 4); i++) {
3738 if (candidate[i] >= 0) {
3739 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3740 result[3][j] = result[candidate[i]][j];
3741 retval = false;
3742 }
3743 }
3744 return retval;
3745 } else if (!(simubitmap & 0x0f)) {
3746 /* path A OK */
3747 for (i = 0; i < 4; i++)
3748 result[3][i] = result[c1][i];
3749 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
3750 /* path B OK */
3751 for (i = 4; i < 8; i++)
3752 result[3][i] = result[c1][i];
3753 }
3754
3755 return false;
3756 }
3757
3758 static bool rtl8723bu_simularity_compare(struct rtl8xxxu_priv *priv,
3759 int result[][8], int c1, int c2)
3760 {
3761 u32 i, j, diff, simubitmap, bound = 0;
3762 int candidate[2] = {-1, -1}; /* for path A and path B */
3763 int tmp1, tmp2;
3764 bool retval = true;
3765
3766 if (priv->tx_paths > 1)
3767 bound = 8;
3768 else
3769 bound = 4;
3770
3771 simubitmap = 0;
3772
3773 for (i = 0; i < bound; i++) {
3774 if (i & 1) {
3775 if ((result[c1][i] & 0x00000200))
3776 tmp1 = result[c1][i] | 0xfffffc00;
3777 else
3778 tmp1 = result[c1][i];
3779
3780 if ((result[c2][i]& 0x00000200))
3781 tmp2 = result[c2][i] | 0xfffffc00;
3782 else
3783 tmp2 = result[c2][i];
3784 } else {
3785 tmp1 = result[c1][i];
3786 tmp2 = result[c2][i];
3787 }
3788
3789 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
3790
3791 if (diff > MAX_TOLERANCE) {
3792 if ((i == 2 || i == 6) && !simubitmap) {
3793 if (result[c1][i] + result[c1][i + 1] == 0)
3794 candidate[(i / 4)] = c2;
3795 else if (result[c2][i] + result[c2][i + 1] == 0)
3796 candidate[(i / 4)] = c1;
3797 else
3798 simubitmap = simubitmap | (1 << i);
3799 } else {
3800 simubitmap = simubitmap | (1 << i);
3801 }
3802 }
3803 }
3804
3805 if (simubitmap == 0) {
3806 for (i = 0; i < (bound / 4); i++) {
3807 if (candidate[i] >= 0) {
3808 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3809 result[3][j] = result[candidate[i]][j];
3810 retval = false;
3811 }
3812 }
3813 return retval;
3814 } else {
3815 if (!(simubitmap & 0x03)) {
3816 /* path A TX OK */
3817 for (i = 0; i < 2; i++)
3818 result[3][i] = result[c1][i];
3819 }
3820
3821 if (!(simubitmap & 0x0c)) {
3822 /* path A RX OK */
3823 for (i = 2; i < 4; i++)
3824 result[3][i] = result[c1][i];
3825 }
3826
3827 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
3828 /* path B RX OK */
3829 for (i = 4; i < 6; i++)
3830 result[3][i] = result[c1][i];
3831 }
3832
3833 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
3834 /* path B RX OK */
3835 for (i = 6; i < 8; i++)
3836 result[3][i] = result[c1][i];
3837 }
3838 }
3839
3840 return false;
3841 }
3842
3843 static void
3844 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
3845 {
3846 int i;
3847
3848 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3849 backup[i] = rtl8xxxu_read8(priv, reg[i]);
3850
3851 backup[i] = rtl8xxxu_read32(priv, reg[i]);
3852 }
3853
3854 static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
3855 const u32 *reg, u32 *backup)
3856 {
3857 int i;
3858
3859 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3860 rtl8xxxu_write8(priv, reg[i], backup[i]);
3861
3862 rtl8xxxu_write32(priv, reg[i], backup[i]);
3863 }
3864
3865 static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3866 u32 *backup, int count)
3867 {
3868 int i;
3869
3870 for (i = 0; i < count; i++)
3871 backup[i] = rtl8xxxu_read32(priv, regs[i]);
3872 }
3873
3874 static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3875 u32 *backup, int count)
3876 {
3877 int i;
3878
3879 for (i = 0; i < count; i++)
3880 rtl8xxxu_write32(priv, regs[i], backup[i]);
3881 }
3882
3883
3884 static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
3885 bool path_a_on)
3886 {
3887 u32 path_on;
3888 int i;
3889
3890 if (priv->tx_paths == 1) {
3891 path_on = priv->fops->adda_1t_path_on;
3892 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init);
3893 } else {
3894 path_on = path_a_on ? priv->fops->adda_2t_path_on_a :
3895 priv->fops->adda_2t_path_on_b;
3896
3897 rtl8xxxu_write32(priv, regs[0], path_on);
3898 }
3899
3900 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3901 rtl8xxxu_write32(priv, regs[i], path_on);
3902 }
3903
3904 static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3905 const u32 *regs, u32 *backup)
3906 {
3907 int i = 0;
3908
3909 rtl8xxxu_write8(priv, regs[i], 0x3f);
3910
3911 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3912 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3913
3914 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3915 }
3916
3917 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3918 {
3919 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3920 int result = 0;
3921
3922 /* path-A IQK setting */
3923 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3924 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3925 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3926
3927 val32 = (priv->rf_paths > 1) ? 0x28160202 :
3928 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3929 0x28160502;
3930 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3931
3932 /* path-B IQK setting */
3933 if (priv->rf_paths > 1) {
3934 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3935 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3936 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3937 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3938 }
3939
3940 /* LO calibration setting */
3941 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3942
3943 /* One shot, path A LOK & IQK */
3944 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3945 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3946
3947 mdelay(1);
3948
3949 /* Check failed */
3950 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3951 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3952 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3953 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3954
3955 if (!(reg_eac & BIT(28)) &&
3956 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3957 ((reg_e9c & 0x03ff0000) != 0x00420000))
3958 result |= 0x01;
3959 else /* If TX not OK, ignore RX */
3960 goto out;
3961
3962 /* If TX is OK, check whether RX is OK */
3963 if (!(reg_eac & BIT(27)) &&
3964 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3965 ((reg_eac & 0x03ff0000) != 0x00360000))
3966 result |= 0x02;
3967 else
3968 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3969 __func__);
3970 out:
3971 return result;
3972 }
3973
3974 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3975 {
3976 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3977 int result = 0;
3978
3979 /* One shot, path B LOK & IQK */
3980 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3981 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3982
3983 mdelay(1);
3984
3985 /* Check failed */
3986 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3987 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3988 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3989 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3990 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3991
3992 if (!(reg_eac & BIT(31)) &&
3993 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3994 ((reg_ebc & 0x03ff0000) != 0x00420000))
3995 result |= 0x01;
3996 else
3997 goto out;
3998
3999 if (!(reg_eac & BIT(30)) &&
4000 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
4001 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
4002 result |= 0x02;
4003 else
4004 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
4005 __func__);
4006 out:
4007 return result;
4008 }
4009
4010 static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv)
4011 {
4012 u32 reg_eac, reg_e94, reg_e9c, path_sel, val32;
4013 int result = 0;
4014
4015 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4016
4017 /*
4018 * Leave IQK mode
4019 */
4020 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4021 val32 &= 0x000000ff;
4022 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4023
4024 /*
4025 * Enable path A PA in TX IQK mode
4026 */
4027 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4028 val32 |= 0x80000;
4029 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4030 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000);
4031 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f);
4032 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87);
4033
4034 /*
4035 * Tx IQK setting
4036 */
4037 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4038 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4039
4040 /* path-A IQK setting */
4041 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
4042 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
4043 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4044 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4045
4046 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea);
4047 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
4048 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4049 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4050
4051 /* LO calibration setting */
4052 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);
4053
4054 /*
4055 * Enter IQK mode
4056 */
4057 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4058 val32 &= 0x000000ff;
4059 val32 |= 0x80800000;
4060 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4061
4062 /*
4063 * The vendor driver indicates the USB module is always using
4064 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4065 */
4066 if (priv->rf_paths > 1)
4067 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4068 else
4069 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4070
4071 /*
4072 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4073 * No trace of this in the 8192eu or 8188eu vendor drivers.
4074 */
4075 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4076
4077 /* One shot, path A LOK & IQK */
4078 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4079 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4080
4081 mdelay(1);
4082
4083 /* Restore Ant Path */
4084 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4085 #ifdef RTL8723BU_BT
4086 /* GNT_BT = 1 */
4087 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4088 #endif
4089
4090 /*
4091 * Leave IQK mode
4092 */
4093 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4094 val32 &= 0x000000ff;
4095 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4096
4097 /* Check failed */
4098 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4099 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4100 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4101
4102 val32 = (reg_e9c >> 16) & 0x3ff;
4103 if (val32 & 0x200)
4104 val32 = 0x400 - val32;
4105
4106 if (!(reg_eac & BIT(28)) &&
4107 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4108 ((reg_e9c & 0x03ff0000) != 0x00420000) &&
4109 ((reg_e94 & 0x03ff0000) < 0x01100000) &&
4110 ((reg_e94 & 0x03ff0000) > 0x00f00000) &&
4111 val32 < 0xf)
4112 result |= 0x01;
4113 else /* If TX not OK, ignore RX */
4114 goto out;
4115
4116 out:
4117 return result;
4118 }
4119
4120 static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
4121 {
4122 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, path_sel, val32;
4123 int result = 0;
4124
4125 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4126
4127 /*
4128 * Leave IQK mode
4129 */
4130 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4131 val32 &= 0x000000ff;
4132 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4133
4134 /*
4135 * Enable path A PA in TX IQK mode
4136 */
4137 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4138 val32 |= 0x80000;
4139 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4140 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4141 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4142 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
4143
4144 /*
4145 * Tx IQK setting
4146 */
4147 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4148 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4149
4150 /* path-A IQK setting */
4151 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
4152 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
4153 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4154 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4155
4156 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0);
4157 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
4158 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4159 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4160
4161 /* LO calibration setting */
4162 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
4163
4164 /*
4165 * Enter IQK mode
4166 */
4167 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4168 val32 &= 0x000000ff;
4169 val32 |= 0x80800000;
4170 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4171
4172 /*
4173 * The vendor driver indicates the USB module is always using
4174 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4175 */
4176 if (priv->rf_paths > 1)
4177 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4178 else
4179 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4180
4181 /*
4182 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4183 * No trace of this in the 8192eu or 8188eu vendor drivers.
4184 */
4185 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4186
4187 /* One shot, path A LOK & IQK */
4188 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4189 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4190
4191 mdelay(1);
4192
4193 /* Restore Ant Path */
4194 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4195 #ifdef RTL8723BU_BT
4196 /* GNT_BT = 1 */
4197 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4198 #endif
4199
4200 /*
4201 * Leave IQK mode
4202 */
4203 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4204 val32 &= 0x000000ff;
4205 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4206
4207 /* Check failed */
4208 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4209 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4210 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4211
4212 val32 = (reg_e9c >> 16) & 0x3ff;
4213 if (val32 & 0x200)
4214 val32 = 0x400 - val32;
4215
4216 if (!(reg_eac & BIT(28)) &&
4217 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4218 ((reg_e9c & 0x03ff0000) != 0x00420000) &&
4219 ((reg_e94 & 0x03ff0000) < 0x01100000) &&
4220 ((reg_e94 & 0x03ff0000) > 0x00f00000) &&
4221 val32 < 0xf)
4222 result |= 0x01;
4223 else /* If TX not OK, ignore RX */
4224 goto out;
4225
4226 val32 = 0x80007c00 | (reg_e94 &0x3ff0000) |
4227 ((reg_e9c & 0x3ff0000) >> 16);
4228 rtl8xxxu_write32(priv, REG_TX_IQK, val32);
4229
4230 /*
4231 * Modify RX IQK mode
4232 */
4233 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4234 val32 &= 0x000000ff;
4235 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4236 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4237 val32 |= 0x80000;
4238 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4239 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4240 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4241 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77);
4242
4243 /*
4244 * PA, PAD setting
4245 */
4246 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0xf80);
4247 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f);
4248
4249 /*
4250 * RX IQK setting
4251 */
4252 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4253
4254 /* path-A IQK setting */
4255 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
4256 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
4257 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4258 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4259
4260 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000);
4261 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f);
4262 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4263 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4264
4265 /* LO calibration setting */
4266 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1);
4267
4268 /*
4269 * Enter IQK mode
4270 */
4271 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4272 val32 &= 0x000000ff;
4273 val32 |= 0x80800000;
4274 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4275
4276 if (priv->rf_paths > 1)
4277 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4278 else
4279 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4280
4281 /*
4282 * Disable BT
4283 */
4284 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4285
4286 /* One shot, path A LOK & IQK */
4287 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4288 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4289
4290 mdelay(1);
4291
4292 /* Restore Ant Path */
4293 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4294 #ifdef RTL8723BU_BT
4295 /* GNT_BT = 1 */
4296 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4297 #endif
4298
4299 /*
4300 * Leave IQK mode
4301 */
4302 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4303 val32 &= 0x000000ff;
4304 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4305
4306 /* Check failed */
4307 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4308 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
4309
4310 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x780);
4311
4312 val32 = (reg_eac >> 16) & 0x3ff;
4313 if (val32 & 0x200)
4314 val32 = 0x400 - val32;
4315
4316 if (!(reg_eac & BIT(27)) &&
4317 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
4318 ((reg_eac & 0x03ff0000) != 0x00360000) &&
4319 ((reg_ea4 & 0x03ff0000) < 0x01100000) &&
4320 ((reg_ea4 & 0x03ff0000) > 0x00f00000) &&
4321 val32 < 0xf)
4322 result |= 0x02;
4323 else /* If TX not OK, ignore RX */
4324 goto out;
4325 out:
4326 return result;
4327 }
4328
4329 #ifdef RTL8723BU_PATH_B
4330 static int rtl8723bu_iqk_path_b(struct rtl8xxxu_priv *priv)
4331 {
4332 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, path_sel;
4333 int result = 0;
4334
4335 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4336
4337 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4338 val32 &= 0x000000ff;
4339 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4340
4341 /* One shot, path B LOK & IQK */
4342 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
4343 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
4344
4345 mdelay(1);
4346
4347 /* Check failed */
4348 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4349 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4350 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4351 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4352 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4353
4354 if (!(reg_eac & BIT(31)) &&
4355 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
4356 ((reg_ebc & 0x03ff0000) != 0x00420000))
4357 result |= 0x01;
4358 else
4359 goto out;
4360
4361 if (!(reg_eac & BIT(30)) &&
4362 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
4363 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
4364 result |= 0x02;
4365 else
4366 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
4367 __func__);
4368 out:
4369 return result;
4370 }
4371 #endif
4372
4373 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
4374 int result[][8], int t)
4375 {
4376 struct device *dev = &priv->udev->dev;
4377 u32 i, val32;
4378 int path_a_ok, path_b_ok;
4379 int retry = 2;
4380 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
4381 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
4382 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
4383 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
4384 REG_TX_OFDM_BBON, REG_TX_TO_RX,
4385 REG_TX_TO_TX, REG_RX_CCK,
4386 REG_RX_OFDM, REG_RX_WAIT_RIFS,
4387 REG_RX_TO_RX, REG_STANDBY,
4388 REG_SLEEP, REG_PMPD_ANAEN
4389 };
4390 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
4391 REG_TXPAUSE, REG_BEACON_CTRL,
4392 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
4393 };
4394 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
4395 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
4396 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
4397 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
4398 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
4399 };
4400
4401 /*
4402 * Note: IQ calibration must be performed after loading
4403 * PHY_REG.txt , and radio_a, radio_b.txt
4404 */
4405
4406 if (t == 0) {
4407 /* Save ADDA parameters, turn Path A ADDA on */
4408 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
4409 RTL8XXXU_ADDA_REGS);
4410 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4411 rtl8xxxu_save_regs(priv, iqk_bb_regs,
4412 priv->bb_backup, RTL8XXXU_BB_REGS);
4413 }
4414
4415 rtl8xxxu_path_adda_on(priv, adda_regs, true);
4416
4417 if (t == 0) {
4418 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
4419 if (val32 & FPGA0_HSSI_PARM1_PI)
4420 priv->pi_enabled = 1;
4421 }
4422
4423 if (!priv->pi_enabled) {
4424 /* Switch BB to PI mode to do IQ Calibration. */
4425 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
4426 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
4427 }
4428
4429 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4430 val32 &= ~FPGA_RF_MODE_CCK;
4431 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4432
4433 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
4434 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
4435 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
4436
4437 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
4438 val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
4439 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4440
4441 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
4442 val32 &= ~BIT(10);
4443 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
4444 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
4445 val32 &= ~BIT(10);
4446 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
4447
4448 if (priv->tx_paths > 1) {
4449 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
4450 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
4451 }
4452
4453 /* MAC settings */
4454 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
4455
4456 /* Page B init */
4457 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
4458
4459 if (priv->tx_paths > 1)
4460 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
4461
4462 /* IQ calibration setting */
4463 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
4464 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4465 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4466
4467 for (i = 0; i < retry; i++) {
4468 path_a_ok = rtl8xxxu_iqk_path_a(priv);
4469 if (path_a_ok == 0x03) {
4470 val32 = rtl8xxxu_read32(priv,
4471 REG_TX_POWER_BEFORE_IQK_A);
4472 result[t][0] = (val32 >> 16) & 0x3ff;
4473 val32 = rtl8xxxu_read32(priv,
4474 REG_TX_POWER_AFTER_IQK_A);
4475 result[t][1] = (val32 >> 16) & 0x3ff;
4476 val32 = rtl8xxxu_read32(priv,
4477 REG_RX_POWER_BEFORE_IQK_A_2);
4478 result[t][2] = (val32 >> 16) & 0x3ff;
4479 val32 = rtl8xxxu_read32(priv,
4480 REG_RX_POWER_AFTER_IQK_A_2);
4481 result[t][3] = (val32 >> 16) & 0x3ff;
4482 break;
4483 } else if (i == (retry - 1) && path_a_ok == 0x01) {
4484 /* TX IQK OK */
4485 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
4486 __func__);
4487
4488 val32 = rtl8xxxu_read32(priv,
4489 REG_TX_POWER_BEFORE_IQK_A);
4490 result[t][0] = (val32 >> 16) & 0x3ff;
4491 val32 = rtl8xxxu_read32(priv,
4492 REG_TX_POWER_AFTER_IQK_A);
4493 result[t][1] = (val32 >> 16) & 0x3ff;
4494 }
4495 }
4496
4497 if (!path_a_ok)
4498 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
4499
4500 if (priv->tx_paths > 1) {
4501 /*
4502 * Path A into standby
4503 */
4504 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
4505 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
4506 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
4507
4508 /* Turn Path B ADDA on */
4509 rtl8xxxu_path_adda_on(priv, adda_regs, false);
4510
4511 for (i = 0; i < retry; i++) {
4512 path_b_ok = rtl8xxxu_iqk_path_b(priv);
4513 if (path_b_ok == 0x03) {
4514 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4515 result[t][4] = (val32 >> 16) & 0x3ff;
4516 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4517 result[t][5] = (val32 >> 16) & 0x3ff;
4518 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4519 result[t][6] = (val32 >> 16) & 0x3ff;
4520 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4521 result[t][7] = (val32 >> 16) & 0x3ff;
4522 break;
4523 } else if (i == (retry - 1) && path_b_ok == 0x01) {
4524 /* TX IQK OK */
4525 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4526 result[t][4] = (val32 >> 16) & 0x3ff;
4527 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4528 result[t][5] = (val32 >> 16) & 0x3ff;
4529 }
4530 }
4531
4532 if (!path_b_ok)
4533 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
4534 }
4535
4536 /* Back to BB mode, load original value */
4537 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
4538
4539 if (t) {
4540 if (!priv->pi_enabled) {
4541 /*
4542 * Switch back BB to SI mode after finishing
4543 * IQ Calibration
4544 */
4545 val32 = 0x01000000;
4546 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
4547 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
4548 }
4549
4550 /* Reload ADDA power saving parameters */
4551 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
4552 RTL8XXXU_ADDA_REGS);
4553
4554 /* Reload MAC parameters */
4555 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4556
4557 /* Reload BB parameters */
4558 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
4559 priv->bb_backup, RTL8XXXU_BB_REGS);
4560
4561 /* Restore RX initial gain */
4562 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
4563
4564 if (priv->tx_paths > 1) {
4565 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
4566 0x00032ed3);
4567 }
4568
4569 /* Load 0xe30 IQC default value */
4570 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
4571 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
4572 }
4573 }
4574
4575 static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
4576 int result[][8], int t)
4577 {
4578 struct device *dev = &priv->udev->dev;
4579 u32 i, val32;
4580 int path_a_ok /*, path_b_ok */;
4581 int retry = 2;
4582 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
4583 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
4584 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
4585 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
4586 REG_TX_OFDM_BBON, REG_TX_TO_RX,
4587 REG_TX_TO_TX, REG_RX_CCK,
4588 REG_RX_OFDM, REG_RX_WAIT_RIFS,
4589 REG_RX_TO_RX, REG_STANDBY,
4590 REG_SLEEP, REG_PMPD_ANAEN
4591 };
4592 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
4593 REG_TXPAUSE, REG_BEACON_CTRL,
4594 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
4595 };
4596 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
4597 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
4598 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
4599 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
4600 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
4601 };
4602 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff;
4603 u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff;
4604
4605 /*
4606 * Note: IQ calibration must be performed after loading
4607 * PHY_REG.txt , and radio_a, radio_b.txt
4608 */
4609
4610 if (t == 0) {
4611 /* Save ADDA parameters, turn Path A ADDA on */
4612 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
4613 RTL8XXXU_ADDA_REGS);
4614 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4615 rtl8xxxu_save_regs(priv, iqk_bb_regs,
4616 priv->bb_backup, RTL8XXXU_BB_REGS);
4617 }
4618
4619 rtl8xxxu_path_adda_on(priv, adda_regs, true);
4620
4621 /* MAC settings */
4622 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
4623
4624 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
4625 val32 |= 0x0f000000;
4626 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
4627
4628 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
4629 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
4630 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
4631
4632 #ifdef RTL8723BU_PATH_B
4633 /* Set RF mode to standby Path B */
4634 if (priv->tx_paths > 1)
4635 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x10000);
4636 #endif
4637
4638 #if 0
4639 /* Page B init */
4640 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x0f600000);
4641
4642 if (priv->tx_paths > 1)
4643 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x0f600000);
4644 #endif
4645
4646 /*
4647 * RX IQ calibration setting for 8723B D cut large current issue
4648 * when leaving IPS
4649 */
4650 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4651 val32 &= 0x000000ff;
4652 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4653
4654 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4655 val32 |= 0x80000;
4656 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4657
4658 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4659 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4660 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
4661
4662 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
4663 val32 |= 0x20;
4664 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
4665
4666 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd);
4667
4668 for (i = 0; i < retry; i++) {
4669 path_a_ok = rtl8723bu_iqk_path_a(priv);
4670 if (path_a_ok == 0x01) {
4671 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4672 val32 &= 0x000000ff;
4673 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4674
4675 #if 0 /* Only needed in restore case, we may need this when going to suspend */
4676 priv->RFCalibrateInfo.TxLOK[RF_A] =
4677 rtl8xxxu_read_rfreg(priv, RF_A,
4678 RF6052_REG_TXM_IDAC);
4679 #endif
4680
4681 val32 = rtl8xxxu_read32(priv,
4682 REG_TX_POWER_BEFORE_IQK_A);
4683 result[t][0] = (val32 >> 16) & 0x3ff;
4684 val32 = rtl8xxxu_read32(priv,
4685 REG_TX_POWER_AFTER_IQK_A);
4686 result[t][1] = (val32 >> 16) & 0x3ff;
4687
4688 break;
4689 }
4690 }
4691
4692 if (!path_a_ok)
4693 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);
4694
4695 for (i = 0; i < retry; i++) {
4696 path_a_ok = rtl8723bu_rx_iqk_path_a(priv);
4697 if (path_a_ok == 0x03) {
4698 val32 = rtl8xxxu_read32(priv,
4699 REG_RX_POWER_BEFORE_IQK_A_2);
4700 result[t][2] = (val32 >> 16) & 0x3ff;
4701 val32 = rtl8xxxu_read32(priv,
4702 REG_RX_POWER_AFTER_IQK_A_2);
4703 result[t][3] = (val32 >> 16) & 0x3ff;
4704
4705 break;
4706 }
4707 }
4708
4709 if (!path_a_ok)
4710 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);
4711
4712 if (priv->tx_paths > 1) {
4713 #if 1
4714 dev_warn(dev, "%s: Path B not supported\n", __func__);
4715 #else
4716
4717 /*
4718 * Path A into standby
4719 */
4720 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4721 val32 &= 0x000000ff;
4722 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4723 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000);
4724
4725 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4726 val32 &= 0x000000ff;
4727 val32 |= 0x80800000;
4728 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4729
4730 /* Turn Path B ADDA on */
4731 rtl8xxxu_path_adda_on(priv, adda_regs, false);
4732
4733 for (i = 0; i < retry; i++) {
4734 path_b_ok = rtl8xxxu_iqk_path_b(priv);
4735 if (path_b_ok == 0x03) {
4736 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4737 result[t][4] = (val32 >> 16) & 0x3ff;
4738 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4739 result[t][5] = (val32 >> 16) & 0x3ff;
4740 break;
4741 }
4742 }
4743
4744 if (!path_b_ok)
4745 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
4746
4747 for (i = 0; i < retry; i++) {
4748 path_b_ok = rtl8723bu_rx_iqk_path_b(priv);
4749 if (path_a_ok == 0x03) {
4750 val32 = rtl8xxxu_read32(priv,
4751 REG_RX_POWER_BEFORE_IQK_B_2);
4752 result[t][6] = (val32 >> 16) & 0x3ff;
4753 val32 = rtl8xxxu_read32(priv,
4754 REG_RX_POWER_AFTER_IQK_B_2);
4755 result[t][7] = (val32 >> 16) & 0x3ff;
4756 break;
4757 }
4758 }
4759
4760 if (!path_b_ok)
4761 dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__);
4762 #endif
4763 }
4764
4765 /* Back to BB mode, load original value */
4766 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4767 val32 &= 0x000000ff;
4768 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4769
4770 if (t) {
4771 /* Reload ADDA power saving parameters */
4772 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
4773 RTL8XXXU_ADDA_REGS);
4774
4775 /* Reload MAC parameters */
4776 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4777
4778 /* Reload BB parameters */
4779 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
4780 priv->bb_backup, RTL8XXXU_BB_REGS);
4781
4782 /* Restore RX initial gain */
4783 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
4784 val32 &= 0xffffff00;
4785 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50);
4786 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc);
4787
4788 if (priv->tx_paths > 1) {
4789 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);
4790 val32 &= 0xffffff00;
4791 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
4792 val32 | 0x50);
4793 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
4794 val32 | xb_agc);
4795 }
4796
4797 /* Load 0xe30 IQC default value */
4798 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
4799 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
4800 }
4801 }
4802
4803 static void rtl8xxxu_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start)
4804 {
4805 struct h2c_cmd h2c;
4806
4807 if (priv->fops->mbox_ext_width < 4)
4808 return;
4809
4810 memset(&h2c, 0, sizeof(struct h2c_cmd));
4811 h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION;
4812 h2c.bt_wlan_calibration.data = start;
4813
4814 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration));
4815 }
4816
4817 static void rtl8723au_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
4818 {
4819 struct device *dev = &priv->udev->dev;
4820 int result[4][8]; /* last is final result */
4821 int i, candidate;
4822 bool path_a_ok, path_b_ok;
4823 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
4824 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4825 s32 reg_tmp = 0;
4826 bool simu;
4827
4828 rtl8xxxu_prepare_calibrate(priv, 1);
4829
4830 memset(result, 0, sizeof(result));
4831 candidate = -1;
4832
4833 path_a_ok = false;
4834 path_b_ok = false;
4835
4836 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4837
4838 for (i = 0; i < 3; i++) {
4839 rtl8xxxu_phy_iqcalibrate(priv, result, i);
4840
4841 if (i == 1) {
4842 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
4843 if (simu) {
4844 candidate = 0;
4845 break;
4846 }
4847 }
4848
4849 if (i == 2) {
4850 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
4851 if (simu) {
4852 candidate = 0;
4853 break;
4854 }
4855
4856 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
4857 if (simu) {
4858 candidate = 1;
4859 } else {
4860 for (i = 0; i < 8; i++)
4861 reg_tmp += result[3][i];
4862
4863 if (reg_tmp)
4864 candidate = 3;
4865 else
4866 candidate = -1;
4867 }
4868 }
4869 }
4870
4871 for (i = 0; i < 4; i++) {
4872 reg_e94 = result[i][0];
4873 reg_e9c = result[i][1];
4874 reg_ea4 = result[i][2];
4875 reg_eac = result[i][3];
4876 reg_eb4 = result[i][4];
4877 reg_ebc = result[i][5];
4878 reg_ec4 = result[i][6];
4879 reg_ecc = result[i][7];
4880 }
4881
4882 if (candidate >= 0) {
4883 reg_e94 = result[candidate][0];
4884 priv->rege94 = reg_e94;
4885 reg_e9c = result[candidate][1];
4886 priv->rege9c = reg_e9c;
4887 reg_ea4 = result[candidate][2];
4888 reg_eac = result[candidate][3];
4889 reg_eb4 = result[candidate][4];
4890 priv->regeb4 = reg_eb4;
4891 reg_ebc = result[candidate][5];
4892 priv->regebc = reg_ebc;
4893 reg_ec4 = result[candidate][6];
4894 reg_ecc = result[candidate][7];
4895 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
4896 dev_dbg(dev,
4897 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
4898 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
4899 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
4900 path_a_ok = true;
4901 path_b_ok = true;
4902 } else {
4903 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
4904 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
4905 }
4906
4907 if (reg_e94 && candidate >= 0)
4908 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
4909 candidate, (reg_ea4 == 0));
4910
4911 if (priv->tx_paths > 1 && reg_eb4)
4912 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
4913 candidate, (reg_ec4 == 0));
4914
4915 rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
4916 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
4917
4918 rtl8xxxu_prepare_calibrate(priv, 0);
4919 }
4920
4921 static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
4922 {
4923 struct device *dev = &priv->udev->dev;
4924 int result[4][8]; /* last is final result */
4925 int i, candidate;
4926 bool path_a_ok, path_b_ok;
4927 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
4928 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4929 u32 val32, bt_control;
4930 s32 reg_tmp = 0;
4931 bool simu;
4932
4933 rtl8xxxu_prepare_calibrate(priv, 1);
4934
4935 memset(result, 0, sizeof(result));
4936 candidate = -1;
4937
4938 path_a_ok = false;
4939 path_b_ok = false;
4940
4941 bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU);
4942
4943 for (i = 0; i < 3; i++) {
4944 rtl8723bu_phy_iqcalibrate(priv, result, i);
4945
4946 if (i == 1) {
4947 simu = rtl8723bu_simularity_compare(priv, result, 0, 1);
4948 if (simu) {
4949 candidate = 0;
4950 break;
4951 }
4952 }
4953
4954 if (i == 2) {
4955 simu = rtl8723bu_simularity_compare(priv, result, 0, 2);
4956 if (simu) {
4957 candidate = 0;
4958 break;
4959 }
4960
4961 simu = rtl8723bu_simularity_compare(priv, result, 1, 2);
4962 if (simu) {
4963 candidate = 1;
4964 } else {
4965 for (i = 0; i < 8; i++)
4966 reg_tmp += result[3][i];
4967
4968 if (reg_tmp)
4969 candidate = 3;
4970 else
4971 candidate = -1;
4972 }
4973 }
4974 }
4975
4976 for (i = 0; i < 4; i++) {
4977 reg_e94 = result[i][0];
4978 reg_e9c = result[i][1];
4979 reg_ea4 = result[i][2];
4980 reg_eac = result[i][3];
4981 reg_eb4 = result[i][4];
4982 reg_ebc = result[i][5];
4983 reg_ec4 = result[i][6];
4984 reg_ecc = result[i][7];
4985 }
4986
4987 if (candidate >= 0) {
4988 reg_e94 = result[candidate][0];
4989 priv->rege94 = reg_e94;
4990 reg_e9c = result[candidate][1];
4991 priv->rege9c = reg_e9c;
4992 reg_ea4 = result[candidate][2];
4993 reg_eac = result[candidate][3];
4994 reg_eb4 = result[candidate][4];
4995 priv->regeb4 = reg_eb4;
4996 reg_ebc = result[candidate][5];
4997 priv->regebc = reg_ebc;
4998 reg_ec4 = result[candidate][6];
4999 reg_ecc = result[candidate][7];
5000 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
5001 dev_dbg(dev,
5002 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
5003 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
5004 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
5005 path_a_ok = true;
5006 path_b_ok = true;
5007 } else {
5008 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
5009 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
5010 }
5011
5012 if (reg_e94 && candidate >= 0)
5013 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
5014 candidate, (reg_ea4 == 0));
5015
5016 if (priv->tx_paths > 1 && reg_eb4)
5017 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
5018 candidate, (reg_ec4 == 0));
5019
5020 rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
5021 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
5022
5023 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control);
5024
5025 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
5026 val32 |= 0x80000;
5027 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
5028 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000);
5029 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
5030 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177);
5031 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
5032 val32 |= 0x20;
5033 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
5034 rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd);
5035
5036 if (priv->rf_paths > 1) {
5037 dev_dbg(dev, "%s: beware 2T not yet supported\n", __func__);
5038 #ifdef RTL8723BU_PATH_B
5039 if (RF_Path == 0x0) //S1
5040 ODM_SetIQCbyRFpath(pDM_Odm, 0);
5041 else //S0
5042 ODM_SetIQCbyRFpath(pDM_Odm, 1);
5043 #endif
5044 }
5045 rtl8xxxu_prepare_calibrate(priv, 0);
5046 }
5047
5048 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
5049 {
5050 u32 val32;
5051 u32 rf_amode, rf_bmode = 0, lstf;
5052
5053 /* Check continuous TX and Packet TX */
5054 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
5055
5056 if (lstf & OFDM_LSTF_MASK) {
5057 /* Disable all continuous TX */
5058 val32 = lstf & ~OFDM_LSTF_MASK;
5059 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
5060
5061 /* Read original RF mode Path A */
5062 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
5063
5064 /* Set RF mode to standby Path A */
5065 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
5066 (rf_amode & 0x8ffff) | 0x10000);
5067
5068 /* Path-B */
5069 if (priv->tx_paths > 1) {
5070 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
5071 RF6052_REG_AC);
5072
5073 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
5074 (rf_bmode & 0x8ffff) | 0x10000);
5075 }
5076 } else {
5077 /* Deal with Packet TX case */
5078 /* block all queues */
5079 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5080 }
5081
5082 /* Start LC calibration */
5083 if (priv->fops->has_s0s1)
5084 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0);
5085 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
5086 val32 |= 0x08000;
5087 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
5088
5089 msleep(100);
5090
5091 if (priv->fops->has_s0s1)
5092 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0);
5093
5094 /* Restore original parameters */
5095 if (lstf & OFDM_LSTF_MASK) {
5096 /* Path-A */
5097 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
5098 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
5099
5100 /* Path-B */
5101 if (priv->tx_paths > 1)
5102 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
5103 rf_bmode);
5104 } else /* Deal with Packet TX case */
5105 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
5106 }
5107
5108 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
5109 {
5110 int i;
5111 u16 reg;
5112
5113 reg = REG_MACID;
5114
5115 for (i = 0; i < ETH_ALEN; i++)
5116 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
5117
5118 return 0;
5119 }
5120
5121 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
5122 {
5123 int i;
5124 u16 reg;
5125
5126 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
5127
5128 reg = REG_BSSID;
5129
5130 for (i = 0; i < ETH_ALEN; i++)
5131 rtl8xxxu_write8(priv, reg + i, bssid[i]);
5132
5133 return 0;
5134 }
5135
5136 static void
5137 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
5138 {
5139 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
5140 u8 max_agg = 0xf;
5141 int i;
5142
5143 ampdu_factor = 1 << (ampdu_factor + 2);
5144 if (ampdu_factor > max_agg)
5145 ampdu_factor = max_agg;
5146
5147 for (i = 0; i < 4; i++) {
5148 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
5149 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
5150
5151 if ((vals[i] & 0x0f) > ampdu_factor)
5152 vals[i] = (vals[i] & 0xf0) | ampdu_factor;
5153
5154 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
5155 }
5156 }
5157
5158 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
5159 {
5160 u8 val8;
5161
5162 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
5163 val8 &= 0xf8;
5164 val8 |= density;
5165 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
5166 }
5167
5168 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
5169 {
5170 u8 val8;
5171 int count, ret;
5172
5173 /* Start of rtl8723AU_card_enable_flow */
5174 /* Act to Cardemu sequence*/
5175 /* Turn off RF */
5176 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
5177
5178 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
5179 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
5180 val8 &= ~LEDCFG2_DPDT_SELECT;
5181 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
5182
5183 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
5184 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5185 val8 |= BIT(1);
5186 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5187
5188 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5189 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5190 if ((val8 & BIT(1)) == 0)
5191 break;
5192 udelay(10);
5193 }
5194
5195 if (!count) {
5196 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
5197 __func__);
5198 ret = -EBUSY;
5199 goto exit;
5200 }
5201
5202 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
5203 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5204 val8 |= SYS_ISO_ANALOG_IPS;
5205 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5206
5207 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
5208 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5209 val8 &= ~LDOA15_ENABLE;
5210 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5211
5212 exit:
5213 return ret;
5214 }
5215
5216 static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
5217 {
5218 u8 val8;
5219 u8 val32;
5220 int count, ret;
5221
5222 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5223
5224 /*
5225 * Poll - wait for RX packet to complete
5226 */
5227 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5228 val32 = rtl8xxxu_read32(priv, 0x5f8);
5229 if (!val32)
5230 break;
5231 udelay(10);
5232 }
5233
5234 if (!count) {
5235 dev_warn(&priv->udev->dev,
5236 "%s: RX poll timed out (0x05f8)\n", __func__);
5237 ret = -EBUSY;
5238 goto exit;
5239 }
5240
5241 /* Disable CCK and OFDM, clock gated */
5242 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
5243 val8 &= ~SYS_FUNC_BBRSTB;
5244 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
5245
5246 udelay(2);
5247
5248 /* Reset baseband */
5249 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
5250 val8 &= ~SYS_FUNC_BB_GLB_RSTN;
5251 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
5252
5253 /* Reset MAC TRX */
5254 val8 = rtl8xxxu_read8(priv, REG_CR);
5255 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
5256 rtl8xxxu_write8(priv, REG_CR, val8);
5257
5258 /* Reset MAC TRX */
5259 val8 = rtl8xxxu_read8(priv, REG_CR + 1);
5260 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
5261 rtl8xxxu_write8(priv, REG_CR + 1, val8);
5262
5263 /* Respond TX OK to scheduler */
5264 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
5265 val8 |= DUAL_TSF_TX_OK;
5266 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
5267
5268 exit:
5269 return ret;
5270 }
5271
5272 static void rtl8723a_disabled_to_emu(struct rtl8xxxu_priv *priv)
5273 {
5274 u8 val8;
5275
5276 /* Clear suspend enable and power down enable*/
5277 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5278 val8 &= ~(BIT(3) | BIT(7));
5279 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5280
5281 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
5282 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
5283 val8 &= ~BIT(0);
5284 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
5285
5286 /* 0x04[12:11] = 11 enable WL suspend*/
5287 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5288 val8 &= ~(BIT(3) | BIT(4));
5289 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5290 }
5291
5292 static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv)
5293 {
5294 u8 val8;
5295
5296 /* Clear suspend enable and power down enable*/
5297 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5298 val8 &= ~(BIT(3) | BIT(4));
5299 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5300 }
5301
5302 static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv)
5303 {
5304 u8 val8;
5305 u32 val32;
5306 int count, ret = 0;
5307
5308 /* disable HWPDN 0x04[15]=0*/
5309 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5310 val8 &= ~BIT(7);
5311 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5312
5313 /* disable SW LPS 0x04[10]= 0 */
5314 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5315 val8 &= ~BIT(2);
5316 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5317
5318 /* disable WL suspend*/
5319 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5320 val8 &= ~(BIT(3) | BIT(4));
5321 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5322
5323 /* wait till 0x04[17] = 1 power ready*/
5324 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5325 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5326 if (val32 & BIT(17))
5327 break;
5328
5329 udelay(10);
5330 }
5331
5332 if (!count) {
5333 ret = -EBUSY;
5334 goto exit;
5335 }
5336
5337 /* We should be able to optimize the following three entries into one */
5338
5339 /* release WLON reset 0x04[16]= 1*/
5340 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5341 val8 |= BIT(0);
5342 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5343
5344 /* set, then poll until 0 */
5345 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5346 val32 |= APS_FSMCO_MAC_ENABLE;
5347 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5348
5349 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5350 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5351 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5352 ret = 0;
5353 break;
5354 }
5355 udelay(10);
5356 }
5357
5358 if (!count) {
5359 ret = -EBUSY;
5360 goto exit;
5361 }
5362
5363 exit:
5364 return ret;
5365 }
5366
5367 static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv)
5368 {
5369 u8 val8;
5370 u32 val32;
5371 int count, ret = 0;
5372
5373 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
5374 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5375 val8 |= LDOA15_ENABLE;
5376 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5377
5378 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
5379 val8 = rtl8xxxu_read8(priv, 0x0067);
5380 val8 &= ~BIT(4);
5381 rtl8xxxu_write8(priv, 0x0067, val8);
5382
5383 mdelay(1);
5384
5385 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
5386 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5387 val8 &= ~SYS_ISO_ANALOG_IPS;
5388 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5389
5390 /* disable SW LPS 0x04[10]= 0 */
5391 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5392 val8 &= ~BIT(2);
5393 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5394
5395 /* wait till 0x04[17] = 1 power ready*/
5396 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5397 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5398 if (val32 & BIT(17))
5399 break;
5400
5401 udelay(10);
5402 }
5403
5404 if (!count) {
5405 ret = -EBUSY;
5406 goto exit;
5407 }
5408
5409 /* We should be able to optimize the following three entries into one */
5410
5411 /* release WLON reset 0x04[16]= 1*/
5412 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5413 val8 |= BIT(0);
5414 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5415
5416 /* disable HWPDN 0x04[15]= 0*/
5417 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5418 val8 &= ~BIT(7);
5419 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5420
5421 /* disable WL suspend*/
5422 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5423 val8 &= ~(BIT(3) | BIT(4));
5424 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5425
5426 /* set, then poll until 0 */
5427 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5428 val32 |= APS_FSMCO_MAC_ENABLE;
5429 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5430
5431 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5432 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5433 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5434 ret = 0;
5435 break;
5436 }
5437 udelay(10);
5438 }
5439
5440 if (!count) {
5441 ret = -EBUSY;
5442 goto exit;
5443 }
5444
5445 /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
5446 /*
5447 * Note: Vendor driver actually clears this bit, despite the
5448 * documentation claims it's being set!
5449 */
5450 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
5451 val8 |= LEDCFG2_DPDT_SELECT;
5452 val8 &= ~LEDCFG2_DPDT_SELECT;
5453 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
5454
5455 exit:
5456 return ret;
5457 }
5458
5459 static int rtl8723b_emu_to_active(struct rtl8xxxu_priv *priv)
5460 {
5461 u8 val8;
5462 u32 val32;
5463 int count, ret = 0;
5464
5465 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface */
5466 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5467 val8 |= LDOA15_ENABLE;
5468 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5469
5470 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
5471 val8 = rtl8xxxu_read8(priv, 0x0067);
5472 val8 &= ~BIT(4);
5473 rtl8xxxu_write8(priv, 0x0067, val8);
5474
5475 mdelay(1);
5476
5477 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
5478 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5479 val8 &= ~SYS_ISO_ANALOG_IPS;
5480 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5481
5482 /* Disable SW LPS 0x04[10]= 0 */
5483 val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
5484 val32 &= ~APS_FSMCO_SW_LPS;
5485 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5486
5487 /* Wait until 0x04[17] = 1 power ready */
5488 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5489 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5490 if (val32 & BIT(17))
5491 break;
5492
5493 udelay(10);
5494 }
5495
5496 if (!count) {
5497 ret = -EBUSY;
5498 goto exit;
5499 }
5500
5501 /* We should be able to optimize the following three entries into one */
5502
5503 /* Release WLON reset 0x04[16]= 1*/
5504 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5505 val32 |= APS_FSMCO_WLON_RESET;
5506 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5507
5508 /* Disable HWPDN 0x04[15]= 0*/
5509 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5510 val32 &= ~APS_FSMCO_HW_POWERDOWN;
5511 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5512
5513 /* Disable WL suspend*/
5514 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5515 val32 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE);
5516 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5517
5518 /* Set, then poll until 0 */
5519 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5520 val32 |= APS_FSMCO_MAC_ENABLE;
5521 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5522
5523 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5524 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5525 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5526 ret = 0;
5527 break;
5528 }
5529 udelay(10);
5530 }
5531
5532 if (!count) {
5533 ret = -EBUSY;
5534 goto exit;
5535 }
5536
5537 /* Enable WL control XTAL setting */
5538 val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
5539 val8 |= AFE_MISC_WL_XTAL_CTRL;
5540 rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
5541
5542 /* Enable falling edge triggering interrupt */
5543 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 1);
5544 val8 |= BIT(1);
5545 rtl8xxxu_write8(priv, REG_GPIO_INTM + 1, val8);
5546
5547 /* Enable GPIO9 interrupt mode */
5548 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2 + 1);
5549 val8 |= BIT(1);
5550 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2 + 1, val8);
5551
5552 /* Enable GPIO9 input mode */
5553 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2);
5554 val8 &= ~BIT(1);
5555 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2, val8);
5556
5557 /* Enable HSISR GPIO[C:0] interrupt */
5558 val8 = rtl8xxxu_read8(priv, REG_HSIMR);
5559 val8 |= BIT(0);
5560 rtl8xxxu_write8(priv, REG_HSIMR, val8);
5561
5562 /* Enable HSISR GPIO9 interrupt */
5563 val8 = rtl8xxxu_read8(priv, REG_HSIMR + 2);
5564 val8 |= BIT(1);
5565 rtl8xxxu_write8(priv, REG_HSIMR + 2, val8);
5566
5567 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL);
5568 val8 |= MULTI_WIFI_HW_ROF_EN;
5569 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL, val8);
5570
5571 /* For GPIO9 internal pull high setting BIT(14) */
5572 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL + 1);
5573 val8 |= BIT(6);
5574 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL + 1, val8);
5575
5576 exit:
5577 return ret;
5578 }
5579
5580 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
5581 {
5582 u8 val8;
5583
5584 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
5585 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
5586
5587 /* 0x04[12:11] = 01 enable WL suspend */
5588 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5589 val8 &= ~BIT(4);
5590 val8 |= BIT(3);
5591 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5592
5593 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5594 val8 |= BIT(7);
5595 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5596
5597 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
5598 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
5599 val8 |= BIT(0);
5600 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
5601
5602 return 0;
5603 }
5604
5605 static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
5606 {
5607 u8 val8;
5608 u16 val16;
5609 u32 val32;
5610 int ret;
5611
5612 /*
5613 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5614 */
5615 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
5616
5617 rtl8723a_disabled_to_emu(priv);
5618
5619 ret = rtl8723a_emu_to_active(priv);
5620 if (ret)
5621 goto exit;
5622
5623 /*
5624 * 0x0004[19] = 1, reset 8051
5625 */
5626 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5627 val8 |= BIT(3);
5628 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5629
5630 /*
5631 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5632 * Set CR bit10 to enable 32k calibration.
5633 */
5634 val16 = rtl8xxxu_read16(priv, REG_CR);
5635 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5636 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5637 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5638 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5639 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5640 rtl8xxxu_write16(priv, REG_CR, val16);
5641
5642 /* For EFuse PG */
5643 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
5644 val32 &= ~(BIT(28) | BIT(29) | BIT(30));
5645 val32 |= (0x06 << 28);
5646 rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
5647 exit:
5648 return ret;
5649 }
5650
5651 static int rtl8723bu_power_on(struct rtl8xxxu_priv *priv)
5652 {
5653 u8 val8;
5654 u16 val16;
5655 u32 val32;
5656 int ret;
5657
5658 rtl8723a_disabled_to_emu(priv);
5659
5660 ret = rtl8723b_emu_to_active(priv);
5661 if (ret)
5662 goto exit;
5663
5664 /*
5665 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5666 * Set CR bit10 to enable 32k calibration.
5667 */
5668 val16 = rtl8xxxu_read16(priv, REG_CR);
5669 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5670 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5671 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5672 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5673 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5674 rtl8xxxu_write16(priv, REG_CR, val16);
5675
5676 /*
5677 * BT coexist power on settings. This is identical for 1 and 2
5678 * antenna parts.
5679 */
5680 rtl8xxxu_write8(priv, REG_PAD_CTRL1 + 3, 0x20);
5681
5682 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
5683 val16 |= SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN;
5684 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
5685
5686 rtl8xxxu_write8(priv, REG_BT_CONTROL_8723BU + 1, 0x18);
5687 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
5688 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
5689 /* Antenna inverse */
5690 rtl8xxxu_write8(priv, 0xfe08, 0x01);
5691
5692 val16 = rtl8xxxu_read16(priv, REG_PWR_DATA);
5693 val16 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
5694 rtl8xxxu_write16(priv, REG_PWR_DATA, val16);
5695
5696 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
5697 val32 |= LEDCFG0_DPDT_SELECT;
5698 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
5699
5700 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
5701 val8 &= ~PAD_CTRL1_SW_DPDT_SEL_DATA;
5702 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
5703 exit:
5704 return ret;
5705 }
5706
5707 #ifdef CONFIG_RTL8XXXU_UNTESTED
5708
5709 static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
5710 {
5711 u8 val8;
5712 u16 val16;
5713 u32 val32;
5714 int i;
5715
5716 for (i = 100; i; i--) {
5717 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
5718 if (val8 & APS_FSMCO_PFM_ALDN)
5719 break;
5720 }
5721
5722 if (!i) {
5723 pr_info("%s: Poll failed\n", __func__);
5724 return -ENODEV;
5725 }
5726
5727 /*
5728 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5729 */
5730 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
5731 rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
5732 udelay(100);
5733
5734 val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
5735 if (!(val8 & LDOV12D_ENABLE)) {
5736 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
5737 val8 |= LDOV12D_ENABLE;
5738 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
5739
5740 udelay(100);
5741
5742 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5743 val8 &= ~SYS_ISO_MD2PP;
5744 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5745 }
5746
5747 /*
5748 * Auto enable WLAN
5749 */
5750 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
5751 val16 |= APS_FSMCO_MAC_ENABLE;
5752 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
5753
5754 for (i = 1000; i; i--) {
5755 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
5756 if (!(val16 & APS_FSMCO_MAC_ENABLE))
5757 break;
5758 }
5759 if (!i) {
5760 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
5761 return -EBUSY;
5762 }
5763
5764 /*
5765 * Enable radio, GPIO, LED
5766 */
5767 val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
5768 APS_FSMCO_PFM_ALDN;
5769 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
5770
5771 /*
5772 * Release RF digital isolation
5773 */
5774 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
5775 val16 &= ~SYS_ISO_DIOR;
5776 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
5777
5778 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
5779 val8 &= ~APSD_CTRL_OFF;
5780 rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
5781 for (i = 200; i; i--) {
5782 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
5783 if (!(val8 & APSD_CTRL_OFF_STATUS))
5784 break;
5785 }
5786
5787 if (!i) {
5788 pr_info("%s: APSD_CTRL poll failed\n", __func__);
5789 return -EBUSY;
5790 }
5791
5792 /*
5793 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5794 */
5795 val16 = rtl8xxxu_read16(priv, REG_CR);
5796 val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5797 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
5798 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
5799 rtl8xxxu_write16(priv, REG_CR, val16);
5800
5801 /*
5802 * Workaround for 8188RU LNA power leakage problem.
5803 */
5804 if (priv->rtlchip == 0x8188c && priv->hi_pa) {
5805 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
5806 val32 &= ~BIT(1);
5807 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
5808 }
5809 return 0;
5810 }
5811
5812 #endif
5813
5814 static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv)
5815 {
5816 u16 val16;
5817 u32 val32;
5818 int ret;
5819
5820 ret = 0;
5821
5822 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
5823 if (val32 & SYS_CFG_SPS_LDO_SEL) {
5824 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3);
5825 } else {
5826 /*
5827 * Raise 1.2V voltage
5828 */
5829 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL);
5830 val32 &= 0xff0fffff;
5831 val32 |= 0x00500000;
5832 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32);
5833 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83);
5834 }
5835
5836 rtl8192e_disabled_to_emu(priv);
5837
5838 ret = rtl8192e_emu_to_active(priv);
5839 if (ret)
5840 goto exit;
5841
5842 rtl8xxxu_write16(priv, REG_CR, 0x0000);
5843
5844 /*
5845 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5846 * Set CR bit10 to enable 32k calibration.
5847 */
5848 val16 = rtl8xxxu_read16(priv, REG_CR);
5849 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5850 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5851 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5852 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5853 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5854 rtl8xxxu_write16(priv, REG_CR, val16);
5855
5856 exit:
5857 return ret;
5858 }
5859
5860 static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
5861 {
5862 u8 val8;
5863 u16 val16;
5864 u32 val32;
5865
5866 /*
5867 * Workaround for 8188RU LNA power leakage problem.
5868 */
5869 if (priv->rtlchip == 0x8188c && priv->hi_pa) {
5870 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
5871 val32 |= BIT(1);
5872 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
5873 }
5874
5875 rtl8xxxu_active_to_lps(priv);
5876
5877 /* Turn off RF */
5878 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
5879
5880 /* Reset Firmware if running in RAM */
5881 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
5882 rtl8xxxu_firmware_self_reset(priv);
5883
5884 /* Reset MCU */
5885 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
5886 val16 &= ~SYS_FUNC_CPU_ENABLE;
5887 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
5888
5889 /* Reset MCU ready status */
5890 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
5891
5892 rtl8xxxu_active_to_emu(priv);
5893 rtl8xxxu_emu_to_disabled(priv);
5894
5895 /* Reset MCU IO Wrapper */
5896 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
5897 val8 &= ~BIT(0);
5898 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
5899
5900 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
5901 val8 |= BIT(0);
5902 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
5903
5904 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
5905 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
5906 }
5907
5908 #ifdef NEED_PS_TDMA
5909 static void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
5910 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5)
5911 {
5912 struct h2c_cmd h2c;
5913
5914 memset(&h2c, 0, sizeof(struct h2c_cmd));
5915 h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA;
5916 h2c.b_type_dma.data1 = arg1;
5917 h2c.b_type_dma.data2 = arg2;
5918 h2c.b_type_dma.data3 = arg3;
5919 h2c.b_type_dma.data4 = arg4;
5920 h2c.b_type_dma.data5 = arg5;
5921 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma));
5922 }
5923 #endif
5924
5925 static void rtl8723bu_init_bt(struct rtl8xxxu_priv *priv)
5926 {
5927 struct h2c_cmd h2c;
5928 u32 val32;
5929 u8 val8;
5930
5931 /*
5932 * No indication anywhere as to what 0x0790 does. The 2 antenna
5933 * vendor code preserves bits 6-7 here.
5934 */
5935 rtl8xxxu_write8(priv, 0x0790, 0x05);
5936 /*
5937 * 0x0778 seems to be related to enabling the number of antennas
5938 * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it
5939 * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01
5940 */
5941 rtl8xxxu_write8(priv, 0x0778, 0x01);
5942
5943 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
5944 val8 |= BIT(5);
5945 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
5946
5947 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780);
5948
5949 rtl8723bu_write_btreg(priv, 0x3c, 0x15); /* BT TRx Mask on */
5950
5951 /*
5952 * Set BT grant to low
5953 */
5954 memset(&h2c, 0, sizeof(struct h2c_cmd));
5955 h2c.bt_grant.cmd = H2C_8723B_BT_GRANT;
5956 h2c.bt_grant.data = 0;
5957 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_grant));
5958
5959 /*
5960 * WLAN action by PTA
5961 */
5962 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
5963
5964 /*
5965 * BT select S0/S1 controlled by WiFi
5966 */
5967 val8 = rtl8xxxu_read8(priv, 0x0067);
5968 val8 |= BIT(5);
5969 rtl8xxxu_write8(priv, 0x0067, val8);
5970
5971 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
5972 val32 |= BIT(11);
5973 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
5974
5975 /*
5976 * Bits 6/7 are marked in/out ... but for what?
5977 */
5978 rtl8xxxu_write8(priv, 0x0974, 0xff);
5979
5980 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
5981 val32 |= (BIT(0) | BIT(1));
5982 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
5983
5984 rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77);
5985
5986 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
5987 val32 &= ~BIT(24);
5988 val32 |= BIT(23);
5989 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
5990
5991 /*
5992 * Fix external switch Main->S1, Aux->S0
5993 */
5994 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
5995 val8 &= ~BIT(0);
5996 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
5997
5998 memset(&h2c, 0, sizeof(struct h2c_cmd));
5999 h2c.ant_sel_rsv.cmd = H2C_8723B_ANT_SEL_RSV;
6000 h2c.ant_sel_rsv.ant_inverse = 1;
6001 h2c.ant_sel_rsv.int_switch_type = 0;
6002 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv));
6003
6004 /*
6005 * 0x280, 0x00, 0x200, 0x80 - not clear
6006 */
6007 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
6008
6009 /*
6010 * Software control, antenna at WiFi side
6011 */
6012 #ifdef NEED_PS_TDMA
6013 rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00);
6014 #endif
6015
6016 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
6017 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555);
6018 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
6019 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
6020
6021 memset(&h2c, 0, sizeof(struct h2c_cmd));
6022 h2c.bt_info.cmd = H2C_8723B_BT_INFO;
6023 h2c.bt_info.data = BIT(0);
6024 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_info));
6025
6026 memset(&h2c, 0, sizeof(struct h2c_cmd));
6027 h2c.ignore_wlan.cmd = H2C_8723B_BT_IGNORE_WLANACT;
6028 h2c.ignore_wlan.data = 0;
6029 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ignore_wlan));
6030 }
6031
6032 static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv *priv)
6033 {
6034 u32 agg_rx;
6035 u8 agg_ctrl;
6036
6037 /*
6038 * For now simply disable RX aggregation
6039 */
6040 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
6041 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
6042
6043 agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH);
6044 agg_rx &= ~RXDMA_USB_AGG_ENABLE;
6045 agg_rx &= ~0xff0f;
6046
6047 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
6048 rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx);
6049 }
6050
6051 static void rtl8723bu_init_statistics(struct rtl8xxxu_priv *priv)
6052 {
6053 u32 val32;
6054
6055 /* Time duration for NHM unit: 4us, 0x2710=40ms */
6056 rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0x2710);
6057 rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff);
6058 rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52);
6059 rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff);
6060 /* TH8 */
6061 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
6062 val32 |= 0xff;
6063 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
6064 /* Enable CCK */
6065 val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B);
6066 val32 |= BIT(8) | BIT(9) | BIT(10);
6067 rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32);
6068 /* Max power amongst all RX antennas */
6069 val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC);
6070 val32 |= BIT(7);
6071 rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32);
6072 }
6073
6074 static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
6075 {
6076 struct rtl8xxxu_priv *priv = hw->priv;
6077 struct device *dev = &priv->udev->dev;
6078 struct rtl8xxxu_rfregval *rftable;
6079 bool macpower;
6080 int ret;
6081 u8 val8;
6082 u16 val16;
6083 u32 val32;
6084
6085 /* Check if MAC is already powered on */
6086 val8 = rtl8xxxu_read8(priv, REG_CR);
6087
6088 /*
6089 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
6090 * initialized. First MAC returns 0xea, second MAC returns 0x00
6091 */
6092 if (val8 == 0xea)
6093 macpower = false;
6094 else
6095 macpower = true;
6096
6097 ret = priv->fops->power_on(priv);
6098 if (ret < 0) {
6099 dev_warn(dev, "%s: Failed power on\n", __func__);
6100 goto exit;
6101 }
6102
6103 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
6104 if (!macpower) {
6105 ret = priv->fops->llt_init(priv, TX_TOTAL_PAGE_NUM);
6106 if (ret) {
6107 dev_warn(dev, "%s: LLT table init failed\n", __func__);
6108 goto exit;
6109 }
6110
6111 /*
6112 * Presumably this is for 8188EU as well
6113 * Enable TX report and TX report timer
6114 */
6115 if (priv->rtlchip == 0x8723bu) {
6116 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
6117 val8 |= BIT(1);
6118 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
6119 /* Set MAX RPT MACID */
6120 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02);
6121 /* TX report Timer. Unit: 32us */
6122 rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0);
6123
6124 /* tmp ps ? */
6125 val8 = rtl8xxxu_read8(priv, 0xa3);
6126 val8 &= 0xf8;
6127 rtl8xxxu_write8(priv, 0xa3, val8);
6128 }
6129 }
6130
6131 ret = rtl8xxxu_download_firmware(priv);
6132 dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
6133 if (ret)
6134 goto exit;
6135 ret = rtl8xxxu_start_firmware(priv);
6136 dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
6137 if (ret)
6138 goto exit;
6139
6140 /* Solve too many protocol error on USB bus */
6141 /* Can't do this for 8188/8192 UMC A cut parts */
6142 if (priv->rtlchip == 0x8723a ||
6143 ((priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c ||
6144 priv->rtlchip == 0x8188c) &&
6145 (priv->chip_cut || !priv->vendor_umc))) {
6146 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
6147 rtl8xxxu_write8(priv, 0xfe41, 0x94);
6148 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6149
6150 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
6151 rtl8xxxu_write8(priv, 0xfe41, 0x19);
6152 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6153
6154 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
6155 rtl8xxxu_write8(priv, 0xfe41, 0x91);
6156 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6157
6158 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
6159 rtl8xxxu_write8(priv, 0xfe41, 0x81);
6160 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6161 }
6162
6163 if (priv->rtlchip == 0x8192e) {
6164 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
6165 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
6166 }
6167
6168 if (priv->fops->phy_init_antenna_selection)
6169 priv->fops->phy_init_antenna_selection(priv);
6170
6171 if (priv->rtlchip == 0x8723b)
6172 ret = rtl8xxxu_init_mac(priv, rtl8723b_mac_init_table);
6173 else
6174 ret = rtl8xxxu_init_mac(priv, rtl8723a_mac_init_table);
6175
6176 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
6177 if (ret)
6178 goto exit;
6179
6180 ret = rtl8xxxu_init_phy_bb(priv);
6181 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
6182 if (ret)
6183 goto exit;
6184
6185 switch(priv->rtlchip) {
6186 case 0x8723a:
6187 rftable = rtl8723au_radioa_1t_init_table;
6188 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6189 break;
6190 case 0x8723b:
6191 rftable = rtl8723bu_radioa_1t_init_table;
6192 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6193 /*
6194 * PHY LCK
6195 */
6196 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdfbe0);
6197 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, 0x8c01);
6198 msleep(200);
6199 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdffe0);
6200 break;
6201 case 0x8188c:
6202 if (priv->hi_pa)
6203 rftable = rtl8188ru_radioa_1t_highpa_table;
6204 else
6205 rftable = rtl8192cu_radioa_1t_init_table;
6206 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6207 break;
6208 case 0x8191c:
6209 rftable = rtl8192cu_radioa_1t_init_table;
6210 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6211 break;
6212 case 0x8192c:
6213 rftable = rtl8192cu_radioa_2t_init_table;
6214 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6215 if (ret)
6216 break;
6217 rftable = rtl8192cu_radiob_2t_init_table;
6218 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
6219 break;
6220 default:
6221 ret = -EINVAL;
6222 }
6223
6224 if (ret)
6225 goto exit;
6226
6227 /*
6228 * Chip specific quirks
6229 */
6230 if (priv->rtlchip == 0x8723a) {
6231 /* Fix USB interface interference issue */
6232 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
6233 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
6234 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6235 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
6236
6237 /* Reduce 80M spur */
6238 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
6239 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
6240 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
6241 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
6242 } else {
6243 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
6244 val32 |= TXDMA_OFFSET_DROP_DATA_EN;
6245 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
6246 }
6247
6248 if (!macpower) {
6249 if (priv->ep_tx_normal_queue)
6250 val8 = TX_PAGE_NUM_NORM_PQ;
6251 else
6252 val8 = 0;
6253
6254 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
6255
6256 val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD;
6257
6258 if (priv->ep_tx_high_queue)
6259 val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
6260 if (priv->ep_tx_low_queue)
6261 val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
6262
6263 rtl8xxxu_write32(priv, REG_RQPN, val32);
6264
6265 /*
6266 * Set TX buffer boundary
6267 */
6268 val8 = TX_TOTAL_PAGE_NUM + 1;
6269
6270 if (priv->rtlchip == 0x8723b)
6271 val8 -= 1;
6272
6273 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
6274 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
6275 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
6276 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
6277 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
6278 }
6279
6280 ret = rtl8xxxu_init_queue_priority(priv);
6281 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
6282 if (ret)
6283 goto exit;
6284
6285 /* RFSW Control - clear bit 14 ?? */
6286 if (priv->rtlchip != 0x8723b)
6287 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
6288 /* 0x07000760 */
6289 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
6290 FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
6291 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
6292 FPGA0_RF_BD_CTRL_SHIFT);
6293 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
6294 /* 0x860[6:5]= 00 - why? - this sets antenna B */
6295 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210);
6296
6297 priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
6298 RF6052_REG_MODE_AG);
6299
6300 /*
6301 * Set RX page boundary
6302 */
6303 if (priv->rtlchip == 0x8723b)
6304 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x3f7f);
6305 else
6306 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x27ff);
6307 /*
6308 * Transfer page size is always 128
6309 */
6310 if (priv->rtlchip == 0x8723b)
6311 val8 = (PBP_PAGE_SIZE_256 << PBP_PAGE_SIZE_RX_SHIFT) |
6312 (PBP_PAGE_SIZE_256 << PBP_PAGE_SIZE_TX_SHIFT);
6313 else
6314 val8 = (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_RX_SHIFT) |
6315 (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_TX_SHIFT);
6316 rtl8xxxu_write8(priv, REG_PBP, val8);
6317
6318 /*
6319 * Unit in 8 bytes, not obvious what it is used for
6320 */
6321 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
6322
6323 /*
6324 * Enable all interrupts - not obvious USB needs to do this
6325 */
6326 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
6327 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
6328
6329 rtl8xxxu_set_mac(priv);
6330 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
6331
6332 /*
6333 * Configure initial WMAC settings
6334 */
6335 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
6336 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
6337 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
6338 rtl8xxxu_write32(priv, REG_RCR, val32);
6339
6340 /*
6341 * Accept all multicast
6342 */
6343 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
6344 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
6345
6346 /*
6347 * Init adaptive controls
6348 */
6349 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6350 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
6351 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
6352 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6353
6354 /* CCK = 0x0a, OFDM = 0x10 */
6355 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
6356 rtl8xxxu_set_retry(priv, 0x30, 0x30);
6357 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
6358
6359 /*
6360 * Init EDCA
6361 */
6362 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
6363
6364 /* Set CCK SIFS */
6365 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
6366
6367 /* Set OFDM SIFS */
6368 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
6369
6370 /* TXOP */
6371 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
6372 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
6373 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
6374 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
6375
6376 /* Set data auto rate fallback retry count */
6377 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
6378 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
6379 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
6380 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
6381
6382 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
6383 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
6384 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
6385
6386 /* Set ACK timeout */
6387 rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
6388
6389 /*
6390 * Initialize beacon parameters
6391 */
6392 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
6393 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
6394 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
6395 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
6396 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
6397 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
6398
6399 /*
6400 * Initialize burst parameters
6401 */
6402 if (priv->rtlchip == 0x8723b) {
6403 /*
6404 * For USB high speed set 512B packets
6405 */
6406 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B);
6407 val8 &= ~(BIT(4) | BIT(5));
6408 val8 |= BIT(4);
6409 val8 |= BIT(1) | BIT(2) | BIT(3);
6410 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8);
6411
6412 /*
6413 * For USB high speed set 512B packets
6414 */
6415 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B);
6416 val8 |= BIT(7);
6417 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8);
6418
6419 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14);
6420 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 0x5e);
6421 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff);
6422 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18);
6423 rtl8xxxu_write8(priv, REG_PIFS, 0x00);
6424 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, 0x50);
6425 rtl8xxxu_write8(priv, REG_USTIME_EDCA, 0x50);
6426
6427 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
6428 val8 |= BIT(5) | BIT(6);
6429 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
6430 }
6431
6432 if (priv->fops->init_aggregation)
6433 priv->fops->init_aggregation(priv);
6434
6435 /*
6436 * Enable CCK and OFDM block
6437 */
6438 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
6439 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
6440 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
6441
6442 /*
6443 * Invalidate all CAM entries - bit 30 is undocumented
6444 */
6445 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
6446
6447 /*
6448 * Start out with default power levels for channel 6, 20MHz
6449 */
6450 priv->fops->set_tx_power(priv, 1, false);
6451
6452 /* Let the 8051 take control of antenna setting */
6453 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
6454 val8 |= LEDCFG2_DPDT_SELECT;
6455 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
6456
6457 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
6458
6459 /* Disable BAR - not sure if this has any effect on USB */
6460 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
6461
6462 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
6463
6464 if (priv->fops->init_statistics)
6465 priv->fops->init_statistics(priv);
6466
6467 rtl8723a_phy_lc_calibrate(priv);
6468
6469 priv->fops->phy_iq_calibrate(priv);
6470
6471 /*
6472 * This should enable thermal meter
6473 */
6474 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
6475
6476 /* Init BT hw config. */
6477 if (priv->fops->init_bt)
6478 priv->fops->init_bt(priv);
6479
6480 /* Set NAV_UPPER to 30000us */
6481 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
6482 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
6483
6484 if (priv->rtlchip == 0x8723a) {
6485 /*
6486 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
6487 * but we need to find root cause.
6488 * This is 8723au only.
6489 */
6490 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
6491 if ((val32 & 0xff000000) != 0x83000000) {
6492 val32 |= FPGA_RF_MODE_CCK;
6493 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
6494 }
6495 }
6496
6497 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
6498 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
6499 /* ack for xmit mgmt frames. */
6500 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
6501
6502 exit:
6503 return ret;
6504 }
6505
6506 static void rtl8xxxu_disable_device(struct ieee80211_hw *hw)
6507 {
6508 struct rtl8xxxu_priv *priv = hw->priv;
6509
6510 rtl8xxxu_power_off(priv);
6511 }
6512
6513 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
6514 struct ieee80211_key_conf *key, const u8 *mac)
6515 {
6516 u32 cmd, val32, addr, ctrl;
6517 int j, i, tmp_debug;
6518
6519 tmp_debug = rtl8xxxu_debug;
6520 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
6521 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
6522
6523 /*
6524 * This is a bit of a hack - the lower bits of the cipher
6525 * suite selector happens to match the cipher index in the CAM
6526 */
6527 addr = key->keyidx << CAM_CMD_KEY_SHIFT;
6528 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
6529
6530 for (j = 5; j >= 0; j--) {
6531 switch (j) {
6532 case 0:
6533 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
6534 break;
6535 case 1:
6536 val32 = mac[2] | (mac[3] << 8) |
6537 (mac[4] << 16) | (mac[5] << 24);
6538 break;
6539 default:
6540 i = (j - 2) << 2;
6541 val32 = key->key[i] | (key->key[i + 1] << 8) |
6542 key->key[i + 2] << 16 | key->key[i + 3] << 24;
6543 break;
6544 }
6545
6546 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
6547 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
6548 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
6549 udelay(100);
6550 }
6551
6552 rtl8xxxu_debug = tmp_debug;
6553 }
6554
6555 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
6556 struct ieee80211_vif *vif, const u8 *mac)
6557 {
6558 struct rtl8xxxu_priv *priv = hw->priv;
6559 u8 val8;
6560
6561 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6562 val8 |= BEACON_DISABLE_TSF_UPDATE;
6563 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6564 }
6565
6566 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
6567 struct ieee80211_vif *vif)
6568 {
6569 struct rtl8xxxu_priv *priv = hw->priv;
6570 u8 val8;
6571
6572 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6573 val8 &= ~BEACON_DISABLE_TSF_UPDATE;
6574 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6575 }
6576
6577 static void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
6578 u32 ramask, int sgi)
6579 {
6580 struct h2c_cmd h2c;
6581
6582 h2c.ramask.cmd = H2C_SET_RATE_MASK;
6583 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
6584 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
6585
6586 h2c.ramask.arg = 0x80;
6587 if (sgi)
6588 h2c.ramask.arg |= 0x20;
6589
6590 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
6591 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask));
6592 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ramask));
6593 }
6594
6595 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
6596 {
6597 u32 val32;
6598 u8 rate_idx = 0;
6599
6600 rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
6601
6602 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6603 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
6604 val32 |= rate_cfg;
6605 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6606
6607 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
6608
6609 while (rate_cfg) {
6610 rate_cfg = (rate_cfg >> 1);
6611 rate_idx++;
6612 }
6613 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
6614 }
6615
6616 static void
6617 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6618 struct ieee80211_bss_conf *bss_conf, u32 changed)
6619 {
6620 struct rtl8xxxu_priv *priv = hw->priv;
6621 struct device *dev = &priv->udev->dev;
6622 struct ieee80211_sta *sta;
6623 u32 val32;
6624 u8 val8;
6625
6626 if (changed & BSS_CHANGED_ASSOC) {
6627 struct h2c_cmd h2c;
6628
6629 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
6630
6631 memset(&h2c, 0, sizeof(struct h2c_cmd));
6632 rtl8xxxu_set_linktype(priv, vif->type);
6633
6634 if (bss_conf->assoc) {
6635 u32 ramask;
6636 int sgi = 0;
6637
6638 rcu_read_lock();
6639 sta = ieee80211_find_sta(vif, bss_conf->bssid);
6640 if (!sta) {
6641 dev_info(dev, "%s: ASSOC no sta found\n",
6642 __func__);
6643 rcu_read_unlock();
6644 goto error;
6645 }
6646
6647 if (sta->ht_cap.ht_supported)
6648 dev_info(dev, "%s: HT supported\n", __func__);
6649 if (sta->vht_cap.vht_supported)
6650 dev_info(dev, "%s: VHT supported\n", __func__);
6651
6652 /* TODO: Set bits 28-31 for rate adaptive id */
6653 ramask = (sta->supp_rates[0] & 0xfff) |
6654 sta->ht_cap.mcs.rx_mask[0] << 12 |
6655 sta->ht_cap.mcs.rx_mask[1] << 20;
6656 if (sta->ht_cap.cap &
6657 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
6658 sgi = 1;
6659 rcu_read_unlock();
6660
6661 rtl8xxxu_update_rate_mask(priv, ramask, sgi);
6662
6663 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
6664
6665 rtl8723a_stop_tx_beacon(priv);
6666
6667 /* joinbss sequence */
6668 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
6669 0xc000 | bss_conf->aid);
6670
6671 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
6672 } else {
6673 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6674 val8 |= BEACON_DISABLE_TSF_UPDATE;
6675 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6676
6677 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
6678 }
6679 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
6680 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss));
6681 }
6682
6683 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
6684 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
6685 bss_conf->use_short_preamble);
6686 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6687 if (bss_conf->use_short_preamble)
6688 val32 |= RSR_ACK_SHORT_PREAMBLE;
6689 else
6690 val32 &= ~RSR_ACK_SHORT_PREAMBLE;
6691 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6692 }
6693
6694 if (changed & BSS_CHANGED_ERP_SLOT) {
6695 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
6696 bss_conf->use_short_slot);
6697
6698 if (bss_conf->use_short_slot)
6699 val8 = 9;
6700 else
6701 val8 = 20;
6702 rtl8xxxu_write8(priv, REG_SLOT, val8);
6703 }
6704
6705 if (changed & BSS_CHANGED_BSSID) {
6706 dev_dbg(dev, "Changed BSSID!\n");
6707 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
6708 }
6709
6710 if (changed & BSS_CHANGED_BASIC_RATES) {
6711 dev_dbg(dev, "Changed BASIC_RATES!\n");
6712 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
6713 }
6714 error:
6715 return;
6716 }
6717
6718 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
6719 {
6720 u32 rtlqueue;
6721
6722 switch (queue) {
6723 case IEEE80211_AC_VO:
6724 rtlqueue = TXDESC_QUEUE_VO;
6725 break;
6726 case IEEE80211_AC_VI:
6727 rtlqueue = TXDESC_QUEUE_VI;
6728 break;
6729 case IEEE80211_AC_BE:
6730 rtlqueue = TXDESC_QUEUE_BE;
6731 break;
6732 case IEEE80211_AC_BK:
6733 rtlqueue = TXDESC_QUEUE_BK;
6734 break;
6735 default:
6736 rtlqueue = TXDESC_QUEUE_BE;
6737 }
6738
6739 return rtlqueue;
6740 }
6741
6742 static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
6743 {
6744 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
6745 u32 queue;
6746
6747 if (ieee80211_is_mgmt(hdr->frame_control))
6748 queue = TXDESC_QUEUE_MGNT;
6749 else
6750 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
6751
6752 return queue;
6753 }
6754
6755 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_tx_desc *tx_desc)
6756 {
6757 __le16 *ptr = (__le16 *)tx_desc;
6758 u16 csum = 0;
6759 int i;
6760
6761 /*
6762 * Clear csum field before calculation, as the csum field is
6763 * in the middle of the struct.
6764 */
6765 tx_desc->csum = cpu_to_le16(0);
6766
6767 for (i = 0; i < (sizeof(struct rtl8xxxu_tx_desc) / sizeof(u16)); i++)
6768 csum = csum ^ le16_to_cpu(ptr[i]);
6769
6770 tx_desc->csum |= cpu_to_le16(csum);
6771 }
6772
6773 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
6774 {
6775 struct rtl8xxxu_tx_urb *tx_urb, *tmp;
6776 unsigned long flags;
6777
6778 spin_lock_irqsave(&priv->tx_urb_lock, flags);
6779 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
6780 list_del(&tx_urb->list);
6781 priv->tx_urb_free_count--;
6782 usb_free_urb(&tx_urb->urb);
6783 }
6784 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
6785 }
6786
6787 static struct rtl8xxxu_tx_urb *
6788 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
6789 {
6790 struct rtl8xxxu_tx_urb *tx_urb;
6791 unsigned long flags;
6792
6793 spin_lock_irqsave(&priv->tx_urb_lock, flags);
6794 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
6795 struct rtl8xxxu_tx_urb, list);
6796 if (tx_urb) {
6797 list_del(&tx_urb->list);
6798 priv->tx_urb_free_count--;
6799 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
6800 !priv->tx_stopped) {
6801 priv->tx_stopped = true;
6802 ieee80211_stop_queues(priv->hw);
6803 }
6804 }
6805
6806 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
6807
6808 return tx_urb;
6809 }
6810
6811 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
6812 struct rtl8xxxu_tx_urb *tx_urb)
6813 {
6814 unsigned long flags;
6815
6816 INIT_LIST_HEAD(&tx_urb->list);
6817
6818 spin_lock_irqsave(&priv->tx_urb_lock, flags);
6819
6820 list_add(&tx_urb->list, &priv->tx_urb_free_list);
6821 priv->tx_urb_free_count++;
6822 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
6823 priv->tx_stopped) {
6824 priv->tx_stopped = false;
6825 ieee80211_wake_queues(priv->hw);
6826 }
6827
6828 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
6829 }
6830
6831 static void rtl8xxxu_tx_complete(struct urb *urb)
6832 {
6833 struct sk_buff *skb = (struct sk_buff *)urb->context;
6834 struct ieee80211_tx_info *tx_info;
6835 struct ieee80211_hw *hw;
6836 struct rtl8xxxu_tx_urb *tx_urb =
6837 container_of(urb, struct rtl8xxxu_tx_urb, urb);
6838
6839 tx_info = IEEE80211_SKB_CB(skb);
6840 hw = tx_info->rate_driver_data[0];
6841
6842 skb_pull(skb, sizeof(struct rtl8xxxu_tx_desc));
6843
6844 ieee80211_tx_info_clear_status(tx_info);
6845 tx_info->status.rates[0].idx = -1;
6846 tx_info->status.rates[0].count = 0;
6847
6848 if (!urb->status)
6849 tx_info->flags |= IEEE80211_TX_STAT_ACK;
6850
6851 ieee80211_tx_status_irqsafe(hw, skb);
6852
6853 rtl8xxxu_free_tx_urb(hw->priv, tx_urb);
6854 }
6855
6856 static void rtl8xxxu_dump_action(struct device *dev,
6857 struct ieee80211_hdr *hdr)
6858 {
6859 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
6860 u16 cap, timeout;
6861
6862 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
6863 return;
6864
6865 switch (mgmt->u.action.u.addba_resp.action_code) {
6866 case WLAN_ACTION_ADDBA_RESP:
6867 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
6868 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
6869 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
6870 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
6871 "status %02x\n",
6872 timeout,
6873 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
6874 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
6875 (cap >> 1) & 0x1,
6876 le16_to_cpu(mgmt->u.action.u.addba_resp.status));
6877 break;
6878 case WLAN_ACTION_ADDBA_REQ:
6879 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
6880 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
6881 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
6882 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
6883 timeout,
6884 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
6885 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
6886 (cap >> 1) & 0x1);
6887 break;
6888 default:
6889 dev_info(dev, "action frame %02x\n",
6890 mgmt->u.action.u.addba_resp.action_code);
6891 break;
6892 }
6893 }
6894
6895 static void rtl8xxxu_tx(struct ieee80211_hw *hw,
6896 struct ieee80211_tx_control *control,
6897 struct sk_buff *skb)
6898 {
6899 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
6900 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
6901 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
6902 struct rtl8xxxu_priv *priv = hw->priv;
6903 struct rtl8xxxu_tx_desc *tx_desc;
6904 struct rtl8xxxu_tx_urb *tx_urb;
6905 struct ieee80211_sta *sta = NULL;
6906 struct ieee80211_vif *vif = tx_info->control.vif;
6907 struct device *dev = &priv->udev->dev;
6908 u32 queue, rate;
6909 u16 pktlen = skb->len;
6910 u16 seq_number;
6911 u16 rate_flag = tx_info->control.rates[0].flags;
6912 int ret;
6913
6914 if (skb_headroom(skb) < sizeof(struct rtl8xxxu_tx_desc)) {
6915 dev_warn(dev,
6916 "%s: Not enough headroom (%i) for tx descriptor\n",
6917 __func__, skb_headroom(skb));
6918 goto error;
6919 }
6920
6921 if (unlikely(skb->len > (65535 - sizeof(struct rtl8xxxu_tx_desc)))) {
6922 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
6923 __func__, skb->len);
6924 goto error;
6925 }
6926
6927 tx_urb = rtl8xxxu_alloc_tx_urb(priv);
6928 if (!tx_urb) {
6929 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
6930 goto error;
6931 }
6932
6933 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
6934 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
6935 __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
6936
6937 if (ieee80211_is_action(hdr->frame_control))
6938 rtl8xxxu_dump_action(dev, hdr);
6939
6940 tx_info->rate_driver_data[0] = hw;
6941
6942 if (control && control->sta)
6943 sta = control->sta;
6944
6945 tx_desc = (struct rtl8xxxu_tx_desc *)
6946 skb_push(skb, sizeof(struct rtl8xxxu_tx_desc));
6947
6948 memset(tx_desc, 0, sizeof(struct rtl8xxxu_tx_desc));
6949 tx_desc->pkt_size = cpu_to_le16(pktlen);
6950 tx_desc->pkt_offset = sizeof(struct rtl8xxxu_tx_desc);
6951
6952 tx_desc->txdw0 =
6953 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
6954 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
6955 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
6956 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
6957
6958 queue = rtl8xxxu_queue_select(hw, skb);
6959 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
6960
6961 if (tx_info->control.hw_key) {
6962 switch (tx_info->control.hw_key->cipher) {
6963 case WLAN_CIPHER_SUITE_WEP40:
6964 case WLAN_CIPHER_SUITE_WEP104:
6965 case WLAN_CIPHER_SUITE_TKIP:
6966 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
6967 break;
6968 case WLAN_CIPHER_SUITE_CCMP:
6969 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
6970 break;
6971 default:
6972 break;
6973 }
6974 }
6975
6976 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
6977 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT);
6978
6979 if (rate_flag & IEEE80211_TX_RC_MCS)
6980 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
6981 else
6982 rate = tx_rate->hw_value;
6983 tx_desc->txdw5 = cpu_to_le32(rate);
6984
6985 if (ieee80211_is_data(hdr->frame_control))
6986 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
6987
6988 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
6989 if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
6990 if (sta->ht_cap.ht_supported) {
6991 u32 ampdu, val32;
6992
6993 ampdu = (u32)sta->ht_cap.ampdu_density;
6994 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
6995 tx_desc->txdw2 |= cpu_to_le32(val32);
6996 tx_desc->txdw1 |= cpu_to_le32(TXDESC_AGG_ENABLE);
6997 } else
6998 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
6999 } else
7000 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
7001
7002 if (ieee80211_is_data_qos(hdr->frame_control))
7003 tx_desc->txdw4 |= cpu_to_le32(TXDESC_QOS);
7004 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
7005 (sta && vif && vif->bss_conf.use_short_preamble))
7006 tx_desc->txdw4 |= cpu_to_le32(TXDESC_SHORT_PREAMBLE);
7007 if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
7008 (ieee80211_is_data_qos(hdr->frame_control) &&
7009 sta && sta->ht_cap.cap &
7010 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
7011 tx_desc->txdw5 |= cpu_to_le32(TXDESC_SHORT_GI);
7012 }
7013 if (ieee80211_is_mgmt(hdr->frame_control)) {
7014 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
7015 tx_desc->txdw4 |= cpu_to_le32(TXDESC_USE_DRIVER_RATE);
7016 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC_RETRY_LIMIT_SHIFT);
7017 tx_desc->txdw5 |= cpu_to_le32(TXDESC_RETRY_LIMIT_ENABLE);
7018 }
7019
7020 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
7021 /* Use RTS rate 24M - does the mac80211 tell us which to use? */
7022 tx_desc->txdw4 |= cpu_to_le32(DESC_RATE_24M);
7023 tx_desc->txdw4 |= cpu_to_le32(TXDESC_RTS_CTS_ENABLE);
7024 tx_desc->txdw4 |= cpu_to_le32(TXDESC_HW_RTS_ENABLE);
7025 }
7026
7027 rtl8xxxu_calc_tx_desc_csum(tx_desc);
7028
7029 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
7030 skb->data, skb->len, rtl8xxxu_tx_complete, skb);
7031
7032 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
7033 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
7034 if (ret) {
7035 usb_unanchor_urb(&tx_urb->urb);
7036 rtl8xxxu_free_tx_urb(priv, tx_urb);
7037 goto error;
7038 }
7039 return;
7040 error:
7041 dev_kfree_skb(skb);
7042 }
7043
7044 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
7045 struct ieee80211_rx_status *rx_status,
7046 struct rtl8xxxu_rx_desc *rx_desc,
7047 struct rtl8723au_phy_stats *phy_stats)
7048 {
7049 if (phy_stats->sgi_en)
7050 rx_status->flag |= RX_FLAG_SHORT_GI;
7051
7052 if (rx_desc->rxmcs < DESC_RATE_6M) {
7053 /*
7054 * Handle PHY stats for CCK rates
7055 */
7056 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
7057
7058 switch (cck_agc_rpt & 0xc0) {
7059 case 0xc0:
7060 rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
7061 break;
7062 case 0x80:
7063 rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
7064 break;
7065 case 0x40:
7066 rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
7067 break;
7068 case 0x00:
7069 rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
7070 break;
7071 }
7072 } else {
7073 rx_status->signal =
7074 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
7075 }
7076 }
7077
7078 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
7079 {
7080 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
7081 unsigned long flags;
7082
7083 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7084
7085 list_for_each_entry_safe(rx_urb, tmp,
7086 &priv->rx_urb_pending_list, list) {
7087 list_del(&rx_urb->list);
7088 priv->rx_urb_pending_count--;
7089 usb_free_urb(&rx_urb->urb);
7090 }
7091
7092 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7093 }
7094
7095 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
7096 struct rtl8xxxu_rx_urb *rx_urb)
7097 {
7098 struct sk_buff *skb;
7099 unsigned long flags;
7100 int pending = 0;
7101
7102 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7103
7104 if (!priv->shutdown) {
7105 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
7106 priv->rx_urb_pending_count++;
7107 pending = priv->rx_urb_pending_count;
7108 } else {
7109 skb = (struct sk_buff *)rx_urb->urb.context;
7110 dev_kfree_skb(skb);
7111 usb_free_urb(&rx_urb->urb);
7112 }
7113
7114 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7115
7116 if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
7117 schedule_work(&priv->rx_urb_wq);
7118 }
7119
7120 static void rtl8xxxu_rx_urb_work(struct work_struct *work)
7121 {
7122 struct rtl8xxxu_priv *priv;
7123 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
7124 struct list_head local;
7125 struct sk_buff *skb;
7126 unsigned long flags;
7127 int ret;
7128
7129 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
7130 INIT_LIST_HEAD(&local);
7131
7132 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7133
7134 list_splice_init(&priv->rx_urb_pending_list, &local);
7135 priv->rx_urb_pending_count = 0;
7136
7137 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7138
7139 list_for_each_entry_safe(rx_urb, tmp, &local, list) {
7140 list_del_init(&rx_urb->list);
7141 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
7142 /*
7143 * If out of memory or temporary error, put it back on the
7144 * queue and try again. Otherwise the device is dead/gone
7145 * and we should drop it.
7146 */
7147 switch (ret) {
7148 case 0:
7149 break;
7150 case -ENOMEM:
7151 case -EAGAIN:
7152 rtl8xxxu_queue_rx_urb(priv, rx_urb);
7153 break;
7154 default:
7155 pr_info("failed to requeue urb %i\n", ret);
7156 skb = (struct sk_buff *)rx_urb->urb.context;
7157 dev_kfree_skb(skb);
7158 usb_free_urb(&rx_urb->urb);
7159 }
7160 }
7161 }
7162
7163 static int rtl8723au_parse_rx_desc(struct rtl8xxxu_priv *priv,
7164 struct sk_buff *skb,
7165 struct ieee80211_rx_status *rx_status)
7166 {
7167 struct rtl8xxxu_rx_desc *rx_desc = (struct rtl8xxxu_rx_desc *)skb->data;
7168 struct rtl8723au_phy_stats *phy_stats;
7169 int drvinfo_sz, desc_shift;
7170
7171 skb_pull(skb, sizeof(struct rtl8xxxu_rx_desc));
7172
7173 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
7174
7175 drvinfo_sz = rx_desc->drvinfo_sz * 8;
7176 desc_shift = rx_desc->shift;
7177 skb_pull(skb, drvinfo_sz + desc_shift);
7178
7179 if (rx_desc->phy_stats)
7180 rtl8xxxu_rx_parse_phystats(priv, rx_status, rx_desc, phy_stats);
7181
7182 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
7183 rx_status->flag |= RX_FLAG_MACTIME_START;
7184
7185 if (!rx_desc->swdec)
7186 rx_status->flag |= RX_FLAG_DECRYPTED;
7187 if (rx_desc->crc32)
7188 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7189 if (rx_desc->bw)
7190 rx_status->flag |= RX_FLAG_40MHZ;
7191
7192 if (rx_desc->rxht) {
7193 rx_status->flag |= RX_FLAG_HT;
7194 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
7195 } else {
7196 rx_status->rate_idx = rx_desc->rxmcs;
7197 }
7198
7199 return RX_TYPE_DATA_PKT;
7200 }
7201
7202 static int rtl8723bu_parse_rx_desc(struct rtl8xxxu_priv *priv,
7203 struct sk_buff *skb,
7204 struct ieee80211_rx_status *rx_status)
7205 {
7206 struct rtl8723bu_rx_desc *rx_desc =
7207 (struct rtl8723bu_rx_desc *)skb->data;
7208 struct rtl8723au_phy_stats *phy_stats;
7209 int drvinfo_sz, desc_shift;
7210 int rx_type;
7211
7212 skb_pull(skb, sizeof(struct rtl8723bu_rx_desc));
7213
7214 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
7215
7216 drvinfo_sz = rx_desc->drvinfo_sz * 8;
7217 desc_shift = rx_desc->shift;
7218 skb_pull(skb, drvinfo_sz + desc_shift);
7219
7220 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
7221 rx_status->flag |= RX_FLAG_MACTIME_START;
7222
7223 if (!rx_desc->swdec)
7224 rx_status->flag |= RX_FLAG_DECRYPTED;
7225 if (rx_desc->crc32)
7226 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7227 if (rx_desc->bw)
7228 rx_status->flag |= RX_FLAG_40MHZ;
7229
7230 if (rx_desc->rxmcs >= DESC_RATE_MCS0) {
7231 rx_status->flag |= RX_FLAG_HT;
7232 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
7233 } else {
7234 rx_status->rate_idx = rx_desc->rxmcs;
7235 }
7236
7237 if (rx_desc->rpt_sel) {
7238 struct device *dev = &priv->udev->dev;
7239 dev_dbg(dev, "%s: C2H packet\n", __func__);
7240 rx_type = RX_TYPE_C2H;
7241 } else {
7242 rx_type = RX_TYPE_DATA_PKT;
7243 }
7244
7245 return rx_type;
7246 }
7247
7248 static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv,
7249 struct sk_buff *skb)
7250 {
7251 struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data;
7252 struct device *dev = &priv->udev->dev;
7253 int len;
7254
7255 len = skb->len - 2;
7256
7257 dev_info(dev, "C2H ID %02x seq %02x, len %02x source %02x\n",
7258 c2h->id, c2h->seq, len, c2h->bt_info.response_source);
7259
7260 switch(c2h->id) {
7261 case C2H_8723B_BT_INFO:
7262 if (c2h->bt_info.response_source >
7263 BT_INFO_SRC_8723B_BT_ACTIVE_SEND)
7264 dev_info(dev, "C2H_BT_INFO WiFi only firmware\n");
7265 else
7266 dev_info(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n");
7267
7268 if (c2h->bt_info.bt_has_reset)
7269 dev_info(dev, "BT has been reset\n");
7270 if (c2h->bt_info.tx_rx_mask)
7271 dev_info(dev, "BT TRx mask\n");
7272
7273 break;
7274 case C2H_8723B_BT_MP_INFO:
7275 dev_info(dev, "C2H_MP_INFO ext ID %02x, status %02x\n",
7276 c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status);
7277 break;
7278 default:
7279 pr_info("%s: Unhandled C2H event %02x\n", __func__, c2h->id);
7280 break;
7281 }
7282 }
7283
7284 static void rtl8xxxu_rx_complete(struct urb *urb)
7285 {
7286 struct rtl8xxxu_rx_urb *rx_urb =
7287 container_of(urb, struct rtl8xxxu_rx_urb, urb);
7288 struct ieee80211_hw *hw = rx_urb->hw;
7289 struct rtl8xxxu_priv *priv = hw->priv;
7290 struct sk_buff *skb = (struct sk_buff *)urb->context;
7291 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
7292 struct device *dev = &priv->udev->dev;
7293 __le32 *_rx_desc_le = (__le32 *)skb->data;
7294 u32 *_rx_desc = (u32 *)skb->data;
7295 int rx_type, i;
7296
7297 for (i = 0; i < (sizeof(struct rtl8xxxu_rx_desc) / sizeof(u32)); i++)
7298 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
7299
7300 skb_put(skb, urb->actual_length);
7301
7302 if (urb->status == 0) {
7303 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
7304
7305 rx_type = priv->fops->parse_rx_desc(priv, skb, rx_status);
7306
7307 rx_status->freq = hw->conf.chandef.chan->center_freq;
7308 rx_status->band = hw->conf.chandef.chan->band;
7309
7310 if (rx_type == RX_TYPE_DATA_PKT)
7311 ieee80211_rx_irqsafe(hw, skb);
7312 else {
7313 rtl8723bu_handle_c2h(priv, skb);
7314 dev_kfree_skb(skb);
7315 }
7316
7317 skb = NULL;
7318 rx_urb->urb.context = NULL;
7319 rtl8xxxu_queue_rx_urb(priv, rx_urb);
7320 } else {
7321 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
7322 goto cleanup;
7323 }
7324 return;
7325
7326 cleanup:
7327 usb_free_urb(urb);
7328 dev_kfree_skb(skb);
7329 return;
7330 }
7331
7332 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
7333 struct rtl8xxxu_rx_urb *rx_urb)
7334 {
7335 struct sk_buff *skb;
7336 int skb_size;
7337 int ret;
7338
7339 skb_size = sizeof(struct rtl8xxxu_rx_desc) + RTL_RX_BUFFER_SIZE;
7340 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
7341 if (!skb)
7342 return -ENOMEM;
7343
7344 memset(skb->data, 0, sizeof(struct rtl8xxxu_rx_desc));
7345 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
7346 skb_size, rtl8xxxu_rx_complete, skb);
7347 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
7348 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
7349 if (ret)
7350 usb_unanchor_urb(&rx_urb->urb);
7351 return ret;
7352 }
7353
7354 static void rtl8xxxu_int_complete(struct urb *urb)
7355 {
7356 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
7357 struct device *dev = &priv->udev->dev;
7358 int ret;
7359
7360 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
7361 if (urb->status == 0) {
7362 usb_anchor_urb(urb, &priv->int_anchor);
7363 ret = usb_submit_urb(urb, GFP_ATOMIC);
7364 if (ret)
7365 usb_unanchor_urb(urb);
7366 } else {
7367 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
7368 }
7369 }
7370
7371
7372 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
7373 {
7374 struct rtl8xxxu_priv *priv = hw->priv;
7375 struct urb *urb;
7376 u32 val32;
7377 int ret;
7378
7379 urb = usb_alloc_urb(0, GFP_KERNEL);
7380 if (!urb)
7381 return -ENOMEM;
7382
7383 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
7384 priv->int_buf, USB_INTR_CONTENT_LENGTH,
7385 rtl8xxxu_int_complete, priv, 1);
7386 usb_anchor_urb(urb, &priv->int_anchor);
7387 ret = usb_submit_urb(urb, GFP_KERNEL);
7388 if (ret) {
7389 usb_unanchor_urb(urb);
7390 goto error;
7391 }
7392
7393 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
7394 val32 |= USB_HIMR_CPWM;
7395 rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
7396
7397 error:
7398 return ret;
7399 }
7400
7401 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
7402 struct ieee80211_vif *vif)
7403 {
7404 struct rtl8xxxu_priv *priv = hw->priv;
7405 int ret;
7406 u8 val8;
7407
7408 switch (vif->type) {
7409 case NL80211_IFTYPE_STATION:
7410 rtl8723a_stop_tx_beacon(priv);
7411
7412 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
7413 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
7414 BEACON_DISABLE_TSF_UPDATE;
7415 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
7416 ret = 0;
7417 break;
7418 default:
7419 ret = -EOPNOTSUPP;
7420 }
7421
7422 rtl8xxxu_set_linktype(priv, vif->type);
7423
7424 return ret;
7425 }
7426
7427 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
7428 struct ieee80211_vif *vif)
7429 {
7430 struct rtl8xxxu_priv *priv = hw->priv;
7431
7432 dev_dbg(&priv->udev->dev, "%s\n", __func__);
7433 }
7434
7435 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
7436 {
7437 struct rtl8xxxu_priv *priv = hw->priv;
7438 struct device *dev = &priv->udev->dev;
7439 u16 val16;
7440 int ret = 0, channel;
7441 bool ht40;
7442
7443 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
7444 dev_info(dev,
7445 "%s: channel: %i (changed %08x chandef.width %02x)\n",
7446 __func__, hw->conf.chandef.chan->hw_value,
7447 changed, hw->conf.chandef.width);
7448
7449 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
7450 val16 = ((hw->conf.long_frame_max_tx_count <<
7451 RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
7452 ((hw->conf.short_frame_max_tx_count <<
7453 RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
7454 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
7455 }
7456
7457 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
7458 switch (hw->conf.chandef.width) {
7459 case NL80211_CHAN_WIDTH_20_NOHT:
7460 case NL80211_CHAN_WIDTH_20:
7461 ht40 = false;
7462 break;
7463 case NL80211_CHAN_WIDTH_40:
7464 ht40 = true;
7465 break;
7466 default:
7467 ret = -ENOTSUPP;
7468 goto exit;
7469 }
7470
7471 channel = hw->conf.chandef.chan->hw_value;
7472
7473 priv->fops->set_tx_power(priv, channel, ht40);
7474
7475 priv->fops->config_channel(hw);
7476 }
7477
7478 exit:
7479 return ret;
7480 }
7481
7482 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
7483 struct ieee80211_vif *vif, u16 queue,
7484 const struct ieee80211_tx_queue_params *param)
7485 {
7486 struct rtl8xxxu_priv *priv = hw->priv;
7487 struct device *dev = &priv->udev->dev;
7488 u32 val32;
7489 u8 aifs, acm_ctrl, acm_bit;
7490
7491 aifs = param->aifs;
7492
7493 val32 = aifs |
7494 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
7495 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
7496 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
7497
7498 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
7499 dev_dbg(dev,
7500 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
7501 __func__, queue, val32, param->acm, acm_ctrl);
7502
7503 switch (queue) {
7504 case IEEE80211_AC_VO:
7505 acm_bit = ACM_HW_CTRL_VO;
7506 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
7507 break;
7508 case IEEE80211_AC_VI:
7509 acm_bit = ACM_HW_CTRL_VI;
7510 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
7511 break;
7512 case IEEE80211_AC_BE:
7513 acm_bit = ACM_HW_CTRL_BE;
7514 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
7515 break;
7516 case IEEE80211_AC_BK:
7517 acm_bit = ACM_HW_CTRL_BK;
7518 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
7519 break;
7520 default:
7521 acm_bit = 0;
7522 break;
7523 }
7524
7525 if (param->acm)
7526 acm_ctrl |= acm_bit;
7527 else
7528 acm_ctrl &= ~acm_bit;
7529 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
7530
7531 return 0;
7532 }
7533
7534 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
7535 unsigned int changed_flags,
7536 unsigned int *total_flags, u64 multicast)
7537 {
7538 struct rtl8xxxu_priv *priv = hw->priv;
7539 u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
7540
7541 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
7542 __func__, changed_flags, *total_flags);
7543
7544 /*
7545 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
7546 */
7547
7548 if (*total_flags & FIF_FCSFAIL)
7549 rcr |= RCR_ACCEPT_CRC32;
7550 else
7551 rcr &= ~RCR_ACCEPT_CRC32;
7552
7553 /*
7554 * FIF_PLCPFAIL not supported?
7555 */
7556
7557 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
7558 rcr &= ~RCR_CHECK_BSSID_BEACON;
7559 else
7560 rcr |= RCR_CHECK_BSSID_BEACON;
7561
7562 if (*total_flags & FIF_CONTROL)
7563 rcr |= RCR_ACCEPT_CTRL_FRAME;
7564 else
7565 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
7566
7567 if (*total_flags & FIF_OTHER_BSS) {
7568 rcr |= RCR_ACCEPT_AP;
7569 rcr &= ~RCR_CHECK_BSSID_MATCH;
7570 } else {
7571 rcr &= ~RCR_ACCEPT_AP;
7572 rcr |= RCR_CHECK_BSSID_MATCH;
7573 }
7574
7575 if (*total_flags & FIF_PSPOLL)
7576 rcr |= RCR_ACCEPT_PM;
7577 else
7578 rcr &= ~RCR_ACCEPT_PM;
7579
7580 /*
7581 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
7582 */
7583
7584 rtl8xxxu_write32(priv, REG_RCR, rcr);
7585
7586 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
7587 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
7588 FIF_PROBE_REQ);
7589 }
7590
7591 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
7592 {
7593 if (rts > 2347)
7594 return -EINVAL;
7595
7596 return 0;
7597 }
7598
7599 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
7600 struct ieee80211_vif *vif,
7601 struct ieee80211_sta *sta,
7602 struct ieee80211_key_conf *key)
7603 {
7604 struct rtl8xxxu_priv *priv = hw->priv;
7605 struct device *dev = &priv->udev->dev;
7606 u8 mac_addr[ETH_ALEN];
7607 u8 val8;
7608 u16 val16;
7609 u32 val32;
7610 int retval = -EOPNOTSUPP;
7611
7612 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
7613 __func__, cmd, key->cipher, key->keyidx);
7614
7615 if (vif->type != NL80211_IFTYPE_STATION)
7616 return -EOPNOTSUPP;
7617
7618 if (key->keyidx > 3)
7619 return -EOPNOTSUPP;
7620
7621 switch (key->cipher) {
7622 case WLAN_CIPHER_SUITE_WEP40:
7623 case WLAN_CIPHER_SUITE_WEP104:
7624
7625 break;
7626 case WLAN_CIPHER_SUITE_CCMP:
7627 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
7628 break;
7629 case WLAN_CIPHER_SUITE_TKIP:
7630 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
7631 default:
7632 return -EOPNOTSUPP;
7633 }
7634
7635 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
7636 dev_dbg(dev, "%s: pairwise key\n", __func__);
7637 ether_addr_copy(mac_addr, sta->addr);
7638 } else {
7639 dev_dbg(dev, "%s: group key\n", __func__);
7640 eth_broadcast_addr(mac_addr);
7641 }
7642
7643 val16 = rtl8xxxu_read16(priv, REG_CR);
7644 val16 |= CR_SECURITY_ENABLE;
7645 rtl8xxxu_write16(priv, REG_CR, val16);
7646
7647 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
7648 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
7649 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
7650 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
7651
7652 switch (cmd) {
7653 case SET_KEY:
7654 key->hw_key_idx = key->keyidx;
7655 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
7656 rtl8xxxu_cam_write(priv, key, mac_addr);
7657 retval = 0;
7658 break;
7659 case DISABLE_KEY:
7660 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
7661 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
7662 key->keyidx << CAM_CMD_KEY_SHIFT;
7663 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
7664 retval = 0;
7665 break;
7666 default:
7667 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
7668 }
7669
7670 return retval;
7671 }
7672
7673 static int
7674 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
7675 struct ieee80211_ampdu_params *params)
7676 {
7677 struct rtl8xxxu_priv *priv = hw->priv;
7678 struct device *dev = &priv->udev->dev;
7679 u8 ampdu_factor, ampdu_density;
7680 struct ieee80211_sta *sta = params->sta;
7681 enum ieee80211_ampdu_mlme_action action = params->action;
7682
7683 switch (action) {
7684 case IEEE80211_AMPDU_TX_START:
7685 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
7686 ampdu_factor = sta->ht_cap.ampdu_factor;
7687 ampdu_density = sta->ht_cap.ampdu_density;
7688 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
7689 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
7690 dev_dbg(dev,
7691 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
7692 ampdu_factor, ampdu_density);
7693 break;
7694 case IEEE80211_AMPDU_TX_STOP_FLUSH:
7695 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
7696 rtl8xxxu_set_ampdu_factor(priv, 0);
7697 rtl8xxxu_set_ampdu_min_space(priv, 0);
7698 break;
7699 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
7700 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
7701 __func__);
7702 rtl8xxxu_set_ampdu_factor(priv, 0);
7703 rtl8xxxu_set_ampdu_min_space(priv, 0);
7704 break;
7705 case IEEE80211_AMPDU_RX_START:
7706 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
7707 break;
7708 case IEEE80211_AMPDU_RX_STOP:
7709 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
7710 break;
7711 default:
7712 break;
7713 }
7714 return 0;
7715 }
7716
7717 static int rtl8xxxu_start(struct ieee80211_hw *hw)
7718 {
7719 struct rtl8xxxu_priv *priv = hw->priv;
7720 struct rtl8xxxu_rx_urb *rx_urb;
7721 struct rtl8xxxu_tx_urb *tx_urb;
7722 unsigned long flags;
7723 int ret, i;
7724
7725 ret = 0;
7726
7727 init_usb_anchor(&priv->rx_anchor);
7728 init_usb_anchor(&priv->tx_anchor);
7729 init_usb_anchor(&priv->int_anchor);
7730
7731 priv->fops->enable_rf(priv);
7732 if (priv->usb_interrupts) {
7733 ret = rtl8xxxu_submit_int_urb(hw);
7734 if (ret)
7735 goto exit;
7736 }
7737
7738 for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
7739 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
7740 if (!tx_urb) {
7741 if (!i)
7742 ret = -ENOMEM;
7743
7744 goto error_out;
7745 }
7746 usb_init_urb(&tx_urb->urb);
7747 INIT_LIST_HEAD(&tx_urb->list);
7748 tx_urb->hw = hw;
7749 list_add(&tx_urb->list, &priv->tx_urb_free_list);
7750 priv->tx_urb_free_count++;
7751 }
7752
7753 priv->tx_stopped = false;
7754
7755 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7756 priv->shutdown = false;
7757 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7758
7759 for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
7760 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
7761 if (!rx_urb) {
7762 if (!i)
7763 ret = -ENOMEM;
7764
7765 goto error_out;
7766 }
7767 usb_init_urb(&rx_urb->urb);
7768 INIT_LIST_HEAD(&rx_urb->list);
7769 rx_urb->hw = hw;
7770
7771 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
7772 }
7773 exit:
7774 /*
7775 * Accept all data and mgmt frames
7776 */
7777 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
7778 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
7779
7780 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
7781
7782 return ret;
7783
7784 error_out:
7785 rtl8xxxu_free_tx_resources(priv);
7786 /*
7787 * Disable all data and mgmt frames
7788 */
7789 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
7790 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
7791
7792 return ret;
7793 }
7794
7795 static void rtl8xxxu_stop(struct ieee80211_hw *hw)
7796 {
7797 struct rtl8xxxu_priv *priv = hw->priv;
7798 unsigned long flags;
7799
7800 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
7801
7802 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
7803 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
7804
7805 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7806 priv->shutdown = true;
7807 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7808
7809 usb_kill_anchored_urbs(&priv->rx_anchor);
7810 usb_kill_anchored_urbs(&priv->tx_anchor);
7811 if (priv->usb_interrupts)
7812 usb_kill_anchored_urbs(&priv->int_anchor);
7813
7814 rtl8723a_disable_rf(priv);
7815
7816 /*
7817 * Disable interrupts
7818 */
7819 if (priv->usb_interrupts)
7820 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
7821
7822 rtl8xxxu_free_rx_resources(priv);
7823 rtl8xxxu_free_tx_resources(priv);
7824 }
7825
7826 static const struct ieee80211_ops rtl8xxxu_ops = {
7827 .tx = rtl8xxxu_tx,
7828 .add_interface = rtl8xxxu_add_interface,
7829 .remove_interface = rtl8xxxu_remove_interface,
7830 .config = rtl8xxxu_config,
7831 .conf_tx = rtl8xxxu_conf_tx,
7832 .bss_info_changed = rtl8xxxu_bss_info_changed,
7833 .configure_filter = rtl8xxxu_configure_filter,
7834 .set_rts_threshold = rtl8xxxu_set_rts_threshold,
7835 .start = rtl8xxxu_start,
7836 .stop = rtl8xxxu_stop,
7837 .sw_scan_start = rtl8xxxu_sw_scan_start,
7838 .sw_scan_complete = rtl8xxxu_sw_scan_complete,
7839 .set_key = rtl8xxxu_set_key,
7840 .ampdu_action = rtl8xxxu_ampdu_action,
7841 };
7842
7843 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
7844 struct usb_interface *interface)
7845 {
7846 struct usb_interface_descriptor *interface_desc;
7847 struct usb_host_interface *host_interface;
7848 struct usb_endpoint_descriptor *endpoint;
7849 struct device *dev = &priv->udev->dev;
7850 int i, j = 0, endpoints;
7851 u8 dir, xtype, num;
7852 int ret = 0;
7853
7854 host_interface = &interface->altsetting[0];
7855 interface_desc = &host_interface->desc;
7856 endpoints = interface_desc->bNumEndpoints;
7857
7858 for (i = 0; i < endpoints; i++) {
7859 endpoint = &host_interface->endpoint[i].desc;
7860
7861 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
7862 num = usb_endpoint_num(endpoint);
7863 xtype = usb_endpoint_type(endpoint);
7864 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7865 dev_dbg(dev,
7866 "%s: endpoint: dir %02x, # %02x, type %02x\n",
7867 __func__, dir, num, xtype);
7868 if (usb_endpoint_dir_in(endpoint) &&
7869 usb_endpoint_xfer_bulk(endpoint)) {
7870 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7871 dev_dbg(dev, "%s: in endpoint num %i\n",
7872 __func__, num);
7873
7874 if (priv->pipe_in) {
7875 dev_warn(dev,
7876 "%s: Too many IN pipes\n", __func__);
7877 ret = -EINVAL;
7878 goto exit;
7879 }
7880
7881 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
7882 }
7883
7884 if (usb_endpoint_dir_in(endpoint) &&
7885 usb_endpoint_xfer_int(endpoint)) {
7886 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7887 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
7888 __func__, num);
7889
7890 if (priv->pipe_interrupt) {
7891 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
7892 __func__);
7893 ret = -EINVAL;
7894 goto exit;
7895 }
7896
7897 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
7898 }
7899
7900 if (usb_endpoint_dir_out(endpoint) &&
7901 usb_endpoint_xfer_bulk(endpoint)) {
7902 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7903 dev_dbg(dev, "%s: out endpoint num %i\n",
7904 __func__, num);
7905 if (j >= RTL8XXXU_OUT_ENDPOINTS) {
7906 dev_warn(dev,
7907 "%s: Too many OUT pipes\n", __func__);
7908 ret = -EINVAL;
7909 goto exit;
7910 }
7911 priv->out_ep[j++] = num;
7912 }
7913 }
7914 exit:
7915 priv->nr_out_eps = j;
7916 return ret;
7917 }
7918
7919 static int rtl8xxxu_probe(struct usb_interface *interface,
7920 const struct usb_device_id *id)
7921 {
7922 struct rtl8xxxu_priv *priv;
7923 struct ieee80211_hw *hw;
7924 struct usb_device *udev;
7925 struct ieee80211_supported_band *sband;
7926 int ret = 0;
7927 int untested = 1;
7928
7929 udev = usb_get_dev(interface_to_usbdev(interface));
7930
7931 switch (id->idVendor) {
7932 case USB_VENDOR_ID_REALTEK:
7933 switch(id->idProduct) {
7934 case 0x1724:
7935 case 0x8176:
7936 case 0x8178:
7937 case 0x817f:
7938 untested = 0;
7939 break;
7940 }
7941 break;
7942 case 0x7392:
7943 if (id->idProduct == 0x7811)
7944 untested = 0;
7945 break;
7946 default:
7947 break;
7948 }
7949
7950 if (untested) {
7951 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE;
7952 dev_info(&udev->dev,
7953 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
7954 id->idVendor, id->idProduct);
7955 dev_info(&udev->dev,
7956 "Please report results to Jes.Sorensen@gmail.com\n");
7957 }
7958
7959 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
7960 if (!hw) {
7961 ret = -ENOMEM;
7962 goto exit;
7963 }
7964
7965 priv = hw->priv;
7966 priv->hw = hw;
7967 priv->udev = udev;
7968 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
7969 mutex_init(&priv->usb_buf_mutex);
7970 mutex_init(&priv->h2c_mutex);
7971 INIT_LIST_HEAD(&priv->tx_urb_free_list);
7972 spin_lock_init(&priv->tx_urb_lock);
7973 INIT_LIST_HEAD(&priv->rx_urb_pending_list);
7974 spin_lock_init(&priv->rx_urb_lock);
7975 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
7976
7977 usb_set_intfdata(interface, hw);
7978
7979 ret = rtl8xxxu_parse_usb(priv, interface);
7980 if (ret)
7981 goto exit;
7982
7983 ret = rtl8xxxu_identify_chip(priv);
7984 if (ret) {
7985 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
7986 goto exit;
7987 }
7988
7989 ret = rtl8xxxu_read_efuse(priv);
7990 if (ret) {
7991 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
7992 goto exit;
7993 }
7994
7995 ret = priv->fops->parse_efuse(priv);
7996 if (ret) {
7997 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
7998 goto exit;
7999 }
8000
8001 rtl8xxxu_print_chipinfo(priv);
8002
8003 ret = priv->fops->load_firmware(priv);
8004 if (ret) {
8005 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
8006 goto exit;
8007 }
8008
8009 ret = rtl8xxxu_init_device(hw);
8010
8011 hw->wiphy->max_scan_ssids = 1;
8012 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
8013 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
8014 hw->queues = 4;
8015
8016 sband = &rtl8xxxu_supported_band;
8017 sband->ht_cap.ht_supported = true;
8018 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
8019 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
8020 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
8021 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
8022 sband->ht_cap.mcs.rx_mask[0] = 0xff;
8023 sband->ht_cap.mcs.rx_mask[4] = 0x01;
8024 if (priv->rf_paths > 1) {
8025 sband->ht_cap.mcs.rx_mask[1] = 0xff;
8026 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
8027 }
8028 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
8029 /*
8030 * Some APs will negotiate HT20_40 in a noisy environment leading
8031 * to miserable performance. Rather than defaulting to this, only
8032 * enable it if explicitly requested at module load time.
8033 */
8034 if (rtl8xxxu_ht40_2g) {
8035 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
8036 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
8037 }
8038 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
8039
8040 hw->wiphy->rts_threshold = 2347;
8041
8042 SET_IEEE80211_DEV(priv->hw, &interface->dev);
8043 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
8044
8045 hw->extra_tx_headroom = sizeof(struct rtl8xxxu_tx_desc);
8046 ieee80211_hw_set(hw, SIGNAL_DBM);
8047 /*
8048 * The firmware handles rate control
8049 */
8050 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
8051 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
8052
8053 ret = ieee80211_register_hw(priv->hw);
8054 if (ret) {
8055 dev_err(&udev->dev, "%s: Failed to register: %i\n",
8056 __func__, ret);
8057 goto exit;
8058 }
8059
8060 exit:
8061 if (ret < 0)
8062 usb_put_dev(udev);
8063 return ret;
8064 }
8065
8066 static void rtl8xxxu_disconnect(struct usb_interface *interface)
8067 {
8068 struct rtl8xxxu_priv *priv;
8069 struct ieee80211_hw *hw;
8070
8071 hw = usb_get_intfdata(interface);
8072 priv = hw->priv;
8073
8074 rtl8xxxu_disable_device(hw);
8075 usb_set_intfdata(interface, NULL);
8076
8077 dev_info(&priv->udev->dev, "disconnecting\n");
8078
8079 ieee80211_unregister_hw(hw);
8080
8081 kfree(priv->fw_data);
8082 mutex_destroy(&priv->usb_buf_mutex);
8083 mutex_destroy(&priv->h2c_mutex);
8084
8085 usb_put_dev(priv->udev);
8086 ieee80211_free_hw(hw);
8087 }
8088
8089 static struct rtl8xxxu_fileops rtl8723au_fops = {
8090 .parse_efuse = rtl8723au_parse_efuse,
8091 .load_firmware = rtl8723au_load_firmware,
8092 .power_on = rtl8723au_power_on,
8093 .llt_init = rtl8xxxu_init_llt_table,
8094 .phy_iq_calibrate = rtl8723au_phy_iq_calibrate,
8095 .config_channel = rtl8723au_config_channel,
8096 .parse_rx_desc = rtl8723au_parse_rx_desc,
8097 .enable_rf = rtl8723a_enable_rf,
8098 .set_tx_power = rtl8723a_set_tx_power,
8099 .writeN_block_size = 1024,
8100 .mbox_ext_reg = REG_HMBOX_EXT_0,
8101 .mbox_ext_width = 2,
8102 .adda_1t_init = 0x0b1b25a0,
8103 .adda_1t_path_on = 0x0bdb25a0,
8104 .adda_2t_path_on_a = 0x04db25a4,
8105 .adda_2t_path_on_b = 0x0b1b25a4,
8106 };
8107
8108 static struct rtl8xxxu_fileops rtl8723bu_fops = {
8109 .parse_efuse = rtl8723bu_parse_efuse,
8110 .load_firmware = rtl8723bu_load_firmware,
8111 .power_on = rtl8723bu_power_on,
8112 .llt_init = rtl8xxxu_auto_llt_table,
8113 .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection,
8114 .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
8115 .config_channel = rtl8723bu_config_channel,
8116 .init_bt = rtl8723bu_init_bt,
8117 .parse_rx_desc = rtl8723bu_parse_rx_desc,
8118 .init_aggregation = rtl8723bu_init_aggregation,
8119 .init_statistics = rtl8723bu_init_statistics,
8120 .enable_rf = rtl8723b_enable_rf,
8121 .set_tx_power = rtl8723b_set_tx_power,
8122 .writeN_block_size = 1024,
8123 .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
8124 .mbox_ext_width = 4,
8125 .has_s0s1 = 1,
8126 .adda_1t_init = 0x01c00014,
8127 .adda_1t_path_on = 0x01c00014,
8128 .adda_2t_path_on_a = 0x01c00014,
8129 .adda_2t_path_on_b = 0x01c00014,
8130 };
8131
8132 #ifdef CONFIG_RTL8XXXU_UNTESTED
8133
8134 static struct rtl8xxxu_fileops rtl8192cu_fops = {
8135 .parse_efuse = rtl8192cu_parse_efuse,
8136 .load_firmware = rtl8192cu_load_firmware,
8137 .power_on = rtl8192cu_power_on,
8138 .llt_init = rtl8xxxu_init_llt_table,
8139 .phy_iq_calibrate = rtl8723au_phy_iq_calibrate,
8140 .config_channel = rtl8723au_config_channel,
8141 .parse_rx_desc = rtl8723au_parse_rx_desc,
8142 .enable_rf = rtl8723a_enable_rf,
8143 .set_tx_power = rtl8723a_set_tx_power,
8144 .writeN_block_size = 128,
8145 .mbox_ext_reg = REG_HMBOX_EXT_0,
8146 .mbox_ext_width = 2,
8147 .adda_1t_init = 0x0b1b25a0,
8148 .adda_1t_path_on = 0x0bdb25a0,
8149 .adda_2t_path_on_a = 0x04db25a4,
8150 .adda_2t_path_on_b = 0x0b1b25a4,
8151 };
8152
8153 #endif
8154
8155 static struct rtl8xxxu_fileops rtl8192eu_fops = {
8156 .parse_efuse = rtl8192eu_parse_efuse,
8157 .load_firmware = rtl8192eu_load_firmware,
8158 .power_on = rtl8192eu_power_on,
8159 .llt_init = rtl8xxxu_auto_llt_table,
8160 .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
8161 .config_channel = rtl8723bu_config_channel,
8162 .parse_rx_desc = rtl8723bu_parse_rx_desc,
8163 .enable_rf = rtl8723b_enable_rf,
8164 .set_tx_power = rtl8723b_set_tx_power,
8165 .writeN_block_size = 128,
8166 .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
8167 .mbox_ext_width = 4,
8168 .has_s0s1 = 1,
8169 .adda_1t_init = 0x0fc01616,
8170 .adda_1t_path_on = 0x0fc01616,
8171 .adda_2t_path_on_a = 0x0fc01616,
8172 .adda_2t_path_on_b = 0x0fc01616,
8173 };
8174
8175 static struct usb_device_id dev_table[] = {
8176 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
8177 .driver_info = (unsigned long)&rtl8723au_fops},
8178 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
8179 .driver_info = (unsigned long)&rtl8723au_fops},
8180 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
8181 .driver_info = (unsigned long)&rtl8723au_fops},
8182 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
8183 .driver_info = (unsigned long)&rtl8192eu_fops},
8184 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
8185 .driver_info = (unsigned long)&rtl8723bu_fops},
8186 #ifdef CONFIG_RTL8XXXU_UNTESTED
8187 /* Still supported by rtlwifi */
8188 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
8189 .driver_info = (unsigned long)&rtl8192cu_fops},
8190 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
8191 .driver_info = (unsigned long)&rtl8192cu_fops},
8192 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
8193 .driver_info = (unsigned long)&rtl8192cu_fops},
8194 /* Tested by Larry Finger */
8195 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
8196 .driver_info = (unsigned long)&rtl8192cu_fops},
8197 /* Currently untested 8188 series devices */
8198 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
8199 .driver_info = (unsigned long)&rtl8192cu_fops},
8200 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
8201 .driver_info = (unsigned long)&rtl8192cu_fops},
8202 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
8203 .driver_info = (unsigned long)&rtl8192cu_fops},
8204 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
8205 .driver_info = (unsigned long)&rtl8192cu_fops},
8206 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
8207 .driver_info = (unsigned long)&rtl8192cu_fops},
8208 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
8209 .driver_info = (unsigned long)&rtl8192cu_fops},
8210 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
8211 .driver_info = (unsigned long)&rtl8192cu_fops},
8212 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
8213 .driver_info = (unsigned long)&rtl8192cu_fops},
8214 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
8215 .driver_info = (unsigned long)&rtl8192cu_fops},
8216 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
8217 .driver_info = (unsigned long)&rtl8192cu_fops},
8218 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
8219 .driver_info = (unsigned long)&rtl8192cu_fops},
8220 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
8221 .driver_info = (unsigned long)&rtl8192cu_fops},
8222 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
8223 .driver_info = (unsigned long)&rtl8192cu_fops},
8224 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
8225 .driver_info = (unsigned long)&rtl8192cu_fops},
8226 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
8227 .driver_info = (unsigned long)&rtl8192cu_fops},
8228 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
8229 .driver_info = (unsigned long)&rtl8192cu_fops},
8230 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
8231 .driver_info = (unsigned long)&rtl8192cu_fops},
8232 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
8233 .driver_info = (unsigned long)&rtl8192cu_fops},
8234 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
8235 .driver_info = (unsigned long)&rtl8192cu_fops},
8236 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
8237 .driver_info = (unsigned long)&rtl8192cu_fops},
8238 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
8239 .driver_info = (unsigned long)&rtl8192cu_fops},
8240 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
8241 .driver_info = (unsigned long)&rtl8192cu_fops},
8242 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
8243 .driver_info = (unsigned long)&rtl8192cu_fops},
8244 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
8245 .driver_info = (unsigned long)&rtl8192cu_fops},
8246 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
8247 .driver_info = (unsigned long)&rtl8192cu_fops},
8248 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
8249 .driver_info = (unsigned long)&rtl8192cu_fops},
8250 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
8251 .driver_info = (unsigned long)&rtl8192cu_fops},
8252 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
8253 .driver_info = (unsigned long)&rtl8192cu_fops},
8254 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
8255 .driver_info = (unsigned long)&rtl8192cu_fops},
8256 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
8257 .driver_info = (unsigned long)&rtl8192cu_fops},
8258 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
8259 .driver_info = (unsigned long)&rtl8192cu_fops},
8260 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
8261 .driver_info = (unsigned long)&rtl8192cu_fops},
8262 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
8263 .driver_info = (unsigned long)&rtl8192cu_fops},
8264 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
8265 .driver_info = (unsigned long)&rtl8192cu_fops},
8266 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
8267 .driver_info = (unsigned long)&rtl8192cu_fops},
8268 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
8269 .driver_info = (unsigned long)&rtl8192cu_fops},
8270 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
8271 .driver_info = (unsigned long)&rtl8192cu_fops},
8272 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
8273 .driver_info = (unsigned long)&rtl8192cu_fops},
8274 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
8275 .driver_info = (unsigned long)&rtl8192cu_fops},
8276 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
8277 .driver_info = (unsigned long)&rtl8192cu_fops},
8278 /* Currently untested 8192 series devices */
8279 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
8280 .driver_info = (unsigned long)&rtl8192cu_fops},
8281 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
8282 .driver_info = (unsigned long)&rtl8192cu_fops},
8283 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
8284 .driver_info = (unsigned long)&rtl8192cu_fops},
8285 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
8286 .driver_info = (unsigned long)&rtl8192cu_fops},
8287 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
8288 .driver_info = (unsigned long)&rtl8192cu_fops},
8289 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
8290 .driver_info = (unsigned long)&rtl8192cu_fops},
8291 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
8292 .driver_info = (unsigned long)&rtl8192cu_fops},
8293 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
8294 .driver_info = (unsigned long)&rtl8192cu_fops},
8295 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
8296 .driver_info = (unsigned long)&rtl8192cu_fops},
8297 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
8298 .driver_info = (unsigned long)&rtl8192cu_fops},
8299 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
8300 .driver_info = (unsigned long)&rtl8192cu_fops},
8301 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
8302 .driver_info = (unsigned long)&rtl8192cu_fops},
8303 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
8304 .driver_info = (unsigned long)&rtl8192cu_fops},
8305 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
8306 .driver_info = (unsigned long)&rtl8192cu_fops},
8307 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
8308 .driver_info = (unsigned long)&rtl8192cu_fops},
8309 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
8310 .driver_info = (unsigned long)&rtl8192cu_fops},
8311 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
8312 .driver_info = (unsigned long)&rtl8192cu_fops},
8313 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
8314 .driver_info = (unsigned long)&rtl8192cu_fops},
8315 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
8316 .driver_info = (unsigned long)&rtl8192cu_fops},
8317 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
8318 .driver_info = (unsigned long)&rtl8192cu_fops},
8319 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
8320 .driver_info = (unsigned long)&rtl8192cu_fops},
8321 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
8322 .driver_info = (unsigned long)&rtl8192cu_fops},
8323 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
8324 .driver_info = (unsigned long)&rtl8192cu_fops},
8325 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
8326 .driver_info = (unsigned long)&rtl8192cu_fops},
8327 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
8328 .driver_info = (unsigned long)&rtl8192cu_fops},
8329 #endif
8330 { }
8331 };
8332
8333 static struct usb_driver rtl8xxxu_driver = {
8334 .name = DRIVER_NAME,
8335 .probe = rtl8xxxu_probe,
8336 .disconnect = rtl8xxxu_disconnect,
8337 .id_table = dev_table,
8338 .disable_hub_initiated_lpm = 1,
8339 };
8340
8341 static int __init rtl8xxxu_module_init(void)
8342 {
8343 int res;
8344
8345 res = usb_register(&rtl8xxxu_driver);
8346 if (res < 0)
8347 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
8348
8349 return res;
8350 }
8351
8352 static void __exit rtl8xxxu_module_exit(void)
8353 {
8354 usb_deregister(&rtl8xxxu_driver);
8355 }
8356
8357
8358 MODULE_DEVICE_TABLE(usb, dev_table);
8359
8360 module_init(rtl8xxxu_module_init);
8361 module_exit(rtl8xxxu_module_exit);
Linux kernel - Deliverables
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