2 * RTL8XXXU mac80211 USB driver
4 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
6 * Portions, notably calibration code:
7 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
9 * This driver was written as a replacement for the vendor provided
10 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
11 * their programming interface, I have started adding support for
12 * additional 8xxx chips like the 8192cu, 8188cus, etc.
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of version 2 of the GNU General Public License as
16 * published by the Free Software Foundation.
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
24 #include <linux/init.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/errno.h>
28 #include <linux/slab.h>
29 #include <linux/module.h>
30 #include <linux/spinlock.h>
31 #include <linux/list.h>
32 #include <linux/usb.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/wireless.h>
37 #include <linux/firmware.h>
38 #include <linux/moduleparam.h>
39 #include <net/mac80211.h>
41 #include "rtl8xxxu_regs.h"
43 #define DRIVER_NAME "rtl8xxxu"
45 static int rtl8xxxu_debug
= RTL8XXXU_DEBUG_EFUSE
;
46 static bool rtl8xxxu_ht40_2g
;
48 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
49 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
50 MODULE_LICENSE("GPL");
51 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
52 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
53 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
54 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
55 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
56 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
57 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
58 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
59 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
61 module_param_named(debug
, rtl8xxxu_debug
, int, 0600);
62 MODULE_PARM_DESC(debug
, "Set debug mask");
63 module_param_named(ht40_2g
, rtl8xxxu_ht40_2g
, bool, 0600);
64 MODULE_PARM_DESC(ht40_2g
, "Enable HT40 support on the 2.4GHz band");
66 #define USB_VENDOR_ID_REALTEK 0x0bda
67 /* Minimum IEEE80211_MAX_FRAME_LEN */
68 #define RTL_RX_BUFFER_SIZE IEEE80211_MAX_FRAME_LEN
69 #define RTL8XXXU_RX_URBS 32
70 #define RTL8XXXU_RX_URB_PENDING_WATER 8
71 #define RTL8XXXU_TX_URBS 64
72 #define RTL8XXXU_TX_URB_LOW_WATER 25
73 #define RTL8XXXU_TX_URB_HIGH_WATER 32
75 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv
*priv
,
76 struct rtl8xxxu_rx_urb
*rx_urb
);
78 static struct ieee80211_rate rtl8xxxu_rates
[] = {
79 { .bitrate
= 10, .hw_value
= DESC_RATE_1M
, .flags
= 0 },
80 { .bitrate
= 20, .hw_value
= DESC_RATE_2M
, .flags
= 0 },
81 { .bitrate
= 55, .hw_value
= DESC_RATE_5_5M
, .flags
= 0 },
82 { .bitrate
= 110, .hw_value
= DESC_RATE_11M
, .flags
= 0 },
83 { .bitrate
= 60, .hw_value
= DESC_RATE_6M
, .flags
= 0 },
84 { .bitrate
= 90, .hw_value
= DESC_RATE_9M
, .flags
= 0 },
85 { .bitrate
= 120, .hw_value
= DESC_RATE_12M
, .flags
= 0 },
86 { .bitrate
= 180, .hw_value
= DESC_RATE_18M
, .flags
= 0 },
87 { .bitrate
= 240, .hw_value
= DESC_RATE_24M
, .flags
= 0 },
88 { .bitrate
= 360, .hw_value
= DESC_RATE_36M
, .flags
= 0 },
89 { .bitrate
= 480, .hw_value
= DESC_RATE_48M
, .flags
= 0 },
90 { .bitrate
= 540, .hw_value
= DESC_RATE_54M
, .flags
= 0 },
93 static struct ieee80211_channel rtl8xxxu_channels_2g
[] = {
94 { .band
= IEEE80211_BAND_2GHZ
, .center_freq
= 2412,
95 .hw_value
= 1, .max_power
= 30 },
96 { .band
= IEEE80211_BAND_2GHZ
, .center_freq
= 2417,
97 .hw_value
= 2, .max_power
= 30 },
98 { .band
= IEEE80211_BAND_2GHZ
, .center_freq
= 2422,
99 .hw_value
= 3, .max_power
= 30 },
100 { .band
= IEEE80211_BAND_2GHZ
, .center_freq
= 2427,
101 .hw_value
= 4, .max_power
= 30 },
102 { .band
= IEEE80211_BAND_2GHZ
, .center_freq
= 2432,
103 .hw_value
= 5, .max_power
= 30 },
104 { .band
= IEEE80211_BAND_2GHZ
, .center_freq
= 2437,
105 .hw_value
= 6, .max_power
= 30 },
106 { .band
= IEEE80211_BAND_2GHZ
, .center_freq
= 2442,
107 .hw_value
= 7, .max_power
= 30 },
108 { .band
= IEEE80211_BAND_2GHZ
, .center_freq
= 2447,
109 .hw_value
= 8, .max_power
= 30 },
110 { .band
= IEEE80211_BAND_2GHZ
, .center_freq
= 2452,
111 .hw_value
= 9, .max_power
= 30 },
112 { .band
= IEEE80211_BAND_2GHZ
, .center_freq
= 2457,
113 .hw_value
= 10, .max_power
= 30 },
114 { .band
= IEEE80211_BAND_2GHZ
, .center_freq
= 2462,
115 .hw_value
= 11, .max_power
= 30 },
116 { .band
= IEEE80211_BAND_2GHZ
, .center_freq
= 2467,
117 .hw_value
= 12, .max_power
= 30 },
118 { .band
= IEEE80211_BAND_2GHZ
, .center_freq
= 2472,
119 .hw_value
= 13, .max_power
= 30 },
120 { .band
= IEEE80211_BAND_2GHZ
, .center_freq
= 2484,
121 .hw_value
= 14, .max_power
= 30 }
124 static struct ieee80211_supported_band rtl8xxxu_supported_band
= {
125 .channels
= rtl8xxxu_channels_2g
,
126 .n_channels
= ARRAY_SIZE(rtl8xxxu_channels_2g
),
127 .bitrates
= rtl8xxxu_rates
,
128 .n_bitrates
= ARRAY_SIZE(rtl8xxxu_rates
),
131 static struct rtl8xxxu_reg8val rtl8723a_mac_init_table
[] = {
132 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
133 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
134 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
135 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
136 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
137 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
138 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
139 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
140 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
141 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
142 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
143 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
144 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
145 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
146 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
147 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
148 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
149 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
150 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
151 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
152 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
153 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
156 static struct rtl8xxxu_reg8val rtl8723b_mac_init_table
[] = {
157 {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0},
158 {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10},
159 {0x430, 0x00}, {0x431, 0x00},
160 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
161 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
162 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
163 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
164 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
165 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
166 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
167 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
168 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
169 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
170 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
171 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
172 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
173 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
174 {0x516, 0x0a}, {0x525, 0x4f},
175 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50},
176 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
177 {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff},
178 {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff},
179 {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
180 {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00},
181 {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
182 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
183 {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04},
187 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table
[] = {
188 {0x800, 0x80040000}, {0x804, 0x00000003},
189 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
190 {0x810, 0x10001331}, {0x814, 0x020c3d10},
191 {0x818, 0x02200385}, {0x81c, 0x00000000},
192 {0x820, 0x01000100}, {0x824, 0x00390004},
193 {0x828, 0x00000000}, {0x82c, 0x00000000},
194 {0x830, 0x00000000}, {0x834, 0x00000000},
195 {0x838, 0x00000000}, {0x83c, 0x00000000},
196 {0x840, 0x00010000}, {0x844, 0x00000000},
197 {0x848, 0x00000000}, {0x84c, 0x00000000},
198 {0x850, 0x00000000}, {0x854, 0x00000000},
199 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
200 {0x860, 0x66f60110}, {0x864, 0x061f0130},
201 {0x868, 0x00000000}, {0x86c, 0x32323200},
202 {0x870, 0x07000760}, {0x874, 0x22004000},
203 {0x878, 0x00000808}, {0x87c, 0x00000000},
204 {0x880, 0xc0083070}, {0x884, 0x000004d5},
205 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
206 {0x890, 0x00000800}, {0x894, 0xfffffffe},
207 {0x898, 0x40302010}, {0x89c, 0x00706050},
208 {0x900, 0x00000000}, {0x904, 0x00000023},
209 {0x908, 0x00000000}, {0x90c, 0x81121111},
210 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
211 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
212 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
213 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
214 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
215 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
216 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
218 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
219 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
220 {0xc10, 0x08800000}, {0xc14, 0x40000100},
221 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
222 {0xc20, 0x00000000}, {0xc24, 0x00000000},
223 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
224 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
225 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
226 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
227 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
228 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
229 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
230 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
231 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
232 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
233 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
234 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
235 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
236 {0xc90, 0x00121820}, {0xc94, 0x00000000},
237 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
238 {0xca0, 0x00000000}, {0xca4, 0x00000080},
239 {0xca8, 0x00000000}, {0xcac, 0x00000000},
240 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
241 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
242 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
243 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
244 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
245 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
246 {0xce0, 0x00222222}, {0xce4, 0x00000000},
247 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
248 {0xd00, 0x00080740}, {0xd04, 0x00020401},
249 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
250 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
251 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
252 {0xd30, 0x00000000}, {0xd34, 0x80608000},
253 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
254 {0xd40, 0x00000000}, {0xd44, 0x00000000},
255 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
256 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
257 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
258 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
259 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
260 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
261 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
262 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
263 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
264 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
265 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
266 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
267 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
268 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
269 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
270 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
271 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
272 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
273 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
274 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
275 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
276 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
277 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
278 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
279 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
280 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
282 {0xffff, 0xffffffff},
285 static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table
[] = {
286 {0x800, 0x80040000}, {0x804, 0x00000003},
287 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
288 {0x810, 0x10001331}, {0x814, 0x020c3d10},
289 {0x818, 0x02200385}, {0x81c, 0x00000000},
290 {0x820, 0x01000100}, {0x824, 0x00190204},
291 {0x828, 0x00000000}, {0x82c, 0x00000000},
292 {0x830, 0x00000000}, {0x834, 0x00000000},
293 {0x838, 0x00000000}, {0x83c, 0x00000000},
294 {0x840, 0x00010000}, {0x844, 0x00000000},
295 {0x848, 0x00000000}, {0x84c, 0x00000000},
296 {0x850, 0x00000000}, {0x854, 0x00000000},
297 {0x858, 0x569a11a9}, {0x85c, 0x01000014},
298 {0x860, 0x66f60110}, {0x864, 0x061f0649},
299 {0x868, 0x00000000}, {0x86c, 0x27272700},
300 {0x870, 0x07000760}, {0x874, 0x25004000},
301 {0x878, 0x00000808}, {0x87c, 0x00000000},
302 {0x880, 0xb0000c1c}, {0x884, 0x00000001},
303 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
304 {0x890, 0x00000800}, {0x894, 0xfffffffe},
305 {0x898, 0x40302010}, {0x89c, 0x00706050},
306 {0x900, 0x00000000}, {0x904, 0x00000023},
307 {0x908, 0x00000000}, {0x90c, 0x81121111},
308 {0x910, 0x00000002}, {0x914, 0x00000201},
309 {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},
310 {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},
311 {0xa10, 0x9500bb78}, {0xa14, 0x1114d028},
312 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
313 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
314 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
315 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
316 {0xa78, 0x00000900}, {0xa7c, 0x225b0606},
317 {0xa80, 0x21806490}, {0xb2c, 0x00000000},
318 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
319 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
320 {0xc10, 0x08800000}, {0xc14, 0x40000100},
321 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
322 {0xc20, 0x00000000}, {0xc24, 0x00000000},
323 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
324 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
325 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
326 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
327 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
328 {0xc50, 0x69553420}, {0xc54, 0x43bc0094},
329 {0xc58, 0x00013149}, {0xc5c, 0x00250492},
330 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
331 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
332 {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},
333 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
334 {0xc80, 0x390000e4}, {0xc84, 0x20f60000},
335 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
336 {0xc90, 0x00020e1a}, {0xc94, 0x00000000},
337 {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f},
338 {0xca0, 0x00000000}, {0xca4, 0x000300a0},
339 {0xca8, 0x00000000}, {0xcac, 0x00000000},
340 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
341 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
342 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
343 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
344 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
345 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
346 {0xce0, 0x00222222}, {0xce4, 0x00000000},
347 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
348 {0xd00, 0x00000740}, {0xd04, 0x40020401},
349 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
350 {0xd10, 0xa0633333}, {0xd14, 0x3333bc53},
351 {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},
352 {0xd30, 0x00000000}, {0xd34, 0x80608000},
353 {0xd38, 0x00000000}, {0xd3c, 0x00127353},
354 {0xd40, 0x00000000}, {0xd44, 0x00000000},
355 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
356 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
357 {0xd58, 0x00000282}, {0xd5c, 0x30032064},
358 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
359 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
360 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
361 {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},
362 {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},
363 {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},
364 {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},
365 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
366 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
367 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
368 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
369 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
370 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
371 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
372 {0xe68, 0x001b2556}, {0xe6c, 0x00c00096},
373 {0xe70, 0x00c00096}, {0xe74, 0x01000056},
374 {0xe78, 0x01000014}, {0xe7c, 0x01000056},
375 {0xe80, 0x01000014}, {0xe84, 0x00c00096},
376 {0xe88, 0x01000056}, {0xe8c, 0x00c00096},
377 {0xed0, 0x00c00096}, {0xed4, 0x00c00096},
378 {0xed8, 0x00c00096}, {0xedc, 0x000000d6},
379 {0xee0, 0x000000d6}, {0xeec, 0x01c00016},
380 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
382 {0x820, 0x01000100}, {0x800, 0x83040000},
383 {0xffff, 0xffffffff},
386 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table
[] = {
387 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
388 {0x800, 0x80040002}, {0x804, 0x00000003},
389 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
390 {0x810, 0x10000330}, {0x814, 0x020c3d10},
391 {0x818, 0x02200385}, {0x81c, 0x00000000},
392 {0x820, 0x01000100}, {0x824, 0x00390004},
393 {0x828, 0x01000100}, {0x82c, 0x00390004},
394 {0x830, 0x27272727}, {0x834, 0x27272727},
395 {0x838, 0x27272727}, {0x83c, 0x27272727},
396 {0x840, 0x00010000}, {0x844, 0x00010000},
397 {0x848, 0x27272727}, {0x84c, 0x27272727},
398 {0x850, 0x00000000}, {0x854, 0x00000000},
399 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
400 {0x860, 0x66e60230}, {0x864, 0x061f0130},
401 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
402 {0x870, 0x07000700}, {0x874, 0x22184000},
403 {0x878, 0x08080808}, {0x87c, 0x00000000},
404 {0x880, 0xc0083070}, {0x884, 0x000004d5},
405 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
406 {0x890, 0x00000800}, {0x894, 0xfffffffe},
407 {0x898, 0x40302010}, {0x89c, 0x00706050},
408 {0x900, 0x00000000}, {0x904, 0x00000023},
409 {0x908, 0x00000000}, {0x90c, 0x81121313},
410 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
411 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
412 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
413 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
414 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
415 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
416 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
417 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
418 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
419 {0xc10, 0x08800000}, {0xc14, 0x40000100},
420 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
421 {0xc20, 0x00000000}, {0xc24, 0x00000000},
422 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
423 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
424 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
425 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
426 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
427 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
428 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
429 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
430 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
431 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
432 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
433 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
434 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
435 {0xc90, 0x00121820}, {0xc94, 0x00000000},
436 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
437 {0xca0, 0x00000000}, {0xca4, 0x00000080},
438 {0xca8, 0x00000000}, {0xcac, 0x00000000},
439 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
440 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
441 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
442 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
443 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
444 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
445 {0xce0, 0x00222222}, {0xce4, 0x00000000},
446 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
447 {0xd00, 0x00080740}, {0xd04, 0x00020403},
448 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
449 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
450 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
451 {0xd30, 0x00000000}, {0xd34, 0x80608000},
452 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
453 {0xd40, 0x00000000}, {0xd44, 0x00000000},
454 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
455 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
456 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
457 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
458 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
459 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
460 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
461 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
462 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
463 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
464 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
465 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
466 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
467 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
468 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
469 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
470 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
471 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
472 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
473 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
474 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
475 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
476 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
477 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
478 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
479 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
481 {0xffff, 0xffffffff},
484 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table
[] = {
485 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
486 {0x040, 0x000c0004}, {0x800, 0x80040000},
487 {0x804, 0x00000001}, {0x808, 0x0000fc00},
488 {0x80c, 0x0000000a}, {0x810, 0x10005388},
489 {0x814, 0x020c3d10}, {0x818, 0x02200385},
490 {0x81c, 0x00000000}, {0x820, 0x01000100},
491 {0x824, 0x00390204}, {0x828, 0x00000000},
492 {0x82c, 0x00000000}, {0x830, 0x00000000},
493 {0x834, 0x00000000}, {0x838, 0x00000000},
494 {0x83c, 0x00000000}, {0x840, 0x00010000},
495 {0x844, 0x00000000}, {0x848, 0x00000000},
496 {0x84c, 0x00000000}, {0x850, 0x00000000},
497 {0x854, 0x00000000}, {0x858, 0x569a569a},
498 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
499 {0x864, 0x061f0130}, {0x868, 0x00000000},
500 {0x86c, 0x20202000}, {0x870, 0x03000300},
501 {0x874, 0x22004000}, {0x878, 0x00000808},
502 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
503 {0x884, 0x000004d5}, {0x888, 0x00000000},
504 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
505 {0x894, 0xfffffffe}, {0x898, 0x40302010},
506 {0x89c, 0x00706050}, {0x900, 0x00000000},
507 {0x904, 0x00000023}, {0x908, 0x00000000},
508 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
509 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
510 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
511 {0xa14, 0x11144028}, {0xa18, 0x00881117},
512 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
513 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
514 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
515 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
516 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
517 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
518 {0xc14, 0x40000100}, {0xc18, 0x08800000},
519 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
520 {0xc24, 0x00000000}, {0xc28, 0x00000000},
521 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
522 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
523 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
524 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
525 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
526 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
527 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
528 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
529 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
530 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
531 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
532 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
533 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
534 {0xc94, 0x00000000}, {0xc98, 0x00121820},
535 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
536 {0xca4, 0x00000080}, {0xca8, 0x00000000},
537 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
538 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
539 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
540 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
541 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
542 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
543 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
544 {0xce4, 0x00000000}, {0xce8, 0x37644302},
545 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
546 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
547 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
548 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
549 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
550 {0xd34, 0x80608000}, {0xd38, 0x00000000},
551 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
552 {0xd44, 0x00000000}, {0xd48, 0x00000000},
553 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
554 {0xd54, 0x00000000}, {0xd58, 0x00000000},
555 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
556 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
557 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
558 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
559 {0xe00, 0x24242424}, {0xe04, 0x24242424},
560 {0xe08, 0x03902024}, {0xe10, 0x24242424},
561 {0xe14, 0x24242424}, {0xe18, 0x24242424},
562 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
563 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
564 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
565 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
566 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
567 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
568 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
569 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
570 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
571 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
572 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
573 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
574 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
575 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
576 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
577 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
578 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
580 {0xffff, 0xffffffff},
583 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table
[] = {
584 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
585 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
586 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
587 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
588 {0xc78, 0x78080001}, {0xc78, 0x77090001},
589 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
590 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
591 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
592 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
593 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
594 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
595 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
596 {0xc78, 0x68180001}, {0xc78, 0x67190001},
597 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
598 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
599 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
600 {0xc78, 0x60200001}, {0xc78, 0x49210001},
601 {0xc78, 0x48220001}, {0xc78, 0x47230001},
602 {0xc78, 0x46240001}, {0xc78, 0x45250001},
603 {0xc78, 0x44260001}, {0xc78, 0x43270001},
604 {0xc78, 0x42280001}, {0xc78, 0x41290001},
605 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
606 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
607 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
608 {0xc78, 0x21300001}, {0xc78, 0x20310001},
609 {0xc78, 0x06320001}, {0xc78, 0x05330001},
610 {0xc78, 0x04340001}, {0xc78, 0x03350001},
611 {0xc78, 0x02360001}, {0xc78, 0x01370001},
612 {0xc78, 0x00380001}, {0xc78, 0x00390001},
613 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
614 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
615 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
616 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
617 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
618 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
619 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
620 {0xc78, 0x78480001}, {0xc78, 0x77490001},
621 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
622 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
623 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
624 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
625 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
626 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
627 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
628 {0xc78, 0x68580001}, {0xc78, 0x67590001},
629 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
630 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
631 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
632 {0xc78, 0x60600001}, {0xc78, 0x49610001},
633 {0xc78, 0x48620001}, {0xc78, 0x47630001},
634 {0xc78, 0x46640001}, {0xc78, 0x45650001},
635 {0xc78, 0x44660001}, {0xc78, 0x43670001},
636 {0xc78, 0x42680001}, {0xc78, 0x41690001},
637 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
638 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
639 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
640 {0xc78, 0x21700001}, {0xc78, 0x20710001},
641 {0xc78, 0x06720001}, {0xc78, 0x05730001},
642 {0xc78, 0x04740001}, {0xc78, 0x03750001},
643 {0xc78, 0x02760001}, {0xc78, 0x01770001},
644 {0xc78, 0x00780001}, {0xc78, 0x00790001},
645 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
646 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
647 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
648 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
649 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
650 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
651 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
652 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
653 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
654 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
655 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
656 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
657 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
658 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
659 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
660 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
661 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
662 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
663 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
667 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table
[] = {
668 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
669 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
670 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
671 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
672 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
673 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
674 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
675 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
676 {0xc78, 0x73100001}, {0xc78, 0x72110001},
677 {0xc78, 0x71120001}, {0xc78, 0x70130001},
678 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
679 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
680 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
681 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
682 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
683 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
684 {0xc78, 0x63200001}, {0xc78, 0x62210001},
685 {0xc78, 0x61220001}, {0xc78, 0x60230001},
686 {0xc78, 0x46240001}, {0xc78, 0x45250001},
687 {0xc78, 0x44260001}, {0xc78, 0x43270001},
688 {0xc78, 0x42280001}, {0xc78, 0x41290001},
689 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
690 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
691 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
692 {0xc78, 0x21300001}, {0xc78, 0x20310001},
693 {0xc78, 0x06320001}, {0xc78, 0x05330001},
694 {0xc78, 0x04340001}, {0xc78, 0x03350001},
695 {0xc78, 0x02360001}, {0xc78, 0x01370001},
696 {0xc78, 0x00380001}, {0xc78, 0x00390001},
697 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
698 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
699 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
700 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
701 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
702 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
703 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
704 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
705 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
706 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
707 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
708 {0xc78, 0x73500001}, {0xc78, 0x72510001},
709 {0xc78, 0x71520001}, {0xc78, 0x70530001},
710 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
711 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
712 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
713 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
714 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
715 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
716 {0xc78, 0x63600001}, {0xc78, 0x62610001},
717 {0xc78, 0x61620001}, {0xc78, 0x60630001},
718 {0xc78, 0x46640001}, {0xc78, 0x45650001},
719 {0xc78, 0x44660001}, {0xc78, 0x43670001},
720 {0xc78, 0x42680001}, {0xc78, 0x41690001},
721 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
722 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
723 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
724 {0xc78, 0x21700001}, {0xc78, 0x20710001},
725 {0xc78, 0x06720001}, {0xc78, 0x05730001},
726 {0xc78, 0x04740001}, {0xc78, 0x03750001},
727 {0xc78, 0x02760001}, {0xc78, 0x01770001},
728 {0xc78, 0x00780001}, {0xc78, 0x00790001},
729 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
730 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
731 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
732 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
733 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
734 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
735 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
736 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
737 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
738 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
739 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
740 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
741 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
742 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
743 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
744 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
745 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
746 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
747 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
751 static struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table
[] = {
752 {0xc78, 0xfd000001}, {0xc78, 0xfc010001},
753 {0xc78, 0xfb020001}, {0xc78, 0xfa030001},
754 {0xc78, 0xf9040001}, {0xc78, 0xf8050001},
755 {0xc78, 0xf7060001}, {0xc78, 0xf6070001},
756 {0xc78, 0xf5080001}, {0xc78, 0xf4090001},
757 {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001},
758 {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001},
759 {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001},
760 {0xc78, 0xed100001}, {0xc78, 0xec110001},
761 {0xc78, 0xeb120001}, {0xc78, 0xea130001},
762 {0xc78, 0xe9140001}, {0xc78, 0xe8150001},
763 {0xc78, 0xe7160001}, {0xc78, 0xe6170001},
764 {0xc78, 0xe5180001}, {0xc78, 0xe4190001},
765 {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001},
766 {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001},
767 {0xc78, 0x671e0001}, {0xc78, 0x661f0001},
768 {0xc78, 0x65200001}, {0xc78, 0x64210001},
769 {0xc78, 0x63220001}, {0xc78, 0x4a230001},
770 {0xc78, 0x49240001}, {0xc78, 0x48250001},
771 {0xc78, 0x47260001}, {0xc78, 0x46270001},
772 {0xc78, 0x45280001}, {0xc78, 0x44290001},
773 {0xc78, 0x432a0001}, {0xc78, 0x422b0001},
774 {0xc78, 0x292c0001}, {0xc78, 0x282d0001},
775 {0xc78, 0x272e0001}, {0xc78, 0x262f0001},
776 {0xc78, 0x0a300001}, {0xc78, 0x09310001},
777 {0xc78, 0x08320001}, {0xc78, 0x07330001},
778 {0xc78, 0x06340001}, {0xc78, 0x05350001},
779 {0xc78, 0x04360001}, {0xc78, 0x03370001},
780 {0xc78, 0x02380001}, {0xc78, 0x01390001},
781 {0xc78, 0x013a0001}, {0xc78, 0x013b0001},
782 {0xc78, 0x013c0001}, {0xc78, 0x013d0001},
783 {0xc78, 0x013e0001}, {0xc78, 0x013f0001},
784 {0xc78, 0xfc400001}, {0xc78, 0xfb410001},
785 {0xc78, 0xfa420001}, {0xc78, 0xf9430001},
786 {0xc78, 0xf8440001}, {0xc78, 0xf7450001},
787 {0xc78, 0xf6460001}, {0xc78, 0xf5470001},
788 {0xc78, 0xf4480001}, {0xc78, 0xf3490001},
789 {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001},
790 {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001},
791 {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001},
792 {0xc78, 0xec500001}, {0xc78, 0xeb510001},
793 {0xc78, 0xea520001}, {0xc78, 0xe9530001},
794 {0xc78, 0xe8540001}, {0xc78, 0xe7550001},
795 {0xc78, 0xe6560001}, {0xc78, 0xe5570001},
796 {0xc78, 0xe4580001}, {0xc78, 0xe3590001},
797 {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001},
798 {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001},
799 {0xc78, 0x675e0001}, {0xc78, 0x665f0001},
800 {0xc78, 0x65600001}, {0xc78, 0x64610001},
801 {0xc78, 0x63620001}, {0xc78, 0x62630001},
802 {0xc78, 0x61640001}, {0xc78, 0x48650001},
803 {0xc78, 0x47660001}, {0xc78, 0x46670001},
804 {0xc78, 0x45680001}, {0xc78, 0x44690001},
805 {0xc78, 0x436a0001}, {0xc78, 0x426b0001},
806 {0xc78, 0x286c0001}, {0xc78, 0x276d0001},
807 {0xc78, 0x266e0001}, {0xc78, 0x256f0001},
808 {0xc78, 0x24700001}, {0xc78, 0x09710001},
809 {0xc78, 0x08720001}, {0xc78, 0x07730001},
810 {0xc78, 0x06740001}, {0xc78, 0x05750001},
811 {0xc78, 0x04760001}, {0xc78, 0x03770001},
812 {0xc78, 0x02780001}, {0xc78, 0x01790001},
813 {0xc78, 0x017a0001}, {0xc78, 0x017b0001},
814 {0xc78, 0x017c0001}, {0xc78, 0x017d0001},
815 {0xc78, 0x017e0001}, {0xc78, 0x017f0001},
822 static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table
[] = {
823 {0x00, 0x00030159}, {0x01, 0x00031284},
824 {0x02, 0x00098000}, {0x03, 0x00039c63},
825 {0x04, 0x000210e7}, {0x09, 0x0002044f},
826 {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
827 {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
828 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
829 {0x19, 0x00000000}, {0x1a, 0x00030355},
830 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
831 {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
832 {0x1f, 0x00000000}, {0x20, 0x0000b614},
833 {0x21, 0x0006c000}, {0x22, 0x00000000},
834 {0x23, 0x00001558}, {0x24, 0x00000060},
835 {0x25, 0x00000483}, {0x26, 0x0004f000},
836 {0x27, 0x000ec7d9}, {0x28, 0x00057730},
837 {0x29, 0x00004783}, {0x2a, 0x00000001},
838 {0x2b, 0x00021334}, {0x2a, 0x00000000},
839 {0x2b, 0x00000054}, {0x2a, 0x00000001},
840 {0x2b, 0x00000808}, {0x2b, 0x00053333},
841 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
842 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
843 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
844 {0x2b, 0x00000808}, {0x2b, 0x00063333},
845 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
846 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
847 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
848 {0x2b, 0x00000808}, {0x2b, 0x00073333},
849 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
850 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
851 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
852 {0x2b, 0x00000709}, {0x2b, 0x00063333},
853 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
854 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
855 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
856 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
857 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
858 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
859 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
860 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
861 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
862 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
863 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
864 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
865 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
866 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
867 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
868 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
869 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
870 {0x10, 0x0002000f}, {0x11, 0x000203f9},
871 {0x10, 0x0003000f}, {0x11, 0x000ff500},
872 {0x10, 0x00000000}, {0x11, 0x00000000},
873 {0x10, 0x0008000f}, {0x11, 0x0003f100},
874 {0x10, 0x0009000f}, {0x11, 0x00023100},
875 {0x12, 0x00032000}, {0x12, 0x00071000},
876 {0x12, 0x000b0000}, {0x12, 0x000fc000},
877 {0x13, 0x000287b3}, {0x13, 0x000244b7},
878 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
879 {0x13, 0x00018493}, {0x13, 0x0001429b},
880 {0x13, 0x00010299}, {0x13, 0x0000c29c},
881 {0x13, 0x000081a0}, {0x13, 0x000040ac},
882 {0x13, 0x00000020}, {0x14, 0x0001944c},
883 {0x14, 0x00059444}, {0x14, 0x0009944c},
884 {0x14, 0x000d9444}, {0x15, 0x0000f474},
885 {0x15, 0x0004f477}, {0x15, 0x0008f455},
886 {0x15, 0x000cf455}, {0x16, 0x00000339},
887 {0x16, 0x00040339}, {0x16, 0x00080339},
888 {0x16, 0x000c0366}, {0x00, 0x00010159},
889 {0x18, 0x0000f401}, {0xfe, 0x00000000},
890 {0xfe, 0x00000000}, {0x1f, 0x00000003},
891 {0xfe, 0x00000000}, {0xfe, 0x00000000},
892 {0x1e, 0x00000247}, {0x1f, 0x00000000},
897 static struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table
[] = {
898 {0x00, 0x00010000}, {0xb0, 0x000dffe0},
899 {0xfe, 0x00000000}, {0xfe, 0x00000000},
900 {0xfe, 0x00000000}, {0xb1, 0x00000018},
901 {0xfe, 0x00000000}, {0xfe, 0x00000000},
902 {0xfe, 0x00000000}, {0xb2, 0x00084c00},
903 {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa},
904 {0xb7, 0x00000010}, {0xb8, 0x0000907f},
905 {0x5c, 0x00000002}, {0x7c, 0x00000002},
906 {0x7e, 0x00000005}, {0x8b, 0x0006fc00},
907 {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2},
908 {0x1e, 0x00000000}, {0xdf, 0x00000780},
911 * The 8723bu vendor driver indicates that bit 8 should be set in
912 * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However
913 * they never actually check the package type - and just default
917 {0x52, 0x000007d2}, {0x53, 0x00000000},
918 {0x54, 0x00050400}, {0x55, 0x0004026e},
919 {0xdd, 0x0000004c}, {0x70, 0x00067435},
921 * 0x71 has same package type condition as for register 0x51
924 {0x72, 0x000007d2}, {0x73, 0x00000000},
925 {0x74, 0x00050400}, {0x75, 0x0004026e},
926 {0xef, 0x00000100}, {0x34, 0x0000add7},
927 {0x35, 0x00005c00}, {0x34, 0x00009dd4},
928 {0x35, 0x00005000}, {0x34, 0x00008dd1},
929 {0x35, 0x00004400}, {0x34, 0x00007dce},
930 {0x35, 0x00003800}, {0x34, 0x00006cd1},
931 {0x35, 0x00004400}, {0x34, 0x00005cce},
932 {0x35, 0x00003800}, {0x34, 0x000048ce},
933 {0x35, 0x00004400}, {0x34, 0x000034ce},
934 {0x35, 0x00003800}, {0x34, 0x00002451},
935 {0x35, 0x00004400}, {0x34, 0x0000144e},
936 {0x35, 0x00003800}, {0x34, 0x00000051},
937 {0x35, 0x00004400}, {0xef, 0x00000000},
938 {0xef, 0x00000100}, {0xed, 0x00000010},
939 {0x44, 0x0000add7}, {0x44, 0x00009dd4},
940 {0x44, 0x00008dd1}, {0x44, 0x00007dce},
941 {0x44, 0x00006cc1}, {0x44, 0x00005cce},
942 {0x44, 0x000044d1}, {0x44, 0x000034ce},
943 {0x44, 0x00002451}, {0x44, 0x0000144e},
944 {0x44, 0x00000051}, {0xef, 0x00000000},
945 {0xed, 0x00000000}, {0x7f, 0x00020080},
946 {0xef, 0x00002000}, {0x3b, 0x000380ef},
947 {0x3b, 0x000302fe}, {0x3b, 0x00028ce6},
948 {0x3b, 0x000200bc}, {0x3b, 0x000188a5},
949 {0x3b, 0x00010fbc}, {0x3b, 0x00008f71},
950 {0x3b, 0x00000900}, {0xef, 0x00000000},
951 {0xed, 0x00000001}, {0x40, 0x000380ef},
952 {0x40, 0x000302fe}, {0x40, 0x00028ce6},
953 {0x40, 0x000200bc}, {0x40, 0x000188a5},
954 {0x40, 0x00010fbc}, {0x40, 0x00008f71},
955 {0x40, 0x00000900}, {0xed, 0x00000000},
956 {0x82, 0x00080000}, {0x83, 0x00008000},
957 {0x84, 0x00048d80}, {0x85, 0x00068000},
958 {0xa2, 0x00080000}, {0xa3, 0x00008000},
959 {0xa4, 0x00048d80}, {0xa5, 0x00068000},
960 {0xed, 0x00000002}, {0xef, 0x00000002},
961 {0x56, 0x00000032}, {0x76, 0x00000032},
966 static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table
[] = {
967 {0x00, 0x00030159}, {0x01, 0x00031284},
968 {0x02, 0x00098000}, {0x03, 0x00018c63},
969 {0x04, 0x000210e7}, {0x09, 0x0002044f},
970 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
971 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
972 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
973 {0x19, 0x00000000}, {0x1a, 0x00010255},
974 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
975 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
976 {0x1f, 0x00080001}, {0x20, 0x0000b614},
977 {0x21, 0x0006c000}, {0x22, 0x00000000},
978 {0x23, 0x00001558}, {0x24, 0x00000060},
979 {0x25, 0x00000483}, {0x26, 0x0004f000},
980 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
981 {0x29, 0x00004783}, {0x2a, 0x00000001},
982 {0x2b, 0x00021334}, {0x2a, 0x00000000},
983 {0x2b, 0x00000054}, {0x2a, 0x00000001},
984 {0x2b, 0x00000808}, {0x2b, 0x00053333},
985 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
986 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
987 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
988 {0x2b, 0x00000808}, {0x2b, 0x00063333},
989 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
990 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
991 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
992 {0x2b, 0x00000808}, {0x2b, 0x00073333},
993 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
994 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
995 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
996 {0x2b, 0x00000709}, {0x2b, 0x00063333},
997 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
998 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
999 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1000 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1001 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1002 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1003 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1004 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1005 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1006 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1007 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1008 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1009 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1010 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1011 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1012 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1013 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1014 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1015 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1016 {0x10, 0x00000000}, {0x11, 0x00000000},
1017 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1018 {0x10, 0x0009000f}, {0x11, 0x00023100},
1019 {0x12, 0x00032000}, {0x12, 0x00071000},
1020 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1021 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1022 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1023 {0x13, 0x00018493}, {0x13, 0x0001429b},
1024 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1025 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1026 {0x13, 0x00000020}, {0x14, 0x0001944c},
1027 {0x14, 0x00059444}, {0x14, 0x0009944c},
1028 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1029 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1030 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1031 {0x16, 0x000a0330}, {0x16, 0x00060330},
1032 {0x16, 0x00020330}, {0x00, 0x00010159},
1033 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1034 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1035 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1036 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1041 static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table
[] = {
1042 {0x00, 0x00030159}, {0x01, 0x00031284},
1043 {0x02, 0x00098000}, {0x03, 0x00018c63},
1044 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1045 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1046 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1047 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1048 {0x12, 0x00032000}, {0x12, 0x00071000},
1049 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1050 {0x13, 0x000287af}, {0x13, 0x000244b7},
1051 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1052 {0x13, 0x00018493}, {0x13, 0x00014297},
1053 {0x13, 0x00010295}, {0x13, 0x0000c298},
1054 {0x13, 0x0000819c}, {0x13, 0x000040a8},
1055 {0x13, 0x0000001c}, {0x14, 0x0001944c},
1056 {0x14, 0x00059444}, {0x14, 0x0009944c},
1057 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1058 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1059 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1060 {0x16, 0x000a0330}, {0x16, 0x00060330},
1065 static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table
[] = {
1066 {0x00, 0x00030159}, {0x01, 0x00031284},
1067 {0x02, 0x00098000}, {0x03, 0x00018c63},
1068 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1069 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1070 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1071 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1072 {0x19, 0x00000000}, {0x1a, 0x00010255},
1073 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1074 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1075 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1076 {0x21, 0x0006c000}, {0x22, 0x00000000},
1077 {0x23, 0x00001558}, {0x24, 0x00000060},
1078 {0x25, 0x00000483}, {0x26, 0x0004f000},
1079 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1080 {0x29, 0x00004783}, {0x2a, 0x00000001},
1081 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1082 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1083 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1084 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1085 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1086 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1087 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1088 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1089 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1090 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1091 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1092 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1093 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1094 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1095 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1096 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1097 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1098 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1099 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1100 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1101 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1102 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1103 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1104 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1105 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1106 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1107 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1108 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1109 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1110 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1111 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1112 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1113 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1114 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1115 {0x10, 0x00000000}, {0x11, 0x00000000},
1116 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1117 {0x10, 0x0009000f}, {0x11, 0x00023100},
1118 {0x12, 0x00032000}, {0x12, 0x00071000},
1119 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1120 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1121 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1122 {0x13, 0x00018493}, {0x13, 0x0001429b},
1123 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1124 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1125 {0x13, 0x00000020}, {0x14, 0x0001944c},
1126 {0x14, 0x00059444}, {0x14, 0x0009944c},
1127 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1128 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1129 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1130 {0x16, 0x000a0330}, {0x16, 0x00060330},
1131 {0x16, 0x00020330}, {0x00, 0x00010159},
1132 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1133 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1134 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1135 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1140 static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table
[] = {
1141 {0x00, 0x00030159}, {0x01, 0x00031284},
1142 {0x02, 0x00098000}, {0x03, 0x00018c63},
1143 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1144 {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
1145 {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
1146 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1147 {0x19, 0x00000000}, {0x1a, 0x00000255},
1148 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1149 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1150 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1151 {0x21, 0x0006c000}, {0x22, 0x0000083c},
1152 {0x23, 0x00001558}, {0x24, 0x00000060},
1153 {0x25, 0x00000483}, {0x26, 0x0004f000},
1154 {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
1155 {0x29, 0x00004783}, {0x2a, 0x00000001},
1156 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1157 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1158 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1159 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1160 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1161 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1162 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1163 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1164 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1165 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1166 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1167 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1168 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1169 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1170 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1171 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1172 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1173 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1174 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1175 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1176 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1177 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1178 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1179 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1180 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1181 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1182 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1183 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1184 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1185 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1186 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1187 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1188 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1189 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1190 {0x10, 0x00000000}, {0x11, 0x00000000},
1191 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1192 {0x10, 0x0009000f}, {0x11, 0x00023100},
1193 {0x12, 0x000d8000}, {0x12, 0x00090000},
1194 {0x12, 0x00051000}, {0x12, 0x00012000},
1195 {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
1196 {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
1197 {0x13, 0x000183a4}, {0x13, 0x00014398},
1198 {0x13, 0x000101a4}, {0x13, 0x0000c198},
1199 {0x13, 0x000080a4}, {0x13, 0x00004098},
1200 {0x13, 0x00000000}, {0x14, 0x0001944c},
1201 {0x14, 0x00059444}, {0x14, 0x0009944c},
1202 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1203 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1204 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1205 {0x16, 0x000a0330}, {0x16, 0x00060330},
1206 {0x16, 0x00020330}, {0x00, 0x00010159},
1207 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1208 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1209 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1210 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1215 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs
[] = {
1217 .hssiparm1
= REG_FPGA0_XA_HSSI_PARM1
,
1218 .hssiparm2
= REG_FPGA0_XA_HSSI_PARM2
,
1219 .lssiparm
= REG_FPGA0_XA_LSSI_PARM
,
1220 .hspiread
= REG_HSPI_XA_READBACK
,
1221 .lssiread
= REG_FPGA0_XA_LSSI_READBACK
,
1222 .rf_sw_ctrl
= REG_FPGA0_XA_RF_SW_CTRL
,
1225 .hssiparm1
= REG_FPGA0_XB_HSSI_PARM1
,
1226 .hssiparm2
= REG_FPGA0_XB_HSSI_PARM2
,
1227 .lssiparm
= REG_FPGA0_XB_LSSI_PARM
,
1228 .hspiread
= REG_HSPI_XB_READBACK
,
1229 .lssiread
= REG_FPGA0_XB_LSSI_READBACK
,
1230 .rf_sw_ctrl
= REG_FPGA0_XB_RF_SW_CTRL
,
1234 static const u32 rtl8723au_iqk_phy_iq_bb_reg
[RTL8XXXU_BB_REGS
] = {
1235 REG_OFDM0_XA_RX_IQ_IMBALANCE
,
1236 REG_OFDM0_XB_RX_IQ_IMBALANCE
,
1237 REG_OFDM0_ENERGY_CCA_THRES
,
1238 REG_OFDM0_AGCR_SSI_TABLE
,
1239 REG_OFDM0_XA_TX_IQ_IMBALANCE
,
1240 REG_OFDM0_XB_TX_IQ_IMBALANCE
,
1241 REG_OFDM0_XC_TX_AFE
,
1242 REG_OFDM0_XD_TX_AFE
,
1243 REG_OFDM0_RX_IQ_EXT_ANTA
1246 static u8
rtl8xxxu_read8(struct rtl8xxxu_priv
*priv
, u16 addr
)
1248 struct usb_device
*udev
= priv
->udev
;
1252 mutex_lock(&priv
->usb_buf_mutex
);
1253 len
= usb_control_msg(udev
, usb_rcvctrlpipe(udev
, 0),
1254 REALTEK_USB_CMD_REQ
, REALTEK_USB_READ
,
1255 addr
, 0, &priv
->usb_buf
.val8
, sizeof(u8
),
1256 RTW_USB_CONTROL_MSG_TIMEOUT
);
1257 data
= priv
->usb_buf
.val8
;
1258 mutex_unlock(&priv
->usb_buf_mutex
);
1260 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_REG_READ
)
1261 dev_info(&udev
->dev
, "%s(%04x) = 0x%02x, len %i\n",
1262 __func__
, addr
, data
, len
);
1266 static u16
rtl8xxxu_read16(struct rtl8xxxu_priv
*priv
, u16 addr
)
1268 struct usb_device
*udev
= priv
->udev
;
1272 mutex_lock(&priv
->usb_buf_mutex
);
1273 len
= usb_control_msg(udev
, usb_rcvctrlpipe(udev
, 0),
1274 REALTEK_USB_CMD_REQ
, REALTEK_USB_READ
,
1275 addr
, 0, &priv
->usb_buf
.val16
, sizeof(u16
),
1276 RTW_USB_CONTROL_MSG_TIMEOUT
);
1277 data
= le16_to_cpu(priv
->usb_buf
.val16
);
1278 mutex_unlock(&priv
->usb_buf_mutex
);
1280 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_REG_READ
)
1281 dev_info(&udev
->dev
, "%s(%04x) = 0x%04x, len %i\n",
1282 __func__
, addr
, data
, len
);
1286 static u32
rtl8xxxu_read32(struct rtl8xxxu_priv
*priv
, u16 addr
)
1288 struct usb_device
*udev
= priv
->udev
;
1292 mutex_lock(&priv
->usb_buf_mutex
);
1293 len
= usb_control_msg(udev
, usb_rcvctrlpipe(udev
, 0),
1294 REALTEK_USB_CMD_REQ
, REALTEK_USB_READ
,
1295 addr
, 0, &priv
->usb_buf
.val32
, sizeof(u32
),
1296 RTW_USB_CONTROL_MSG_TIMEOUT
);
1297 data
= le32_to_cpu(priv
->usb_buf
.val32
);
1298 mutex_unlock(&priv
->usb_buf_mutex
);
1300 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_REG_READ
)
1301 dev_info(&udev
->dev
, "%s(%04x) = 0x%08x, len %i\n",
1302 __func__
, addr
, data
, len
);
1306 static int rtl8xxxu_write8(struct rtl8xxxu_priv
*priv
, u16 addr
, u8 val
)
1308 struct usb_device
*udev
= priv
->udev
;
1311 mutex_lock(&priv
->usb_buf_mutex
);
1312 priv
->usb_buf
.val8
= val
;
1313 ret
= usb_control_msg(udev
, usb_sndctrlpipe(udev
, 0),
1314 REALTEK_USB_CMD_REQ
, REALTEK_USB_WRITE
,
1315 addr
, 0, &priv
->usb_buf
.val8
, sizeof(u8
),
1316 RTW_USB_CONTROL_MSG_TIMEOUT
);
1318 mutex_unlock(&priv
->usb_buf_mutex
);
1320 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_REG_WRITE
)
1321 dev_info(&udev
->dev
, "%s(%04x) = 0x%02x\n",
1322 __func__
, addr
, val
);
1326 static int rtl8xxxu_write16(struct rtl8xxxu_priv
*priv
, u16 addr
, u16 val
)
1328 struct usb_device
*udev
= priv
->udev
;
1331 mutex_lock(&priv
->usb_buf_mutex
);
1332 priv
->usb_buf
.val16
= cpu_to_le16(val
);
1333 ret
= usb_control_msg(udev
, usb_sndctrlpipe(udev
, 0),
1334 REALTEK_USB_CMD_REQ
, REALTEK_USB_WRITE
,
1335 addr
, 0, &priv
->usb_buf
.val16
, sizeof(u16
),
1336 RTW_USB_CONTROL_MSG_TIMEOUT
);
1337 mutex_unlock(&priv
->usb_buf_mutex
);
1339 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_REG_WRITE
)
1340 dev_info(&udev
->dev
, "%s(%04x) = 0x%04x\n",
1341 __func__
, addr
, val
);
1345 static int rtl8xxxu_write32(struct rtl8xxxu_priv
*priv
, u16 addr
, u32 val
)
1347 struct usb_device
*udev
= priv
->udev
;
1350 mutex_lock(&priv
->usb_buf_mutex
);
1351 priv
->usb_buf
.val32
= cpu_to_le32(val
);
1352 ret
= usb_control_msg(udev
, usb_sndctrlpipe(udev
, 0),
1353 REALTEK_USB_CMD_REQ
, REALTEK_USB_WRITE
,
1354 addr
, 0, &priv
->usb_buf
.val32
, sizeof(u32
),
1355 RTW_USB_CONTROL_MSG_TIMEOUT
);
1356 mutex_unlock(&priv
->usb_buf_mutex
);
1358 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_REG_WRITE
)
1359 dev_info(&udev
->dev
, "%s(%04x) = 0x%08x\n",
1360 __func__
, addr
, val
);
1365 rtl8xxxu_writeN(struct rtl8xxxu_priv
*priv
, u16 addr
, u8
*buf
, u16 len
)
1367 struct usb_device
*udev
= priv
->udev
;
1368 int blocksize
= priv
->fops
->writeN_block_size
;
1369 int ret
, i
, count
, remainder
;
1371 count
= len
/ blocksize
;
1372 remainder
= len
% blocksize
;
1374 for (i
= 0; i
< count
; i
++) {
1375 ret
= usb_control_msg(udev
, usb_sndctrlpipe(udev
, 0),
1376 REALTEK_USB_CMD_REQ
, REALTEK_USB_WRITE
,
1377 addr
, 0, buf
, blocksize
,
1378 RTW_USB_CONTROL_MSG_TIMEOUT
);
1379 if (ret
!= blocksize
)
1387 ret
= usb_control_msg(udev
, usb_sndctrlpipe(udev
, 0),
1388 REALTEK_USB_CMD_REQ
, REALTEK_USB_WRITE
,
1389 addr
, 0, buf
, remainder
,
1390 RTW_USB_CONTROL_MSG_TIMEOUT
);
1391 if (ret
!= remainder
)
1398 dev_info(&udev
->dev
,
1399 "%s: Failed to write block at addr: %04x size: %04x\n",
1400 __func__
, addr
, blocksize
);
1404 static u32
rtl8xxxu_read_rfreg(struct rtl8xxxu_priv
*priv
,
1405 enum rtl8xxxu_rfpath path
, u8 reg
)
1407 u32 hssia
, val32
, retval
;
1409 hssia
= rtl8xxxu_read32(priv
, REG_FPGA0_XA_HSSI_PARM2
);
1411 val32
= rtl8xxxu_read32(priv
, rtl8xxxu_rfregs
[path
].hssiparm2
);
1415 val32
&= ~FPGA0_HSSI_PARM2_ADDR_MASK
;
1416 val32
|= (reg
<< FPGA0_HSSI_PARM2_ADDR_SHIFT
);
1417 val32
|= FPGA0_HSSI_PARM2_EDGE_READ
;
1418 hssia
&= ~FPGA0_HSSI_PARM2_EDGE_READ
;
1419 rtl8xxxu_write32(priv
, REG_FPGA0_XA_HSSI_PARM2
, hssia
);
1423 rtl8xxxu_write32(priv
, rtl8xxxu_rfregs
[path
].hssiparm2
, val32
);
1426 hssia
|= FPGA0_HSSI_PARM2_EDGE_READ
;
1427 rtl8xxxu_write32(priv
, REG_FPGA0_XA_HSSI_PARM2
, hssia
);
1430 val32
= rtl8xxxu_read32(priv
, rtl8xxxu_rfregs
[path
].hssiparm1
);
1431 if (val32
& FPGA0_HSSI_PARM1_PI
)
1432 retval
= rtl8xxxu_read32(priv
, rtl8xxxu_rfregs
[path
].hspiread
);
1434 retval
= rtl8xxxu_read32(priv
, rtl8xxxu_rfregs
[path
].lssiread
);
1438 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_RFREG_READ
)
1439 dev_info(&priv
->udev
->dev
, "%s(%02x) = 0x%06x\n",
1440 __func__
, reg
, retval
);
1445 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
1446 * have write issues in high temperature conditions. We may have to
1447 * retry writing them.
1449 static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv
*priv
,
1450 enum rtl8xxxu_rfpath path
, u8 reg
, u32 data
)
1455 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_RFREG_WRITE
)
1456 dev_info(&priv
->udev
->dev
, "%s(%02x) = 0x%06x\n",
1457 __func__
, reg
, data
);
1459 data
&= FPGA0_LSSI_PARM_DATA_MASK
;
1460 dataaddr
= (reg
<< FPGA0_LSSI_PARM_ADDR_SHIFT
) | data
;
1462 /* Use XB for path B */
1463 ret
= rtl8xxxu_write32(priv
, rtl8xxxu_rfregs
[path
].lssiparm
, dataaddr
);
1464 if (ret
!= sizeof(dataaddr
))
1474 static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv
*priv
,
1475 struct h2c_cmd
*h2c
, int len
)
1477 struct device
*dev
= &priv
->udev
->dev
;
1478 int mbox_nr
, retry
, retval
= 0;
1479 int mbox_reg
, mbox_ext_reg
;
1482 mutex_lock(&priv
->h2c_mutex
);
1484 mbox_nr
= priv
->next_mbox
;
1485 mbox_reg
= REG_HMBOX_0
+ (mbox_nr
* 4);
1486 mbox_ext_reg
= priv
->fops
->mbox_ext_reg
+
1487 (mbox_nr
* priv
->fops
->mbox_ext_width
);
1494 val8
= rtl8xxxu_read8(priv
, REG_HMTFR
);
1495 if (!(val8
& BIT(mbox_nr
)))
1500 dev_info(dev
, "%s: Mailbox busy\n", __func__
);
1506 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1508 if (len
> sizeof(u32
)) {
1509 if (priv
->fops
->mbox_ext_width
== 4) {
1510 rtl8xxxu_write32(priv
, mbox_ext_reg
,
1511 le32_to_cpu(h2c
->raw_wide
.ext
));
1512 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_H2C
)
1513 dev_info(dev
, "H2C_EXT %08x\n",
1514 le32_to_cpu(h2c
->raw_wide
.ext
));
1516 rtl8xxxu_write16(priv
, mbox_ext_reg
,
1517 le16_to_cpu(h2c
->raw
.ext
));
1518 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_H2C
)
1519 dev_info(dev
, "H2C_EXT %04x\n",
1520 le16_to_cpu(h2c
->raw
.ext
));
1523 rtl8xxxu_write32(priv
, mbox_reg
, le32_to_cpu(h2c
->raw
.data
));
1524 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_H2C
)
1525 dev_info(dev
, "H2C %08x\n", le32_to_cpu(h2c
->raw
.data
));
1527 priv
->next_mbox
= (mbox_nr
+ 1) % H2C_MAX_MBOX
;
1530 mutex_unlock(&priv
->h2c_mutex
);
1534 static void rtl8723bu_write_btreg(struct rtl8xxxu_priv
*priv
, u8 reg
, u8 data
)
1539 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
1540 h2c
.bt_mp_oper
.cmd
= H2C_8723B_BT_MP_OPER
;
1541 h2c
.bt_mp_oper
.operreq
= 0 | (reqnum
<< 4);
1542 h2c
.bt_mp_oper
.opcode
= BT_MP_OP_WRITE_REG_VALUE
;
1543 h2c
.bt_mp_oper
.data
= data
;
1544 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.bt_mp_oper
));
1547 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
1548 h2c
.bt_mp_oper
.cmd
= H2C_8723B_BT_MP_OPER
;
1549 h2c
.bt_mp_oper
.operreq
= 0 | (reqnum
<< 4);
1550 h2c
.bt_mp_oper
.opcode
= BT_MP_OP_WRITE_REG_VALUE
;
1551 h2c
.bt_mp_oper
.addr
= reg
;
1552 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.bt_mp_oper
));
1555 static void rtl8723a_enable_rf(struct rtl8xxxu_priv
*priv
)
1560 val8
= rtl8xxxu_read8(priv
, REG_SPS0_CTRL
);
1561 val8
|= BIT(0) | BIT(3);
1562 rtl8xxxu_write8(priv
, REG_SPS0_CTRL
, val8
);
1564 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XAB_RF_PARM
);
1565 val32
&= ~(BIT(4) | BIT(5));
1567 if (priv
->rf_paths
== 2) {
1568 val32
&= ~(BIT(20) | BIT(21));
1571 rtl8xxxu_write32(priv
, REG_FPGA0_XAB_RF_PARM
, val32
);
1573 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_TRX_PATH_ENABLE
);
1574 val32
&= ~OFDM_RF_PATH_TX_MASK
;
1575 if (priv
->tx_paths
== 2)
1576 val32
|= OFDM_RF_PATH_TX_A
| OFDM_RF_PATH_TX_B
;
1577 else if (priv
->rtlchip
== 0x8192c || priv
->rtlchip
== 0x8191c)
1578 val32
|= OFDM_RF_PATH_TX_B
;
1580 val32
|= OFDM_RF_PATH_TX_A
;
1581 rtl8xxxu_write32(priv
, REG_OFDM0_TRX_PATH_ENABLE
, val32
);
1583 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
1584 val32
&= ~FPGA_RF_MODE_JAPAN
;
1585 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
1587 if (priv
->rf_paths
== 2)
1588 rtl8xxxu_write32(priv
, REG_RX_WAIT_CCA
, 0x63db25a0);
1590 rtl8xxxu_write32(priv
, REG_RX_WAIT_CCA
, 0x631b25a0);
1592 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_AC
, 0x32d95);
1593 if (priv
->rf_paths
== 2)
1594 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_AC
, 0x32d95);
1596 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0x00);
1599 static void rtl8723b_enable_rf(struct rtl8xxxu_priv
*priv
)
1603 static void rtl8723a_disable_rf(struct rtl8xxxu_priv
*priv
)
1608 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0xff);
1610 sps0
= rtl8xxxu_read8(priv
, REG_SPS0_CTRL
);
1612 /* RF RX code for preamble power saving */
1613 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XAB_RF_PARM
);
1614 val32
&= ~(BIT(3) | BIT(4) | BIT(5));
1615 if (priv
->rf_paths
== 2)
1616 val32
&= ~(BIT(19) | BIT(20) | BIT(21));
1617 rtl8xxxu_write32(priv
, REG_FPGA0_XAB_RF_PARM
, val32
);
1619 /* Disable TX for four paths */
1620 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_TRX_PATH_ENABLE
);
1621 val32
&= ~OFDM_RF_PATH_TX_MASK
;
1622 rtl8xxxu_write32(priv
, REG_OFDM0_TRX_PATH_ENABLE
, val32
);
1624 /* Enable power saving */
1625 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
1626 val32
|= FPGA_RF_MODE_JAPAN
;
1627 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
1629 /* AFE control register to power down bits [30:22] */
1630 if (priv
->rf_paths
== 2)
1631 rtl8xxxu_write32(priv
, REG_RX_WAIT_CCA
, 0x00db25a0);
1633 rtl8xxxu_write32(priv
, REG_RX_WAIT_CCA
, 0x001b25a0);
1635 /* Power down RF module */
1636 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_AC
, 0);
1637 if (priv
->rf_paths
== 2)
1638 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_AC
, 0);
1640 sps0
&= ~(BIT(0) | BIT(3));
1641 rtl8xxxu_write8(priv
, REG_SPS0_CTRL
, sps0
);
1645 static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv
*priv
)
1649 val8
= rtl8xxxu_read8(priv
, REG_FWHW_TXQ_CTRL
+ 2);
1651 rtl8xxxu_write8(priv
, REG_FWHW_TXQ_CTRL
+ 2, val8
);
1653 rtl8xxxu_write8(priv
, REG_TBTT_PROHIBIT
+ 1, 0x64);
1654 val8
= rtl8xxxu_read8(priv
, REG_TBTT_PROHIBIT
+ 2);
1656 rtl8xxxu_write8(priv
, REG_TBTT_PROHIBIT
+ 2, val8
);
1661 * The rtl8723a has 3 channel groups for it's efuse settings. It only
1662 * supports the 2.4GHz band, so channels 1 - 14:
1663 * group 0: channels 1 - 3
1664 * group 1: channels 4 - 9
1665 * group 2: channels 10 - 14
1667 * Note: We index from 0 in the code
1669 static int rtl8723a_channel_to_group(int channel
)
1675 else if (channel
< 10)
1683 static int rtl8723b_channel_to_group(int channel
)
1689 else if (channel
< 6)
1691 else if (channel
< 9)
1693 else if (channel
< 12)
1701 static void rtl8723au_config_channel(struct ieee80211_hw
*hw
)
1703 struct rtl8xxxu_priv
*priv
= hw
->priv
;
1707 int sec_ch_above
, channel
;
1710 opmode
= rtl8xxxu_read8(priv
, REG_BW_OPMODE
);
1711 rsr
= rtl8xxxu_read32(priv
, REG_RESPONSE_RATE_SET
);
1712 channel
= hw
->conf
.chandef
.chan
->hw_value
;
1714 switch (hw
->conf
.chandef
.width
) {
1715 case NL80211_CHAN_WIDTH_20_NOHT
:
1717 case NL80211_CHAN_WIDTH_20
:
1718 opmode
|= BW_OPMODE_20MHZ
;
1719 rtl8xxxu_write8(priv
, REG_BW_OPMODE
, opmode
);
1721 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
1722 val32
&= ~FPGA_RF_MODE
;
1723 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
1725 val32
= rtl8xxxu_read32(priv
, REG_FPGA1_RF_MODE
);
1726 val32
&= ~FPGA_RF_MODE
;
1727 rtl8xxxu_write32(priv
, REG_FPGA1_RF_MODE
, val32
);
1729 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_ANALOG2
);
1730 val32
|= FPGA0_ANALOG2_20MHZ
;
1731 rtl8xxxu_write32(priv
, REG_FPGA0_ANALOG2
, val32
);
1733 case NL80211_CHAN_WIDTH_40
:
1734 if (hw
->conf
.chandef
.center_freq1
>
1735 hw
->conf
.chandef
.chan
->center_freq
) {
1743 opmode
&= ~BW_OPMODE_20MHZ
;
1744 rtl8xxxu_write8(priv
, REG_BW_OPMODE
, opmode
);
1745 rsr
&= ~RSR_RSC_BANDWIDTH_40M
;
1747 rsr
|= RSR_RSC_UPPER_SUB_CHANNEL
;
1749 rsr
|= RSR_RSC_LOWER_SUB_CHANNEL
;
1750 rtl8xxxu_write32(priv
, REG_RESPONSE_RATE_SET
, rsr
);
1752 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
1753 val32
|= FPGA_RF_MODE
;
1754 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
1756 val32
= rtl8xxxu_read32(priv
, REG_FPGA1_RF_MODE
);
1757 val32
|= FPGA_RF_MODE
;
1758 rtl8xxxu_write32(priv
, REG_FPGA1_RF_MODE
, val32
);
1761 * Set Control channel to upper or lower. These settings
1762 * are required only for 40MHz
1764 val32
= rtl8xxxu_read32(priv
, REG_CCK0_SYSTEM
);
1765 val32
&= ~CCK0_SIDEBAND
;
1767 val32
|= CCK0_SIDEBAND
;
1768 rtl8xxxu_write32(priv
, REG_CCK0_SYSTEM
, val32
);
1770 val32
= rtl8xxxu_read32(priv
, REG_OFDM1_LSTF
);
1771 val32
&= ~OFDM_LSTF_PRIME_CH_MASK
; /* 0xc00 */
1773 val32
|= OFDM_LSTF_PRIME_CH_LOW
;
1775 val32
|= OFDM_LSTF_PRIME_CH_HIGH
;
1776 rtl8xxxu_write32(priv
, REG_OFDM1_LSTF
, val32
);
1778 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_ANALOG2
);
1779 val32
&= ~FPGA0_ANALOG2_20MHZ
;
1780 rtl8xxxu_write32(priv
, REG_FPGA0_ANALOG2
, val32
);
1782 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_POWER_SAVE
);
1783 val32
&= ~(FPGA0_PS_LOWER_CHANNEL
| FPGA0_PS_UPPER_CHANNEL
);
1785 val32
|= FPGA0_PS_UPPER_CHANNEL
;
1787 val32
|= FPGA0_PS_LOWER_CHANNEL
;
1788 rtl8xxxu_write32(priv
, REG_FPGA0_POWER_SAVE
, val32
);
1795 for (i
= RF_A
; i
< priv
->rf_paths
; i
++) {
1796 val32
= rtl8xxxu_read_rfreg(priv
, i
, RF6052_REG_MODE_AG
);
1797 val32
&= ~MODE_AG_CHANNEL_MASK
;
1799 rtl8xxxu_write_rfreg(priv
, i
, RF6052_REG_MODE_AG
, val32
);
1807 rtl8xxxu_write8(priv
, REG_SIFS_CCK
+ 1, val8
);
1808 rtl8xxxu_write8(priv
, REG_SIFS_OFDM
+ 1, val8
);
1810 rtl8xxxu_write16(priv
, REG_R2T_SIFS
, 0x0808);
1811 rtl8xxxu_write16(priv
, REG_T2T_SIFS
, 0x0a0a);
1813 for (i
= RF_A
; i
< priv
->rf_paths
; i
++) {
1814 val32
= rtl8xxxu_read_rfreg(priv
, i
, RF6052_REG_MODE_AG
);
1815 if (hw
->conf
.chandef
.width
== NL80211_CHAN_WIDTH_40
)
1816 val32
&= ~MODE_AG_CHANNEL_20MHZ
;
1818 val32
|= MODE_AG_CHANNEL_20MHZ
;
1819 rtl8xxxu_write_rfreg(priv
, i
, RF6052_REG_MODE_AG
, val32
);
1823 static void rtl8723bu_config_channel(struct ieee80211_hw
*hw
)
1825 struct rtl8xxxu_priv
*priv
= hw
->priv
;
1827 u8 val8
, subchannel
;
1830 int sec_ch_above
, channel
;
1833 rf_mode_bw
= rtl8xxxu_read16(priv
, REG_WMAC_TRXPTCL_CTL
);
1834 rf_mode_bw
&= ~WMAC_TRXPTCL_CTL_BW_MASK
;
1835 rsr
= rtl8xxxu_read32(priv
, REG_RESPONSE_RATE_SET
);
1836 channel
= hw
->conf
.chandef
.chan
->hw_value
;
1841 switch (hw
->conf
.chandef
.width
) {
1842 case NL80211_CHAN_WIDTH_20_NOHT
:
1844 case NL80211_CHAN_WIDTH_20
:
1845 rf_mode_bw
|= WMAC_TRXPTCL_CTL_BW_20
;
1848 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
1849 val32
&= ~FPGA_RF_MODE
;
1850 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
1852 val32
= rtl8xxxu_read32(priv
, REG_FPGA1_RF_MODE
);
1853 val32
&= ~FPGA_RF_MODE
;
1854 rtl8xxxu_write32(priv
, REG_FPGA1_RF_MODE
, val32
);
1856 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_TX_PSDO_NOISE_WEIGHT
);
1857 val32
&= ~(BIT(30) | BIT(31));
1858 rtl8xxxu_write32(priv
, REG_OFDM0_TX_PSDO_NOISE_WEIGHT
, val32
);
1861 case NL80211_CHAN_WIDTH_40
:
1862 rf_mode_bw
|= WMAC_TRXPTCL_CTL_BW_40
;
1864 if (hw
->conf
.chandef
.center_freq1
>
1865 hw
->conf
.chandef
.chan
->center_freq
) {
1873 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
1874 val32
|= FPGA_RF_MODE
;
1875 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
1877 val32
= rtl8xxxu_read32(priv
, REG_FPGA1_RF_MODE
);
1878 val32
|= FPGA_RF_MODE
;
1879 rtl8xxxu_write32(priv
, REG_FPGA1_RF_MODE
, val32
);
1882 * Set Control channel to upper or lower. These settings
1883 * are required only for 40MHz
1885 val32
= rtl8xxxu_read32(priv
, REG_CCK0_SYSTEM
);
1886 val32
&= ~CCK0_SIDEBAND
;
1888 val32
|= CCK0_SIDEBAND
;
1889 rtl8xxxu_write32(priv
, REG_CCK0_SYSTEM
, val32
);
1891 val32
= rtl8xxxu_read32(priv
, REG_OFDM1_LSTF
);
1892 val32
&= ~OFDM_LSTF_PRIME_CH_MASK
; /* 0xc00 */
1894 val32
|= OFDM_LSTF_PRIME_CH_LOW
;
1896 val32
|= OFDM_LSTF_PRIME_CH_HIGH
;
1897 rtl8xxxu_write32(priv
, REG_OFDM1_LSTF
, val32
);
1899 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_POWER_SAVE
);
1900 val32
&= ~(FPGA0_PS_LOWER_CHANNEL
| FPGA0_PS_UPPER_CHANNEL
);
1902 val32
|= FPGA0_PS_UPPER_CHANNEL
;
1904 val32
|= FPGA0_PS_LOWER_CHANNEL
;
1905 rtl8xxxu_write32(priv
, REG_FPGA0_POWER_SAVE
, val32
);
1907 case NL80211_CHAN_WIDTH_80
:
1908 rf_mode_bw
|= WMAC_TRXPTCL_CTL_BW_80
;
1914 for (i
= RF_A
; i
< priv
->rf_paths
; i
++) {
1915 val32
= rtl8xxxu_read_rfreg(priv
, i
, RF6052_REG_MODE_AG
);
1916 val32
&= ~MODE_AG_CHANNEL_MASK
;
1918 rtl8xxxu_write_rfreg(priv
, i
, RF6052_REG_MODE_AG
, val32
);
1921 rtl8xxxu_write16(priv
, REG_WMAC_TRXPTCL_CTL
, rf_mode_bw
);
1922 rtl8xxxu_write8(priv
, REG_DATA_SUBCHANNEL
, subchannel
);
1929 rtl8xxxu_write8(priv
, REG_SIFS_CCK
+ 1, val8
);
1930 rtl8xxxu_write8(priv
, REG_SIFS_OFDM
+ 1, val8
);
1932 rtl8xxxu_write16(priv
, REG_R2T_SIFS
, 0x0808);
1933 rtl8xxxu_write16(priv
, REG_T2T_SIFS
, 0x0a0a);
1935 for (i
= RF_A
; i
< priv
->rf_paths
; i
++) {
1936 val32
= rtl8xxxu_read_rfreg(priv
, i
, RF6052_REG_MODE_AG
);
1937 val32
&= ~MODE_AG_BW_MASK
;
1938 switch(hw
->conf
.chandef
.width
) {
1939 case NL80211_CHAN_WIDTH_80
:
1940 val32
|= MODE_AG_BW_80MHZ_8723B
;
1942 case NL80211_CHAN_WIDTH_40
:
1943 val32
|= MODE_AG_BW_40MHZ_8723B
;
1946 val32
|= MODE_AG_BW_20MHZ_8723B
;
1949 rtl8xxxu_write_rfreg(priv
, i
, RF6052_REG_MODE_AG
, val32
);
1954 rtl8723a_set_tx_power(struct rtl8xxxu_priv
*priv
, int channel
, bool ht40
)
1956 u8 cck
[RTL8723A_MAX_RF_PATHS
], ofdm
[RTL8723A_MAX_RF_PATHS
];
1957 u8 ofdmbase
[RTL8723A_MAX_RF_PATHS
], mcsbase
[RTL8723A_MAX_RF_PATHS
];
1958 u32 val32
, ofdm_a
, ofdm_b
, mcs_a
, mcs_b
;
1962 group
= rtl8723a_channel_to_group(channel
);
1964 cck
[0] = priv
->cck_tx_power_index_A
[group
];
1965 cck
[1] = priv
->cck_tx_power_index_B
[group
];
1967 ofdm
[0] = priv
->ht40_1s_tx_power_index_A
[group
];
1968 ofdm
[1] = priv
->ht40_1s_tx_power_index_B
[group
];
1970 ofdmbase
[0] = ofdm
[0] + priv
->ofdm_tx_power_index_diff
[group
].a
;
1971 ofdmbase
[1] = ofdm
[1] + priv
->ofdm_tx_power_index_diff
[group
].b
;
1973 mcsbase
[0] = ofdm
[0];
1974 mcsbase
[1] = ofdm
[1];
1976 mcsbase
[0] += priv
->ht20_tx_power_index_diff
[group
].a
;
1977 mcsbase
[1] += priv
->ht20_tx_power_index_diff
[group
].b
;
1980 if (priv
->tx_paths
> 1) {
1981 if (ofdm
[0] > priv
->ht40_2s_tx_power_index_diff
[group
].a
)
1982 ofdm
[0] -= priv
->ht40_2s_tx_power_index_diff
[group
].a
;
1983 if (ofdm
[1] > priv
->ht40_2s_tx_power_index_diff
[group
].b
)
1984 ofdm
[1] -= priv
->ht40_2s_tx_power_index_diff
[group
].b
;
1987 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_CHANNEL
)
1988 dev_info(&priv
->udev
->dev
,
1989 "%s: Setting TX power CCK A: %02x, "
1990 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1991 __func__
, cck
[0], cck
[1], ofdm
[0], ofdm
[1]);
1993 for (i
= 0; i
< RTL8723A_MAX_RF_PATHS
; i
++) {
1994 if (cck
[i
] > RF6052_MAX_TX_PWR
)
1995 cck
[i
] = RF6052_MAX_TX_PWR
;
1996 if (ofdm
[i
] > RF6052_MAX_TX_PWR
)
1997 ofdm
[i
] = RF6052_MAX_TX_PWR
;
2000 val32
= rtl8xxxu_read32(priv
, REG_TX_AGC_A_CCK1_MCS32
);
2001 val32
&= 0xffff00ff;
2002 val32
|= (cck
[0] << 8);
2003 rtl8xxxu_write32(priv
, REG_TX_AGC_A_CCK1_MCS32
, val32
);
2005 val32
= rtl8xxxu_read32(priv
, REG_TX_AGC_B_CCK11_A_CCK2_11
);
2007 val32
|= ((cck
[0] << 8) | (cck
[0] << 16) | (cck
[0] << 24));
2008 rtl8xxxu_write32(priv
, REG_TX_AGC_B_CCK11_A_CCK2_11
, val32
);
2010 val32
= rtl8xxxu_read32(priv
, REG_TX_AGC_B_CCK11_A_CCK2_11
);
2011 val32
&= 0xffffff00;
2013 rtl8xxxu_write32(priv
, REG_TX_AGC_B_CCK11_A_CCK2_11
, val32
);
2015 val32
= rtl8xxxu_read32(priv
, REG_TX_AGC_B_CCK1_55_MCS32
);
2017 val32
|= ((cck
[1] << 8) | (cck
[1] << 16) | (cck
[1] << 24));
2018 rtl8xxxu_write32(priv
, REG_TX_AGC_B_CCK1_55_MCS32
, val32
);
2020 ofdm_a
= ofdmbase
[0] | ofdmbase
[0] << 8 |
2021 ofdmbase
[0] << 16 | ofdmbase
[0] << 24;
2022 ofdm_b
= ofdmbase
[1] | ofdmbase
[1] << 8 |
2023 ofdmbase
[1] << 16 | ofdmbase
[1] << 24;
2024 rtl8xxxu_write32(priv
, REG_TX_AGC_A_RATE18_06
, ofdm_a
);
2025 rtl8xxxu_write32(priv
, REG_TX_AGC_B_RATE18_06
, ofdm_b
);
2027 rtl8xxxu_write32(priv
, REG_TX_AGC_A_RATE54_24
, ofdm_a
);
2028 rtl8xxxu_write32(priv
, REG_TX_AGC_B_RATE54_24
, ofdm_b
);
2030 mcs_a
= mcsbase
[0] | mcsbase
[0] << 8 |
2031 mcsbase
[0] << 16 | mcsbase
[0] << 24;
2032 mcs_b
= mcsbase
[1] | mcsbase
[1] << 8 |
2033 mcsbase
[1] << 16 | mcsbase
[1] << 24;
2035 rtl8xxxu_write32(priv
, REG_TX_AGC_A_MCS03_MCS00
, mcs_a
);
2036 rtl8xxxu_write32(priv
, REG_TX_AGC_B_MCS03_MCS00
, mcs_b
);
2038 rtl8xxxu_write32(priv
, REG_TX_AGC_A_MCS07_MCS04
, mcs_a
);
2039 rtl8xxxu_write32(priv
, REG_TX_AGC_B_MCS07_MCS04
, mcs_b
);
2041 rtl8xxxu_write32(priv
, REG_TX_AGC_A_MCS11_MCS08
, mcs_a
);
2042 rtl8xxxu_write32(priv
, REG_TX_AGC_B_MCS11_MCS08
, mcs_b
);
2044 rtl8xxxu_write32(priv
, REG_TX_AGC_A_MCS15_MCS12
, mcs_a
);
2045 for (i
= 0; i
< 3; i
++) {
2047 val8
= (mcsbase
[0] > 8) ? (mcsbase
[0] - 8) : 0;
2049 val8
= (mcsbase
[0] > 6) ? (mcsbase
[0] - 6) : 0;
2050 rtl8xxxu_write8(priv
, REG_OFDM0_XC_TX_IQ_IMBALANCE
+ i
, val8
);
2052 rtl8xxxu_write32(priv
, REG_TX_AGC_B_MCS15_MCS12
, mcs_b
);
2053 for (i
= 0; i
< 3; i
++) {
2055 val8
= (mcsbase
[1] > 8) ? (mcsbase
[1] - 8) : 0;
2057 val8
= (mcsbase
[1] > 6) ? (mcsbase
[1] - 6) : 0;
2058 rtl8xxxu_write8(priv
, REG_OFDM0_XD_TX_IQ_IMBALANCE
+ i
, val8
);
2063 rtl8723b_set_tx_power(struct rtl8xxxu_priv
*priv
, int channel
, bool ht40
)
2065 u32 val32
, ofdm
, mcs
;
2066 u8 cck
, ofdmbase
, mcsbase
;
2070 group
= rtl8723b_channel_to_group(channel
);
2072 cck
= priv
->cck_tx_power_index_B
[group
];
2073 val32
= rtl8xxxu_read32(priv
, REG_TX_AGC_A_CCK1_MCS32
);
2074 val32
&= 0xffff00ff;
2075 val32
|= (cck
<< 8);
2076 rtl8xxxu_write32(priv
, REG_TX_AGC_A_CCK1_MCS32
, val32
);
2078 val32
= rtl8xxxu_read32(priv
, REG_TX_AGC_B_CCK11_A_CCK2_11
);
2080 val32
|= ((cck
<< 8) | (cck
<< 16) | (cck
<< 24));
2081 rtl8xxxu_write32(priv
, REG_TX_AGC_B_CCK11_A_CCK2_11
, val32
);
2083 ofdmbase
= priv
->ht40_1s_tx_power_index_B
[group
];
2084 ofdmbase
+= priv
->ofdm_tx_power_diff
[tx_idx
].b
;
2085 ofdm
= ofdmbase
| ofdmbase
<< 8 | ofdmbase
<< 16 | ofdmbase
<< 24;
2087 rtl8xxxu_write32(priv
, REG_TX_AGC_A_RATE18_06
, ofdm
);
2088 rtl8xxxu_write32(priv
, REG_TX_AGC_A_RATE54_24
, ofdm
);
2090 mcsbase
= priv
->ht40_1s_tx_power_index_B
[group
];
2092 mcsbase
+= priv
->ht40_tx_power_diff
[tx_idx
++].b
;
2094 mcsbase
+= priv
->ht20_tx_power_diff
[tx_idx
++].b
;
2095 mcs
= mcsbase
| mcsbase
<< 8 | mcsbase
<< 16 | mcsbase
<< 24;
2097 rtl8xxxu_write32(priv
, REG_TX_AGC_A_MCS03_MCS00
, mcs
);
2098 rtl8xxxu_write32(priv
, REG_TX_AGC_A_MCS07_MCS04
, mcs
);
2101 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv
*priv
,
2102 enum nl80211_iftype linktype
)
2106 val8
= rtl8xxxu_read8(priv
, REG_MSR
);
2107 val8
&= ~MSR_LINKTYPE_MASK
;
2110 case NL80211_IFTYPE_UNSPECIFIED
:
2111 val8
|= MSR_LINKTYPE_NONE
;
2113 case NL80211_IFTYPE_ADHOC
:
2114 val8
|= MSR_LINKTYPE_ADHOC
;
2116 case NL80211_IFTYPE_STATION
:
2117 val8
|= MSR_LINKTYPE_STATION
;
2119 case NL80211_IFTYPE_AP
:
2120 val8
|= MSR_LINKTYPE_AP
;
2126 rtl8xxxu_write8(priv
, REG_MSR
, val8
);
2132 rtl8xxxu_set_retry(struct rtl8xxxu_priv
*priv
, u16 short_retry
, u16 long_retry
)
2136 val16
= ((short_retry
<< RETRY_LIMIT_SHORT_SHIFT
) &
2137 RETRY_LIMIT_SHORT_MASK
) |
2138 ((long_retry
<< RETRY_LIMIT_LONG_SHIFT
) &
2139 RETRY_LIMIT_LONG_MASK
);
2141 rtl8xxxu_write16(priv
, REG_RETRY_LIMIT
, val16
);
2145 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv
*priv
, u16 cck
, u16 ofdm
)
2149 val16
= ((cck
<< SPEC_SIFS_CCK_SHIFT
) & SPEC_SIFS_CCK_MASK
) |
2150 ((ofdm
<< SPEC_SIFS_OFDM_SHIFT
) & SPEC_SIFS_OFDM_MASK
);
2152 rtl8xxxu_write16(priv
, REG_SPEC_SIFS
, val16
);
2155 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv
*priv
)
2157 struct device
*dev
= &priv
->udev
->dev
;
2160 switch (priv
->chip_cut
) {
2181 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
2182 priv
->chip_name
, cut
, priv
->chip_vendor
, priv
->tx_paths
,
2183 priv
->rx_paths
, priv
->ep_tx_count
, priv
->has_wifi
,
2184 priv
->has_bluetooth
, priv
->has_gps
, priv
->hi_pa
);
2186 dev_info(dev
, "RTL%s MAC: %pM\n", priv
->chip_name
, priv
->mac_addr
);
2189 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv
*priv
)
2191 struct device
*dev
= &priv
->udev
->dev
;
2195 val32
= rtl8xxxu_read32(priv
, REG_SYS_CFG
);
2196 priv
->chip_cut
= (val32
& SYS_CFG_CHIP_VERSION_MASK
) >>
2197 SYS_CFG_CHIP_VERSION_SHIFT
;
2198 if (val32
& SYS_CFG_TRP_VAUX_EN
) {
2199 dev_info(dev
, "Unsupported test chip\n");
2203 if (val32
& SYS_CFG_BT_FUNC
) {
2204 if (priv
->chip_cut
>= 3) {
2205 sprintf(priv
->chip_name
, "8723BU");
2206 priv
->rtlchip
= 0x8723b;
2208 sprintf(priv
->chip_name
, "8723AU");
2209 priv
->usb_interrupts
= 1;
2210 priv
->rtlchip
= 0x8723a;
2217 val32
= rtl8xxxu_read32(priv
, REG_MULTI_FUNC_CTRL
);
2218 if (val32
& MULTI_WIFI_FUNC_EN
)
2220 if (val32
& MULTI_BT_FUNC_EN
)
2221 priv
->has_bluetooth
= 1;
2222 if (val32
& MULTI_GPS_FUNC_EN
)
2224 priv
->is_multi_func
= 1;
2225 } else if (val32
& SYS_CFG_TYPE_ID
) {
2226 bonding
= rtl8xxxu_read32(priv
, REG_HPON_FSM
);
2227 bonding
&= HPON_FSM_BONDING_MASK
;
2228 if (priv
->chip_cut
>= 3) {
2229 if (bonding
== HPON_FSM_BONDING_1T2R
) {
2230 sprintf(priv
->chip_name
, "8191EU");
2234 priv
->rtlchip
= 0x8191e;
2236 sprintf(priv
->chip_name
, "8192EU");
2240 priv
->rtlchip
= 0x8192e;
2242 } else if (bonding
== HPON_FSM_BONDING_1T2R
) {
2243 sprintf(priv
->chip_name
, "8191CU");
2247 priv
->usb_interrupts
= 1;
2248 priv
->rtlchip
= 0x8191c;
2250 sprintf(priv
->chip_name
, "8192CU");
2254 priv
->usb_interrupts
= 1;
2255 priv
->rtlchip
= 0x8192c;
2259 sprintf(priv
->chip_name
, "8188CU");
2263 priv
->rtlchip
= 0x8188c;
2264 priv
->usb_interrupts
= 1;
2268 switch (priv
->rtlchip
) {
2272 switch (val32
& SYS_CFG_VENDOR_EXT_MASK
) {
2273 case SYS_CFG_VENDOR_ID_TSMC
:
2274 sprintf(priv
->chip_vendor
, "TSMC");
2276 case SYS_CFG_VENDOR_ID_SMIC
:
2277 sprintf(priv
->chip_vendor
, "SMIC");
2278 priv
->vendor_smic
= 1;
2280 case SYS_CFG_VENDOR_ID_UMC
:
2281 sprintf(priv
->chip_vendor
, "UMC");
2282 priv
->vendor_umc
= 1;
2285 sprintf(priv
->chip_vendor
, "unknown");
2289 if (val32
& SYS_CFG_VENDOR_ID
) {
2290 sprintf(priv
->chip_vendor
, "UMC");
2291 priv
->vendor_umc
= 1;
2293 sprintf(priv
->chip_vendor
, "TSMC");
2297 val32
= rtl8xxxu_read32(priv
, REG_GPIO_OUTSTS
);
2298 priv
->rom_rev
= (val32
& GPIO_RF_RL_ID
) >> 28;
2300 val16
= rtl8xxxu_read16(priv
, REG_NORMAL_SIE_EP_TX
);
2301 if (val16
& NORMAL_SIE_EP_TX_HIGH_MASK
) {
2302 priv
->ep_tx_high_queue
= 1;
2303 priv
->ep_tx_count
++;
2306 if (val16
& NORMAL_SIE_EP_TX_NORMAL_MASK
) {
2307 priv
->ep_tx_normal_queue
= 1;
2308 priv
->ep_tx_count
++;
2311 if (val16
& NORMAL_SIE_EP_TX_LOW_MASK
) {
2312 priv
->ep_tx_low_queue
= 1;
2313 priv
->ep_tx_count
++;
2317 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
2319 if (!priv
->ep_tx_count
) {
2320 switch (priv
->nr_out_eps
) {
2323 priv
->ep_tx_low_queue
= 1;
2324 priv
->ep_tx_count
++;
2326 priv
->ep_tx_normal_queue
= 1;
2327 priv
->ep_tx_count
++;
2329 priv
->ep_tx_high_queue
= 1;
2330 priv
->ep_tx_count
++;
2333 dev_info(dev
, "Unsupported USB TX end-points\n");
2341 static int rtl8723au_parse_efuse(struct rtl8xxxu_priv
*priv
)
2343 struct rtl8723au_efuse
*efuse
= &priv
->efuse_wifi
.efuse8723
;
2345 if (efuse
->rtl_id
!= cpu_to_le16(0x8129))
2348 ether_addr_copy(priv
->mac_addr
, efuse
->mac_addr
);
2350 memcpy(priv
->cck_tx_power_index_A
,
2351 efuse
->cck_tx_power_index_A
,
2352 sizeof(efuse
->cck_tx_power_index_A
));
2353 memcpy(priv
->cck_tx_power_index_B
,
2354 efuse
->cck_tx_power_index_B
,
2355 sizeof(efuse
->cck_tx_power_index_B
));
2357 memcpy(priv
->ht40_1s_tx_power_index_A
,
2358 efuse
->ht40_1s_tx_power_index_A
,
2359 sizeof(efuse
->ht40_1s_tx_power_index_A
));
2360 memcpy(priv
->ht40_1s_tx_power_index_B
,
2361 efuse
->ht40_1s_tx_power_index_B
,
2362 sizeof(efuse
->ht40_1s_tx_power_index_B
));
2364 memcpy(priv
->ht20_tx_power_index_diff
,
2365 efuse
->ht20_tx_power_index_diff
,
2366 sizeof(efuse
->ht20_tx_power_index_diff
));
2367 memcpy(priv
->ofdm_tx_power_index_diff
,
2368 efuse
->ofdm_tx_power_index_diff
,
2369 sizeof(efuse
->ofdm_tx_power_index_diff
));
2371 memcpy(priv
->ht40_max_power_offset
,
2372 efuse
->ht40_max_power_offset
,
2373 sizeof(efuse
->ht40_max_power_offset
));
2374 memcpy(priv
->ht20_max_power_offset
,
2375 efuse
->ht20_max_power_offset
,
2376 sizeof(efuse
->ht20_max_power_offset
));
2378 if (priv
->efuse_wifi
.efuse8723
.version
>= 0x01) {
2379 priv
->has_xtalk
= 1;
2380 priv
->xtalk
= priv
->efuse_wifi
.efuse8723
.xtal_k
& 0x3f;
2382 dev_info(&priv
->udev
->dev
, "Vendor: %.7s\n",
2383 efuse
->vendor_name
);
2384 dev_info(&priv
->udev
->dev
, "Product: %.41s\n",
2385 efuse
->device_name
);
2389 static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv
*priv
)
2391 struct rtl8723bu_efuse
*efuse
= &priv
->efuse_wifi
.efuse8723bu
;
2394 if (efuse
->rtl_id
!= cpu_to_le16(0x8129))
2397 ether_addr_copy(priv
->mac_addr
, efuse
->mac_addr
);
2399 memcpy(priv
->cck_tx_power_index_A
, efuse
->tx_power_index_A
.cck_base
,
2400 sizeof(efuse
->tx_power_index_A
.cck_base
));
2401 memcpy(priv
->cck_tx_power_index_B
, efuse
->tx_power_index_B
.cck_base
,
2402 sizeof(efuse
->tx_power_index_B
.cck_base
));
2404 memcpy(priv
->ht40_1s_tx_power_index_A
,
2405 efuse
->tx_power_index_A
.ht40_base
,
2406 sizeof(efuse
->tx_power_index_A
.ht40_base
));
2407 memcpy(priv
->ht40_1s_tx_power_index_B
,
2408 efuse
->tx_power_index_B
.ht40_base
,
2409 sizeof(efuse
->tx_power_index_B
.ht40_base
));
2411 priv
->ofdm_tx_power_diff
[0].a
=
2412 efuse
->tx_power_index_A
.ht20_ofdm_1s_diff
.a
;
2413 priv
->ofdm_tx_power_diff
[0].b
=
2414 efuse
->tx_power_index_B
.ht20_ofdm_1s_diff
.a
;
2416 priv
->ht20_tx_power_diff
[0].a
=
2417 efuse
->tx_power_index_A
.ht20_ofdm_1s_diff
.b
;
2418 priv
->ht20_tx_power_diff
[0].b
=
2419 efuse
->tx_power_index_B
.ht20_ofdm_1s_diff
.b
;
2421 priv
->ht40_tx_power_diff
[0].a
= 0;
2422 priv
->ht40_tx_power_diff
[0].b
= 0;
2424 for (i
= 1; i
< RTL8723B_TX_COUNT
; i
++) {
2425 priv
->ofdm_tx_power_diff
[i
].a
=
2426 efuse
->tx_power_index_A
.pwr_diff
[i
- 1].ofdm
;
2427 priv
->ofdm_tx_power_diff
[i
].b
=
2428 efuse
->tx_power_index_B
.pwr_diff
[i
- 1].ofdm
;
2430 priv
->ht20_tx_power_diff
[i
].a
=
2431 efuse
->tx_power_index_A
.pwr_diff
[i
- 1].ht20
;
2432 priv
->ht20_tx_power_diff
[i
].b
=
2433 efuse
->tx_power_index_B
.pwr_diff
[i
- 1].ht20
;
2435 priv
->ht40_tx_power_diff
[i
].a
=
2436 efuse
->tx_power_index_A
.pwr_diff
[i
- 1].ht40
;
2437 priv
->ht40_tx_power_diff
[i
].b
=
2438 efuse
->tx_power_index_B
.pwr_diff
[i
- 1].ht40
;
2441 priv
->has_xtalk
= 1;
2442 priv
->xtalk
= priv
->efuse_wifi
.efuse8723bu
.xtal_k
& 0x3f;
2444 dev_info(&priv
->udev
->dev
, "Vendor: %.7s\n", efuse
->vendor_name
);
2445 dev_info(&priv
->udev
->dev
, "Product: %.41s\n", efuse
->device_name
);
2447 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_EFUSE
) {
2449 unsigned char *raw
= priv
->efuse_wifi
.raw
;
2451 dev_info(&priv
->udev
->dev
,
2452 "%s: dumping efuse (0x%02zx bytes):\n",
2453 __func__
, sizeof(struct rtl8723bu_efuse
));
2454 for (i
= 0; i
< sizeof(struct rtl8723bu_efuse
); i
+= 8) {
2455 dev_info(&priv
->udev
->dev
, "%02x: "
2456 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i
,
2457 raw
[i
], raw
[i
+ 1], raw
[i
+ 2],
2458 raw
[i
+ 3], raw
[i
+ 4], raw
[i
+ 5],
2459 raw
[i
+ 6], raw
[i
+ 7]);
2466 #ifdef CONFIG_RTL8XXXU_UNTESTED
2468 static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv
*priv
)
2470 struct rtl8192cu_efuse
*efuse
= &priv
->efuse_wifi
.efuse8192
;
2473 if (efuse
->rtl_id
!= cpu_to_le16(0x8129))
2476 ether_addr_copy(priv
->mac_addr
, efuse
->mac_addr
);
2478 memcpy(priv
->cck_tx_power_index_A
,
2479 efuse
->cck_tx_power_index_A
,
2480 sizeof(efuse
->cck_tx_power_index_A
));
2481 memcpy(priv
->cck_tx_power_index_B
,
2482 efuse
->cck_tx_power_index_B
,
2483 sizeof(efuse
->cck_tx_power_index_B
));
2485 memcpy(priv
->ht40_1s_tx_power_index_A
,
2486 efuse
->ht40_1s_tx_power_index_A
,
2487 sizeof(efuse
->ht40_1s_tx_power_index_A
));
2488 memcpy(priv
->ht40_1s_tx_power_index_B
,
2489 efuse
->ht40_1s_tx_power_index_B
,
2490 sizeof(efuse
->ht40_1s_tx_power_index_B
));
2491 memcpy(priv
->ht40_2s_tx_power_index_diff
,
2492 efuse
->ht40_2s_tx_power_index_diff
,
2493 sizeof(efuse
->ht40_2s_tx_power_index_diff
));
2495 memcpy(priv
->ht20_tx_power_index_diff
,
2496 efuse
->ht20_tx_power_index_diff
,
2497 sizeof(efuse
->ht20_tx_power_index_diff
));
2498 memcpy(priv
->ofdm_tx_power_index_diff
,
2499 efuse
->ofdm_tx_power_index_diff
,
2500 sizeof(efuse
->ofdm_tx_power_index_diff
));
2502 memcpy(priv
->ht40_max_power_offset
,
2503 efuse
->ht40_max_power_offset
,
2504 sizeof(efuse
->ht40_max_power_offset
));
2505 memcpy(priv
->ht20_max_power_offset
,
2506 efuse
->ht20_max_power_offset
,
2507 sizeof(efuse
->ht20_max_power_offset
));
2509 dev_info(&priv
->udev
->dev
, "Vendor: %.7s\n",
2510 efuse
->vendor_name
);
2511 dev_info(&priv
->udev
->dev
, "Product: %.20s\n",
2512 efuse
->device_name
);
2514 if (efuse
->rf_regulatory
& 0x20) {
2515 sprintf(priv
->chip_name
, "8188RU");
2519 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_EFUSE
) {
2520 unsigned char *raw
= priv
->efuse_wifi
.raw
;
2522 dev_info(&priv
->udev
->dev
,
2523 "%s: dumping efuse (0x%02zx bytes):\n",
2524 __func__
, sizeof(struct rtl8192cu_efuse
));
2525 for (i
= 0; i
< sizeof(struct rtl8192cu_efuse
); i
+= 8) {
2526 dev_info(&priv
->udev
->dev
, "%02x: "
2527 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i
,
2528 raw
[i
], raw
[i
+ 1], raw
[i
+ 2],
2529 raw
[i
+ 3], raw
[i
+ 4], raw
[i
+ 5],
2530 raw
[i
+ 6], raw
[i
+ 7]);
2538 static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv
*priv
)
2540 struct rtl8192eu_efuse
*efuse
= &priv
->efuse_wifi
.efuse8192eu
;
2543 if (efuse
->rtl_id
!= cpu_to_le16(0x8129))
2546 ether_addr_copy(priv
->mac_addr
, efuse
->mac_addr
);
2548 priv
->has_xtalk
= 1;
2549 priv
->xtalk
= priv
->efuse_wifi
.efuse8192eu
.xtal_k
& 0x3f;
2551 dev_info(&priv
->udev
->dev
, "Vendor: %.7s\n", efuse
->vendor_name
);
2552 dev_info(&priv
->udev
->dev
, "Product: %.11s\n", efuse
->device_name
);
2553 dev_info(&priv
->udev
->dev
, "Serial: %.11s\n", efuse
->serial
);
2555 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_EFUSE
) {
2556 unsigned char *raw
= priv
->efuse_wifi
.raw
;
2558 dev_info(&priv
->udev
->dev
,
2559 "%s: dumping efuse (0x%02zx bytes):\n",
2560 __func__
, sizeof(struct rtl8192eu_efuse
));
2561 for (i
= 0; i
< sizeof(struct rtl8192eu_efuse
); i
+= 8) {
2562 dev_info(&priv
->udev
->dev
, "%02x: "
2563 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i
,
2564 raw
[i
], raw
[i
+ 1], raw
[i
+ 2],
2565 raw
[i
+ 3], raw
[i
+ 4], raw
[i
+ 5],
2566 raw
[i
+ 6], raw
[i
+ 7]);
2573 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv
*priv
, u16 offset
, u8
*data
)
2580 rtl8xxxu_write8(priv
, REG_EFUSE_CTRL
+ 1, offset
& 0xff);
2581 val8
= rtl8xxxu_read8(priv
, REG_EFUSE_CTRL
+ 2);
2583 val8
|= (offset
>> 8) & 0x03;
2584 rtl8xxxu_write8(priv
, REG_EFUSE_CTRL
+ 2, val8
);
2586 val8
= rtl8xxxu_read8(priv
, REG_EFUSE_CTRL
+ 3);
2587 rtl8xxxu_write8(priv
, REG_EFUSE_CTRL
+ 3, val8
& 0x7f);
2589 /* Poll for data read */
2590 val32
= rtl8xxxu_read32(priv
, REG_EFUSE_CTRL
);
2591 for (i
= 0; i
< RTL8XXXU_MAX_REG_POLL
; i
++) {
2592 val32
= rtl8xxxu_read32(priv
, REG_EFUSE_CTRL
);
2593 if (val32
& BIT(31))
2597 if (i
== RTL8XXXU_MAX_REG_POLL
)
2601 val32
= rtl8xxxu_read32(priv
, REG_EFUSE_CTRL
);
2603 *data
= val32
& 0xff;
2607 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv
*priv
)
2609 struct device
*dev
= &priv
->udev
->dev
;
2611 u8 val8
, word_mask
, header
, extheader
;
2612 u16 val16
, efuse_addr
, offset
;
2615 val16
= rtl8xxxu_read16(priv
, REG_9346CR
);
2616 if (val16
& EEPROM_ENABLE
)
2617 priv
->has_eeprom
= 1;
2618 if (val16
& EEPROM_BOOT
)
2619 priv
->boot_eeprom
= 1;
2621 if (priv
->is_multi_func
) {
2622 val32
= rtl8xxxu_read32(priv
, REG_EFUSE_TEST
);
2623 val32
= (val32
& ~EFUSE_SELECT_MASK
) | EFUSE_WIFI_SELECT
;
2624 rtl8xxxu_write32(priv
, REG_EFUSE_TEST
, val32
);
2627 dev_dbg(dev
, "Booting from %s\n",
2628 priv
->boot_eeprom
? "EEPROM" : "EFUSE");
2630 rtl8xxxu_write8(priv
, REG_EFUSE_ACCESS
, EFUSE_ACCESS_ENABLE
);
2632 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
2633 val16
= rtl8xxxu_read16(priv
, REG_SYS_ISO_CTRL
);
2634 if (!(val16
& SYS_ISO_PWC_EV12V
)) {
2635 val16
|= SYS_ISO_PWC_EV12V
;
2636 rtl8xxxu_write16(priv
, REG_SYS_ISO_CTRL
, val16
);
2638 /* Reset: 0x0000[28], default valid */
2639 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
2640 if (!(val16
& SYS_FUNC_ELDR
)) {
2641 val16
|= SYS_FUNC_ELDR
;
2642 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
2646 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
2648 val16
= rtl8xxxu_read16(priv
, REG_SYS_CLKR
);
2649 if (!(val16
& SYS_CLK_LOADER_ENABLE
) || !(val16
& SYS_CLK_ANA8M
)) {
2650 val16
|= (SYS_CLK_LOADER_ENABLE
| SYS_CLK_ANA8M
);
2651 rtl8xxxu_write16(priv
, REG_SYS_CLKR
, val16
);
2654 /* Default value is 0xff */
2655 memset(priv
->efuse_wifi
.raw
, 0xff, EFUSE_MAP_LEN
);
2658 while (efuse_addr
< EFUSE_REAL_CONTENT_LEN_8723A
) {
2661 ret
= rtl8xxxu_read_efuse8(priv
, efuse_addr
++, &header
);
2662 if (ret
|| header
== 0xff)
2665 if ((header
& 0x1f) == 0x0f) { /* extended header */
2666 offset
= (header
& 0xe0) >> 5;
2668 ret
= rtl8xxxu_read_efuse8(priv
, efuse_addr
++,
2672 /* All words disabled */
2673 if ((extheader
& 0x0f) == 0x0f)
2676 offset
|= ((extheader
& 0xf0) >> 1);
2677 word_mask
= extheader
& 0x0f;
2679 offset
= (header
>> 4) & 0x0f;
2680 word_mask
= header
& 0x0f;
2683 /* Get word enable value from PG header */
2685 /* We have 8 bits to indicate validity */
2686 map_addr
= offset
* 8;
2687 if (map_addr
>= EFUSE_MAP_LEN
) {
2688 dev_warn(dev
, "%s: Illegal map_addr (%04x), "
2690 __func__
, map_addr
);
2694 for (i
= 0; i
< EFUSE_MAX_WORD_UNIT
; i
++) {
2695 /* Check word enable condition in the section */
2696 if (word_mask
& BIT(i
)) {
2701 ret
= rtl8xxxu_read_efuse8(priv
, efuse_addr
++, &val8
);
2704 priv
->efuse_wifi
.raw
[map_addr
++] = val8
;
2706 ret
= rtl8xxxu_read_efuse8(priv
, efuse_addr
++, &val8
);
2709 priv
->efuse_wifi
.raw
[map_addr
++] = val8
;
2714 rtl8xxxu_write8(priv
, REG_EFUSE_ACCESS
, EFUSE_ACCESS_DISABLE
);
2719 static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv
*priv
)
2724 val8
= rtl8xxxu_read8(priv
, REG_RSV_CTRL
+ 1);
2726 rtl8xxxu_write8(priv
, REG_RSV_CTRL
+ 1, val8
);
2727 sys_func
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
2728 sys_func
&= ~SYS_FUNC_CPU_ENABLE
;
2729 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, sys_func
);
2730 val8
= rtl8xxxu_read8(priv
, REG_RSV_CTRL
+ 1);
2732 rtl8xxxu_write8(priv
, REG_RSV_CTRL
+ 1, val8
);
2733 sys_func
|= SYS_FUNC_CPU_ENABLE
;
2734 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, sys_func
);
2737 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv
*priv
)
2739 struct device
*dev
= &priv
->udev
->dev
;
2743 /* Poll checksum report */
2744 for (i
= 0; i
< RTL8XXXU_FIRMWARE_POLL_MAX
; i
++) {
2745 val32
= rtl8xxxu_read32(priv
, REG_MCU_FW_DL
);
2746 if (val32
& MCU_FW_DL_CSUM_REPORT
)
2750 if (i
== RTL8XXXU_FIRMWARE_POLL_MAX
) {
2751 dev_warn(dev
, "Firmware checksum poll timed out\n");
2756 val32
= rtl8xxxu_read32(priv
, REG_MCU_FW_DL
);
2757 val32
|= MCU_FW_DL_READY
;
2758 val32
&= ~MCU_WINT_INIT_READY
;
2759 rtl8xxxu_write32(priv
, REG_MCU_FW_DL
, val32
);
2762 * Reset the 8051 in order for the firmware to start running,
2763 * otherwise it won't come up on the 8192eu
2765 rtl8xxxu_reset_8051(priv
);
2767 /* Wait for firmware to become ready */
2768 for (i
= 0; i
< RTL8XXXU_FIRMWARE_POLL_MAX
; i
++) {
2769 val32
= rtl8xxxu_read32(priv
, REG_MCU_FW_DL
);
2770 if (val32
& MCU_WINT_INIT_READY
)
2776 if (i
== RTL8XXXU_FIRMWARE_POLL_MAX
) {
2777 dev_warn(dev
, "Firmware failed to start\n");
2785 if (priv
->rtlchip
== 0x8723b)
2786 rtl8xxxu_write8(priv
, REG_HMTFR
, 0x0f);
2791 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv
*priv
)
2793 int pages
, remainder
, i
, ret
;
2799 val8
= rtl8xxxu_read8(priv
, REG_SYS_FUNC
+ 1);
2801 rtl8xxxu_write8(priv
, REG_SYS_FUNC
+ 1, val8
);
2804 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
2805 val16
|= SYS_FUNC_CPU_ENABLE
;
2806 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
2808 val8
= rtl8xxxu_read8(priv
, REG_MCU_FW_DL
);
2809 if (val8
& MCU_FW_RAM_SEL
) {
2810 pr_info("do the RAM reset\n");
2811 rtl8xxxu_write8(priv
, REG_MCU_FW_DL
, 0x00);
2812 rtl8xxxu_reset_8051(priv
);
2815 /* MCU firmware download enable */
2816 val8
= rtl8xxxu_read8(priv
, REG_MCU_FW_DL
);
2817 val8
|= MCU_FW_DL_ENABLE
;
2818 rtl8xxxu_write8(priv
, REG_MCU_FW_DL
, val8
);
2821 val32
= rtl8xxxu_read32(priv
, REG_MCU_FW_DL
);
2823 rtl8xxxu_write32(priv
, REG_MCU_FW_DL
, val32
);
2825 /* Reset firmware download checksum */
2826 val8
= rtl8xxxu_read8(priv
, REG_MCU_FW_DL
);
2827 val8
|= MCU_FW_DL_CSUM_REPORT
;
2828 rtl8xxxu_write8(priv
, REG_MCU_FW_DL
, val8
);
2830 pages
= priv
->fw_size
/ RTL_FW_PAGE_SIZE
;
2831 remainder
= priv
->fw_size
% RTL_FW_PAGE_SIZE
;
2833 fwptr
= priv
->fw_data
->data
;
2835 for (i
= 0; i
< pages
; i
++) {
2836 val8
= rtl8xxxu_read8(priv
, REG_MCU_FW_DL
+ 2) & 0xF8;
2838 rtl8xxxu_write8(priv
, REG_MCU_FW_DL
+ 2, val8
);
2840 ret
= rtl8xxxu_writeN(priv
, REG_FW_START_ADDRESS
,
2841 fwptr
, RTL_FW_PAGE_SIZE
);
2842 if (ret
!= RTL_FW_PAGE_SIZE
) {
2847 fwptr
+= RTL_FW_PAGE_SIZE
;
2851 val8
= rtl8xxxu_read8(priv
, REG_MCU_FW_DL
+ 2) & 0xF8;
2853 rtl8xxxu_write8(priv
, REG_MCU_FW_DL
+ 2, val8
);
2854 ret
= rtl8xxxu_writeN(priv
, REG_FW_START_ADDRESS
,
2856 if (ret
!= remainder
) {
2864 /* MCU firmware download disable */
2865 val16
= rtl8xxxu_read16(priv
, REG_MCU_FW_DL
);
2866 val16
&= ~MCU_FW_DL_ENABLE
;
2867 rtl8xxxu_write16(priv
, REG_MCU_FW_DL
, val16
);
2872 static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv
*priv
, char *fw_name
)
2874 struct device
*dev
= &priv
->udev
->dev
;
2875 const struct firmware
*fw
;
2879 dev_info(dev
, "%s: Loading firmware %s\n", DRIVER_NAME
, fw_name
);
2880 if (request_firmware(&fw
, fw_name
, &priv
->udev
->dev
)) {
2881 dev_warn(dev
, "request_firmware(%s) failed\n", fw_name
);
2886 dev_warn(dev
, "Firmware data not available\n");
2891 priv
->fw_data
= kmemdup(fw
->data
, fw
->size
, GFP_KERNEL
);
2892 if (!priv
->fw_data
) {
2896 priv
->fw_size
= fw
->size
- sizeof(struct rtl8xxxu_firmware_header
);
2898 signature
= le16_to_cpu(priv
->fw_data
->signature
);
2899 switch (signature
& 0xfff0) {
2908 dev_warn(dev
, "%s: Invalid firmware signature: 0x%04x\n",
2909 __func__
, signature
);
2912 dev_info(dev
, "Firmware revision %i.%i (signature 0x%04x)\n",
2913 le16_to_cpu(priv
->fw_data
->major_version
),
2914 priv
->fw_data
->minor_version
, signature
);
2917 release_firmware(fw
);
2921 static int rtl8723au_load_firmware(struct rtl8xxxu_priv
*priv
)
2926 switch (priv
->chip_cut
) {
2928 fw_name
= "rtlwifi/rtl8723aufw_A.bin";
2931 if (priv
->enable_bluetooth
)
2932 fw_name
= "rtlwifi/rtl8723aufw_B.bin";
2934 fw_name
= "rtlwifi/rtl8723aufw_B_NoBT.bin";
2941 ret
= rtl8xxxu_load_firmware(priv
, fw_name
);
2945 static int rtl8723bu_load_firmware(struct rtl8xxxu_priv
*priv
)
2950 if (priv
->enable_bluetooth
)
2951 fw_name
= "rtlwifi/rtl8723bu_bt.bin";
2953 fw_name
= "rtlwifi/rtl8723bu_nic.bin";
2955 ret
= rtl8xxxu_load_firmware(priv
, fw_name
);
2959 #ifdef CONFIG_RTL8XXXU_UNTESTED
2961 static int rtl8192cu_load_firmware(struct rtl8xxxu_priv
*priv
)
2966 if (!priv
->vendor_umc
)
2967 fw_name
= "rtlwifi/rtl8192cufw_TMSC.bin";
2968 else if (priv
->chip_cut
|| priv
->rtlchip
== 0x8192c)
2969 fw_name
= "rtlwifi/rtl8192cufw_B.bin";
2971 fw_name
= "rtlwifi/rtl8192cufw_A.bin";
2973 ret
= rtl8xxxu_load_firmware(priv
, fw_name
);
2980 static int rtl8192eu_load_firmware(struct rtl8xxxu_priv
*priv
)
2985 fw_name
= "rtlwifi/rtl8192eu_nic.bin";
2987 ret
= rtl8xxxu_load_firmware(priv
, fw_name
);
2992 static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv
*priv
)
2997 /* Inform 8051 to perform reset */
2998 rtl8xxxu_write8(priv
, REG_HMTFR
+ 3, 0x20);
3000 for (i
= 100; i
> 0; i
--) {
3001 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
3003 if (!(val16
& SYS_FUNC_CPU_ENABLE
)) {
3004 dev_dbg(&priv
->udev
->dev
,
3005 "%s: Firmware self reset success!\n", __func__
);
3012 /* Force firmware reset */
3013 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
3014 val16
&= ~SYS_FUNC_CPU_ENABLE
;
3015 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
3019 static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv
*priv
)
3023 val32
= rtl8xxxu_read32(priv
, 0x64);
3024 val32
&= ~(BIT(20) | BIT(24));
3025 rtl8xxxu_write32(priv
, 0x64, val32
);
3027 val32
= rtl8xxxu_read32(priv
, REG_GPIO_MUXCFG
);
3029 rtl8xxxu_write32(priv
, REG_GPIO_MUXCFG
, val32
);
3031 val32
= rtl8xxxu_read32(priv
, REG_GPIO_MUXCFG
);
3033 rtl8xxxu_write32(priv
, REG_GPIO_MUXCFG
, val32
);
3035 val32
= rtl8xxxu_read32(priv
, REG_LEDCFG0
);
3037 rtl8xxxu_write32(priv
, REG_LEDCFG0
, val32
);
3039 val32
= rtl8xxxu_read32(priv
, REG_LEDCFG0
);
3041 rtl8xxxu_write32(priv
, REG_LEDCFG0
, val32
);
3043 val32
= rtl8xxxu_read32(priv
, REG_RFE_BUFFER
);
3044 val32
|= (BIT(0) | BIT(1));
3045 rtl8xxxu_write32(priv
, REG_RFE_BUFFER
, val32
);
3047 val32
= rtl8xxxu_read32(priv
, REG_RFE_CTRL_ANTA_SRC
);
3048 val32
&= 0xffffff00;
3050 rtl8xxxu_write32(priv
, REG_RFE_CTRL_ANTA_SRC
, val32
);
3052 val32
= rtl8xxxu_read32(priv
, REG_PWR_DATA
);
3053 val32
|= PWR_DATA_EEPRPAD_RFE_CTRL_EN
;
3054 rtl8xxxu_write32(priv
, REG_PWR_DATA
, val32
);
3058 rtl8xxxu_init_mac(struct rtl8xxxu_priv
*priv
, struct rtl8xxxu_reg8val
*array
)
3064 for (i
= 0; ; i
++) {
3068 if (reg
== 0xffff && val
== 0xff)
3071 ret
= rtl8xxxu_write8(priv
, reg
, val
);
3073 dev_warn(&priv
->udev
->dev
,
3074 "Failed to initialize MAC\n");
3079 if (priv
->rtlchip
!= 0x8723b)
3080 rtl8xxxu_write8(priv
, REG_MAX_AGGR_NUM
, 0x0a);
3085 static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv
*priv
,
3086 struct rtl8xxxu_reg32val
*array
)
3092 for (i
= 0; ; i
++) {
3096 if (reg
== 0xffff && val
== 0xffffffff)
3099 ret
= rtl8xxxu_write32(priv
, reg
, val
);
3100 if (ret
!= sizeof(val
)) {
3101 dev_warn(&priv
->udev
->dev
,
3102 "Failed to initialize PHY\n");
3112 * Most of this is black magic retrieved from the old rtl8723au driver
3114 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv
*priv
)
3116 u8 val8
, ldoa15
, ldov12d
, lpldo
, ldohci12
;
3121 * Todo: The vendor driver maintains a table of PHY register
3122 * addresses, which is initialized here. Do we need this?
3125 if (priv
->rtlchip
== 0x8723b) {
3126 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
3127 val16
|= SYS_FUNC_BB_GLB_RSTN
| SYS_FUNC_BBRSTB
|
3129 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
3131 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00);
3133 val8
= rtl8xxxu_read8(priv
, REG_AFE_PLL_CTRL
);
3135 val8
|= AFE_PLL_320_ENABLE
;
3136 rtl8xxxu_write8(priv
, REG_AFE_PLL_CTRL
, val8
);
3139 rtl8xxxu_write8(priv
, REG_AFE_PLL_CTRL
+ 1, 0xff);
3142 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
3143 val16
|= SYS_FUNC_BB_GLB_RSTN
| SYS_FUNC_BBRSTB
;
3144 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
3147 if (priv
->rtlchip
!= 0x8723b) {
3148 /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
3149 val32
= rtl8xxxu_read32(priv
, REG_AFE_XTAL_CTRL
);
3150 val32
&= ~AFE_XTAL_RF_GATE
;
3151 if (priv
->has_bluetooth
)
3152 val32
&= ~AFE_XTAL_BT_GATE
;
3153 rtl8xxxu_write32(priv
, REG_AFE_XTAL_CTRL
, val32
);
3156 /* 6. 0x1f[7:0] = 0x07 */
3157 val8
= RF_ENABLE
| RF_RSTB
| RF_SDMRSTB
;
3158 rtl8xxxu_write8(priv
, REG_RF_CTRL
, val8
);
3161 rtl8xxxu_init_phy_regs(priv
, rtl8188ru_phy_1t_highpa_table
);
3162 else if (priv
->tx_paths
== 2)
3163 rtl8xxxu_init_phy_regs(priv
, rtl8192cu_phy_2t_init_table
);
3164 else if (priv
->rtlchip
== 0x8723b) {
3168 rtl8xxxu_write8(priv
, REG_SYS_FUNC
, 0xe3);
3169 rtl8xxxu_write8(priv
, REG_AFE_XTAL_CTRL
+ 1, 0x80);
3170 rtl8xxxu_init_phy_regs(priv
, rtl8723b_phy_1t_init_table
);
3172 rtl8xxxu_init_phy_regs(priv
, rtl8723a_phy_1t_init_table
);
3175 if (priv
->rtlchip
== 0x8188c && priv
->hi_pa
&&
3176 priv
->vendor_umc
&& priv
->chip_cut
== 1)
3177 rtl8xxxu_write8(priv
, REG_OFDM0_AGC_PARM1
+ 2, 0x50);
3179 if (priv
->tx_paths
== 1 && priv
->rx_paths
== 2) {
3181 * For 1T2R boards, patch the registers.
3183 * It looks like 8191/2 1T2R boards use path B for TX
3185 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_TX_INFO
);
3186 val32
&= ~(BIT(0) | BIT(1));
3188 rtl8xxxu_write32(priv
, REG_FPGA0_TX_INFO
, val32
);
3190 val32
= rtl8xxxu_read32(priv
, REG_FPGA1_TX_INFO
);
3193 rtl8xxxu_write32(priv
, REG_FPGA1_TX_INFO
, val32
);
3195 val32
= rtl8xxxu_read32(priv
, REG_CCK0_AFE_SETTING
);
3196 val32
&= 0xff000000;
3197 val32
|= 0x45000000;
3198 rtl8xxxu_write32(priv
, REG_CCK0_AFE_SETTING
, val32
);
3200 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_TRX_PATH_ENABLE
);
3201 val32
&= ~(OFDM_RF_PATH_RX_MASK
| OFDM_RF_PATH_TX_MASK
);
3202 val32
|= (OFDM_RF_PATH_RX_A
| OFDM_RF_PATH_RX_B
|
3204 rtl8xxxu_write32(priv
, REG_OFDM0_TRX_PATH_ENABLE
, val32
);
3206 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_AGC_PARM1
);
3207 val32
&= ~(BIT(4) | BIT(5));
3209 rtl8xxxu_write32(priv
, REG_OFDM0_AGC_PARM1
, val32
);
3211 val32
= rtl8xxxu_read32(priv
, REG_TX_CCK_RFON
);
3212 val32
&= ~(BIT(27) | BIT(26));
3214 rtl8xxxu_write32(priv
, REG_TX_CCK_RFON
, val32
);
3216 val32
= rtl8xxxu_read32(priv
, REG_TX_CCK_BBON
);
3217 val32
&= ~(BIT(27) | BIT(26));
3219 rtl8xxxu_write32(priv
, REG_TX_CCK_BBON
, val32
);
3221 val32
= rtl8xxxu_read32(priv
, REG_TX_OFDM_RFON
);
3222 val32
&= ~(BIT(27) | BIT(26));
3224 rtl8xxxu_write32(priv
, REG_TX_OFDM_RFON
, val32
);
3226 val32
= rtl8xxxu_read32(priv
, REG_TX_OFDM_BBON
);
3227 val32
&= ~(BIT(27) | BIT(26));
3229 rtl8xxxu_write32(priv
, REG_TX_OFDM_BBON
, val32
);
3231 val32
= rtl8xxxu_read32(priv
, REG_TX_TO_TX
);
3232 val32
&= ~(BIT(27) | BIT(26));
3234 rtl8xxxu_write32(priv
, REG_TX_TO_TX
, val32
);
3237 if (priv
->rtlchip
== 0x8723b)
3238 rtl8xxxu_init_phy_regs(priv
, rtl8xxx_agc_8723bu_table
);
3239 else if (priv
->hi_pa
)
3240 rtl8xxxu_init_phy_regs(priv
, rtl8xxx_agc_highpa_table
);
3242 rtl8xxxu_init_phy_regs(priv
, rtl8xxx_agc_standard_table
);
3244 if (priv
->has_xtalk
) {
3245 val32
= rtl8xxxu_read32(priv
, REG_MAC_PHY_CTRL
);
3248 val32
&= 0xff000fff;
3249 val32
|= ((val8
| (val8
<< 6)) << 12);
3251 rtl8xxxu_write32(priv
, REG_MAC_PHY_CTRL
, val32
);
3254 if (priv
->rtlchip
!= 0x8723bu
) {
3255 ldoa15
= LDOA15_ENABLE
| LDOA15_OBUF
;
3256 ldov12d
= LDOV12D_ENABLE
| BIT(2) | (2 << LDOV12D_VADJ_SHIFT
);
3259 val32
= (lpldo
<< 24) | (ldohci12
<< 16) |
3260 (ldov12d
<< 8) | ldoa15
;
3262 rtl8xxxu_write32(priv
, REG_LDOA15_CTRL
, val32
);
3268 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv
*priv
,
3269 struct rtl8xxxu_rfregval
*array
,
3270 enum rtl8xxxu_rfpath path
)
3276 for (i
= 0; ; i
++) {
3280 if (reg
== 0xff && val
== 0xffffffff)
3304 ret
= rtl8xxxu_write_rfreg(priv
, path
, reg
, val
);
3306 dev_warn(&priv
->udev
->dev
,
3307 "Failed to initialize RF\n");
3316 static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv
*priv
,
3317 struct rtl8xxxu_rfregval
*table
,
3318 enum rtl8xxxu_rfpath path
)
3321 u16 val16
, rfsi_rfenv
;
3322 u16 reg_sw_ctrl
, reg_int_oe
, reg_hssi_parm2
;
3326 reg_sw_ctrl
= REG_FPGA0_XA_RF_SW_CTRL
;
3327 reg_int_oe
= REG_FPGA0_XA_RF_INT_OE
;
3328 reg_hssi_parm2
= REG_FPGA0_XA_HSSI_PARM2
;
3331 reg_sw_ctrl
= REG_FPGA0_XB_RF_SW_CTRL
;
3332 reg_int_oe
= REG_FPGA0_XB_RF_INT_OE
;
3333 reg_hssi_parm2
= REG_FPGA0_XB_HSSI_PARM2
;
3336 dev_err(&priv
->udev
->dev
, "%s:Unsupported RF path %c\n",
3337 __func__
, path
+ 'A');
3340 /* For path B, use XB */
3341 rfsi_rfenv
= rtl8xxxu_read16(priv
, reg_sw_ctrl
);
3342 rfsi_rfenv
&= FPGA0_RF_RFENV
;
3345 * These two we might be able to optimize into one
3347 val32
= rtl8xxxu_read32(priv
, reg_int_oe
);
3348 val32
|= BIT(20); /* 0x10 << 16 */
3349 rtl8xxxu_write32(priv
, reg_int_oe
, val32
);
3352 val32
= rtl8xxxu_read32(priv
, reg_int_oe
);
3354 rtl8xxxu_write32(priv
, reg_int_oe
, val32
);
3358 * These two we might be able to optimize into one
3360 val32
= rtl8xxxu_read32(priv
, reg_hssi_parm2
);
3361 val32
&= ~FPGA0_HSSI_3WIRE_ADDR_LEN
;
3362 rtl8xxxu_write32(priv
, reg_hssi_parm2
, val32
);
3365 val32
= rtl8xxxu_read32(priv
, reg_hssi_parm2
);
3366 val32
&= ~FPGA0_HSSI_3WIRE_DATA_LEN
;
3367 rtl8xxxu_write32(priv
, reg_hssi_parm2
, val32
);
3370 rtl8xxxu_init_rf_regs(priv
, table
, path
);
3372 /* For path B, use XB */
3373 val16
= rtl8xxxu_read16(priv
, reg_sw_ctrl
);
3374 val16
&= ~FPGA0_RF_RFENV
;
3375 val16
|= rfsi_rfenv
;
3376 rtl8xxxu_write16(priv
, reg_sw_ctrl
, val16
);
3381 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv
*priv
, u8 address
, u8 data
)
3387 value
= LLT_OP_WRITE
| address
<< 8 | data
;
3389 rtl8xxxu_write32(priv
, REG_LLT_INIT
, value
);
3392 value
= rtl8xxxu_read32(priv
, REG_LLT_INIT
);
3393 if ((value
& LLT_OP_MASK
) == LLT_OP_INACTIVE
) {
3397 } while (count
++ < 20);
3402 static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv
*priv
, u8 last_tx_page
)
3407 for (i
= 0; i
< last_tx_page
; i
++) {
3408 ret
= rtl8xxxu_llt_write(priv
, i
, i
+ 1);
3413 ret
= rtl8xxxu_llt_write(priv
, last_tx_page
, 0xff);
3417 /* Mark remaining pages as a ring buffer */
3418 for (i
= last_tx_page
+ 1; i
< 0xff; i
++) {
3419 ret
= rtl8xxxu_llt_write(priv
, i
, (i
+ 1));
3424 /* Let last entry point to the start entry of ring buffer */
3425 ret
= rtl8xxxu_llt_write(priv
, 0xff, last_tx_page
+ 1);
3433 static int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv
*priv
, u8 last_tx_page
)
3439 val32
= rtl8xxxu_read32(priv
, REG_AUTO_LLT
);
3440 val32
|= AUTO_LLT_INIT_LLT
;
3441 rtl8xxxu_write32(priv
, REG_AUTO_LLT
, val32
);
3443 for (i
= 500; i
; i
--) {
3444 val32
= rtl8xxxu_read32(priv
, REG_AUTO_LLT
);
3445 if (!(val32
& AUTO_LLT_INIT_LLT
))
3452 dev_warn(&priv
->udev
->dev
, "LLT table init failed\n");
3458 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv
*priv
)
3461 u16 hiq
, mgq
, bkq
, beq
, viq
, voq
;
3462 int hip
, mgp
, bkp
, bep
, vip
, vop
;
3465 switch (priv
->ep_tx_count
) {
3467 if (priv
->ep_tx_high_queue
) {
3468 hi
= TRXDMA_QUEUE_HIGH
;
3469 } else if (priv
->ep_tx_low_queue
) {
3470 hi
= TRXDMA_QUEUE_LOW
;
3471 } else if (priv
->ep_tx_normal_queue
) {
3472 hi
= TRXDMA_QUEUE_NORMAL
;
3493 if (priv
->ep_tx_high_queue
&& priv
->ep_tx_low_queue
) {
3494 hi
= TRXDMA_QUEUE_HIGH
;
3495 lo
= TRXDMA_QUEUE_LOW
;
3496 } else if (priv
->ep_tx_normal_queue
&& priv
->ep_tx_low_queue
) {
3497 hi
= TRXDMA_QUEUE_NORMAL
;
3498 lo
= TRXDMA_QUEUE_LOW
;
3499 } else if (priv
->ep_tx_high_queue
&& priv
->ep_tx_normal_queue
) {
3500 hi
= TRXDMA_QUEUE_HIGH
;
3501 lo
= TRXDMA_QUEUE_NORMAL
;
3523 beq
= TRXDMA_QUEUE_LOW
;
3524 bkq
= TRXDMA_QUEUE_LOW
;
3525 viq
= TRXDMA_QUEUE_NORMAL
;
3526 voq
= TRXDMA_QUEUE_HIGH
;
3527 mgq
= TRXDMA_QUEUE_HIGH
;
3528 hiq
= TRXDMA_QUEUE_HIGH
;
3542 * None of the vendor drivers are configuring the beacon
3543 * queue here .... why?
3546 val16
= rtl8xxxu_read16(priv
, REG_TRXDMA_CTRL
);
3548 val16
|= (voq
<< TRXDMA_CTRL_VOQ_SHIFT
) |
3549 (viq
<< TRXDMA_CTRL_VIQ_SHIFT
) |
3550 (beq
<< TRXDMA_CTRL_BEQ_SHIFT
) |
3551 (bkq
<< TRXDMA_CTRL_BKQ_SHIFT
) |
3552 (mgq
<< TRXDMA_CTRL_MGQ_SHIFT
) |
3553 (hiq
<< TRXDMA_CTRL_HIQ_SHIFT
);
3554 rtl8xxxu_write16(priv
, REG_TRXDMA_CTRL
, val16
);
3556 priv
->pipe_out
[TXDESC_QUEUE_VO
] =
3557 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[vop
]);
3558 priv
->pipe_out
[TXDESC_QUEUE_VI
] =
3559 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[vip
]);
3560 priv
->pipe_out
[TXDESC_QUEUE_BE
] =
3561 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[bep
]);
3562 priv
->pipe_out
[TXDESC_QUEUE_BK
] =
3563 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[bkp
]);
3564 priv
->pipe_out
[TXDESC_QUEUE_BEACON
] =
3565 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[0]);
3566 priv
->pipe_out
[TXDESC_QUEUE_MGNT
] =
3567 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[mgp
]);
3568 priv
->pipe_out
[TXDESC_QUEUE_HIGH
] =
3569 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[hip
]);
3570 priv
->pipe_out
[TXDESC_QUEUE_CMD
] =
3571 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[0]);
3577 static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv
*priv
,
3578 bool iqk_ok
, int result
[][8],
3579 int candidate
, bool tx_only
)
3581 u32 oldval
, x
, tx0_a
, reg
;
3588 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_TX_IQ_IMBALANCE
);
3589 oldval
= val32
>> 22;
3591 x
= result
[candidate
][0];
3592 if ((x
& 0x00000200) != 0)
3594 tx0_a
= (x
* oldval
) >> 8;
3596 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_TX_IQ_IMBALANCE
);
3599 rtl8xxxu_write32(priv
, REG_OFDM0_XA_TX_IQ_IMBALANCE
, val32
);
3601 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_ENERGY_CCA_THRES
);
3603 if ((x
* oldval
>> 7) & 0x1)
3605 rtl8xxxu_write32(priv
, REG_OFDM0_ENERGY_CCA_THRES
, val32
);
3607 y
= result
[candidate
][1];
3608 if ((y
& 0x00000200) != 0)
3610 tx0_c
= (y
* oldval
) >> 8;
3612 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XC_TX_AFE
);
3613 val32
&= ~0xf0000000;
3614 val32
|= (((tx0_c
& 0x3c0) >> 6) << 28);
3615 rtl8xxxu_write32(priv
, REG_OFDM0_XC_TX_AFE
, val32
);
3617 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_TX_IQ_IMBALANCE
);
3618 val32
&= ~0x003f0000;
3619 val32
|= ((tx0_c
& 0x3f) << 16);
3620 rtl8xxxu_write32(priv
, REG_OFDM0_XA_TX_IQ_IMBALANCE
, val32
);
3622 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_ENERGY_CCA_THRES
);
3624 if ((y
* oldval
>> 7) & 0x1)
3626 rtl8xxxu_write32(priv
, REG_OFDM0_ENERGY_CCA_THRES
, val32
);
3629 dev_dbg(&priv
->udev
->dev
, "%s: only TX\n", __func__
);
3633 reg
= result
[candidate
][2];
3635 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_RX_IQ_IMBALANCE
);
3637 val32
|= (reg
& 0x3ff);
3638 rtl8xxxu_write32(priv
, REG_OFDM0_XA_RX_IQ_IMBALANCE
, val32
);
3640 reg
= result
[candidate
][3] & 0x3F;
3642 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_RX_IQ_IMBALANCE
);
3644 val32
|= ((reg
<< 10) & 0xfc00);
3645 rtl8xxxu_write32(priv
, REG_OFDM0_XA_RX_IQ_IMBALANCE
, val32
);
3647 reg
= (result
[candidate
][3] >> 6) & 0xF;
3649 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_RX_IQ_EXT_ANTA
);
3650 val32
&= ~0xf0000000;
3651 val32
|= (reg
<< 28);
3652 rtl8xxxu_write32(priv
, REG_OFDM0_RX_IQ_EXT_ANTA
, val32
);
3655 static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv
*priv
,
3656 bool iqk_ok
, int result
[][8],
3657 int candidate
, bool tx_only
)
3659 u32 oldval
, x
, tx1_a
, reg
;
3666 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_TX_IQ_IMBALANCE
);
3667 oldval
= val32
>> 22;
3669 x
= result
[candidate
][4];
3670 if ((x
& 0x00000200) != 0)
3672 tx1_a
= (x
* oldval
) >> 8;
3674 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_TX_IQ_IMBALANCE
);
3677 rtl8xxxu_write32(priv
, REG_OFDM0_XB_TX_IQ_IMBALANCE
, val32
);
3679 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_ENERGY_CCA_THRES
);
3681 if ((x
* oldval
>> 7) & 0x1)
3683 rtl8xxxu_write32(priv
, REG_OFDM0_ENERGY_CCA_THRES
, val32
);
3685 y
= result
[candidate
][5];
3686 if ((y
& 0x00000200) != 0)
3688 tx1_c
= (y
* oldval
) >> 8;
3690 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XD_TX_AFE
);
3691 val32
&= ~0xf0000000;
3692 val32
|= (((tx1_c
& 0x3c0) >> 6) << 28);
3693 rtl8xxxu_write32(priv
, REG_OFDM0_XD_TX_AFE
, val32
);
3695 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_TX_IQ_IMBALANCE
);
3696 val32
&= ~0x003f0000;
3697 val32
|= ((tx1_c
& 0x3f) << 16);
3698 rtl8xxxu_write32(priv
, REG_OFDM0_XB_TX_IQ_IMBALANCE
, val32
);
3700 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_ENERGY_CCA_THRES
);
3702 if ((y
* oldval
>> 7) & 0x1)
3704 rtl8xxxu_write32(priv
, REG_OFDM0_ENERGY_CCA_THRES
, val32
);
3707 dev_dbg(&priv
->udev
->dev
, "%s: only TX\n", __func__
);
3711 reg
= result
[candidate
][6];
3713 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_RX_IQ_IMBALANCE
);
3715 val32
|= (reg
& 0x3ff);
3716 rtl8xxxu_write32(priv
, REG_OFDM0_XB_RX_IQ_IMBALANCE
, val32
);
3718 reg
= result
[candidate
][7] & 0x3f;
3720 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_RX_IQ_IMBALANCE
);
3722 val32
|= ((reg
<< 10) & 0xfc00);
3723 rtl8xxxu_write32(priv
, REG_OFDM0_XB_RX_IQ_IMBALANCE
, val32
);
3725 reg
= (result
[candidate
][7] >> 6) & 0xf;
3727 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_AGCR_SSI_TABLE
);
3728 val32
&= ~0x0000f000;
3729 val32
|= (reg
<< 12);
3730 rtl8xxxu_write32(priv
, REG_OFDM0_AGCR_SSI_TABLE
, val32
);
3733 #define MAX_TOLERANCE 5
3735 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv
*priv
,
3736 int result
[][8], int c1
, int c2
)
3738 u32 i
, j
, diff
, simubitmap
, bound
= 0;
3739 int candidate
[2] = {-1, -1}; /* for path A and path B */
3742 if (priv
->tx_paths
> 1)
3749 for (i
= 0; i
< bound
; i
++) {
3750 diff
= (result
[c1
][i
] > result
[c2
][i
]) ?
3751 (result
[c1
][i
] - result
[c2
][i
]) :
3752 (result
[c2
][i
] - result
[c1
][i
]);
3753 if (diff
> MAX_TOLERANCE
) {
3754 if ((i
== 2 || i
== 6) && !simubitmap
) {
3755 if (result
[c1
][i
] + result
[c1
][i
+ 1] == 0)
3756 candidate
[(i
/ 4)] = c2
;
3757 else if (result
[c2
][i
] + result
[c2
][i
+ 1] == 0)
3758 candidate
[(i
/ 4)] = c1
;
3760 simubitmap
= simubitmap
| (1 << i
);
3762 simubitmap
= simubitmap
| (1 << i
);
3767 if (simubitmap
== 0) {
3768 for (i
= 0; i
< (bound
/ 4); i
++) {
3769 if (candidate
[i
] >= 0) {
3770 for (j
= i
* 4; j
< (i
+ 1) * 4 - 2; j
++)
3771 result
[3][j
] = result
[candidate
[i
]][j
];
3776 } else if (!(simubitmap
& 0x0f)) {
3778 for (i
= 0; i
< 4; i
++)
3779 result
[3][i
] = result
[c1
][i
];
3780 } else if (!(simubitmap
& 0xf0) && priv
->tx_paths
> 1) {
3782 for (i
= 4; i
< 8; i
++)
3783 result
[3][i
] = result
[c1
][i
];
3789 static bool rtl8723bu_simularity_compare(struct rtl8xxxu_priv
*priv
,
3790 int result
[][8], int c1
, int c2
)
3792 u32 i
, j
, diff
, simubitmap
, bound
= 0;
3793 int candidate
[2] = {-1, -1}; /* for path A and path B */
3797 if (priv
->tx_paths
> 1)
3804 for (i
= 0; i
< bound
; i
++) {
3806 if ((result
[c1
][i
] & 0x00000200))
3807 tmp1
= result
[c1
][i
] | 0xfffffc00;
3809 tmp1
= result
[c1
][i
];
3811 if ((result
[c2
][i
]& 0x00000200))
3812 tmp2
= result
[c2
][i
] | 0xfffffc00;
3814 tmp2
= result
[c2
][i
];
3816 tmp1
= result
[c1
][i
];
3817 tmp2
= result
[c2
][i
];
3820 diff
= (tmp1
> tmp2
) ? (tmp1
- tmp2
) : (tmp2
- tmp1
);
3822 if (diff
> MAX_TOLERANCE
) {
3823 if ((i
== 2 || i
== 6) && !simubitmap
) {
3824 if (result
[c1
][i
] + result
[c1
][i
+ 1] == 0)
3825 candidate
[(i
/ 4)] = c2
;
3826 else if (result
[c2
][i
] + result
[c2
][i
+ 1] == 0)
3827 candidate
[(i
/ 4)] = c1
;
3829 simubitmap
= simubitmap
| (1 << i
);
3831 simubitmap
= simubitmap
| (1 << i
);
3836 if (simubitmap
== 0) {
3837 for (i
= 0; i
< (bound
/ 4); i
++) {
3838 if (candidate
[i
] >= 0) {
3839 for (j
= i
* 4; j
< (i
+ 1) * 4 - 2; j
++)
3840 result
[3][j
] = result
[candidate
[i
]][j
];
3846 if (!(simubitmap
& 0x03)) {
3848 for (i
= 0; i
< 2; i
++)
3849 result
[3][i
] = result
[c1
][i
];
3852 if (!(simubitmap
& 0x0c)) {
3854 for (i
= 2; i
< 4; i
++)
3855 result
[3][i
] = result
[c1
][i
];
3858 if (!(simubitmap
& 0x30) && priv
->tx_paths
> 1) {
3860 for (i
= 4; i
< 6; i
++)
3861 result
[3][i
] = result
[c1
][i
];
3864 if (!(simubitmap
& 0x30) && priv
->tx_paths
> 1) {
3866 for (i
= 6; i
< 8; i
++)
3867 result
[3][i
] = result
[c1
][i
];
3875 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv
*priv
, const u32
*reg
, u32
*backup
)
3879 for (i
= 0; i
< (RTL8XXXU_MAC_REGS
- 1); i
++)
3880 backup
[i
] = rtl8xxxu_read8(priv
, reg
[i
]);
3882 backup
[i
] = rtl8xxxu_read32(priv
, reg
[i
]);
3885 static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv
*priv
,
3886 const u32
*reg
, u32
*backup
)
3890 for (i
= 0; i
< (RTL8XXXU_MAC_REGS
- 1); i
++)
3891 rtl8xxxu_write8(priv
, reg
[i
], backup
[i
]);
3893 rtl8xxxu_write32(priv
, reg
[i
], backup
[i
]);
3896 static void rtl8xxxu_save_regs(struct rtl8xxxu_priv
*priv
, const u32
*regs
,
3897 u32
*backup
, int count
)
3901 for (i
= 0; i
< count
; i
++)
3902 backup
[i
] = rtl8xxxu_read32(priv
, regs
[i
]);
3905 static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv
*priv
, const u32
*regs
,
3906 u32
*backup
, int count
)
3910 for (i
= 0; i
< count
; i
++)
3911 rtl8xxxu_write32(priv
, regs
[i
], backup
[i
]);
3915 static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv
*priv
, const u32
*regs
,
3921 if (priv
->tx_paths
== 1) {
3922 path_on
= priv
->fops
->adda_1t_path_on
;
3923 rtl8xxxu_write32(priv
, regs
[0], priv
->fops
->adda_1t_init
);
3925 path_on
= path_a_on
? priv
->fops
->adda_2t_path_on_a
:
3926 priv
->fops
->adda_2t_path_on_b
;
3928 rtl8xxxu_write32(priv
, regs
[0], path_on
);
3931 for (i
= 1 ; i
< RTL8XXXU_ADDA_REGS
; i
++)
3932 rtl8xxxu_write32(priv
, regs
[i
], path_on
);
3935 static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv
*priv
,
3936 const u32
*regs
, u32
*backup
)
3940 rtl8xxxu_write8(priv
, regs
[i
], 0x3f);
3942 for (i
= 1 ; i
< (RTL8XXXU_MAC_REGS
- 1); i
++)
3943 rtl8xxxu_write8(priv
, regs
[i
], (u8
)(backup
[i
] & ~BIT(3)));
3945 rtl8xxxu_write8(priv
, regs
[i
], (u8
)(backup
[i
] & ~BIT(5)));
3948 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv
*priv
)
3950 u32 reg_eac
, reg_e94
, reg_e9c
, reg_ea4
, val32
;
3953 /* path-A IQK setting */
3954 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x10008c1f);
3955 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x10008c1f);
3956 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_A
, 0x82140102);
3958 val32
= (priv
->rf_paths
> 1) ? 0x28160202 :
3959 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3961 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_A
, val32
);
3963 /* path-B IQK setting */
3964 if (priv
->rf_paths
> 1) {
3965 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_B
, 0x10008c22);
3966 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_B
, 0x10008c22);
3967 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_B
, 0x82140102);
3968 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_B
, 0x28160202);
3971 /* LO calibration setting */
3972 rtl8xxxu_write32(priv
, REG_IQK_AGC_RSP
, 0x001028d1);
3974 /* One shot, path A LOK & IQK */
3975 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf9000000);
3976 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf8000000);
3981 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
3982 reg_e94
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_A
);
3983 reg_e9c
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_A
);
3984 reg_ea4
= rtl8xxxu_read32(priv
, REG_RX_POWER_BEFORE_IQK_A_2
);
3986 if (!(reg_eac
& BIT(28)) &&
3987 ((reg_e94
& 0x03ff0000) != 0x01420000) &&
3988 ((reg_e9c
& 0x03ff0000) != 0x00420000))
3990 else /* If TX not OK, ignore RX */
3993 /* If TX is OK, check whether RX is OK */
3994 if (!(reg_eac
& BIT(27)) &&
3995 ((reg_ea4
& 0x03ff0000) != 0x01320000) &&
3996 ((reg_eac
& 0x03ff0000) != 0x00360000))
3999 dev_warn(&priv
->udev
->dev
, "%s: Path A RX IQK failed!\n",
4005 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv
*priv
)
4007 u32 reg_eac
, reg_eb4
, reg_ebc
, reg_ec4
, reg_ecc
;
4010 /* One shot, path B LOK & IQK */
4011 rtl8xxxu_write32(priv
, REG_IQK_AGC_CONT
, 0x00000002);
4012 rtl8xxxu_write32(priv
, REG_IQK_AGC_CONT
, 0x00000000);
4017 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
4018 reg_eb4
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_B
);
4019 reg_ebc
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_B
);
4020 reg_ec4
= rtl8xxxu_read32(priv
, REG_RX_POWER_BEFORE_IQK_B_2
);
4021 reg_ecc
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_B_2
);
4023 if (!(reg_eac
& BIT(31)) &&
4024 ((reg_eb4
& 0x03ff0000) != 0x01420000) &&
4025 ((reg_ebc
& 0x03ff0000) != 0x00420000))
4030 if (!(reg_eac
& BIT(30)) &&
4031 (((reg_ec4
& 0x03ff0000) >> 16) != 0x132) &&
4032 (((reg_ecc
& 0x03ff0000) >> 16) != 0x36))
4035 dev_warn(&priv
->udev
->dev
, "%s: Path B RX IQK failed!\n",
4041 static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv
*priv
)
4043 u32 reg_eac
, reg_e94
, reg_e9c
, path_sel
, val32
;
4046 path_sel
= rtl8xxxu_read32(priv
, REG_S0S1_PATH_SWITCH
);
4051 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4052 val32
&= 0x000000ff;
4053 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4056 * Enable path A PA in TX IQK mode
4058 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
);
4060 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
, val32
);
4061 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_RCK_OS
, 0x20000);
4062 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G1
, 0x0003f);
4063 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G2
, 0xc7f87);
4068 rtl8xxxu_write32(priv
, REG_TX_IQK
, 0x01007c00);
4069 rtl8xxxu_write32(priv
, REG_RX_IQK
, 0x01004800);
4071 /* path-A IQK setting */
4072 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x18008c1c);
4073 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x38008c1c);
4074 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_B
, 0x38008c1c);
4075 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_B
, 0x38008c1c);
4077 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_A
, 0x821403ea);
4078 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_A
, 0x28110000);
4079 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_B
, 0x82110000);
4080 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_B
, 0x28110000);
4082 /* LO calibration setting */
4083 rtl8xxxu_write32(priv
, REG_IQK_AGC_RSP
, 0x00462911);
4088 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4089 val32
&= 0x000000ff;
4090 val32
|= 0x80800000;
4091 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4094 * The vendor driver indicates the USB module is always using
4095 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4097 if (priv
->rf_paths
> 1)
4098 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00000000);
4100 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00000280);
4103 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4104 * No trace of this in the 8192eu or 8188eu vendor drivers.
4106 rtl8xxxu_write32(priv
, REG_BT_CONTROL_8723BU
, 0x00000800);
4108 /* One shot, path A LOK & IQK */
4109 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf9000000);
4110 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf8000000);
4114 /* Restore Ant Path */
4115 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, path_sel
);
4118 rtl8xxxu_write32(priv
, REG_BT_CONTROL_8723BU
, 0x00001800);
4124 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4125 val32
&= 0x000000ff;
4126 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4129 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
4130 reg_e94
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_A
);
4131 reg_e9c
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_A
);
4133 val32
= (reg_e9c
>> 16) & 0x3ff;
4135 val32
= 0x400 - val32
;
4137 if (!(reg_eac
& BIT(28)) &&
4138 ((reg_e94
& 0x03ff0000) != 0x01420000) &&
4139 ((reg_e9c
& 0x03ff0000) != 0x00420000) &&
4140 ((reg_e94
& 0x03ff0000) < 0x01100000) &&
4141 ((reg_e94
& 0x03ff0000) > 0x00f00000) &&
4144 else /* If TX not OK, ignore RX */
4151 static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv
*priv
)
4153 u32 reg_ea4
, reg_eac
, reg_e94
, reg_e9c
, path_sel
, val32
;
4156 path_sel
= rtl8xxxu_read32(priv
, REG_S0S1_PATH_SWITCH
);
4161 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4162 val32
&= 0x000000ff;
4163 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4166 * Enable path A PA in TX IQK mode
4168 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
);
4170 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
, val32
);
4171 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_RCK_OS
, 0x30000);
4172 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G1
, 0x0001f);
4173 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G2
, 0xf7fb7);
4178 rtl8xxxu_write32(priv
, REG_TX_IQK
, 0x01007c00);
4179 rtl8xxxu_write32(priv
, REG_RX_IQK
, 0x01004800);
4181 /* path-A IQK setting */
4182 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x18008c1c);
4183 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x38008c1c);
4184 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_B
, 0x38008c1c);
4185 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_B
, 0x38008c1c);
4187 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_A
, 0x82160ff0);
4188 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_A
, 0x28110000);
4189 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_B
, 0x82110000);
4190 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_B
, 0x28110000);
4192 /* LO calibration setting */
4193 rtl8xxxu_write32(priv
, REG_IQK_AGC_RSP
, 0x0046a911);
4198 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4199 val32
&= 0x000000ff;
4200 val32
|= 0x80800000;
4201 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4204 * The vendor driver indicates the USB module is always using
4205 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4207 if (priv
->rf_paths
> 1)
4208 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00000000);
4210 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00000280);
4213 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4214 * No trace of this in the 8192eu or 8188eu vendor drivers.
4216 rtl8xxxu_write32(priv
, REG_BT_CONTROL_8723BU
, 0x00000800);
4218 /* One shot, path A LOK & IQK */
4219 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf9000000);
4220 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf8000000);
4224 /* Restore Ant Path */
4225 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, path_sel
);
4228 rtl8xxxu_write32(priv
, REG_BT_CONTROL_8723BU
, 0x00001800);
4234 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4235 val32
&= 0x000000ff;
4236 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4239 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
4240 reg_e94
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_A
);
4241 reg_e9c
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_A
);
4243 val32
= (reg_e9c
>> 16) & 0x3ff;
4245 val32
= 0x400 - val32
;
4247 if (!(reg_eac
& BIT(28)) &&
4248 ((reg_e94
& 0x03ff0000) != 0x01420000) &&
4249 ((reg_e9c
& 0x03ff0000) != 0x00420000) &&
4250 ((reg_e94
& 0x03ff0000) < 0x01100000) &&
4251 ((reg_e94
& 0x03ff0000) > 0x00f00000) &&
4254 else /* If TX not OK, ignore RX */
4257 val32
= 0x80007c00 | (reg_e94
&0x3ff0000) |
4258 ((reg_e9c
& 0x3ff0000) >> 16);
4259 rtl8xxxu_write32(priv
, REG_TX_IQK
, val32
);
4262 * Modify RX IQK mode
4264 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4265 val32
&= 0x000000ff;
4266 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4267 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
);
4269 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
, val32
);
4270 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_RCK_OS
, 0x30000);
4271 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G1
, 0x0001f);
4272 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G2
, 0xf7d77);
4277 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_DF
, 0xf80);
4278 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_55
, 0x4021f);
4283 rtl8xxxu_write32(priv
, REG_RX_IQK
, 0x01004800);
4285 /* path-A IQK setting */
4286 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x38008c1c);
4287 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x18008c1c);
4288 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_B
, 0x38008c1c);
4289 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_B
, 0x38008c1c);
4291 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_A
, 0x82110000);
4292 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_A
, 0x2816001f);
4293 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_B
, 0x82110000);
4294 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_B
, 0x28110000);
4296 /* LO calibration setting */
4297 rtl8xxxu_write32(priv
, REG_IQK_AGC_RSP
, 0x0046a8d1);
4302 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4303 val32
&= 0x000000ff;
4304 val32
|= 0x80800000;
4305 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4307 if (priv
->rf_paths
> 1)
4308 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00000000);
4310 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00000280);
4315 rtl8xxxu_write32(priv
, REG_BT_CONTROL_8723BU
, 0x00000800);
4317 /* One shot, path A LOK & IQK */
4318 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf9000000);
4319 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf8000000);
4323 /* Restore Ant Path */
4324 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, path_sel
);
4327 rtl8xxxu_write32(priv
, REG_BT_CONTROL_8723BU
, 0x00001800);
4333 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4334 val32
&= 0x000000ff;
4335 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4338 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
4339 reg_ea4
= rtl8xxxu_read32(priv
, REG_RX_POWER_BEFORE_IQK_A_2
);
4341 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_DF
, 0x780);
4343 val32
= (reg_eac
>> 16) & 0x3ff;
4345 val32
= 0x400 - val32
;
4347 if (!(reg_eac
& BIT(27)) &&
4348 ((reg_ea4
& 0x03ff0000) != 0x01320000) &&
4349 ((reg_eac
& 0x03ff0000) != 0x00360000) &&
4350 ((reg_ea4
& 0x03ff0000) < 0x01100000) &&
4351 ((reg_ea4
& 0x03ff0000) > 0x00f00000) &&
4354 else /* If TX not OK, ignore RX */
4360 #ifdef RTL8723BU_PATH_B
4361 static int rtl8723bu_iqk_path_b(struct rtl8xxxu_priv
*priv
)
4363 u32 reg_eac
, reg_eb4
, reg_ebc
, reg_ec4
, reg_ecc
, path_sel
;
4366 path_sel
= rtl8xxxu_read32(priv
, REG_S0S1_PATH_SWITCH
);
4368 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4369 val32
&= 0x000000ff;
4370 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4372 /* One shot, path B LOK & IQK */
4373 rtl8xxxu_write32(priv
, REG_IQK_AGC_CONT
, 0x00000002);
4374 rtl8xxxu_write32(priv
, REG_IQK_AGC_CONT
, 0x00000000);
4379 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
4380 reg_eb4
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_B
);
4381 reg_ebc
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_B
);
4382 reg_ec4
= rtl8xxxu_read32(priv
, REG_RX_POWER_BEFORE_IQK_B_2
);
4383 reg_ecc
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_B_2
);
4385 if (!(reg_eac
& BIT(31)) &&
4386 ((reg_eb4
& 0x03ff0000) != 0x01420000) &&
4387 ((reg_ebc
& 0x03ff0000) != 0x00420000))
4392 if (!(reg_eac
& BIT(30)) &&
4393 (((reg_ec4
& 0x03ff0000) >> 16) != 0x132) &&
4394 (((reg_ecc
& 0x03ff0000) >> 16) != 0x36))
4397 dev_warn(&priv
->udev
->dev
, "%s: Path B RX IQK failed!\n",
4404 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv
*priv
,
4405 int result
[][8], int t
)
4407 struct device
*dev
= &priv
->udev
->dev
;
4409 int path_a_ok
, path_b_ok
;
4411 const u32 adda_regs
[RTL8XXXU_ADDA_REGS
] = {
4412 REG_FPGA0_XCD_SWITCH_CTRL
, REG_BLUETOOTH
,
4413 REG_RX_WAIT_CCA
, REG_TX_CCK_RFON
,
4414 REG_TX_CCK_BBON
, REG_TX_OFDM_RFON
,
4415 REG_TX_OFDM_BBON
, REG_TX_TO_RX
,
4416 REG_TX_TO_TX
, REG_RX_CCK
,
4417 REG_RX_OFDM
, REG_RX_WAIT_RIFS
,
4418 REG_RX_TO_RX
, REG_STANDBY
,
4419 REG_SLEEP
, REG_PMPD_ANAEN
4421 const u32 iqk_mac_regs
[RTL8XXXU_MAC_REGS
] = {
4422 REG_TXPAUSE
, REG_BEACON_CTRL
,
4423 REG_BEACON_CTRL_1
, REG_GPIO_MUXCFG
4425 const u32 iqk_bb_regs
[RTL8XXXU_BB_REGS
] = {
4426 REG_OFDM0_TRX_PATH_ENABLE
, REG_OFDM0_TR_MUX_PAR
,
4427 REG_FPGA0_XCD_RF_SW_CTRL
, REG_CONFIG_ANT_A
, REG_CONFIG_ANT_B
,
4428 REG_FPGA0_XAB_RF_SW_CTRL
, REG_FPGA0_XA_RF_INT_OE
,
4429 REG_FPGA0_XB_RF_INT_OE
, REG_FPGA0_RF_MODE
4433 * Note: IQ calibration must be performed after loading
4434 * PHY_REG.txt , and radio_a, radio_b.txt
4438 /* Save ADDA parameters, turn Path A ADDA on */
4439 rtl8xxxu_save_regs(priv
, adda_regs
, priv
->adda_backup
,
4440 RTL8XXXU_ADDA_REGS
);
4441 rtl8xxxu_save_mac_regs(priv
, iqk_mac_regs
, priv
->mac_backup
);
4442 rtl8xxxu_save_regs(priv
, iqk_bb_regs
,
4443 priv
->bb_backup
, RTL8XXXU_BB_REGS
);
4446 rtl8xxxu_path_adda_on(priv
, adda_regs
, true);
4449 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XA_HSSI_PARM1
);
4450 if (val32
& FPGA0_HSSI_PARM1_PI
)
4451 priv
->pi_enabled
= 1;
4454 if (!priv
->pi_enabled
) {
4455 /* Switch BB to PI mode to do IQ Calibration. */
4456 rtl8xxxu_write32(priv
, REG_FPGA0_XA_HSSI_PARM1
, 0x01000100);
4457 rtl8xxxu_write32(priv
, REG_FPGA0_XB_HSSI_PARM1
, 0x01000100);
4460 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
4461 val32
&= ~FPGA_RF_MODE_CCK
;
4462 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
4464 rtl8xxxu_write32(priv
, REG_OFDM0_TRX_PATH_ENABLE
, 0x03a05600);
4465 rtl8xxxu_write32(priv
, REG_OFDM0_TR_MUX_PAR
, 0x000800e4);
4466 rtl8xxxu_write32(priv
, REG_FPGA0_XCD_RF_SW_CTRL
, 0x22204000);
4468 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XAB_RF_SW_CTRL
);
4469 val32
|= (FPGA0_RF_PAPE
| (FPGA0_RF_PAPE
<< FPGA0_RF_BD_CTRL_SHIFT
));
4470 rtl8xxxu_write32(priv
, REG_FPGA0_XAB_RF_SW_CTRL
, val32
);
4472 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XA_RF_INT_OE
);
4474 rtl8xxxu_write32(priv
, REG_FPGA0_XA_RF_INT_OE
, val32
);
4475 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XB_RF_INT_OE
);
4477 rtl8xxxu_write32(priv
, REG_FPGA0_XB_RF_INT_OE
, val32
);
4479 if (priv
->tx_paths
> 1) {
4480 rtl8xxxu_write32(priv
, REG_FPGA0_XA_LSSI_PARM
, 0x00010000);
4481 rtl8xxxu_write32(priv
, REG_FPGA0_XB_LSSI_PARM
, 0x00010000);
4485 rtl8xxxu_mac_calibration(priv
, iqk_mac_regs
, priv
->mac_backup
);
4488 rtl8xxxu_write32(priv
, REG_CONFIG_ANT_A
, 0x00080000);
4490 if (priv
->tx_paths
> 1)
4491 rtl8xxxu_write32(priv
, REG_CONFIG_ANT_B
, 0x00080000);
4493 /* IQ calibration setting */
4494 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x80800000);
4495 rtl8xxxu_write32(priv
, REG_TX_IQK
, 0x01007c00);
4496 rtl8xxxu_write32(priv
, REG_RX_IQK
, 0x01004800);
4498 for (i
= 0; i
< retry
; i
++) {
4499 path_a_ok
= rtl8xxxu_iqk_path_a(priv
);
4500 if (path_a_ok
== 0x03) {
4501 val32
= rtl8xxxu_read32(priv
,
4502 REG_TX_POWER_BEFORE_IQK_A
);
4503 result
[t
][0] = (val32
>> 16) & 0x3ff;
4504 val32
= rtl8xxxu_read32(priv
,
4505 REG_TX_POWER_AFTER_IQK_A
);
4506 result
[t
][1] = (val32
>> 16) & 0x3ff;
4507 val32
= rtl8xxxu_read32(priv
,
4508 REG_RX_POWER_BEFORE_IQK_A_2
);
4509 result
[t
][2] = (val32
>> 16) & 0x3ff;
4510 val32
= rtl8xxxu_read32(priv
,
4511 REG_RX_POWER_AFTER_IQK_A_2
);
4512 result
[t
][3] = (val32
>> 16) & 0x3ff;
4514 } else if (i
== (retry
- 1) && path_a_ok
== 0x01) {
4516 dev_dbg(dev
, "%s: Path A IQK Only Tx Success!!\n",
4519 val32
= rtl8xxxu_read32(priv
,
4520 REG_TX_POWER_BEFORE_IQK_A
);
4521 result
[t
][0] = (val32
>> 16) & 0x3ff;
4522 val32
= rtl8xxxu_read32(priv
,
4523 REG_TX_POWER_AFTER_IQK_A
);
4524 result
[t
][1] = (val32
>> 16) & 0x3ff;
4529 dev_dbg(dev
, "%s: Path A IQK failed!\n", __func__
);
4531 if (priv
->tx_paths
> 1) {
4533 * Path A into standby
4535 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x0);
4536 rtl8xxxu_write32(priv
, REG_FPGA0_XA_LSSI_PARM
, 0x00010000);
4537 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x80800000);
4539 /* Turn Path B ADDA on */
4540 rtl8xxxu_path_adda_on(priv
, adda_regs
, false);
4542 for (i
= 0; i
< retry
; i
++) {
4543 path_b_ok
= rtl8xxxu_iqk_path_b(priv
);
4544 if (path_b_ok
== 0x03) {
4545 val32
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_B
);
4546 result
[t
][4] = (val32
>> 16) & 0x3ff;
4547 val32
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_B
);
4548 result
[t
][5] = (val32
>> 16) & 0x3ff;
4549 val32
= rtl8xxxu_read32(priv
, REG_RX_POWER_BEFORE_IQK_B_2
);
4550 result
[t
][6] = (val32
>> 16) & 0x3ff;
4551 val32
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_B_2
);
4552 result
[t
][7] = (val32
>> 16) & 0x3ff;
4554 } else if (i
== (retry
- 1) && path_b_ok
== 0x01) {
4556 val32
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_B
);
4557 result
[t
][4] = (val32
>> 16) & 0x3ff;
4558 val32
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_B
);
4559 result
[t
][5] = (val32
>> 16) & 0x3ff;
4564 dev_dbg(dev
, "%s: Path B IQK failed!\n", __func__
);
4567 /* Back to BB mode, load original value */
4568 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0);
4571 if (!priv
->pi_enabled
) {
4573 * Switch back BB to SI mode after finishing
4577 rtl8xxxu_write32(priv
, REG_FPGA0_XA_HSSI_PARM1
, val32
);
4578 rtl8xxxu_write32(priv
, REG_FPGA0_XB_HSSI_PARM1
, val32
);
4581 /* Reload ADDA power saving parameters */
4582 rtl8xxxu_restore_regs(priv
, adda_regs
, priv
->adda_backup
,
4583 RTL8XXXU_ADDA_REGS
);
4585 /* Reload MAC parameters */
4586 rtl8xxxu_restore_mac_regs(priv
, iqk_mac_regs
, priv
->mac_backup
);
4588 /* Reload BB parameters */
4589 rtl8xxxu_restore_regs(priv
, iqk_bb_regs
,
4590 priv
->bb_backup
, RTL8XXXU_BB_REGS
);
4592 /* Restore RX initial gain */
4593 rtl8xxxu_write32(priv
, REG_FPGA0_XA_LSSI_PARM
, 0x00032ed3);
4595 if (priv
->tx_paths
> 1) {
4596 rtl8xxxu_write32(priv
, REG_FPGA0_XB_LSSI_PARM
,
4600 /* Load 0xe30 IQC default value */
4601 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x01008c00);
4602 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x01008c00);
4606 static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv
*priv
,
4607 int result
[][8], int t
)
4609 struct device
*dev
= &priv
->udev
->dev
;
4611 int path_a_ok
/*, path_b_ok */;
4613 const u32 adda_regs
[RTL8XXXU_ADDA_REGS
] = {
4614 REG_FPGA0_XCD_SWITCH_CTRL
, REG_BLUETOOTH
,
4615 REG_RX_WAIT_CCA
, REG_TX_CCK_RFON
,
4616 REG_TX_CCK_BBON
, REG_TX_OFDM_RFON
,
4617 REG_TX_OFDM_BBON
, REG_TX_TO_RX
,
4618 REG_TX_TO_TX
, REG_RX_CCK
,
4619 REG_RX_OFDM
, REG_RX_WAIT_RIFS
,
4620 REG_RX_TO_RX
, REG_STANDBY
,
4621 REG_SLEEP
, REG_PMPD_ANAEN
4623 const u32 iqk_mac_regs
[RTL8XXXU_MAC_REGS
] = {
4624 REG_TXPAUSE
, REG_BEACON_CTRL
,
4625 REG_BEACON_CTRL_1
, REG_GPIO_MUXCFG
4627 const u32 iqk_bb_regs
[RTL8XXXU_BB_REGS
] = {
4628 REG_OFDM0_TRX_PATH_ENABLE
, REG_OFDM0_TR_MUX_PAR
,
4629 REG_FPGA0_XCD_RF_SW_CTRL
, REG_CONFIG_ANT_A
, REG_CONFIG_ANT_B
,
4630 REG_FPGA0_XAB_RF_SW_CTRL
, REG_FPGA0_XA_RF_INT_OE
,
4631 REG_FPGA0_XB_RF_INT_OE
, REG_FPGA0_RF_MODE
4633 u8 xa_agc
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_AGC_CORE1
) & 0xff;
4634 u8 xb_agc
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_AGC_CORE1
) & 0xff;
4637 * Note: IQ calibration must be performed after loading
4638 * PHY_REG.txt , and radio_a, radio_b.txt
4642 /* Save ADDA parameters, turn Path A ADDA on */
4643 rtl8xxxu_save_regs(priv
, adda_regs
, priv
->adda_backup
,
4644 RTL8XXXU_ADDA_REGS
);
4645 rtl8xxxu_save_mac_regs(priv
, iqk_mac_regs
, priv
->mac_backup
);
4646 rtl8xxxu_save_regs(priv
, iqk_bb_regs
,
4647 priv
->bb_backup
, RTL8XXXU_BB_REGS
);
4650 rtl8xxxu_path_adda_on(priv
, adda_regs
, true);
4653 rtl8xxxu_mac_calibration(priv
, iqk_mac_regs
, priv
->mac_backup
);
4655 val32
= rtl8xxxu_read32(priv
, REG_CCK0_AFE_SETTING
);
4656 val32
|= 0x0f000000;
4657 rtl8xxxu_write32(priv
, REG_CCK0_AFE_SETTING
, val32
);
4659 rtl8xxxu_write32(priv
, REG_OFDM0_TRX_PATH_ENABLE
, 0x03a05600);
4660 rtl8xxxu_write32(priv
, REG_OFDM0_TR_MUX_PAR
, 0x000800e4);
4661 rtl8xxxu_write32(priv
, REG_FPGA0_XCD_RF_SW_CTRL
, 0x22204000);
4663 #ifdef RTL8723BU_PATH_B
4664 /* Set RF mode to standby Path B */
4665 if (priv
->tx_paths
> 1)
4666 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_AC
, 0x10000);
4671 rtl8xxxu_write32(priv
, REG_CONFIG_ANT_A
, 0x0f600000);
4673 if (priv
->tx_paths
> 1)
4674 rtl8xxxu_write32(priv
, REG_CONFIG_ANT_B
, 0x0f600000);
4678 * RX IQ calibration setting for 8723B D cut large current issue
4681 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4682 val32
&= 0x000000ff;
4683 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4685 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
);
4687 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
, val32
);
4689 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_RCK_OS
, 0x30000);
4690 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G1
, 0x0001f);
4691 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G2
, 0xf7fb7);
4693 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_ED
);
4695 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_ED
, val32
);
4697 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_43
, 0x60fbd);
4699 for (i
= 0; i
< retry
; i
++) {
4700 path_a_ok
= rtl8723bu_iqk_path_a(priv
);
4701 if (path_a_ok
== 0x01) {
4702 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4703 val32
&= 0x000000ff;
4704 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4706 #if 0 /* Only needed in restore case, we may need this when going to suspend */
4707 priv
->RFCalibrateInfo
.TxLOK
[RF_A
] =
4708 rtl8xxxu_read_rfreg(priv
, RF_A
,
4709 RF6052_REG_TXM_IDAC
);
4712 val32
= rtl8xxxu_read32(priv
,
4713 REG_TX_POWER_BEFORE_IQK_A
);
4714 result
[t
][0] = (val32
>> 16) & 0x3ff;
4715 val32
= rtl8xxxu_read32(priv
,
4716 REG_TX_POWER_AFTER_IQK_A
);
4717 result
[t
][1] = (val32
>> 16) & 0x3ff;
4724 dev_dbg(dev
, "%s: Path A TX IQK failed!\n", __func__
);
4726 for (i
= 0; i
< retry
; i
++) {
4727 path_a_ok
= rtl8723bu_rx_iqk_path_a(priv
);
4728 if (path_a_ok
== 0x03) {
4729 val32
= rtl8xxxu_read32(priv
,
4730 REG_RX_POWER_BEFORE_IQK_A_2
);
4731 result
[t
][2] = (val32
>> 16) & 0x3ff;
4732 val32
= rtl8xxxu_read32(priv
,
4733 REG_RX_POWER_AFTER_IQK_A_2
);
4734 result
[t
][3] = (val32
>> 16) & 0x3ff;
4741 dev_dbg(dev
, "%s: Path A RX IQK failed!\n", __func__
);
4743 if (priv
->tx_paths
> 1) {
4745 dev_warn(dev
, "%s: Path B not supported\n", __func__
);
4749 * Path A into standby
4751 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4752 val32
&= 0x000000ff;
4753 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4754 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_AC
, 0x10000);
4756 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4757 val32
&= 0x000000ff;
4758 val32
|= 0x80800000;
4759 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4761 /* Turn Path B ADDA on */
4762 rtl8xxxu_path_adda_on(priv
, adda_regs
, false);
4764 for (i
= 0; i
< retry
; i
++) {
4765 path_b_ok
= rtl8xxxu_iqk_path_b(priv
);
4766 if (path_b_ok
== 0x03) {
4767 val32
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_B
);
4768 result
[t
][4] = (val32
>> 16) & 0x3ff;
4769 val32
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_B
);
4770 result
[t
][5] = (val32
>> 16) & 0x3ff;
4776 dev_dbg(dev
, "%s: Path B IQK failed!\n", __func__
);
4778 for (i
= 0; i
< retry
; i
++) {
4779 path_b_ok
= rtl8723bu_rx_iqk_path_b(priv
);
4780 if (path_a_ok
== 0x03) {
4781 val32
= rtl8xxxu_read32(priv
,
4782 REG_RX_POWER_BEFORE_IQK_B_2
);
4783 result
[t
][6] = (val32
>> 16) & 0x3ff;
4784 val32
= rtl8xxxu_read32(priv
,
4785 REG_RX_POWER_AFTER_IQK_B_2
);
4786 result
[t
][7] = (val32
>> 16) & 0x3ff;
4792 dev_dbg(dev
, "%s: Path B RX IQK failed!\n", __func__
);
4796 /* Back to BB mode, load original value */
4797 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4798 val32
&= 0x000000ff;
4799 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4802 /* Reload ADDA power saving parameters */
4803 rtl8xxxu_restore_regs(priv
, adda_regs
, priv
->adda_backup
,
4804 RTL8XXXU_ADDA_REGS
);
4806 /* Reload MAC parameters */
4807 rtl8xxxu_restore_mac_regs(priv
, iqk_mac_regs
, priv
->mac_backup
);
4809 /* Reload BB parameters */
4810 rtl8xxxu_restore_regs(priv
, iqk_bb_regs
,
4811 priv
->bb_backup
, RTL8XXXU_BB_REGS
);
4813 /* Restore RX initial gain */
4814 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_AGC_CORE1
);
4815 val32
&= 0xffffff00;
4816 rtl8xxxu_write32(priv
, REG_OFDM0_XA_AGC_CORE1
, val32
| 0x50);
4817 rtl8xxxu_write32(priv
, REG_OFDM0_XA_AGC_CORE1
, val32
| xa_agc
);
4819 if (priv
->tx_paths
> 1) {
4820 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_AGC_CORE1
);
4821 val32
&= 0xffffff00;
4822 rtl8xxxu_write32(priv
, REG_OFDM0_XB_AGC_CORE1
,
4824 rtl8xxxu_write32(priv
, REG_OFDM0_XB_AGC_CORE1
,
4828 /* Load 0xe30 IQC default value */
4829 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x01008c00);
4830 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x01008c00);
4834 static void rtl8xxxu_prepare_calibrate(struct rtl8xxxu_priv
*priv
, u8 start
)
4838 if (priv
->fops
->mbox_ext_width
< 4)
4841 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
4842 h2c
.bt_wlan_calibration
.cmd
= H2C_8723B_BT_WLAN_CALIBRATION
;
4843 h2c
.bt_wlan_calibration
.data
= start
;
4845 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.bt_wlan_calibration
));
4848 static void rtl8723au_phy_iq_calibrate(struct rtl8xxxu_priv
*priv
)
4850 struct device
*dev
= &priv
->udev
->dev
;
4851 int result
[4][8]; /* last is final result */
4853 bool path_a_ok
, path_b_ok
;
4854 u32 reg_e94
, reg_e9c
, reg_ea4
, reg_eac
;
4855 u32 reg_eb4
, reg_ebc
, reg_ec4
, reg_ecc
;
4859 rtl8xxxu_prepare_calibrate(priv
, 1);
4861 memset(result
, 0, sizeof(result
));
4867 rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
4869 for (i
= 0; i
< 3; i
++) {
4870 rtl8xxxu_phy_iqcalibrate(priv
, result
, i
);
4873 simu
= rtl8xxxu_simularity_compare(priv
, result
, 0, 1);
4881 simu
= rtl8xxxu_simularity_compare(priv
, result
, 0, 2);
4887 simu
= rtl8xxxu_simularity_compare(priv
, result
, 1, 2);
4891 for (i
= 0; i
< 8; i
++)
4892 reg_tmp
+= result
[3][i
];
4902 for (i
= 0; i
< 4; i
++) {
4903 reg_e94
= result
[i
][0];
4904 reg_e9c
= result
[i
][1];
4905 reg_ea4
= result
[i
][2];
4906 reg_eac
= result
[i
][3];
4907 reg_eb4
= result
[i
][4];
4908 reg_ebc
= result
[i
][5];
4909 reg_ec4
= result
[i
][6];
4910 reg_ecc
= result
[i
][7];
4913 if (candidate
>= 0) {
4914 reg_e94
= result
[candidate
][0];
4915 priv
->rege94
= reg_e94
;
4916 reg_e9c
= result
[candidate
][1];
4917 priv
->rege9c
= reg_e9c
;
4918 reg_ea4
= result
[candidate
][2];
4919 reg_eac
= result
[candidate
][3];
4920 reg_eb4
= result
[candidate
][4];
4921 priv
->regeb4
= reg_eb4
;
4922 reg_ebc
= result
[candidate
][5];
4923 priv
->regebc
= reg_ebc
;
4924 reg_ec4
= result
[candidate
][6];
4925 reg_ecc
= result
[candidate
][7];
4926 dev_dbg(dev
, "%s: candidate is %x\n", __func__
, candidate
);
4928 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
4929 "ecc=%x\n ", __func__
, reg_e94
, reg_e9c
,
4930 reg_ea4
, reg_eac
, reg_eb4
, reg_ebc
, reg_ec4
, reg_ecc
);
4934 reg_e94
= reg_eb4
= priv
->rege94
= priv
->regeb4
= 0x100;
4935 reg_e9c
= reg_ebc
= priv
->rege9c
= priv
->regebc
= 0x0;
4938 if (reg_e94
&& candidate
>= 0)
4939 rtl8xxxu_fill_iqk_matrix_a(priv
, path_a_ok
, result
,
4940 candidate
, (reg_ea4
== 0));
4942 if (priv
->tx_paths
> 1 && reg_eb4
)
4943 rtl8xxxu_fill_iqk_matrix_b(priv
, path_b_ok
, result
,
4944 candidate
, (reg_ec4
== 0));
4946 rtl8xxxu_save_regs(priv
, rtl8723au_iqk_phy_iq_bb_reg
,
4947 priv
->bb_recovery_backup
, RTL8XXXU_BB_REGS
);
4949 rtl8xxxu_prepare_calibrate(priv
, 0);
4952 static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv
*priv
)
4954 struct device
*dev
= &priv
->udev
->dev
;
4955 int result
[4][8]; /* last is final result */
4957 bool path_a_ok
, path_b_ok
;
4958 u32 reg_e94
, reg_e9c
, reg_ea4
, reg_eac
;
4959 u32 reg_eb4
, reg_ebc
, reg_ec4
, reg_ecc
;
4960 u32 val32
, bt_control
;
4964 rtl8xxxu_prepare_calibrate(priv
, 1);
4966 memset(result
, 0, sizeof(result
));
4972 bt_control
= rtl8xxxu_read32(priv
, REG_BT_CONTROL_8723BU
);
4974 for (i
= 0; i
< 3; i
++) {
4975 rtl8723bu_phy_iqcalibrate(priv
, result
, i
);
4978 simu
= rtl8723bu_simularity_compare(priv
, result
, 0, 1);
4986 simu
= rtl8723bu_simularity_compare(priv
, result
, 0, 2);
4992 simu
= rtl8723bu_simularity_compare(priv
, result
, 1, 2);
4996 for (i
= 0; i
< 8; i
++)
4997 reg_tmp
+= result
[3][i
];
5007 for (i
= 0; i
< 4; i
++) {
5008 reg_e94
= result
[i
][0];
5009 reg_e9c
= result
[i
][1];
5010 reg_ea4
= result
[i
][2];
5011 reg_eac
= result
[i
][3];
5012 reg_eb4
= result
[i
][4];
5013 reg_ebc
= result
[i
][5];
5014 reg_ec4
= result
[i
][6];
5015 reg_ecc
= result
[i
][7];
5018 if (candidate
>= 0) {
5019 reg_e94
= result
[candidate
][0];
5020 priv
->rege94
= reg_e94
;
5021 reg_e9c
= result
[candidate
][1];
5022 priv
->rege9c
= reg_e9c
;
5023 reg_ea4
= result
[candidate
][2];
5024 reg_eac
= result
[candidate
][3];
5025 reg_eb4
= result
[candidate
][4];
5026 priv
->regeb4
= reg_eb4
;
5027 reg_ebc
= result
[candidate
][5];
5028 priv
->regebc
= reg_ebc
;
5029 reg_ec4
= result
[candidate
][6];
5030 reg_ecc
= result
[candidate
][7];
5031 dev_dbg(dev
, "%s: candidate is %x\n", __func__
, candidate
);
5033 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
5034 "ecc=%x\n ", __func__
, reg_e94
, reg_e9c
,
5035 reg_ea4
, reg_eac
, reg_eb4
, reg_ebc
, reg_ec4
, reg_ecc
);
5039 reg_e94
= reg_eb4
= priv
->rege94
= priv
->regeb4
= 0x100;
5040 reg_e9c
= reg_ebc
= priv
->rege9c
= priv
->regebc
= 0x0;
5043 if (reg_e94
&& candidate
>= 0)
5044 rtl8xxxu_fill_iqk_matrix_a(priv
, path_a_ok
, result
,
5045 candidate
, (reg_ea4
== 0));
5047 if (priv
->tx_paths
> 1 && reg_eb4
)
5048 rtl8xxxu_fill_iqk_matrix_b(priv
, path_b_ok
, result
,
5049 candidate
, (reg_ec4
== 0));
5051 rtl8xxxu_save_regs(priv
, rtl8723au_iqk_phy_iq_bb_reg
,
5052 priv
->bb_recovery_backup
, RTL8XXXU_BB_REGS
);
5054 rtl8xxxu_write32(priv
, REG_BT_CONTROL_8723BU
, bt_control
);
5056 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
);
5058 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
, val32
);
5059 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_RCK_OS
, 0x18000);
5060 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G1
, 0x0001f);
5061 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G2
, 0xe6177);
5062 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_ED
);
5064 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_ED
, val32
);
5065 rtl8xxxu_write_rfreg(priv
, RF_A
, 0x43, 0x300bd);
5067 if (priv
->rf_paths
> 1) {
5068 dev_dbg(dev
, "%s: beware 2T not yet supported\n", __func__
);
5069 #ifdef RTL8723BU_PATH_B
5070 if (RF_Path
== 0x0) //S1
5071 ODM_SetIQCbyRFpath(pDM_Odm
, 0);
5073 ODM_SetIQCbyRFpath(pDM_Odm
, 1);
5076 rtl8xxxu_prepare_calibrate(priv
, 0);
5079 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv
*priv
)
5082 u32 rf_amode
, rf_bmode
= 0, lstf
;
5084 /* Check continuous TX and Packet TX */
5085 lstf
= rtl8xxxu_read32(priv
, REG_OFDM1_LSTF
);
5087 if (lstf
& OFDM_LSTF_MASK
) {
5088 /* Disable all continuous TX */
5089 val32
= lstf
& ~OFDM_LSTF_MASK
;
5090 rtl8xxxu_write32(priv
, REG_OFDM1_LSTF
, val32
);
5092 /* Read original RF mode Path A */
5093 rf_amode
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_AC
);
5095 /* Set RF mode to standby Path A */
5096 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_AC
,
5097 (rf_amode
& 0x8ffff) | 0x10000);
5100 if (priv
->tx_paths
> 1) {
5101 rf_bmode
= rtl8xxxu_read_rfreg(priv
, RF_B
,
5104 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_AC
,
5105 (rf_bmode
& 0x8ffff) | 0x10000);
5108 /* Deal with Packet TX case */
5109 /* block all queues */
5110 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0xff);
5113 /* Start LC calibration */
5114 if (priv
->fops
->has_s0s1
)
5115 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_S0S1
, 0xdfbe0);
5116 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_MODE_AG
);
5118 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_MODE_AG
, val32
);
5122 if (priv
->fops
->has_s0s1
)
5123 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_S0S1
, 0xdffe0);
5125 /* Restore original parameters */
5126 if (lstf
& OFDM_LSTF_MASK
) {
5128 rtl8xxxu_write32(priv
, REG_OFDM1_LSTF
, lstf
);
5129 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_AC
, rf_amode
);
5132 if (priv
->tx_paths
> 1)
5133 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_AC
,
5135 } else /* Deal with Packet TX case */
5136 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0x00);
5139 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv
*priv
)
5146 for (i
= 0; i
< ETH_ALEN
; i
++)
5147 rtl8xxxu_write8(priv
, reg
+ i
, priv
->mac_addr
[i
]);
5152 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv
*priv
, const u8
*bssid
)
5157 dev_dbg(&priv
->udev
->dev
, "%s: (%pM)\n", __func__
, bssid
);
5161 for (i
= 0; i
< ETH_ALEN
; i
++)
5162 rtl8xxxu_write8(priv
, reg
+ i
, bssid
[i
]);
5168 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv
*priv
, u8 ampdu_factor
)
5170 u8 vals
[4] = { 0x41, 0xa8, 0x72, 0xb9 };
5174 ampdu_factor
= 1 << (ampdu_factor
+ 2);
5175 if (ampdu_factor
> max_agg
)
5176 ampdu_factor
= max_agg
;
5178 for (i
= 0; i
< 4; i
++) {
5179 if ((vals
[i
] & 0xf0) > (ampdu_factor
<< 4))
5180 vals
[i
] = (vals
[i
] & 0x0f) | (ampdu_factor
<< 4);
5182 if ((vals
[i
] & 0x0f) > ampdu_factor
)
5183 vals
[i
] = (vals
[i
] & 0xf0) | ampdu_factor
;
5185 rtl8xxxu_write8(priv
, REG_AGGLEN_LMT
+ i
, vals
[i
]);
5189 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv
*priv
, u8 density
)
5193 val8
= rtl8xxxu_read8(priv
, REG_AMPDU_MIN_SPACE
);
5196 rtl8xxxu_write8(priv
, REG_AMPDU_MIN_SPACE
, val8
);
5199 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv
*priv
)
5204 /* Start of rtl8723AU_card_enable_flow */
5205 /* Act to Cardemu sequence*/
5207 rtl8xxxu_write8(priv
, REG_RF_CTRL
, 0);
5209 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
5210 val8
= rtl8xxxu_read8(priv
, REG_LEDCFG2
);
5211 val8
&= ~LEDCFG2_DPDT_SELECT
;
5212 rtl8xxxu_write8(priv
, REG_LEDCFG2
, val8
);
5214 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
5215 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5217 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5219 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
5220 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5221 if ((val8
& BIT(1)) == 0)
5227 dev_warn(&priv
->udev
->dev
, "%s: Disabling MAC timed out\n",
5233 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
5234 val8
= rtl8xxxu_read8(priv
, REG_SYS_ISO_CTRL
);
5235 val8
|= SYS_ISO_ANALOG_IPS
;
5236 rtl8xxxu_write8(priv
, REG_SYS_ISO_CTRL
, val8
);
5238 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
5239 val8
= rtl8xxxu_read8(priv
, REG_LDOA15_CTRL
);
5240 val8
&= ~LDOA15_ENABLE
;
5241 rtl8xxxu_write8(priv
, REG_LDOA15_CTRL
, val8
);
5247 static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv
*priv
)
5253 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0xff);
5256 * Poll - wait for RX packet to complete
5258 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
5259 val32
= rtl8xxxu_read32(priv
, 0x5f8);
5266 dev_warn(&priv
->udev
->dev
,
5267 "%s: RX poll timed out (0x05f8)\n", __func__
);
5272 /* Disable CCK and OFDM, clock gated */
5273 val8
= rtl8xxxu_read8(priv
, REG_SYS_FUNC
);
5274 val8
&= ~SYS_FUNC_BBRSTB
;
5275 rtl8xxxu_write8(priv
, REG_SYS_FUNC
, val8
);
5279 /* Reset baseband */
5280 val8
= rtl8xxxu_read8(priv
, REG_SYS_FUNC
);
5281 val8
&= ~SYS_FUNC_BB_GLB_RSTN
;
5282 rtl8xxxu_write8(priv
, REG_SYS_FUNC
, val8
);
5285 val8
= rtl8xxxu_read8(priv
, REG_CR
);
5286 val8
= CR_HCI_TXDMA_ENABLE
| CR_HCI_RXDMA_ENABLE
;
5287 rtl8xxxu_write8(priv
, REG_CR
, val8
);
5290 val8
= rtl8xxxu_read8(priv
, REG_CR
+ 1);
5291 val8
&= ~BIT(1); /* CR_SECURITY_ENABLE */
5292 rtl8xxxu_write8(priv
, REG_CR
+ 1, val8
);
5294 /* Respond TX OK to scheduler */
5295 val8
= rtl8xxxu_read8(priv
, REG_DUAL_TSF_RST
);
5296 val8
|= DUAL_TSF_TX_OK
;
5297 rtl8xxxu_write8(priv
, REG_DUAL_TSF_RST
, val8
);
5303 static void rtl8723a_disabled_to_emu(struct rtl8xxxu_priv
*priv
)
5307 /* Clear suspend enable and power down enable*/
5308 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5309 val8
&= ~(BIT(3) | BIT(7));
5310 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5312 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
5313 val8
= rtl8xxxu_read8(priv
, REG_GPIO_INTM
+ 2);
5315 rtl8xxxu_write8(priv
, REG_GPIO_INTM
+ 2, val8
);
5317 /* 0x04[12:11] = 11 enable WL suspend*/
5318 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5319 val8
&= ~(BIT(3) | BIT(4));
5320 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5323 static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv
*priv
)
5327 /* Clear suspend enable and power down enable*/
5328 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5329 val8
&= ~(BIT(3) | BIT(4));
5330 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5333 static int rtl8192e_emu_to_active(struct rtl8xxxu_priv
*priv
)
5339 /* disable HWPDN 0x04[15]=0*/
5340 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5342 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5344 /* disable SW LPS 0x04[10]= 0 */
5345 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5347 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5349 /* disable WL suspend*/
5350 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5351 val8
&= ~(BIT(3) | BIT(4));
5352 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5354 /* wait till 0x04[17] = 1 power ready*/
5355 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
5356 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5357 if (val32
& BIT(17))
5368 /* We should be able to optimize the following three entries into one */
5370 /* release WLON reset 0x04[16]= 1*/
5371 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 2);
5373 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 2, val8
);
5375 /* set, then poll until 0 */
5376 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5377 val32
|= APS_FSMCO_MAC_ENABLE
;
5378 rtl8xxxu_write32(priv
, REG_APS_FSMCO
, val32
);
5380 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
5381 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5382 if ((val32
& APS_FSMCO_MAC_ENABLE
) == 0) {
5398 static int rtl8723a_emu_to_active(struct rtl8xxxu_priv
*priv
)
5404 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
5405 val8
= rtl8xxxu_read8(priv
, REG_LDOA15_CTRL
);
5406 val8
|= LDOA15_ENABLE
;
5407 rtl8xxxu_write8(priv
, REG_LDOA15_CTRL
, val8
);
5409 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
5410 val8
= rtl8xxxu_read8(priv
, 0x0067);
5412 rtl8xxxu_write8(priv
, 0x0067, val8
);
5416 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
5417 val8
= rtl8xxxu_read8(priv
, REG_SYS_ISO_CTRL
);
5418 val8
&= ~SYS_ISO_ANALOG_IPS
;
5419 rtl8xxxu_write8(priv
, REG_SYS_ISO_CTRL
, val8
);
5421 /* disable SW LPS 0x04[10]= 0 */
5422 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5424 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5426 /* wait till 0x04[17] = 1 power ready*/
5427 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
5428 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5429 if (val32
& BIT(17))
5440 /* We should be able to optimize the following three entries into one */
5442 /* release WLON reset 0x04[16]= 1*/
5443 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 2);
5445 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 2, val8
);
5447 /* disable HWPDN 0x04[15]= 0*/
5448 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5450 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5452 /* disable WL suspend*/
5453 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5454 val8
&= ~(BIT(3) | BIT(4));
5455 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5457 /* set, then poll until 0 */
5458 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5459 val32
|= APS_FSMCO_MAC_ENABLE
;
5460 rtl8xxxu_write32(priv
, REG_APS_FSMCO
, val32
);
5462 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
5463 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5464 if ((val32
& APS_FSMCO_MAC_ENABLE
) == 0) {
5476 /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
5478 * Note: Vendor driver actually clears this bit, despite the
5479 * documentation claims it's being set!
5481 val8
= rtl8xxxu_read8(priv
, REG_LEDCFG2
);
5482 val8
|= LEDCFG2_DPDT_SELECT
;
5483 val8
&= ~LEDCFG2_DPDT_SELECT
;
5484 rtl8xxxu_write8(priv
, REG_LEDCFG2
, val8
);
5490 static int rtl8723b_emu_to_active(struct rtl8xxxu_priv
*priv
)
5496 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface */
5497 val8
= rtl8xxxu_read8(priv
, REG_LDOA15_CTRL
);
5498 val8
|= LDOA15_ENABLE
;
5499 rtl8xxxu_write8(priv
, REG_LDOA15_CTRL
, val8
);
5501 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
5502 val8
= rtl8xxxu_read8(priv
, 0x0067);
5504 rtl8xxxu_write8(priv
, 0x0067, val8
);
5508 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
5509 val8
= rtl8xxxu_read8(priv
, REG_SYS_ISO_CTRL
);
5510 val8
&= ~SYS_ISO_ANALOG_IPS
;
5511 rtl8xxxu_write8(priv
, REG_SYS_ISO_CTRL
, val8
);
5513 /* Disable SW LPS 0x04[10]= 0 */
5514 val32
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
);
5515 val32
&= ~APS_FSMCO_SW_LPS
;
5516 rtl8xxxu_write32(priv
, REG_APS_FSMCO
, val32
);
5518 /* Wait until 0x04[17] = 1 power ready */
5519 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
5520 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5521 if (val32
& BIT(17))
5532 /* We should be able to optimize the following three entries into one */
5534 /* Release WLON reset 0x04[16]= 1*/
5535 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5536 val32
|= APS_FSMCO_WLON_RESET
;
5537 rtl8xxxu_write32(priv
, REG_APS_FSMCO
, val32
);
5539 /* Disable HWPDN 0x04[15]= 0*/
5540 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5541 val32
&= ~APS_FSMCO_HW_POWERDOWN
;
5542 rtl8xxxu_write32(priv
, REG_APS_FSMCO
, val32
);
5544 /* Disable WL suspend*/
5545 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5546 val32
&= ~(APS_FSMCO_HW_SUSPEND
| APS_FSMCO_PCIE
);
5547 rtl8xxxu_write32(priv
, REG_APS_FSMCO
, val32
);
5549 /* Set, then poll until 0 */
5550 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5551 val32
|= APS_FSMCO_MAC_ENABLE
;
5552 rtl8xxxu_write32(priv
, REG_APS_FSMCO
, val32
);
5554 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
5555 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5556 if ((val32
& APS_FSMCO_MAC_ENABLE
) == 0) {
5568 /* Enable WL control XTAL setting */
5569 val8
= rtl8xxxu_read8(priv
, REG_AFE_MISC
);
5570 val8
|= AFE_MISC_WL_XTAL_CTRL
;
5571 rtl8xxxu_write8(priv
, REG_AFE_MISC
, val8
);
5573 /* Enable falling edge triggering interrupt */
5574 val8
= rtl8xxxu_read8(priv
, REG_GPIO_INTM
+ 1);
5576 rtl8xxxu_write8(priv
, REG_GPIO_INTM
+ 1, val8
);
5578 /* Enable GPIO9 interrupt mode */
5579 val8
= rtl8xxxu_read8(priv
, REG_GPIO_IO_SEL_2
+ 1);
5581 rtl8xxxu_write8(priv
, REG_GPIO_IO_SEL_2
+ 1, val8
);
5583 /* Enable GPIO9 input mode */
5584 val8
= rtl8xxxu_read8(priv
, REG_GPIO_IO_SEL_2
);
5586 rtl8xxxu_write8(priv
, REG_GPIO_IO_SEL_2
, val8
);
5588 /* Enable HSISR GPIO[C:0] interrupt */
5589 val8
= rtl8xxxu_read8(priv
, REG_HSIMR
);
5591 rtl8xxxu_write8(priv
, REG_HSIMR
, val8
);
5593 /* Enable HSISR GPIO9 interrupt */
5594 val8
= rtl8xxxu_read8(priv
, REG_HSIMR
+ 2);
5596 rtl8xxxu_write8(priv
, REG_HSIMR
+ 2, val8
);
5598 val8
= rtl8xxxu_read8(priv
, REG_MULTI_FUNC_CTRL
);
5599 val8
|= MULTI_WIFI_HW_ROF_EN
;
5600 rtl8xxxu_write8(priv
, REG_MULTI_FUNC_CTRL
, val8
);
5602 /* For GPIO9 internal pull high setting BIT(14) */
5603 val8
= rtl8xxxu_read8(priv
, REG_MULTI_FUNC_CTRL
+ 1);
5605 rtl8xxxu_write8(priv
, REG_MULTI_FUNC_CTRL
+ 1, val8
);
5611 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv
*priv
)
5615 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
5616 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 3, 0x20);
5618 /* 0x04[12:11] = 01 enable WL suspend */
5619 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5622 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5624 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5626 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5628 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
5629 val8
= rtl8xxxu_read8(priv
, REG_GPIO_INTM
+ 2);
5631 rtl8xxxu_write8(priv
, REG_GPIO_INTM
+ 2, val8
);
5636 static int rtl8723au_power_on(struct rtl8xxxu_priv
*priv
)
5644 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5646 rtl8xxxu_write8(priv
, REG_RSV_CTRL
, 0x0);
5648 rtl8723a_disabled_to_emu(priv
);
5650 ret
= rtl8723a_emu_to_active(priv
);
5655 * 0x0004[19] = 1, reset 8051
5657 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 2);
5659 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 2, val8
);
5662 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5663 * Set CR bit10 to enable 32k calibration.
5665 val16
= rtl8xxxu_read16(priv
, REG_CR
);
5666 val16
|= (CR_HCI_TXDMA_ENABLE
| CR_HCI_RXDMA_ENABLE
|
5667 CR_TXDMA_ENABLE
| CR_RXDMA_ENABLE
|
5668 CR_PROTOCOL_ENABLE
| CR_SCHEDULE_ENABLE
|
5669 CR_MAC_TX_ENABLE
| CR_MAC_RX_ENABLE
|
5670 CR_SECURITY_ENABLE
| CR_CALTIMER_ENABLE
);
5671 rtl8xxxu_write16(priv
, REG_CR
, val16
);
5674 val32
= rtl8xxxu_read32(priv
, REG_EFUSE_CTRL
);
5675 val32
&= ~(BIT(28) | BIT(29) | BIT(30));
5676 val32
|= (0x06 << 28);
5677 rtl8xxxu_write32(priv
, REG_EFUSE_CTRL
, val32
);
5682 static int rtl8723bu_power_on(struct rtl8xxxu_priv
*priv
)
5689 rtl8723a_disabled_to_emu(priv
);
5691 ret
= rtl8723b_emu_to_active(priv
);
5696 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5697 * Set CR bit10 to enable 32k calibration.
5699 val16
= rtl8xxxu_read16(priv
, REG_CR
);
5700 val16
|= (CR_HCI_TXDMA_ENABLE
| CR_HCI_RXDMA_ENABLE
|
5701 CR_TXDMA_ENABLE
| CR_RXDMA_ENABLE
|
5702 CR_PROTOCOL_ENABLE
| CR_SCHEDULE_ENABLE
|
5703 CR_MAC_TX_ENABLE
| CR_MAC_RX_ENABLE
|
5704 CR_SECURITY_ENABLE
| CR_CALTIMER_ENABLE
);
5705 rtl8xxxu_write16(priv
, REG_CR
, val16
);
5708 * BT coexist power on settings. This is identical for 1 and 2
5711 rtl8xxxu_write8(priv
, REG_PAD_CTRL1
+ 3, 0x20);
5713 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
5714 val16
|= SYS_FUNC_BBRSTB
| SYS_FUNC_BB_GLB_RSTN
;
5715 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
5717 rtl8xxxu_write8(priv
, REG_BT_CONTROL_8723BU
+ 1, 0x18);
5718 rtl8xxxu_write8(priv
, REG_WLAN_ACT_CONTROL_8723B
, 0x04);
5719 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00);
5720 /* Antenna inverse */
5721 rtl8xxxu_write8(priv
, 0xfe08, 0x01);
5723 val16
= rtl8xxxu_read16(priv
, REG_PWR_DATA
);
5724 val16
|= PWR_DATA_EEPRPAD_RFE_CTRL_EN
;
5725 rtl8xxxu_write16(priv
, REG_PWR_DATA
, val16
);
5727 val32
= rtl8xxxu_read32(priv
, REG_LEDCFG0
);
5728 val32
|= LEDCFG0_DPDT_SELECT
;
5729 rtl8xxxu_write32(priv
, REG_LEDCFG0
, val32
);
5731 val8
= rtl8xxxu_read8(priv
, REG_PAD_CTRL1
);
5732 val8
&= ~PAD_CTRL1_SW_DPDT_SEL_DATA
;
5733 rtl8xxxu_write8(priv
, REG_PAD_CTRL1
, val8
);
5738 #ifdef CONFIG_RTL8XXXU_UNTESTED
5740 static int rtl8192cu_power_on(struct rtl8xxxu_priv
*priv
)
5747 for (i
= 100; i
; i
--) {
5748 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
);
5749 if (val8
& APS_FSMCO_PFM_ALDN
)
5754 pr_info("%s: Poll failed\n", __func__
);
5759 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5761 rtl8xxxu_write8(priv
, REG_RSV_CTRL
, 0x0);
5762 rtl8xxxu_write8(priv
, REG_SPS0_CTRL
, 0x2b);
5765 val8
= rtl8xxxu_read8(priv
, REG_LDOV12D_CTRL
);
5766 if (!(val8
& LDOV12D_ENABLE
)) {
5767 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__
, val8
);
5768 val8
|= LDOV12D_ENABLE
;
5769 rtl8xxxu_write8(priv
, REG_LDOV12D_CTRL
, val8
);
5773 val8
= rtl8xxxu_read8(priv
, REG_SYS_ISO_CTRL
);
5774 val8
&= ~SYS_ISO_MD2PP
;
5775 rtl8xxxu_write8(priv
, REG_SYS_ISO_CTRL
, val8
);
5781 val16
= rtl8xxxu_read16(priv
, REG_APS_FSMCO
);
5782 val16
|= APS_FSMCO_MAC_ENABLE
;
5783 rtl8xxxu_write16(priv
, REG_APS_FSMCO
, val16
);
5785 for (i
= 1000; i
; i
--) {
5786 val16
= rtl8xxxu_read16(priv
, REG_APS_FSMCO
);
5787 if (!(val16
& APS_FSMCO_MAC_ENABLE
))
5791 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__
);
5796 * Enable radio, GPIO, LED
5798 val16
= APS_FSMCO_HW_SUSPEND
| APS_FSMCO_ENABLE_POWERDOWN
|
5800 rtl8xxxu_write16(priv
, REG_APS_FSMCO
, val16
);
5803 * Release RF digital isolation
5805 val16
= rtl8xxxu_read16(priv
, REG_SYS_ISO_CTRL
);
5806 val16
&= ~SYS_ISO_DIOR
;
5807 rtl8xxxu_write16(priv
, REG_SYS_ISO_CTRL
, val16
);
5809 val8
= rtl8xxxu_read8(priv
, REG_APSD_CTRL
);
5810 val8
&= ~APSD_CTRL_OFF
;
5811 rtl8xxxu_write8(priv
, REG_APSD_CTRL
, val8
);
5812 for (i
= 200; i
; i
--) {
5813 val8
= rtl8xxxu_read8(priv
, REG_APSD_CTRL
);
5814 if (!(val8
& APSD_CTRL_OFF_STATUS
))
5819 pr_info("%s: APSD_CTRL poll failed\n", __func__
);
5824 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5826 val16
= rtl8xxxu_read16(priv
, REG_CR
);
5827 val16
|= CR_HCI_TXDMA_ENABLE
| CR_HCI_RXDMA_ENABLE
|
5828 CR_TXDMA_ENABLE
| CR_RXDMA_ENABLE
| CR_PROTOCOL_ENABLE
|
5829 CR_SCHEDULE_ENABLE
| CR_MAC_TX_ENABLE
| CR_MAC_RX_ENABLE
;
5830 rtl8xxxu_write16(priv
, REG_CR
, val16
);
5833 * Workaround for 8188RU LNA power leakage problem.
5835 if (priv
->rtlchip
== 0x8188c && priv
->hi_pa
) {
5836 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XCD_RF_PARM
);
5838 rtl8xxxu_write32(priv
, REG_FPGA0_XCD_RF_PARM
, val32
);
5845 static int rtl8192eu_power_on(struct rtl8xxxu_priv
*priv
)
5853 val32
= rtl8xxxu_read32(priv
, REG_SYS_CFG
);
5854 if (val32
& SYS_CFG_SPS_LDO_SEL
) {
5855 rtl8xxxu_write8(priv
, REG_LDO_SW_CTRL
, 0xc3);
5858 * Raise 1.2V voltage
5860 val32
= rtl8xxxu_read32(priv
, REG_8192E_LDOV12_CTRL
);
5861 val32
&= 0xff0fffff;
5862 val32
|= 0x00500000;
5863 rtl8xxxu_write32(priv
, REG_8192E_LDOV12_CTRL
, val32
);
5864 rtl8xxxu_write8(priv
, REG_LDO_SW_CTRL
, 0x83);
5867 rtl8192e_disabled_to_emu(priv
);
5869 ret
= rtl8192e_emu_to_active(priv
);
5873 rtl8xxxu_write16(priv
, REG_CR
, 0x0000);
5876 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5877 * Set CR bit10 to enable 32k calibration.
5879 val16
= rtl8xxxu_read16(priv
, REG_CR
);
5880 val16
|= (CR_HCI_TXDMA_ENABLE
| CR_HCI_RXDMA_ENABLE
|
5881 CR_TXDMA_ENABLE
| CR_RXDMA_ENABLE
|
5882 CR_PROTOCOL_ENABLE
| CR_SCHEDULE_ENABLE
|
5883 CR_MAC_TX_ENABLE
| CR_MAC_RX_ENABLE
|
5884 CR_SECURITY_ENABLE
| CR_CALTIMER_ENABLE
);
5885 rtl8xxxu_write16(priv
, REG_CR
, val16
);
5891 static void rtl8xxxu_power_off(struct rtl8xxxu_priv
*priv
)
5898 * Workaround for 8188RU LNA power leakage problem.
5900 if (priv
->rtlchip
== 0x8188c && priv
->hi_pa
) {
5901 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XCD_RF_PARM
);
5903 rtl8xxxu_write32(priv
, REG_FPGA0_XCD_RF_PARM
, val32
);
5906 rtl8xxxu_active_to_lps(priv
);
5909 rtl8xxxu_write8(priv
, REG_RF_CTRL
, 0x00);
5911 /* Reset Firmware if running in RAM */
5912 if (rtl8xxxu_read8(priv
, REG_MCU_FW_DL
) & MCU_FW_RAM_SEL
)
5913 rtl8xxxu_firmware_self_reset(priv
);
5916 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
5917 val16
&= ~SYS_FUNC_CPU_ENABLE
;
5918 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
5920 /* Reset MCU ready status */
5921 rtl8xxxu_write8(priv
, REG_MCU_FW_DL
, 0x00);
5923 rtl8xxxu_active_to_emu(priv
);
5924 rtl8xxxu_emu_to_disabled(priv
);
5926 /* Reset MCU IO Wrapper */
5927 val8
= rtl8xxxu_read8(priv
, REG_RSV_CTRL
+ 1);
5929 rtl8xxxu_write8(priv
, REG_RSV_CTRL
+ 1, val8
);
5931 val8
= rtl8xxxu_read8(priv
, REG_RSV_CTRL
+ 1);
5933 rtl8xxxu_write8(priv
, REG_RSV_CTRL
+ 1, val8
);
5935 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
5936 rtl8xxxu_write8(priv
, REG_RSV_CTRL
, 0x0e);
5940 static void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv
*priv
,
5941 u8 arg1
, u8 arg2
, u8 arg3
, u8 arg4
, u8 arg5
)
5945 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
5946 h2c
.b_type_dma
.cmd
= H2C_8723B_B_TYPE_TDMA
;
5947 h2c
.b_type_dma
.data1
= arg1
;
5948 h2c
.b_type_dma
.data2
= arg2
;
5949 h2c
.b_type_dma
.data3
= arg3
;
5950 h2c
.b_type_dma
.data4
= arg4
;
5951 h2c
.b_type_dma
.data5
= arg5
;
5952 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.b_type_dma
));
5956 static void rtl8723bu_init_bt(struct rtl8xxxu_priv
*priv
)
5963 * No indication anywhere as to what 0x0790 does. The 2 antenna
5964 * vendor code preserves bits 6-7 here.
5966 rtl8xxxu_write8(priv
, 0x0790, 0x05);
5968 * 0x0778 seems to be related to enabling the number of antennas
5969 * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it
5970 * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01
5972 rtl8xxxu_write8(priv
, 0x0778, 0x01);
5974 val8
= rtl8xxxu_read8(priv
, REG_GPIO_MUXCFG
);
5976 rtl8xxxu_write8(priv
, REG_GPIO_MUXCFG
, val8
);
5978 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_IQADJ_G1
, 0x780);
5980 rtl8723bu_write_btreg(priv
, 0x3c, 0x15); /* BT TRx Mask on */
5983 * Set BT grant to low
5985 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
5986 h2c
.bt_grant
.cmd
= H2C_8723B_BT_GRANT
;
5987 h2c
.bt_grant
.data
= 0;
5988 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.bt_grant
));
5991 * WLAN action by PTA
5993 rtl8xxxu_write8(priv
, REG_WLAN_ACT_CONTROL_8723B
, 0x04);
5996 * BT select S0/S1 controlled by WiFi
5998 val8
= rtl8xxxu_read8(priv
, 0x0067);
6000 rtl8xxxu_write8(priv
, 0x0067, val8
);
6002 val32
= rtl8xxxu_read32(priv
, REG_PWR_DATA
);
6004 rtl8xxxu_write32(priv
, REG_PWR_DATA
, val32
);
6007 * Bits 6/7 are marked in/out ... but for what?
6009 rtl8xxxu_write8(priv
, 0x0974, 0xff);
6011 val32
= rtl8xxxu_read32(priv
, REG_RFE_BUFFER
);
6012 val32
|= (BIT(0) | BIT(1));
6013 rtl8xxxu_write32(priv
, REG_RFE_BUFFER
, val32
);
6015 rtl8xxxu_write8(priv
, REG_RFE_CTRL_ANTA_SRC
, 0x77);
6017 val32
= rtl8xxxu_read32(priv
, REG_LEDCFG0
);
6020 rtl8xxxu_write32(priv
, REG_LEDCFG0
, val32
);
6023 * Fix external switch Main->S1, Aux->S0
6025 val8
= rtl8xxxu_read8(priv
, REG_PAD_CTRL1
);
6027 rtl8xxxu_write8(priv
, REG_PAD_CTRL1
, val8
);
6029 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
6030 h2c
.ant_sel_rsv
.cmd
= H2C_8723B_ANT_SEL_RSV
;
6031 h2c
.ant_sel_rsv
.ant_inverse
= 1;
6032 h2c
.ant_sel_rsv
.int_switch_type
= 0;
6033 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.ant_sel_rsv
));
6036 * 0x280, 0x00, 0x200, 0x80 - not clear
6038 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00);
6041 * Software control, antenna at WiFi side
6044 rtl8723bu_set_ps_tdma(priv
, 0x08, 0x00, 0x00, 0x00, 0x00);
6047 rtl8xxxu_write32(priv
, REG_BT_COEX_TABLE1
, 0x55555555);
6048 rtl8xxxu_write32(priv
, REG_BT_COEX_TABLE2
, 0x55555555);
6049 rtl8xxxu_write32(priv
, REG_BT_COEX_TABLE3
, 0x00ffffff);
6050 rtl8xxxu_write8(priv
, REG_BT_COEX_TABLE4
, 0x03);
6052 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
6053 h2c
.bt_info
.cmd
= H2C_8723B_BT_INFO
;
6054 h2c
.bt_info
.data
= BIT(0);
6055 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.bt_info
));
6057 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
6058 h2c
.ignore_wlan
.cmd
= H2C_8723B_BT_IGNORE_WLANACT
;
6059 h2c
.ignore_wlan
.data
= 0;
6060 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.ignore_wlan
));
6063 static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv
*priv
)
6069 * For now simply disable RX aggregation
6071 agg_ctrl
= rtl8xxxu_read8(priv
, REG_TRXDMA_CTRL
);
6072 agg_ctrl
&= ~TRXDMA_CTRL_RXDMA_AGG_EN
;
6074 agg_rx
= rtl8xxxu_read32(priv
, REG_RXDMA_AGG_PG_TH
);
6075 agg_rx
&= ~RXDMA_USB_AGG_ENABLE
;
6078 rtl8xxxu_write8(priv
, REG_TRXDMA_CTRL
, agg_ctrl
);
6079 rtl8xxxu_write32(priv
, REG_RXDMA_AGG_PG_TH
, agg_rx
);
6082 static void rtl8723bu_init_statistics(struct rtl8xxxu_priv
*priv
)
6086 /* Time duration for NHM unit: 4us, 0x2710=40ms */
6087 rtl8xxxu_write16(priv
, REG_NHM_TIMER_8723B
+ 2, 0x2710);
6088 rtl8xxxu_write16(priv
, REG_NHM_TH9_TH10_8723B
+ 2, 0xffff);
6089 rtl8xxxu_write32(priv
, REG_NHM_TH3_TO_TH0_8723B
, 0xffffff52);
6090 rtl8xxxu_write32(priv
, REG_NHM_TH7_TO_TH4_8723B
, 0xffffffff);
6092 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
6094 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
6096 val32
= rtl8xxxu_read32(priv
, REG_NHM_TH9_TH10_8723B
);
6097 val32
|= BIT(8) | BIT(9) | BIT(10);
6098 rtl8xxxu_write32(priv
, REG_NHM_TH9_TH10_8723B
, val32
);
6099 /* Max power amongst all RX antennas */
6100 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_FA_RSTC
);
6102 rtl8xxxu_write32(priv
, REG_OFDM0_FA_RSTC
, val32
);
6105 static int rtl8xxxu_init_device(struct ieee80211_hw
*hw
)
6107 struct rtl8xxxu_priv
*priv
= hw
->priv
;
6108 struct device
*dev
= &priv
->udev
->dev
;
6109 struct rtl8xxxu_rfregval
*rftable
;
6116 /* Check if MAC is already powered on */
6117 val8
= rtl8xxxu_read8(priv
, REG_CR
);
6120 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
6121 * initialized. First MAC returns 0xea, second MAC returns 0x00
6128 ret
= priv
->fops
->power_on(priv
);
6130 dev_warn(dev
, "%s: Failed power on\n", __func__
);
6134 dev_dbg(dev
, "%s: macpower %i\n", __func__
, macpower
);
6136 ret
= priv
->fops
->llt_init(priv
, TX_TOTAL_PAGE_NUM
);
6138 dev_warn(dev
, "%s: LLT table init failed\n", __func__
);
6143 * Presumably this is for 8188EU as well
6144 * Enable TX report and TX report timer
6146 if (priv
->rtlchip
== 0x8723bu
) {
6147 val8
= rtl8xxxu_read8(priv
, REG_TX_REPORT_CTRL
);
6149 rtl8xxxu_write8(priv
, REG_TX_REPORT_CTRL
, val8
);
6150 /* Set MAX RPT MACID */
6151 rtl8xxxu_write8(priv
, REG_TX_REPORT_CTRL
+ 1, 0x02);
6152 /* TX report Timer. Unit: 32us */
6153 rtl8xxxu_write16(priv
, REG_TX_REPORT_TIME
, 0xcdf0);
6156 val8
= rtl8xxxu_read8(priv
, 0xa3);
6158 rtl8xxxu_write8(priv
, 0xa3, val8
);
6162 ret
= rtl8xxxu_download_firmware(priv
);
6163 dev_dbg(dev
, "%s: download_fiwmare %i\n", __func__
, ret
);
6166 ret
= rtl8xxxu_start_firmware(priv
);
6167 dev_dbg(dev
, "%s: start_fiwmare %i\n", __func__
, ret
);
6171 /* Solve too many protocol error on USB bus */
6172 /* Can't do this for 8188/8192 UMC A cut parts */
6173 if (priv
->rtlchip
== 0x8723a ||
6174 ((priv
->rtlchip
== 0x8192c || priv
->rtlchip
== 0x8191c ||
6175 priv
->rtlchip
== 0x8188c) &&
6176 (priv
->chip_cut
|| !priv
->vendor_umc
))) {
6177 rtl8xxxu_write8(priv
, 0xfe40, 0xe6);
6178 rtl8xxxu_write8(priv
, 0xfe41, 0x94);
6179 rtl8xxxu_write8(priv
, 0xfe42, 0x80);
6181 rtl8xxxu_write8(priv
, 0xfe40, 0xe0);
6182 rtl8xxxu_write8(priv
, 0xfe41, 0x19);
6183 rtl8xxxu_write8(priv
, 0xfe42, 0x80);
6185 rtl8xxxu_write8(priv
, 0xfe40, 0xe5);
6186 rtl8xxxu_write8(priv
, 0xfe41, 0x91);
6187 rtl8xxxu_write8(priv
, 0xfe42, 0x80);
6189 rtl8xxxu_write8(priv
, 0xfe40, 0xe2);
6190 rtl8xxxu_write8(priv
, 0xfe41, 0x81);
6191 rtl8xxxu_write8(priv
, 0xfe42, 0x80);
6194 if (priv
->rtlchip
== 0x8192e) {
6195 rtl8xxxu_write32(priv
, REG_HIMR0
, 0x00);
6196 rtl8xxxu_write32(priv
, REG_HIMR1
, 0x00);
6199 if (priv
->fops
->phy_init_antenna_selection
)
6200 priv
->fops
->phy_init_antenna_selection(priv
);
6202 if (priv
->rtlchip
== 0x8723b)
6203 ret
= rtl8xxxu_init_mac(priv
, rtl8723b_mac_init_table
);
6205 ret
= rtl8xxxu_init_mac(priv
, rtl8723a_mac_init_table
);
6207 dev_dbg(dev
, "%s: init_mac %i\n", __func__
, ret
);
6211 ret
= rtl8xxxu_init_phy_bb(priv
);
6212 dev_dbg(dev
, "%s: init_phy_bb %i\n", __func__
, ret
);
6216 switch(priv
->rtlchip
) {
6218 rftable
= rtl8723au_radioa_1t_init_table
;
6219 ret
= rtl8xxxu_init_phy_rf(priv
, rftable
, RF_A
);
6222 rftable
= rtl8723bu_radioa_1t_init_table
;
6223 ret
= rtl8xxxu_init_phy_rf(priv
, rftable
, RF_A
);
6227 rtl8xxxu_write_rfreg(priv
, RF_A
, 0xb0, 0xdfbe0);
6228 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_MODE_AG
, 0x8c01);
6230 rtl8xxxu_write_rfreg(priv
, RF_A
, 0xb0, 0xdffe0);
6234 rftable
= rtl8188ru_radioa_1t_highpa_table
;
6236 rftable
= rtl8192cu_radioa_1t_init_table
;
6237 ret
= rtl8xxxu_init_phy_rf(priv
, rftable
, RF_A
);
6240 rftable
= rtl8192cu_radioa_1t_init_table
;
6241 ret
= rtl8xxxu_init_phy_rf(priv
, rftable
, RF_A
);
6244 rftable
= rtl8192cu_radioa_2t_init_table
;
6245 ret
= rtl8xxxu_init_phy_rf(priv
, rftable
, RF_A
);
6248 rftable
= rtl8192cu_radiob_2t_init_table
;
6249 ret
= rtl8xxxu_init_phy_rf(priv
, rftable
, RF_B
);
6259 * Chip specific quirks
6261 if (priv
->rtlchip
== 0x8723a) {
6262 /* Fix USB interface interference issue */
6263 rtl8xxxu_write8(priv
, 0xfe40, 0xe0);
6264 rtl8xxxu_write8(priv
, 0xfe41, 0x8d);
6265 rtl8xxxu_write8(priv
, 0xfe42, 0x80);
6266 rtl8xxxu_write32(priv
, REG_TXDMA_OFFSET_CHK
, 0xfd0320);
6268 /* Reduce 80M spur */
6269 rtl8xxxu_write32(priv
, REG_AFE_XTAL_CTRL
, 0x0381808d);
6270 rtl8xxxu_write32(priv
, REG_AFE_PLL_CTRL
, 0xf0ffff83);
6271 rtl8xxxu_write32(priv
, REG_AFE_PLL_CTRL
, 0xf0ffff82);
6272 rtl8xxxu_write32(priv
, REG_AFE_PLL_CTRL
, 0xf0ffff83);
6274 val32
= rtl8xxxu_read32(priv
, REG_TXDMA_OFFSET_CHK
);
6275 val32
|= TXDMA_OFFSET_DROP_DATA_EN
;
6276 rtl8xxxu_write32(priv
, REG_TXDMA_OFFSET_CHK
, val32
);
6280 if (priv
->ep_tx_normal_queue
)
6281 val8
= TX_PAGE_NUM_NORM_PQ
;
6285 rtl8xxxu_write8(priv
, REG_RQPN_NPQ
, val8
);
6287 val32
= (TX_PAGE_NUM_PUBQ
<< RQPN_NORM_PQ_SHIFT
) | RQPN_LOAD
;
6289 if (priv
->ep_tx_high_queue
)
6290 val32
|= (TX_PAGE_NUM_HI_PQ
<< RQPN_HI_PQ_SHIFT
);
6291 if (priv
->ep_tx_low_queue
)
6292 val32
|= (TX_PAGE_NUM_LO_PQ
<< RQPN_LO_PQ_SHIFT
);
6294 rtl8xxxu_write32(priv
, REG_RQPN
, val32
);
6297 * Set TX buffer boundary
6299 val8
= TX_TOTAL_PAGE_NUM
+ 1;
6301 if (priv
->rtlchip
== 0x8723b)
6304 rtl8xxxu_write8(priv
, REG_TXPKTBUF_BCNQ_BDNY
, val8
);
6305 rtl8xxxu_write8(priv
, REG_TXPKTBUF_MGQ_BDNY
, val8
);
6306 rtl8xxxu_write8(priv
, REG_TXPKTBUF_WMAC_LBK_BF_HD
, val8
);
6307 rtl8xxxu_write8(priv
, REG_TRXFF_BNDY
, val8
);
6308 rtl8xxxu_write8(priv
, REG_TDECTRL
+ 1, val8
);
6311 ret
= rtl8xxxu_init_queue_priority(priv
);
6312 dev_dbg(dev
, "%s: init_queue_priority %i\n", __func__
, ret
);
6316 /* RFSW Control - clear bit 14 ?? */
6317 if (priv
->rtlchip
!= 0x8723b)
6318 rtl8xxxu_write32(priv
, REG_FPGA0_TX_INFO
, 0x00000003);
6320 val32
= FPGA0_RF_TRSW
| FPGA0_RF_TRSWB
| FPGA0_RF_ANTSW
|
6321 FPGA0_RF_ANTSWB
| FPGA0_RF_PAPE
|
6322 ((FPGA0_RF_ANTSW
| FPGA0_RF_ANTSWB
| FPGA0_RF_PAPE
) <<
6323 FPGA0_RF_BD_CTRL_SHIFT
);
6324 rtl8xxxu_write32(priv
, REG_FPGA0_XAB_RF_SW_CTRL
, val32
);
6325 /* 0x860[6:5]= 00 - why? - this sets antenna B */
6326 rtl8xxxu_write32(priv
, REG_FPGA0_XA_RF_INT_OE
, 0x66F60210);
6328 priv
->rf_mode_ag
[0] = rtl8xxxu_read_rfreg(priv
, RF_A
,
6329 RF6052_REG_MODE_AG
);
6332 * Set RX page boundary
6334 if (priv
->rtlchip
== 0x8723b)
6335 rtl8xxxu_write16(priv
, REG_TRXFF_BNDY
+ 2, 0x3f7f);
6337 rtl8xxxu_write16(priv
, REG_TRXFF_BNDY
+ 2, 0x27ff);
6339 * Transfer page size is always 128
6341 if (priv
->rtlchip
== 0x8723b)
6342 val8
= (PBP_PAGE_SIZE_256
<< PBP_PAGE_SIZE_RX_SHIFT
) |
6343 (PBP_PAGE_SIZE_256
<< PBP_PAGE_SIZE_TX_SHIFT
);
6345 val8
= (PBP_PAGE_SIZE_128
<< PBP_PAGE_SIZE_RX_SHIFT
) |
6346 (PBP_PAGE_SIZE_128
<< PBP_PAGE_SIZE_TX_SHIFT
);
6347 rtl8xxxu_write8(priv
, REG_PBP
, val8
);
6350 * Unit in 8 bytes, not obvious what it is used for
6352 rtl8xxxu_write8(priv
, REG_RX_DRVINFO_SZ
, 4);
6355 * Enable all interrupts - not obvious USB needs to do this
6357 rtl8xxxu_write32(priv
, REG_HISR
, 0xffffffff);
6358 rtl8xxxu_write32(priv
, REG_HIMR
, 0xffffffff);
6360 rtl8xxxu_set_mac(priv
);
6361 rtl8xxxu_set_linktype(priv
, NL80211_IFTYPE_STATION
);
6364 * Configure initial WMAC settings
6366 val32
= RCR_ACCEPT_PHYS_MATCH
| RCR_ACCEPT_MCAST
| RCR_ACCEPT_BCAST
|
6367 RCR_ACCEPT_MGMT_FRAME
| RCR_HTC_LOC_CTRL
|
6368 RCR_APPEND_PHYSTAT
| RCR_APPEND_ICV
| RCR_APPEND_MIC
;
6369 rtl8xxxu_write32(priv
, REG_RCR
, val32
);
6372 * Accept all multicast
6374 rtl8xxxu_write32(priv
, REG_MAR
, 0xffffffff);
6375 rtl8xxxu_write32(priv
, REG_MAR
+ 4, 0xffffffff);
6378 * Init adaptive controls
6380 val32
= rtl8xxxu_read32(priv
, REG_RESPONSE_RATE_SET
);
6381 val32
&= ~RESPONSE_RATE_BITMAP_ALL
;
6382 val32
|= RESPONSE_RATE_RRSR_CCK_ONLY_1M
;
6383 rtl8xxxu_write32(priv
, REG_RESPONSE_RATE_SET
, val32
);
6385 /* CCK = 0x0a, OFDM = 0x10 */
6386 rtl8xxxu_set_spec_sifs(priv
, 0x10, 0x10);
6387 rtl8xxxu_set_retry(priv
, 0x30, 0x30);
6388 rtl8xxxu_set_spec_sifs(priv
, 0x0a, 0x10);
6393 rtl8xxxu_write16(priv
, REG_MAC_SPEC_SIFS
, 0x100a);
6396 rtl8xxxu_write16(priv
, REG_SIFS_CCK
, 0x100a);
6399 rtl8xxxu_write16(priv
, REG_SIFS_OFDM
, 0x100a);
6402 rtl8xxxu_write32(priv
, REG_EDCA_BE_PARAM
, 0x005ea42b);
6403 rtl8xxxu_write32(priv
, REG_EDCA_BK_PARAM
, 0x0000a44f);
6404 rtl8xxxu_write32(priv
, REG_EDCA_VI_PARAM
, 0x005ea324);
6405 rtl8xxxu_write32(priv
, REG_EDCA_VO_PARAM
, 0x002fa226);
6407 /* Set data auto rate fallback retry count */
6408 rtl8xxxu_write32(priv
, REG_DARFRC
, 0x00000000);
6409 rtl8xxxu_write32(priv
, REG_DARFRC
+ 4, 0x10080404);
6410 rtl8xxxu_write32(priv
, REG_RARFRC
, 0x04030201);
6411 rtl8xxxu_write32(priv
, REG_RARFRC
+ 4, 0x08070605);
6413 val8
= rtl8xxxu_read8(priv
, REG_FWHW_TXQ_CTRL
);
6414 val8
|= FWHW_TXQ_CTRL_AMPDU_RETRY
;
6415 rtl8xxxu_write8(priv
, REG_FWHW_TXQ_CTRL
, val8
);
6417 /* Set ACK timeout */
6418 rtl8xxxu_write8(priv
, REG_ACKTO
, 0x40);
6421 * Initialize beacon parameters
6423 val16
= BEACON_DISABLE_TSF_UPDATE
| (BEACON_DISABLE_TSF_UPDATE
<< 8);
6424 rtl8xxxu_write16(priv
, REG_BEACON_CTRL
, val16
);
6425 rtl8xxxu_write16(priv
, REG_TBTT_PROHIBIT
, 0x6404);
6426 rtl8xxxu_write8(priv
, REG_DRIVER_EARLY_INT
, DRIVER_EARLY_INT_TIME
);
6427 rtl8xxxu_write8(priv
, REG_BEACON_DMA_TIME
, BEACON_DMA_ATIME_INT_TIME
);
6428 rtl8xxxu_write16(priv
, REG_BEACON_TCFG
, 0x660F);
6431 * Initialize burst parameters
6433 if (priv
->rtlchip
== 0x8723b) {
6435 * For USB high speed set 512B packets
6437 val8
= rtl8xxxu_read8(priv
, REG_RXDMA_PRO_8723B
);
6438 val8
&= ~(BIT(4) | BIT(5));
6440 val8
|= BIT(1) | BIT(2) | BIT(3);
6441 rtl8xxxu_write8(priv
, REG_RXDMA_PRO_8723B
, val8
);
6444 * For USB high speed set 512B packets
6446 val8
= rtl8xxxu_read8(priv
, REG_HT_SINGLE_AMPDU_8723B
);
6448 rtl8xxxu_write8(priv
, REG_HT_SINGLE_AMPDU_8723B
, val8
);
6450 rtl8xxxu_write16(priv
, REG_MAX_AGGR_NUM
, 0x0c14);
6451 rtl8xxxu_write8(priv
, REG_AMPDU_MAX_TIME_8723B
, 0x5e);
6452 rtl8xxxu_write32(priv
, REG_AGGLEN_LMT
, 0xffffffff);
6453 rtl8xxxu_write8(priv
, REG_RX_PKT_LIMIT
, 0x18);
6454 rtl8xxxu_write8(priv
, REG_PIFS
, 0x00);
6455 rtl8xxxu_write8(priv
, REG_USTIME_TSF_8723B
, 0x50);
6456 rtl8xxxu_write8(priv
, REG_USTIME_EDCA
, 0x50);
6458 val8
= rtl8xxxu_read8(priv
, REG_RSV_CTRL
);
6459 val8
|= BIT(5) | BIT(6);
6460 rtl8xxxu_write8(priv
, REG_RSV_CTRL
, val8
);
6463 if (priv
->fops
->init_aggregation
)
6464 priv
->fops
->init_aggregation(priv
);
6467 * Enable CCK and OFDM block
6469 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
6470 val32
|= (FPGA_RF_MODE_CCK
| FPGA_RF_MODE_OFDM
);
6471 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
6474 * Invalidate all CAM entries - bit 30 is undocumented
6476 rtl8xxxu_write32(priv
, REG_CAM_CMD
, CAM_CMD_POLLING
| BIT(30));
6479 * Start out with default power levels for channel 6, 20MHz
6481 priv
->fops
->set_tx_power(priv
, 1, false);
6483 /* Let the 8051 take control of antenna setting */
6484 val8
= rtl8xxxu_read8(priv
, REG_LEDCFG2
);
6485 val8
|= LEDCFG2_DPDT_SELECT
;
6486 rtl8xxxu_write8(priv
, REG_LEDCFG2
, val8
);
6488 rtl8xxxu_write8(priv
, REG_HWSEQ_CTRL
, 0xff);
6490 /* Disable BAR - not sure if this has any effect on USB */
6491 rtl8xxxu_write32(priv
, REG_BAR_MODE_CTRL
, 0x0201ffff);
6493 rtl8xxxu_write16(priv
, REG_FAST_EDCA_CTRL
, 0);
6495 if (priv
->fops
->init_statistics
)
6496 priv
->fops
->init_statistics(priv
);
6498 rtl8723a_phy_lc_calibrate(priv
);
6500 priv
->fops
->phy_iq_calibrate(priv
);
6503 * This should enable thermal meter
6505 if (priv
->fops
->has_s0s1
)
6506 rtl8xxxu_write_rfreg(priv
,
6507 RF_A
, RF6052_REG_T_METER_8723B
, 0x37cf8);
6509 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_T_METER
, 0x60);
6511 /* Init BT hw config. */
6512 if (priv
->fops
->init_bt
)
6513 priv
->fops
->init_bt(priv
);
6515 /* Set NAV_UPPER to 30000us */
6516 val8
= ((30000 + NAV_UPPER_UNIT
- 1) / NAV_UPPER_UNIT
);
6517 rtl8xxxu_write8(priv
, REG_NAV_UPPER
, val8
);
6519 if (priv
->rtlchip
== 0x8723a) {
6521 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
6522 * but we need to find root cause.
6523 * This is 8723au only.
6525 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
6526 if ((val32
& 0xff000000) != 0x83000000) {
6527 val32
|= FPGA_RF_MODE_CCK
;
6528 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
6532 val32
= rtl8xxxu_read32(priv
, REG_FWHW_TXQ_CTRL
);
6533 val32
|= FWHW_TXQ_CTRL_XMIT_MGMT_ACK
;
6534 /* ack for xmit mgmt frames. */
6535 rtl8xxxu_write32(priv
, REG_FWHW_TXQ_CTRL
, val32
);
6541 static void rtl8xxxu_disable_device(struct ieee80211_hw
*hw
)
6543 struct rtl8xxxu_priv
*priv
= hw
->priv
;
6545 rtl8xxxu_power_off(priv
);
6548 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv
*priv
,
6549 struct ieee80211_key_conf
*key
, const u8
*mac
)
6551 u32 cmd
, val32
, addr
, ctrl
;
6552 int j
, i
, tmp_debug
;
6554 tmp_debug
= rtl8xxxu_debug
;
6555 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_KEY
)
6556 rtl8xxxu_debug
|= RTL8XXXU_DEBUG_REG_WRITE
;
6559 * This is a bit of a hack - the lower bits of the cipher
6560 * suite selector happens to match the cipher index in the CAM
6562 addr
= key
->keyidx
<< CAM_CMD_KEY_SHIFT
;
6563 ctrl
= (key
->cipher
& 0x0f) << 2 | key
->keyidx
| CAM_WRITE_VALID
;
6565 for (j
= 5; j
>= 0; j
--) {
6568 val32
= ctrl
| (mac
[0] << 16) | (mac
[1] << 24);
6571 val32
= mac
[2] | (mac
[3] << 8) |
6572 (mac
[4] << 16) | (mac
[5] << 24);
6576 val32
= key
->key
[i
] | (key
->key
[i
+ 1] << 8) |
6577 key
->key
[i
+ 2] << 16 | key
->key
[i
+ 3] << 24;
6581 rtl8xxxu_write32(priv
, REG_CAM_WRITE
, val32
);
6582 cmd
= CAM_CMD_POLLING
| CAM_CMD_WRITE
| (addr
+ j
);
6583 rtl8xxxu_write32(priv
, REG_CAM_CMD
, cmd
);
6587 rtl8xxxu_debug
= tmp_debug
;
6590 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw
*hw
,
6591 struct ieee80211_vif
*vif
, const u8
*mac
)
6593 struct rtl8xxxu_priv
*priv
= hw
->priv
;
6596 val8
= rtl8xxxu_read8(priv
, REG_BEACON_CTRL
);
6597 val8
|= BEACON_DISABLE_TSF_UPDATE
;
6598 rtl8xxxu_write8(priv
, REG_BEACON_CTRL
, val8
);
6601 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw
*hw
,
6602 struct ieee80211_vif
*vif
)
6604 struct rtl8xxxu_priv
*priv
= hw
->priv
;
6607 val8
= rtl8xxxu_read8(priv
, REG_BEACON_CTRL
);
6608 val8
&= ~BEACON_DISABLE_TSF_UPDATE
;
6609 rtl8xxxu_write8(priv
, REG_BEACON_CTRL
, val8
);
6612 static void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv
*priv
,
6613 u32 ramask
, int sgi
)
6617 h2c
.ramask
.cmd
= H2C_SET_RATE_MASK
;
6618 h2c
.ramask
.mask_lo
= cpu_to_le16(ramask
& 0xffff);
6619 h2c
.ramask
.mask_hi
= cpu_to_le16(ramask
>> 16);
6621 h2c
.ramask
.arg
= 0x80;
6623 h2c
.ramask
.arg
|= 0x20;
6625 dev_dbg(&priv
->udev
->dev
, "%s: rate mask %08x, arg %02x, size %zi\n",
6626 __func__
, ramask
, h2c
.ramask
.arg
, sizeof(h2c
.ramask
));
6627 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.ramask
));
6630 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv
*priv
, u32 rate_cfg
)
6635 rate_cfg
&= RESPONSE_RATE_BITMAP_ALL
;
6637 val32
= rtl8xxxu_read32(priv
, REG_RESPONSE_RATE_SET
);
6638 val32
&= ~RESPONSE_RATE_BITMAP_ALL
;
6640 rtl8xxxu_write32(priv
, REG_RESPONSE_RATE_SET
, val32
);
6642 dev_dbg(&priv
->udev
->dev
, "%s: rates %08x\n", __func__
, rate_cfg
);
6645 rate_cfg
= (rate_cfg
>> 1);
6648 rtl8xxxu_write8(priv
, REG_INIRTS_RATE_SEL
, rate_idx
);
6652 rtl8xxxu_bss_info_changed(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
6653 struct ieee80211_bss_conf
*bss_conf
, u32 changed
)
6655 struct rtl8xxxu_priv
*priv
= hw
->priv
;
6656 struct device
*dev
= &priv
->udev
->dev
;
6657 struct ieee80211_sta
*sta
;
6661 if (changed
& BSS_CHANGED_ASSOC
) {
6664 dev_dbg(dev
, "Changed ASSOC: %i!\n", bss_conf
->assoc
);
6666 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
6667 rtl8xxxu_set_linktype(priv
, vif
->type
);
6669 if (bss_conf
->assoc
) {
6674 sta
= ieee80211_find_sta(vif
, bss_conf
->bssid
);
6676 dev_info(dev
, "%s: ASSOC no sta found\n",
6682 if (sta
->ht_cap
.ht_supported
)
6683 dev_info(dev
, "%s: HT supported\n", __func__
);
6684 if (sta
->vht_cap
.vht_supported
)
6685 dev_info(dev
, "%s: VHT supported\n", __func__
);
6687 /* TODO: Set bits 28-31 for rate adaptive id */
6688 ramask
= (sta
->supp_rates
[0] & 0xfff) |
6689 sta
->ht_cap
.mcs
.rx_mask
[0] << 12 |
6690 sta
->ht_cap
.mcs
.rx_mask
[1] << 20;
6691 if (sta
->ht_cap
.cap
&
6692 (IEEE80211_HT_CAP_SGI_40
| IEEE80211_HT_CAP_SGI_20
))
6696 rtl8xxxu_update_rate_mask(priv
, ramask
, sgi
);
6698 rtl8xxxu_write8(priv
, REG_BCN_MAX_ERR
, 0xff);
6700 rtl8723a_stop_tx_beacon(priv
);
6702 /* joinbss sequence */
6703 rtl8xxxu_write16(priv
, REG_BCN_PSR_RPT
,
6704 0xc000 | bss_conf
->aid
);
6706 h2c
.joinbss
.data
= H2C_JOIN_BSS_CONNECT
;
6708 val8
= rtl8xxxu_read8(priv
, REG_BEACON_CTRL
);
6709 val8
|= BEACON_DISABLE_TSF_UPDATE
;
6710 rtl8xxxu_write8(priv
, REG_BEACON_CTRL
, val8
);
6712 h2c
.joinbss
.data
= H2C_JOIN_BSS_DISCONNECT
;
6714 h2c
.joinbss
.cmd
= H2C_JOIN_BSS_REPORT
;
6715 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.joinbss
));
6718 if (changed
& BSS_CHANGED_ERP_PREAMBLE
) {
6719 dev_dbg(dev
, "Changed ERP_PREAMBLE: Use short preamble %i\n",
6720 bss_conf
->use_short_preamble
);
6721 val32
= rtl8xxxu_read32(priv
, REG_RESPONSE_RATE_SET
);
6722 if (bss_conf
->use_short_preamble
)
6723 val32
|= RSR_ACK_SHORT_PREAMBLE
;
6725 val32
&= ~RSR_ACK_SHORT_PREAMBLE
;
6726 rtl8xxxu_write32(priv
, REG_RESPONSE_RATE_SET
, val32
);
6729 if (changed
& BSS_CHANGED_ERP_SLOT
) {
6730 dev_dbg(dev
, "Changed ERP_SLOT: short_slot_time %i\n",
6731 bss_conf
->use_short_slot
);
6733 if (bss_conf
->use_short_slot
)
6737 rtl8xxxu_write8(priv
, REG_SLOT
, val8
);
6740 if (changed
& BSS_CHANGED_BSSID
) {
6741 dev_dbg(dev
, "Changed BSSID!\n");
6742 rtl8xxxu_set_bssid(priv
, bss_conf
->bssid
);
6745 if (changed
& BSS_CHANGED_BASIC_RATES
) {
6746 dev_dbg(dev
, "Changed BASIC_RATES!\n");
6747 rtl8xxxu_set_basic_rates(priv
, bss_conf
->basic_rates
);
6753 static u32
rtl8xxxu_80211_to_rtl_queue(u32 queue
)
6758 case IEEE80211_AC_VO
:
6759 rtlqueue
= TXDESC_QUEUE_VO
;
6761 case IEEE80211_AC_VI
:
6762 rtlqueue
= TXDESC_QUEUE_VI
;
6764 case IEEE80211_AC_BE
:
6765 rtlqueue
= TXDESC_QUEUE_BE
;
6767 case IEEE80211_AC_BK
:
6768 rtlqueue
= TXDESC_QUEUE_BK
;
6771 rtlqueue
= TXDESC_QUEUE_BE
;
6777 static u32
rtl8xxxu_queue_select(struct ieee80211_hw
*hw
, struct sk_buff
*skb
)
6779 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
6782 if (ieee80211_is_mgmt(hdr
->frame_control
))
6783 queue
= TXDESC_QUEUE_MGNT
;
6785 queue
= rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb
));
6791 * Despite newer chips 8723b/8812/8821 having a larger TX descriptor
6792 * format. The descriptor checksum is still only calculated over the
6793 * initial 32 bytes of the descriptor!
6795 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8723au_tx_desc
*tx_desc
)
6797 __le16
*ptr
= (__le16
*)tx_desc
;
6802 * Clear csum field before calculation, as the csum field is
6803 * in the middle of the struct.
6805 tx_desc
->csum
= cpu_to_le16(0);
6807 for (i
= 0; i
< (sizeof(struct rtl8723au_tx_desc
) / sizeof(u16
)); i
++)
6808 csum
= csum
^ le16_to_cpu(ptr
[i
]);
6810 tx_desc
->csum
|= cpu_to_le16(csum
);
6813 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv
*priv
)
6815 struct rtl8xxxu_tx_urb
*tx_urb
, *tmp
;
6816 unsigned long flags
;
6818 spin_lock_irqsave(&priv
->tx_urb_lock
, flags
);
6819 list_for_each_entry_safe(tx_urb
, tmp
, &priv
->tx_urb_free_list
, list
) {
6820 list_del(&tx_urb
->list
);
6821 priv
->tx_urb_free_count
--;
6822 usb_free_urb(&tx_urb
->urb
);
6824 spin_unlock_irqrestore(&priv
->tx_urb_lock
, flags
);
6827 static struct rtl8xxxu_tx_urb
*
6828 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv
*priv
)
6830 struct rtl8xxxu_tx_urb
*tx_urb
;
6831 unsigned long flags
;
6833 spin_lock_irqsave(&priv
->tx_urb_lock
, flags
);
6834 tx_urb
= list_first_entry_or_null(&priv
->tx_urb_free_list
,
6835 struct rtl8xxxu_tx_urb
, list
);
6837 list_del(&tx_urb
->list
);
6838 priv
->tx_urb_free_count
--;
6839 if (priv
->tx_urb_free_count
< RTL8XXXU_TX_URB_LOW_WATER
&&
6840 !priv
->tx_stopped
) {
6841 priv
->tx_stopped
= true;
6842 ieee80211_stop_queues(priv
->hw
);
6846 spin_unlock_irqrestore(&priv
->tx_urb_lock
, flags
);
6851 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv
*priv
,
6852 struct rtl8xxxu_tx_urb
*tx_urb
)
6854 unsigned long flags
;
6856 INIT_LIST_HEAD(&tx_urb
->list
);
6858 spin_lock_irqsave(&priv
->tx_urb_lock
, flags
);
6860 list_add(&tx_urb
->list
, &priv
->tx_urb_free_list
);
6861 priv
->tx_urb_free_count
++;
6862 if (priv
->tx_urb_free_count
> RTL8XXXU_TX_URB_HIGH_WATER
&&
6864 priv
->tx_stopped
= false;
6865 ieee80211_wake_queues(priv
->hw
);
6868 spin_unlock_irqrestore(&priv
->tx_urb_lock
, flags
);
6871 static void rtl8xxxu_tx_complete(struct urb
*urb
)
6873 struct sk_buff
*skb
= (struct sk_buff
*)urb
->context
;
6874 struct ieee80211_tx_info
*tx_info
;
6875 struct ieee80211_hw
*hw
;
6876 struct rtl8xxxu_priv
*priv
;
6877 struct rtl8xxxu_tx_urb
*tx_urb
=
6878 container_of(urb
, struct rtl8xxxu_tx_urb
, urb
);
6880 tx_info
= IEEE80211_SKB_CB(skb
);
6881 hw
= tx_info
->rate_driver_data
[0];
6884 skb_pull(skb
, priv
->fops
->tx_desc_size
);
6886 ieee80211_tx_info_clear_status(tx_info
);
6887 tx_info
->status
.rates
[0].idx
= -1;
6888 tx_info
->status
.rates
[0].count
= 0;
6891 tx_info
->flags
|= IEEE80211_TX_STAT_ACK
;
6893 ieee80211_tx_status_irqsafe(hw
, skb
);
6895 rtl8xxxu_free_tx_urb(priv
, tx_urb
);
6898 static void rtl8xxxu_dump_action(struct device
*dev
,
6899 struct ieee80211_hdr
*hdr
)
6901 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)hdr
;
6904 if (!(rtl8xxxu_debug
& RTL8XXXU_DEBUG_ACTION
))
6907 switch (mgmt
->u
.action
.u
.addba_resp
.action_code
) {
6908 case WLAN_ACTION_ADDBA_RESP
:
6909 cap
= le16_to_cpu(mgmt
->u
.action
.u
.addba_resp
.capab
);
6910 timeout
= le16_to_cpu(mgmt
->u
.action
.u
.addba_resp
.timeout
);
6911 dev_info(dev
, "WLAN_ACTION_ADDBA_RESP: "
6912 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
6915 (cap
& IEEE80211_ADDBA_PARAM_TID_MASK
) >> 2,
6916 (cap
& IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK
) >> 6,
6918 le16_to_cpu(mgmt
->u
.action
.u
.addba_resp
.status
));
6920 case WLAN_ACTION_ADDBA_REQ
:
6921 cap
= le16_to_cpu(mgmt
->u
.action
.u
.addba_req
.capab
);
6922 timeout
= le16_to_cpu(mgmt
->u
.action
.u
.addba_req
.timeout
);
6923 dev_info(dev
, "WLAN_ACTION_ADDBA_REQ: "
6924 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
6926 (cap
& IEEE80211_ADDBA_PARAM_TID_MASK
) >> 2,
6927 (cap
& IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK
) >> 6,
6931 dev_info(dev
, "action frame %02x\n",
6932 mgmt
->u
.action
.u
.addba_resp
.action_code
);
6937 static void rtl8xxxu_tx(struct ieee80211_hw
*hw
,
6938 struct ieee80211_tx_control
*control
,
6939 struct sk_buff
*skb
)
6941 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
6942 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
6943 struct ieee80211_rate
*tx_rate
= ieee80211_get_tx_rate(hw
, tx_info
);
6944 struct rtl8xxxu_priv
*priv
= hw
->priv
;
6945 struct rtl8723au_tx_desc
*tx_desc
;
6946 struct rtl8723bu_tx_desc
*tx_desc40
;
6947 struct rtl8xxxu_tx_urb
*tx_urb
;
6948 struct ieee80211_sta
*sta
= NULL
;
6949 struct ieee80211_vif
*vif
= tx_info
->control
.vif
;
6950 struct device
*dev
= &priv
->udev
->dev
;
6952 u16 pktlen
= skb
->len
;
6954 u16 rate_flag
= tx_info
->control
.rates
[0].flags
;
6955 int tx_desc_size
= priv
->fops
->tx_desc_size
;
6957 bool usedesc40
, ampdu_enable
;
6959 if (skb_headroom(skb
) < tx_desc_size
) {
6961 "%s: Not enough headroom (%i) for tx descriptor\n",
6962 __func__
, skb_headroom(skb
));
6966 if (unlikely(skb
->len
> (65535 - tx_desc_size
))) {
6967 dev_warn(dev
, "%s: Trying to send over-sized skb (%i)\n",
6968 __func__
, skb
->len
);
6972 tx_urb
= rtl8xxxu_alloc_tx_urb(priv
);
6974 dev_warn(dev
, "%s: Unable to allocate tx urb\n", __func__
);
6978 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_TX
)
6979 dev_info(dev
, "%s: TX rate: %d (%d), pkt size %d\n",
6980 __func__
, tx_rate
->bitrate
, tx_rate
->hw_value
, pktlen
);
6982 if (ieee80211_is_action(hdr
->frame_control
))
6983 rtl8xxxu_dump_action(dev
, hdr
);
6985 usedesc40
= (tx_desc_size
== 40);
6986 tx_info
->rate_driver_data
[0] = hw
;
6988 if (control
&& control
->sta
)
6991 tx_desc
= (struct rtl8723au_tx_desc
*)skb_push(skb
, tx_desc_size
);
6993 memset(tx_desc
, 0, tx_desc_size
);
6994 tx_desc
->pkt_size
= cpu_to_le16(pktlen
);
6995 tx_desc
->pkt_offset
= tx_desc_size
;
6998 TXDESC_OWN
| TXDESC_FIRST_SEGMENT
| TXDESC_LAST_SEGMENT
;
6999 if (is_multicast_ether_addr(ieee80211_get_DA(hdr
)) ||
7000 is_broadcast_ether_addr(ieee80211_get_DA(hdr
)))
7001 tx_desc
->txdw0
|= TXDESC_BROADMULTICAST
;
7003 queue
= rtl8xxxu_queue_select(hw
, skb
);
7004 tx_desc
->txdw1
= cpu_to_le32(queue
<< TXDESC_QUEUE_SHIFT
);
7006 if (tx_info
->control
.hw_key
) {
7007 switch (tx_info
->control
.hw_key
->cipher
) {
7008 case WLAN_CIPHER_SUITE_WEP40
:
7009 case WLAN_CIPHER_SUITE_WEP104
:
7010 case WLAN_CIPHER_SUITE_TKIP
:
7011 tx_desc
->txdw1
|= cpu_to_le32(TXDESC_SEC_RC4
);
7013 case WLAN_CIPHER_SUITE_CCMP
:
7014 tx_desc
->txdw1
|= cpu_to_le32(TXDESC_SEC_AES
);
7021 if (rate_flag
& IEEE80211_TX_RC_MCS
)
7022 rate
= tx_info
->control
.rates
[0].idx
+ DESC_RATE_MCS0
;
7024 rate
= tx_rate
->hw_value
;
7025 tx_desc
->txdw5
= cpu_to_le32(rate
);
7027 if (ieee80211_is_data(hdr
->frame_control
))
7028 tx_desc
->txdw5
|= cpu_to_le32(0x0001ff00);
7030 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
7031 ampdu_enable
= false;
7032 if (ieee80211_is_data_qos(hdr
->frame_control
) && sta
) {
7033 if (sta
->ht_cap
.ht_supported
) {
7036 ampdu
= (u32
)sta
->ht_cap
.ampdu_density
;
7037 val32
= ampdu
<< TXDESC_AMPDU_DENSITY_SHIFT
;
7038 tx_desc
->txdw2
|= cpu_to_le32(val32
);
7040 ampdu_enable
= true;
7044 seq_number
= IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr
->seq_ctrl
));
7047 cpu_to_le32((u32
)seq_number
<< TXDESC_SEQ_SHIFT_8723A
);
7050 tx_desc
->txdw1
|= cpu_to_le32(TXDESC_AGG_ENABLE_8723A
);
7052 tx_desc
->txdw1
|= cpu_to_le32(TXDESC_AGG_BREAK_8723A
);
7054 tx_desc40
= (struct rtl8723bu_tx_desc
*)tx_desc
;
7057 cpu_to_le32((u32
)seq_number
<< TXDESC_SEQ_SHIFT_8723B
);
7061 cpu_to_le32(TXDESC_AGG_ENABLE_8723B
);
7063 tx_desc40
->txdw2
|= cpu_to_le32(TXDESC_AGG_BREAK_8723B
);
7066 if (ieee80211_is_data_qos(hdr
->frame_control
))
7067 tx_desc
->txdw4
|= cpu_to_le32(TXDESC_QOS
);
7068 if (rate_flag
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
||
7069 (sta
&& vif
&& vif
->bss_conf
.use_short_preamble
))
7070 tx_desc
->txdw4
|= cpu_to_le32(TXDESC_SHORT_PREAMBLE
);
7071 if (rate_flag
& IEEE80211_TX_RC_SHORT_GI
||
7072 (ieee80211_is_data_qos(hdr
->frame_control
) &&
7073 sta
&& sta
->ht_cap
.cap
&
7074 (IEEE80211_HT_CAP_SGI_40
| IEEE80211_HT_CAP_SGI_20
))) {
7075 tx_desc
->txdw5
|= cpu_to_le32(TXDESC_SHORT_GI
);
7077 if (ieee80211_is_mgmt(hdr
->frame_control
)) {
7078 tx_desc
->txdw5
= cpu_to_le32(tx_rate
->hw_value
);
7079 tx_desc
->txdw4
|= cpu_to_le32(TXDESC_USE_DRIVER_RATE_8723A
);
7081 cpu_to_le32(6 << TXDESC_RETRY_LIMIT_SHIFT_8723A
);
7082 tx_desc
->txdw5
|= cpu_to_le32(TXDESC_RETRY_LIMIT_ENABLE_8723A
);
7085 if (rate_flag
& IEEE80211_TX_RC_USE_RTS_CTS
) {
7086 /* Use RTS rate 24M - does the mac80211 tell us which to use? */
7087 tx_desc
->txdw4
|= cpu_to_le32(DESC_RATE_24M
<<
7088 TXDESC_RTS_RATE_SHIFT_8723A
);
7089 tx_desc
->txdw4
|= cpu_to_le32(TXDESC_RTS_CTS_ENABLE_8723A
);
7090 tx_desc
->txdw4
|= cpu_to_le32(TXDESC_HW_RTS_ENABLE_8723A
);
7093 rtl8xxxu_calc_tx_desc_csum(tx_desc
);
7095 usb_fill_bulk_urb(&tx_urb
->urb
, priv
->udev
, priv
->pipe_out
[queue
],
7096 skb
->data
, skb
->len
, rtl8xxxu_tx_complete
, skb
);
7098 usb_anchor_urb(&tx_urb
->urb
, &priv
->tx_anchor
);
7099 ret
= usb_submit_urb(&tx_urb
->urb
, GFP_ATOMIC
);
7101 usb_unanchor_urb(&tx_urb
->urb
);
7102 rtl8xxxu_free_tx_urb(priv
, tx_urb
);
7110 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv
*priv
,
7111 struct ieee80211_rx_status
*rx_status
,
7112 struct rtl8xxxu_rx_desc
*rx_desc
,
7113 struct rtl8723au_phy_stats
*phy_stats
)
7115 if (phy_stats
->sgi_en
)
7116 rx_status
->flag
|= RX_FLAG_SHORT_GI
;
7118 if (rx_desc
->rxmcs
< DESC_RATE_6M
) {
7120 * Handle PHY stats for CCK rates
7122 u8 cck_agc_rpt
= phy_stats
->cck_agc_rpt_ofdm_cfosho_a
;
7124 switch (cck_agc_rpt
& 0xc0) {
7126 rx_status
->signal
= -46 - (cck_agc_rpt
& 0x3e);
7129 rx_status
->signal
= -26 - (cck_agc_rpt
& 0x3e);
7132 rx_status
->signal
= -12 - (cck_agc_rpt
& 0x3e);
7135 rx_status
->signal
= 16 - (cck_agc_rpt
& 0x3e);
7140 (phy_stats
->cck_sig_qual_ofdm_pwdb_all
>> 1) - 110;
7144 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv
*priv
)
7146 struct rtl8xxxu_rx_urb
*rx_urb
, *tmp
;
7147 unsigned long flags
;
7149 spin_lock_irqsave(&priv
->rx_urb_lock
, flags
);
7151 list_for_each_entry_safe(rx_urb
, tmp
,
7152 &priv
->rx_urb_pending_list
, list
) {
7153 list_del(&rx_urb
->list
);
7154 priv
->rx_urb_pending_count
--;
7155 usb_free_urb(&rx_urb
->urb
);
7158 spin_unlock_irqrestore(&priv
->rx_urb_lock
, flags
);
7161 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv
*priv
,
7162 struct rtl8xxxu_rx_urb
*rx_urb
)
7164 struct sk_buff
*skb
;
7165 unsigned long flags
;
7168 spin_lock_irqsave(&priv
->rx_urb_lock
, flags
);
7170 if (!priv
->shutdown
) {
7171 list_add_tail(&rx_urb
->list
, &priv
->rx_urb_pending_list
);
7172 priv
->rx_urb_pending_count
++;
7173 pending
= priv
->rx_urb_pending_count
;
7175 skb
= (struct sk_buff
*)rx_urb
->urb
.context
;
7177 usb_free_urb(&rx_urb
->urb
);
7180 spin_unlock_irqrestore(&priv
->rx_urb_lock
, flags
);
7182 if (pending
> RTL8XXXU_RX_URB_PENDING_WATER
)
7183 schedule_work(&priv
->rx_urb_wq
);
7186 static void rtl8xxxu_rx_urb_work(struct work_struct
*work
)
7188 struct rtl8xxxu_priv
*priv
;
7189 struct rtl8xxxu_rx_urb
*rx_urb
, *tmp
;
7190 struct list_head local
;
7191 struct sk_buff
*skb
;
7192 unsigned long flags
;
7195 priv
= container_of(work
, struct rtl8xxxu_priv
, rx_urb_wq
);
7196 INIT_LIST_HEAD(&local
);
7198 spin_lock_irqsave(&priv
->rx_urb_lock
, flags
);
7200 list_splice_init(&priv
->rx_urb_pending_list
, &local
);
7201 priv
->rx_urb_pending_count
= 0;
7203 spin_unlock_irqrestore(&priv
->rx_urb_lock
, flags
);
7205 list_for_each_entry_safe(rx_urb
, tmp
, &local
, list
) {
7206 list_del_init(&rx_urb
->list
);
7207 ret
= rtl8xxxu_submit_rx_urb(priv
, rx_urb
);
7209 * If out of memory or temporary error, put it back on the
7210 * queue and try again. Otherwise the device is dead/gone
7211 * and we should drop it.
7218 rtl8xxxu_queue_rx_urb(priv
, rx_urb
);
7221 pr_info("failed to requeue urb %i\n", ret
);
7222 skb
= (struct sk_buff
*)rx_urb
->urb
.context
;
7224 usb_free_urb(&rx_urb
->urb
);
7229 static int rtl8723au_parse_rx_desc(struct rtl8xxxu_priv
*priv
,
7230 struct sk_buff
*skb
,
7231 struct ieee80211_rx_status
*rx_status
)
7233 struct rtl8xxxu_rx_desc
*rx_desc
= (struct rtl8xxxu_rx_desc
*)skb
->data
;
7234 struct rtl8723au_phy_stats
*phy_stats
;
7235 int drvinfo_sz
, desc_shift
;
7237 skb_pull(skb
, sizeof(struct rtl8xxxu_rx_desc
));
7239 phy_stats
= (struct rtl8723au_phy_stats
*)skb
->data
;
7241 drvinfo_sz
= rx_desc
->drvinfo_sz
* 8;
7242 desc_shift
= rx_desc
->shift
;
7243 skb_pull(skb
, drvinfo_sz
+ desc_shift
);
7245 if (rx_desc
->phy_stats
)
7246 rtl8xxxu_rx_parse_phystats(priv
, rx_status
, rx_desc
, phy_stats
);
7248 rx_status
->mactime
= le32_to_cpu(rx_desc
->tsfl
);
7249 rx_status
->flag
|= RX_FLAG_MACTIME_START
;
7251 if (!rx_desc
->swdec
)
7252 rx_status
->flag
|= RX_FLAG_DECRYPTED
;
7254 rx_status
->flag
|= RX_FLAG_FAILED_FCS_CRC
;
7256 rx_status
->flag
|= RX_FLAG_40MHZ
;
7258 if (rx_desc
->rxht
) {
7259 rx_status
->flag
|= RX_FLAG_HT
;
7260 rx_status
->rate_idx
= rx_desc
->rxmcs
- DESC_RATE_MCS0
;
7262 rx_status
->rate_idx
= rx_desc
->rxmcs
;
7265 return RX_TYPE_DATA_PKT
;
7268 static int rtl8723bu_parse_rx_desc(struct rtl8xxxu_priv
*priv
,
7269 struct sk_buff
*skb
,
7270 struct ieee80211_rx_status
*rx_status
)
7272 struct rtl8723bu_rx_desc
*rx_desc
=
7273 (struct rtl8723bu_rx_desc
*)skb
->data
;
7274 struct rtl8723au_phy_stats
*phy_stats
;
7275 int drvinfo_sz
, desc_shift
;
7278 skb_pull(skb
, sizeof(struct rtl8723bu_rx_desc
));
7280 phy_stats
= (struct rtl8723au_phy_stats
*)skb
->data
;
7282 drvinfo_sz
= rx_desc
->drvinfo_sz
* 8;
7283 desc_shift
= rx_desc
->shift
;
7284 skb_pull(skb
, drvinfo_sz
+ desc_shift
);
7286 rx_status
->mactime
= le32_to_cpu(rx_desc
->tsfl
);
7287 rx_status
->flag
|= RX_FLAG_MACTIME_START
;
7289 if (!rx_desc
->swdec
)
7290 rx_status
->flag
|= RX_FLAG_DECRYPTED
;
7292 rx_status
->flag
|= RX_FLAG_FAILED_FCS_CRC
;
7294 rx_status
->flag
|= RX_FLAG_40MHZ
;
7296 if (rx_desc
->rxmcs
>= DESC_RATE_MCS0
) {
7297 rx_status
->flag
|= RX_FLAG_HT
;
7298 rx_status
->rate_idx
= rx_desc
->rxmcs
- DESC_RATE_MCS0
;
7300 rx_status
->rate_idx
= rx_desc
->rxmcs
;
7303 if (rx_desc
->rpt_sel
) {
7304 struct device
*dev
= &priv
->udev
->dev
;
7305 dev_dbg(dev
, "%s: C2H packet\n", __func__
);
7306 rx_type
= RX_TYPE_C2H
;
7308 rx_type
= RX_TYPE_DATA_PKT
;
7314 static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv
*priv
,
7315 struct sk_buff
*skb
)
7317 struct rtl8723bu_c2h
*c2h
= (struct rtl8723bu_c2h
*)skb
->data
;
7318 struct device
*dev
= &priv
->udev
->dev
;
7323 dev_dbg(dev
, "C2H ID %02x seq %02x, len %02x source %02x\n",
7324 c2h
->id
, c2h
->seq
, len
, c2h
->bt_info
.response_source
);
7327 case C2H_8723B_BT_INFO
:
7328 if (c2h
->bt_info
.response_source
>
7329 BT_INFO_SRC_8723B_BT_ACTIVE_SEND
)
7330 dev_dbg(dev
, "C2H_BT_INFO WiFi only firmware\n");
7332 dev_dbg(dev
, "C2H_BT_INFO BT/WiFi coexist firmware\n");
7334 if (c2h
->bt_info
.bt_has_reset
)
7335 dev_dbg(dev
, "BT has been reset\n");
7336 if (c2h
->bt_info
.tx_rx_mask
)
7337 dev_dbg(dev
, "BT TRx mask\n");
7340 case C2H_8723B_BT_MP_INFO
:
7341 dev_dbg(dev
, "C2H_MP_INFO ext ID %02x, status %02x\n",
7342 c2h
->bt_mp_info
.ext_id
, c2h
->bt_mp_info
.status
);
7345 dev_info(dev
, "Unhandled C2H event %02x\n", c2h
->id
);
7350 static void rtl8xxxu_rx_complete(struct urb
*urb
)
7352 struct rtl8xxxu_rx_urb
*rx_urb
=
7353 container_of(urb
, struct rtl8xxxu_rx_urb
, urb
);
7354 struct ieee80211_hw
*hw
= rx_urb
->hw
;
7355 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7356 struct sk_buff
*skb
= (struct sk_buff
*)urb
->context
;
7357 struct ieee80211_rx_status
*rx_status
= IEEE80211_SKB_RXCB(skb
);
7358 struct device
*dev
= &priv
->udev
->dev
;
7359 __le32
*_rx_desc_le
= (__le32
*)skb
->data
;
7360 u32
*_rx_desc
= (u32
*)skb
->data
;
7363 for (i
= 0; i
< (sizeof(struct rtl8xxxu_rx_desc
) / sizeof(u32
)); i
++)
7364 _rx_desc
[i
] = le32_to_cpu(_rx_desc_le
[i
]);
7366 skb_put(skb
, urb
->actual_length
);
7368 if (urb
->status
== 0) {
7369 memset(rx_status
, 0, sizeof(struct ieee80211_rx_status
));
7371 rx_type
= priv
->fops
->parse_rx_desc(priv
, skb
, rx_status
);
7373 rx_status
->freq
= hw
->conf
.chandef
.chan
->center_freq
;
7374 rx_status
->band
= hw
->conf
.chandef
.chan
->band
;
7376 if (rx_type
== RX_TYPE_DATA_PKT
)
7377 ieee80211_rx_irqsafe(hw
, skb
);
7379 rtl8723bu_handle_c2h(priv
, skb
);
7384 rx_urb
->urb
.context
= NULL
;
7385 rtl8xxxu_queue_rx_urb(priv
, rx_urb
);
7387 dev_dbg(dev
, "%s: status %i\n", __func__
, urb
->status
);
7398 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv
*priv
,
7399 struct rtl8xxxu_rx_urb
*rx_urb
)
7401 struct sk_buff
*skb
;
7405 skb_size
= sizeof(struct rtl8xxxu_rx_desc
) + RTL_RX_BUFFER_SIZE
;
7406 skb
= __netdev_alloc_skb(NULL
, skb_size
, GFP_KERNEL
);
7410 memset(skb
->data
, 0, sizeof(struct rtl8xxxu_rx_desc
));
7411 usb_fill_bulk_urb(&rx_urb
->urb
, priv
->udev
, priv
->pipe_in
, skb
->data
,
7412 skb_size
, rtl8xxxu_rx_complete
, skb
);
7413 usb_anchor_urb(&rx_urb
->urb
, &priv
->rx_anchor
);
7414 ret
= usb_submit_urb(&rx_urb
->urb
, GFP_ATOMIC
);
7416 usb_unanchor_urb(&rx_urb
->urb
);
7420 static void rtl8xxxu_int_complete(struct urb
*urb
)
7422 struct rtl8xxxu_priv
*priv
= (struct rtl8xxxu_priv
*)urb
->context
;
7423 struct device
*dev
= &priv
->udev
->dev
;
7426 dev_dbg(dev
, "%s: status %i\n", __func__
, urb
->status
);
7427 if (urb
->status
== 0) {
7428 usb_anchor_urb(urb
, &priv
->int_anchor
);
7429 ret
= usb_submit_urb(urb
, GFP_ATOMIC
);
7431 usb_unanchor_urb(urb
);
7433 dev_info(dev
, "%s: Error %i\n", __func__
, urb
->status
);
7438 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw
*hw
)
7440 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7445 urb
= usb_alloc_urb(0, GFP_KERNEL
);
7449 usb_fill_int_urb(urb
, priv
->udev
, priv
->pipe_interrupt
,
7450 priv
->int_buf
, USB_INTR_CONTENT_LENGTH
,
7451 rtl8xxxu_int_complete
, priv
, 1);
7452 usb_anchor_urb(urb
, &priv
->int_anchor
);
7453 ret
= usb_submit_urb(urb
, GFP_KERNEL
);
7455 usb_unanchor_urb(urb
);
7459 val32
= rtl8xxxu_read32(priv
, REG_USB_HIMR
);
7460 val32
|= USB_HIMR_CPWM
;
7461 rtl8xxxu_write32(priv
, REG_USB_HIMR
, val32
);
7467 static int rtl8xxxu_add_interface(struct ieee80211_hw
*hw
,
7468 struct ieee80211_vif
*vif
)
7470 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7474 switch (vif
->type
) {
7475 case NL80211_IFTYPE_STATION
:
7476 rtl8723a_stop_tx_beacon(priv
);
7478 val8
= rtl8xxxu_read8(priv
, REG_BEACON_CTRL
);
7479 val8
|= BEACON_ATIM
| BEACON_FUNCTION_ENABLE
|
7480 BEACON_DISABLE_TSF_UPDATE
;
7481 rtl8xxxu_write8(priv
, REG_BEACON_CTRL
, val8
);
7488 rtl8xxxu_set_linktype(priv
, vif
->type
);
7493 static void rtl8xxxu_remove_interface(struct ieee80211_hw
*hw
,
7494 struct ieee80211_vif
*vif
)
7496 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7498 dev_dbg(&priv
->udev
->dev
, "%s\n", __func__
);
7501 static int rtl8xxxu_config(struct ieee80211_hw
*hw
, u32 changed
)
7503 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7504 struct device
*dev
= &priv
->udev
->dev
;
7506 int ret
= 0, channel
;
7509 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_CHANNEL
)
7511 "%s: channel: %i (changed %08x chandef.width %02x)\n",
7512 __func__
, hw
->conf
.chandef
.chan
->hw_value
,
7513 changed
, hw
->conf
.chandef
.width
);
7515 if (changed
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
) {
7516 val16
= ((hw
->conf
.long_frame_max_tx_count
<<
7517 RETRY_LIMIT_LONG_SHIFT
) & RETRY_LIMIT_LONG_MASK
) |
7518 ((hw
->conf
.short_frame_max_tx_count
<<
7519 RETRY_LIMIT_SHORT_SHIFT
) & RETRY_LIMIT_SHORT_MASK
);
7520 rtl8xxxu_write16(priv
, REG_RETRY_LIMIT
, val16
);
7523 if (changed
& IEEE80211_CONF_CHANGE_CHANNEL
) {
7524 switch (hw
->conf
.chandef
.width
) {
7525 case NL80211_CHAN_WIDTH_20_NOHT
:
7526 case NL80211_CHAN_WIDTH_20
:
7529 case NL80211_CHAN_WIDTH_40
:
7537 channel
= hw
->conf
.chandef
.chan
->hw_value
;
7539 priv
->fops
->set_tx_power(priv
, channel
, ht40
);
7541 priv
->fops
->config_channel(hw
);
7548 static int rtl8xxxu_conf_tx(struct ieee80211_hw
*hw
,
7549 struct ieee80211_vif
*vif
, u16 queue
,
7550 const struct ieee80211_tx_queue_params
*param
)
7552 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7553 struct device
*dev
= &priv
->udev
->dev
;
7555 u8 aifs
, acm_ctrl
, acm_bit
;
7560 fls(param
->cw_min
) << EDCA_PARAM_ECW_MIN_SHIFT
|
7561 fls(param
->cw_max
) << EDCA_PARAM_ECW_MAX_SHIFT
|
7562 (u32
)param
->txop
<< EDCA_PARAM_TXOP_SHIFT
;
7564 acm_ctrl
= rtl8xxxu_read8(priv
, REG_ACM_HW_CTRL
);
7566 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
7567 __func__
, queue
, val32
, param
->acm
, acm_ctrl
);
7570 case IEEE80211_AC_VO
:
7571 acm_bit
= ACM_HW_CTRL_VO
;
7572 rtl8xxxu_write32(priv
, REG_EDCA_VO_PARAM
, val32
);
7574 case IEEE80211_AC_VI
:
7575 acm_bit
= ACM_HW_CTRL_VI
;
7576 rtl8xxxu_write32(priv
, REG_EDCA_VI_PARAM
, val32
);
7578 case IEEE80211_AC_BE
:
7579 acm_bit
= ACM_HW_CTRL_BE
;
7580 rtl8xxxu_write32(priv
, REG_EDCA_BE_PARAM
, val32
);
7582 case IEEE80211_AC_BK
:
7583 acm_bit
= ACM_HW_CTRL_BK
;
7584 rtl8xxxu_write32(priv
, REG_EDCA_BK_PARAM
, val32
);
7592 acm_ctrl
|= acm_bit
;
7594 acm_ctrl
&= ~acm_bit
;
7595 rtl8xxxu_write8(priv
, REG_ACM_HW_CTRL
, acm_ctrl
);
7600 static void rtl8xxxu_configure_filter(struct ieee80211_hw
*hw
,
7601 unsigned int changed_flags
,
7602 unsigned int *total_flags
, u64 multicast
)
7604 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7605 u32 rcr
= rtl8xxxu_read32(priv
, REG_RCR
);
7607 dev_dbg(&priv
->udev
->dev
, "%s: changed_flags %08x, total_flags %08x\n",
7608 __func__
, changed_flags
, *total_flags
);
7611 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
7614 if (*total_flags
& FIF_FCSFAIL
)
7615 rcr
|= RCR_ACCEPT_CRC32
;
7617 rcr
&= ~RCR_ACCEPT_CRC32
;
7620 * FIF_PLCPFAIL not supported?
7623 if (*total_flags
& FIF_BCN_PRBRESP_PROMISC
)
7624 rcr
&= ~RCR_CHECK_BSSID_BEACON
;
7626 rcr
|= RCR_CHECK_BSSID_BEACON
;
7628 if (*total_flags
& FIF_CONTROL
)
7629 rcr
|= RCR_ACCEPT_CTRL_FRAME
;
7631 rcr
&= ~RCR_ACCEPT_CTRL_FRAME
;
7633 if (*total_flags
& FIF_OTHER_BSS
) {
7634 rcr
|= RCR_ACCEPT_AP
;
7635 rcr
&= ~RCR_CHECK_BSSID_MATCH
;
7637 rcr
&= ~RCR_ACCEPT_AP
;
7638 rcr
|= RCR_CHECK_BSSID_MATCH
;
7641 if (*total_flags
& FIF_PSPOLL
)
7642 rcr
|= RCR_ACCEPT_PM
;
7644 rcr
&= ~RCR_ACCEPT_PM
;
7647 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
7650 rtl8xxxu_write32(priv
, REG_RCR
, rcr
);
7652 *total_flags
&= (FIF_ALLMULTI
| FIF_FCSFAIL
| FIF_BCN_PRBRESP_PROMISC
|
7653 FIF_CONTROL
| FIF_OTHER_BSS
| FIF_PSPOLL
|
7657 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw
*hw
, u32 rts
)
7665 static int rtl8xxxu_set_key(struct ieee80211_hw
*hw
, enum set_key_cmd cmd
,
7666 struct ieee80211_vif
*vif
,
7667 struct ieee80211_sta
*sta
,
7668 struct ieee80211_key_conf
*key
)
7670 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7671 struct device
*dev
= &priv
->udev
->dev
;
7672 u8 mac_addr
[ETH_ALEN
];
7676 int retval
= -EOPNOTSUPP
;
7678 dev_dbg(dev
, "%s: cmd %02x, cipher %08x, index %i\n",
7679 __func__
, cmd
, key
->cipher
, key
->keyidx
);
7681 if (vif
->type
!= NL80211_IFTYPE_STATION
)
7684 if (key
->keyidx
> 3)
7687 switch (key
->cipher
) {
7688 case WLAN_CIPHER_SUITE_WEP40
:
7689 case WLAN_CIPHER_SUITE_WEP104
:
7692 case WLAN_CIPHER_SUITE_CCMP
:
7693 key
->flags
|= IEEE80211_KEY_FLAG_SW_MGMT_TX
;
7695 case WLAN_CIPHER_SUITE_TKIP
:
7696 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_MMIC
;
7701 if (key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
) {
7702 dev_dbg(dev
, "%s: pairwise key\n", __func__
);
7703 ether_addr_copy(mac_addr
, sta
->addr
);
7705 dev_dbg(dev
, "%s: group key\n", __func__
);
7706 eth_broadcast_addr(mac_addr
);
7709 val16
= rtl8xxxu_read16(priv
, REG_CR
);
7710 val16
|= CR_SECURITY_ENABLE
;
7711 rtl8xxxu_write16(priv
, REG_CR
, val16
);
7713 val8
= SEC_CFG_TX_SEC_ENABLE
| SEC_CFG_TXBC_USE_DEFKEY
|
7714 SEC_CFG_RX_SEC_ENABLE
| SEC_CFG_RXBC_USE_DEFKEY
;
7715 val8
|= SEC_CFG_TX_USE_DEFKEY
| SEC_CFG_RX_USE_DEFKEY
;
7716 rtl8xxxu_write8(priv
, REG_SECURITY_CFG
, val8
);
7720 key
->hw_key_idx
= key
->keyidx
;
7721 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
7722 rtl8xxxu_cam_write(priv
, key
, mac_addr
);
7726 rtl8xxxu_write32(priv
, REG_CAM_WRITE
, 0x00000000);
7727 val32
= CAM_CMD_POLLING
| CAM_CMD_WRITE
|
7728 key
->keyidx
<< CAM_CMD_KEY_SHIFT
;
7729 rtl8xxxu_write32(priv
, REG_CAM_CMD
, val32
);
7733 dev_warn(dev
, "%s: Unsupported command %02x\n", __func__
, cmd
);
7740 rtl8xxxu_ampdu_action(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
7741 struct ieee80211_ampdu_params
*params
)
7743 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7744 struct device
*dev
= &priv
->udev
->dev
;
7745 u8 ampdu_factor
, ampdu_density
;
7746 struct ieee80211_sta
*sta
= params
->sta
;
7747 enum ieee80211_ampdu_mlme_action action
= params
->action
;
7750 case IEEE80211_AMPDU_TX_START
:
7751 dev_info(dev
, "%s: IEEE80211_AMPDU_TX_START\n", __func__
);
7752 ampdu_factor
= sta
->ht_cap
.ampdu_factor
;
7753 ampdu_density
= sta
->ht_cap
.ampdu_density
;
7754 rtl8xxxu_set_ampdu_factor(priv
, ampdu_factor
);
7755 rtl8xxxu_set_ampdu_min_space(priv
, ampdu_density
);
7757 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
7758 ampdu_factor
, ampdu_density
);
7760 case IEEE80211_AMPDU_TX_STOP_FLUSH
:
7761 dev_info(dev
, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__
);
7762 rtl8xxxu_set_ampdu_factor(priv
, 0);
7763 rtl8xxxu_set_ampdu_min_space(priv
, 0);
7765 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT
:
7766 dev_info(dev
, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
7768 rtl8xxxu_set_ampdu_factor(priv
, 0);
7769 rtl8xxxu_set_ampdu_min_space(priv
, 0);
7771 case IEEE80211_AMPDU_RX_START
:
7772 dev_info(dev
, "%s: IEEE80211_AMPDU_RX_START\n", __func__
);
7774 case IEEE80211_AMPDU_RX_STOP
:
7775 dev_info(dev
, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__
);
7783 static int rtl8xxxu_start(struct ieee80211_hw
*hw
)
7785 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7786 struct rtl8xxxu_rx_urb
*rx_urb
;
7787 struct rtl8xxxu_tx_urb
*tx_urb
;
7788 unsigned long flags
;
7793 init_usb_anchor(&priv
->rx_anchor
);
7794 init_usb_anchor(&priv
->tx_anchor
);
7795 init_usb_anchor(&priv
->int_anchor
);
7797 priv
->fops
->enable_rf(priv
);
7798 if (priv
->usb_interrupts
) {
7799 ret
= rtl8xxxu_submit_int_urb(hw
);
7804 for (i
= 0; i
< RTL8XXXU_TX_URBS
; i
++) {
7805 tx_urb
= kmalloc(sizeof(struct rtl8xxxu_tx_urb
), GFP_KERNEL
);
7812 usb_init_urb(&tx_urb
->urb
);
7813 INIT_LIST_HEAD(&tx_urb
->list
);
7815 list_add(&tx_urb
->list
, &priv
->tx_urb_free_list
);
7816 priv
->tx_urb_free_count
++;
7819 priv
->tx_stopped
= false;
7821 spin_lock_irqsave(&priv
->rx_urb_lock
, flags
);
7822 priv
->shutdown
= false;
7823 spin_unlock_irqrestore(&priv
->rx_urb_lock
, flags
);
7825 for (i
= 0; i
< RTL8XXXU_RX_URBS
; i
++) {
7826 rx_urb
= kmalloc(sizeof(struct rtl8xxxu_rx_urb
), GFP_KERNEL
);
7833 usb_init_urb(&rx_urb
->urb
);
7834 INIT_LIST_HEAD(&rx_urb
->list
);
7837 ret
= rtl8xxxu_submit_rx_urb(priv
, rx_urb
);
7841 * Accept all data and mgmt frames
7843 rtl8xxxu_write16(priv
, REG_RXFLTMAP2
, 0xffff);
7844 rtl8xxxu_write16(priv
, REG_RXFLTMAP0
, 0xffff);
7846 rtl8xxxu_write32(priv
, REG_OFDM0_XA_AGC_CORE1
, 0x6954341e);
7851 rtl8xxxu_free_tx_resources(priv
);
7853 * Disable all data and mgmt frames
7855 rtl8xxxu_write16(priv
, REG_RXFLTMAP2
, 0x0000);
7856 rtl8xxxu_write16(priv
, REG_RXFLTMAP0
, 0x0000);
7861 static void rtl8xxxu_stop(struct ieee80211_hw
*hw
)
7863 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7864 unsigned long flags
;
7866 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0xff);
7868 rtl8xxxu_write16(priv
, REG_RXFLTMAP0
, 0x0000);
7869 rtl8xxxu_write16(priv
, REG_RXFLTMAP2
, 0x0000);
7871 spin_lock_irqsave(&priv
->rx_urb_lock
, flags
);
7872 priv
->shutdown
= true;
7873 spin_unlock_irqrestore(&priv
->rx_urb_lock
, flags
);
7875 usb_kill_anchored_urbs(&priv
->rx_anchor
);
7876 usb_kill_anchored_urbs(&priv
->tx_anchor
);
7877 if (priv
->usb_interrupts
)
7878 usb_kill_anchored_urbs(&priv
->int_anchor
);
7880 rtl8723a_disable_rf(priv
);
7883 * Disable interrupts
7885 if (priv
->usb_interrupts
)
7886 rtl8xxxu_write32(priv
, REG_USB_HIMR
, 0);
7888 rtl8xxxu_free_rx_resources(priv
);
7889 rtl8xxxu_free_tx_resources(priv
);
7892 static const struct ieee80211_ops rtl8xxxu_ops
= {
7894 .add_interface
= rtl8xxxu_add_interface
,
7895 .remove_interface
= rtl8xxxu_remove_interface
,
7896 .config
= rtl8xxxu_config
,
7897 .conf_tx
= rtl8xxxu_conf_tx
,
7898 .bss_info_changed
= rtl8xxxu_bss_info_changed
,
7899 .configure_filter
= rtl8xxxu_configure_filter
,
7900 .set_rts_threshold
= rtl8xxxu_set_rts_threshold
,
7901 .start
= rtl8xxxu_start
,
7902 .stop
= rtl8xxxu_stop
,
7903 .sw_scan_start
= rtl8xxxu_sw_scan_start
,
7904 .sw_scan_complete
= rtl8xxxu_sw_scan_complete
,
7905 .set_key
= rtl8xxxu_set_key
,
7906 .ampdu_action
= rtl8xxxu_ampdu_action
,
7909 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv
*priv
,
7910 struct usb_interface
*interface
)
7912 struct usb_interface_descriptor
*interface_desc
;
7913 struct usb_host_interface
*host_interface
;
7914 struct usb_endpoint_descriptor
*endpoint
;
7915 struct device
*dev
= &priv
->udev
->dev
;
7916 int i
, j
= 0, endpoints
;
7920 host_interface
= &interface
->altsetting
[0];
7921 interface_desc
= &host_interface
->desc
;
7922 endpoints
= interface_desc
->bNumEndpoints
;
7924 for (i
= 0; i
< endpoints
; i
++) {
7925 endpoint
= &host_interface
->endpoint
[i
].desc
;
7927 dir
= endpoint
->bEndpointAddress
& USB_ENDPOINT_DIR_MASK
;
7928 num
= usb_endpoint_num(endpoint
);
7929 xtype
= usb_endpoint_type(endpoint
);
7930 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_USB
)
7932 "%s: endpoint: dir %02x, # %02x, type %02x\n",
7933 __func__
, dir
, num
, xtype
);
7934 if (usb_endpoint_dir_in(endpoint
) &&
7935 usb_endpoint_xfer_bulk(endpoint
)) {
7936 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_USB
)
7937 dev_dbg(dev
, "%s: in endpoint num %i\n",
7940 if (priv
->pipe_in
) {
7942 "%s: Too many IN pipes\n", __func__
);
7947 priv
->pipe_in
= usb_rcvbulkpipe(priv
->udev
, num
);
7950 if (usb_endpoint_dir_in(endpoint
) &&
7951 usb_endpoint_xfer_int(endpoint
)) {
7952 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_USB
)
7953 dev_dbg(dev
, "%s: interrupt endpoint num %i\n",
7956 if (priv
->pipe_interrupt
) {
7957 dev_warn(dev
, "%s: Too many INTERRUPT pipes\n",
7963 priv
->pipe_interrupt
= usb_rcvintpipe(priv
->udev
, num
);
7966 if (usb_endpoint_dir_out(endpoint
) &&
7967 usb_endpoint_xfer_bulk(endpoint
)) {
7968 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_USB
)
7969 dev_dbg(dev
, "%s: out endpoint num %i\n",
7971 if (j
>= RTL8XXXU_OUT_ENDPOINTS
) {
7973 "%s: Too many OUT pipes\n", __func__
);
7977 priv
->out_ep
[j
++] = num
;
7981 priv
->nr_out_eps
= j
;
7985 static int rtl8xxxu_probe(struct usb_interface
*interface
,
7986 const struct usb_device_id
*id
)
7988 struct rtl8xxxu_priv
*priv
;
7989 struct ieee80211_hw
*hw
;
7990 struct usb_device
*udev
;
7991 struct ieee80211_supported_band
*sband
;
7995 udev
= usb_get_dev(interface_to_usbdev(interface
));
7997 switch (id
->idVendor
) {
7998 case USB_VENDOR_ID_REALTEK
:
7999 switch(id
->idProduct
) {
8009 if (id
->idProduct
== 0x7811)
8017 rtl8xxxu_debug
|= RTL8XXXU_DEBUG_EFUSE
;
8018 dev_info(&udev
->dev
,
8019 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
8020 id
->idVendor
, id
->idProduct
);
8021 dev_info(&udev
->dev
,
8022 "Please report results to Jes.Sorensen@gmail.com\n");
8025 hw
= ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv
), &rtl8xxxu_ops
);
8034 priv
->fops
= (struct rtl8xxxu_fileops
*)id
->driver_info
;
8035 mutex_init(&priv
->usb_buf_mutex
);
8036 mutex_init(&priv
->h2c_mutex
);
8037 INIT_LIST_HEAD(&priv
->tx_urb_free_list
);
8038 spin_lock_init(&priv
->tx_urb_lock
);
8039 INIT_LIST_HEAD(&priv
->rx_urb_pending_list
);
8040 spin_lock_init(&priv
->rx_urb_lock
);
8041 INIT_WORK(&priv
->rx_urb_wq
, rtl8xxxu_rx_urb_work
);
8043 usb_set_intfdata(interface
, hw
);
8045 ret
= rtl8xxxu_parse_usb(priv
, interface
);
8049 ret
= rtl8xxxu_identify_chip(priv
);
8051 dev_err(&udev
->dev
, "Fatal - failed to identify chip\n");
8055 ret
= rtl8xxxu_read_efuse(priv
);
8057 dev_err(&udev
->dev
, "Fatal - failed to read EFuse\n");
8061 ret
= priv
->fops
->parse_efuse(priv
);
8063 dev_err(&udev
->dev
, "Fatal - failed to parse EFuse\n");
8067 rtl8xxxu_print_chipinfo(priv
);
8069 ret
= priv
->fops
->load_firmware(priv
);
8071 dev_err(&udev
->dev
, "Fatal - failed to load firmware\n");
8075 ret
= rtl8xxxu_init_device(hw
);
8077 hw
->wiphy
->max_scan_ssids
= 1;
8078 hw
->wiphy
->max_scan_ie_len
= IEEE80211_MAX_DATA_LEN
;
8079 hw
->wiphy
->interface_modes
= BIT(NL80211_IFTYPE_STATION
);
8082 sband
= &rtl8xxxu_supported_band
;
8083 sband
->ht_cap
.ht_supported
= true;
8084 sband
->ht_cap
.ampdu_factor
= IEEE80211_HT_MAX_AMPDU_64K
;
8085 sband
->ht_cap
.ampdu_density
= IEEE80211_HT_MPDU_DENSITY_16
;
8086 sband
->ht_cap
.cap
= IEEE80211_HT_CAP_SGI_20
| IEEE80211_HT_CAP_SGI_40
;
8087 memset(&sband
->ht_cap
.mcs
, 0, sizeof(sband
->ht_cap
.mcs
));
8088 sband
->ht_cap
.mcs
.rx_mask
[0] = 0xff;
8089 sband
->ht_cap
.mcs
.rx_mask
[4] = 0x01;
8090 if (priv
->rf_paths
> 1) {
8091 sband
->ht_cap
.mcs
.rx_mask
[1] = 0xff;
8092 sband
->ht_cap
.cap
|= IEEE80211_HT_CAP_SGI_40
;
8094 sband
->ht_cap
.mcs
.tx_params
= IEEE80211_HT_MCS_TX_DEFINED
;
8096 * Some APs will negotiate HT20_40 in a noisy environment leading
8097 * to miserable performance. Rather than defaulting to this, only
8098 * enable it if explicitly requested at module load time.
8100 if (rtl8xxxu_ht40_2g
) {
8101 dev_info(&udev
->dev
, "Enabling HT_20_40 on the 2.4GHz band\n");
8102 sband
->ht_cap
.cap
|= IEEE80211_HT_CAP_SUP_WIDTH_20_40
;
8104 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
8106 hw
->wiphy
->rts_threshold
= 2347;
8108 SET_IEEE80211_DEV(priv
->hw
, &interface
->dev
);
8109 SET_IEEE80211_PERM_ADDR(hw
, priv
->mac_addr
);
8111 hw
->extra_tx_headroom
= priv
->fops
->tx_desc_size
;
8112 ieee80211_hw_set(hw
, SIGNAL_DBM
);
8114 * The firmware handles rate control
8116 ieee80211_hw_set(hw
, HAS_RATE_CONTROL
);
8117 ieee80211_hw_set(hw
, AMPDU_AGGREGATION
);
8119 ret
= ieee80211_register_hw(priv
->hw
);
8121 dev_err(&udev
->dev
, "%s: Failed to register: %i\n",
8132 static void rtl8xxxu_disconnect(struct usb_interface
*interface
)
8134 struct rtl8xxxu_priv
*priv
;
8135 struct ieee80211_hw
*hw
;
8137 hw
= usb_get_intfdata(interface
);
8140 rtl8xxxu_disable_device(hw
);
8141 usb_set_intfdata(interface
, NULL
);
8143 dev_info(&priv
->udev
->dev
, "disconnecting\n");
8145 ieee80211_unregister_hw(hw
);
8147 kfree(priv
->fw_data
);
8148 mutex_destroy(&priv
->usb_buf_mutex
);
8149 mutex_destroy(&priv
->h2c_mutex
);
8151 usb_put_dev(priv
->udev
);
8152 ieee80211_free_hw(hw
);
8155 static struct rtl8xxxu_fileops rtl8723au_fops
= {
8156 .parse_efuse
= rtl8723au_parse_efuse
,
8157 .load_firmware
= rtl8723au_load_firmware
,
8158 .power_on
= rtl8723au_power_on
,
8159 .llt_init
= rtl8xxxu_init_llt_table
,
8160 .phy_iq_calibrate
= rtl8723au_phy_iq_calibrate
,
8161 .config_channel
= rtl8723au_config_channel
,
8162 .parse_rx_desc
= rtl8723au_parse_rx_desc
,
8163 .enable_rf
= rtl8723a_enable_rf
,
8164 .set_tx_power
= rtl8723a_set_tx_power
,
8165 .writeN_block_size
= 1024,
8166 .mbox_ext_reg
= REG_HMBOX_EXT_0
,
8167 .mbox_ext_width
= 2,
8168 .tx_desc_size
= sizeof(struct rtl8723au_tx_desc
),
8169 .adda_1t_init
= 0x0b1b25a0,
8170 .adda_1t_path_on
= 0x0bdb25a0,
8171 .adda_2t_path_on_a
= 0x04db25a4,
8172 .adda_2t_path_on_b
= 0x0b1b25a4,
8175 static struct rtl8xxxu_fileops rtl8723bu_fops
= {
8176 .parse_efuse
= rtl8723bu_parse_efuse
,
8177 .load_firmware
= rtl8723bu_load_firmware
,
8178 .power_on
= rtl8723bu_power_on
,
8179 .llt_init
= rtl8xxxu_auto_llt_table
,
8180 .phy_init_antenna_selection
= rtl8723bu_phy_init_antenna_selection
,
8181 .phy_iq_calibrate
= rtl8723bu_phy_iq_calibrate
,
8182 .config_channel
= rtl8723bu_config_channel
,
8183 .init_bt
= rtl8723bu_init_bt
,
8184 .parse_rx_desc
= rtl8723bu_parse_rx_desc
,
8185 .init_aggregation
= rtl8723bu_init_aggregation
,
8186 .init_statistics
= rtl8723bu_init_statistics
,
8187 .enable_rf
= rtl8723b_enable_rf
,
8188 .set_tx_power
= rtl8723b_set_tx_power
,
8189 .writeN_block_size
= 1024,
8190 .mbox_ext_reg
= REG_HMBOX_EXT0_8723B
,
8191 .mbox_ext_width
= 4,
8192 .tx_desc_size
= sizeof(struct rtl8723bu_tx_desc
),
8194 .adda_1t_init
= 0x01c00014,
8195 .adda_1t_path_on
= 0x01c00014,
8196 .adda_2t_path_on_a
= 0x01c00014,
8197 .adda_2t_path_on_b
= 0x01c00014,
8200 #ifdef CONFIG_RTL8XXXU_UNTESTED
8202 static struct rtl8xxxu_fileops rtl8192cu_fops
= {
8203 .parse_efuse
= rtl8192cu_parse_efuse
,
8204 .load_firmware
= rtl8192cu_load_firmware
,
8205 .power_on
= rtl8192cu_power_on
,
8206 .llt_init
= rtl8xxxu_init_llt_table
,
8207 .phy_iq_calibrate
= rtl8723au_phy_iq_calibrate
,
8208 .config_channel
= rtl8723au_config_channel
,
8209 .parse_rx_desc
= rtl8723au_parse_rx_desc
,
8210 .enable_rf
= rtl8723a_enable_rf
,
8211 .set_tx_power
= rtl8723a_set_tx_power
,
8212 .writeN_block_size
= 128,
8213 .mbox_ext_reg
= REG_HMBOX_EXT_0
,
8214 .mbox_ext_width
= 2,
8215 .tx_desc_size
= sizeof(struct rtl8723au_tx_desc
),
8216 .adda_1t_init
= 0x0b1b25a0,
8217 .adda_1t_path_on
= 0x0bdb25a0,
8218 .adda_2t_path_on_a
= 0x04db25a4,
8219 .adda_2t_path_on_b
= 0x0b1b25a4,
8224 static struct rtl8xxxu_fileops rtl8192eu_fops
= {
8225 .parse_efuse
= rtl8192eu_parse_efuse
,
8226 .load_firmware
= rtl8192eu_load_firmware
,
8227 .power_on
= rtl8192eu_power_on
,
8228 .llt_init
= rtl8xxxu_auto_llt_table
,
8229 .phy_iq_calibrate
= rtl8723bu_phy_iq_calibrate
,
8230 .config_channel
= rtl8723bu_config_channel
,
8231 .parse_rx_desc
= rtl8723bu_parse_rx_desc
,
8232 .enable_rf
= rtl8723b_enable_rf
,
8233 .set_tx_power
= rtl8723b_set_tx_power
,
8234 .writeN_block_size
= 128,
8235 .mbox_ext_reg
= REG_HMBOX_EXT0_8723B
,
8236 .mbox_ext_width
= 4,
8237 .tx_desc_size
= sizeof(struct rtl8723au_tx_desc
),
8239 .adda_1t_init
= 0x0fc01616,
8240 .adda_1t_path_on
= 0x0fc01616,
8241 .adda_2t_path_on_a
= 0x0fc01616,
8242 .adda_2t_path_on_b
= 0x0fc01616,
8245 static struct usb_device_id dev_table
[] = {
8246 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x8724, 0xff, 0xff, 0xff),
8247 .driver_info
= (unsigned long)&rtl8723au_fops
},
8248 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x1724, 0xff, 0xff, 0xff),
8249 .driver_info
= (unsigned long)&rtl8723au_fops
},
8250 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x0724, 0xff, 0xff, 0xff),
8251 .driver_info
= (unsigned long)&rtl8723au_fops
},
8252 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x818b, 0xff, 0xff, 0xff),
8253 .driver_info
= (unsigned long)&rtl8192eu_fops
},
8254 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0xb720, 0xff, 0xff, 0xff),
8255 .driver_info
= (unsigned long)&rtl8723bu_fops
},
8256 #ifdef CONFIG_RTL8XXXU_UNTESTED
8257 /* Still supported by rtlwifi */
8258 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x8176, 0xff, 0xff, 0xff),
8259 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8260 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x8178, 0xff, 0xff, 0xff),
8261 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8262 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x817f, 0xff, 0xff, 0xff),
8263 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8264 /* Tested by Larry Finger */
8265 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
8266 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8267 /* Currently untested 8188 series devices */
8268 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x8191, 0xff, 0xff, 0xff),
8269 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8270 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x8170, 0xff, 0xff, 0xff),
8271 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8272 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x8177, 0xff, 0xff, 0xff),
8273 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8274 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x817a, 0xff, 0xff, 0xff),
8275 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8276 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x817b, 0xff, 0xff, 0xff),
8277 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8278 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x817d, 0xff, 0xff, 0xff),
8279 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8280 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x817e, 0xff, 0xff, 0xff),
8281 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8282 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x818a, 0xff, 0xff, 0xff),
8283 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8284 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x317f, 0xff, 0xff, 0xff),
8285 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8286 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
8287 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8288 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
8289 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8290 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
8291 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8292 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
8293 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8294 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
8295 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8296 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
8297 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8298 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
8299 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8300 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x1e1e, 0xff, 0xff, 0xff),
8301 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8302 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x5088, 0xff, 0xff, 0xff),
8303 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8304 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
8305 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8306 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
8307 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8308 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
8309 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8310 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
8311 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8312 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
8313 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8314 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
8315 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8316 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
8317 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8318 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
8319 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8320 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
8321 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8322 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
8323 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8324 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
8325 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8326 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
8327 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8328 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
8329 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8330 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
8331 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8332 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
8333 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8334 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
8335 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8336 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
8337 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8338 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
8339 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8340 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
8341 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8342 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
8343 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8344 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
8345 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8346 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
8347 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8348 /* Currently untested 8192 series devices */
8349 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
8350 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8351 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
8352 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8353 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
8354 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8355 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
8356 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8357 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
8358 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8359 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
8360 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8361 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
8362 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8363 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
8364 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8365 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
8366 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8367 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
8368 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8369 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
8370 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8371 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
8372 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8373 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
8374 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8375 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
8376 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8377 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x2e2e, 0xff, 0xff, 0xff),
8378 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8379 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
8380 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8381 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
8382 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8383 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
8384 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8385 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
8386 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8387 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
8388 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8389 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
8390 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8391 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
8392 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8393 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
8394 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8395 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
8396 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8397 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
8398 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8403 static struct usb_driver rtl8xxxu_driver
= {
8404 .name
= DRIVER_NAME
,
8405 .probe
= rtl8xxxu_probe
,
8406 .disconnect
= rtl8xxxu_disconnect
,
8407 .id_table
= dev_table
,
8408 .disable_hub_initiated_lpm
= 1,
8411 static int __init
rtl8xxxu_module_init(void)
8415 res
= usb_register(&rtl8xxxu_driver
);
8417 pr_err(DRIVER_NAME
": usb_register() failed (%i)\n", res
);
8422 static void __exit
rtl8xxxu_module_exit(void)
8424 usb_deregister(&rtl8xxxu_driver
);
8428 MODULE_DEVICE_TABLE(usb
, dev_table
);
8430 module_init(rtl8xxxu_module_init
);
8431 module_exit(rtl8xxxu_module_exit
);