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net: cdc_ncm: update datagram size after changing mtu
[deliverable/linux.git] / drivers / net / wireless / realtek / rtl8xxxu / rtl8xxxu.h
1 /*
2 * Copyright (c) 2014 - 2016 Jes Sorensen <Jes.Sorensen@redhat.com>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * Register definitions taken from original Realtek rtl8723au driver
14 */
15
16 #include <asm/byteorder.h>
17
18 #define RTL8XXXU_DEBUG_REG_WRITE 0x01
19 #define RTL8XXXU_DEBUG_REG_READ 0x02
20 #define RTL8XXXU_DEBUG_RFREG_WRITE 0x04
21 #define RTL8XXXU_DEBUG_RFREG_READ 0x08
22 #define RTL8XXXU_DEBUG_CHANNEL 0x10
23 #define RTL8XXXU_DEBUG_TX 0x20
24 #define RTL8XXXU_DEBUG_TX_DUMP 0x40
25 #define RTL8XXXU_DEBUG_RX 0x80
26 #define RTL8XXXU_DEBUG_RX_DUMP 0x100
27 #define RTL8XXXU_DEBUG_USB 0x200
28 #define RTL8XXXU_DEBUG_KEY 0x400
29 #define RTL8XXXU_DEBUG_H2C 0x800
30 #define RTL8XXXU_DEBUG_ACTION 0x1000
31 #define RTL8XXXU_DEBUG_EFUSE 0x2000
32
33 #define RTW_USB_CONTROL_MSG_TIMEOUT 500
34 #define RTL8XXXU_MAX_REG_POLL 500
35 #define USB_INTR_CONTENT_LENGTH 56
36
37 #define RTL8XXXU_OUT_ENDPOINTS 4
38
39 #define REALTEK_USB_READ 0xc0
40 #define REALTEK_USB_WRITE 0x40
41 #define REALTEK_USB_CMD_REQ 0x05
42 #define REALTEK_USB_CMD_IDX 0x00
43
44 #define TX_TOTAL_PAGE_NUM 0xf8
45 #define TX_TOTAL_PAGE_NUM_8192E 0xf3
46 /* (HPQ + LPQ + NPQ + PUBQ) = TX_TOTAL_PAGE_NUM */
47 #define TX_PAGE_NUM_PUBQ 0xe7
48 #define TX_PAGE_NUM_HI_PQ 0x0c
49 #define TX_PAGE_NUM_LO_PQ 0x02
50 #define TX_PAGE_NUM_NORM_PQ 0x02
51
52 #define TX_PAGE_NUM_PUBQ_8192E 0xe7
53 #define TX_PAGE_NUM_HI_PQ_8192E 0x08
54 #define TX_PAGE_NUM_LO_PQ_8192E 0x0c
55 #define TX_PAGE_NUM_NORM_PQ_8192E 0x00
56
57 #define RTL_FW_PAGE_SIZE 4096
58 #define RTL8XXXU_FIRMWARE_POLL_MAX 1000
59
60 #define RTL8723A_CHANNEL_GROUPS 3
61 #define RTL8723A_MAX_RF_PATHS 2
62 #define RTL8723B_CHANNEL_GROUPS 6
63 #define RTL8723B_TX_COUNT 4
64 #define RTL8723B_MAX_RF_PATHS 4
65 #define RTL8XXXU_MAX_CHANNEL_GROUPS 6
66 #define RF6052_MAX_TX_PWR 0x3f
67
68 #define EFUSE_MAP_LEN 512
69 #define EFUSE_MAX_SECTION_8723A 64
70 #define EFUSE_REAL_CONTENT_LEN_8723A 512
71 #define EFUSE_BT_MAP_LEN_8723A 1024
72 #define EFUSE_MAX_WORD_UNIT 4
73
74 enum rtl8xxxu_rtl_chip {
75 RTL8192S = 0x81920,
76 RTL8191S = 0x81910,
77 RTL8192C = 0x8192c,
78 RTL8191C = 0x8191c,
79 RTL8188C = 0x8188c,
80 RTL8188R = 0x81889,
81 RTL8192D = 0x8192d,
82 RTL8723A = 0x8723a,
83 RTL8188E = 0x8188e,
84 RTL8812 = 0x88120,
85 RTL8821 = 0x88210,
86 RTL8192E = 0x8192e,
87 RTL8191E = 0x8191e,
88 RTL8723B = 0x8723b,
89 RTL8814A = 0x8814a,
90 RTL8881A = 0x8881a,
91 RTL8821B = 0x8821b,
92 RTL8822B = 0x8822b,
93 RTL8703B = 0x8703b,
94 RTL8195A = 0x8195a,
95 RTL8188F = 0x8188f
96 };
97
98 enum rtl8xxxu_rx_type {
99 RX_TYPE_DATA_PKT = 0,
100 RX_TYPE_C2H = 1,
101 RX_TYPE_ERROR = -1
102 };
103
104 struct rtl8xxxu_rxdesc16 {
105 #ifdef __LITTLE_ENDIAN
106 u32 pktlen:14;
107 u32 crc32:1;
108 u32 icverr:1;
109 u32 drvinfo_sz:4;
110 u32 security:3;
111 u32 qos:1;
112 u32 shift:2;
113 u32 phy_stats:1;
114 u32 swdec:1;
115 u32 ls:1;
116 u32 fs:1;
117 u32 eor:1;
118 u32 own:1;
119
120 u32 macid:5;
121 u32 tid:4;
122 u32 hwrsvd:4;
123 u32 amsdu:1;
124 u32 paggr:1;
125 u32 faggr:1;
126 u32 a1fit:4;
127 u32 a2fit:4;
128 u32 pam:1;
129 u32 pwr:1;
130 u32 md:1;
131 u32 mf:1;
132 u32 type:2;
133 u32 mc:1;
134 u32 bc:1;
135
136 u32 seq:12;
137 u32 frag:4;
138 u32 nextpktlen:14;
139 u32 nextind:1;
140 u32 reserved0:1;
141
142 u32 rxmcs:6;
143 u32 rxht:1;
144 u32 gf:1;
145 u32 splcp:1;
146 u32 bw:1;
147 u32 htc:1;
148 u32 eosp:1;
149 u32 bssidfit:2;
150 u32 reserved1:16;
151 u32 unicastwake:1;
152 u32 magicwake:1;
153
154 u32 pattern0match:1;
155 u32 pattern1match:1;
156 u32 pattern2match:1;
157 u32 pattern3match:1;
158 u32 pattern4match:1;
159 u32 pattern5match:1;
160 u32 pattern6match:1;
161 u32 pattern7match:1;
162 u32 pattern8match:1;
163 u32 pattern9match:1;
164 u32 patternamatch:1;
165 u32 patternbmatch:1;
166 u32 patterncmatch:1;
167 u32 reserved2:19;
168 #else
169 u32 own:1;
170 u32 eor:1;
171 u32 fs:1;
172 u32 ls:1;
173 u32 swdec:1;
174 u32 phy_stats:1;
175 u32 shift:2;
176 u32 qos:1;
177 u32 security:3;
178 u32 drvinfo_sz:4;
179 u32 icverr:1;
180 u32 crc32:1;
181 u32 pktlen:14;
182
183 u32 bc:1;
184 u32 mc:1;
185 u32 type:2;
186 u32 mf:1;
187 u32 md:1;
188 u32 pwr:1;
189 u32 pam:1;
190 u32 a2fit:4;
191 u32 a1fit:4;
192 u32 faggr:1;
193 u32 paggr:1;
194 u32 amsdu:1;
195 u32 hwrsvd:4;
196 u32 tid:4;
197 u32 macid:5;
198
199 u32 reserved0:1;
200 u32 nextind:1;
201 u32 nextpktlen:14;
202 u32 frag:4;
203 u32 seq:12;
204
205 u32 magicwake:1;
206 u32 unicastwake:1;
207 u32 reserved1:16;
208 u32 bssidfit:2;
209 u32 eosp:1;
210 u32 htc:1;
211 u32 bw:1;
212 u32 splcp:1;
213 u32 gf:1;
214 u32 rxht:1;
215 u32 rxmcs:6;
216
217 u32 reserved2:19;
218 u32 patterncmatch:1;
219 u32 patternbmatch:1;
220 u32 patternamatch:1;
221 u32 pattern9match:1;
222 u32 pattern8match:1;
223 u32 pattern7match:1;
224 u32 pattern6match:1;
225 u32 pattern5match:1;
226 u32 pattern4match:1;
227 u32 pattern3match:1;
228 u32 pattern2match:1;
229 u32 pattern1match:1;
230 u32 pattern0match:1;
231 #endif
232 __le32 tsfl;
233 #if 0
234 u32 bassn:12;
235 u32 bavld:1;
236 u32 reserved3:19;
237 #endif
238 };
239
240 struct rtl8xxxu_rxdesc24 {
241 #ifdef __LITTLE_ENDIAN
242 u32 pktlen:14;
243 u32 crc32:1;
244 u32 icverr:1;
245 u32 drvinfo_sz:4;
246 u32 security:3;
247 u32 qos:1;
248 u32 shift:2;
249 u32 phy_stats:1;
250 u32 swdec:1;
251 u32 ls:1;
252 u32 fs:1;
253 u32 eor:1;
254 u32 own:1;
255
256 u32 macid:7;
257 u32 dummy1_0:1;
258 u32 tid:4;
259 u32 dummy1_1:1;
260 u32 amsdu:1;
261 u32 rxid_match:1;
262 u32 paggr:1;
263 u32 a1fit:4; /* 16 */
264 u32 chkerr:1;
265 u32 ipver:1;
266 u32 tcpudp:1;
267 u32 chkvld:1;
268 u32 pam:1;
269 u32 pwr:1;
270 u32 more_data:1;
271 u32 more_frag:1;
272 u32 type:2;
273 u32 mc:1;
274 u32 bc:1;
275
276 u32 seq:12;
277 u32 frag:4;
278 u32 rx_is_qos:1; /* 16 */
279 u32 dummy2_0:1;
280 u32 wlanhd_iv_len:6;
281 u32 dummy2_1:4;
282 u32 rpt_sel:1;
283 u32 dummy2_2:3;
284
285 u32 rxmcs:7;
286 u32 dummy3_0:3;
287 u32 htc:1;
288 u32 eosp:1;
289 u32 bssidfit:2;
290 u32 dummy3_1:2;
291 u32 usb_agg_pktnum:8; /* 16 */
292 u32 dummy3_2:5;
293 u32 pattern_match:1;
294 u32 unicast_match:1;
295 u32 magic_match:1;
296
297 u32 splcp:1;
298 u32 ldcp:1;
299 u32 stbc:1;
300 u32 dummy4_0:1;
301 u32 bw:2;
302 u32 dummy4_1:26;
303 #else
304 u32 own:1;
305 u32 eor:1;
306 u32 fs:1;
307 u32 ls:1;
308 u32 swdec:1;
309 u32 phy_stats:1;
310 u32 shift:2;
311 u32 qos:1;
312 u32 security:3;
313 u32 drvinfo_sz:4;
314 u32 icverr:1;
315 u32 crc32:1;
316 u32 pktlen:14;
317
318 u32 bc:1;
319 u32 mc:1;
320 u32 type:2;
321 u32 mf:1;
322 u32 md:1;
323 u32 pwr:1;
324 u32 pam:1;
325 u32 a2fit:4;
326 u32 a1fit:4;
327 u32 faggr:1;
328 u32 paggr:1;
329 u32 amsdu:1;
330 u32 hwrsvd:4;
331 u32 tid:4;
332 u32 macid:5;
333
334 u32 dummy2_2:3;
335 u32 rpt_sel:1;
336 u32 dummy2_1:4;
337 u32 wlanhd_iv_len:6;
338 u32 dummy2_0:1;
339 u32 rx_is_qos:1;
340 u32 frag:4; /* 16 */
341 u32 seq:12;
342
343 u32 magic_match:1;
344 u32 unicast_match:1;
345 u32 pattern_match:1;
346 u32 dummy3_2:5;
347 u32 usb_agg_pktnum:8;
348 u32 dummy3_1:2; /* 16 */
349 u32 bssidfit:2;
350 u32 eosp:1;
351 u32 htc:1;
352 u32 dummy3_0:3;
353 u32 rxmcs:7;
354
355 u32 dumm4_1:26;
356 u32 bw:2;
357 u32 dummy4_0:1;
358 u32 stbc:1;
359 u32 ldcp:1;
360 u32 splcp:1;
361 #endif
362 __le32 tsfl;
363 };
364
365 struct rtl8xxxu_txdesc32 {
366 __le16 pkt_size;
367 u8 pkt_offset;
368 u8 txdw0;
369 __le32 txdw1;
370 __le32 txdw2;
371 __le32 txdw3;
372 __le32 txdw4;
373 __le32 txdw5;
374 __le32 txdw6;
375 __le16 csum;
376 __le16 txdw7;
377 };
378
379 struct rtl8xxxu_txdesc40 {
380 __le16 pkt_size;
381 u8 pkt_offset;
382 u8 txdw0;
383 __le32 txdw1;
384 __le32 txdw2;
385 __le32 txdw3;
386 __le32 txdw4;
387 __le32 txdw5;
388 __le32 txdw6;
389 __le16 csum;
390 __le16 txdw7;
391 __le32 txdw8;
392 __le32 txdw9;
393 };
394
395 /* CCK Rates, TxHT = 0 */
396 #define DESC_RATE_1M 0x00
397 #define DESC_RATE_2M 0x01
398 #define DESC_RATE_5_5M 0x02
399 #define DESC_RATE_11M 0x03
400
401 /* OFDM Rates, TxHT = 0 */
402 #define DESC_RATE_6M 0x04
403 #define DESC_RATE_9M 0x05
404 #define DESC_RATE_12M 0x06
405 #define DESC_RATE_18M 0x07
406 #define DESC_RATE_24M 0x08
407 #define DESC_RATE_36M 0x09
408 #define DESC_RATE_48M 0x0a
409 #define DESC_RATE_54M 0x0b
410
411 /* MCS Rates, TxHT = 1 */
412 #define DESC_RATE_MCS0 0x0c
413 #define DESC_RATE_MCS1 0x0d
414 #define DESC_RATE_MCS2 0x0e
415 #define DESC_RATE_MCS3 0x0f
416 #define DESC_RATE_MCS4 0x10
417 #define DESC_RATE_MCS5 0x11
418 #define DESC_RATE_MCS6 0x12
419 #define DESC_RATE_MCS7 0x13
420 #define DESC_RATE_MCS8 0x14
421 #define DESC_RATE_MCS9 0x15
422 #define DESC_RATE_MCS10 0x16
423 #define DESC_RATE_MCS11 0x17
424 #define DESC_RATE_MCS12 0x18
425 #define DESC_RATE_MCS13 0x19
426 #define DESC_RATE_MCS14 0x1a
427 #define DESC_RATE_MCS15 0x1b
428 #define DESC_RATE_MCS15_SG 0x1c
429 #define DESC_RATE_MCS32 0x20
430
431 #define TXDESC_OFFSET_SZ 0
432 #define TXDESC_OFFSET_SHT 16
433 #if 0
434 #define TXDESC_BMC BIT(24)
435 #define TXDESC_LSG BIT(26)
436 #define TXDESC_FSG BIT(27)
437 #define TXDESC_OWN BIT(31)
438 #else
439 #define TXDESC_BROADMULTICAST BIT(0)
440 #define TXDESC_HTC BIT(1)
441 #define TXDESC_LAST_SEGMENT BIT(2)
442 #define TXDESC_FIRST_SEGMENT BIT(3)
443 #define TXDESC_LINIP BIT(4)
444 #define TXDESC_NO_ACM BIT(5)
445 #define TXDESC_GF BIT(6)
446 #define TXDESC_OWN BIT(7)
447 #endif
448
449 /* Word 1 */
450 /*
451 * Bits 0-7 differ dependent on chip generation. For 8723au bits 5/6 are
452 * aggregation enable and break respectively. For 8723bu, bits 0-7 are macid.
453 */
454 #define TXDESC_PKT_OFFSET_SZ 0
455 #define TXDESC32_AGG_ENABLE BIT(5)
456 #define TXDESC32_AGG_BREAK BIT(6)
457 #define TXDESC40_MACID_SHIFT 0
458 #define TXDESC40_MACID_MASK 0x00f0
459 #define TXDESC_QUEUE_SHIFT 8
460 #define TXDESC_QUEUE_MASK 0x1f00
461 #define TXDESC_QUEUE_BK 0x2
462 #define TXDESC_QUEUE_BE 0x0
463 #define TXDESC_QUEUE_VI 0x5
464 #define TXDESC_QUEUE_VO 0x7
465 #define TXDESC_QUEUE_BEACON 0x10
466 #define TXDESC_QUEUE_HIGH 0x11
467 #define TXDESC_QUEUE_MGNT 0x12
468 #define TXDESC_QUEUE_CMD 0x13
469 #define TXDESC_QUEUE_MAX (TXDESC_QUEUE_CMD + 1)
470 #define TXDESC40_RDG_NAV_EXT BIT(13)
471 #define TXDESC40_LSIG_TXOP_ENABLE BIT(14)
472 #define TXDESC40_PIFS BIT(15)
473
474 #define DESC_RATE_ID_SHIFT 16
475 #define DESC_RATE_ID_MASK 0xf
476 #define TXDESC_NAVUSEHDR BIT(20)
477 #define TXDESC_SEC_RC4 0x00400000
478 #define TXDESC_SEC_AES 0x00c00000
479 #define TXDESC_PKT_OFFSET_SHIFT 26
480 #define TXDESC_AGG_EN BIT(29)
481 #define TXDESC_HWPC BIT(31)
482
483 /* Word 2 */
484 #define TXDESC40_PAID_SHIFT 0
485 #define TXDESC40_PAID_MASK 0x1ff
486 #define TXDESC40_CCA_RTS_SHIFT 10
487 #define TXDESC40_CCA_RTS_MASK 0xc00
488 #define TXDESC40_AGG_ENABLE BIT(12)
489 #define TXDESC40_RDG_ENABLE BIT(13)
490 #define TXDESC40_AGG_BREAK BIT(16)
491 #define TXDESC40_MORE_FRAG BIT(17)
492 #define TXDESC40_RAW BIT(18)
493 #define TXDESC32_ACK_REPORT BIT(19)
494 #define TXDESC40_SPE_RPT BIT(19)
495 #define TXDESC_AMPDU_DENSITY_SHIFT 20
496 #define TXDESC40_BT_INT BIT(23)
497 #define TXDESC40_GID_SHIFT 24
498
499 /* Word 3 */
500 #define TXDESC40_USE_DRIVER_RATE BIT(8)
501 #define TXDESC40_CTS_SELF_ENABLE BIT(11)
502 #define TXDESC40_RTS_CTS_ENABLE BIT(12)
503 #define TXDESC40_HW_RTS_ENABLE BIT(13)
504 #define TXDESC32_SEQ_SHIFT 16
505 #define TXDESC32_SEQ_MASK 0x0fff0000
506
507 /* Word 4 */
508 #define TXDESC32_RTS_RATE_SHIFT 0
509 #define TXDESC32_RTS_RATE_MASK 0x3f
510 #define TXDESC32_QOS BIT(6)
511 #define TXDESC32_HW_SEQ_ENABLE BIT(7)
512 #define TXDESC32_USE_DRIVER_RATE BIT(8)
513 #define TXDESC_DISABLE_DATA_FB BIT(10)
514 #define TXDESC32_CTS_SELF_ENABLE BIT(11)
515 #define TXDESC32_RTS_CTS_ENABLE BIT(12)
516 #define TXDESC32_HW_RTS_ENABLE BIT(13)
517 #define TXDESC_PRIME_CH_OFF_LOWER BIT(20)
518 #define TXDESC_PRIME_CH_OFF_UPPER BIT(21)
519 #define TXDESC32_SHORT_PREAMBLE BIT(24)
520 #define TXDESC_DATA_BW BIT(25)
521 #define TXDESC_RTS_DATA_BW BIT(27)
522 #define TXDESC_RTS_PRIME_CH_OFF_LOWER BIT(28)
523 #define TXDESC_RTS_PRIME_CH_OFF_UPPER BIT(29)
524 #define TXDESC40_DATA_RATE_FB_SHIFT 8
525 #define TXDESC40_DATA_RATE_FB_MASK 0x00001f00
526 #define TXDESC40_RETRY_LIMIT_ENABLE BIT(17)
527 #define TXDESC40_RETRY_LIMIT_SHIFT 18
528 #define TXDESC40_RETRY_LIMIT_MASK 0x00fc0000
529 #define TXDESC40_RTS_RATE_SHIFT 24
530 #define TXDESC40_RTS_RATE_MASK 0x3f000000
531
532 /* Word 5 */
533 #define TXDESC40_SHORT_PREAMBLE BIT(4)
534 #define TXDESC32_SHORT_GI BIT(6)
535 #define TXDESC_CCX_TAG BIT(7)
536 #define TXDESC32_RETRY_LIMIT_ENABLE BIT(17)
537 #define TXDESC32_RETRY_LIMIT_SHIFT 18
538 #define TXDESC32_RETRY_LIMIT_MASK 0x00fc0000
539
540 /* Word 6 */
541 #define TXDESC_MAX_AGG_SHIFT 11
542
543 /* Word 8 */
544 #define TXDESC40_HW_SEQ_ENABLE BIT(15)
545
546 /* Word 9 */
547 #define TXDESC40_SEQ_SHIFT 12
548 #define TXDESC40_SEQ_MASK 0x00fff000
549
550 struct phy_rx_agc_info {
551 #ifdef __LITTLE_ENDIAN
552 u8 gain:7, trsw:1;
553 #else
554 u8 trsw:1, gain:7;
555 #endif
556 };
557
558 struct rtl8723au_phy_stats {
559 struct phy_rx_agc_info path_agc[RTL8723A_MAX_RF_PATHS];
560 u8 ch_corr[RTL8723A_MAX_RF_PATHS];
561 u8 cck_sig_qual_ofdm_pwdb_all;
562 u8 cck_agc_rpt_ofdm_cfosho_a;
563 u8 cck_rpt_b_ofdm_cfosho_b;
564 u8 reserved_1;
565 u8 noise_power_db_msb;
566 u8 path_cfotail[RTL8723A_MAX_RF_PATHS];
567 u8 pcts_mask[RTL8723A_MAX_RF_PATHS];
568 s8 stream_rxevm[RTL8723A_MAX_RF_PATHS];
569 u8 path_rxsnr[RTL8723A_MAX_RF_PATHS];
570 u8 noise_power_db_lsb;
571 u8 reserved_2[3];
572 u8 stream_csi[RTL8723A_MAX_RF_PATHS];
573 u8 stream_target_csi[RTL8723A_MAX_RF_PATHS];
574 s8 sig_evm;
575 u8 reserved_3;
576
577 #ifdef __LITTLE_ENDIAN
578 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */
579 u8 sgi_en:1;
580 u8 rxsc:2;
581 u8 idle_long:1;
582 u8 r_ant_train_en:1;
583 u8 antenna_select_b:1;
584 u8 antenna_select:1;
585 #else /* _BIG_ENDIAN_ */
586 u8 antenna_select:1;
587 u8 antenna_select_b:1;
588 u8 r_ant_train_en:1;
589 u8 idle_long:1;
590 u8 rxsc:2;
591 u8 sgi_en:1;
592 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */
593 #endif
594 };
595
596 /*
597 * Regs to backup
598 */
599 #define RTL8XXXU_ADDA_REGS 16
600 #define RTL8XXXU_MAC_REGS 4
601 #define RTL8XXXU_BB_REGS 9
602
603 struct rtl8xxxu_firmware_header {
604 __le16 signature; /* 92C0: test chip; 92C,
605 88C0: test chip;
606 88C1: MP A-cut;
607 92C1: MP A-cut */
608 u8 category; /* AP/NIC and USB/PCI */
609 u8 function;
610
611 __le16 major_version; /* FW Version */
612 u8 minor_version; /* FW Subversion, default 0x00 */
613 u8 reserved1;
614
615 u8 month; /* Release time Month field */
616 u8 date; /* Release time Date field */
617 u8 hour; /* Release time Hour field */
618 u8 minute; /* Release time Minute field */
619
620 __le16 ramcodesize; /* Size of RAM code */
621 u16 reserved2;
622
623 __le32 svn_idx; /* SVN entry index */
624 u32 reserved3;
625
626 u32 reserved4;
627 u32 reserved5;
628
629 u8 data[0];
630 };
631
632 /*
633 * 8723au/8192cu/8188ru required base power index offset tables.
634 */
635 struct rtl8xxxu_power_base {
636 u32 reg_0e00;
637 u32 reg_0e04;
638 u32 reg_0e08;
639 u32 reg_086c;
640
641 u32 reg_0e10;
642 u32 reg_0e14;
643 u32 reg_0e18;
644 u32 reg_0e1c;
645
646 u32 reg_0830;
647 u32 reg_0834;
648 u32 reg_0838;
649 u32 reg_086c_2;
650
651 u32 reg_083c;
652 u32 reg_0848;
653 u32 reg_084c;
654 u32 reg_0868;
655 };
656
657 /*
658 * The 8723au has 3 channel groups: 1-3, 4-9, and 10-14
659 */
660 struct rtl8723au_idx {
661 #ifdef __LITTLE_ENDIAN
662 int a:4;
663 int b:4;
664 #else
665 int b:4;
666 int a:4;
667 #endif
668 } __attribute__((packed));
669
670 struct rtl8723au_efuse {
671 __le16 rtl_id;
672 u8 res0[0xe];
673 u8 cck_tx_power_index_A[3]; /* 0x10 */
674 u8 cck_tx_power_index_B[3];
675 u8 ht40_1s_tx_power_index_A[3]; /* 0x16 */
676 u8 ht40_1s_tx_power_index_B[3];
677 /*
678 * The following entries are half-bytes split as:
679 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed
680 */
681 struct rtl8723au_idx ht20_tx_power_index_diff[3];
682 struct rtl8723au_idx ofdm_tx_power_index_diff[3];
683 struct rtl8723au_idx ht40_max_power_offset[3];
684 struct rtl8723au_idx ht20_max_power_offset[3];
685 u8 channel_plan; /* 0x28 */
686 u8 tssi_a;
687 u8 thermal_meter;
688 u8 rf_regulatory;
689 u8 rf_option_2;
690 u8 rf_option_3;
691 u8 rf_option_4;
692 u8 res7;
693 u8 version /* 0x30 */;
694 u8 customer_id_major;
695 u8 customer_id_minor;
696 u8 xtal_k;
697 u8 chipset; /* 0x34 */
698 u8 res8[0x82];
699 u8 vid; /* 0xb7 */
700 u8 res9;
701 u8 pid; /* 0xb9 */
702 u8 res10[0x0c];
703 u8 mac_addr[ETH_ALEN]; /* 0xc6 */
704 u8 res11[2];
705 u8 vendor_name[7];
706 u8 res12[2];
707 u8 device_name[0x29]; /* 0xd7 */
708 };
709
710 struct rtl8192cu_efuse {
711 __le16 rtl_id;
712 __le16 hpon;
713 u8 res0[2];
714 __le16 clk;
715 __le16 testr;
716 __le16 vid;
717 __le16 did;
718 __le16 svid;
719 __le16 smid; /* 0x10 */
720 u8 res1[4];
721 u8 mac_addr[ETH_ALEN]; /* 0x16 */
722 u8 res2[2];
723 u8 vendor_name[7];
724 u8 res3[3];
725 u8 device_name[0x14]; /* 0x28 */
726 u8 res4[0x1e]; /* 0x3c */
727 u8 cck_tx_power_index_A[3]; /* 0x5a */
728 u8 cck_tx_power_index_B[3];
729 u8 ht40_1s_tx_power_index_A[3]; /* 0x60 */
730 u8 ht40_1s_tx_power_index_B[3];
731 /*
732 * The following entries are half-bytes split as:
733 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed
734 */
735 struct rtl8723au_idx ht40_2s_tx_power_index_diff[3];
736 struct rtl8723au_idx ht20_tx_power_index_diff[3]; /* 0x69 */
737 struct rtl8723au_idx ofdm_tx_power_index_diff[3];
738 struct rtl8723au_idx ht40_max_power_offset[3]; /* 0x6f */
739 struct rtl8723au_idx ht20_max_power_offset[3];
740 u8 channel_plan; /* 0x75 */
741 u8 tssi_a;
742 u8 tssi_b;
743 u8 thermal_meter; /* xtal_k */ /* 0x78 */
744 u8 rf_regulatory;
745 u8 rf_option_2;
746 u8 rf_option_3;
747 u8 rf_option_4;
748 u8 res5[1]; /* 0x7d */
749 u8 version;
750 u8 customer_id;
751 };
752
753 struct rtl8723bu_pwr_idx {
754 #ifdef __LITTLE_ENDIAN
755 int ht20:4;
756 int ht40:4;
757 int ofdm:4;
758 int cck:4;
759 #else
760 int cck:4;
761 int ofdm:4;
762 int ht40:4;
763 int ht20:4;
764 #endif
765 } __attribute__((packed));
766
767 struct rtl8723bu_efuse_tx_power {
768 u8 cck_base[6];
769 u8 ht40_base[5];
770 struct rtl8723au_idx ht20_ofdm_1s_diff;
771 struct rtl8723bu_pwr_idx pwr_diff[3];
772 u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */
773 };
774
775 struct rtl8723bu_efuse {
776 __le16 rtl_id;
777 u8 res0[0x0e];
778 struct rtl8723bu_efuse_tx_power tx_power_index_A; /* 0x10 */
779 struct rtl8723bu_efuse_tx_power tx_power_index_B; /* 0x3a */
780 struct rtl8723bu_efuse_tx_power tx_power_index_C; /* 0x64 */
781 struct rtl8723bu_efuse_tx_power tx_power_index_D; /* 0x8e */
782 u8 channel_plan; /* 0xb8 */
783 u8 xtal_k;
784 u8 thermal_meter;
785 u8 iqk_lck;
786 u8 pa_type; /* 0xbc */
787 u8 lna_type_2g; /* 0xbd */
788 u8 res2[3];
789 u8 rf_board_option;
790 u8 rf_feature_option;
791 u8 rf_bt_setting;
792 u8 eeprom_version;
793 u8 eeprom_customer_id;
794 u8 res3[2];
795 u8 tx_pwr_calibrate_rate;
796 u8 rf_antenna_option; /* 0xc9 */
797 u8 rfe_option;
798 u8 res4[9];
799 u8 usb_optional_function;
800 u8 res5[0x1e];
801 u8 res6[2];
802 u8 serial[0x0b]; /* 0xf5 */
803 u8 vid; /* 0x100 */
804 u8 res7;
805 u8 pid;
806 u8 res8[4];
807 u8 mac_addr[ETH_ALEN]; /* 0x107 */
808 u8 res9[2];
809 u8 vendor_name[0x07];
810 u8 res10[2];
811 u8 device_name[0x14];
812 u8 res11[0xcf];
813 u8 package_type; /* 0x1fb */
814 u8 res12[0x4];
815 };
816
817 struct rtl8192eu_efuse_tx_power {
818 u8 cck_base[6];
819 u8 ht40_base[5];
820 struct rtl8723au_idx ht20_ofdm_1s_diff;
821 struct rtl8723bu_pwr_idx pwr_diff[3];
822 u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */
823 };
824
825 struct rtl8192eu_efuse {
826 __le16 rtl_id;
827 u8 res0[0x0e];
828 struct rtl8192eu_efuse_tx_power tx_power_index_A; /* 0x10 */
829 struct rtl8192eu_efuse_tx_power tx_power_index_B; /* 0x3a */
830 u8 res2[0x54];
831 u8 channel_plan; /* 0xb8 */
832 u8 xtal_k;
833 u8 thermal_meter;
834 u8 iqk_lck;
835 u8 pa_type; /* 0xbc */
836 u8 lna_type_2g; /* 0xbd */
837 u8 res3[1];
838 u8 lna_type_5g; /* 0xbf */
839 u8 res4[1];
840 u8 rf_board_option;
841 u8 rf_feature_option;
842 u8 rf_bt_setting;
843 u8 eeprom_version;
844 u8 eeprom_customer_id;
845 u8 res5[3];
846 u8 rf_antenna_option; /* 0xc9 */
847 u8 res6[6];
848 u8 vid; /* 0xd0 */
849 u8 res7[1];
850 u8 pid; /* 0xd2 */
851 u8 res8[1];
852 u8 usb_optional_function;
853 u8 res9[2];
854 u8 mac_addr[ETH_ALEN]; /* 0xd7 */
855 u8 res10[2];
856 u8 vendor_name[7];
857 u8 res11[2];
858 u8 device_name[0x0b]; /* 0xe8 */
859 u8 res12[2];
860 u8 serial[0x0b]; /* 0xf5 */
861 u8 res13[0x30];
862 u8 unknown[0x0d]; /* 0x130 */
863 u8 res14[0xc3];
864 };
865
866 struct rtl8xxxu_reg8val {
867 u16 reg;
868 u8 val;
869 };
870
871 struct rtl8xxxu_reg32val {
872 u16 reg;
873 u32 val;
874 };
875
876 struct rtl8xxxu_rfregval {
877 u8 reg;
878 u32 val;
879 };
880
881 enum rtl8xxxu_rfpath {
882 RF_A = 0,
883 RF_B = 1,
884 };
885
886 struct rtl8xxxu_rfregs {
887 u16 hssiparm1;
888 u16 hssiparm2;
889 u16 lssiparm;
890 u16 hspiread;
891 u16 lssiread;
892 u16 rf_sw_ctrl;
893 };
894
895 #define H2C_MAX_MBOX 4
896 #define H2C_EXT BIT(7)
897 #define H2C_JOIN_BSS_DISCONNECT 0
898 #define H2C_JOIN_BSS_CONNECT 1
899
900 /*
901 * H2C (firmware) commands differ between the older generation chips
902 * 8188[cr]u, 819[12]cu, and 8723au, and the more recent chips 8723bu,
903 * 8192[de]u, 8192eu, and 8812.
904 */
905 enum h2c_cmd_8723a {
906 H2C_SET_POWER_MODE = 1,
907 H2C_JOIN_BSS_REPORT = 2,
908 H2C_SET_RSSI = 5,
909 H2C_SET_RATE_MASK = (6 | H2C_EXT),
910 };
911
912 enum h2c_cmd_8723b {
913 /*
914 * Common Class: 000
915 */
916 H2C_8723B_RSVD_PAGE = 0x00,
917 H2C_8723B_MEDIA_STATUS_RPT = 0x01,
918 H2C_8723B_SCAN_ENABLE = 0x02,
919 H2C_8723B_KEEP_ALIVE = 0x03,
920 H2C_8723B_DISCON_DECISION = 0x04,
921 H2C_8723B_PSD_OFFLOAD = 0x05,
922 H2C_8723B_AP_OFFLOAD = 0x08,
923 H2C_8723B_BCN_RSVDPAGE = 0x09,
924 H2C_8723B_PROBERSP_RSVDPAGE = 0x0A,
925 H2C_8723B_FCS_RSVDPAGE = 0x10,
926 H2C_8723B_FCS_INFO = 0x11,
927 H2C_8723B_AP_WOW_GPIO_CTRL = 0x13,
928
929 /*
930 * PoweSave Class: 001
931 */
932 H2C_8723B_SET_PWR_MODE = 0x20,
933 H2C_8723B_PS_TUNING_PARA = 0x21,
934 H2C_8723B_PS_TUNING_PARA2 = 0x22,
935 H2C_8723B_P2P_LPS_PARAM = 0x23,
936 H2C_8723B_P2P_PS_OFFLOAD = 0x24,
937 H2C_8723B_PS_SCAN_ENABLE = 0x25,
938 H2C_8723B_SAP_PS_ = 0x26,
939 H2C_8723B_INACTIVE_PS_ = 0x27,
940 H2C_8723B_FWLPS_IN_IPS_ = 0x28,
941
942 /*
943 * Dynamic Mechanism Class: 010
944 */
945 H2C_8723B_MACID_CFG_RAID = 0x40,
946 H2C_8723B_TXBF = 0x41,
947 H2C_8723B_RSSI_SETTING = 0x42,
948 H2C_8723B_AP_REQ_TXRPT = 0x43,
949 H2C_8723B_INIT_RATE_COLLECT = 0x44,
950
951 /*
952 * BT Class: 011
953 */
954 H2C_8723B_B_TYPE_TDMA = 0x60,
955 H2C_8723B_BT_INFO = 0x61,
956 H2C_8723B_FORCE_BT_TXPWR = 0x62,
957 H2C_8723B_BT_IGNORE_WLANACT = 0x63,
958 H2C_8723B_DAC_SWING_VALUE = 0x64,
959 H2C_8723B_ANT_SEL_RSV = 0x65,
960 H2C_8723B_WL_OPMODE = 0x66,
961 H2C_8723B_BT_MP_OPER = 0x67,
962 H2C_8723B_BT_CONTROL = 0x68,
963 H2C_8723B_BT_WIFI_CTRL = 0x69,
964 H2C_8723B_BT_FW_PATCH = 0x6a,
965 H2C_8723B_BT_WLAN_CALIBRATION = 0x6d,
966 H2C_8723B_BT_GRANT = 0x6e,
967
968 /*
969 * WOWLAN Class: 100
970 */
971 H2C_8723B_WOWLAN = 0x80,
972 H2C_8723B_REMOTE_WAKE_CTRL = 0x81,
973 H2C_8723B_AOAC_GLOBAL_INFO = 0x82,
974 H2C_8723B_AOAC_RSVD_PAGE = 0x83,
975 H2C_8723B_AOAC_RSVD_PAGE2 = 0x84,
976 H2C_8723B_D0_SCAN_OFFLOAD_CTRL = 0x85,
977 H2C_8723B_D0_SCAN_OFFLOAD_INFO = 0x86,
978 H2C_8723B_CHNL_SWITCH_OFFLOAD = 0x87,
979
980 H2C_8723B_RESET_TSF = 0xC0,
981 };
982
983
984 struct h2c_cmd {
985 union {
986 struct {
987 u8 cmd;
988 u8 data[7];
989 } __packed cmd;
990 struct {
991 __le32 data;
992 __le16 ext;
993 } __packed raw;
994 struct {
995 __le32 data;
996 __le32 ext;
997 } __packed raw_wide;
998 struct {
999 u8 cmd;
1000 u8 data;
1001 } __packed joinbss;
1002 struct {
1003 u8 cmd;
1004 __le16 mask_hi;
1005 u8 arg;
1006 __le16 mask_lo;
1007 } __packed ramask;
1008 struct {
1009 u8 cmd;
1010 u8 parm;
1011 u8 macid;
1012 u8 macid_end;
1013 } __packed media_status_rpt;
1014 struct {
1015 u8 cmd;
1016 u8 macid;
1017 /*
1018 * [0:4] - RAID
1019 * [7] - SGI
1020 */
1021 u8 data1;
1022 /*
1023 * [0:1] - Bandwidth
1024 * [3] - No Update
1025 * [4:5] - VHT enable
1026 * [6] - DISPT
1027 * [7] - DISRA
1028 */
1029 u8 data2;
1030 u8 ramask0;
1031 u8 ramask1;
1032 u8 ramask2;
1033 u8 ramask3;
1034 } __packed b_macid_cfg;
1035 struct {
1036 u8 cmd;
1037 u8 data1;
1038 u8 data2;
1039 u8 data3;
1040 u8 data4;
1041 u8 data5;
1042 } __packed b_type_dma;
1043 struct {
1044 u8 cmd;
1045 u8 data;
1046 } __packed bt_info;
1047 struct {
1048 u8 cmd;
1049 u8 operreq;
1050 u8 opcode;
1051 u8 data;
1052 u8 addr;
1053 } __packed bt_mp_oper;
1054 struct {
1055 u8 cmd;
1056 u8 data;
1057 } __packed bt_wlan_calibration;
1058 struct {
1059 u8 cmd;
1060 u8 data;
1061 } __packed ignore_wlan;
1062 struct {
1063 u8 cmd;
1064 u8 ant_inverse;
1065 u8 int_switch_type;
1066 } __packed ant_sel_rsv;
1067 struct {
1068 u8 cmd;
1069 u8 data;
1070 } __packed bt_grant;
1071 };
1072 };
1073
1074 enum c2h_evt_8723b {
1075 C2H_8723B_DEBUG = 0,
1076 C2H_8723B_TSF = 1,
1077 C2H_8723B_AP_RPT_RSP = 2,
1078 C2H_8723B_CCX_TX_RPT = 3,
1079 C2H_8723B_BT_RSSI = 4,
1080 C2H_8723B_BT_OP_MODE = 5,
1081 C2H_8723B_EXT_RA_RPT = 6,
1082 C2H_8723B_BT_INFO = 9,
1083 C2H_8723B_HW_INFO_EXCH = 0x0a,
1084 C2H_8723B_BT_MP_INFO = 0x0b,
1085 C2H_8723B_RA_REPORT = 0x0c,
1086 C2H_8723B_FW_DEBUG = 0xff,
1087 };
1088
1089 enum bt_info_src_8723b {
1090 BT_INFO_SRC_8723B_WIFI_FW = 0x0,
1091 BT_INFO_SRC_8723B_BT_RSP = 0x1,
1092 BT_INFO_SRC_8723B_BT_ACTIVE_SEND = 0x2,
1093 };
1094
1095 enum bt_mp_oper_opcode_8723b {
1096 BT_MP_OP_GET_BT_VERSION = 0x00,
1097 BT_MP_OP_RESET = 0x01,
1098 BT_MP_OP_TEST_CTRL = 0x02,
1099 BT_MP_OP_SET_BT_MODE = 0x03,
1100 BT_MP_OP_SET_CHNL_TX_GAIN = 0x04,
1101 BT_MP_OP_SET_PKT_TYPE_LEN = 0x05,
1102 BT_MP_OP_SET_PKT_CNT_L_PL_TYPE = 0x06,
1103 BT_MP_OP_SET_PKT_CNT_H_PKT_INTV = 0x07,
1104 BT_MP_OP_SET_PKT_HEADER = 0x08,
1105 BT_MP_OP_SET_WHITENCOEFF = 0x09,
1106 BT_MP_OP_SET_BD_ADDR_L = 0x0a,
1107 BT_MP_OP_SET_BD_ADDR_H = 0x0b,
1108 BT_MP_OP_WRITE_REG_ADDR = 0x0c,
1109 BT_MP_OP_WRITE_REG_VALUE = 0x0d,
1110 BT_MP_OP_GET_BT_STATUS = 0x0e,
1111 BT_MP_OP_GET_BD_ADDR_L = 0x0f,
1112 BT_MP_OP_GET_BD_ADDR_H = 0x10,
1113 BT_MP_OP_READ_REG = 0x11,
1114 BT_MP_OP_SET_TARGET_BD_ADDR_L = 0x12,
1115 BT_MP_OP_SET_TARGET_BD_ADDR_H = 0x13,
1116 BT_MP_OP_SET_TX_POWER_CALIBRATION = 0x14,
1117 BT_MP_OP_GET_RX_PKT_CNT_L = 0x15,
1118 BT_MP_OP_GET_RX_PKT_CNT_H = 0x16,
1119 BT_MP_OP_GET_RX_ERROR_BITS_L = 0x17,
1120 BT_MP_OP_GET_RX_ERROR_BITS_H = 0x18,
1121 BT_MP_OP_GET_RSSI = 0x19,
1122 BT_MP_OP_GET_CFO_HDR_QUALITY_L = 0x1a,
1123 BT_MP_OP_GET_CFO_HDR_QUALITY_H = 0x1b,
1124 BT_MP_OP_GET_TARGET_BD_ADDR_L = 0x1c,
1125 BT_MP_OP_GET_TARGET_BD_ADDR_H = 0x1d,
1126 BT_MP_OP_GET_AFH_MAP_L = 0x1e,
1127 BT_MP_OP_GET_AFH_MAP_M = 0x1f,
1128 BT_MP_OP_GET_AFH_MAP_H = 0x20,
1129 BT_MP_OP_GET_AFH_STATUS = 0x21,
1130 BT_MP_OP_SET_TRACKING_INTERVAL = 0x22,
1131 BT_MP_OP_SET_THERMAL_METER = 0x23,
1132 BT_MP_OP_ENABLE_CFO_TRACKING = 0x24,
1133 };
1134
1135 struct rtl8723bu_c2h {
1136 u8 id;
1137 u8 seq;
1138 union {
1139 struct {
1140 u8 payload[0];
1141 } __packed raw;
1142 struct {
1143 u8 ext_id;
1144 u8 status:4;
1145 u8 retlen:4;
1146 u8 opcode_ver:4;
1147 u8 req_num:4;
1148 u8 payload[2];
1149 } __packed bt_mp_info;
1150 struct {
1151 u8 response_source:4;
1152 u8 dummy0_0:4;
1153
1154 u8 bt_info;
1155
1156 u8 retry_count:4;
1157 u8 dummy2_0:1;
1158 u8 bt_page:1;
1159 u8 tx_rx_mask:1;
1160 u8 dummy2_2:1;
1161
1162 u8 rssi;
1163
1164 u8 basic_rate:1;
1165 u8 bt_has_reset:1;
1166 u8 dummy4_1:1;;
1167 u8 ignore_wlan:1;
1168 u8 auto_report:1;
1169 u8 dummy4_2:3;
1170
1171 u8 a4;
1172 u8 a5;
1173 } __packed bt_info;
1174 struct {
1175 u8 rate:7;
1176 u8 dummy0_0:1;
1177 u8 macid;
1178 u8 ldpc:1;
1179 u8 txbf:1;
1180 u8 noisy_state:1;
1181 u8 dummy2_0:5;
1182 u8 dummy3_0;
1183 } __packed ra_report;
1184 };
1185 };
1186
1187 struct rtl8xxxu_fileops;
1188
1189 struct rtl8xxxu_priv {
1190 struct ieee80211_hw *hw;
1191 struct usb_device *udev;
1192 struct rtl8xxxu_fileops *fops;
1193
1194 spinlock_t tx_urb_lock;
1195 struct list_head tx_urb_free_list;
1196 int tx_urb_free_count;
1197 bool tx_stopped;
1198
1199 spinlock_t rx_urb_lock;
1200 struct list_head rx_urb_pending_list;
1201 int rx_urb_pending_count;
1202 bool shutdown;
1203 struct work_struct rx_urb_wq;
1204
1205 u8 mac_addr[ETH_ALEN];
1206 char chip_name[8];
1207 char chip_vendor[8];
1208 u8 cck_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS];
1209 u8 cck_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS];
1210 u8 ht40_1s_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS];
1211 u8 ht40_1s_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS];
1212 /*
1213 * The following entries are half-bytes split as:
1214 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed
1215 */
1216 struct rtl8723au_idx ht40_2s_tx_power_index_diff[
1217 RTL8723A_CHANNEL_GROUPS];
1218 struct rtl8723au_idx ht20_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS];
1219 struct rtl8723au_idx ofdm_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS];
1220 struct rtl8723au_idx ht40_max_power_offset[RTL8723A_CHANNEL_GROUPS];
1221 struct rtl8723au_idx ht20_max_power_offset[RTL8723A_CHANNEL_GROUPS];
1222 /*
1223 * Newer generation chips only keep power diffs per TX count,
1224 * not per channel group.
1225 */
1226 struct rtl8723au_idx ofdm_tx_power_diff[RTL8723B_TX_COUNT];
1227 struct rtl8723au_idx ht20_tx_power_diff[RTL8723B_TX_COUNT];
1228 struct rtl8723au_idx ht40_tx_power_diff[RTL8723B_TX_COUNT];
1229 struct rtl8xxxu_power_base *power_base;
1230 u32 chip_cut:4;
1231 u32 rom_rev:4;
1232 u32 is_multi_func:1;
1233 u32 has_wifi:1;
1234 u32 has_bluetooth:1;
1235 u32 enable_bluetooth:1;
1236 u32 has_gps:1;
1237 u32 hi_pa:1;
1238 u32 vendor_umc:1;
1239 u32 vendor_smic:1;
1240 u32 has_polarity_ctrl:1;
1241 u32 has_eeprom:1;
1242 u32 boot_eeprom:1;
1243 u32 usb_interrupts:1;
1244 u32 ep_tx_high_queue:1;
1245 u32 ep_tx_normal_queue:1;
1246 u32 ep_tx_low_queue:1;
1247 u32 has_xtalk:1;
1248 u8 xtalk;
1249 unsigned int pipe_interrupt;
1250 unsigned int pipe_in;
1251 unsigned int pipe_out[TXDESC_QUEUE_MAX];
1252 u8 out_ep[RTL8XXXU_OUT_ENDPOINTS];
1253 u8 ep_tx_count;
1254 u8 rf_paths;
1255 u8 rx_paths;
1256 u8 tx_paths;
1257 u32 rege94;
1258 u32 rege9c;
1259 u32 regeb4;
1260 u32 regebc;
1261 int next_mbox;
1262 int nr_out_eps;
1263
1264 struct mutex h2c_mutex;
1265
1266 struct usb_anchor rx_anchor;
1267 struct usb_anchor tx_anchor;
1268 struct usb_anchor int_anchor;
1269 struct rtl8xxxu_firmware_header *fw_data;
1270 size_t fw_size;
1271 struct mutex usb_buf_mutex;
1272 union {
1273 __le32 val32;
1274 __le16 val16;
1275 u8 val8;
1276 } usb_buf;
1277 union {
1278 u8 raw[EFUSE_MAP_LEN];
1279 struct rtl8723au_efuse efuse8723;
1280 struct rtl8723bu_efuse efuse8723bu;
1281 struct rtl8192cu_efuse efuse8192;
1282 struct rtl8192eu_efuse efuse8192eu;
1283 } efuse_wifi;
1284 u32 adda_backup[RTL8XXXU_ADDA_REGS];
1285 u32 mac_backup[RTL8XXXU_MAC_REGS];
1286 u32 bb_backup[RTL8XXXU_BB_REGS];
1287 u32 bb_recovery_backup[RTL8XXXU_BB_REGS];
1288 enum rtl8xxxu_rtl_chip rtl_chip;
1289 u8 pi_enabled:1;
1290 u8 no_pape:1;
1291 u8 int_buf[USB_INTR_CONTENT_LENGTH];
1292 };
1293
1294 struct rtl8xxxu_rx_urb {
1295 struct urb urb;
1296 struct ieee80211_hw *hw;
1297 struct list_head list;
1298 };
1299
1300 struct rtl8xxxu_tx_urb {
1301 struct urb urb;
1302 struct ieee80211_hw *hw;
1303 struct list_head list;
1304 };
1305
1306 struct rtl8xxxu_fileops {
1307 int (*parse_efuse) (struct rtl8xxxu_priv *priv);
1308 int (*load_firmware) (struct rtl8xxxu_priv *priv);
1309 int (*power_on) (struct rtl8xxxu_priv *priv);
1310 void (*power_off) (struct rtl8xxxu_priv *priv);
1311 void (*reset_8051) (struct rtl8xxxu_priv *priv);
1312 int (*llt_init) (struct rtl8xxxu_priv *priv, u8 last_tx_page);
1313 void (*init_phy_bb) (struct rtl8xxxu_priv *priv);
1314 int (*init_phy_rf) (struct rtl8xxxu_priv *priv);
1315 void (*phy_init_antenna_selection) (struct rtl8xxxu_priv *priv);
1316 void (*phy_iq_calibrate) (struct rtl8xxxu_priv *priv);
1317 void (*config_channel) (struct ieee80211_hw *hw);
1318 int (*parse_rx_desc) (struct rtl8xxxu_priv *priv, struct sk_buff *skb,
1319 struct ieee80211_rx_status *rx_status);
1320 void (*init_aggregation) (struct rtl8xxxu_priv *priv);
1321 void (*init_statistics) (struct rtl8xxxu_priv *priv);
1322 void (*enable_rf) (struct rtl8xxxu_priv *priv);
1323 void (*disable_rf) (struct rtl8xxxu_priv *priv);
1324 void (*usb_quirks) (struct rtl8xxxu_priv *priv);
1325 void (*set_tx_power) (struct rtl8xxxu_priv *priv, int channel,
1326 bool ht40);
1327 void (*update_rate_mask) (struct rtl8xxxu_priv *priv,
1328 u32 ramask, int sgi);
1329 void (*report_connect) (struct rtl8xxxu_priv *priv,
1330 u8 macid, bool connect);
1331 int writeN_block_size;
1332 u16 mbox_ext_reg;
1333 char mbox_ext_width;
1334 char tx_desc_size;
1335 char rx_desc_size;
1336 char has_s0s1;
1337 u32 adda_1t_init;
1338 u32 adda_1t_path_on;
1339 u32 adda_2t_path_on_a;
1340 u32 adda_2t_path_on_b;
1341 u16 trxff_boundary;
1342 u8 pbp_rx;
1343 u8 pbp_tx;
1344 struct rtl8xxxu_reg8val *mactable;
1345 u8 total_page_num;
1346 u8 page_num_hi;
1347 u8 page_num_lo;
1348 u8 page_num_norm;
1349 };
Linux kernel - Deliverables
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