2 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * Register definitions taken from original Realtek rtl8723au driver
16 #include <asm/byteorder.h>
18 #define RTL8XXXU_DEBUG_REG_WRITE 0x01
19 #define RTL8XXXU_DEBUG_REG_READ 0x02
20 #define RTL8XXXU_DEBUG_RFREG_WRITE 0x04
21 #define RTL8XXXU_DEBUG_RFREG_READ 0x08
22 #define RTL8XXXU_DEBUG_CHANNEL 0x10
23 #define RTL8XXXU_DEBUG_TX 0x20
24 #define RTL8XXXU_DEBUG_TX_DUMP 0x40
25 #define RTL8XXXU_DEBUG_RX 0x80
26 #define RTL8XXXU_DEBUG_RX_DUMP 0x100
27 #define RTL8XXXU_DEBUG_USB 0x200
28 #define RTL8XXXU_DEBUG_KEY 0x400
29 #define RTL8XXXU_DEBUG_H2C 0x800
30 #define RTL8XXXU_DEBUG_ACTION 0x1000
31 #define RTL8XXXU_DEBUG_EFUSE 0x2000
33 #define RTW_USB_CONTROL_MSG_TIMEOUT 500
34 #define RTL8XXXU_MAX_REG_POLL 500
35 #define USB_INTR_CONTENT_LENGTH 56
37 #define RTL8XXXU_OUT_ENDPOINTS 4
39 #define REALTEK_USB_READ 0xc0
40 #define REALTEK_USB_WRITE 0x40
41 #define REALTEK_USB_CMD_REQ 0x05
42 #define REALTEK_USB_CMD_IDX 0x00
44 #define TX_TOTAL_PAGE_NUM 0xf8
45 /* (HPQ + LPQ + NPQ + PUBQ) = TX_TOTAL_PAGE_NUM */
46 #define TX_PAGE_NUM_PUBQ 0xe7
47 #define TX_PAGE_NUM_HI_PQ 0x0c
48 #define TX_PAGE_NUM_LO_PQ 0x02
49 #define TX_PAGE_NUM_NORM_PQ 0x02
51 #define RTL_FW_PAGE_SIZE 4096
52 #define RTL8XXXU_FIRMWARE_POLL_MAX 1000
54 #define RTL8723A_CHANNEL_GROUPS 3
55 #define RTL8723A_MAX_RF_PATHS 2
56 #define RTL8723B_MAX_RF_PATHS 4
57 #define RF6052_MAX_TX_PWR 0x3f
59 #define EFUSE_MAP_LEN 512
60 #define EFUSE_MAX_SECTION_8723A 64
61 #define EFUSE_REAL_CONTENT_LEN_8723A 512
62 #define EFUSE_BT_MAP_LEN_8723A 1024
63 #define EFUSE_MAX_WORD_UNIT 4
65 enum rtl8xxxu_rx_type
{
71 struct rtl8xxxu_rx_desc
{
72 #ifdef __LITTLE_ENDIAN
207 struct rtl8723bu_rx_desc
{
208 #ifdef __LITTLE_ENDIAN
230 u32 a1fit
:4; /* 16 */
245 u32 rx_is_qos
:1; /* 16 */
258 u32 usb_agg_pktnum
:8; /* 16 */
314 u32 usb_agg_pktnum
:8;
315 u32 dummy3_1
:2; /* 16 */
332 struct rtl8xxxu_tx_desc
{
346 /* CCK Rates, TxHT = 0 */
347 #define DESC_RATE_1M 0x00
348 #define DESC_RATE_2M 0x01
349 #define DESC_RATE_5_5M 0x02
350 #define DESC_RATE_11M 0x03
352 /* OFDM Rates, TxHT = 0 */
353 #define DESC_RATE_6M 0x04
354 #define DESC_RATE_9M 0x05
355 #define DESC_RATE_12M 0x06
356 #define DESC_RATE_18M 0x07
357 #define DESC_RATE_24M 0x08
358 #define DESC_RATE_36M 0x09
359 #define DESC_RATE_48M 0x0a
360 #define DESC_RATE_54M 0x0b
362 /* MCS Rates, TxHT = 1 */
363 #define DESC_RATE_MCS0 0x0c
364 #define DESC_RATE_MCS1 0x0d
365 #define DESC_RATE_MCS2 0x0e
366 #define DESC_RATE_MCS3 0x0f
367 #define DESC_RATE_MCS4 0x10
368 #define DESC_RATE_MCS5 0x11
369 #define DESC_RATE_MCS6 0x12
370 #define DESC_RATE_MCS7 0x13
371 #define DESC_RATE_MCS8 0x14
372 #define DESC_RATE_MCS9 0x15
373 #define DESC_RATE_MCS10 0x16
374 #define DESC_RATE_MCS11 0x17
375 #define DESC_RATE_MCS12 0x18
376 #define DESC_RATE_MCS13 0x19
377 #define DESC_RATE_MCS14 0x1a
378 #define DESC_RATE_MCS15 0x1b
379 #define DESC_RATE_MCS15_SG 0x1c
380 #define DESC_RATE_MCS32 0x20
382 #define TXDESC_OFFSET_SZ 0
383 #define TXDESC_OFFSET_SHT 16
385 #define TXDESC_BMC BIT(24)
386 #define TXDESC_LSG BIT(26)
387 #define TXDESC_FSG BIT(27)
388 #define TXDESC_OWN BIT(31)
390 #define TXDESC_BROADMULTICAST BIT(0)
391 #define TXDESC_LAST_SEGMENT BIT(2)
392 #define TXDESC_FIRST_SEGMENT BIT(3)
393 #define TXDESC_OWN BIT(7)
397 #define TXDESC_PKT_OFFSET_SZ 0
398 #define TXDESC_AGG_ENABLE BIT(5)
399 #define TXDESC_BK BIT(6)
400 #define TXDESC_QUEUE_SHIFT 8
401 #define TXDESC_QUEUE_MASK 0x1f00
402 #define TXDESC_QUEUE_BK 0x2
403 #define TXDESC_QUEUE_BE 0x0
404 #define TXDESC_QUEUE_VI 0x5
405 #define TXDESC_QUEUE_VO 0x7
406 #define TXDESC_QUEUE_BEACON 0x10
407 #define TXDESC_QUEUE_HIGH 0x11
408 #define TXDESC_QUEUE_MGNT 0x12
409 #define TXDESC_QUEUE_CMD 0x13
410 #define TXDESC_QUEUE_MAX (TXDESC_QUEUE_CMD + 1)
412 #define DESC_RATE_ID_SHIFT 16
413 #define DESC_RATE_ID_MASK 0xf
414 #define TXDESC_NAVUSEHDR BIT(20)
415 #define TXDESC_SEC_RC4 0x00400000
416 #define TXDESC_SEC_AES 0x00c00000
417 #define TXDESC_PKT_OFFSET_SHIFT 26
418 #define TXDESC_AGG_EN BIT(29)
419 #define TXDESC_HWPC BIT(31)
422 #define TXDESC_ACK_REPORT BIT(19)
423 #define TXDESC_AMPDU_DENSITY_SHIFT 20
426 #define TXDESC_SEQ_SHIFT 16
427 #define TXDESC_SEQ_MASK 0x0fff0000
430 #define TXDESC_QOS BIT(6)
431 #define TXDESC_HW_SEQ_ENABLE BIT(7)
432 #define TXDESC_USE_DRIVER_RATE BIT(8)
433 #define TXDESC_DISABLE_DATA_FB BIT(10)
434 #define TXDESC_CTS_SELF_ENABLE BIT(11)
435 #define TXDESC_RTS_CTS_ENABLE BIT(12)
436 #define TXDESC_HW_RTS_ENABLE BIT(13)
437 #define TXDESC_PRIME_CH_OFF_LOWER BIT(20)
438 #define TXDESC_PRIME_CH_OFF_UPPER BIT(21)
439 #define TXDESC_SHORT_PREAMBLE BIT(24)
440 #define TXDESC_DATA_BW BIT(25)
441 #define TXDESC_RTS_DATA_BW BIT(27)
442 #define TXDESC_RTS_PRIME_CH_OFF_LOWER BIT(28)
443 #define TXDESC_RTS_PRIME_CH_OFF_UPPER BIT(29)
446 #define TXDESC_RTS_RATE_SHIFT 0
447 #define TXDESC_RTS_RATE_MASK 0x3f
448 #define TXDESC_SHORT_GI BIT(6)
449 #define TXDESC_CCX_TAG BIT(7)
450 #define TXDESC_RETRY_LIMIT_ENABLE BIT(17)
451 #define TXDESC_RETRY_LIMIT_SHIFT 18
452 #define TXDESC_RETRY_LIMIT_MASK 0x00fc0000
455 #define TXDESC_MAX_AGG_SHIFT 11
457 struct phy_rx_agc_info
{
458 #ifdef __LITTLE_ENDIAN
465 struct rtl8723au_phy_stats
{
466 struct phy_rx_agc_info path_agc
[RTL8723A_MAX_RF_PATHS
];
467 u8 ch_corr
[RTL8723A_MAX_RF_PATHS
];
468 u8 cck_sig_qual_ofdm_pwdb_all
;
469 u8 cck_agc_rpt_ofdm_cfosho_a
;
470 u8 cck_rpt_b_ofdm_cfosho_b
;
472 u8 noise_power_db_msb
;
473 u8 path_cfotail
[RTL8723A_MAX_RF_PATHS
];
474 u8 pcts_mask
[RTL8723A_MAX_RF_PATHS
];
475 s8 stream_rxevm
[RTL8723A_MAX_RF_PATHS
];
476 u8 path_rxsnr
[RTL8723A_MAX_RF_PATHS
];
477 u8 noise_power_db_lsb
;
479 u8 stream_csi
[RTL8723A_MAX_RF_PATHS
];
480 u8 stream_target_csi
[RTL8723A_MAX_RF_PATHS
];
484 #ifdef __LITTLE_ENDIAN
485 u8 antsel_rx_keep_2
:1; /* ex_intf_flg:1; */
490 u8 antenna_select_b
:1;
492 #else /* _BIG_ENDIAN_ */
494 u8 antenna_select_b
:1;
499 u8 antsel_rx_keep_2
:1; /* ex_intf_flg:1; */
506 #define RTL8XXXU_ADDA_REGS 16
507 #define RTL8XXXU_MAC_REGS 4
508 #define RTL8XXXU_BB_REGS 9
510 struct rtl8xxxu_firmware_header
{
511 __le16 signature
; /* 92C0: test chip; 92C,
515 u8 category
; /* AP/NIC and USB/PCI */
518 __le16 major_version
; /* FW Version */
519 u8 minor_version
; /* FW Subversion, default 0x00 */
522 u8 month
; /* Release time Month field */
523 u8 date
; /* Release time Date field */
524 u8 hour
; /* Release time Hour field */
525 u8 minute
; /* Release time Minute field */
527 __le16 ramcodesize
; /* Size of RAM code */
530 __le32 svn_idx
; /* SVN entry index */
540 * The 8723au has 3 channel groups: 1-3, 4-9, and 10-14
542 struct rtl8723au_idx
{
543 #ifdef __LITTLE_ENDIAN
550 } __attribute__((packed
));
552 struct rtl8723au_efuse
{
555 u8 cck_tx_power_index_A
[3]; /* 0x10 */
556 u8 cck_tx_power_index_B
[3];
557 u8 ht40_1s_tx_power_index_A
[3]; /* 0x16 */
558 u8 ht40_1s_tx_power_index_B
[3];
560 * The following entries are half-bytes split as:
561 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed
563 struct rtl8723au_idx ht20_tx_power_index_diff
[3];
564 struct rtl8723au_idx ofdm_tx_power_index_diff
[3];
565 struct rtl8723au_idx ht40_max_power_offset
[3];
566 struct rtl8723au_idx ht20_max_power_offset
[3];
567 u8 channel_plan
; /* 0x28 */
575 u8 version
/* 0x30 */;
576 u8 customer_id_major
;
577 u8 customer_id_minor
;
579 u8 chipset
; /* 0x34 */
585 u8 mac_addr
[ETH_ALEN
]; /* 0xc6 */
589 u8 device_name
[0x29]; /* 0xd7 */
592 struct rtl8192cu_efuse
{
601 __le16 smid
; /* 0x10 */
603 u8 mac_addr
[ETH_ALEN
]; /* 0x16 */
607 u8 device_name
[0x14]; /* 0x28 */
608 u8 res4
[0x1e]; /* 0x3c */
609 u8 cck_tx_power_index_A
[3]; /* 0x5a */
610 u8 cck_tx_power_index_B
[3];
611 u8 ht40_1s_tx_power_index_A
[3]; /* 0x60 */
612 u8 ht40_1s_tx_power_index_B
[3];
614 * The following entries are half-bytes split as:
615 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed
617 struct rtl8723au_idx ht40_2s_tx_power_index_diff
[3];
618 struct rtl8723au_idx ht20_tx_power_index_diff
[3]; /* 0x69 */
619 struct rtl8723au_idx ofdm_tx_power_index_diff
[3];
620 struct rtl8723au_idx ht40_max_power_offset
[3]; /* 0x6f */
621 struct rtl8723au_idx ht20_max_power_offset
[3];
622 u8 channel_plan
; /* 0x75 */
625 u8 thermal_meter
; /* xtal_k */ /* 0x78 */
630 u8 res5
[1]; /* 0x7d */
635 struct rtl8723bu_efuse_tx_power
{
638 struct rtl8723au_idx ht20_ofdm_1s_diff
;
639 struct rtl8723au_idx ht40_ht20_2s_diff
;
640 struct rtl8723au_idx ofdm_cck_2s_diff
; /* not used */
641 struct rtl8723au_idx ht40_ht20_3s_diff
;
642 struct rtl8723au_idx ofdm_cck_3s_diff
; /* not used */
643 struct rtl8723au_idx ht40_ht20_4s_diff
;
644 struct rtl8723au_idx ofdm_cck_4s_diff
; /* not used */
645 u8 dummy5g
[24]; /* max channel group (14) + power diff offset (10) */
648 struct rtl8723bu_efuse
{
651 struct rtl8723bu_efuse_tx_power tx_power_index_A
; /* 0x10 */
652 struct rtl8723bu_efuse_tx_power tx_power_index_B
; /* 0x3a */
653 struct rtl8723bu_efuse_tx_power tx_power_index_C
; /* 0x64 */
654 struct rtl8723bu_efuse_tx_power tx_power_index_D
; /* 0x8e */
655 u8 channel_plan
; /* 0xb8 */
659 u8 pa_type
; /* 0xbc */
660 u8 lna_type_2g
; /* 0xbd */
663 u8 rf_feature_option
;
666 u8 eeprom_customer_id
;
668 u8 tx_pwr_calibrate_rate
;
669 u8 rf_antenna_option
; /* 0xc9 */
672 u8 usb_optional_function
;
675 u8 serial
[0x0b]; /* 0xf5 */
680 u8 mac_addr
[ETH_ALEN
]; /* 0x107 */
682 u8 vendor_name
[0x07];
684 u8 device_name
[0x14];
686 u8 package_type
; /* 0x1fb */
690 struct rtl8192eu_efuse_tx_power
{
693 struct rtl8723au_idx ht20_ofdm_1s_diff
;
694 struct rtl8723au_idx ht40_ht20_2s_diff
;
695 struct rtl8723au_idx ofdm_cck_2s_diff
; /* not used */
696 struct rtl8723au_idx ht40_ht20_3s_diff
;
697 struct rtl8723au_idx ofdm_cck_3s_diff
; /* not used */
698 struct rtl8723au_idx ht40_ht20_4s_diff
;
699 struct rtl8723au_idx ofdm_cck_4s_diff
; /* not used */
702 struct rtl8192eu_efuse
{
705 struct rtl8192eu_efuse_tx_power tx_power_index_A
; /* 0x10 */
706 struct rtl8192eu_efuse_tx_power tx_power_index_B
; /* 0x22 */
707 struct rtl8192eu_efuse_tx_power tx_power_index_C
; /* 0x34 */
708 struct rtl8192eu_efuse_tx_power tx_power_index_D
; /* 0x46 */
710 u8 channel_plan
; /* 0xb8 */
714 u8 pa_type
; /* 0xbc */
715 u8 lna_type_2g
; /* 0xbd */
717 u8 lna_type_5g
; /* 0xbf */
720 u8 rf_feature_option
;
723 u8 eeprom_customer_id
;
725 u8 rf_antenna_option
; /* 0xc9 */
731 u8 usb_optional_function
;
733 u8 mac_addr
[ETH_ALEN
]; /* 0xd7 */
737 u8 device_name
[0x0b]; /* 0xe8 */
739 u8 serial
[0x0b]; /* 0xf5 */
741 u8 unknown
[0x0d]; /* 0x130 */
745 struct rtl8xxxu_reg8val
{
750 struct rtl8xxxu_reg32val
{
755 struct rtl8xxxu_rfregval
{
760 enum rtl8xxxu_rfpath
{
765 struct rtl8xxxu_rfregs
{
774 #define H2C_MAX_MBOX 4
775 #define H2C_EXT BIT(7)
776 #define H2C_JOIN_BSS_DISCONNECT 0
777 #define H2C_JOIN_BSS_CONNECT 1
780 * H2C (firmware) commands differ between the older generation chips
781 * 8188[cr]u, 819[12]cu, and 8723au, and the more recent chips 8723bu,
782 * 8192[de]u, 8192eu, and 8812.
785 H2C_SET_POWER_MODE
= 1,
786 H2C_JOIN_BSS_REPORT
= 2,
788 H2C_SET_RATE_MASK
= (6 | H2C_EXT
),
795 H2C_8723B_RSVD_PAGE
= 0x00,
796 H2C_8723B_MEDIA_STATUS_RPT
= 0x01,
797 H2C_8723B_SCAN_ENABLE
= 0x02,
798 H2C_8723B_KEEP_ALIVE
= 0x03,
799 H2C_8723B_DISCON_DECISION
= 0x04,
800 H2C_8723B_PSD_OFFLOAD
= 0x05,
801 H2C_8723B_AP_OFFLOAD
= 0x08,
802 H2C_8723B_BCN_RSVDPAGE
= 0x09,
803 H2C_8723B_PROBERSP_RSVDPAGE
= 0x0A,
804 H2C_8723B_FCS_RSVDPAGE
= 0x10,
805 H2C_8723B_FCS_INFO
= 0x11,
806 H2C_8723B_AP_WOW_GPIO_CTRL
= 0x13,
809 * PoweSave Class: 001
811 H2C_8723B_SET_PWR_MODE
= 0x20,
812 H2C_8723B_PS_TUNING_PARA
= 0x21,
813 H2C_8723B_PS_TUNING_PARA2
= 0x22,
814 H2C_8723B_P2P_LPS_PARAM
= 0x23,
815 H2C_8723B_P2P_PS_OFFLOAD
= 0x24,
816 H2C_8723B_PS_SCAN_ENABLE
= 0x25,
817 H2C_8723B_SAP_PS_
= 0x26,
818 H2C_8723B_INACTIVE_PS_
= 0x27,
819 H2C_8723B_FWLPS_IN_IPS_
= 0x28,
822 * Dynamic Mechanism Class: 010
824 H2C_8723B_MACID_CFG
= 0x40,
825 H2C_8723B_TXBF
= 0x41,
826 H2C_8723B_RSSI_SETTING
= 0x42,
827 H2C_8723B_AP_REQ_TXRPT
= 0x43,
828 H2C_8723B_INIT_RATE_COLLECT
= 0x44,
833 H2C_8723B_B_TYPE_TDMA
= 0x60,
834 H2C_8723B_BT_INFO
= 0x61,
835 H2C_8723B_FORCE_BT_TXPWR
= 0x62,
836 H2C_8723B_BT_IGNORE_WLANACT
= 0x63,
837 H2C_8723B_DAC_SWING_VALUE
= 0x64,
838 H2C_8723B_ANT_SEL_RSV
= 0x65,
839 H2C_8723B_WL_OPMODE
= 0x66,
840 H2C_8723B_BT_MP_OPER
= 0x67,
841 H2C_8723B_BT_CONTROL
= 0x68,
842 H2C_8723B_BT_WIFI_CTRL
= 0x69,
843 H2C_8723B_BT_FW_PATCH
= 0x6a,
844 H2C_8723B_BT_WLAN_CALIBRATION
= 0x6d,
845 H2C_8723B_BT_GRANT
= 0x6e,
850 H2C_8723B_WOWLAN
= 0x80,
851 H2C_8723B_REMOTE_WAKE_CTRL
= 0x81,
852 H2C_8723B_AOAC_GLOBAL_INFO
= 0x82,
853 H2C_8723B_AOAC_RSVD_PAGE
= 0x83,
854 H2C_8723B_AOAC_RSVD_PAGE2
= 0x84,
855 H2C_8723B_D0_SCAN_OFFLOAD_CTRL
= 0x85,
856 H2C_8723B_D0_SCAN_OFFLOAD_INFO
= 0x86,
857 H2C_8723B_CHNL_SWITCH_OFFLOAD
= 0x87,
859 H2C_8723B_RESET_TSF
= 0xC0,
894 } __packed b_type_dma
;
905 } __packed bt_mp_oper
;
909 } __packed bt_wlan_calibration
;
913 } __packed ignore_wlan
;
918 } __packed ant_sel_rsv
;
929 C2H_8723B_AP_RPT_RSP
= 2,
930 C2H_8723B_CCX_TX_RPT
= 3,
931 C2H_8723B_BT_RSSI
= 4,
932 C2H_8723B_BT_OP_MODE
= 5,
933 C2H_8723B_EXT_RA_RPT
= 6,
934 C2H_8723B_BT_INFO
= 9,
935 C2H_8723B_HW_INFO_EXCH
= 0x0a,
936 C2H_8723B_BT_MP_INFO
= 0x0b,
937 C2H_8723B_FW_DEBUG
= 0xff,
940 enum bt_info_src_8723b
{
941 BT_INFO_SRC_8723B_WIFI_FW
= 0x0,
942 BT_INFO_SRC_8723B_BT_RSP
= 0x1,
943 BT_INFO_SRC_8723B_BT_ACTIVE_SEND
= 0x2,
946 enum bt_mp_oper_opcode_8723b
{
947 BT_MP_OP_GET_BT_VERSION
= 0x00,
948 BT_MP_OP_RESET
= 0x01,
949 BT_MP_OP_TEST_CTRL
= 0x02,
950 BT_MP_OP_SET_BT_MODE
= 0x03,
951 BT_MP_OP_SET_CHNL_TX_GAIN
= 0x04,
952 BT_MP_OP_SET_PKT_TYPE_LEN
= 0x05,
953 BT_MP_OP_SET_PKT_CNT_L_PL_TYPE
= 0x06,
954 BT_MP_OP_SET_PKT_CNT_H_PKT_INTV
= 0x07,
955 BT_MP_OP_SET_PKT_HEADER
= 0x08,
956 BT_MP_OP_SET_WHITENCOEFF
= 0x09,
957 BT_MP_OP_SET_BD_ADDR_L
= 0x0a,
958 BT_MP_OP_SET_BD_ADDR_H
= 0x0b,
959 BT_MP_OP_WRITE_REG_ADDR
= 0x0c,
960 BT_MP_OP_WRITE_REG_VALUE
= 0x0d,
961 BT_MP_OP_GET_BT_STATUS
= 0x0e,
962 BT_MP_OP_GET_BD_ADDR_L
= 0x0f,
963 BT_MP_OP_GET_BD_ADDR_H
= 0x10,
964 BT_MP_OP_READ_REG
= 0x11,
965 BT_MP_OP_SET_TARGET_BD_ADDR_L
= 0x12,
966 BT_MP_OP_SET_TARGET_BD_ADDR_H
= 0x13,
967 BT_MP_OP_SET_TX_POWER_CALIBRATION
= 0x14,
968 BT_MP_OP_GET_RX_PKT_CNT_L
= 0x15,
969 BT_MP_OP_GET_RX_PKT_CNT_H
= 0x16,
970 BT_MP_OP_GET_RX_ERROR_BITS_L
= 0x17,
971 BT_MP_OP_GET_RX_ERROR_BITS_H
= 0x18,
972 BT_MP_OP_GET_RSSI
= 0x19,
973 BT_MP_OP_GET_CFO_HDR_QUALITY_L
= 0x1a,
974 BT_MP_OP_GET_CFO_HDR_QUALITY_H
= 0x1b,
975 BT_MP_OP_GET_TARGET_BD_ADDR_L
= 0x1c,
976 BT_MP_OP_GET_TARGET_BD_ADDR_H
= 0x1d,
977 BT_MP_OP_GET_AFH_MAP_L
= 0x1e,
978 BT_MP_OP_GET_AFH_MAP_M
= 0x1f,
979 BT_MP_OP_GET_AFH_MAP_H
= 0x20,
980 BT_MP_OP_GET_AFH_STATUS
= 0x21,
981 BT_MP_OP_SET_TRACKING_INTERVAL
= 0x22,
982 BT_MP_OP_SET_THERMAL_METER
= 0x23,
983 BT_MP_OP_ENABLE_CFO_TRACKING
= 0x24,
986 struct rtl8723bu_c2h
{
1000 } __packed bt_mp_info
;
1002 u8 response_source
:4;
1028 struct rtl8xxxu_fileops
;
1030 struct rtl8xxxu_priv
{
1031 struct ieee80211_hw
*hw
;
1032 struct usb_device
*udev
;
1033 struct rtl8xxxu_fileops
*fops
;
1035 spinlock_t tx_urb_lock
;
1036 struct list_head tx_urb_free_list
;
1037 int tx_urb_free_count
;
1040 spinlock_t rx_urb_lock
;
1041 struct list_head rx_urb_pending_list
;
1042 int rx_urb_pending_count
;
1044 struct work_struct rx_urb_wq
;
1046 u8 mac_addr
[ETH_ALEN
];
1048 char chip_vendor
[8];
1049 u8 cck_tx_power_index_A
[3]; /* 0x10 */
1050 u8 cck_tx_power_index_B
[3];
1051 u8 ht40_1s_tx_power_index_A
[3]; /* 0x16 */
1052 u8 ht40_1s_tx_power_index_B
[3];
1054 * The following entries are half-bytes split as:
1055 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed
1057 struct rtl8723au_idx ht40_2s_tx_power_index_diff
[3];
1058 struct rtl8723au_idx ht20_tx_power_index_diff
[3];
1059 struct rtl8723au_idx ofdm_tx_power_index_diff
[3];
1060 struct rtl8723au_idx ht40_max_power_offset
[3];
1061 struct rtl8723au_idx ht20_max_power_offset
[3];
1064 u32 is_multi_func
:1;
1066 u32 has_bluetooth
:1;
1067 u32 enable_bluetooth
:1;
1072 u32 has_polarity_ctrl
:1;
1075 u32 usb_interrupts
:1;
1076 u32 ep_tx_high_queue
:1;
1077 u32 ep_tx_normal_queue
:1;
1078 u32 ep_tx_low_queue
:1;
1081 unsigned int pipe_interrupt
;
1082 unsigned int pipe_in
;
1083 unsigned int pipe_out
[TXDESC_QUEUE_MAX
];
1084 u8 out_ep
[RTL8XXXU_OUT_ENDPOINTS
];
1097 struct mutex h2c_mutex
;
1099 struct usb_anchor rx_anchor
;
1100 struct usb_anchor tx_anchor
;
1101 struct usb_anchor int_anchor
;
1102 struct rtl8xxxu_firmware_header
*fw_data
;
1104 struct mutex usb_buf_mutex
;
1111 u8 raw
[EFUSE_MAP_LEN
];
1112 struct rtl8723au_efuse efuse8723
;
1113 struct rtl8723bu_efuse efuse8723bu
;
1114 struct rtl8192cu_efuse efuse8192
;
1115 struct rtl8192eu_efuse efuse8192eu
;
1117 u32 adda_backup
[RTL8XXXU_ADDA_REGS
];
1118 u32 mac_backup
[RTL8XXXU_MAC_REGS
];
1119 u32 bb_backup
[RTL8XXXU_BB_REGS
];
1120 u32 bb_recovery_backup
[RTL8XXXU_BB_REGS
];
1123 u8 int_buf
[USB_INTR_CONTENT_LENGTH
];
1126 struct rtl8xxxu_rx_urb
{
1128 struct ieee80211_hw
*hw
;
1129 struct list_head list
;
1132 struct rtl8xxxu_tx_urb
{
1134 struct ieee80211_hw
*hw
;
1135 struct list_head list
;
1138 struct rtl8xxxu_fileops
{
1139 int (*parse_efuse
) (struct rtl8xxxu_priv
*priv
);
1140 int (*load_firmware
) (struct rtl8xxxu_priv
*priv
);
1141 int (*power_on
) (struct rtl8xxxu_priv
*priv
);
1142 int (*llt_init
) (struct rtl8xxxu_priv
*priv
, u8 last_tx_page
);
1143 void (*phy_init_antenna_selection
) (struct rtl8xxxu_priv
*priv
);
1144 void (*phy_iq_calibrate
) (struct rtl8xxxu_priv
*priv
);
1145 void (*config_channel
) (struct ieee80211_hw
*hw
);
1146 void (*init_bt
) (struct rtl8xxxu_priv
*priv
);
1147 int (*parse_rx_desc
) (struct rtl8xxxu_priv
*priv
, struct sk_buff
*skb
,
1148 struct ieee80211_rx_status
*rx_status
);
1149 void (*init_aggregation
) (struct rtl8xxxu_priv
*priv
);
1150 void (*init_statistics
) (struct rtl8xxxu_priv
*priv
);
1151 void (*enable_rf
) (struct rtl8xxxu_priv
*priv
);
1152 int writeN_block_size
;
1154 char mbox_ext_width
;
1157 u32 adda_1t_path_on
;
1158 u32 adda_2t_path_on_a
;
1159 u32 adda_2t_path_on_b
;