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rtl8xxxu: Add additional tx descriptor bits for data word 0
[deliverable/linux.git] / drivers / net / wireless / realtek / rtl8xxxu / rtl8xxxu.h
1 /*
2 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * Register definitions taken from original Realtek rtl8723au driver
14 */
15
16 #include <asm/byteorder.h>
17
18 #define RTL8XXXU_DEBUG_REG_WRITE 0x01
19 #define RTL8XXXU_DEBUG_REG_READ 0x02
20 #define RTL8XXXU_DEBUG_RFREG_WRITE 0x04
21 #define RTL8XXXU_DEBUG_RFREG_READ 0x08
22 #define RTL8XXXU_DEBUG_CHANNEL 0x10
23 #define RTL8XXXU_DEBUG_TX 0x20
24 #define RTL8XXXU_DEBUG_TX_DUMP 0x40
25 #define RTL8XXXU_DEBUG_RX 0x80
26 #define RTL8XXXU_DEBUG_RX_DUMP 0x100
27 #define RTL8XXXU_DEBUG_USB 0x200
28 #define RTL8XXXU_DEBUG_KEY 0x400
29 #define RTL8XXXU_DEBUG_H2C 0x800
30 #define RTL8XXXU_DEBUG_ACTION 0x1000
31 #define RTL8XXXU_DEBUG_EFUSE 0x2000
32
33 #define RTW_USB_CONTROL_MSG_TIMEOUT 500
34 #define RTL8XXXU_MAX_REG_POLL 500
35 #define USB_INTR_CONTENT_LENGTH 56
36
37 #define RTL8XXXU_OUT_ENDPOINTS 4
38
39 #define REALTEK_USB_READ 0xc0
40 #define REALTEK_USB_WRITE 0x40
41 #define REALTEK_USB_CMD_REQ 0x05
42 #define REALTEK_USB_CMD_IDX 0x00
43
44 #define TX_TOTAL_PAGE_NUM 0xf8
45 /* (HPQ + LPQ + NPQ + PUBQ) = TX_TOTAL_PAGE_NUM */
46 #define TX_PAGE_NUM_PUBQ 0xe7
47 #define TX_PAGE_NUM_HI_PQ 0x0c
48 #define TX_PAGE_NUM_LO_PQ 0x02
49 #define TX_PAGE_NUM_NORM_PQ 0x02
50
51 #define RTL_FW_PAGE_SIZE 4096
52 #define RTL8XXXU_FIRMWARE_POLL_MAX 1000
53
54 #define RTL8723A_CHANNEL_GROUPS 3
55 #define RTL8723A_MAX_RF_PATHS 2
56 #define RTL8723B_CHANNEL_GROUPS 6
57 #define RTL8723B_TX_COUNT 4
58 #define RTL8723B_MAX_RF_PATHS 4
59 #define RTL8XXXU_MAX_CHANNEL_GROUPS 6
60 #define RF6052_MAX_TX_PWR 0x3f
61
62 #define EFUSE_MAP_LEN 512
63 #define EFUSE_MAX_SECTION_8723A 64
64 #define EFUSE_REAL_CONTENT_LEN_8723A 512
65 #define EFUSE_BT_MAP_LEN_8723A 1024
66 #define EFUSE_MAX_WORD_UNIT 4
67
68 enum rtl8xxxu_rx_type {
69 RX_TYPE_DATA_PKT = 0,
70 RX_TYPE_C2H = 1,
71 RX_TYPE_ERROR = -1
72 };
73
74 struct rtl8xxxu_rx_desc {
75 #ifdef __LITTLE_ENDIAN
76 u32 pktlen:14;
77 u32 crc32:1;
78 u32 icverr:1;
79 u32 drvinfo_sz:4;
80 u32 security:3;
81 u32 qos:1;
82 u32 shift:2;
83 u32 phy_stats:1;
84 u32 swdec:1;
85 u32 ls:1;
86 u32 fs:1;
87 u32 eor:1;
88 u32 own:1;
89
90 u32 macid:5;
91 u32 tid:4;
92 u32 hwrsvd:4;
93 u32 amsdu:1;
94 u32 paggr:1;
95 u32 faggr:1;
96 u32 a1fit:4;
97 u32 a2fit:4;
98 u32 pam:1;
99 u32 pwr:1;
100 u32 md:1;
101 u32 mf:1;
102 u32 type:2;
103 u32 mc:1;
104 u32 bc:1;
105
106 u32 seq:12;
107 u32 frag:4;
108 u32 nextpktlen:14;
109 u32 nextind:1;
110 u32 reserved0:1;
111
112 u32 rxmcs:6;
113 u32 rxht:1;
114 u32 gf:1;
115 u32 splcp:1;
116 u32 bw:1;
117 u32 htc:1;
118 u32 eosp:1;
119 u32 bssidfit:2;
120 u32 reserved1:16;
121 u32 unicastwake:1;
122 u32 magicwake:1;
123
124 u32 pattern0match:1;
125 u32 pattern1match:1;
126 u32 pattern2match:1;
127 u32 pattern3match:1;
128 u32 pattern4match:1;
129 u32 pattern5match:1;
130 u32 pattern6match:1;
131 u32 pattern7match:1;
132 u32 pattern8match:1;
133 u32 pattern9match:1;
134 u32 patternamatch:1;
135 u32 patternbmatch:1;
136 u32 patterncmatch:1;
137 u32 reserved2:19;
138 #else
139 u32 own:1;
140 u32 eor:1;
141 u32 fs:1;
142 u32 ls:1;
143 u32 swdec:1;
144 u32 phy_stats:1;
145 u32 shift:2;
146 u32 qos:1;
147 u32 security:3;
148 u32 drvinfo_sz:4;
149 u32 icverr:1;
150 u32 crc32:1;
151 u32 pktlen:14;
152
153 u32 bc:1;
154 u32 mc:1;
155 u32 type:2;
156 u32 mf:1;
157 u32 md:1;
158 u32 pwr:1;
159 u32 pam:1;
160 u32 a2fit:4;
161 u32 a1fit:4;
162 u32 faggr:1;
163 u32 paggr:1;
164 u32 amsdu:1;
165 u32 hwrsvd:4;
166 u32 tid:4;
167 u32 macid:5;
168
169 u32 reserved0:1;
170 u32 nextind:1;
171 u32 nextpktlen:14;
172 u32 frag:4;
173 u32 seq:12;
174
175 u32 magicwake:1;
176 u32 unicastwake:1;
177 u32 reserved1:16;
178 u32 bssidfit:2;
179 u32 eosp:1;
180 u32 htc:1;
181 u32 bw:1;
182 u32 splcp:1;
183 u32 gf:1;
184 u32 rxht:1;
185 u32 rxmcs:6;
186
187 u32 reserved2:19;
188 u32 patterncmatch:1;
189 u32 patternbmatch:1;
190 u32 patternamatch:1;
191 u32 pattern9match:1;
192 u32 pattern8match:1;
193 u32 pattern7match:1;
194 u32 pattern6match:1;
195 u32 pattern5match:1;
196 u32 pattern4match:1;
197 u32 pattern3match:1;
198 u32 pattern2match:1;
199 u32 pattern1match:1;
200 u32 pattern0match:1;
201 #endif
202 __le32 tsfl;
203 #if 0
204 u32 bassn:12;
205 u32 bavld:1;
206 u32 reserved3:19;
207 #endif
208 };
209
210 struct rtl8723bu_rx_desc {
211 #ifdef __LITTLE_ENDIAN
212 u32 pktlen:14;
213 u32 crc32:1;
214 u32 icverr:1;
215 u32 drvinfo_sz:4;
216 u32 security:3;
217 u32 qos:1;
218 u32 shift:2;
219 u32 phy_stats:1;
220 u32 swdec:1;
221 u32 ls:1;
222 u32 fs:1;
223 u32 eor:1;
224 u32 own:1;
225
226 u32 macid:7;
227 u32 dummy1_0:1;
228 u32 tid:4;
229 u32 dummy1_1:1;
230 u32 amsdu:1;
231 u32 rxid_match:1;
232 u32 paggr:1;
233 u32 a1fit:4; /* 16 */
234 u32 chkerr:1;
235 u32 ipver:1;
236 u32 tcpudp:1;
237 u32 chkvld:1;
238 u32 pam:1;
239 u32 pwr:1;
240 u32 more_data:1;
241 u32 more_frag:1;
242 u32 type:2;
243 u32 mc:1;
244 u32 bc:1;
245
246 u32 seq:12;
247 u32 frag:4;
248 u32 rx_is_qos:1; /* 16 */
249 u32 dummy2_0:1;
250 u32 wlanhd_iv_len:6;
251 u32 dummy2_1:4;
252 u32 rpt_sel:1;
253 u32 dummy2_2:3;
254
255 u32 rxmcs:7;
256 u32 dummy3_0:3;
257 u32 htc:1;
258 u32 eosp:1;
259 u32 bssidfit:2;
260 u32 dummy3_1:2;
261 u32 usb_agg_pktnum:8; /* 16 */
262 u32 dummy3_2:5;
263 u32 pattern_match:1;
264 u32 unicast_match:1;
265 u32 magic_match:1;
266
267 u32 splcp:1;
268 u32 ldcp:1;
269 u32 stbc:1;
270 u32 dummy4_0:1;
271 u32 bw:2;
272 u32 dummy4_1:26;
273 #else
274 u32 own:1;
275 u32 eor:1;
276 u32 fs:1;
277 u32 ls:1;
278 u32 swdec:1;
279 u32 phy_stats:1;
280 u32 shift:2;
281 u32 qos:1;
282 u32 security:3;
283 u32 drvinfo_sz:4;
284 u32 icverr:1;
285 u32 crc32:1;
286 u32 pktlen:14;
287
288 u32 bc:1;
289 u32 mc:1;
290 u32 type:2;
291 u32 mf:1;
292 u32 md:1;
293 u32 pwr:1;
294 u32 pam:1;
295 u32 a2fit:4;
296 u32 a1fit:4;
297 u32 faggr:1;
298 u32 paggr:1;
299 u32 amsdu:1;
300 u32 hwrsvd:4;
301 u32 tid:4;
302 u32 macid:5;
303
304 u32 dummy2_2:3;
305 u32 rpt_sel:1;
306 u32 dummy2_1:4;
307 u32 wlanhd_iv_len:6;
308 u32 dummy2_0:1;
309 u32 rx_is_qos:1;
310 u32 frag:4; /* 16 */
311 u32 seq:12;
312
313 u32 magic_match:1;
314 u32 unicast_match:1;
315 u32 pattern_match:1;
316 u32 dummy3_2:5;
317 u32 usb_agg_pktnum:8;
318 u32 dummy3_1:2; /* 16 */
319 u32 bssidfit:2;
320 u32 eosp:1;
321 u32 htc:1;
322 u32 dummy3_0:3;
323 u32 rxmcs:7;
324
325 u32 dumm4_1:26;
326 u32 bw:2;
327 u32 dummy4_0:1;
328 u32 stbc:1;
329 u32 ldcp:1;
330 u32 splcp:1;
331 #endif
332 __le32 tsfl;
333 };
334
335 struct rtl8723au_tx_desc {
336 __le16 pkt_size;
337 u8 pkt_offset;
338 u8 txdw0;
339 __le32 txdw1;
340 __le32 txdw2;
341 __le32 txdw3;
342 __le32 txdw4;
343 __le32 txdw5;
344 __le32 txdw6;
345 __le16 csum;
346 __le16 txdw7;
347 };
348
349 struct rtl8723bu_tx_desc {
350 __le16 pkt_size;
351 u8 pkt_offset;
352 u8 txdw0;
353 __le32 txdw1;
354 __le32 txdw2;
355 __le32 txdw3;
356 __le32 txdw4;
357 __le32 txdw5;
358 __le32 txdw6;
359 __le16 csum;
360 __le16 txdw7;
361 __le32 txdw8;
362 __le32 txdw9;
363 };
364
365 /* CCK Rates, TxHT = 0 */
366 #define DESC_RATE_1M 0x00
367 #define DESC_RATE_2M 0x01
368 #define DESC_RATE_5_5M 0x02
369 #define DESC_RATE_11M 0x03
370
371 /* OFDM Rates, TxHT = 0 */
372 #define DESC_RATE_6M 0x04
373 #define DESC_RATE_9M 0x05
374 #define DESC_RATE_12M 0x06
375 #define DESC_RATE_18M 0x07
376 #define DESC_RATE_24M 0x08
377 #define DESC_RATE_36M 0x09
378 #define DESC_RATE_48M 0x0a
379 #define DESC_RATE_54M 0x0b
380
381 /* MCS Rates, TxHT = 1 */
382 #define DESC_RATE_MCS0 0x0c
383 #define DESC_RATE_MCS1 0x0d
384 #define DESC_RATE_MCS2 0x0e
385 #define DESC_RATE_MCS3 0x0f
386 #define DESC_RATE_MCS4 0x10
387 #define DESC_RATE_MCS5 0x11
388 #define DESC_RATE_MCS6 0x12
389 #define DESC_RATE_MCS7 0x13
390 #define DESC_RATE_MCS8 0x14
391 #define DESC_RATE_MCS9 0x15
392 #define DESC_RATE_MCS10 0x16
393 #define DESC_RATE_MCS11 0x17
394 #define DESC_RATE_MCS12 0x18
395 #define DESC_RATE_MCS13 0x19
396 #define DESC_RATE_MCS14 0x1a
397 #define DESC_RATE_MCS15 0x1b
398 #define DESC_RATE_MCS15_SG 0x1c
399 #define DESC_RATE_MCS32 0x20
400
401 #define TXDESC_OFFSET_SZ 0
402 #define TXDESC_OFFSET_SHT 16
403 #if 0
404 #define TXDESC_BMC BIT(24)
405 #define TXDESC_LSG BIT(26)
406 #define TXDESC_FSG BIT(27)
407 #define TXDESC_OWN BIT(31)
408 #else
409 #define TXDESC_BROADMULTICAST BIT(0)
410 #define TXDESC_HTC BIT(1)
411 #define TXDESC_LAST_SEGMENT BIT(2)
412 #define TXDESC_FIRST_SEGMENT BIT(3)
413 #define TXDESC_LINIP BIT(4)
414 #define TXDESC_NO_ACM BIT(5)
415 #define TXDESC_GF BIT(6)
416 #define TXDESC_OWN BIT(7)
417 #endif
418
419 /* Word 1 */
420 #define TXDESC_PKT_OFFSET_SZ 0
421 #define TXDESC_AGG_ENABLE BIT(5)
422 #define TXDESC_BK BIT(6)
423 #define TXDESC_QUEUE_SHIFT 8
424 #define TXDESC_QUEUE_MASK 0x1f00
425 #define TXDESC_QUEUE_BK 0x2
426 #define TXDESC_QUEUE_BE 0x0
427 #define TXDESC_QUEUE_VI 0x5
428 #define TXDESC_QUEUE_VO 0x7
429 #define TXDESC_QUEUE_BEACON 0x10
430 #define TXDESC_QUEUE_HIGH 0x11
431 #define TXDESC_QUEUE_MGNT 0x12
432 #define TXDESC_QUEUE_CMD 0x13
433 #define TXDESC_QUEUE_MAX (TXDESC_QUEUE_CMD + 1)
434
435 #define DESC_RATE_ID_SHIFT 16
436 #define DESC_RATE_ID_MASK 0xf
437 #define TXDESC_NAVUSEHDR BIT(20)
438 #define TXDESC_SEC_RC4 0x00400000
439 #define TXDESC_SEC_AES 0x00c00000
440 #define TXDESC_PKT_OFFSET_SHIFT 26
441 #define TXDESC_AGG_EN BIT(29)
442 #define TXDESC_HWPC BIT(31)
443
444 /* Word 2 */
445 #define TXDESC_ACK_REPORT BIT(19)
446 #define TXDESC_AMPDU_DENSITY_SHIFT 20
447
448 /* Word 3 */
449 #define TXDESC_SEQ_SHIFT 16
450 #define TXDESC_SEQ_MASK 0x0fff0000
451
452 /* Word 4 */
453 #define TXDESC_QOS BIT(6)
454 #define TXDESC_HW_SEQ_ENABLE BIT(7)
455 #define TXDESC_USE_DRIVER_RATE BIT(8)
456 #define TXDESC_DISABLE_DATA_FB BIT(10)
457 #define TXDESC_CTS_SELF_ENABLE BIT(11)
458 #define TXDESC_RTS_CTS_ENABLE BIT(12)
459 #define TXDESC_HW_RTS_ENABLE BIT(13)
460 #define TXDESC_PRIME_CH_OFF_LOWER BIT(20)
461 #define TXDESC_PRIME_CH_OFF_UPPER BIT(21)
462 #define TXDESC_SHORT_PREAMBLE BIT(24)
463 #define TXDESC_DATA_BW BIT(25)
464 #define TXDESC_RTS_DATA_BW BIT(27)
465 #define TXDESC_RTS_PRIME_CH_OFF_LOWER BIT(28)
466 #define TXDESC_RTS_PRIME_CH_OFF_UPPER BIT(29)
467
468 /* Word 5 */
469 #define TXDESC_RTS_RATE_SHIFT 0
470 #define TXDESC_RTS_RATE_MASK 0x3f
471 #define TXDESC_SHORT_GI BIT(6)
472 #define TXDESC_CCX_TAG BIT(7)
473 #define TXDESC_RETRY_LIMIT_ENABLE BIT(17)
474 #define TXDESC_RETRY_LIMIT_SHIFT 18
475 #define TXDESC_RETRY_LIMIT_MASK 0x00fc0000
476
477 /* Word 6 */
478 #define TXDESC_MAX_AGG_SHIFT 11
479
480 struct phy_rx_agc_info {
481 #ifdef __LITTLE_ENDIAN
482 u8 gain:7, trsw:1;
483 #else
484 u8 trsw:1, gain:7;
485 #endif
486 };
487
488 struct rtl8723au_phy_stats {
489 struct phy_rx_agc_info path_agc[RTL8723A_MAX_RF_PATHS];
490 u8 ch_corr[RTL8723A_MAX_RF_PATHS];
491 u8 cck_sig_qual_ofdm_pwdb_all;
492 u8 cck_agc_rpt_ofdm_cfosho_a;
493 u8 cck_rpt_b_ofdm_cfosho_b;
494 u8 reserved_1;
495 u8 noise_power_db_msb;
496 u8 path_cfotail[RTL8723A_MAX_RF_PATHS];
497 u8 pcts_mask[RTL8723A_MAX_RF_PATHS];
498 s8 stream_rxevm[RTL8723A_MAX_RF_PATHS];
499 u8 path_rxsnr[RTL8723A_MAX_RF_PATHS];
500 u8 noise_power_db_lsb;
501 u8 reserved_2[3];
502 u8 stream_csi[RTL8723A_MAX_RF_PATHS];
503 u8 stream_target_csi[RTL8723A_MAX_RF_PATHS];
504 s8 sig_evm;
505 u8 reserved_3;
506
507 #ifdef __LITTLE_ENDIAN
508 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */
509 u8 sgi_en:1;
510 u8 rxsc:2;
511 u8 idle_long:1;
512 u8 r_ant_train_en:1;
513 u8 antenna_select_b:1;
514 u8 antenna_select:1;
515 #else /* _BIG_ENDIAN_ */
516 u8 antenna_select:1;
517 u8 antenna_select_b:1;
518 u8 r_ant_train_en:1;
519 u8 idle_long:1;
520 u8 rxsc:2;
521 u8 sgi_en:1;
522 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */
523 #endif
524 };
525
526 /*
527 * Regs to backup
528 */
529 #define RTL8XXXU_ADDA_REGS 16
530 #define RTL8XXXU_MAC_REGS 4
531 #define RTL8XXXU_BB_REGS 9
532
533 struct rtl8xxxu_firmware_header {
534 __le16 signature; /* 92C0: test chip; 92C,
535 88C0: test chip;
536 88C1: MP A-cut;
537 92C1: MP A-cut */
538 u8 category; /* AP/NIC and USB/PCI */
539 u8 function;
540
541 __le16 major_version; /* FW Version */
542 u8 minor_version; /* FW Subversion, default 0x00 */
543 u8 reserved1;
544
545 u8 month; /* Release time Month field */
546 u8 date; /* Release time Date field */
547 u8 hour; /* Release time Hour field */
548 u8 minute; /* Release time Minute field */
549
550 __le16 ramcodesize; /* Size of RAM code */
551 u16 reserved2;
552
553 __le32 svn_idx; /* SVN entry index */
554 u32 reserved3;
555
556 u32 reserved4;
557 u32 reserved5;
558
559 u8 data[0];
560 };
561
562 /*
563 * The 8723au has 3 channel groups: 1-3, 4-9, and 10-14
564 */
565 struct rtl8723au_idx {
566 #ifdef __LITTLE_ENDIAN
567 int a:4;
568 int b:4;
569 #else
570 int b:4;
571 int a:4;
572 #endif
573 } __attribute__((packed));
574
575 struct rtl8723au_efuse {
576 __le16 rtl_id;
577 u8 res0[0xe];
578 u8 cck_tx_power_index_A[3]; /* 0x10 */
579 u8 cck_tx_power_index_B[3];
580 u8 ht40_1s_tx_power_index_A[3]; /* 0x16 */
581 u8 ht40_1s_tx_power_index_B[3];
582 /*
583 * The following entries are half-bytes split as:
584 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed
585 */
586 struct rtl8723au_idx ht20_tx_power_index_diff[3];
587 struct rtl8723au_idx ofdm_tx_power_index_diff[3];
588 struct rtl8723au_idx ht40_max_power_offset[3];
589 struct rtl8723au_idx ht20_max_power_offset[3];
590 u8 channel_plan; /* 0x28 */
591 u8 tssi_a;
592 u8 thermal_meter;
593 u8 rf_regulatory;
594 u8 rf_option_2;
595 u8 rf_option_3;
596 u8 rf_option_4;
597 u8 res7;
598 u8 version /* 0x30 */;
599 u8 customer_id_major;
600 u8 customer_id_minor;
601 u8 xtal_k;
602 u8 chipset; /* 0x34 */
603 u8 res8[0x82];
604 u8 vid; /* 0xb7 */
605 u8 res9;
606 u8 pid; /* 0xb9 */
607 u8 res10[0x0c];
608 u8 mac_addr[ETH_ALEN]; /* 0xc6 */
609 u8 res11[2];
610 u8 vendor_name[7];
611 u8 res12[2];
612 u8 device_name[0x29]; /* 0xd7 */
613 };
614
615 struct rtl8192cu_efuse {
616 __le16 rtl_id;
617 __le16 hpon;
618 u8 res0[2];
619 __le16 clk;
620 __le16 testr;
621 __le16 vid;
622 __le16 did;
623 __le16 svid;
624 __le16 smid; /* 0x10 */
625 u8 res1[4];
626 u8 mac_addr[ETH_ALEN]; /* 0x16 */
627 u8 res2[2];
628 u8 vendor_name[7];
629 u8 res3[3];
630 u8 device_name[0x14]; /* 0x28 */
631 u8 res4[0x1e]; /* 0x3c */
632 u8 cck_tx_power_index_A[3]; /* 0x5a */
633 u8 cck_tx_power_index_B[3];
634 u8 ht40_1s_tx_power_index_A[3]; /* 0x60 */
635 u8 ht40_1s_tx_power_index_B[3];
636 /*
637 * The following entries are half-bytes split as:
638 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed
639 */
640 struct rtl8723au_idx ht40_2s_tx_power_index_diff[3];
641 struct rtl8723au_idx ht20_tx_power_index_diff[3]; /* 0x69 */
642 struct rtl8723au_idx ofdm_tx_power_index_diff[3];
643 struct rtl8723au_idx ht40_max_power_offset[3]; /* 0x6f */
644 struct rtl8723au_idx ht20_max_power_offset[3];
645 u8 channel_plan; /* 0x75 */
646 u8 tssi_a;
647 u8 tssi_b;
648 u8 thermal_meter; /* xtal_k */ /* 0x78 */
649 u8 rf_regulatory;
650 u8 rf_option_2;
651 u8 rf_option_3;
652 u8 rf_option_4;
653 u8 res5[1]; /* 0x7d */
654 u8 version;
655 u8 customer_id;
656 };
657
658 struct rtl8723bu_pwr_idx {
659 #ifdef __LITTLE_ENDIAN
660 int ht20:4;
661 int ht40:4;
662 int ofdm:4;
663 int cck:4;
664 #else
665 int cck:4;
666 int ofdm:4;
667 int ht40:4;
668 int ht20:4;
669 #endif
670 } __attribute__((packed));
671
672 struct rtl8723bu_efuse_tx_power {
673 u8 cck_base[6];
674 u8 ht40_base[5];
675 struct rtl8723au_idx ht20_ofdm_1s_diff;
676 struct rtl8723bu_pwr_idx pwr_diff[3];
677 u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */
678 };
679
680 struct rtl8723bu_efuse {
681 __le16 rtl_id;
682 u8 res0[0x0e];
683 struct rtl8723bu_efuse_tx_power tx_power_index_A; /* 0x10 */
684 struct rtl8723bu_efuse_tx_power tx_power_index_B; /* 0x3a */
685 struct rtl8723bu_efuse_tx_power tx_power_index_C; /* 0x64 */
686 struct rtl8723bu_efuse_tx_power tx_power_index_D; /* 0x8e */
687 u8 channel_plan; /* 0xb8 */
688 u8 xtal_k;
689 u8 thermal_meter;
690 u8 iqk_lck;
691 u8 pa_type; /* 0xbc */
692 u8 lna_type_2g; /* 0xbd */
693 u8 res2[3];
694 u8 rf_board_option;
695 u8 rf_feature_option;
696 u8 rf_bt_setting;
697 u8 eeprom_version;
698 u8 eeprom_customer_id;
699 u8 res3[2];
700 u8 tx_pwr_calibrate_rate;
701 u8 rf_antenna_option; /* 0xc9 */
702 u8 rfe_option;
703 u8 res4[9];
704 u8 usb_optional_function;
705 u8 res5[0x1e];
706 u8 res6[2];
707 u8 serial[0x0b]; /* 0xf5 */
708 u8 vid; /* 0x100 */
709 u8 res7;
710 u8 pid;
711 u8 res8[4];
712 u8 mac_addr[ETH_ALEN]; /* 0x107 */
713 u8 res9[2];
714 u8 vendor_name[0x07];
715 u8 res10[2];
716 u8 device_name[0x14];
717 u8 res11[0xcf];
718 u8 package_type; /* 0x1fb */
719 u8 res12[0x4];
720 };
721
722 struct rtl8192eu_efuse_tx_power {
723 u8 cck_base[6];
724 u8 ht40_base[5];
725 struct rtl8723au_idx ht20_ofdm_1s_diff;
726 struct rtl8723au_idx ht40_ht20_2s_diff;
727 struct rtl8723au_idx ofdm_cck_2s_diff; /* not used */
728 struct rtl8723au_idx ht40_ht20_3s_diff;
729 struct rtl8723au_idx ofdm_cck_3s_diff; /* not used */
730 struct rtl8723au_idx ht40_ht20_4s_diff;
731 struct rtl8723au_idx ofdm_cck_4s_diff; /* not used */
732 };
733
734 struct rtl8192eu_efuse {
735 __le16 rtl_id;
736 u8 res0[0x0e];
737 struct rtl8192eu_efuse_tx_power tx_power_index_A; /* 0x10 */
738 struct rtl8192eu_efuse_tx_power tx_power_index_B; /* 0x22 */
739 struct rtl8192eu_efuse_tx_power tx_power_index_C; /* 0x34 */
740 struct rtl8192eu_efuse_tx_power tx_power_index_D; /* 0x46 */
741 u8 res1[0x60];
742 u8 channel_plan; /* 0xb8 */
743 u8 xtal_k;
744 u8 thermal_meter;
745 u8 iqk_lck;
746 u8 pa_type; /* 0xbc */
747 u8 lna_type_2g; /* 0xbd */
748 u8 res2[1];
749 u8 lna_type_5g; /* 0xbf */
750 u8 res13[1];
751 u8 rf_board_option;
752 u8 rf_feature_option;
753 u8 rf_bt_setting;
754 u8 eeprom_version;
755 u8 eeprom_customer_id;
756 u8 res3[3];
757 u8 rf_antenna_option; /* 0xc9 */
758 u8 res4[6];
759 u8 vid; /* 0xd0 */
760 u8 res5[1];
761 u8 pid; /* 0xd2 */
762 u8 res6[1];
763 u8 usb_optional_function;
764 u8 res7[2];
765 u8 mac_addr[ETH_ALEN]; /* 0xd7 */
766 u8 res8[2];
767 u8 vendor_name[7];
768 u8 res9[2];
769 u8 device_name[0x0b]; /* 0xe8 */
770 u8 res10[2];
771 u8 serial[0x0b]; /* 0xf5 */
772 u8 res11[0x30];
773 u8 unknown[0x0d]; /* 0x130 */
774 u8 res12[0xc3];
775 };
776
777 struct rtl8xxxu_reg8val {
778 u16 reg;
779 u8 val;
780 };
781
782 struct rtl8xxxu_reg32val {
783 u16 reg;
784 u32 val;
785 };
786
787 struct rtl8xxxu_rfregval {
788 u8 reg;
789 u32 val;
790 };
791
792 enum rtl8xxxu_rfpath {
793 RF_A = 0,
794 RF_B = 1,
795 };
796
797 struct rtl8xxxu_rfregs {
798 u16 hssiparm1;
799 u16 hssiparm2;
800 u16 lssiparm;
801 u16 hspiread;
802 u16 lssiread;
803 u16 rf_sw_ctrl;
804 };
805
806 #define H2C_MAX_MBOX 4
807 #define H2C_EXT BIT(7)
808 #define H2C_JOIN_BSS_DISCONNECT 0
809 #define H2C_JOIN_BSS_CONNECT 1
810
811 /*
812 * H2C (firmware) commands differ between the older generation chips
813 * 8188[cr]u, 819[12]cu, and 8723au, and the more recent chips 8723bu,
814 * 8192[de]u, 8192eu, and 8812.
815 */
816 enum h2c_cmd_8723a {
817 H2C_SET_POWER_MODE = 1,
818 H2C_JOIN_BSS_REPORT = 2,
819 H2C_SET_RSSI = 5,
820 H2C_SET_RATE_MASK = (6 | H2C_EXT),
821 };
822
823 enum h2c_cmd_8723b {
824 /*
825 * Common Class: 000
826 */
827 H2C_8723B_RSVD_PAGE = 0x00,
828 H2C_8723B_MEDIA_STATUS_RPT = 0x01,
829 H2C_8723B_SCAN_ENABLE = 0x02,
830 H2C_8723B_KEEP_ALIVE = 0x03,
831 H2C_8723B_DISCON_DECISION = 0x04,
832 H2C_8723B_PSD_OFFLOAD = 0x05,
833 H2C_8723B_AP_OFFLOAD = 0x08,
834 H2C_8723B_BCN_RSVDPAGE = 0x09,
835 H2C_8723B_PROBERSP_RSVDPAGE = 0x0A,
836 H2C_8723B_FCS_RSVDPAGE = 0x10,
837 H2C_8723B_FCS_INFO = 0x11,
838 H2C_8723B_AP_WOW_GPIO_CTRL = 0x13,
839
840 /*
841 * PoweSave Class: 001
842 */
843 H2C_8723B_SET_PWR_MODE = 0x20,
844 H2C_8723B_PS_TUNING_PARA = 0x21,
845 H2C_8723B_PS_TUNING_PARA2 = 0x22,
846 H2C_8723B_P2P_LPS_PARAM = 0x23,
847 H2C_8723B_P2P_PS_OFFLOAD = 0x24,
848 H2C_8723B_PS_SCAN_ENABLE = 0x25,
849 H2C_8723B_SAP_PS_ = 0x26,
850 H2C_8723B_INACTIVE_PS_ = 0x27,
851 H2C_8723B_FWLPS_IN_IPS_ = 0x28,
852
853 /*
854 * Dynamic Mechanism Class: 010
855 */
856 H2C_8723B_MACID_CFG = 0x40,
857 H2C_8723B_TXBF = 0x41,
858 H2C_8723B_RSSI_SETTING = 0x42,
859 H2C_8723B_AP_REQ_TXRPT = 0x43,
860 H2C_8723B_INIT_RATE_COLLECT = 0x44,
861
862 /*
863 * BT Class: 011
864 */
865 H2C_8723B_B_TYPE_TDMA = 0x60,
866 H2C_8723B_BT_INFO = 0x61,
867 H2C_8723B_FORCE_BT_TXPWR = 0x62,
868 H2C_8723B_BT_IGNORE_WLANACT = 0x63,
869 H2C_8723B_DAC_SWING_VALUE = 0x64,
870 H2C_8723B_ANT_SEL_RSV = 0x65,
871 H2C_8723B_WL_OPMODE = 0x66,
872 H2C_8723B_BT_MP_OPER = 0x67,
873 H2C_8723B_BT_CONTROL = 0x68,
874 H2C_8723B_BT_WIFI_CTRL = 0x69,
875 H2C_8723B_BT_FW_PATCH = 0x6a,
876 H2C_8723B_BT_WLAN_CALIBRATION = 0x6d,
877 H2C_8723B_BT_GRANT = 0x6e,
878
879 /*
880 * WOWLAN Class: 100
881 */
882 H2C_8723B_WOWLAN = 0x80,
883 H2C_8723B_REMOTE_WAKE_CTRL = 0x81,
884 H2C_8723B_AOAC_GLOBAL_INFO = 0x82,
885 H2C_8723B_AOAC_RSVD_PAGE = 0x83,
886 H2C_8723B_AOAC_RSVD_PAGE2 = 0x84,
887 H2C_8723B_D0_SCAN_OFFLOAD_CTRL = 0x85,
888 H2C_8723B_D0_SCAN_OFFLOAD_INFO = 0x86,
889 H2C_8723B_CHNL_SWITCH_OFFLOAD = 0x87,
890
891 H2C_8723B_RESET_TSF = 0xC0,
892 };
893
894
895 struct h2c_cmd {
896 union {
897 struct {
898 u8 cmd;
899 u8 data[7];
900 } __packed cmd;
901 struct {
902 __le32 data;
903 __le16 ext;
904 } __packed raw;
905 struct {
906 __le32 data;
907 __le32 ext;
908 } __packed raw_wide;
909 struct {
910 u8 cmd;
911 u8 data;
912 } __packed joinbss;
913 struct {
914 u8 cmd;
915 __le16 mask_hi;
916 u8 arg;
917 __le16 mask_lo;
918 } __packed ramask;
919 struct {
920 u8 cmd;
921 u8 data1;
922 u8 data2;
923 u8 data3;
924 u8 data4;
925 u8 data5;
926 } __packed b_type_dma;
927 struct {
928 u8 cmd;
929 u8 data;
930 } __packed bt_info;
931 struct {
932 u8 cmd;
933 u8 operreq;
934 u8 opcode;
935 u8 data;
936 u8 addr;
937 } __packed bt_mp_oper;
938 struct {
939 u8 cmd;
940 u8 data;
941 } __packed bt_wlan_calibration;
942 struct {
943 u8 cmd;
944 u8 data;
945 } __packed ignore_wlan;
946 struct {
947 u8 cmd;
948 u8 ant_inverse;
949 u8 int_switch_type;
950 } __packed ant_sel_rsv;
951 struct {
952 u8 cmd;
953 u8 data;
954 } __packed bt_grant;
955 };
956 };
957
958 enum c2h_evt_8723b {
959 C2H_8723B_DEBUG = 0,
960 C2H_8723B_TSF = 1,
961 C2H_8723B_AP_RPT_RSP = 2,
962 C2H_8723B_CCX_TX_RPT = 3,
963 C2H_8723B_BT_RSSI = 4,
964 C2H_8723B_BT_OP_MODE = 5,
965 C2H_8723B_EXT_RA_RPT = 6,
966 C2H_8723B_BT_INFO = 9,
967 C2H_8723B_HW_INFO_EXCH = 0x0a,
968 C2H_8723B_BT_MP_INFO = 0x0b,
969 C2H_8723B_FW_DEBUG = 0xff,
970 };
971
972 enum bt_info_src_8723b {
973 BT_INFO_SRC_8723B_WIFI_FW = 0x0,
974 BT_INFO_SRC_8723B_BT_RSP = 0x1,
975 BT_INFO_SRC_8723B_BT_ACTIVE_SEND = 0x2,
976 };
977
978 enum bt_mp_oper_opcode_8723b {
979 BT_MP_OP_GET_BT_VERSION = 0x00,
980 BT_MP_OP_RESET = 0x01,
981 BT_MP_OP_TEST_CTRL = 0x02,
982 BT_MP_OP_SET_BT_MODE = 0x03,
983 BT_MP_OP_SET_CHNL_TX_GAIN = 0x04,
984 BT_MP_OP_SET_PKT_TYPE_LEN = 0x05,
985 BT_MP_OP_SET_PKT_CNT_L_PL_TYPE = 0x06,
986 BT_MP_OP_SET_PKT_CNT_H_PKT_INTV = 0x07,
987 BT_MP_OP_SET_PKT_HEADER = 0x08,
988 BT_MP_OP_SET_WHITENCOEFF = 0x09,
989 BT_MP_OP_SET_BD_ADDR_L = 0x0a,
990 BT_MP_OP_SET_BD_ADDR_H = 0x0b,
991 BT_MP_OP_WRITE_REG_ADDR = 0x0c,
992 BT_MP_OP_WRITE_REG_VALUE = 0x0d,
993 BT_MP_OP_GET_BT_STATUS = 0x0e,
994 BT_MP_OP_GET_BD_ADDR_L = 0x0f,
995 BT_MP_OP_GET_BD_ADDR_H = 0x10,
996 BT_MP_OP_READ_REG = 0x11,
997 BT_MP_OP_SET_TARGET_BD_ADDR_L = 0x12,
998 BT_MP_OP_SET_TARGET_BD_ADDR_H = 0x13,
999 BT_MP_OP_SET_TX_POWER_CALIBRATION = 0x14,
1000 BT_MP_OP_GET_RX_PKT_CNT_L = 0x15,
1001 BT_MP_OP_GET_RX_PKT_CNT_H = 0x16,
1002 BT_MP_OP_GET_RX_ERROR_BITS_L = 0x17,
1003 BT_MP_OP_GET_RX_ERROR_BITS_H = 0x18,
1004 BT_MP_OP_GET_RSSI = 0x19,
1005 BT_MP_OP_GET_CFO_HDR_QUALITY_L = 0x1a,
1006 BT_MP_OP_GET_CFO_HDR_QUALITY_H = 0x1b,
1007 BT_MP_OP_GET_TARGET_BD_ADDR_L = 0x1c,
1008 BT_MP_OP_GET_TARGET_BD_ADDR_H = 0x1d,
1009 BT_MP_OP_GET_AFH_MAP_L = 0x1e,
1010 BT_MP_OP_GET_AFH_MAP_M = 0x1f,
1011 BT_MP_OP_GET_AFH_MAP_H = 0x20,
1012 BT_MP_OP_GET_AFH_STATUS = 0x21,
1013 BT_MP_OP_SET_TRACKING_INTERVAL = 0x22,
1014 BT_MP_OP_SET_THERMAL_METER = 0x23,
1015 BT_MP_OP_ENABLE_CFO_TRACKING = 0x24,
1016 };
1017
1018 struct rtl8723bu_c2h {
1019 u8 id;
1020 u8 seq;
1021 union {
1022 struct {
1023 u8 payload[0];
1024 } __packed raw;
1025 struct {
1026 u8 ext_id;
1027 u8 status:4;
1028 u8 retlen:4;
1029 u8 opcode_ver:4;
1030 u8 req_num:4;
1031 u8 payload[2];
1032 } __packed bt_mp_info;
1033 struct {
1034 u8 response_source:4;
1035 u8 dummy0_0:4;
1036
1037 u8 bt_info;
1038
1039 u8 retry_count:4;
1040 u8 dummy2_0:1;
1041 u8 bt_page:1;
1042 u8 tx_rx_mask:1;
1043 u8 dummy2_2:1;
1044
1045 u8 rssi;
1046
1047 u8 basic_rate:1;
1048 u8 bt_has_reset:1;
1049 u8 dummy4_1:1;;
1050 u8 ignore_wlan:1;
1051 u8 auto_report:1;
1052 u8 dummy4_2:3;
1053
1054 u8 a4;
1055 u8 a5;
1056 } __packed bt_info;
1057 };
1058 };
1059
1060 struct rtl8xxxu_fileops;
1061
1062 struct rtl8xxxu_priv {
1063 struct ieee80211_hw *hw;
1064 struct usb_device *udev;
1065 struct rtl8xxxu_fileops *fops;
1066
1067 spinlock_t tx_urb_lock;
1068 struct list_head tx_urb_free_list;
1069 int tx_urb_free_count;
1070 bool tx_stopped;
1071
1072 spinlock_t rx_urb_lock;
1073 struct list_head rx_urb_pending_list;
1074 int rx_urb_pending_count;
1075 bool shutdown;
1076 struct work_struct rx_urb_wq;
1077
1078 u8 mac_addr[ETH_ALEN];
1079 char chip_name[8];
1080 char chip_vendor[8];
1081 u8 cck_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS];
1082 u8 cck_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS];
1083 u8 ht40_1s_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS];
1084 u8 ht40_1s_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS];
1085 /*
1086 * The following entries are half-bytes split as:
1087 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed
1088 */
1089 struct rtl8723au_idx ht40_2s_tx_power_index_diff[
1090 RTL8723A_CHANNEL_GROUPS];
1091 struct rtl8723au_idx ht20_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS];
1092 struct rtl8723au_idx ofdm_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS];
1093 struct rtl8723au_idx ht40_max_power_offset[RTL8723A_CHANNEL_GROUPS];
1094 struct rtl8723au_idx ht20_max_power_offset[RTL8723A_CHANNEL_GROUPS];
1095 /*
1096 * Newer generation chips only keep power diffs per TX count,
1097 * not per channel group.
1098 */
1099 struct rtl8723au_idx ofdm_tx_power_diff[RTL8723B_TX_COUNT];
1100 struct rtl8723au_idx ht20_tx_power_diff[RTL8723B_TX_COUNT];
1101 struct rtl8723au_idx ht40_tx_power_diff[RTL8723B_TX_COUNT];
1102 u32 chip_cut:4;
1103 u32 rom_rev:4;
1104 u32 is_multi_func:1;
1105 u32 has_wifi:1;
1106 u32 has_bluetooth:1;
1107 u32 enable_bluetooth:1;
1108 u32 has_gps:1;
1109 u32 hi_pa:1;
1110 u32 vendor_umc:1;
1111 u32 vendor_smic:1;
1112 u32 has_polarity_ctrl:1;
1113 u32 has_eeprom:1;
1114 u32 boot_eeprom:1;
1115 u32 usb_interrupts:1;
1116 u32 ep_tx_high_queue:1;
1117 u32 ep_tx_normal_queue:1;
1118 u32 ep_tx_low_queue:1;
1119 u32 has_xtalk:1;
1120 u8 xtalk;
1121 unsigned int pipe_interrupt;
1122 unsigned int pipe_in;
1123 unsigned int pipe_out[TXDESC_QUEUE_MAX];
1124 u8 out_ep[RTL8XXXU_OUT_ENDPOINTS];
1125 u8 ep_tx_count;
1126 u8 rf_paths;
1127 u8 rx_paths;
1128 u8 tx_paths;
1129 u32 rf_mode_ag[2];
1130 u32 rege94;
1131 u32 rege9c;
1132 u32 regeb4;
1133 u32 regebc;
1134 int next_mbox;
1135 int nr_out_eps;
1136
1137 struct mutex h2c_mutex;
1138
1139 struct usb_anchor rx_anchor;
1140 struct usb_anchor tx_anchor;
1141 struct usb_anchor int_anchor;
1142 struct rtl8xxxu_firmware_header *fw_data;
1143 size_t fw_size;
1144 struct mutex usb_buf_mutex;
1145 union {
1146 __le32 val32;
1147 __le16 val16;
1148 u8 val8;
1149 } usb_buf;
1150 union {
1151 u8 raw[EFUSE_MAP_LEN];
1152 struct rtl8723au_efuse efuse8723;
1153 struct rtl8723bu_efuse efuse8723bu;
1154 struct rtl8192cu_efuse efuse8192;
1155 struct rtl8192eu_efuse efuse8192eu;
1156 } efuse_wifi;
1157 u32 adda_backup[RTL8XXXU_ADDA_REGS];
1158 u32 mac_backup[RTL8XXXU_MAC_REGS];
1159 u32 bb_backup[RTL8XXXU_BB_REGS];
1160 u32 bb_recovery_backup[RTL8XXXU_BB_REGS];
1161 u32 rtlchip;
1162 u8 pi_enabled:1;
1163 u8 int_buf[USB_INTR_CONTENT_LENGTH];
1164 };
1165
1166 struct rtl8xxxu_rx_urb {
1167 struct urb urb;
1168 struct ieee80211_hw *hw;
1169 struct list_head list;
1170 };
1171
1172 struct rtl8xxxu_tx_urb {
1173 struct urb urb;
1174 struct ieee80211_hw *hw;
1175 struct list_head list;
1176 };
1177
1178 struct rtl8xxxu_fileops {
1179 int (*parse_efuse) (struct rtl8xxxu_priv *priv);
1180 int (*load_firmware) (struct rtl8xxxu_priv *priv);
1181 int (*power_on) (struct rtl8xxxu_priv *priv);
1182 int (*llt_init) (struct rtl8xxxu_priv *priv, u8 last_tx_page);
1183 void (*phy_init_antenna_selection) (struct rtl8xxxu_priv *priv);
1184 void (*phy_iq_calibrate) (struct rtl8xxxu_priv *priv);
1185 void (*config_channel) (struct ieee80211_hw *hw);
1186 void (*init_bt) (struct rtl8xxxu_priv *priv);
1187 int (*parse_rx_desc) (struct rtl8xxxu_priv *priv, struct sk_buff *skb,
1188 struct ieee80211_rx_status *rx_status);
1189 void (*init_aggregation) (struct rtl8xxxu_priv *priv);
1190 void (*init_statistics) (struct rtl8xxxu_priv *priv);
1191 void (*enable_rf) (struct rtl8xxxu_priv *priv);
1192 void (*set_tx_power) (struct rtl8xxxu_priv *priv, int channel,
1193 bool ht40);
1194 int writeN_block_size;
1195 u16 mbox_ext_reg;
1196 char mbox_ext_width;
1197 char tx_desc_size;
1198 char has_s0s1;
1199 u32 adda_1t_init;
1200 u32 adda_1t_path_on;
1201 u32 adda_2t_path_on_a;
1202 u32 adda_2t_path_on_b;
1203 };
Linux kernel - Deliverables
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