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Merge branch 'drm-tda998x-devel' of git://ftp.arm.linux.org.uk/~rmk/linux-arm into...
[deliverable/linux.git] / drivers / net / wireless / realtek / rtlwifi / rtl8192se / hw.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #include "../wifi.h"
31 #include "../efuse.h"
32 #include "../base.h"
33 #include "../regd.h"
34 #include "../cam.h"
35 #include "../ps.h"
36 #include "../pci.h"
37 #include "reg.h"
38 #include "def.h"
39 #include "phy.h"
40 #include "dm.h"
41 #include "fw.h"
42 #include "led.h"
43 #include "hw.h"
44
45 void rtl92se_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
46 {
47 struct rtl_priv *rtlpriv = rtl_priv(hw);
48 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
50
51 switch (variable) {
52 case HW_VAR_RCR: {
53 *((u32 *) (val)) = rtlpci->receive_config;
54 break;
55 }
56 case HW_VAR_RF_STATE: {
57 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
58 break;
59 }
60 case HW_VAR_FW_PSMODE_STATUS: {
61 *((bool *) (val)) = ppsc->fw_current_inpsmode;
62 break;
63 }
64 case HW_VAR_CORRECT_TSF: {
65 u64 tsf;
66 u32 *ptsf_low = (u32 *)&tsf;
67 u32 *ptsf_high = ((u32 *)&tsf) + 1;
68
69 *ptsf_high = rtl_read_dword(rtlpriv, (TSFR + 4));
70 *ptsf_low = rtl_read_dword(rtlpriv, TSFR);
71
72 *((u64 *) (val)) = tsf;
73
74 break;
75 }
76 case HW_VAR_MRC: {
77 *((bool *)(val)) = rtlpriv->dm.current_mrc_switch;
78 break;
79 }
80 default: {
81 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
82 "switch case not processed\n");
83 break;
84 }
85 }
86 }
87
88 void rtl92se_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
89 {
90 struct rtl_priv *rtlpriv = rtl_priv(hw);
91 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
92 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
93 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
94 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
95 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
96
97 switch (variable) {
98 case HW_VAR_ETHER_ADDR:{
99 rtl_write_dword(rtlpriv, IDR0, ((u32 *)(val))[0]);
100 rtl_write_word(rtlpriv, IDR4, ((u16 *)(val + 4))[0]);
101 break;
102 }
103 case HW_VAR_BASIC_RATE:{
104 u16 rate_cfg = ((u16 *) val)[0];
105 u8 rate_index = 0;
106
107 if (rtlhal->version == VERSION_8192S_ACUT)
108 rate_cfg = rate_cfg & 0x150;
109 else
110 rate_cfg = rate_cfg & 0x15f;
111
112 rate_cfg |= 0x01;
113
114 rtl_write_byte(rtlpriv, RRSR, rate_cfg & 0xff);
115 rtl_write_byte(rtlpriv, RRSR + 1,
116 (rate_cfg >> 8) & 0xff);
117
118 while (rate_cfg > 0x1) {
119 rate_cfg = (rate_cfg >> 1);
120 rate_index++;
121 }
122 rtl_write_byte(rtlpriv, INIRTSMCS_SEL, rate_index);
123
124 break;
125 }
126 case HW_VAR_BSSID:{
127 rtl_write_dword(rtlpriv, BSSIDR, ((u32 *)(val))[0]);
128 rtl_write_word(rtlpriv, BSSIDR + 4,
129 ((u16 *)(val + 4))[0]);
130 break;
131 }
132 case HW_VAR_SIFS:{
133 rtl_write_byte(rtlpriv, SIFS_OFDM, val[0]);
134 rtl_write_byte(rtlpriv, SIFS_OFDM + 1, val[1]);
135 break;
136 }
137 case HW_VAR_SLOT_TIME:{
138 u8 e_aci;
139
140 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
141 "HW_VAR_SLOT_TIME %x\n", val[0]);
142
143 rtl_write_byte(rtlpriv, SLOT_TIME, val[0]);
144
145 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
146 rtlpriv->cfg->ops->set_hw_reg(hw,
147 HW_VAR_AC_PARAM,
148 (&e_aci));
149 }
150 break;
151 }
152 case HW_VAR_ACK_PREAMBLE:{
153 u8 reg_tmp;
154 u8 short_preamble = (bool) (*val);
155 reg_tmp = (mac->cur_40_prime_sc) << 5;
156 if (short_preamble)
157 reg_tmp |= 0x80;
158
159 rtl_write_byte(rtlpriv, RRSR + 2, reg_tmp);
160 break;
161 }
162 case HW_VAR_AMPDU_MIN_SPACE:{
163 u8 min_spacing_to_set;
164 u8 sec_min_space;
165
166 min_spacing_to_set = *val;
167 if (min_spacing_to_set <= 7) {
168 if (rtlpriv->sec.pairwise_enc_algorithm ==
169 NO_ENCRYPTION)
170 sec_min_space = 0;
171 else
172 sec_min_space = 1;
173
174 if (min_spacing_to_set < sec_min_space)
175 min_spacing_to_set = sec_min_space;
176 if (min_spacing_to_set > 5)
177 min_spacing_to_set = 5;
178
179 mac->min_space_cfg =
180 ((mac->min_space_cfg & 0xf8) |
181 min_spacing_to_set);
182
183 *val = min_spacing_to_set;
184
185 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
186 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
187 mac->min_space_cfg);
188
189 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
190 mac->min_space_cfg);
191 }
192 break;
193 }
194 case HW_VAR_SHORTGI_DENSITY:{
195 u8 density_to_set;
196
197 density_to_set = *val;
198 mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
199 mac->min_space_cfg |= (density_to_set << 3);
200
201 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
202 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
203 mac->min_space_cfg);
204
205 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
206 mac->min_space_cfg);
207
208 break;
209 }
210 case HW_VAR_AMPDU_FACTOR:{
211 u8 factor_toset;
212 u8 regtoset;
213 u8 factorlevel[18] = {
214 2, 4, 4, 7, 7, 13, 13,
215 13, 2, 7, 7, 13, 13,
216 15, 15, 15, 15, 0};
217 u8 index = 0;
218
219 factor_toset = *val;
220 if (factor_toset <= 3) {
221 factor_toset = (1 << (factor_toset + 2));
222 if (factor_toset > 0xf)
223 factor_toset = 0xf;
224
225 for (index = 0; index < 17; index++) {
226 if (factorlevel[index] > factor_toset)
227 factorlevel[index] =
228 factor_toset;
229 }
230
231 for (index = 0; index < 8; index++) {
232 regtoset = ((factorlevel[index * 2]) |
233 (factorlevel[index *
234 2 + 1] << 4));
235 rtl_write_byte(rtlpriv,
236 AGGLEN_LMT_L + index,
237 regtoset);
238 }
239
240 regtoset = ((factorlevel[16]) |
241 (factorlevel[17] << 4));
242 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, regtoset);
243
244 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
245 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
246 factor_toset);
247 }
248 break;
249 }
250 case HW_VAR_AC_PARAM:{
251 u8 e_aci = *val;
252 rtl92s_dm_init_edca_turbo(hw);
253
254 if (rtlpci->acm_method != EACMWAY2_SW)
255 rtlpriv->cfg->ops->set_hw_reg(hw,
256 HW_VAR_ACM_CTRL,
257 &e_aci);
258 break;
259 }
260 case HW_VAR_ACM_CTRL:{
261 u8 e_aci = *val;
262 union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)(&(
263 mac->ac[0].aifs));
264 u8 acm = p_aci_aifsn->f.acm;
265 u8 acm_ctrl = rtl_read_byte(rtlpriv, AcmHwCtrl);
266
267 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ?
268 0x0 : 0x1);
269
270 if (acm) {
271 switch (e_aci) {
272 case AC0_BE:
273 acm_ctrl |= AcmHw_BeqEn;
274 break;
275 case AC2_VI:
276 acm_ctrl |= AcmHw_ViqEn;
277 break;
278 case AC3_VO:
279 acm_ctrl |= AcmHw_VoqEn;
280 break;
281 default:
282 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
283 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
284 acm);
285 break;
286 }
287 } else {
288 switch (e_aci) {
289 case AC0_BE:
290 acm_ctrl &= (~AcmHw_BeqEn);
291 break;
292 case AC2_VI:
293 acm_ctrl &= (~AcmHw_ViqEn);
294 break;
295 case AC3_VO:
296 acm_ctrl &= (~AcmHw_VoqEn);
297 break;
298 default:
299 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
300 "switch case not processed\n");
301 break;
302 }
303 }
304
305 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
306 "HW_VAR_ACM_CTRL Write 0x%X\n", acm_ctrl);
307 rtl_write_byte(rtlpriv, AcmHwCtrl, acm_ctrl);
308 break;
309 }
310 case HW_VAR_RCR:{
311 rtl_write_dword(rtlpriv, RCR, ((u32 *) (val))[0]);
312 rtlpci->receive_config = ((u32 *) (val))[0];
313 break;
314 }
315 case HW_VAR_RETRY_LIMIT:{
316 u8 retry_limit = val[0];
317
318 rtl_write_word(rtlpriv, RETRY_LIMIT,
319 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
320 retry_limit << RETRY_LIMIT_LONG_SHIFT);
321 break;
322 }
323 case HW_VAR_DUAL_TSF_RST: {
324 break;
325 }
326 case HW_VAR_EFUSE_BYTES: {
327 rtlefuse->efuse_usedbytes = *((u16 *) val);
328 break;
329 }
330 case HW_VAR_EFUSE_USAGE: {
331 rtlefuse->efuse_usedpercentage = *val;
332 break;
333 }
334 case HW_VAR_IO_CMD: {
335 break;
336 }
337 case HW_VAR_WPA_CONFIG: {
338 rtl_write_byte(rtlpriv, REG_SECR, *val);
339 break;
340 }
341 case HW_VAR_SET_RPWM:{
342 break;
343 }
344 case HW_VAR_H2C_FW_PWRMODE:{
345 break;
346 }
347 case HW_VAR_FW_PSMODE_STATUS: {
348 ppsc->fw_current_inpsmode = *((bool *) val);
349 break;
350 }
351 case HW_VAR_H2C_FW_JOINBSSRPT:{
352 break;
353 }
354 case HW_VAR_AID:{
355 break;
356 }
357 case HW_VAR_CORRECT_TSF:{
358 break;
359 }
360 case HW_VAR_MRC: {
361 bool bmrc_toset = *((bool *)val);
362 u8 u1bdata = 0;
363
364 if (bmrc_toset) {
365 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
366 MASKBYTE0, 0x33);
367 u1bdata = (u8)rtl_get_bbreg(hw,
368 ROFDM1_TRXPATHENABLE,
369 MASKBYTE0);
370 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
371 MASKBYTE0,
372 ((u1bdata & 0xf0) | 0x03));
373 u1bdata = (u8)rtl_get_bbreg(hw,
374 ROFDM0_TRXPATHENABLE,
375 MASKBYTE1);
376 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
377 MASKBYTE1,
378 (u1bdata | 0x04));
379
380 /* Update current settings. */
381 rtlpriv->dm.current_mrc_switch = bmrc_toset;
382 } else {
383 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
384 MASKBYTE0, 0x13);
385 u1bdata = (u8)rtl_get_bbreg(hw,
386 ROFDM1_TRXPATHENABLE,
387 MASKBYTE0);
388 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
389 MASKBYTE0,
390 ((u1bdata & 0xf0) | 0x01));
391 u1bdata = (u8)rtl_get_bbreg(hw,
392 ROFDM0_TRXPATHENABLE,
393 MASKBYTE1);
394 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
395 MASKBYTE1, (u1bdata & 0xfb));
396
397 /* Update current settings. */
398 rtlpriv->dm.current_mrc_switch = bmrc_toset;
399 }
400
401 break;
402 }
403 case HW_VAR_FW_LPS_ACTION: {
404 bool enter_fwlps = *((bool *)val);
405 u8 rpwm_val, fw_pwrmode;
406 bool fw_current_inps;
407
408 if (enter_fwlps) {
409 rpwm_val = 0x02; /* RF off */
410 fw_current_inps = true;
411 rtlpriv->cfg->ops->set_hw_reg(hw,
412 HW_VAR_FW_PSMODE_STATUS,
413 (u8 *)(&fw_current_inps));
414 rtlpriv->cfg->ops->set_hw_reg(hw,
415 HW_VAR_H2C_FW_PWRMODE,
416 &ppsc->fwctrl_psmode);
417
418 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
419 &rpwm_val);
420 } else {
421 rpwm_val = 0x0C; /* RF on */
422 fw_pwrmode = FW_PS_ACTIVE_MODE;
423 fw_current_inps = false;
424 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
425 &rpwm_val);
426 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
427 &fw_pwrmode);
428
429 rtlpriv->cfg->ops->set_hw_reg(hw,
430 HW_VAR_FW_PSMODE_STATUS,
431 (u8 *)(&fw_current_inps));
432 }
433 break; }
434 default:
435 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
436 "switch case not processed\n");
437 break;
438 }
439
440 }
441
442 void rtl92se_enable_hw_security_config(struct ieee80211_hw *hw)
443 {
444 struct rtl_priv *rtlpriv = rtl_priv(hw);
445 u8 sec_reg_value = 0x0;
446
447 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
448 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
449 rtlpriv->sec.pairwise_enc_algorithm,
450 rtlpriv->sec.group_enc_algorithm);
451
452 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
453 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
454 "not open hw encryption\n");
455 return;
456 }
457
458 sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
459
460 if (rtlpriv->sec.use_defaultkey) {
461 sec_reg_value |= SCR_TXUSEDK;
462 sec_reg_value |= SCR_RXUSEDK;
463 }
464
465 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n",
466 sec_reg_value);
467
468 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
469
470 }
471
472 static u8 _rtl92se_halset_sysclk(struct ieee80211_hw *hw, u8 data)
473 {
474 struct rtl_priv *rtlpriv = rtl_priv(hw);
475 u8 waitcount = 100;
476 bool bresult = false;
477 u8 tmpvalue;
478
479 rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
480
481 /* Wait the MAC synchronized. */
482 udelay(400);
483
484 /* Check if it is set ready. */
485 tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
486 bresult = ((tmpvalue & BIT(7)) == (data & BIT(7)));
487
488 if ((data & (BIT(6) | BIT(7))) == false) {
489 waitcount = 100;
490 tmpvalue = 0;
491
492 while (1) {
493 waitcount--;
494
495 tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
496 if ((tmpvalue & BIT(6)))
497 break;
498
499 pr_err("wait for BIT(6) return value %x\n", tmpvalue);
500 if (waitcount == 0)
501 break;
502
503 udelay(10);
504 }
505
506 if (waitcount == 0)
507 bresult = false;
508 else
509 bresult = true;
510 }
511
512 return bresult;
513 }
514
515 void rtl8192se_gpiobit3_cfg_inputmode(struct ieee80211_hw *hw)
516 {
517 struct rtl_priv *rtlpriv = rtl_priv(hw);
518 u8 u1tmp;
519
520 /* The following config GPIO function */
521 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
522 u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
523
524 /* config GPIO3 to input */
525 u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
526 rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
527
528 }
529
530 static u8 _rtl92se_rf_onoff_detect(struct ieee80211_hw *hw)
531 {
532 struct rtl_priv *rtlpriv = rtl_priv(hw);
533 u8 u1tmp;
534 u8 retval = ERFON;
535
536 /* The following config GPIO function */
537 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
538 u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
539
540 /* config GPIO3 to input */
541 u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
542 rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
543
544 /* On some of the platform, driver cannot read correct
545 * value without delay between Write_GPIO_SEL and Read_GPIO_IN */
546 mdelay(10);
547
548 /* check GPIO3 */
549 u1tmp = rtl_read_byte(rtlpriv, GPIO_IN_SE);
550 retval = (u1tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? ERFON : ERFOFF;
551
552 return retval;
553 }
554
555 static void _rtl92se_macconfig_before_fwdownload(struct ieee80211_hw *hw)
556 {
557 struct rtl_priv *rtlpriv = rtl_priv(hw);
558 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
559 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
560
561 u8 i;
562 u8 tmpu1b;
563 u16 tmpu2b;
564 u8 pollingcnt = 20;
565
566 if (rtlpci->first_init) {
567 /* Reset PCIE Digital */
568 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
569 tmpu1b &= 0xFE;
570 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
571 udelay(1);
572 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b | BIT(0));
573 }
574
575 /* Switch to SW IO control */
576 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
577 if (tmpu1b & BIT(7)) {
578 tmpu1b &= ~(BIT(6) | BIT(7));
579
580 /* Set failed, return to prevent hang. */
581 if (!_rtl92se_halset_sysclk(hw, tmpu1b))
582 return;
583 }
584
585 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
586 udelay(50);
587 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
588 udelay(50);
589
590 /* Clear FW RPWM for FW control LPS.*/
591 rtl_write_byte(rtlpriv, RPWM, 0x0);
592
593 /* Reset MAC-IO and CPU and Core Digital BIT(10)/11/15 */
594 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
595 tmpu1b &= 0x73;
596 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
597 /* wait for BIT 10/11/15 to pull high automatically!! */
598 mdelay(1);
599
600 rtl_write_byte(rtlpriv, CMDR, 0);
601 rtl_write_byte(rtlpriv, TCR, 0);
602
603 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
604 tmpu1b = rtl_read_byte(rtlpriv, 0x562);
605 tmpu1b |= 0x08;
606 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
607 tmpu1b &= ~(BIT(3));
608 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
609
610 /* Enable AFE clock source */
611 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
612 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
613 /* Delay 1.5ms */
614 mdelay(2);
615 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
616 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
617
618 /* Enable AFE Macro Block's Bandgap */
619 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
620 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
621 mdelay(1);
622
623 /* Enable AFE Mbias */
624 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
625 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
626 mdelay(1);
627
628 /* Enable LDOA15 block */
629 tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
630 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
631
632 /* Set Digital Vdd to Retention isolation Path. */
633 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
634 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
635
636 /* For warm reboot NIC disappera bug. */
637 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
638 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
639
640 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
641
642 /* Enable AFE PLL Macro Block */
643 /* We need to delay 100u before enabling PLL. */
644 udelay(200);
645 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
646 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
647
648 /* for divider reset */
649 udelay(100);
650 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) |
651 BIT(4) | BIT(6)));
652 udelay(10);
653 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
654 udelay(10);
655
656 /* Enable MAC 80MHZ clock */
657 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
658 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
659 mdelay(1);
660
661 /* Release isolation AFE PLL & MD */
662 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
663
664 /* Enable MAC clock */
665 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
666 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
667
668 /* Enable Core digital and enable IOREG R/W */
669 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
670 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
671
672 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
673 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b & ~(BIT(7)));
674
675 /* enable REG_EN */
676 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
677
678 /* Switch the control path. */
679 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
680 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
681
682 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
683 tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
684 if (!_rtl92se_halset_sysclk(hw, tmpu1b))
685 return; /* Set failed, return to prevent hang. */
686
687 rtl_write_word(rtlpriv, CMDR, 0x07FC);
688
689 /* MH We must enable the section of code to prevent load IMEM fail. */
690 /* Load MAC register from WMAc temporarily We simulate macreg. */
691 /* txt HW will provide MAC txt later */
692 rtl_write_byte(rtlpriv, 0x6, 0x30);
693 rtl_write_byte(rtlpriv, 0x49, 0xf0);
694
695 rtl_write_byte(rtlpriv, 0x4b, 0x81);
696
697 rtl_write_byte(rtlpriv, 0xb5, 0x21);
698
699 rtl_write_byte(rtlpriv, 0xdc, 0xff);
700 rtl_write_byte(rtlpriv, 0xdd, 0xff);
701 rtl_write_byte(rtlpriv, 0xde, 0xff);
702 rtl_write_byte(rtlpriv, 0xdf, 0xff);
703
704 rtl_write_byte(rtlpriv, 0x11a, 0x00);
705 rtl_write_byte(rtlpriv, 0x11b, 0x00);
706
707 for (i = 0; i < 32; i++)
708 rtl_write_byte(rtlpriv, INIMCS_SEL + i, 0x1b);
709
710 rtl_write_byte(rtlpriv, 0x236, 0xff);
711
712 rtl_write_byte(rtlpriv, 0x503, 0x22);
713
714 if (ppsc->support_aspm && !ppsc->support_backdoor)
715 rtl_write_byte(rtlpriv, 0x560, 0x40);
716 else
717 rtl_write_byte(rtlpriv, 0x560, 0x00);
718
719 rtl_write_byte(rtlpriv, DBG_PORT, 0x91);
720
721 /* Set RX Desc Address */
722 rtl_write_dword(rtlpriv, RDQDA, rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
723 rtl_write_dword(rtlpriv, RCDA, rtlpci->rx_ring[RX_CMD_QUEUE].dma);
724
725 /* Set TX Desc Address */
726 rtl_write_dword(rtlpriv, TBKDA, rtlpci->tx_ring[BK_QUEUE].dma);
727 rtl_write_dword(rtlpriv, TBEDA, rtlpci->tx_ring[BE_QUEUE].dma);
728 rtl_write_dword(rtlpriv, TVIDA, rtlpci->tx_ring[VI_QUEUE].dma);
729 rtl_write_dword(rtlpriv, TVODA, rtlpci->tx_ring[VO_QUEUE].dma);
730 rtl_write_dword(rtlpriv, TBDA, rtlpci->tx_ring[BEACON_QUEUE].dma);
731 rtl_write_dword(rtlpriv, TCDA, rtlpci->tx_ring[TXCMD_QUEUE].dma);
732 rtl_write_dword(rtlpriv, TMDA, rtlpci->tx_ring[MGNT_QUEUE].dma);
733 rtl_write_dword(rtlpriv, THPDA, rtlpci->tx_ring[HIGH_QUEUE].dma);
734 rtl_write_dword(rtlpriv, HDA, rtlpci->tx_ring[HCCA_QUEUE].dma);
735
736 rtl_write_word(rtlpriv, CMDR, 0x37FC);
737
738 /* To make sure that TxDMA can ready to download FW. */
739 /* We should reset TxDMA if IMEM RPT was not ready. */
740 do {
741 tmpu1b = rtl_read_byte(rtlpriv, TCR);
742 if ((tmpu1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE)
743 break;
744
745 udelay(5);
746 } while (pollingcnt--);
747
748 if (pollingcnt <= 0) {
749 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
750 "Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n",
751 tmpu1b);
752 tmpu1b = rtl_read_byte(rtlpriv, CMDR);
753 rtl_write_byte(rtlpriv, CMDR, tmpu1b & (~TXDMA_EN));
754 udelay(2);
755 /* Reset TxDMA */
756 rtl_write_byte(rtlpriv, CMDR, tmpu1b | TXDMA_EN);
757 }
758
759 /* After MACIO reset,we must refresh LED state. */
760 if ((ppsc->rfoff_reason == RF_CHANGE_BY_IPS) ||
761 (ppsc->rfoff_reason == 0)) {
762 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
763 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
764 enum rf_pwrstate rfpwr_state_toset;
765 rfpwr_state_toset = _rtl92se_rf_onoff_detect(hw);
766
767 if (rfpwr_state_toset == ERFON)
768 rtl92se_sw_led_on(hw, pLed0);
769 }
770 }
771
772 static void _rtl92se_macconfig_after_fwdownload(struct ieee80211_hw *hw)
773 {
774 struct rtl_priv *rtlpriv = rtl_priv(hw);
775 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
776 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
777 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
778 u8 i;
779 u16 tmpu2b;
780
781 /* 1. System Configure Register (Offset: 0x0000 - 0x003F) */
782
783 /* 2. Command Control Register (Offset: 0x0040 - 0x004F) */
784 /* Turn on 0x40 Command register */
785 rtl_write_word(rtlpriv, CMDR, (BBRSTN | BB_GLB_RSTN |
786 SCHEDULE_EN | MACRXEN | MACTXEN | DDMA_EN | FW2HW_EN |
787 RXDMA_EN | TXDMA_EN | HCI_RXDMA_EN | HCI_TXDMA_EN));
788
789 /* Set TCR TX DMA pre 2 FULL enable bit */
790 rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) |
791 TXDMAPRE2FULL);
792
793 /* Set RCR */
794 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
795
796 /* 3. MACID Setting Register (Offset: 0x0050 - 0x007F) */
797
798 /* 4. Timing Control Register (Offset: 0x0080 - 0x009F) */
799 /* Set CCK/OFDM SIFS */
800 /* CCK SIFS shall always be 10us. */
801 rtl_write_word(rtlpriv, SIFS_CCK, 0x0a0a);
802 rtl_write_word(rtlpriv, SIFS_OFDM, 0x1010);
803
804 /* Set AckTimeout */
805 rtl_write_byte(rtlpriv, ACK_TIMEOUT, 0x40);
806
807 /* Beacon related */
808 rtl_write_word(rtlpriv, BCN_INTERVAL, 100);
809 rtl_write_word(rtlpriv, ATIMWND, 2);
810
811 /* 5. FIFO Control Register (Offset: 0x00A0 - 0x015F) */
812 /* 5.1 Initialize Number of Reserved Pages in Firmware Queue */
813 /* Firmware allocate now, associate with FW internal setting.!!! */
814
815 /* 5.2 Setting TX/RX page size 0/1/2/3/4=64/128/256/512/1024 */
816 /* 5.3 Set driver info, we only accept PHY status now. */
817 /* 5.4 Set RXDMA arbitration to control RXDMA/MAC/FW R/W for RXFIFO */
818 rtl_write_byte(rtlpriv, RXDMA, rtl_read_byte(rtlpriv, RXDMA) | BIT(6));
819
820 /* 6. Adaptive Control Register (Offset: 0x0160 - 0x01CF) */
821 /* Set RRSR to all legacy rate and HT rate
822 * CCK rate is supported by default.
823 * CCK rate will be filtered out only when associated
824 * AP does not support it.
825 * Only enable ACK rate to OFDM 24M
826 * Disable RRSR for CCK rate in A-Cut */
827
828 if (rtlhal->version == VERSION_8192S_ACUT)
829 rtl_write_byte(rtlpriv, RRSR, 0xf0);
830 else if (rtlhal->version == VERSION_8192S_BCUT)
831 rtl_write_byte(rtlpriv, RRSR, 0xff);
832 rtl_write_byte(rtlpriv, RRSR + 1, 0x01);
833 rtl_write_byte(rtlpriv, RRSR + 2, 0x00);
834
835 /* A-Cut IC do not support CCK rate. We forbid ARFR to */
836 /* fallback to CCK rate */
837 for (i = 0; i < 8; i++) {
838 /*Disable RRSR for CCK rate in A-Cut */
839 if (rtlhal->version == VERSION_8192S_ACUT)
840 rtl_write_dword(rtlpriv, ARFR0 + i * 4, 0x1f0ff0f0);
841 }
842
843 /* Different rate use different AMPDU size */
844 /* MCS32/ MCS15_SG use max AMPDU size 15*2=30K */
845 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, 0x0f);
846 /* MCS0/1/2/3 use max AMPDU size 4*2=8K */
847 rtl_write_word(rtlpriv, AGGLEN_LMT_L, 0x7442);
848 /* MCS4/5 use max AMPDU size 8*2=16K 6/7 use 10*2=20K */
849 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 2, 0xddd7);
850 /* MCS8/9 use max AMPDU size 8*2=16K 10/11 use 10*2=20K */
851 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 4, 0xd772);
852 /* MCS12/13/14/15 use max AMPDU size 15*2=30K */
853 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 6, 0xfffd);
854
855 /* Set Data / Response auto rate fallack retry count */
856 rtl_write_dword(rtlpriv, DARFRC, 0x04010000);
857 rtl_write_dword(rtlpriv, DARFRC + 4, 0x09070605);
858 rtl_write_dword(rtlpriv, RARFRC, 0x04010000);
859 rtl_write_dword(rtlpriv, RARFRC + 4, 0x09070605);
860
861 /* 7. EDCA Setting Register (Offset: 0x01D0 - 0x01FF) */
862 /* Set all rate to support SG */
863 rtl_write_word(rtlpriv, SG_RATE, 0xFFFF);
864
865 /* 8. WMAC, BA, and CCX related Register (Offset: 0x0200 - 0x023F) */
866 /* Set NAV protection length */
867 rtl_write_word(rtlpriv, NAV_PROT_LEN, 0x0080);
868 /* CF-END Threshold */
869 rtl_write_byte(rtlpriv, CFEND_TH, 0xFF);
870 /* Set AMPDU minimum space */
871 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 0x07);
872 /* Set TXOP stall control for several queue/HI/BCN/MGT/ */
873 rtl_write_byte(rtlpriv, TXOP_STALL_CTRL, 0x00);
874
875 /* 9. Security Control Register (Offset: 0x0240 - 0x025F) */
876 /* 10. Power Save Control Register (Offset: 0x0260 - 0x02DF) */
877 /* 11. General Purpose Register (Offset: 0x02E0 - 0x02FF) */
878 /* 12. Host Interrupt Status Register (Offset: 0x0300 - 0x030F) */
879 /* 13. Test Mode and Debug Control Register (Offset: 0x0310 - 0x034F) */
880
881 /* 14. Set driver info, we only accept PHY status now. */
882 rtl_write_byte(rtlpriv, RXDRVINFO_SZ, 4);
883
884 /* 15. For EEPROM R/W Workaround */
885 /* 16. For EFUSE to share REG_SYS_FUNC_EN with EEPROM!!! */
886 tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
887 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmpu2b | BIT(13));
888 tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
889 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, tmpu2b & (~BIT(8)));
890
891 /* 17. For EFUSE */
892 /* We may R/W EFUSE in EEPROM mode */
893 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
894 u8 tempval;
895
896 tempval = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL + 1);
897 tempval &= 0xFE;
898 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, tempval);
899
900 /* Change Program timing */
901 rtl_write_byte(rtlpriv, REG_EFUSE_CTRL + 3, 0x72);
902 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "EFUSE CONFIG OK\n");
903 }
904
905 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n");
906
907 }
908
909 static void _rtl92se_hw_configure(struct ieee80211_hw *hw)
910 {
911 struct rtl_priv *rtlpriv = rtl_priv(hw);
912 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
913 struct rtl_phy *rtlphy = &(rtlpriv->phy);
914 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
915
916 u8 reg_bw_opmode = 0;
917 u32 reg_rrsr = 0;
918 u8 regtmp = 0;
919
920 reg_bw_opmode = BW_OPMODE_20MHZ;
921 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
922
923 regtmp = rtl_read_byte(rtlpriv, INIRTSMCS_SEL);
924 reg_rrsr = ((reg_rrsr & 0x000fffff) << 8) | regtmp;
925 rtl_write_dword(rtlpriv, INIRTSMCS_SEL, reg_rrsr);
926 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
927
928 /* Set Retry Limit here */
929 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
930 (u8 *)(&rtlpci->shortretry_limit));
931
932 rtl_write_byte(rtlpriv, MLT, 0x8f);
933
934 /* For Min Spacing configuration. */
935 switch (rtlphy->rf_type) {
936 case RF_1T2R:
937 case RF_1T1R:
938 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
939 break;
940 case RF_2T2R:
941 case RF_2T2R_GREEN:
942 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
943 break;
944 }
945 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, rtlhal->minspace_cfg);
946 }
947
948 int rtl92se_hw_init(struct ieee80211_hw *hw)
949 {
950 struct rtl_priv *rtlpriv = rtl_priv(hw);
951 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
952 struct rtl_phy *rtlphy = &(rtlpriv->phy);
953 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
954 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
955 u8 tmp_byte = 0;
956 unsigned long flags;
957 bool rtstatus = true;
958 u8 tmp_u1b;
959 int err = false;
960 u8 i;
961 int wdcapra_add[] = {
962 EDCAPARA_BE, EDCAPARA_BK,
963 EDCAPARA_VI, EDCAPARA_VO};
964 u8 secr_value = 0x0;
965
966 rtlpci->being_init_adapter = true;
967
968 /* As this function can take a very long time (up to 350 ms)
969 * and can be called with irqs disabled, reenable the irqs
970 * to let the other devices continue being serviced.
971 *
972 * It is safe doing so since our own interrupts will only be enabled
973 * in a subsequent step.
974 */
975 local_save_flags(flags);
976 local_irq_enable();
977
978 rtlpriv->intf_ops->disable_aspm(hw);
979
980 /* 1. MAC Initialize */
981 /* Before FW download, we have to set some MAC register */
982 _rtl92se_macconfig_before_fwdownload(hw);
983
984 rtlhal->version = (enum version_8192s)((rtl_read_dword(rtlpriv,
985 PMC_FSM) >> 16) & 0xF);
986
987 rtl8192se_gpiobit3_cfg_inputmode(hw);
988
989 /* 2. download firmware */
990 rtstatus = rtl92s_download_fw(hw);
991 if (!rtstatus) {
992 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
993 "Failed to download FW. Init HW without FW now... "
994 "Please copy FW into /lib/firmware/rtlwifi\n");
995 err = 1;
996 goto exit;
997 }
998
999 /* After FW download, we have to reset MAC register */
1000 _rtl92se_macconfig_after_fwdownload(hw);
1001
1002 /*Retrieve default FW Cmd IO map. */
1003 rtlhal->fwcmd_iomap = rtl_read_word(rtlpriv, LBUS_MON_ADDR);
1004 rtlhal->fwcmd_ioparam = rtl_read_dword(rtlpriv, LBUS_ADDR_MASK);
1005
1006 /* 3. Initialize MAC/PHY Config by MACPHY_reg.txt */
1007 if (!rtl92s_phy_mac_config(hw)) {
1008 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "MAC Config failed\n");
1009 err = rtstatus;
1010 goto exit;
1011 }
1012
1013 /* because last function modify RCR, so we update
1014 * rcr var here, or TP will unstable for receive_config
1015 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1016 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1017 */
1018 rtlpci->receive_config = rtl_read_dword(rtlpriv, RCR);
1019 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1020 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
1021
1022 /* Make sure BB/RF write OK. We should prevent enter IPS. radio off. */
1023 /* We must set flag avoid BB/RF config period later!! */
1024 rtl_write_dword(rtlpriv, CMDR, 0x37FC);
1025
1026 /* 4. Initialize BB After MAC Config PHY_reg.txt, AGC_Tab.txt */
1027 if (!rtl92s_phy_bb_config(hw)) {
1028 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "BB Config failed\n");
1029 err = rtstatus;
1030 goto exit;
1031 }
1032
1033 /* 5. Initiailze RF RAIO_A.txt RF RAIO_B.txt */
1034 /* Before initalizing RF. We can not use FW to do RF-R/W. */
1035
1036 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1037
1038 /* Before RF-R/W we must execute the IO from Scott's suggestion. */
1039 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, 0xDB);
1040 if (rtlhal->version == VERSION_8192S_ACUT)
1041 rtl_write_byte(rtlpriv, SPS1_CTRL + 3, 0x07);
1042 else
1043 rtl_write_byte(rtlpriv, RF_CTRL, 0x07);
1044
1045 if (!rtl92s_phy_rf_config(hw)) {
1046 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RF Config failed\n");
1047 err = rtstatus;
1048 goto exit;
1049 }
1050
1051 /* After read predefined TXT, we must set BB/MAC/RF
1052 * register as our requirement */
1053
1054 rtlphy->rfreg_chnlval[0] = rtl92s_phy_query_rf_reg(hw,
1055 (enum radio_path)0,
1056 RF_CHNLBW,
1057 RFREG_OFFSET_MASK);
1058 rtlphy->rfreg_chnlval[1] = rtl92s_phy_query_rf_reg(hw,
1059 (enum radio_path)1,
1060 RF_CHNLBW,
1061 RFREG_OFFSET_MASK);
1062
1063 /*---- Set CCK and OFDM Block "ON"----*/
1064 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1065 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1066
1067 /*3 Set Hardware(Do nothing now) */
1068 _rtl92se_hw_configure(hw);
1069
1070 /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
1071 /* TX power index for different rate set. */
1072 /* Get original hw reg values */
1073 rtl92s_phy_get_hw_reg_originalvalue(hw);
1074 /* Write correct tx power index */
1075 rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1076
1077 /* We must set MAC address after firmware download. */
1078 for (i = 0; i < 6; i++)
1079 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1080
1081 /* EEPROM R/W workaround */
1082 tmp_u1b = rtl_read_byte(rtlpriv, MAC_PINMUX_CFG);
1083 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, tmp_u1b & (~BIT(3)));
1084
1085 rtl_write_byte(rtlpriv, 0x4d, 0x0);
1086
1087 if (hal_get_firmwareversion(rtlpriv) >= 0x49) {
1088 tmp_byte = rtl_read_byte(rtlpriv, FW_RSVD_PG_CRTL) & (~BIT(4));
1089 tmp_byte = tmp_byte | BIT(5);
1090 rtl_write_byte(rtlpriv, FW_RSVD_PG_CRTL, tmp_byte);
1091 rtl_write_dword(rtlpriv, TXDESC_MSK, 0xFFFFCFFF);
1092 }
1093
1094 /* We enable high power and RA related mechanism after NIC
1095 * initialized. */
1096 if (hal_get_firmwareversion(rtlpriv) >= 0x35) {
1097 /* Fw v.53 and later. */
1098 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_INIT);
1099 } else if (hal_get_firmwareversion(rtlpriv) == 0x34) {
1100 /* Fw v.52. */
1101 rtl_write_dword(rtlpriv, WFM5, FW_RA_INIT);
1102 rtl92s_phy_chk_fwcmd_iodone(hw);
1103 } else {
1104 /* Compatible earlier FW version. */
1105 rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET);
1106 rtl92s_phy_chk_fwcmd_iodone(hw);
1107 rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE);
1108 rtl92s_phy_chk_fwcmd_iodone(hw);
1109 rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH);
1110 rtl92s_phy_chk_fwcmd_iodone(hw);
1111 }
1112
1113 /* Add to prevent ASPM bug. */
1114 /* Always enable hst and NIC clock request. */
1115 rtl92s_phy_switch_ephy_parameter(hw);
1116
1117 /* Security related
1118 * 1. Clear all H/W keys.
1119 * 2. Enable H/W encryption/decryption. */
1120 rtl_cam_reset_all_entry(hw);
1121 secr_value |= SCR_TXENCENABLE;
1122 secr_value |= SCR_RXENCENABLE;
1123 secr_value |= SCR_NOSKMC;
1124 rtl_write_byte(rtlpriv, REG_SECR, secr_value);
1125
1126 for (i = 0; i < 4; i++)
1127 rtl_write_dword(rtlpriv, wdcapra_add[i], 0x5e4322);
1128
1129 if (rtlphy->rf_type == RF_1T2R) {
1130 bool mrc2set = true;
1131 /* Turn on B-Path */
1132 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC, (u8 *)&mrc2set);
1133 }
1134
1135 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_ON);
1136 rtl92s_dm_init(hw);
1137 exit:
1138 local_irq_restore(flags);
1139 rtlpci->being_init_adapter = false;
1140 return err;
1141 }
1142
1143 void rtl92se_set_mac_addr(struct rtl_io *io, const u8 *addr)
1144 {
1145 /* This is a stub. */
1146 }
1147
1148 void rtl92se_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1149 {
1150 struct rtl_priv *rtlpriv = rtl_priv(hw);
1151 u32 reg_rcr;
1152
1153 if (rtlpriv->psc.rfpwr_state != ERFON)
1154 return;
1155
1156 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1157
1158 if (check_bssid) {
1159 reg_rcr |= (RCR_CBSSID);
1160 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1161 } else if (!check_bssid) {
1162 reg_rcr &= (~RCR_CBSSID);
1163 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1164 }
1165
1166 }
1167
1168 static int _rtl92se_set_media_status(struct ieee80211_hw *hw,
1169 enum nl80211_iftype type)
1170 {
1171 struct rtl_priv *rtlpriv = rtl_priv(hw);
1172 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1173 u32 temp;
1174 bt_msr &= ~MSR_LINK_MASK;
1175
1176 switch (type) {
1177 case NL80211_IFTYPE_UNSPECIFIED:
1178 bt_msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
1179 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1180 "Set Network type to NO LINK!\n");
1181 break;
1182 case NL80211_IFTYPE_ADHOC:
1183 bt_msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
1184 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1185 "Set Network type to Ad Hoc!\n");
1186 break;
1187 case NL80211_IFTYPE_STATION:
1188 bt_msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
1189 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1190 "Set Network type to STA!\n");
1191 break;
1192 case NL80211_IFTYPE_AP:
1193 bt_msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
1194 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1195 "Set Network type to AP!\n");
1196 break;
1197 default:
1198 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1199 "Network type %d not supported!\n", type);
1200 return 1;
1201
1202 }
1203
1204 if (type != NL80211_IFTYPE_AP &&
1205 rtlpriv->mac80211.link_state < MAC80211_LINKED)
1206 bt_msr = rtl_read_byte(rtlpriv, MSR) & ~MSR_LINK_MASK;
1207 rtl_write_byte(rtlpriv, MSR, bt_msr);
1208
1209 temp = rtl_read_dword(rtlpriv, TCR);
1210 rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8)));
1211 rtl_write_dword(rtlpriv, TCR, temp | BIT(8));
1212
1213
1214 return 0;
1215 }
1216
1217 /* HW_VAR_MEDIA_STATUS & HW_VAR_CECHK_BSSID */
1218 int rtl92se_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1219 {
1220 struct rtl_priv *rtlpriv = rtl_priv(hw);
1221
1222 if (_rtl92se_set_media_status(hw, type))
1223 return -EOPNOTSUPP;
1224
1225 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1226 if (type != NL80211_IFTYPE_AP)
1227 rtl92se_set_check_bssid(hw, true);
1228 } else {
1229 rtl92se_set_check_bssid(hw, false);
1230 }
1231
1232 return 0;
1233 }
1234
1235 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1236 void rtl92se_set_qos(struct ieee80211_hw *hw, int aci)
1237 {
1238 struct rtl_priv *rtlpriv = rtl_priv(hw);
1239 rtl92s_dm_init_edca_turbo(hw);
1240
1241 switch (aci) {
1242 case AC1_BK:
1243 rtl_write_dword(rtlpriv, EDCAPARA_BK, 0xa44f);
1244 break;
1245 case AC0_BE:
1246 /* rtl_write_dword(rtlpriv, EDCAPARA_BE, u4b_ac_param); */
1247 break;
1248 case AC2_VI:
1249 rtl_write_dword(rtlpriv, EDCAPARA_VI, 0x5e4322);
1250 break;
1251 case AC3_VO:
1252 rtl_write_dword(rtlpriv, EDCAPARA_VO, 0x2f3222);
1253 break;
1254 default:
1255 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1256 break;
1257 }
1258 }
1259
1260 void rtl92se_enable_interrupt(struct ieee80211_hw *hw)
1261 {
1262 struct rtl_priv *rtlpriv = rtl_priv(hw);
1263 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1264
1265 rtl_write_dword(rtlpriv, INTA_MASK, rtlpci->irq_mask[0]);
1266 /* Support Bit 32-37(Assign as Bit 0-5) interrupt setting now */
1267 rtl_write_dword(rtlpriv, INTA_MASK + 4, rtlpci->irq_mask[1] & 0x3F);
1268 rtlpci->irq_enabled = true;
1269 }
1270
1271 void rtl92se_disable_interrupt(struct ieee80211_hw *hw)
1272 {
1273 struct rtl_priv *rtlpriv;
1274 struct rtl_pci *rtlpci;
1275
1276 rtlpriv = rtl_priv(hw);
1277 /* if firmware not available, no interrupts */
1278 if (!rtlpriv || !rtlpriv->max_fw_size)
1279 return;
1280 rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1281 rtl_write_dword(rtlpriv, INTA_MASK, 0);
1282 rtl_write_dword(rtlpriv, INTA_MASK + 4, 0);
1283 rtlpci->irq_enabled = false;
1284 }
1285
1286 static u8 _rtl92s_set_sysclk(struct ieee80211_hw *hw, u8 data)
1287 {
1288 struct rtl_priv *rtlpriv = rtl_priv(hw);
1289 u8 waitcnt = 100;
1290 bool result = false;
1291 u8 tmp;
1292
1293 rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
1294
1295 /* Wait the MAC synchronized. */
1296 udelay(400);
1297
1298 /* Check if it is set ready. */
1299 tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1300 result = ((tmp & BIT(7)) == (data & BIT(7)));
1301
1302 if ((data & (BIT(6) | BIT(7))) == false) {
1303 waitcnt = 100;
1304 tmp = 0;
1305
1306 while (1) {
1307 waitcnt--;
1308 tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1309
1310 if ((tmp & BIT(6)))
1311 break;
1312
1313 pr_err("wait for BIT(6) return value %x\n", tmp);
1314
1315 if (waitcnt == 0)
1316 break;
1317 udelay(10);
1318 }
1319
1320 if (waitcnt == 0)
1321 result = false;
1322 else
1323 result = true;
1324 }
1325
1326 return result;
1327 }
1328
1329 static void _rtl92s_phy_set_rfhalt(struct ieee80211_hw *hw)
1330 {
1331 struct rtl_priv *rtlpriv = rtl_priv(hw);
1332 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1333 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1334 u8 u1btmp;
1335
1336 if (rtlhal->driver_going2unload)
1337 rtl_write_byte(rtlpriv, 0x560, 0x0);
1338
1339 /* Power save for BB/RF */
1340 u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
1341 u1btmp |= BIT(0);
1342 rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
1343 rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
1344 rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
1345 rtl_write_word(rtlpriv, CMDR, 0x57FC);
1346 udelay(100);
1347 rtl_write_word(rtlpriv, CMDR, 0x77FC);
1348 rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
1349 udelay(10);
1350 rtl_write_word(rtlpriv, CMDR, 0x37FC);
1351 udelay(10);
1352 rtl_write_word(rtlpriv, CMDR, 0x77FC);
1353 udelay(10);
1354 rtl_write_word(rtlpriv, CMDR, 0x57FC);
1355 rtl_write_word(rtlpriv, CMDR, 0x0000);
1356
1357 if (rtlhal->driver_going2unload) {
1358 u1btmp = rtl_read_byte(rtlpriv, (REG_SYS_FUNC_EN + 1));
1359 u1btmp &= ~(BIT(0));
1360 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, u1btmp);
1361 }
1362
1363 u1btmp = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1364
1365 /* Add description. After switch control path. register
1366 * after page1 will be invisible. We can not do any IO
1367 * for register>0x40. After resume&MACIO reset, we need
1368 * to remember previous reg content. */
1369 if (u1btmp & BIT(7)) {
1370 u1btmp &= ~(BIT(6) | BIT(7));
1371 if (!_rtl92s_set_sysclk(hw, u1btmp)) {
1372 pr_err("Switch ctrl path fail\n");
1373 return;
1374 }
1375 }
1376
1377 /* Power save for MAC */
1378 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS &&
1379 !rtlhal->driver_going2unload) {
1380 /* enable LED function */
1381 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1382 /* SW/HW radio off or halt adapter!! For example S3/S4 */
1383 } else {
1384 /* LED function disable. Power range is about 8mA now. */
1385 /* if write 0xF1 disconnet_pci power
1386 * ifconfig wlan0 down power are both high 35:70 */
1387 /* if write oxF9 disconnet_pci power
1388 * ifconfig wlan0 down power are both low 12:45*/
1389 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1390 }
1391
1392 rtl_write_byte(rtlpriv, SYS_CLKR + 1, 0x70);
1393 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, 0x68);
1394 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x00);
1395 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1396 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, 0x0E);
1397 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1398
1399 }
1400
1401 static void _rtl92se_gen_refreshledstate(struct ieee80211_hw *hw)
1402 {
1403 struct rtl_priv *rtlpriv = rtl_priv(hw);
1404 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1405 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1406 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
1407
1408 if (rtlpci->up_first_time == 1)
1409 return;
1410
1411 if (rtlpriv->psc.rfoff_reason == RF_CHANGE_BY_IPS)
1412 rtl92se_sw_led_on(hw, pLed0);
1413 else
1414 rtl92se_sw_led_off(hw, pLed0);
1415 }
1416
1417
1418 static void _rtl92se_power_domain_init(struct ieee80211_hw *hw)
1419 {
1420 struct rtl_priv *rtlpriv = rtl_priv(hw);
1421 u16 tmpu2b;
1422 u8 tmpu1b;
1423
1424 rtlpriv->psc.pwrdomain_protect = true;
1425
1426 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1427 if (tmpu1b & BIT(7)) {
1428 tmpu1b &= ~(BIT(6) | BIT(7));
1429 if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1430 rtlpriv->psc.pwrdomain_protect = false;
1431 return;
1432 }
1433 }
1434
1435 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
1436 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1437
1438 /* Reset MAC-IO and CPU and Core Digital BIT10/11/15 */
1439 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1440
1441 /* If IPS we need to turn LED on. So we not
1442 * not disable BIT 3/7 of reg3. */
1443 if (rtlpriv->psc.rfoff_reason & (RF_CHANGE_BY_IPS | RF_CHANGE_BY_HW))
1444 tmpu1b &= 0xFB;
1445 else
1446 tmpu1b &= 0x73;
1447
1448 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
1449 /* wait for BIT 10/11/15 to pull high automatically!! */
1450 mdelay(1);
1451
1452 rtl_write_byte(rtlpriv, CMDR, 0);
1453 rtl_write_byte(rtlpriv, TCR, 0);
1454
1455 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
1456 tmpu1b = rtl_read_byte(rtlpriv, 0x562);
1457 tmpu1b |= 0x08;
1458 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1459 tmpu1b &= ~(BIT(3));
1460 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1461
1462 /* Enable AFE clock source */
1463 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
1464 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
1465 /* Delay 1.5ms */
1466 udelay(1500);
1467 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
1468 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
1469
1470 /* Enable AFE Macro Block's Bandgap */
1471 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1472 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
1473 mdelay(1);
1474
1475 /* Enable AFE Mbias */
1476 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1477 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
1478 mdelay(1);
1479
1480 /* Enable LDOA15 block */
1481 tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
1482 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
1483
1484 /* Set Digital Vdd to Retention isolation Path. */
1485 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
1486 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
1487
1488
1489 /* For warm reboot NIC disappera bug. */
1490 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1491 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
1492
1493 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
1494
1495 /* Enable AFE PLL Macro Block */
1496 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
1497 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
1498 /* Enable MAC 80MHZ clock */
1499 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
1500 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
1501 mdelay(1);
1502
1503 /* Release isolation AFE PLL & MD */
1504 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
1505
1506 /* Enable MAC clock */
1507 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1508 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
1509
1510 /* Enable Core digital and enable IOREG R/W */
1511 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1512 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
1513 /* enable REG_EN */
1514 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
1515
1516 /* Switch the control path. */
1517 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1518 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
1519
1520 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1521 tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
1522 if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1523 rtlpriv->psc.pwrdomain_protect = false;
1524 return;
1525 }
1526
1527 rtl_write_word(rtlpriv, CMDR, 0x37FC);
1528
1529 /* After MACIO reset,we must refresh LED state. */
1530 _rtl92se_gen_refreshledstate(hw);
1531
1532 rtlpriv->psc.pwrdomain_protect = false;
1533 }
1534
1535 void rtl92se_card_disable(struct ieee80211_hw *hw)
1536 {
1537 struct rtl_priv *rtlpriv = rtl_priv(hw);
1538 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1539 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1540 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1541 enum nl80211_iftype opmode;
1542 u8 wait = 30;
1543
1544 rtlpriv->intf_ops->enable_aspm(hw);
1545
1546 if (rtlpci->driver_is_goingto_unload ||
1547 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1548 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1549
1550 /* we should chnge GPIO to input mode
1551 * this will drop away current about 25mA*/
1552 rtl8192se_gpiobit3_cfg_inputmode(hw);
1553
1554 /* this is very important for ips power save */
1555 while (wait-- >= 10 && rtlpriv->psc.pwrdomain_protect) {
1556 if (rtlpriv->psc.pwrdomain_protect)
1557 mdelay(20);
1558 else
1559 break;
1560 }
1561
1562 mac->link_state = MAC80211_NOLINK;
1563 opmode = NL80211_IFTYPE_UNSPECIFIED;
1564 _rtl92se_set_media_status(hw, opmode);
1565
1566 _rtl92s_phy_set_rfhalt(hw);
1567 udelay(100);
1568 }
1569
1570 void rtl92se_interrupt_recognized(struct ieee80211_hw *hw, u32 *p_inta,
1571 u32 *p_intb)
1572 {
1573 struct rtl_priv *rtlpriv = rtl_priv(hw);
1574 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1575
1576 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1577 rtl_write_dword(rtlpriv, ISR, *p_inta);
1578
1579 *p_intb = rtl_read_dword(rtlpriv, ISR + 4) & rtlpci->irq_mask[1];
1580 rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1581 }
1582
1583 void rtl92se_set_beacon_related_registers(struct ieee80211_hw *hw)
1584 {
1585 struct rtl_priv *rtlpriv = rtl_priv(hw);
1586 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1587 u16 bcntime_cfg = 0;
1588 u16 bcn_cw = 6, bcn_ifs = 0xf;
1589 u16 atim_window = 2;
1590
1591 /* ATIM Window (in unit of TU). */
1592 rtl_write_word(rtlpriv, ATIMWND, atim_window);
1593
1594 /* Beacon interval (in unit of TU). */
1595 rtl_write_word(rtlpriv, BCN_INTERVAL, mac->beacon_interval);
1596
1597 /* DrvErlyInt (in unit of TU). (Time to send
1598 * interrupt to notify driver to change
1599 * beacon content) */
1600 rtl_write_word(rtlpriv, BCN_DRV_EARLY_INT, 10 << 4);
1601
1602 /* BcnDMATIM(in unit of us). Indicates the
1603 * time before TBTT to perform beacon queue DMA */
1604 rtl_write_word(rtlpriv, BCN_DMATIME, 256);
1605
1606 /* Force beacon frame transmission even
1607 * after receiving beacon frame from
1608 * other ad hoc STA */
1609 rtl_write_byte(rtlpriv, BCN_ERR_THRESH, 100);
1610
1611 /* Beacon Time Configuration */
1612 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1613 bcntime_cfg |= (bcn_cw << BCN_TCFG_CW_SHIFT);
1614
1615 /* TODO: bcn_ifs may required to be changed on ASIC */
1616 bcntime_cfg |= bcn_ifs << BCN_TCFG_IFS;
1617
1618 /*for beacon changed */
1619 rtl92s_phy_set_beacon_hwreg(hw, mac->beacon_interval);
1620 }
1621
1622 void rtl92se_set_beacon_interval(struct ieee80211_hw *hw)
1623 {
1624 struct rtl_priv *rtlpriv = rtl_priv(hw);
1625 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1626 u16 bcn_interval = mac->beacon_interval;
1627
1628 /* Beacon interval (in unit of TU). */
1629 rtl_write_word(rtlpriv, BCN_INTERVAL, bcn_interval);
1630 /* 2008.10.24 added by tynli for beacon changed. */
1631 rtl92s_phy_set_beacon_hwreg(hw, bcn_interval);
1632 }
1633
1634 void rtl92se_update_interrupt_mask(struct ieee80211_hw *hw,
1635 u32 add_msr, u32 rm_msr)
1636 {
1637 struct rtl_priv *rtlpriv = rtl_priv(hw);
1638 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1639
1640 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1641 add_msr, rm_msr);
1642
1643 if (add_msr)
1644 rtlpci->irq_mask[0] |= add_msr;
1645
1646 if (rm_msr)
1647 rtlpci->irq_mask[0] &= (~rm_msr);
1648
1649 rtl92se_disable_interrupt(hw);
1650 rtl92se_enable_interrupt(hw);
1651 }
1652
1653 static void _rtl8192se_get_IC_Inferiority(struct ieee80211_hw *hw)
1654 {
1655 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1656 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1657 u8 efuse_id;
1658
1659 rtlhal->ic_class = IC_INFERIORITY_A;
1660
1661 /* Only retrieving while using EFUSE. */
1662 if ((rtlefuse->epromtype == EEPROM_BOOT_EFUSE) &&
1663 !rtlefuse->autoload_failflag) {
1664 efuse_id = efuse_read_1byte(hw, EFUSE_IC_ID_OFFSET);
1665
1666 if (efuse_id == 0xfe)
1667 rtlhal->ic_class = IC_INFERIORITY_B;
1668 }
1669 }
1670
1671 static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw)
1672 {
1673 struct rtl_priv *rtlpriv = rtl_priv(hw);
1674 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1675 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1676 u16 i, usvalue;
1677 u16 eeprom_id;
1678 u8 tempval;
1679 u8 hwinfo[HWSET_MAX_SIZE_92S];
1680 u8 rf_path, index;
1681
1682 if (rtlefuse->epromtype == EEPROM_93C46) {
1683 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1684 "RTL819X Not boot from eeprom, check it !!\n");
1685 } else if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1686 rtl_efuse_shadow_map_update(hw);
1687
1688 memcpy((void *)hwinfo, (void *)
1689 &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1690 HWSET_MAX_SIZE_92S);
1691 }
1692
1693 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP",
1694 hwinfo, HWSET_MAX_SIZE_92S);
1695
1696 eeprom_id = *((u16 *)&hwinfo[0]);
1697 if (eeprom_id != RTL8190_EEPROM_ID) {
1698 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1699 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1700 rtlefuse->autoload_failflag = true;
1701 } else {
1702 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1703 rtlefuse->autoload_failflag = false;
1704 }
1705
1706 if (rtlefuse->autoload_failflag)
1707 return;
1708
1709 _rtl8192se_get_IC_Inferiority(hw);
1710
1711 /* Read IC Version && Channel Plan */
1712 /* VID, DID SE 0xA-D */
1713 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1714 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1715 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1716 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1717 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1718
1719 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1720 "EEPROMId = 0x%4x\n", eeprom_id);
1721 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1722 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
1723 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1724 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
1725 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1726 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
1727 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1728 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
1729
1730 for (i = 0; i < 6; i += 2) {
1731 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1732 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1733 }
1734
1735 for (i = 0; i < 6; i++)
1736 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1737
1738 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1739
1740 /* Get Tx Power Level by Channel */
1741 /* Read Tx power of Channel 1 ~ 14 from EEPROM. */
1742 /* 92S suupport RF A & B */
1743 for (rf_path = 0; rf_path < 2; rf_path++) {
1744 for (i = 0; i < 3; i++) {
1745 /* Read CCK RF A & B Tx power */
1746 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1747 hwinfo[EEPROM_TXPOWERBASE + rf_path * 3 + i];
1748
1749 /* Read OFDM RF A & B Tx power for 1T */
1750 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1751 hwinfo[EEPROM_TXPOWERBASE + 6 + rf_path * 3 + i];
1752
1753 /* Read OFDM RF A & B Tx power for 2T */
1754 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[rf_path][i]
1755 = hwinfo[EEPROM_TXPOWERBASE + 12 +
1756 rf_path * 3 + i];
1757 }
1758 }
1759
1760 for (rf_path = 0; rf_path < 2; rf_path++)
1761 for (i = 0; i < 3; i++)
1762 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1763 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1764 rf_path, i,
1765 rtlefuse->eeprom_chnlarea_txpwr_cck
1766 [rf_path][i]);
1767 for (rf_path = 0; rf_path < 2; rf_path++)
1768 for (i = 0; i < 3; i++)
1769 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1770 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1771 rf_path, i,
1772 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1773 [rf_path][i]);
1774 for (rf_path = 0; rf_path < 2; rf_path++)
1775 for (i = 0; i < 3; i++)
1776 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1777 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1778 rf_path, i,
1779 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1780 [rf_path][i]);
1781
1782 for (rf_path = 0; rf_path < 2; rf_path++) {
1783
1784 /* Assign dedicated channel tx power */
1785 for (i = 0; i < 14; i++) {
1786 /* channel 1~3 use the same Tx Power Level. */
1787 if (i < 3)
1788 index = 0;
1789 /* Channel 4-8 */
1790 else if (i < 8)
1791 index = 1;
1792 /* Channel 9-14 */
1793 else
1794 index = 2;
1795
1796 /* Record A & B CCK /OFDM - 1T/2T Channel area
1797 * tx power */
1798 rtlefuse->txpwrlevel_cck[rf_path][i] =
1799 rtlefuse->eeprom_chnlarea_txpwr_cck
1800 [rf_path][index];
1801 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1802 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1803 [rf_path][index];
1804 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1805 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1806 [rf_path][index];
1807 }
1808
1809 for (i = 0; i < 14; i++) {
1810 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1811 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1812 rf_path, i,
1813 rtlefuse->txpwrlevel_cck[rf_path][i],
1814 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1815 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1816 }
1817 }
1818
1819 for (rf_path = 0; rf_path < 2; rf_path++) {
1820 for (i = 0; i < 3; i++) {
1821 /* Read Power diff limit. */
1822 rtlefuse->eeprom_pwrgroup[rf_path][i] =
1823 hwinfo[EEPROM_TXPWRGROUP + rf_path * 3 + i];
1824 }
1825 }
1826
1827 for (rf_path = 0; rf_path < 2; rf_path++) {
1828 /* Fill Pwr group */
1829 for (i = 0; i < 14; i++) {
1830 /* Chanel 1-3 */
1831 if (i < 3)
1832 index = 0;
1833 /* Channel 4-8 */
1834 else if (i < 8)
1835 index = 1;
1836 /* Channel 9-13 */
1837 else
1838 index = 2;
1839
1840 rtlefuse->pwrgroup_ht20[rf_path][i] =
1841 (rtlefuse->eeprom_pwrgroup[rf_path][index] &
1842 0xf);
1843 rtlefuse->pwrgroup_ht40[rf_path][i] =
1844 ((rtlefuse->eeprom_pwrgroup[rf_path][index] &
1845 0xf0) >> 4);
1846
1847 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1848 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1849 rf_path, i,
1850 rtlefuse->pwrgroup_ht20[rf_path][i]);
1851 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1852 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1853 rf_path, i,
1854 rtlefuse->pwrgroup_ht40[rf_path][i]);
1855 }
1856 }
1857
1858 for (i = 0; i < 14; i++) {
1859 /* Read tx power difference between HT OFDM 20/40 MHZ */
1860 /* channel 1-3 */
1861 if (i < 3)
1862 index = 0;
1863 /* Channel 4-8 */
1864 else if (i < 8)
1865 index = 1;
1866 /* Channel 9-14 */
1867 else
1868 index = 2;
1869
1870 tempval = hwinfo[EEPROM_TX_PWR_HT20_DIFF + index] & 0xff;
1871 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1872 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1873 ((tempval >> 4) & 0xF);
1874
1875 /* Read OFDM<->HT tx power diff */
1876 /* Channel 1-3 */
1877 if (i < 3)
1878 index = 0;
1879 /* Channel 4-8 */
1880 else if (i < 8)
1881 index = 0x11;
1882 /* Channel 9-14 */
1883 else
1884 index = 1;
1885
1886 tempval = hwinfo[EEPROM_TX_PWR_OFDM_DIFF + index] & 0xff;
1887 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] =
1888 (tempval & 0xF);
1889 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1890 ((tempval >> 4) & 0xF);
1891
1892 tempval = hwinfo[TX_PWR_SAFETY_CHK];
1893 rtlefuse->txpwr_safetyflag = (tempval & 0x01);
1894 }
1895
1896 rtlefuse->eeprom_regulatory = 0;
1897 if (rtlefuse->eeprom_version >= 2) {
1898 /* BIT(0)~2 */
1899 if (rtlefuse->eeprom_version >= 4)
1900 rtlefuse->eeprom_regulatory =
1901 (hwinfo[EEPROM_REGULATORY] & 0x7);
1902 else /* BIT(0) */
1903 rtlefuse->eeprom_regulatory =
1904 (hwinfo[EEPROM_REGULATORY] & 0x1);
1905 }
1906 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1907 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1908
1909 for (i = 0; i < 14; i++)
1910 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1911 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1912 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1913 for (i = 0; i < 14; i++)
1914 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1915 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1916 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1917 for (i = 0; i < 14; i++)
1918 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1919 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1920 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1921 for (i = 0; i < 14; i++)
1922 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1923 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1924 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1925
1926 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1927 "TxPwrSafetyFlag = %d\n", rtlefuse->txpwr_safetyflag);
1928
1929 /* Read RF-indication and Tx Power gain
1930 * index diff of legacy to HT OFDM rate. */
1931 tempval = hwinfo[EEPROM_RFIND_POWERDIFF] & 0xff;
1932 rtlefuse->eeprom_txpowerdiff = tempval;
1933 rtlefuse->legacy_httxpowerdiff =
1934 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][0];
1935
1936 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1937 "TxPowerDiff = %#x\n", rtlefuse->eeprom_txpowerdiff);
1938
1939 /* Get TSSI value for each path. */
1940 usvalue = *(u16 *)&hwinfo[EEPROM_TSSI_A];
1941 rtlefuse->eeprom_tssi[RF90_PATH_A] = (u8)((usvalue & 0xff00) >> 8);
1942 usvalue = hwinfo[EEPROM_TSSI_B];
1943 rtlefuse->eeprom_tssi[RF90_PATH_B] = (u8)(usvalue & 0xff);
1944
1945 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1946 rtlefuse->eeprom_tssi[RF90_PATH_A],
1947 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1948
1949 /* Read antenna tx power offset of B/C/D to A from EEPROM */
1950 /* and read ThermalMeter from EEPROM */
1951 tempval = hwinfo[EEPROM_THERMALMETER];
1952 rtlefuse->eeprom_thermalmeter = tempval;
1953 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1954 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1955
1956 /* ThermalMeter, BIT(0)~3 for RFIC1, BIT(4)~7 for RFIC2 */
1957 rtlefuse->thermalmeter[0] = (rtlefuse->eeprom_thermalmeter & 0x1f);
1958 rtlefuse->tssi_13dbm = rtlefuse->eeprom_thermalmeter * 100;
1959
1960 /* Read CrystalCap from EEPROM */
1961 tempval = hwinfo[EEPROM_CRYSTALCAP] >> 4;
1962 rtlefuse->eeprom_crystalcap = tempval;
1963 /* CrystalCap, BIT(12)~15 */
1964 rtlefuse->crystalcap = rtlefuse->eeprom_crystalcap;
1965
1966 /* Read IC Version && Channel Plan */
1967 /* Version ID, Channel plan */
1968 rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN];
1969 rtlefuse->txpwr_fromeprom = true;
1970 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1971 "EEPROM ChannelPlan = 0x%4x\n", rtlefuse->eeprom_channelplan);
1972
1973 /* Read Customer ID or Board Type!!! */
1974 tempval = hwinfo[EEPROM_BOARDTYPE];
1975 /* Change RF type definition */
1976 if (tempval == 0)
1977 rtlphy->rf_type = RF_2T2R;
1978 else if (tempval == 1)
1979 rtlphy->rf_type = RF_1T2R;
1980 else if (tempval == 2)
1981 rtlphy->rf_type = RF_1T2R;
1982 else if (tempval == 3)
1983 rtlphy->rf_type = RF_1T1R;
1984
1985 /* 1T2R but 1SS (1x1 receive combining) */
1986 rtlefuse->b1x1_recvcombine = false;
1987 if (rtlphy->rf_type == RF_1T2R) {
1988 tempval = rtl_read_byte(rtlpriv, 0x07);
1989 if (!(tempval & BIT(0))) {
1990 rtlefuse->b1x1_recvcombine = true;
1991 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1992 "RF_TYPE=1T2R but only 1SS\n");
1993 }
1994 }
1995 rtlefuse->b1ss_support = rtlefuse->b1x1_recvcombine;
1996 rtlefuse->eeprom_oemid = *&hwinfo[EEPROM_CUSTOMID];
1997
1998 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x",
1999 rtlefuse->eeprom_oemid);
2000
2001 /* set channel paln to world wide 13 */
2002 rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
2003 }
2004
2005 void rtl92se_read_eeprom_info(struct ieee80211_hw *hw)
2006 {
2007 struct rtl_priv *rtlpriv = rtl_priv(hw);
2008 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2009 u8 tmp_u1b = 0;
2010
2011 tmp_u1b = rtl_read_byte(rtlpriv, EPROM_CMD);
2012
2013 if (tmp_u1b & BIT(4)) {
2014 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
2015 rtlefuse->epromtype = EEPROM_93C46;
2016 } else {
2017 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
2018 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2019 }
2020
2021 if (tmp_u1b & BIT(5)) {
2022 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2023 rtlefuse->autoload_failflag = false;
2024 _rtl92se_read_adapter_info(hw);
2025 } else {
2026 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
2027 rtlefuse->autoload_failflag = true;
2028 }
2029 }
2030
2031 static void rtl92se_update_hal_rate_table(struct ieee80211_hw *hw,
2032 struct ieee80211_sta *sta)
2033 {
2034 struct rtl_priv *rtlpriv = rtl_priv(hw);
2035 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2036 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2037 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2038 u32 ratr_value;
2039 u8 ratr_index = 0;
2040 u8 nmode = mac->ht_enable;
2041 u8 mimo_ps = IEEE80211_SMPS_OFF;
2042 u16 shortgi_rate = 0;
2043 u32 tmp_ratr_value = 0;
2044 u8 curtxbw_40mhz = mac->bw_40;
2045 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2046 1 : 0;
2047 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2048 1 : 0;
2049 enum wireless_mode wirelessmode = mac->mode;
2050
2051 if (rtlhal->current_bandtype == BAND_ON_5G)
2052 ratr_value = sta->supp_rates[1] << 4;
2053 else
2054 ratr_value = sta->supp_rates[0];
2055 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2056 ratr_value = 0xfff;
2057 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2058 sta->ht_cap.mcs.rx_mask[0] << 12);
2059 switch (wirelessmode) {
2060 case WIRELESS_MODE_B:
2061 ratr_value &= 0x0000000D;
2062 break;
2063 case WIRELESS_MODE_G:
2064 ratr_value &= 0x00000FF5;
2065 break;
2066 case WIRELESS_MODE_N_24G:
2067 case WIRELESS_MODE_N_5G:
2068 nmode = 1;
2069 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2070 ratr_value &= 0x0007F005;
2071 } else {
2072 u32 ratr_mask;
2073
2074 if (get_rf_type(rtlphy) == RF_1T2R ||
2075 get_rf_type(rtlphy) == RF_1T1R) {
2076 if (curtxbw_40mhz)
2077 ratr_mask = 0x000ff015;
2078 else
2079 ratr_mask = 0x000ff005;
2080 } else {
2081 if (curtxbw_40mhz)
2082 ratr_mask = 0x0f0ff015;
2083 else
2084 ratr_mask = 0x0f0ff005;
2085 }
2086
2087 ratr_value &= ratr_mask;
2088 }
2089 break;
2090 default:
2091 if (rtlphy->rf_type == RF_1T2R)
2092 ratr_value &= 0x000ff0ff;
2093 else
2094 ratr_value &= 0x0f0ff0ff;
2095
2096 break;
2097 }
2098
2099 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2100 ratr_value &= 0x0FFFFFFF;
2101 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2102 ratr_value &= 0x0FFFFFF0;
2103
2104 if (nmode && ((curtxbw_40mhz &&
2105 curshortgi_40mhz) || (!curtxbw_40mhz &&
2106 curshortgi_20mhz))) {
2107
2108 ratr_value |= 0x10000000;
2109 tmp_ratr_value = (ratr_value >> 12);
2110
2111 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2112 if ((1 << shortgi_rate) & tmp_ratr_value)
2113 break;
2114 }
2115
2116 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2117 (shortgi_rate << 4) | (shortgi_rate);
2118
2119 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2120 }
2121
2122 rtl_write_dword(rtlpriv, ARFR0 + ratr_index * 4, ratr_value);
2123 if (ratr_value & 0xfffff000)
2124 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_N);
2125 else
2126 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_BG);
2127
2128 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
2129 rtl_read_dword(rtlpriv, ARFR0));
2130 }
2131
2132 static void rtl92se_update_hal_rate_mask(struct ieee80211_hw *hw,
2133 struct ieee80211_sta *sta,
2134 u8 rssi_level)
2135 {
2136 struct rtl_priv *rtlpriv = rtl_priv(hw);
2137 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2138 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2139 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2140 struct rtl_sta_info *sta_entry = NULL;
2141 u32 ratr_bitmap;
2142 u8 ratr_index = 0;
2143 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
2144 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2145 1 : 0;
2146 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2147 1 : 0;
2148 enum wireless_mode wirelessmode = 0;
2149 bool shortgi = false;
2150 u32 ratr_value = 0;
2151 u8 shortgi_rate = 0;
2152 u32 mask = 0;
2153 u32 band = 0;
2154 bool bmulticast = false;
2155 u8 macid = 0;
2156 u8 mimo_ps = IEEE80211_SMPS_OFF;
2157
2158 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2159 wirelessmode = sta_entry->wireless_mode;
2160 if (mac->opmode == NL80211_IFTYPE_STATION)
2161 curtxbw_40mhz = mac->bw_40;
2162 else if (mac->opmode == NL80211_IFTYPE_AP ||
2163 mac->opmode == NL80211_IFTYPE_ADHOC)
2164 macid = sta->aid + 1;
2165
2166 if (rtlhal->current_bandtype == BAND_ON_5G)
2167 ratr_bitmap = sta->supp_rates[1] << 4;
2168 else
2169 ratr_bitmap = sta->supp_rates[0];
2170 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2171 ratr_bitmap = 0xfff;
2172 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2173 sta->ht_cap.mcs.rx_mask[0] << 12);
2174 switch (wirelessmode) {
2175 case WIRELESS_MODE_B:
2176 band |= WIRELESS_11B;
2177 ratr_index = RATR_INX_WIRELESS_B;
2178 if (ratr_bitmap & 0x0000000c)
2179 ratr_bitmap &= 0x0000000d;
2180 else
2181 ratr_bitmap &= 0x0000000f;
2182 break;
2183 case WIRELESS_MODE_G:
2184 band |= (WIRELESS_11G | WIRELESS_11B);
2185 ratr_index = RATR_INX_WIRELESS_GB;
2186
2187 if (rssi_level == 1)
2188 ratr_bitmap &= 0x00000f00;
2189 else if (rssi_level == 2)
2190 ratr_bitmap &= 0x00000ff0;
2191 else
2192 ratr_bitmap &= 0x00000ff5;
2193 break;
2194 case WIRELESS_MODE_A:
2195 band |= WIRELESS_11A;
2196 ratr_index = RATR_INX_WIRELESS_A;
2197 ratr_bitmap &= 0x00000ff0;
2198 break;
2199 case WIRELESS_MODE_N_24G:
2200 case WIRELESS_MODE_N_5G:
2201 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2202 ratr_index = RATR_INX_WIRELESS_NGB;
2203
2204 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2205 if (rssi_level == 1)
2206 ratr_bitmap &= 0x00070000;
2207 else if (rssi_level == 2)
2208 ratr_bitmap &= 0x0007f000;
2209 else
2210 ratr_bitmap &= 0x0007f005;
2211 } else {
2212 if (rtlphy->rf_type == RF_1T2R ||
2213 rtlphy->rf_type == RF_1T1R) {
2214 if (rssi_level == 1) {
2215 ratr_bitmap &= 0x000f0000;
2216 } else if (rssi_level == 3) {
2217 ratr_bitmap &= 0x000fc000;
2218 } else if (rssi_level == 5) {
2219 ratr_bitmap &= 0x000ff000;
2220 } else {
2221 if (curtxbw_40mhz)
2222 ratr_bitmap &= 0x000ff015;
2223 else
2224 ratr_bitmap &= 0x000ff005;
2225 }
2226 } else {
2227 if (rssi_level == 1) {
2228 ratr_bitmap &= 0x0f8f0000;
2229 } else if (rssi_level == 3) {
2230 ratr_bitmap &= 0x0f8fc000;
2231 } else if (rssi_level == 5) {
2232 ratr_bitmap &= 0x0f8ff000;
2233 } else {
2234 if (curtxbw_40mhz)
2235 ratr_bitmap &= 0x0f8ff015;
2236 else
2237 ratr_bitmap &= 0x0f8ff005;
2238 }
2239 }
2240 }
2241
2242 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2243 (!curtxbw_40mhz && curshortgi_20mhz)) {
2244 if (macid == 0)
2245 shortgi = true;
2246 else if (macid == 1)
2247 shortgi = false;
2248 }
2249 break;
2250 default:
2251 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2252 ratr_index = RATR_INX_WIRELESS_NGB;
2253
2254 if (rtlphy->rf_type == RF_1T2R)
2255 ratr_bitmap &= 0x000ff0ff;
2256 else
2257 ratr_bitmap &= 0x0f8ff0ff;
2258 break;
2259 }
2260 sta_entry->ratr_index = ratr_index;
2261
2262 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2263 ratr_bitmap &= 0x0FFFFFFF;
2264 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2265 ratr_bitmap &= 0x0FFFFFF0;
2266
2267 if (shortgi) {
2268 ratr_bitmap |= 0x10000000;
2269 /* Get MAX MCS available. */
2270 ratr_value = (ratr_bitmap >> 12);
2271 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2272 if ((1 << shortgi_rate) & ratr_value)
2273 break;
2274 }
2275
2276 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2277 (shortgi_rate << 4) | (shortgi_rate);
2278 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2279 }
2280
2281 mask |= (bmulticast ? 1 : 0) << 9 | (macid & 0x1f) << 4 | (band & 0xf);
2282
2283 RT_TRACE(rtlpriv, COMP_RATR, DBG_TRACE, "mask = %x, bitmap = %x\n",
2284 mask, ratr_bitmap);
2285 rtl_write_dword(rtlpriv, 0x2c4, ratr_bitmap);
2286 rtl_write_dword(rtlpriv, WFM5, (FW_RA_UPDATE_MASK | (mask << 8)));
2287
2288 if (macid != 0)
2289 sta_entry->ratr_index = ratr_index;
2290 }
2291
2292 void rtl92se_update_hal_rate_tbl(struct ieee80211_hw *hw,
2293 struct ieee80211_sta *sta, u8 rssi_level)
2294 {
2295 struct rtl_priv *rtlpriv = rtl_priv(hw);
2296
2297 if (rtlpriv->dm.useramask)
2298 rtl92se_update_hal_rate_mask(hw, sta, rssi_level);
2299 else
2300 rtl92se_update_hal_rate_table(hw, sta);
2301 }
2302
2303 void rtl92se_update_channel_access_setting(struct ieee80211_hw *hw)
2304 {
2305 struct rtl_priv *rtlpriv = rtl_priv(hw);
2306 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2307 u16 sifs_timer;
2308
2309 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2310 &mac->slot_time);
2311 sifs_timer = 0x0e0e;
2312 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2313
2314 }
2315
2316 /* this ifunction is for RFKILL, it's different with windows,
2317 * because UI will disable wireless when GPIO Radio Off.
2318 * And here we not check or Disable/Enable ASPM like windows*/
2319 bool rtl92se_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2320 {
2321 struct rtl_priv *rtlpriv = rtl_priv(hw);
2322 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2323 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2324 enum rf_pwrstate rfpwr_toset /*, cur_rfstate */;
2325 unsigned long flag = 0;
2326 bool actuallyset = false;
2327 bool turnonbypowerdomain = false;
2328
2329 /* just 8191se can check gpio before firstup, 92c/92d have fixed it */
2330 if ((rtlpci->up_first_time == 1) || (rtlpci->being_init_adapter))
2331 return false;
2332
2333 if (ppsc->swrf_processing)
2334 return false;
2335
2336 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2337 if (ppsc->rfchange_inprogress) {
2338 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2339 return false;
2340 } else {
2341 ppsc->rfchange_inprogress = true;
2342 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2343 }
2344
2345 /* cur_rfstate = ppsc->rfpwr_state;*/
2346
2347 /* because after _rtl92s_phy_set_rfhalt, all power
2348 * closed, so we must open some power for GPIO check,
2349 * or we will always check GPIO RFOFF here,
2350 * And we should close power after GPIO check */
2351 if (RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
2352 _rtl92se_power_domain_init(hw);
2353 turnonbypowerdomain = true;
2354 }
2355
2356 rfpwr_toset = _rtl92se_rf_onoff_detect(hw);
2357
2358 if ((ppsc->hwradiooff) && (rfpwr_toset == ERFON)) {
2359 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2360 "RFKILL-HW Radio ON, RF ON\n");
2361
2362 rfpwr_toset = ERFON;
2363 ppsc->hwradiooff = false;
2364 actuallyset = true;
2365 } else if ((!ppsc->hwradiooff) && (rfpwr_toset == ERFOFF)) {
2366 RT_TRACE(rtlpriv, COMP_RF,
2367 DBG_DMESG, "RFKILL-HW Radio OFF, RF OFF\n");
2368
2369 rfpwr_toset = ERFOFF;
2370 ppsc->hwradiooff = true;
2371 actuallyset = true;
2372 }
2373
2374 if (actuallyset) {
2375 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2376 ppsc->rfchange_inprogress = false;
2377 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2378
2379 /* this not include ifconfig wlan0 down case */
2380 /* } else if (rfpwr_toset == ERFOFF || cur_rfstate == ERFOFF) { */
2381 } else {
2382 /* because power_domain_init may be happen when
2383 * _rtl92s_phy_set_rfhalt, this will open some powers
2384 * and cause current increasing about 40 mA for ips,
2385 * rfoff and ifconfig down, so we set
2386 * _rtl92s_phy_set_rfhalt again here */
2387 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC &&
2388 turnonbypowerdomain) {
2389 _rtl92s_phy_set_rfhalt(hw);
2390 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2391 }
2392
2393 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2394 ppsc->rfchange_inprogress = false;
2395 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2396 }
2397
2398 *valid = 1;
2399 return !ppsc->hwradiooff;
2400
2401 }
2402
2403 /* Is_wepkey just used for WEP used as group & pairwise key
2404 * if pairwise is AES ang group is WEP Is_wepkey == false.*/
2405 void rtl92se_set_key(struct ieee80211_hw *hw, u32 key_index, u8 *p_macaddr,
2406 bool is_group, u8 enc_algo, bool is_wepkey, bool clear_all)
2407 {
2408 struct rtl_priv *rtlpriv = rtl_priv(hw);
2409 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2410 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2411 u8 *macaddr = p_macaddr;
2412
2413 u32 entry_id = 0;
2414 bool is_pairwise = false;
2415
2416 static u8 cam_const_addr[4][6] = {
2417 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2418 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2419 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2420 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2421 };
2422 static u8 cam_const_broad[] = {
2423 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2424 };
2425
2426 if (clear_all) {
2427 u8 idx = 0;
2428 u8 cam_offset = 0;
2429 u8 clear_number = 5;
2430
2431 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2432
2433 for (idx = 0; idx < clear_number; idx++) {
2434 rtl_cam_mark_invalid(hw, cam_offset + idx);
2435 rtl_cam_empty_entry(hw, cam_offset + idx);
2436
2437 if (idx < 5) {
2438 memset(rtlpriv->sec.key_buf[idx], 0,
2439 MAX_KEY_LEN);
2440 rtlpriv->sec.key_len[idx] = 0;
2441 }
2442 }
2443
2444 } else {
2445 switch (enc_algo) {
2446 case WEP40_ENCRYPTION:
2447 enc_algo = CAM_WEP40;
2448 break;
2449 case WEP104_ENCRYPTION:
2450 enc_algo = CAM_WEP104;
2451 break;
2452 case TKIP_ENCRYPTION:
2453 enc_algo = CAM_TKIP;
2454 break;
2455 case AESCCMP_ENCRYPTION:
2456 enc_algo = CAM_AES;
2457 break;
2458 default:
2459 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2460 "switch case not processed\n");
2461 enc_algo = CAM_TKIP;
2462 break;
2463 }
2464
2465 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2466 macaddr = cam_const_addr[key_index];
2467 entry_id = key_index;
2468 } else {
2469 if (is_group) {
2470 macaddr = cam_const_broad;
2471 entry_id = key_index;
2472 } else {
2473 if (mac->opmode == NL80211_IFTYPE_AP) {
2474 entry_id = rtl_cam_get_free_entry(hw,
2475 p_macaddr);
2476 if (entry_id >= TOTAL_CAM_ENTRY) {
2477 RT_TRACE(rtlpriv,
2478 COMP_SEC, DBG_EMERG,
2479 "Can not find free hw security cam entry\n");
2480 return;
2481 }
2482 } else {
2483 entry_id = CAM_PAIRWISE_KEY_POSITION;
2484 }
2485
2486 key_index = PAIRWISE_KEYIDX;
2487 is_pairwise = true;
2488 }
2489 }
2490
2491 if (rtlpriv->sec.key_len[key_index] == 0) {
2492 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2493 "delete one entry, entry_id is %d\n",
2494 entry_id);
2495 if (mac->opmode == NL80211_IFTYPE_AP)
2496 rtl_cam_del_entry(hw, p_macaddr);
2497 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2498 } else {
2499 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2500 "add one entry\n");
2501 if (is_pairwise) {
2502 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2503 "set Pairwise key\n");
2504
2505 rtl_cam_add_one_entry(hw, macaddr, key_index,
2506 entry_id, enc_algo,
2507 CAM_CONFIG_NO_USEDK,
2508 rtlpriv->sec.key_buf[key_index]);
2509 } else {
2510 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2511 "set group key\n");
2512
2513 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2514 rtl_cam_add_one_entry(hw,
2515 rtlefuse->dev_addr,
2516 PAIRWISE_KEYIDX,
2517 CAM_PAIRWISE_KEY_POSITION,
2518 enc_algo, CAM_CONFIG_NO_USEDK,
2519 rtlpriv->sec.key_buf[entry_id]);
2520 }
2521
2522 rtl_cam_add_one_entry(hw, macaddr, key_index,
2523 entry_id, enc_algo,
2524 CAM_CONFIG_NO_USEDK,
2525 rtlpriv->sec.key_buf[entry_id]);
2526 }
2527
2528 }
2529 }
2530 }
2531
2532 void rtl92se_suspend(struct ieee80211_hw *hw)
2533 {
2534 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2535
2536 rtlpci->up_first_time = true;
2537 }
2538
2539 void rtl92se_resume(struct ieee80211_hw *hw)
2540 {
2541 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2542 u32 val;
2543
2544 pci_read_config_dword(rtlpci->pdev, 0x40, &val);
2545 if ((val & 0x0000ff00) != 0)
2546 pci_write_config_dword(rtlpci->pdev, 0x40,
2547 val & 0xffff00ff);
2548 }
Linux kernel - Deliverables
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