1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
26 #ifndef __RTL_WIFI_H__
27 #define __RTL_WIFI_H__
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sched.h>
32 #include <linux/firmware.h>
33 #include <linux/etherdevice.h>
34 #include <linux/vmalloc.h>
35 #include <linux/usb.h>
36 #include <net/mac80211.h>
37 #include <linux/completion.h>
40 #define MASKBYTE0 0xff
41 #define MASKBYTE1 0xff00
42 #define MASKBYTE2 0xff0000
43 #define MASKBYTE3 0xff000000
44 #define MASKHWORD 0xffff0000
45 #define MASKLWORD 0x0000ffff
46 #define MASKDWORD 0xffffffff
47 #define MASK12BITS 0xfff
48 #define MASKH4BITS 0xf0000000
49 #define MASKOFDM_D 0xffc00000
50 #define MASKCCK 0x3f3f3f3f
52 #define MASK4BITS 0x0f
53 #define MASK20BITS 0xfffff
54 #define RFREG_OFFSET_MASK 0xfffff
56 #define MASKBYTE0 0xff
57 #define MASKBYTE1 0xff00
58 #define MASKBYTE2 0xff0000
59 #define MASKBYTE3 0xff000000
60 #define MASKHWORD 0xffff0000
61 #define MASKLWORD 0x0000ffff
62 #define MASKDWORD 0xffffffff
63 #define MASK12BITS 0xfff
64 #define MASKH4BITS 0xf0000000
65 #define MASKOFDM_D 0xffc00000
66 #define MASKCCK 0x3f3f3f3f
68 #define MASK4BITS 0x0f
69 #define MASK20BITS 0xfffff
70 #define RFREG_OFFSET_MASK 0xfffff
72 #define RF_CHANGE_BY_INIT 0
73 #define RF_CHANGE_BY_IPS BIT(28)
74 #define RF_CHANGE_BY_PS BIT(29)
75 #define RF_CHANGE_BY_HW BIT(30)
76 #define RF_CHANGE_BY_SW BIT(31)
78 #define IQK_ADDA_REG_NUM 16
79 #define IQK_MAC_REG_NUM 4
80 #define IQK_THRESHOLD 8
82 #define MAX_KEY_LEN 61
83 #define KEY_BUF_SIZE 5
86 /*aci: 0x00 Best Effort*/
87 /*aci: 0x01 Background*/
90 /*Max: define total number.*/
96 #define QOS_QUEUE_NUM 4
97 #define RTL_MAC80211_NUM_QUEUE 5
98 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254
99 #define RTL_USB_MAX_RX_COUNT 100
100 #define QBSS_LOAD_SIZE 5
101 #define MAX_WMMELE_LENGTH 64
103 #define TOTAL_CAM_ENTRY 32
105 /*slot time for 11g. */
106 #define RTL_SLOT_TIME_9 9
107 #define RTL_SLOT_TIME_20 20
109 /*related to tcp/ip. */
111 #define PROTOC_TYPE_SIZE 2
113 /*related with 802.11 frame*/
114 #define MAC80211_3ADDR_LEN 24
115 #define MAC80211_4ADDR_LEN 30
117 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
118 #define CHANNEL_MAX_NUMBER_2G 14
119 #define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to
120 *"phy_GetChnlGroup8812A" and
121 * "Hal_ReadTxPowerInfo8812A"
123 #define CHANNEL_MAX_NUMBER_5G_80M 7
124 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
125 #define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to
126 *"phy_GetChnlGroup8812A" and
127 * "Hal_ReadTxPowerInfo8812A"
129 #define CHANNEL_MAX_NUMBER_5G_80M 7
130 #define MAX_PG_GROUP 13
131 #define CHANNEL_GROUP_MAX_2G 3
132 #define CHANNEL_GROUP_IDX_5GL 3
133 #define CHANNEL_GROUP_IDX_5GM 6
134 #define CHANNEL_GROUP_IDX_5GH 9
135 #define CHANNEL_GROUP_MAX_5G 9
136 #define CHANNEL_MAX_NUMBER_2G 14
137 #define AVG_THERMAL_NUM 8
138 #define AVG_THERMAL_NUM_88E 4
139 #define AVG_THERMAL_NUM_8723BE 4
140 #define MAX_TID_COUNT 9
146 enum rtl8192c_h2c_cmd
{
153 H2C_MACID_PS_MODE
= 7,
154 H2C_P2P_PS_OFFLOAD
= 8,
155 H2C_MAC_MODE_SEL
= 9,
157 H2C_P2P_PS_CTW_CMD
= 24,
161 #define MAX_TX_COUNT 4
162 #define MAX_REGULATION_NUM 4
163 #define MAX_RF_PATH_NUM 4
164 #define MAX_RATE_SECTION_NUM 6
165 #define MAX_2_4G_BANDWITH_NUM 4
166 #define MAX_5G_BANDWITH_NUM 4
167 #define MAX_RF_PATH 4
168 #define MAX_CHNL_GROUP_24G 6
169 #define MAX_CHNL_GROUP_5G 14
171 #define TX_PWR_BY_RATE_NUM_BAND 2
172 #define TX_PWR_BY_RATE_NUM_RF 4
173 #define TX_PWR_BY_RATE_NUM_SECTION 12
174 #define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6
175 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5
177 #define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
179 #define DEL_SW_IDX_SZ 30
182 /* For now, it's just for 8192ee
183 * but not OK yet, keep it 0
185 #define DMA_IS_64BIT 0
186 #define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
192 RF_TX_NUM_NONIMPLEMENT
,
195 #define PACKET_NORMAL 0
196 #define PACKET_DHCP 1
198 #define PACKET_EAPOL 3
200 #define MAX_SUPPORT_WOL_PATTERN_NUM 16
201 #define RSVD_WOL_PATTERN_NUM 1
202 #define WKFMCAM_ADDR_NUM 6
203 #define WKFMCAM_SIZE 24
205 #define MAX_WOL_BIT_MASK_SIZE 16
206 /* MIN LEN keeps 13 here */
207 #define MIN_WOL_PATTERN_SIZE 13
208 #define MAX_WOL_PATTERN_SIZE 128
210 #define WAKE_ON_MAGIC_PACKET BIT(0)
211 #define WAKE_ON_PATTERN_MATCH BIT(1)
213 #define WOL_REASON_PTK_UPDATE BIT(0)
214 #define WOL_REASON_GTK_UPDATE BIT(1)
215 #define WOL_REASON_DISASSOC BIT(2)
216 #define WOL_REASON_DEAUTH BIT(3)
217 #define WOL_REASON_AP_LOST BIT(4)
218 #define WOL_REASON_MAGIC_PKT BIT(5)
219 #define WOL_REASON_UNICAST_PKT BIT(6)
220 #define WOL_REASON_PATTERN_PKT BIT(7)
221 #define WOL_REASON_RTD3_SSID_MATCH BIT(8)
222 #define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9)
223 #define WOL_REASON_REALWOW_V2_ACKLOST BIT(10)
225 struct rtlwifi_firmware_header
{
244 struct txpower_info_2g
{
245 u8 index_cck_base
[MAX_RF_PATH
][MAX_CHNL_GROUP_24G
];
246 u8 index_bw40_base
[MAX_RF_PATH
][MAX_CHNL_GROUP_24G
];
247 /*If only one tx, only BW20 and OFDM are used.*/
248 u8 cck_diff
[MAX_RF_PATH
][MAX_TX_COUNT
];
249 u8 ofdm_diff
[MAX_RF_PATH
][MAX_TX_COUNT
];
250 u8 bw20_diff
[MAX_RF_PATH
][MAX_TX_COUNT
];
251 u8 bw40_diff
[MAX_RF_PATH
][MAX_TX_COUNT
];
252 u8 bw80_diff
[MAX_RF_PATH
][MAX_TX_COUNT
];
253 u8 bw160_diff
[MAX_RF_PATH
][MAX_TX_COUNT
];
256 struct txpower_info_5g
{
257 u8 index_bw40_base
[MAX_RF_PATH
][MAX_CHNL_GROUP_5G
];
258 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
259 u8 ofdm_diff
[MAX_RF_PATH
][MAX_TX_COUNT
];
260 u8 bw20_diff
[MAX_RF_PATH
][MAX_TX_COUNT
];
261 u8 bw40_diff
[MAX_RF_PATH
][MAX_TX_COUNT
];
262 u8 bw80_diff
[MAX_RF_PATH
][MAX_TX_COUNT
];
263 u8 bw160_diff
[MAX_RF_PATH
][MAX_TX_COUNT
];
287 enum regulation_txpwr_lmt
{
293 TXPWR_LMT_MAX_REGULATION_NUM
= 4
296 enum rt_eeprom_type
{
303 RTL_STATUS_INTERFACE_START
= 0,
307 HARDWARE_TYPE_RTL8192E
,
308 HARDWARE_TYPE_RTL8192U
,
309 HARDWARE_TYPE_RTL8192SE
,
310 HARDWARE_TYPE_RTL8192SU
,
311 HARDWARE_TYPE_RTL8192CE
,
312 HARDWARE_TYPE_RTL8192CU
,
313 HARDWARE_TYPE_RTL8192DE
,
314 HARDWARE_TYPE_RTL8192DU
,
315 HARDWARE_TYPE_RTL8723AE
,
316 HARDWARE_TYPE_RTL8723U
,
317 HARDWARE_TYPE_RTL8188EE
,
318 HARDWARE_TYPE_RTL8723BE
,
319 HARDWARE_TYPE_RTL8192EE
,
320 HARDWARE_TYPE_RTL8821AE
,
321 HARDWARE_TYPE_RTL8812AE
,
327 #define IS_HARDWARE_TYPE_8192SU(rtlhal) \
328 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
329 #define IS_HARDWARE_TYPE_8192SE(rtlhal) \
330 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
331 #define IS_HARDWARE_TYPE_8192CE(rtlhal) \
332 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
333 #define IS_HARDWARE_TYPE_8192CU(rtlhal) \
334 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
335 #define IS_HARDWARE_TYPE_8192DE(rtlhal) \
336 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
337 #define IS_HARDWARE_TYPE_8192DU(rtlhal) \
338 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
339 #define IS_HARDWARE_TYPE_8723E(rtlhal) \
340 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
341 #define IS_HARDWARE_TYPE_8723U(rtlhal) \
342 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
343 #define IS_HARDWARE_TYPE_8192S(rtlhal) \
344 (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
345 #define IS_HARDWARE_TYPE_8192C(rtlhal) \
346 (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
347 #define IS_HARDWARE_TYPE_8192D(rtlhal) \
348 (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
349 #define IS_HARDWARE_TYPE_8723(rtlhal) \
350 (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
352 #define RX_HAL_IS_CCK_RATE(rxmcs) \
353 ((rxmcs) == DESC_RATE1M || \
354 (rxmcs) == DESC_RATE2M || \
355 (rxmcs) == DESC_RATE5_5M || \
356 (rxmcs) == DESC_RATE11M)
358 enum scan_operation_backup_opt
{
360 SCAN_OPT_BACKUP_BAND0
= 0,
361 SCAN_OPT_BACKUP_BAND1
,
390 u32 rf_rb
; /* rflssi_readback */
391 u32 rf_rbpi
; /* rflssi_readbackpi */
395 IO_CMD_PAUSE_DM_BY_SCAN
= 0,
396 IO_CMD_PAUSE_BAND0_DM_BY_SCAN
= 0,
397 IO_CMD_PAUSE_BAND1_DM_BY_SCAN
= 1,
398 IO_CMD_RESUME_DM_BY_SCAN
= 2,
403 HW_VAR_MULTICAST_REG
,
407 HW_VAR_SECURITY_CONF
,
408 HW_VAR_BEACON_INTERVAL
,
410 HW_VAR_LISTEN_INTERVAL
,
424 HW_VAR_RATE_FALLBACK_CONTROL
,
425 HW_VAR_CONTENTION_WINDOW
,
430 HW_VAR_AMPDU_MIN_SPACE
,
431 HW_VAR_SHORTGI_DENSITY
,
433 HW_VAR_MCS_RATE_AVAILABLE
,
436 HW_VAR_DIS_Req_Qsize
,
437 HW_VAR_CCX_CHNL_LOAD
,
438 HW_VAR_CCX_NOISE_HISTOGRAM
,
445 HW_VAR_SET_DEV_POWER
,
455 HW_VAR_USER_CONTROL_TURBO_MODE
,
461 HW_VAR_AUTOLOAD_STATUS
,
462 HW_VAR_RF_2R_DISABLE
,
464 HW_VAR_H2C_FW_PWRMODE
,
465 HW_VAR_H2C_FW_JOINBSSRPT
,
466 HW_VAR_H2C_FW_MEDIASTATUSRPT
,
467 HW_VAR_H2C_FW_P2P_PS_OFFLOAD
,
468 HW_VAR_FW_PSMODE_STATUS
,
469 HW_VAR_INIT_RTS_RATE
,
470 HW_VAR_RESUME_CLK_ON
,
471 HW_VAR_FW_LPS_ACTION
,
472 HW_VAR_1X1_RECV_COMBINE
,
473 HW_VAR_STOP_SEND_BEACON
,
478 HW_VAR_H2C_FW_UPDATE_GTK
,
481 HW_VAR_WF_IS_MAC_ADDR
,
482 HW_VAR_H2C_FW_OFFLOAD
,
485 HW_VAR_HANDLE_FW_C2H
,
486 HW_VAR_DL_FW_RSVD_PAGE
,
488 HW_VAR_HW_SEQ_ENABLE
,
493 HW_VAR_SWITCH_EPHY_WoWLAN
,
494 HW_VAR_INT_MIGRATION
,
508 enum rt_media_status
{
509 RT_MEDIA_DISCONNECT
= 0,
515 RT_CID_8187_ALPHA0
= 1,
516 RT_CID_8187_SERCOMM_PS
= 2,
517 RT_CID_8187_HW_LED
= 3,
518 RT_CID_8187_NETGEAR
= 4,
520 RT_CID_819X_CAMEO
= 6,
521 RT_CID_819X_RUNTOP
= 7,
522 RT_CID_819X_SENAO
= 8,
524 RT_CID_819X_NETCORE
= 10,
525 RT_CID_NETTRONIX
= 11,
529 RT_CID_819X_ALPHA
= 15,
530 RT_CID_819X_SITECOM
= 16,
532 RT_CID_819X_LENOVO
= 18,
533 RT_CID_819X_QMI
= 19,
534 RT_CID_819X_EDIMAX_BELKIN
= 20,
535 RT_CID_819X_SERCOMM_BELKIN
= 21,
536 RT_CID_819X_CAMEO1
= 22,
537 RT_CID_819X_MSI
= 23,
538 RT_CID_819X_ACER
= 24,
540 RT_CID_819X_CLEVO
= 28,
541 RT_CID_819X_ARCADYAN_BELKIN
= 29,
542 RT_CID_819X_SAMSUNG
= 30,
543 RT_CID_819X_WNC_COREGA
= 31,
544 RT_CID_819X_FOXCOON
= 32,
545 RT_CID_819X_DELL
= 33,
546 RT_CID_819X_PRONETS
= 34,
547 RT_CID_819X_EDIMAX_ASUS
= 35,
556 HW_DESC_TX_NEXTDESC_ADDR
,
565 PRIME_CHNL_OFFSET_DONT_CARE
= 0,
566 PRIME_CHNL_OFFSET_LOWER
= 1,
567 PRIME_CHNL_OFFSET_UPPER
= 2,
577 enum ht_channel_width
{
578 HT_CHANNEL_WIDTH_20
= 0,
579 HT_CHANNEL_WIDTH_20_40
= 1,
580 HT_CHANNEL_WIDTH_80
= 2,
583 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
584 Cipher Suites Encryption Algorithms */
587 WEP40_ENCRYPTION
= 1,
589 RSERVED_ENCRYPTION
= 3,
590 AESCCMP_ENCRYPTION
= 4,
591 WEP104_ENCRYPTION
= 5,
592 AESCMAC_ENCRYPTION
= 6, /*IEEE802.11w */
597 _HAL_STATE_START
= 1,
600 enum rtl_desc92_rate
{
603 DESC_RATE5_5M
= 0x02,
615 DESC_RATEMCS0
= 0x0c,
616 DESC_RATEMCS1
= 0x0d,
617 DESC_RATEMCS2
= 0x0e,
618 DESC_RATEMCS3
= 0x0f,
619 DESC_RATEMCS4
= 0x10,
620 DESC_RATEMCS5
= 0x11,
621 DESC_RATEMCS6
= 0x12,
622 DESC_RATEMCS7
= 0x13,
623 DESC_RATEMCS8
= 0x14,
624 DESC_RATEMCS9
= 0x15,
625 DESC_RATEMCS10
= 0x16,
626 DESC_RATEMCS11
= 0x17,
627 DESC_RATEMCS12
= 0x18,
628 DESC_RATEMCS13
= 0x19,
629 DESC_RATEMCS14
= 0x1a,
630 DESC_RATEMCS15
= 0x1b,
631 DESC_RATEMCS15_SG
= 0x1c,
632 DESC_RATEMCS32
= 0x20,
634 DESC_RATEVHT1SS_MCS0
= 0x2c,
635 DESC_RATEVHT1SS_MCS1
= 0x2d,
636 DESC_RATEVHT1SS_MCS2
= 0x2e,
637 DESC_RATEVHT1SS_MCS3
= 0x2f,
638 DESC_RATEVHT1SS_MCS4
= 0x30,
639 DESC_RATEVHT1SS_MCS5
= 0x31,
640 DESC_RATEVHT1SS_MCS6
= 0x32,
641 DESC_RATEVHT1SS_MCS7
= 0x33,
642 DESC_RATEVHT1SS_MCS8
= 0x34,
643 DESC_RATEVHT1SS_MCS9
= 0x35,
644 DESC_RATEVHT2SS_MCS0
= 0x36,
645 DESC_RATEVHT2SS_MCS1
= 0x37,
646 DESC_RATEVHT2SS_MCS2
= 0x38,
647 DESC_RATEVHT2SS_MCS3
= 0x39,
648 DESC_RATEVHT2SS_MCS4
= 0x3a,
649 DESC_RATEVHT2SS_MCS5
= 0x3b,
650 DESC_RATEVHT2SS_MCS6
= 0x3c,
651 DESC_RATEVHT2SS_MCS7
= 0x3d,
652 DESC_RATEVHT2SS_MCS8
= 0x3e,
653 DESC_RATEVHT2SS_MCS9
= 0x3f,
679 EFUSE_HWSET_MAX_SIZE
,
680 EFUSE_MAX_SECTION_MAP
,
681 EFUSE_REAL_CONTENT_SIZE
,
682 EFUSE_OOB_PROTECT_BYTES_LEN
,
698 RTL_IMR_BCNDMAINT6
, /*Beacon DMA Interrupt 6 */
699 RTL_IMR_BCNDMAINT5
, /*Beacon DMA Interrupt 5 */
700 RTL_IMR_BCNDMAINT4
, /*Beacon DMA Interrupt 4 */
701 RTL_IMR_BCNDMAINT3
, /*Beacon DMA Interrupt 3 */
702 RTL_IMR_BCNDMAINT2
, /*Beacon DMA Interrupt 2 */
703 RTL_IMR_BCNDMAINT1
, /*Beacon DMA Interrupt 1 */
704 RTL_IMR_BCNDOK8
, /*Beacon Queue DMA OK Interrup 8 */
705 RTL_IMR_BCNDOK7
, /*Beacon Queue DMA OK Interrup 7 */
706 RTL_IMR_BCNDOK6
, /*Beacon Queue DMA OK Interrup 6 */
707 RTL_IMR_BCNDOK5
, /*Beacon Queue DMA OK Interrup 5 */
708 RTL_IMR_BCNDOK4
, /*Beacon Queue DMA OK Interrup 4 */
709 RTL_IMR_BCNDOK3
, /*Beacon Queue DMA OK Interrup 3 */
710 RTL_IMR_BCNDOK2
, /*Beacon Queue DMA OK Interrup 2 */
711 RTL_IMR_BCNDOK1
, /*Beacon Queue DMA OK Interrup 1 */
712 RTL_IMR_TIMEOUT2
, /*Timeout interrupt 2 */
713 RTL_IMR_TIMEOUT1
, /*Timeout interrupt 1 */
714 RTL_IMR_TXFOVW
, /*Transmit FIFO Overflow */
715 RTL_IMR_PSTIMEOUT
, /*Power save time out interrupt */
716 RTL_IMR_BCNINT
, /*Beacon DMA Interrupt 0 */
717 RTL_IMR_RXFOVW
, /*Receive FIFO Overflow */
718 RTL_IMR_RDU
, /*Receive Descriptor Unavailable */
719 RTL_IMR_ATIMEND
, /*For 92C,ATIM Window End Interrupt */
720 RTL_IMR_BDOK
, /*Beacon Queue DMA OK Interrup */
721 RTL_IMR_HIGHDOK
, /*High Queue DMA OK Interrupt */
722 RTL_IMR_COMDOK
, /*Command Queue DMA OK Interrupt*/
723 RTL_IMR_TBDOK
, /*Transmit Beacon OK interrup */
724 RTL_IMR_MGNTDOK
, /*Management Queue DMA OK Interrupt */
725 RTL_IMR_TBDER
, /*For 92C,Transmit Beacon Error Interrupt */
726 RTL_IMR_BKDOK
, /*AC_BK DMA OK Interrupt */
727 RTL_IMR_BEDOK
, /*AC_BE DMA OK Interrupt */
728 RTL_IMR_VIDOK
, /*AC_VI DMA OK Interrupt */
729 RTL_IMR_VODOK
, /*AC_VO DMA Interrupt */
730 RTL_IMR_ROK
, /*Receive DMA OK Interrupt */
731 RTL_IMR_HSISR_IND
, /*HSISR Interrupt*/
732 RTL_IBSS_INT_MASKS
, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK |
734 RTL_IMR_C2HCMD
, /*fw interrupt*/
736 /*CCK Rates, TxHT = 0 */
742 /*OFDM Rates, TxHT = 0 */
755 RTL_RC_VHT_RATE_1SS_MCS7
,
756 RTL_RC_VHT_RATE_1SS_MCS8
,
757 RTL_RC_VHT_RATE_1SS_MCS9
,
758 RTL_RC_VHT_RATE_2SS_MCS7
,
759 RTL_RC_VHT_RATE_2SS_MCS8
,
760 RTL_RC_VHT_RATE_2SS_MCS9
,
766 /*Firmware PS mode for control LPS.*/
768 FW_PS_ACTIVE_MODE
= 0,
773 FW_PS_UAPSD_WMM_MODE
= 5,
774 FW_PS_UAPSD_MODE
= 6,
776 FW_PS_WWLAN_MODE
= 8,
777 FW_PS_PM_Radio_Off
= 9,
778 FW_PS_PM_Card_Disable
= 10,
782 EACTIVE
, /*Active/Continuous access. */
783 EMAXPS
, /*Max power save mode. */
784 EFASTPS
, /*Fast power save mode. */
785 EAUTOPS
, /*Auto power save mode. */
790 LED_CTL_POWER_ON
= 1,
795 LED_CTL_SITE_SURVEY
= 6,
796 LED_CTL_POWER_OFF
= 7,
797 LED_CTL_START_TO_LINK
= 8,
798 LED_CTL_START_WPS
= 9,
799 LED_CTL_STOP_WPS
= 10,
810 /*acm implementation method.*/
812 eAcmWay0_SwAndHw
= 0,
818 SINGLEMAC_SINGLEPHY
= 0,
831 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
845 WIRELESS_MODE_UNKNOWN
= 0x00,
846 WIRELESS_MODE_A
= 0x01,
847 WIRELESS_MODE_B
= 0x02,
848 WIRELESS_MODE_G
= 0x04,
849 WIRELESS_MODE_AUTO
= 0x08,
850 WIRELESS_MODE_N_24G
= 0x10,
851 WIRELESS_MODE_N_5G
= 0x20,
852 WIRELESS_MODE_AC_5G
= 0x40,
853 WIRELESS_MODE_AC_24G
= 0x80,
854 WIRELESS_MODE_AC_ONLY
= 0x100,
855 WIRELESS_MODE_MAX
= 0x800
858 #define IS_WIRELESS_MODE_A(wirelessmode) \
859 (wirelessmode == WIRELESS_MODE_A)
860 #define IS_WIRELESS_MODE_B(wirelessmode) \
861 (wirelessmode == WIRELESS_MODE_B)
862 #define IS_WIRELESS_MODE_G(wirelessmode) \
863 (wirelessmode == WIRELESS_MODE_G)
864 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \
865 (wirelessmode == WIRELESS_MODE_N_24G)
866 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \
867 (wirelessmode == WIRELESS_MODE_N_5G)
869 enum ratr_table_mode
{
870 RATR_INX_WIRELESS_NGB
= 0,
871 RATR_INX_WIRELESS_NG
= 1,
872 RATR_INX_WIRELESS_NB
= 2,
873 RATR_INX_WIRELESS_N
= 3,
874 RATR_INX_WIRELESS_GB
= 4,
875 RATR_INX_WIRELESS_G
= 5,
876 RATR_INX_WIRELESS_B
= 6,
877 RATR_INX_WIRELESS_MC
= 7,
878 RATR_INX_WIRELESS_A
= 8,
879 RATR_INX_WIRELESS_AC_5N
= 8,
880 RATR_INX_WIRELESS_AC_24N
= 9,
883 enum rtl_link_state
{
885 MAC80211_LINKING
= 1,
887 MAC80211_LINKED_SCANNING
= 3,
904 enum rt_polarity_ctl
{
905 RT_POLARITY_LOW_ACT
= 0,
906 RT_POLARITY_HIGH_ACT
= 1,
909 /* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */
910 enum fw_wow_reason_v2
{
911 FW_WOW_V2_PTK_UPDATE_EVENT
= 0x01,
912 FW_WOW_V2_GTK_UPDATE_EVENT
= 0x02,
913 FW_WOW_V2_DISASSOC_EVENT
= 0x04,
914 FW_WOW_V2_DEAUTH_EVENT
= 0x08,
915 FW_WOW_V2_FW_DISCONNECT_EVENT
= 0x10,
916 FW_WOW_V2_MAGIC_PKT_EVENT
= 0x21,
917 FW_WOW_V2_UNICAST_PKT_EVENT
= 0x22,
918 FW_WOW_V2_PATTERN_PKT_EVENT
= 0x23,
919 FW_WOW_V2_RTD3_SSID_MATCH_EVENT
= 0x24,
920 FW_WOW_V2_REALWOW_V2_WAKEUPPKT
= 0x30,
921 FW_WOW_V2_REALWOW_V2_ACKLOST
= 0x31,
922 FW_WOW_V2_REASON_MAX
= 0xff,
925 enum wolpattern_type
{
927 MULTICAST_PATTERN
= 1,
928 BROADCAST_PATTERN
= 2,
933 struct octet_string
{
938 struct rtl_hdr_3addr
{
948 struct rtl_info_element
{
954 struct rtl_probe_rsp
{
955 struct rtl_hdr_3addr header
;
957 __le16 beacon_interval
;
959 /*SSID, supported rates, FH params, DS params,
960 CF params, IBSS params, TIM (if beacon), RSN */
961 struct rtl_info_element info_element
[0];
965 /*ledpin Identify how to implement this SW led.*/
968 enum rtl_led_pin ledpin
;
974 struct rtl_led sw_led0
;
975 struct rtl_led sw_led1
;
978 struct rtl_qos_parameters
{
986 struct rt_smooth_data
{
987 u32 elements
[100]; /*array to store values */
988 u32 index
; /*index to current array to store */
989 u32 total_num
; /*num of valid elements */
990 u32 total_val
; /*sum of valid elements */
993 struct false_alarm_statistics
{
995 u32 cnt_rate_illegal
;
998 u32 cnt_fast_fsync_fail
;
999 u32 cnt_sb_search_fail
;
1019 struct wireless_stats
{
1020 unsigned long txbytesunicast
;
1021 unsigned long txbytesmulticast
;
1022 unsigned long txbytesbroadcast
;
1023 unsigned long rxbytesunicast
;
1026 /*Correct smoothed ss in Dbm, only used
1027 in driver to report real power now. */
1028 long recv_signal_power
;
1029 long signal_quality
;
1030 long last_sigstrength_inpercent
;
1032 u32 rssi_calculate_cnt
;
1035 /*Transformed, in dbm. Beautified signal
1036 strength for UI, not correct. */
1037 long signal_strength
;
1039 u8 rx_rssi_percentage
[4];
1041 u8 rx_evm_percentage
[2];
1043 u16 rx_cfo_short
[4];
1046 struct rt_smooth_data ui_rssi
;
1047 struct rt_smooth_data ui_link_quality
;
1050 struct rate_adaptive
{
1051 u8 rate_adaptive_disabled
;
1055 u32 high_rssi_thresh_for_ra
;
1056 u32 high2low_rssi_thresh_for_ra
;
1057 u8 low2high_rssi_thresh_for_ra40m
;
1058 u32 low_rssi_thresh_for_ra40m
;
1059 u8 low2high_rssi_thresh_for_ra20m
;
1060 u32 low_rssi_thresh_for_ra20m
;
1061 u32 upper_rssi_threshold_ratr
;
1062 u32 middleupper_rssi_threshold_ratr
;
1063 u32 middle_rssi_threshold_ratr
;
1064 u32 middlelow_rssi_threshold_ratr
;
1065 u32 low_rssi_threshold_ratr
;
1066 u32 ultralow_rssi_threshold_ratr
;
1067 u32 low_rssi_threshold_ratr_40m
;
1068 u32 low_rssi_threshold_ratr_20m
;
1069 u8 ping_rssi_enable
;
1071 u32 ping_rssi_thresh_for_ra
;
1076 bool lower_rts_rate
;
1077 bool is_special_data
;
1080 struct regd_pair_mapping
{
1086 struct dynamic_primary_cca
{
1096 struct rtl_regulatory
{
1099 u16 max_power_level
;
1103 int16_t power_limit
;
1104 struct regd_pair_mapping
*regpair
;
1108 bool rfkill_state
; /*0 is off, 1 is on */
1112 #define P2P_MAX_NOA_NUM 2
1115 P2P_ROLE_DISABLE
= 0,
1116 P2P_ROLE_DEVICE
= 1,
1117 P2P_ROLE_CLIENT
= 2,
1125 P2P_PS_SCAN_DONE
= 3,
1126 P2P_PS_ALLSTASLEEP
= 4, /* for P2P GO */
1131 P2P_PS_CTWINDOW
= 1,
1133 P2P_PS_MIX
= 3, /* CTWindow and NoA */
1136 struct rtl_p2p_ps_info
{
1137 enum p2p_ps_mode p2p_ps_mode
; /* indicate p2p ps mode */
1138 enum p2p_ps_state p2p_ps_state
; /* indicate p2p ps state */
1139 u8 noa_index
; /* Identifies instance of Notice of Absence timing. */
1140 /* Client traffic window. A period of time in TU after TBTT. */
1142 u8 opp_ps
; /* opportunistic power save. */
1143 u8 noa_num
; /* number of NoA descriptor in P2P IE. */
1144 /* Count for owner, Type of client. */
1145 u8 noa_count_type
[P2P_MAX_NOA_NUM
];
1146 /* Max duration for owner, preferred or min acceptable duration
1149 u32 noa_duration
[P2P_MAX_NOA_NUM
];
1150 /* Length of interval for owner, preferred or max acceptable intervali
1153 u32 noa_interval
[P2P_MAX_NOA_NUM
];
1154 /* schedule in terms of the lower 4 bytes of the TSF timer. */
1155 u32 noa_start_time
[P2P_MAX_NOA_NUM
];
1158 struct p2p_ps_offload_t
{
1160 u8 role
:1; /* 1: Owner, 0: Client */
1169 #define IQK_MATRIX_REG_NUM 8
1170 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
1172 struct iqk_matrix_regs
{
1174 long value
[1][IQK_MATRIX_REG_NUM
];
1177 struct phy_parameters
{
1182 enum hw_param_tab_index
{
1197 struct bb_reg_def phyreg_def
[4]; /*Radio A/B/C/D */
1198 struct init_gain initgain_backup
;
1199 enum io_type current_io_type
;
1204 u8 set_bwmode_inprogress
;
1205 u8 sw_chnl_inprogress
;
1210 u8 set_io_inprogress
;
1213 /* record for power tracking */
1225 u32 reg_c04
, reg_c08
, reg_874
;
1226 u32 adda_backup
[16];
1227 u32 iqk_mac_backup
[IQK_MAC_REG_NUM
];
1228 u32 iqk_bb_backup
[10];
1229 bool iqk_initialized
;
1231 bool rfpath_rx_enable
[MAX_RF_PATH
];
1235 struct iqk_matrix_regs iqk_matrix
[IQK_MATRIX_SETTINGS_NUM
];
1238 bool iqk_in_progress
;
1242 /* this is for 88E & 8723A */
1243 u32 mcs_txpwrlevel_origoffset
[MAX_PG_GROUP
][16];
1244 /* MAX_PG_GROUP groups of pwr diff by rates */
1245 u32 mcs_offset
[MAX_PG_GROUP
][16];
1246 u32 tx_power_by_rate_offset
[TX_PWR_BY_RATE_NUM_BAND
]
1247 [TX_PWR_BY_RATE_NUM_RF
]
1248 [TX_PWR_BY_RATE_NUM_RF
]
1249 [TX_PWR_BY_RATE_NUM_SECTION
];
1250 u8 txpwr_by_rate_base_24g
[TX_PWR_BY_RATE_NUM_RF
]
1251 [TX_PWR_BY_RATE_NUM_RF
]
1252 [MAX_BASE_NUM_IN_PHY_REG_PG_24G
];
1253 u8 txpwr_by_rate_base_5g
[TX_PWR_BY_RATE_NUM_RF
]
1254 [TX_PWR_BY_RATE_NUM_RF
]
1255 [MAX_BASE_NUM_IN_PHY_REG_PG_5G
];
1256 u8 default_initialgain
[4];
1258 /* the current Tx power level */
1259 u8 cur_cck_txpwridx
;
1260 u8 cur_ofdm24g_txpwridx
;
1261 u8 cur_bw20_txpwridx
;
1262 u8 cur_bw40_txpwridx
;
1264 char txpwr_limit_2_4g
[MAX_REGULATION_NUM
]
1265 [MAX_2_4G_BANDWITH_NUM
]
1266 [MAX_RATE_SECTION_NUM
]
1267 [CHANNEL_MAX_NUMBER_2G
]
1269 char txpwr_limit_5g
[MAX_REGULATION_NUM
]
1270 [MAX_5G_BANDWITH_NUM
]
1271 [MAX_RATE_SECTION_NUM
]
1272 [CHANNEL_MAX_NUMBER_5G
]
1275 u32 rfreg_chnlval
[2];
1277 u32 reg_rf3c
[2]; /* pathA / pathB */
1279 u32 backup_rf_0x1a
;/*92ee*/
1284 u8 num_total_rfpath
;
1285 struct phy_parameters hwparam_tables
[MAX_TAB
];
1288 u8 hw_rof_enable
; /*Enable GPIO[9] as WL RF HW PDn source*/
1289 enum rt_polarity_ctl polarity_ctl
;
1292 #define MAX_TID_COUNT 9
1293 #define RTL_AGG_STOP 0
1294 #define RTL_AGG_PROGRESS 1
1295 #define RTL_AGG_START 2
1296 #define RTL_AGG_OPERATIONAL 3
1297 #define RTL_AGG_OFF 0
1298 #define RTL_AGG_ON 1
1299 #define RTL_RX_AGG_START 1
1300 #define RTL_RX_AGG_STOP 0
1301 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
1302 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
1319 struct rtl_tid_data
{
1321 struct rtl_ht_agg agg
;
1324 struct rtl_sta_info
{
1325 struct list_head list
;
1329 u8 mac_addr
[ETH_ALEN
];
1330 struct rtl_tid_data tids
[MAX_TID_COUNT
];
1332 /* just used for ap adhoc or mesh*/
1333 struct rssi_sta rssi_stat
;
1339 struct mutex bb_mutex
;
1342 unsigned long pci_mem_end
; /*shared mem end */
1343 unsigned long pci_mem_start
; /*shared mem start */
1346 unsigned long pci_base_addr
; /*device I/O address */
1348 void (*write8_async
) (struct rtl_priv
*rtlpriv
, u32 addr
, u8 val
);
1349 void (*write16_async
) (struct rtl_priv
*rtlpriv
, u32 addr
, u16 val
);
1350 void (*write32_async
) (struct rtl_priv
*rtlpriv
, u32 addr
, u32 val
);
1351 void (*writeN_sync
) (struct rtl_priv
*rtlpriv
, u32 addr
, void *buf
,
1354 u8(*read8_sync
) (struct rtl_priv
*rtlpriv
, u32 addr
);
1355 u16(*read16_sync
) (struct rtl_priv
*rtlpriv
, u32 addr
);
1356 u32(*read32_sync
) (struct rtl_priv
*rtlpriv
, u32 addr
);
1361 u8 mac_addr
[ETH_ALEN
];
1362 u8 mac80211_registered
;
1368 struct ieee80211_supported_band bands
[IEEE80211_NUM_BANDS
];
1369 struct ieee80211_hw
*hw
;
1370 struct ieee80211_vif
*vif
;
1371 enum nl80211_iftype opmode
;
1373 /*Probe Beacon management */
1374 struct rtl_tid_data tids
[MAX_TID_COUNT
];
1375 enum rtl_link_state link_state
;
1381 u8 p2p
; /*using p2p role*/
1391 u8 cnt_after_linked
;
1395 /* skb wait queue */
1396 struct sk_buff_head skb_waitq
[MAX_TID_COUNT
];
1413 u8 bssid
[ETH_ALEN
] __aligned(2);
1415 u8 mcs
[16]; /* 16 bytes mcs for HT rates. */
1416 u32 basic_rates
; /* b/g rates */
1421 u16 mode
; /* wireless mode */
1426 u8 cur_40_prime_sc_bk
;
1435 int beacon_interval
;
1438 u8 min_space_cfg
; /*For Min spacing configurations */
1440 u8 current_ampdu_factor
;
1441 u8 current_ampdu_density
;
1444 struct ieee80211_tx_queue_params edca_param
[RTL_MAC80211_NUM_QUEUE
];
1445 struct rtl_qos_parameters ac
[AC_MAX
];
1450 u32 last_bt_edca_ul
;
1451 u32 last_bt_edca_dl
;
1457 bool adc_back_off_on
;
1459 bool low_penalty_rate_adaptive
;
1460 bool rf_rx_lpf_shrink
;
1461 bool reject_aggre_pkt
;
1469 u8 fw_dac_swing_lvl
;
1476 bool sw_dac_swing_on
;
1477 u32 sw_dac_swing_lvl
;
1482 bool ignore_wlan_act
;
1485 struct bt_coexist_8723
{
1486 u32 high_priority_tx
;
1487 u32 high_priority_rx
;
1488 u32 low_priority_tx
;
1489 u32 low_priority_rx
;
1491 bool c2h_bt_info_req_sent
;
1492 bool c2h_bt_inquiry_page
;
1493 u32 bt_inq_page_start_time
;
1495 u8 c2h_bt_info_original
;
1496 u8 bt_inquiry_page_cnt
;
1497 struct btdm_8723 btdm
;
1501 struct ieee80211_hw
*hw
;
1502 bool driver_is_goingto_unload
;
1505 bool being_init_adapter
;
1507 bool mac_func_enable
;
1508 bool pre_edcca_enable
;
1509 struct bt_coexist_8723 hal_coex_8723
;
1511 enum intf_type interface
;
1512 u16 hw_type
; /*92c or 92d or 92s and so on */
1515 u32 version
; /*version of chip */
1516 u8 state
; /*stop 0, start 1 */
1536 bool h2c_setinprogress
;
1539 /*Reserve page start offset except beacon in TxQ. */
1540 u8 fw_rsvdpage_startoffset
;
1544 /* FW Cmd IO related */
1547 bool set_fwcmd_inprogress
;
1548 u8 current_fwcmd_io
;
1550 struct p2p_ps_offload_t p2p_ps_offload
;
1551 bool fw_clk_change_in_progress
;
1552 bool allow_sw_to_change_hwclc
;
1555 bool driver_going2unload
;
1557 /*AMPDU init min space*/
1558 u8 minspace_cfg
; /*For Min spacing configurations */
1561 enum macphy_mode macphymode
;
1562 enum band_type current_bandtype
; /* 0:2.4G, 1:5G */
1563 enum band_type current_bandtypebackup
;
1564 enum band_type bandset
;
1565 /* dual MAC 0--Mac0 1--Mac1 */
1567 /* just for DualMac S3S4 */
1569 bool earlymode_enable
;
1570 u8 max_earlymode_num
;
1572 bool during_mac0init_radiob
;
1573 bool during_mac1init_radioa
;
1574 bool reloadtxpowerindex
;
1575 /* True if IMR or IQK have done
1576 for 2.4G in scan progress */
1577 bool load_imrandiqk_setting_for2g
;
1579 bool disable_amsdu_8k
;
1580 bool master_of_dmsp
;
1583 u16 rx_tag
;/*for 92ee*/
1588 bool enter_pnp_sleep
;
1589 bool wake_from_pnp_sleep
;
1591 __kernel_time_t last_suspend_sec
;
1593 u8
*wowlan_firmware
;
1595 u8 hw_rof_enable
; /*Enable GPIO[9] as WL RF HW PDn source*/
1597 bool real_wow_v2_enable
;
1598 bool re_init_llt_table
;
1601 struct rtl_security
{
1606 bool use_defaultkey
;
1607 /*Encryption Algorithm for Unicast Packet */
1608 enum rt_enc_alg pairwise_enc_algorithm
;
1609 /*Encryption Algorithm for Brocast/Multicast */
1610 enum rt_enc_alg group_enc_algorithm
;
1611 /*Cam Entry Bitmap */
1612 u32 hwsec_cam_bitmap
;
1613 u8 hwsec_cam_sta_addr
[TOTAL_CAM_ENTRY
][ETH_ALEN
];
1614 /*local Key buffer, indx 0 is for
1615 pairwise key 1-4 is for agoup key. */
1616 u8 key_buf
[KEY_BUF_SIZE
][MAX_KEY_LEN
];
1617 u8 key_len
[KEY_BUF_SIZE
];
1619 /*The pointer of Pairwise Key,
1620 it always points to KeyBuf[4] */
1624 #define ASSOCIATE_ENTRY_NUM 33
1626 struct fast_ant_training
{
1628 u8 antsel_rx_keep_0
;
1629 u8 antsel_rx_keep_1
;
1630 u8 antsel_rx_keep_2
;
1636 u8 antsel_a
[ASSOCIATE_ENTRY_NUM
];
1637 u8 antsel_b
[ASSOCIATE_ENTRY_NUM
];
1638 u8 antsel_c
[ASSOCIATE_ENTRY_NUM
];
1639 u32 main_ant_sum
[ASSOCIATE_ENTRY_NUM
];
1640 u32 aux_ant_sum
[ASSOCIATE_ENTRY_NUM
];
1641 u32 main_ant_cnt
[ASSOCIATE_ENTRY_NUM
];
1642 u32 aux_ant_cnt
[ASSOCIATE_ENTRY_NUM
];
1647 struct dm_phy_dbg_info
{
1649 u64 num_qry_phy_status
;
1650 u64 num_qry_phy_status_cck
;
1651 u64 num_qry_phy_status_ofdm
;
1652 u16 num_qry_beacon_pkt
;
1658 /*PHY status for Dynamic Management */
1659 long entry_min_undec_sm_pwdb
;
1661 long undec_sm_pwdb
; /*out dm */
1662 long entry_max_undec_sm_pwdb
;
1664 bool dm_initialgain_enable
;
1665 bool dynamic_txpower_enable
;
1666 bool current_turbo_edca
;
1667 bool is_any_nonbepkts
; /*out dm */
1668 bool is_cur_rdlstate
;
1669 bool txpower_trackinginit
;
1670 bool disable_framebursting
;
1672 bool txpower_tracking
;
1674 bool rfpath_rxenable
[4];
1675 bool inform_fw_driverctrldm
;
1676 bool current_mrc_switch
;
1678 u8 powerindex_backup
[6];
1680 u8 thermalvalue_rxgain
;
1681 u8 thermalvalue_iqk
;
1682 u8 thermalvalue_lck
;
1685 u8 thermalvalue_avg
[AVG_THERMAL_NUM
];
1686 u8 thermalvalue_avg_index
;
1689 u8 dynamic_txhighpower_lvl
; /*Tx high power level */
1690 u8 dm_flag
; /*Indicate each dynamic mechanism's status. */
1694 u8 txpower_track_control
;
1695 bool interrupt_migration
;
1696 bool disable_tx_int
;
1697 char ofdm_index
[MAX_RF_PATH
];
1698 u8 default_ofdm_index
;
1699 u8 default_cck_index
;
1701 char delta_power_index
[MAX_RF_PATH
];
1702 char delta_power_index_last
[MAX_RF_PATH
];
1703 char power_index_offset
[MAX_RF_PATH
];
1704 char absolute_ofdm_swing_idx
[MAX_RF_PATH
];
1705 char remnant_ofdm_swing_idx
[MAX_RF_PATH
];
1706 char remnant_cck_idx
;
1707 bool modify_txagc_flag_path_a
;
1708 bool modify_txagc_flag_path_b
;
1710 bool one_entry_only
;
1711 struct dm_phy_dbg_info dbginfo
;
1713 /* Dynamic ATC switch */
1722 u32 packet_count_pre
;
1725 /*88e tx power tracking*/
1726 u8 swing_idx_ofdm
[MAX_RF_PATH
];
1727 u8 swing_idx_ofdm_cur
;
1728 u8 swing_idx_ofdm_base
[MAX_RF_PATH
];
1729 bool swing_flag_ofdm
;
1731 u8 swing_idx_cck_cur
;
1732 u8 swing_idx_cck_base
;
1733 bool swing_flag_cck
;
1738 u8 delta_swing_table_idx_24gccka_p
[DEL_SW_IDX_SZ
];
1739 u8 delta_swing_table_idx_24gccka_n
[DEL_SW_IDX_SZ
];
1740 u8 delta_swing_table_idx_24gcckb_p
[DEL_SW_IDX_SZ
];
1741 u8 delta_swing_table_idx_24gcckb_n
[DEL_SW_IDX_SZ
];
1742 u8 delta_swing_table_idx_24ga_p
[DEL_SW_IDX_SZ
];
1743 u8 delta_swing_table_idx_24ga_n
[DEL_SW_IDX_SZ
];
1744 u8 delta_swing_table_idx_24gb_p
[DEL_SW_IDX_SZ
];
1745 u8 delta_swing_table_idx_24gb_n
[DEL_SW_IDX_SZ
];
1746 u8 delta_swing_table_idx_5ga_p
[BAND_NUM
][DEL_SW_IDX_SZ
];
1747 u8 delta_swing_table_idx_5ga_n
[BAND_NUM
][DEL_SW_IDX_SZ
];
1748 u8 delta_swing_table_idx_5gb_p
[BAND_NUM
][DEL_SW_IDX_SZ
];
1749 u8 delta_swing_table_idx_5gb_n
[BAND_NUM
][DEL_SW_IDX_SZ
];
1750 u8 delta_swing_table_idx_24ga_p_8188e
[DEL_SW_IDX_SZ
];
1751 u8 delta_swing_table_idx_24ga_n_8188e
[DEL_SW_IDX_SZ
];
1754 bool supp_phymode_switch
;
1757 struct fast_ant_training fat_table
;
1774 #define EFUSE_MAX_LOGICAL_SIZE 512
1779 u16 max_physical_size
;
1781 u8 efuse_map
[2][EFUSE_MAX_LOGICAL_SIZE
];
1782 u16 efuse_usedbytes
;
1783 u8 efuse_usedpercentage
;
1784 #ifdef EFUSE_REPG_WORKAROUND
1785 bool efuse_re_pg_sec1flag
;
1786 u8 efuse_re_pg_data
[8];
1789 u8 autoload_failflag
;
1798 u16 eeprom_channelplan
;
1806 u8 antenna_div_type
;
1808 bool txpwr_fromeprom
;
1809 u8 eeprom_crystalcap
;
1811 u8 eeprom_tssi_5g
[3][2]; /* for 5GL/5GM/5GH band. */
1812 u8 eeprom_pwrlimit_ht20
[CHANNEL_GROUP_MAX
];
1813 u8 eeprom_pwrlimit_ht40
[CHANNEL_GROUP_MAX
];
1814 u8 eeprom_chnlarea_txpwr_cck
[MAX_RF_PATH
][CHANNEL_GROUP_MAX_2G
];
1815 u8 eeprom_chnlarea_txpwr_ht40_1s
[MAX_RF_PATH
][CHANNEL_GROUP_MAX
];
1816 u8 eprom_chnl_txpwr_ht40_2sdf
[MAX_RF_PATH
][CHANNEL_GROUP_MAX
];
1818 u8 internal_pa_5g
[2]; /* pathA / pathB */
1822 /*For power group */
1823 u8 eeprom_pwrgroup
[2][3];
1824 u8 pwrgroup_ht20
[2][CHANNEL_MAX_NUMBER
];
1825 u8 pwrgroup_ht40
[2][CHANNEL_MAX_NUMBER
];
1827 u8 txpwrlevel_cck
[MAX_RF_PATH
][CHANNEL_MAX_NUMBER_2G
];
1828 /*For HT 40MHZ pwr */
1829 u8 txpwrlevel_ht40_1s
[MAX_RF_PATH
][CHANNEL_MAX_NUMBER
];
1830 /*For HT 40MHZ pwr */
1831 u8 txpwrlevel_ht40_2s
[MAX_RF_PATH
][CHANNEL_MAX_NUMBER
];
1833 /*--------------------------------------------------------*
1834 * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays,
1835 * other ICs (8188EE\8723BE\8192EE\8812AE...)
1836 * define new arrays in Windows code.
1837 * BUT, in linux code, we use the same array for all ICs.
1839 * The Correspondance relation between two arrays is:
1840 * txpwr_cckdiff[][] == CCK_24G_Diff[][]
1841 * txpwr_ht20diff[][] == BW20_24G_Diff[][]
1842 * txpwr_ht40diff[][] == BW40_24G_Diff[][]
1843 * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][]
1845 * Sizes of these arrays are decided by the larger ones.
1847 char txpwr_cckdiff
[MAX_RF_PATH
][CHANNEL_MAX_NUMBER
];
1848 char txpwr_ht20diff
[MAX_RF_PATH
][CHANNEL_MAX_NUMBER
];
1849 char txpwr_ht40diff
[MAX_RF_PATH
][CHANNEL_MAX_NUMBER
];
1850 char txpwr_legacyhtdiff
[MAX_RF_PATH
][CHANNEL_MAX_NUMBER
];
1852 u8 txpwr_5g_bw40base
[MAX_RF_PATH
][CHANNEL_MAX_NUMBER
];
1853 u8 txpwr_5g_bw80base
[MAX_RF_PATH
][CHANNEL_MAX_NUMBER_5G_80M
];
1854 char txpwr_5g_ofdmdiff
[MAX_RF_PATH
][MAX_TX_COUNT
];
1855 char txpwr_5g_bw20diff
[MAX_RF_PATH
][MAX_TX_COUNT
];
1856 char txpwr_5g_bw40diff
[MAX_RF_PATH
][MAX_TX_COUNT
];
1857 char txpwr_5g_bw80diff
[MAX_RF_PATH
][MAX_TX_COUNT
];
1859 u8 txpwr_safetyflag
; /* Band edge enable flag */
1860 u16 eeprom_txpowerdiff
;
1861 u8 legacy_httxpowerdiff
; /* Legacy to HT rate power diff */
1862 u8 antenna_txpwdiff
[3];
1864 u8 eeprom_regulatory
;
1865 u8 eeprom_thermalmeter
;
1866 u8 thermalmeter
[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1868 u8 crystalcap
; /* CrystalCap. */
1872 u8 legacy_ht_txpowerdiff
; /*Legacy to HT rate power diff */
1873 bool apk_thermalmeterignore
;
1875 bool b1x1_recvcombine
;
1883 bool pwrdomain_protect
;
1884 bool in_powersavemode
;
1885 bool rfchange_inprogress
;
1886 bool swrf_processing
;
1889 * just for PCIE ASPM
1890 * If it supports ASPM, Offset[560h] = 0x40,
1891 * otherwise Offset[560h] = 0x00.
1894 bool support_backdoor
;
1897 enum rt_psmode dot11_psmode
; /*Power save mode configured. */
1902 /*For Fw control LPS mode */
1904 /*Record Fw PS mode status. */
1905 bool fw_current_inpsmode
;
1906 u8 reg_max_lps_awakeintvl
;
1908 bool low_power_enable
;/*for 32k*/
1919 /*just for PCIE ASPM */
1920 u8 const_amdpci_aspm
;
1923 enum rf_pwrstate inactive_pwrstate
;
1924 enum rf_pwrstate rfpwr_state
; /*cur power state */
1930 bool multi_buffered
;
1932 unsigned int dtim_counter
;
1933 unsigned int sleep_ms
;
1934 unsigned long last_sleep_jiffies
;
1935 unsigned long last_awake_jiffies
;
1936 unsigned long last_delaylps_stamp_jiffies
;
1937 unsigned long last_dtim
;
1938 unsigned long last_beacon
;
1939 unsigned long last_action
;
1940 unsigned long last_slept
;
1943 struct rtl_p2p_ps_info p2p_ps_info
;
1947 /* wake up on line */
1949 u8 arp_offload_enable
;
1950 u8 gtk_offload_enable
;
1951 /* Used for WOL, indicates the reason for waking event.*/
1953 /* Record the last waking time for comparison with setting key. */
1954 u64 last_wakeup_time
;
1958 u8 psaddr
[ETH_ALEN
];
1963 u8 rate
; /* hw desc rate */
1964 u8 received_channel
;
1973 u8 signalquality
; /*in 0-100 index. */
1975 * Real power in dBm for this packet,
1976 * no beautification and aggregation.
1978 s32 recvsignalpower
;
1979 s8 rxpower
; /*in dBm Translate from PWdB */
1980 u8 signalstrength
; /*in 0-100 index. */
1984 u16 shortpreamble
:1;
1996 bool rx_is40Mhzpacket
;
1999 u8 rx_mimo_signalstrength
[4]; /*in 0~100 index */
2000 s8 rx_mimo_signalquality
[4];
2001 u8 rx_mimo_evm_dbm
[4];
2002 u16 cfo_short
[4]; /* per-path's Cfo_short */
2005 s8 rx_mimo_sig_qual
[4];
2006 u8 rx_pwr
[4]; /* per-path's pwdb */
2007 u8 rx_snr
[4]; /* per-path's SNR */
2009 u8 bt_coex_pwr_adjust
;
2010 bool packet_matchbssid
;
2014 bool packet_beacon
; /*for rssi */
2015 char cck_adc_pwdb
[4]; /*for rx path selection */
2021 u8 packet_report_type
;
2025 u32 bt_rx_rssi_percentage
;
2026 u32 macid_valid_entry
[2];
2030 struct rt_link_detect
{
2031 /* count for roaming */
2032 u32 bcn_rx_inperiod
;
2035 u32 num_tx_in4period
[4];
2036 u32 num_rx_in4period
[4];
2038 u32 num_tx_inperiod
;
2039 u32 num_rx_inperiod
;
2042 bool tx_busy_traffic
;
2043 bool rx_busy_traffic
;
2044 bool higher_busytraffic
;
2045 bool higher_busyrxtraffic
;
2047 u32 tidtx_in4period
[MAX_TID_COUNT
][4];
2048 u32 tidtx_inperiod
[MAX_TID_COUNT
];
2049 bool higher_busytxtraffic
[MAX_TID_COUNT
];
2052 struct rtl_tcb_desc
{
2060 u8 rts_use_shortpreamble
:1;
2061 u8 rts_use_shortgi
:1;
2067 u8 use_shortpreamble
:1;
2068 u8 use_driver_rate
:1;
2069 u8 disable_ratefallback
:1;
2081 /* The max value by HW */
2083 bool tx_enable_sw_calc_duration
;
2086 struct rtl_wow_pattern
{
2092 struct rtl_hal_ops
{
2093 int (*init_sw_vars
) (struct ieee80211_hw
*hw
);
2094 void (*deinit_sw_vars
) (struct ieee80211_hw
*hw
);
2095 void (*read_chip_version
)(struct ieee80211_hw
*hw
);
2096 void (*read_eeprom_info
) (struct ieee80211_hw
*hw
);
2097 void (*interrupt_recognized
) (struct ieee80211_hw
*hw
,
2098 u32
*p_inta
, u32
*p_intb
);
2099 int (*hw_init
) (struct ieee80211_hw
*hw
);
2100 void (*hw_disable
) (struct ieee80211_hw
*hw
);
2101 void (*hw_suspend
) (struct ieee80211_hw
*hw
);
2102 void (*hw_resume
) (struct ieee80211_hw
*hw
);
2103 void (*enable_interrupt
) (struct ieee80211_hw
*hw
);
2104 void (*disable_interrupt
) (struct ieee80211_hw
*hw
);
2105 int (*set_network_type
) (struct ieee80211_hw
*hw
,
2106 enum nl80211_iftype type
);
2107 void (*set_chk_bssid
)(struct ieee80211_hw
*hw
,
2109 void (*set_bw_mode
) (struct ieee80211_hw
*hw
,
2110 enum nl80211_channel_type ch_type
);
2111 u8(*switch_channel
) (struct ieee80211_hw
*hw
);
2112 void (*set_qos
) (struct ieee80211_hw
*hw
, int aci
);
2113 void (*set_bcn_reg
) (struct ieee80211_hw
*hw
);
2114 void (*set_bcn_intv
) (struct ieee80211_hw
*hw
);
2115 void (*update_interrupt_mask
) (struct ieee80211_hw
*hw
,
2116 u32 add_msr
, u32 rm_msr
);
2117 void (*get_hw_reg
) (struct ieee80211_hw
*hw
, u8 variable
, u8
*val
);
2118 void (*set_hw_reg
) (struct ieee80211_hw
*hw
, u8 variable
, u8
*val
);
2119 void (*update_rate_tbl
) (struct ieee80211_hw
*hw
,
2120 struct ieee80211_sta
*sta
, u8 rssi_level
);
2121 void (*pre_fill_tx_bd_desc
)(struct ieee80211_hw
*hw
, u8
*tx_bd_desc
,
2122 u8
*desc
, u8 queue_index
,
2123 struct sk_buff
*skb
, dma_addr_t addr
);
2124 void (*update_rate_mask
) (struct ieee80211_hw
*hw
, u8 rssi_level
);
2125 u16 (*rx_desc_buff_remained_cnt
)(struct ieee80211_hw
*hw
,
2127 void (*rx_check_dma_ok
)(struct ieee80211_hw
*hw
, u8
*header_desc
,
2129 void (*fill_tx_desc
) (struct ieee80211_hw
*hw
,
2130 struct ieee80211_hdr
*hdr
, u8
*pdesc_tx
,
2132 struct ieee80211_tx_info
*info
,
2133 struct ieee80211_sta
*sta
,
2134 struct sk_buff
*skb
, u8 hw_queue
,
2135 struct rtl_tcb_desc
*ptcb_desc
);
2136 void (*fill_fake_txdesc
) (struct ieee80211_hw
*hw
, u8
*pDesc
,
2137 u32 buffer_len
, bool bIsPsPoll
);
2138 void (*fill_tx_cmddesc
) (struct ieee80211_hw
*hw
, u8
*pdesc
,
2139 bool firstseg
, bool lastseg
,
2140 struct sk_buff
*skb
);
2141 bool (*query_rx_desc
) (struct ieee80211_hw
*hw
,
2142 struct rtl_stats
*stats
,
2143 struct ieee80211_rx_status
*rx_status
,
2144 u8
*pdesc
, struct sk_buff
*skb
);
2145 void (*set_channel_access
) (struct ieee80211_hw
*hw
);
2146 bool (*radio_onoff_checking
) (struct ieee80211_hw
*hw
, u8
*valid
);
2147 void (*dm_watchdog
) (struct ieee80211_hw
*hw
);
2148 void (*scan_operation_backup
) (struct ieee80211_hw
*hw
, u8 operation
);
2149 bool (*set_rf_power_state
) (struct ieee80211_hw
*hw
,
2150 enum rf_pwrstate rfpwr_state
);
2151 void (*led_control
) (struct ieee80211_hw
*hw
,
2152 enum led_ctl_mode ledaction
);
2153 void (*set_desc
)(struct ieee80211_hw
*hw
, u8
*pdesc
, bool istx
,
2154 u8 desc_name
, u8
*val
);
2155 u32 (*get_desc
) (u8
*pdesc
, bool istx
, u8 desc_name
);
2156 bool (*is_tx_desc_closed
) (struct ieee80211_hw
*hw
,
2157 u8 hw_queue
, u16 index
);
2158 void (*tx_polling
) (struct ieee80211_hw
*hw
, u8 hw_queue
);
2159 void (*enable_hw_sec
) (struct ieee80211_hw
*hw
);
2160 void (*set_key
) (struct ieee80211_hw
*hw
, u32 key_index
,
2161 u8
*macaddr
, bool is_group
, u8 enc_algo
,
2162 bool is_wepkey
, bool clear_all
);
2163 void (*init_sw_leds
) (struct ieee80211_hw
*hw
);
2164 void (*deinit_sw_leds
) (struct ieee80211_hw
*hw
);
2165 u32 (*get_bbreg
) (struct ieee80211_hw
*hw
, u32 regaddr
, u32 bitmask
);
2166 void (*set_bbreg
) (struct ieee80211_hw
*hw
, u32 regaddr
, u32 bitmask
,
2168 u32 (*get_rfreg
) (struct ieee80211_hw
*hw
, enum radio_path rfpath
,
2169 u32 regaddr
, u32 bitmask
);
2170 void (*set_rfreg
) (struct ieee80211_hw
*hw
, enum radio_path rfpath
,
2171 u32 regaddr
, u32 bitmask
, u32 data
);
2172 void (*linked_set_reg
) (struct ieee80211_hw
*hw
);
2173 void (*chk_switch_dmdp
) (struct ieee80211_hw
*hw
);
2174 void (*dualmac_easy_concurrent
) (struct ieee80211_hw
*hw
);
2175 void (*dualmac_switch_to_dmdp
) (struct ieee80211_hw
*hw
);
2176 bool (*phy_rf6052_config
) (struct ieee80211_hw
*hw
);
2177 void (*phy_rf6052_set_cck_txpower
) (struct ieee80211_hw
*hw
,
2179 void (*phy_rf6052_set_ofdm_txpower
) (struct ieee80211_hw
*hw
,
2180 u8
*ppowerlevel
, u8 channel
);
2181 bool (*config_bb_with_headerfile
) (struct ieee80211_hw
*hw
,
2183 bool (*config_bb_with_pgheaderfile
) (struct ieee80211_hw
*hw
,
2185 void (*phy_lc_calibrate
) (struct ieee80211_hw
*hw
, bool is2t
);
2186 void (*phy_set_bw_mode_callback
) (struct ieee80211_hw
*hw
);
2187 void (*dm_dynamic_txpower
) (struct ieee80211_hw
*hw
);
2188 void (*c2h_command_handle
) (struct ieee80211_hw
*hw
);
2189 void (*bt_wifi_media_status_notify
) (struct ieee80211_hw
*hw
,
2191 void (*bt_coex_off_before_lps
) (struct ieee80211_hw
*hw
);
2192 void (*fill_h2c_cmd
) (struct ieee80211_hw
*hw
, u8 element_id
,
2193 u32 cmd_len
, u8
*p_cmdbuffer
);
2194 bool (*get_btc_status
) (void);
2195 bool (*is_fw_header
)(struct rtlwifi_firmware_header
*hdr
);
2196 u32 (*rx_command_packet
)(struct ieee80211_hw
*hw
,
2197 struct rtl_stats status
, struct sk_buff
*skb
);
2198 void (*add_wowlan_pattern
)(struct ieee80211_hw
*hw
,
2199 struct rtl_wow_pattern
*rtl_pattern
,
2201 u16 (*get_available_desc
)(struct ieee80211_hw
*hw
, u8 q_idx
);
2204 struct rtl_intf_ops
{
2206 void (*read_efuse_byte
)(struct ieee80211_hw
*hw
, u16 _offset
, u8
*pbuf
);
2207 int (*adapter_start
) (struct ieee80211_hw
*hw
);
2208 void (*adapter_stop
) (struct ieee80211_hw
*hw
);
2209 bool (*check_buddy_priv
)(struct ieee80211_hw
*hw
,
2210 struct rtl_priv
**buddy_priv
);
2212 int (*adapter_tx
) (struct ieee80211_hw
*hw
,
2213 struct ieee80211_sta
*sta
,
2214 struct sk_buff
*skb
,
2215 struct rtl_tcb_desc
*ptcb_desc
);
2216 void (*flush
)(struct ieee80211_hw
*hw
, u32 queues
, bool drop
);
2217 int (*reset_trx_ring
) (struct ieee80211_hw
*hw
);
2218 bool (*waitq_insert
) (struct ieee80211_hw
*hw
,
2219 struct ieee80211_sta
*sta
,
2220 struct sk_buff
*skb
);
2223 void (*disable_aspm
) (struct ieee80211_hw
*hw
);
2224 void (*enable_aspm
) (struct ieee80211_hw
*hw
);
2229 struct rtl_mod_params
{
2230 /* default: 0 = using hardware encryption */
2233 /* default: 0 = DBG_EMERG (0)*/
2236 /* default: 1 = using no linked power save */
2239 /* default: 1 = using linked sw power save */
2242 /* default: 1 = using linked fw power save */
2245 /* default: 0 = not using MSI interrupts mode
2246 * submodules should set their own default value
2250 /* default 0: 1 means disable */
2251 bool disable_watchdog
;
2253 /* default 0: 1 means do not disable interrupts */
2257 struct rtl_hal_usbint_cfg
{
2264 void (*usb_rx_hdl
)(struct ieee80211_hw
*, struct sk_buff
*);
2265 void (*usb_rx_segregate_hdl
)(struct ieee80211_hw
*, struct sk_buff
*,
2266 struct sk_buff_head
*);
2269 void (*usb_tx_cleanup
)(struct ieee80211_hw
*, struct sk_buff
*);
2270 int (*usb_tx_post_hdl
)(struct ieee80211_hw
*, struct urb
*,
2272 struct sk_buff
*(*usb_tx_aggregate_hdl
)(struct ieee80211_hw
*,
2273 struct sk_buff_head
*);
2275 /* endpoint mapping */
2276 int (*usb_endpoint_mapping
)(struct ieee80211_hw
*hw
);
2277 u16 (*usb_mq_to_hwq
)(__le16 fc
, u16 mac80211_queue_index
);
2280 struct rtl_hal_cfg
{
2282 bool write_readback
;
2286 char *wowlan_fw_name
;
2287 struct rtl_hal_ops
*ops
;
2288 struct rtl_mod_params
*mod_params
;
2289 struct rtl_hal_usbint_cfg
*usb_interface_cfg
;
2291 /*this map used for some registers or vars
2292 defined int HAL but used in MAIN */
2293 u32 maps
[RTL_VAR_MAP_MAX
];
2299 struct mutex conf_mutex
;
2300 struct mutex ps_mutex
;
2303 spinlock_t ips_lock
;
2304 spinlock_t irq_th_lock
;
2305 spinlock_t irq_pci_lock
;
2307 spinlock_t h2c_lock
;
2308 spinlock_t rf_ps_lock
;
2310 spinlock_t lps_lock
;
2311 spinlock_t waitq_lock
;
2312 spinlock_t entry_list_lock
;
2313 spinlock_t usb_lock
;
2315 /*FW clock change */
2316 spinlock_t fw_ps_lock
;
2319 spinlock_t cck_and_rw_pagea_lock
;
2322 spinlock_t check_sendpkt_lock
;
2324 spinlock_t iqk_lock
;
2328 struct ieee80211_hw
*hw
;
2331 struct timer_list watchdog_timer
;
2332 struct timer_list dualmac_easyconcurrent_retrytimer
;
2333 struct timer_list fw_clockoff_timer
;
2334 struct timer_list fast_antenna_training_timer
;
2336 struct tasklet_struct irq_tasklet
;
2337 struct tasklet_struct irq_prepare_bcn_tasklet
;
2340 struct workqueue_struct
*rtl_wq
;
2341 struct delayed_work watchdog_wq
;
2342 struct delayed_work ips_nic_off_wq
;
2345 struct delayed_work ps_work
;
2346 struct delayed_work ps_rfon_wq
;
2347 struct delayed_work fwevt_wq
;
2349 struct work_struct lps_change_work
;
2350 struct work_struct fill_h2c_cmd
;
2354 u32 dbgp_type
[DBGP_TYPE_MAX
];
2355 int global_debuglevel
;
2356 u64 global_debugcomponents
;
2358 /* add for proc debug */
2359 struct proc_dir_entry
*proc_dir
;
2363 #define MIMO_PS_STATIC 0
2364 #define MIMO_PS_DYNAMIC 1
2365 #define MIMO_PS_NOLIMIT 3
2367 struct rtl_dualmac_easy_concurrent_ctl
{
2368 enum band_type currentbandtype_backfordmdp
;
2369 bool close_bbandrf_for_dmsp
;
2370 bool change_to_dmdp
;
2371 bool change_to_dmsp
;
2372 bool switch_in_process
;
2375 struct rtl_dmsp_ctl
{
2376 bool activescan_for_slaveofdmsp
;
2377 bool scan_for_anothermac_fordmsp
;
2378 bool scan_for_itself_fordmsp
;
2379 bool writedig_for_anothermacofdmsp
;
2380 u32 curdigvalue_for_anothermacofdmsp
;
2381 bool changecckpdstate_for_anothermacofdmsp
;
2382 u8 curcckpdstate_for_anothermacofdmsp
;
2383 bool changetxhighpowerlvl_for_anothermacofdmsp
;
2384 u8 curtxhighlvl_for_anothermacofdmsp
;
2385 long rssivalmin_for_anothermacofdmsp
;
2399 u32 rssi_highthresh
;
2402 long last_min_undec_pwdb_for_dm
;
2403 long rssi_highpower_lowthresh
;
2404 long rssi_highpower_highthresh
;
2410 u8 dig_ext_port_stage
;
2412 u8 dig_twoport_algorithm
;
2414 u8 dig_slgorithm_switch
;
2417 u8 curmultista_cstate
;
2420 char back_range_max
;
2421 char back_range_min
;
2424 u8 min_undec_pwdb_for_dm
;
2426 u8 pre_cck_cca_thres
;
2427 u8 cur_cck_cca_thres
;
2428 u8 pre_cck_pd_state
;
2429 u8 cur_cck_pd_state
;
2430 u8 pre_cck_fa_state
;
2431 u8 cur_cck_fa_state
;
2437 u8 dig_highpwrstate
;
2444 u8 cur_cs_ratiostate
;
2445 u8 pre_cs_ratiostate
;
2446 u8 backoff_enable_flag
;
2447 char backoffval_range_max
;
2448 char backoffval_range_min
;
2452 bool media_connect_0
;
2453 bool media_connect_1
;
2455 u32 antdiv_rssi_max
;
2459 struct rtl_global_var
{
2460 /* from this list we can get
2461 * other adapter's rtl_priv */
2462 struct list_head glb_priv_list
;
2463 spinlock_t glb_list_lock
;
2466 struct rtl_btc_info
{
2472 struct bt_coexist_info
{
2473 struct rtl_btc_ops
*btc_ops
;
2474 struct rtl_btc_info btc_info
;
2475 /* EEPROM BT info. */
2476 u8 eeprom_bt_coexist
;
2478 u8 eeprom_bt_ant_num
;
2479 u8 eeprom_bt_ant_isol
;
2480 u8 eeprom_bt_radio_shared
;
2486 u8 bt_cur_state
; /* 0:on, 1:off */
2487 u8 bt_ant_isolation
; /* 0:good, 1:bad */
2488 u8 bt_pape_ctrl
; /* 0:SW, 1:SW/HW dynamic */
2490 u8 bt_radio_shared_type
;
2491 u8 bt_rfreg_origin_1e
;
2492 u8 bt_rfreg_origin_1f
;
2500 bool bt_busy_traffic
;
2501 bool bt_traffic_mode_set
;
2502 bool bt_non_traffic_mode_set
;
2504 bool fw_coexist_all_off
;
2505 bool sw_coexist_all_off
;
2506 bool hw_coexist_all_off
;
2510 u32 previous_state_h
;
2512 u8 bt_pre_rssi_state
;
2513 u8 bt_pre_rssi_state1
;
2518 u8 bt_active_zero_cnt
;
2519 bool cur_bt_disabled
;
2520 bool pre_bt_disabled
;
2523 u8 bt_profile_action
;
2525 bool hold_for_bt_operation
;
2529 struct rtl_btc_ops
{
2530 void (*btc_init_variables
) (struct rtl_priv
*rtlpriv
);
2531 void (*btc_init_hal_vars
) (struct rtl_priv
*rtlpriv
);
2532 void (*btc_init_hw_config
) (struct rtl_priv
*rtlpriv
);
2533 void (*btc_ips_notify
) (struct rtl_priv
*rtlpriv
, u8 type
);
2534 void (*btc_lps_notify
)(struct rtl_priv
*rtlpriv
, u8 type
);
2535 void (*btc_scan_notify
) (struct rtl_priv
*rtlpriv
, u8 scantype
);
2536 void (*btc_connect_notify
) (struct rtl_priv
*rtlpriv
, u8 action
);
2537 void (*btc_mediastatus_notify
) (struct rtl_priv
*rtlpriv
,
2538 enum rt_media_status mstatus
);
2539 void (*btc_periodical
) (struct rtl_priv
*rtlpriv
);
2540 void (*btc_halt_notify
) (void);
2541 void (*btc_btinfo_notify
) (struct rtl_priv
*rtlpriv
,
2542 u8
*tmp_buf
, u8 length
);
2543 bool (*btc_is_limited_dig
) (struct rtl_priv
*rtlpriv
);
2544 bool (*btc_is_disable_edca_turbo
) (struct rtl_priv
*rtlpriv
);
2545 bool (*btc_is_bt_disabled
) (struct rtl_priv
*rtlpriv
);
2546 void (*btc_special_packet_notify
)(struct rtl_priv
*rtlpriv
,
2553 void *proximity_priv
;
2554 int (*proxim_rx
)(struct ieee80211_hw
*hw
, struct rtl_stats
*status
,
2555 struct sk_buff
*skb
);
2556 u8 (*proxim_get_var
)(struct ieee80211_hw
*hw
, u8 type
);
2560 struct ieee80211_hw
*hw
;
2561 struct completion firmware_loading_complete
;
2562 struct list_head list
;
2563 struct rtl_priv
*buddy_priv
;
2564 struct rtl_global_var
*glb_var
;
2565 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl
;
2566 struct rtl_dmsp_ctl dmsp_ctl
;
2567 struct rtl_locks locks
;
2568 struct rtl_works works
;
2569 struct rtl_mac mac80211
;
2570 struct rtl_hal rtlhal
;
2571 struct rtl_regulatory regd
;
2572 struct rtl_rfkill rfkill
;
2576 struct rtl_security sec
;
2577 struct rtl_efuse efuse
;
2579 struct rtl_ps_ctl psc
;
2580 struct rate_adaptive ra
;
2581 struct dynamic_primary_cca primarycca
;
2582 struct wireless_stats stats
;
2583 struct rt_link_detect link_info
;
2584 struct false_alarm_statistics falsealm_cnt
;
2586 struct rtl_rate_priv
*rate_priv
;
2588 /* sta entry list for ap adhoc or mesh */
2589 struct list_head entry_list
;
2591 struct rtl_debug dbg
;
2595 *hal_cfg : for diff cards
2596 *intf_ops : for diff interrface usb/pcie
2598 struct rtl_hal_cfg
*cfg
;
2599 struct rtl_intf_ops
*intf_ops
;
2601 /*this var will be set by set_bit,
2602 and was used to indicate status of
2603 interface or hardware */
2604 unsigned long status
;
2607 struct dig_t dm_digtable
;
2608 struct ps_t dm_pstable
;
2614 bool reg_init
; /* true if regs saved */
2615 bool bt_operation_on
;
2619 bool enter_ps
; /* true when entering PS */
2622 /* intel Proximity, should be alloc mem
2623 * in intel Proximity module and can only
2624 * be used in intel Proximity mode
2626 struct proxim proximity
;
2628 /*for bt coexist use*/
2629 struct bt_coexist_info btcoexist
;
2631 /* separate 92ee from other ICs,
2632 * 92ee use new trx flow.
2634 bool use_new_trx_flow
;
2637 struct wiphy_wowlan_support wowlan
;
2639 /*This must be the last item so
2640 that it points to the data allocated
2641 beyond this structure like:
2642 rtl_pci_priv or rtl_usb_priv */
2643 u8 priv
[0] __aligned(sizeof(void *));
2646 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
2647 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
2648 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
2649 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
2650 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
2653 /***************************************
2654 Bluetooth Co-existence Related
2655 ****************************************/
2676 enum bt_total_ant_num
{
2686 enum bt_service_type
{
2693 BT_OTHER_ACTION
= 6,
2699 enum bt_radio_shared
{
2700 BT_RADIO_SHARED
= 0,
2701 BT_RADIO_INDIVIDUAL
= 1,
2705 /****************************************
2706 mem access macro define start
2707 Call endian free function when
2708 1. Read/write packet content.
2709 2. Before write integer to IO.
2710 3. After read integer from IO.
2711 ****************************************/
2712 /* Convert little data endian to host ordering */
2713 #define EF1BYTE(_val) \
2715 #define EF2BYTE(_val) \
2717 #define EF4BYTE(_val) \
2720 /* Read data from memory */
2721 #define READEF1BYTE(_ptr) \
2722 EF1BYTE(*((u8 *)(_ptr)))
2723 /* Read le16 data from memory and convert to host ordering */
2724 #define READEF2BYTE(_ptr) \
2726 #define READEF4BYTE(_ptr) \
2729 /* Write data to memory */
2730 #define WRITEEF1BYTE(_ptr, _val) \
2731 (*((u8 *)(_ptr))) = EF1BYTE(_val)
2732 /* Write le16 data to memory in host ordering */
2733 #define WRITEEF2BYTE(_ptr, _val) \
2734 (*((u16 *)(_ptr))) = EF2BYTE(_val)
2735 #define WRITEEF4BYTE(_ptr, _val) \
2736 (*((u32 *)(_ptr))) = EF2BYTE(_val)
2738 /* Create a bit mask
2740 * BIT_LEN_MASK_32(0) => 0x00000000
2741 * BIT_LEN_MASK_32(1) => 0x00000001
2742 * BIT_LEN_MASK_32(2) => 0x00000003
2743 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
2745 #define BIT_LEN_MASK_32(__bitlen) \
2746 (0xFFFFFFFF >> (32 - (__bitlen)))
2747 #define BIT_LEN_MASK_16(__bitlen) \
2748 (0xFFFF >> (16 - (__bitlen)))
2749 #define BIT_LEN_MASK_8(__bitlen) \
2750 (0xFF >> (8 - (__bitlen)))
2752 /* Create an offset bit mask
2754 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
2755 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
2757 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
2758 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
2759 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
2760 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
2761 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
2762 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
2765 * Return 4-byte value in host byte ordering from
2766 * 4-byte pointer in little-endian system.
2768 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
2769 (EF4BYTE(*((__le32 *)(__pstart))))
2770 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
2771 (EF2BYTE(*((__le16 *)(__pstart))))
2772 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
2773 (EF1BYTE(*((u8 *)(__pstart))))
2776 Translate subfield (continuous bits in little-endian) of 4-byte
2777 value to host byte ordering.*/
2778 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2780 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
2781 BIT_LEN_MASK_32(__bitlen) \
2783 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2785 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
2786 BIT_LEN_MASK_16(__bitlen) \
2788 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2790 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
2791 BIT_LEN_MASK_8(__bitlen) \
2795 * Mask subfield (continuous bits in little-endian) of 4-byte value
2796 * and return the result in 4-byte value in host byte ordering.
2798 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2800 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
2801 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
2803 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2805 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
2806 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
2808 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2810 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
2811 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
2815 * Set subfield of little-endian 4-byte value to specified value.
2817 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
2818 *((u32 *)(__pstart)) = \
2820 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
2821 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
2823 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
2824 *((u16 *)(__pstart)) = \
2826 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
2827 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
2829 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
2830 *((u8 *)(__pstart)) = EF1BYTE \
2832 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
2833 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
2836 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
2837 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
2839 /****************************************
2840 mem access macro define end
2841 ****************************************/
2843 #define byte(x, n) ((x >> (8 * n)) & 0xff)
2845 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
2846 #define RTL_WATCH_DOG_TIME 2000
2847 #define MSECS(t) msecs_to_jiffies(t)
2848 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
2849 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
2850 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
2851 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
2852 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm))
2854 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
2855 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
2856 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
2857 /*NIC halt, re-initialize hw parameters*/
2858 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
2859 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
2860 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
2861 /*Always enable ASPM and Clock Req in initialization.*/
2862 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
2863 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
2864 #define RT_PS_LEVEL_ASPM BIT(7)
2865 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
2866 #define RT_RF_LPS_DISALBE_2R BIT(30)
2867 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
2868 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
2869 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
2870 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
2871 (ppsc->cur_ps_level &= (~(_ps_flg)))
2872 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
2873 (ppsc->cur_ps_level |= _ps_flg)
2875 #define container_of_dwork_rtl(x, y, z) \
2876 container_of(container_of(x, struct delayed_work, work), y, z)
2878 #define FILL_OCTET_STRING(_os, _octet, _len) \
2879 (_os).octet = (u8 *)(_octet); \
2880 (_os).length = (_len);
2882 #define CP_MACADDR(des, src) \
2883 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
2884 (des)[2] = (src)[2], (des)[3] = (src)[3],\
2885 (des)[4] = (src)[4], (des)[5] = (src)[5])
2887 #define LDPC_HT_ENABLE_RX BIT(0)
2888 #define LDPC_HT_ENABLE_TX BIT(1)
2889 #define LDPC_HT_TEST_TX_ENABLE BIT(2)
2890 #define LDPC_HT_CAP_TX BIT(3)
2892 #define STBC_HT_ENABLE_RX BIT(0)
2893 #define STBC_HT_ENABLE_TX BIT(1)
2894 #define STBC_HT_TEST_TX_ENABLE BIT(2)
2895 #define STBC_HT_CAP_TX BIT(3)
2897 #define LDPC_VHT_ENABLE_RX BIT(0)
2898 #define LDPC_VHT_ENABLE_TX BIT(1)
2899 #define LDPC_VHT_TEST_TX_ENABLE BIT(2)
2900 #define LDPC_VHT_CAP_TX BIT(3)
2902 #define STBC_VHT_ENABLE_RX BIT(0)
2903 #define STBC_VHT_ENABLE_TX BIT(1)
2904 #define STBC_VHT_TEST_TX_ENABLE BIT(2)
2905 #define STBC_VHT_CAP_TX BIT(3)
2907 static inline u8
rtl_read_byte(struct rtl_priv
*rtlpriv
, u32 addr
)
2909 return rtlpriv
->io
.read8_sync(rtlpriv
, addr
);
2912 static inline u16
rtl_read_word(struct rtl_priv
*rtlpriv
, u32 addr
)
2914 return rtlpriv
->io
.read16_sync(rtlpriv
, addr
);
2917 static inline u32
rtl_read_dword(struct rtl_priv
*rtlpriv
, u32 addr
)
2919 return rtlpriv
->io
.read32_sync(rtlpriv
, addr
);
2922 static inline void rtl_write_byte(struct rtl_priv
*rtlpriv
, u32 addr
, u8 val8
)
2924 rtlpriv
->io
.write8_async(rtlpriv
, addr
, val8
);
2926 if (rtlpriv
->cfg
->write_readback
)
2927 rtlpriv
->io
.read8_sync(rtlpriv
, addr
);
2930 static inline void rtl_write_word(struct rtl_priv
*rtlpriv
, u32 addr
, u16 val16
)
2932 rtlpriv
->io
.write16_async(rtlpriv
, addr
, val16
);
2934 if (rtlpriv
->cfg
->write_readback
)
2935 rtlpriv
->io
.read16_sync(rtlpriv
, addr
);
2938 static inline void rtl_write_dword(struct rtl_priv
*rtlpriv
,
2939 u32 addr
, u32 val32
)
2941 rtlpriv
->io
.write32_async(rtlpriv
, addr
, val32
);
2943 if (rtlpriv
->cfg
->write_readback
)
2944 rtlpriv
->io
.read32_sync(rtlpriv
, addr
);
2947 static inline u32
rtl_get_bbreg(struct ieee80211_hw
*hw
,
2948 u32 regaddr
, u32 bitmask
)
2950 struct rtl_priv
*rtlpriv
= hw
->priv
;
2952 return rtlpriv
->cfg
->ops
->get_bbreg(hw
, regaddr
, bitmask
);
2955 static inline void rtl_set_bbreg(struct ieee80211_hw
*hw
, u32 regaddr
,
2956 u32 bitmask
, u32 data
)
2958 struct rtl_priv
*rtlpriv
= hw
->priv
;
2960 rtlpriv
->cfg
->ops
->set_bbreg(hw
, regaddr
, bitmask
, data
);
2963 static inline u32
rtl_get_rfreg(struct ieee80211_hw
*hw
,
2964 enum radio_path rfpath
, u32 regaddr
,
2967 struct rtl_priv
*rtlpriv
= hw
->priv
;
2969 return rtlpriv
->cfg
->ops
->get_rfreg(hw
, rfpath
, regaddr
, bitmask
);
2972 static inline void rtl_set_rfreg(struct ieee80211_hw
*hw
,
2973 enum radio_path rfpath
, u32 regaddr
,
2974 u32 bitmask
, u32 data
)
2976 struct rtl_priv
*rtlpriv
= hw
->priv
;
2978 rtlpriv
->cfg
->ops
->set_rfreg(hw
, rfpath
, regaddr
, bitmask
, data
);
2981 static inline bool is_hal_stop(struct rtl_hal
*rtlhal
)
2983 return (_HAL_STATE_STOP
== rtlhal
->state
);
2986 static inline void set_hal_start(struct rtl_hal
*rtlhal
)
2988 rtlhal
->state
= _HAL_STATE_START
;
2991 static inline void set_hal_stop(struct rtl_hal
*rtlhal
)
2993 rtlhal
->state
= _HAL_STATE_STOP
;
2996 static inline u8
get_rf_type(struct rtl_phy
*rtlphy
)
2998 return rtlphy
->rf_type
;
3001 static inline struct ieee80211_hdr
*rtl_get_hdr(struct sk_buff
*skb
)
3003 return (struct ieee80211_hdr
*)(skb
->data
);
3006 static inline __le16
rtl_get_fc(struct sk_buff
*skb
)
3008 return rtl_get_hdr(skb
)->frame_control
;
3011 static inline u16
rtl_get_tid_h(struct ieee80211_hdr
*hdr
)
3013 return (ieee80211_get_qos_ctl(hdr
))[0] & IEEE80211_QOS_CTL_TID_MASK
;
3016 static inline u16
rtl_get_tid(struct sk_buff
*skb
)
3018 return rtl_get_tid_h(rtl_get_hdr(skb
));
3021 static inline struct ieee80211_sta
*get_sta(struct ieee80211_hw
*hw
,
3022 struct ieee80211_vif
*vif
,
3025 return ieee80211_find_sta(vif
, bssid
);
3028 static inline struct ieee80211_sta
*rtl_find_sta(struct ieee80211_hw
*hw
,
3031 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
3032 return ieee80211_find_sta(mac
->vif
, mac_addr
);