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rt2x00: Cleanup mode registration
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
1 /*
2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt2400pci
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
25 */
26
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
34
35 #include "rt2x00.h"
36 #include "rt2x00pci.h"
37 #include "rt2400pci.h"
38
39 /*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 */
52 static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
53 {
54 u32 reg;
55 unsigned int i;
56
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
60 break;
61 udelay(REGISTER_BUSY_DELAY);
62 }
63
64 return reg;
65 }
66
67 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
68 const unsigned int word, const u8 value)
69 {
70 u32 reg;
71
72 /*
73 * Wait until the BBP becomes ready.
74 */
75 reg = rt2400pci_bbp_check(rt2x00dev);
76 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
78 return;
79 }
80
81 /*
82 * Write the data into the BBP.
83 */
84 reg = 0;
85 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
86 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
89
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
91 }
92
93 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
94 const unsigned int word, u8 *value)
95 {
96 u32 reg;
97
98 /*
99 * Wait until the BBP becomes ready.
100 */
101 reg = rt2400pci_bbp_check(rt2x00dev);
102 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
104 return;
105 }
106
107 /*
108 * Write the request into the BBP.
109 */
110 reg = 0;
111 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
112 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
113 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
114
115 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
116
117 /*
118 * Wait until the BBP becomes ready.
119 */
120 reg = rt2400pci_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
123 *value = 0xff;
124 return;
125 }
126
127 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
128 }
129
130 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
131 const unsigned int word, const u32 value)
132 {
133 u32 reg;
134 unsigned int i;
135
136 if (!word)
137 return;
138
139 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
141 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
142 goto rf_write;
143 udelay(REGISTER_BUSY_DELAY);
144 }
145
146 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
147 return;
148
149 rf_write:
150 reg = 0;
151 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
152 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
153 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
154 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
155
156 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157 rt2x00_rf_write(rt2x00dev, word, value);
158 }
159
160 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
161 {
162 struct rt2x00_dev *rt2x00dev = eeprom->data;
163 u32 reg;
164
165 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
166
167 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169 eeprom->reg_data_clock =
170 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171 eeprom->reg_chip_select =
172 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
173 }
174
175 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
176 {
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
178 u32 reg = 0;
179
180 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
183 !!eeprom->reg_data_clock);
184 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
185 !!eeprom->reg_chip_select);
186
187 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
188 }
189
190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
191 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
192
193 static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
194 const unsigned int word, u32 *data)
195 {
196 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
197 }
198
199 static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, u32 data)
201 {
202 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
203 }
204
205 static const struct rt2x00debug rt2400pci_rt2x00debug = {
206 .owner = THIS_MODULE,
207 .csr = {
208 .read = rt2400pci_read_csr,
209 .write = rt2400pci_write_csr,
210 .word_size = sizeof(u32),
211 .word_count = CSR_REG_SIZE / sizeof(u32),
212 },
213 .eeprom = {
214 .read = rt2x00_eeprom_read,
215 .write = rt2x00_eeprom_write,
216 .word_size = sizeof(u16),
217 .word_count = EEPROM_SIZE / sizeof(u16),
218 },
219 .bbp = {
220 .read = rt2400pci_bbp_read,
221 .write = rt2400pci_bbp_write,
222 .word_size = sizeof(u8),
223 .word_count = BBP_SIZE / sizeof(u8),
224 },
225 .rf = {
226 .read = rt2x00_rf_read,
227 .write = rt2400pci_rf_write,
228 .word_size = sizeof(u32),
229 .word_count = RF_SIZE / sizeof(u32),
230 },
231 };
232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
233
234 #ifdef CONFIG_RT2400PCI_RFKILL
235 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
236 {
237 u32 reg;
238
239 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
240 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
241 }
242 #else
243 #define rt2400pci_rfkill_poll NULL
244 #endif /* CONFIG_RT2400PCI_RFKILL */
245
246 #ifdef CONFIG_RT2400PCI_LEDS
247 static void rt2400pci_led_brightness(struct led_classdev *led_cdev,
248 enum led_brightness brightness)
249 {
250 struct rt2x00_led *led =
251 container_of(led_cdev, struct rt2x00_led, led_dev);
252 unsigned int enabled = brightness != LED_OFF;
253 unsigned int activity =
254 led->rt2x00dev->led_flags & LED_SUPPORT_ACTIVITY;
255 u32 reg;
256
257 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
258
259 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC) {
260 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
261 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled && activity);
262 }
263
264 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
265 }
266 #else
267 #define rt2400pci_led_brightness NULL
268 #endif /* CONFIG_RT2400PCI_LEDS */
269
270 /*
271 * Configuration handlers.
272 */
273 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
274 struct rt2x00_intf *intf,
275 struct rt2x00intf_conf *conf,
276 const unsigned int flags)
277 {
278 unsigned int bcn_preload;
279 u32 reg;
280
281 if (flags & CONFIG_UPDATE_TYPE) {
282 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
283
284 /*
285 * Enable beacon config
286 */
287 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
288 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
289 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
290 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
291
292 /*
293 * Enable synchronisation.
294 */
295 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
296 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
297 rt2x00_set_field32(&reg, CSR14_TBCN,
298 (conf->sync == TSF_SYNC_BEACON));
299 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
300 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
301 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
302 }
303
304 if (flags & CONFIG_UPDATE_MAC)
305 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
306 conf->mac, sizeof(conf->mac));
307
308 if (flags & CONFIG_UPDATE_BSSID)
309 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
310 conf->bssid, sizeof(conf->bssid));
311 }
312
313 static int rt2400pci_config_preamble(struct rt2x00_dev *rt2x00dev,
314 const int short_preamble,
315 const int ack_timeout,
316 const int ack_consume_time)
317 {
318 int preamble_mask;
319 u32 reg;
320
321 /*
322 * When short preamble is enabled, we should set bit 0x08
323 */
324 preamble_mask = short_preamble << 3;
325
326 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
327 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, ack_timeout);
328 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, ack_consume_time);
329 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
330
331 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
332 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
333 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
334 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
335 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
336
337 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
338 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
339 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
340 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
341 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
342
343 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
344 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
345 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
346 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
347 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
348
349 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
350 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
351 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
352 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
353 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
354
355 return 0;
356 }
357
358 static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
359 const int basic_rate_mask)
360 {
361 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
362 }
363
364 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
365 struct rf_channel *rf)
366 {
367 /*
368 * Switch on tuning bits.
369 */
370 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
371 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
372
373 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
374 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
375 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
376
377 /*
378 * RF2420 chipset don't need any additional actions.
379 */
380 if (rt2x00_rf(&rt2x00dev->chip, RF2420))
381 return;
382
383 /*
384 * For the RT2421 chipsets we need to write an invalid
385 * reference clock rate to activate auto_tune.
386 * After that we set the value back to the correct channel.
387 */
388 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
389 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
390 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
391
392 msleep(1);
393
394 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
395 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
396 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
397
398 msleep(1);
399
400 /*
401 * Switch off tuning bits.
402 */
403 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
404 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
405
406 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
407 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
408
409 /*
410 * Clear false CRC during channel switch.
411 */
412 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
413 }
414
415 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
416 {
417 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
418 }
419
420 static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
421 struct antenna_setup *ant)
422 {
423 u8 r1;
424 u8 r4;
425
426 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
427 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
428
429 /*
430 * Configure the TX antenna.
431 */
432 switch (ant->tx) {
433 case ANTENNA_HW_DIVERSITY:
434 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
435 break;
436 case ANTENNA_A:
437 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
438 break;
439 case ANTENNA_SW_DIVERSITY:
440 /*
441 * NOTE: We should never come here because rt2x00lib is
442 * supposed to catch this and send us the correct antenna
443 * explicitely. However we are nog going to bug about this.
444 * Instead, just default to antenna B.
445 */
446 case ANTENNA_B:
447 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
448 break;
449 }
450
451 /*
452 * Configure the RX antenna.
453 */
454 switch (ant->rx) {
455 case ANTENNA_HW_DIVERSITY:
456 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
457 break;
458 case ANTENNA_A:
459 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
460 break;
461 case ANTENNA_SW_DIVERSITY:
462 /*
463 * NOTE: We should never come here because rt2x00lib is
464 * supposed to catch this and send us the correct antenna
465 * explicitely. However we are nog going to bug about this.
466 * Instead, just default to antenna B.
467 */
468 case ANTENNA_B:
469 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
470 break;
471 }
472
473 rt2400pci_bbp_write(rt2x00dev, 4, r4);
474 rt2400pci_bbp_write(rt2x00dev, 1, r1);
475 }
476
477 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
478 struct rt2x00lib_conf *libconf)
479 {
480 u32 reg;
481
482 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
483 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
484 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
485
486 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
487 rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
488 rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
489 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
490
491 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
492 rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
493 rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
494 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
495
496 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
497 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
498 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
499 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
500
501 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
502 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
503 libconf->conf->beacon_int * 16);
504 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
505 libconf->conf->beacon_int * 16);
506 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
507 }
508
509 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
510 struct rt2x00lib_conf *libconf,
511 const unsigned int flags)
512 {
513 if (flags & CONFIG_UPDATE_PHYMODE)
514 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
515 if (flags & CONFIG_UPDATE_CHANNEL)
516 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
517 if (flags & CONFIG_UPDATE_TXPOWER)
518 rt2400pci_config_txpower(rt2x00dev,
519 libconf->conf->power_level);
520 if (flags & CONFIG_UPDATE_ANTENNA)
521 rt2400pci_config_antenna(rt2x00dev, &libconf->ant);
522 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
523 rt2400pci_config_duration(rt2x00dev, libconf);
524 }
525
526 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
527 const int cw_min, const int cw_max)
528 {
529 u32 reg;
530
531 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
532 rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
533 rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
534 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
535 }
536
537 /*
538 * Link tuning
539 */
540 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
541 struct link_qual *qual)
542 {
543 u32 reg;
544 u8 bbp;
545
546 /*
547 * Update FCS error count from register.
548 */
549 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
550 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
551
552 /*
553 * Update False CCA count from register.
554 */
555 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
556 qual->false_cca = bbp;
557 }
558
559 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
560 {
561 rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
562 rt2x00dev->link.vgc_level = 0x08;
563 }
564
565 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
566 {
567 u8 reg;
568
569 /*
570 * The link tuner should not run longer then 60 seconds,
571 * and should run once every 2 seconds.
572 */
573 if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
574 return;
575
576 /*
577 * Base r13 link tuning on the false cca count.
578 */
579 rt2400pci_bbp_read(rt2x00dev, 13, &reg);
580
581 if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
582 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
583 rt2x00dev->link.vgc_level = reg;
584 } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
585 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
586 rt2x00dev->link.vgc_level = reg;
587 }
588 }
589
590 /*
591 * Initialization functions.
592 */
593 static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
594 struct queue_entry *entry)
595 {
596 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
597 u32 word;
598
599 rt2x00_desc_read(priv_rx->desc, 2, &word);
600 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
601 entry->queue->data_size);
602 rt2x00_desc_write(priv_rx->desc, 2, word);
603
604 rt2x00_desc_read(priv_rx->desc, 1, &word);
605 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);
606 rt2x00_desc_write(priv_rx->desc, 1, word);
607
608 rt2x00_desc_read(priv_rx->desc, 0, &word);
609 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
610 rt2x00_desc_write(priv_rx->desc, 0, word);
611 }
612
613 static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
614 struct queue_entry *entry)
615 {
616 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
617 u32 word;
618
619 rt2x00_desc_read(priv_tx->desc, 1, &word);
620 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
621 rt2x00_desc_write(priv_tx->desc, 1, word);
622
623 rt2x00_desc_read(priv_tx->desc, 2, &word);
624 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
625 entry->queue->data_size);
626 rt2x00_desc_write(priv_tx->desc, 2, word);
627
628 rt2x00_desc_read(priv_tx->desc, 0, &word);
629 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
630 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
631 rt2x00_desc_write(priv_tx->desc, 0, word);
632 }
633
634 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
635 {
636 struct queue_entry_priv_pci_rx *priv_rx;
637 struct queue_entry_priv_pci_tx *priv_tx;
638 u32 reg;
639
640 /*
641 * Initialize registers.
642 */
643 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
644 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
645 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
646 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
647 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
648 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
649
650 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
651 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
652 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
653 priv_tx->desc_dma);
654 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
655
656 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
657 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
658 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
659 priv_tx->desc_dma);
660 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
661
662 priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
663 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
664 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
665 priv_tx->desc_dma);
666 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
667
668 priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
669 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
670 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
671 priv_tx->desc_dma);
672 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
673
674 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
675 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
676 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
677 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
678
679 priv_rx = rt2x00dev->rx->entries[0].priv_data;
680 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
681 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_tx->desc_dma);
682 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
683
684 return 0;
685 }
686
687 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
688 {
689 u32 reg;
690
691 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
692 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
693 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
694 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
695
696 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
697 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
698 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
699 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
700 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
701
702 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
703 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
704 (rt2x00dev->rx->data_size / 128));
705 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
706
707 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
708 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
709 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
710 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
711
712 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
713
714 rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
715 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
716 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
717 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
718 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
719 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
720
721 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
722 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
723 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
724 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
725 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
726 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
727 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
728 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
729
730 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
731
732 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
733 return -EBUSY;
734
735 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
736 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
737
738 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
739 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
740 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
741
742 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
743 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
744 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
745 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
746 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
747 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
748
749 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
750 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
751 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
752 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
753 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
754
755 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
756 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
757 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
758 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
759
760 /*
761 * We must clear the FCS and FIFO error count.
762 * These registers are cleared on read,
763 * so we may pass a useless variable to store the value.
764 */
765 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
766 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
767
768 return 0;
769 }
770
771 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
772 {
773 unsigned int i;
774 u16 eeprom;
775 u8 reg_id;
776 u8 value;
777
778 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
779 rt2400pci_bbp_read(rt2x00dev, 0, &value);
780 if ((value != 0xff) && (value != 0x00))
781 goto continue_csr_init;
782 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
783 udelay(REGISTER_BUSY_DELAY);
784 }
785
786 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
787 return -EACCES;
788
789 continue_csr_init:
790 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
791 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
792 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
793 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
794 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
795 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
796 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
797 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
798 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
799 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
800 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
801 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
802 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
803 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
804
805 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
806 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
807
808 if (eeprom != 0xffff && eeprom != 0x0000) {
809 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
810 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
811 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
812 }
813 }
814
815 return 0;
816 }
817
818 /*
819 * Device state switch handlers.
820 */
821 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
822 enum dev_state state)
823 {
824 u32 reg;
825
826 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
827 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
828 state == STATE_RADIO_RX_OFF);
829 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
830 }
831
832 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
833 enum dev_state state)
834 {
835 int mask = (state == STATE_RADIO_IRQ_OFF);
836 u32 reg;
837
838 /*
839 * When interrupts are being enabled, the interrupt registers
840 * should clear the register to assure a clean state.
841 */
842 if (state == STATE_RADIO_IRQ_ON) {
843 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
844 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
845 }
846
847 /*
848 * Only toggle the interrupts bits we are going to use.
849 * Non-checked interrupt bits are disabled by default.
850 */
851 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
852 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
853 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
854 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
855 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
856 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
857 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
858 }
859
860 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
861 {
862 /*
863 * Initialize all registers.
864 */
865 if (rt2400pci_init_queues(rt2x00dev) ||
866 rt2400pci_init_registers(rt2x00dev) ||
867 rt2400pci_init_bbp(rt2x00dev)) {
868 ERROR(rt2x00dev, "Register initialization failed.\n");
869 return -EIO;
870 }
871
872 /*
873 * Enable interrupts.
874 */
875 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
876
877 return 0;
878 }
879
880 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
881 {
882 u32 reg;
883
884 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
885
886 /*
887 * Disable synchronisation.
888 */
889 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
890
891 /*
892 * Cancel RX and TX.
893 */
894 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
895 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
896 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
897
898 /*
899 * Disable interrupts.
900 */
901 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
902 }
903
904 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
905 enum dev_state state)
906 {
907 u32 reg;
908 unsigned int i;
909 char put_to_sleep;
910 char bbp_state;
911 char rf_state;
912
913 put_to_sleep = (state != STATE_AWAKE);
914
915 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
916 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
917 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
918 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
919 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
920 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
921
922 /*
923 * Device is not guaranteed to be in the requested state yet.
924 * We must wait until the register indicates that the
925 * device has entered the correct state.
926 */
927 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
928 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
929 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
930 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
931 if (bbp_state == state && rf_state == state)
932 return 0;
933 msleep(10);
934 }
935
936 NOTICE(rt2x00dev, "Device failed to enter state %d, "
937 "current device state: bbp %d and rf %d.\n",
938 state, bbp_state, rf_state);
939
940 return -EBUSY;
941 }
942
943 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
944 enum dev_state state)
945 {
946 int retval = 0;
947
948 switch (state) {
949 case STATE_RADIO_ON:
950 retval = rt2400pci_enable_radio(rt2x00dev);
951 break;
952 case STATE_RADIO_OFF:
953 rt2400pci_disable_radio(rt2x00dev);
954 break;
955 case STATE_RADIO_RX_ON:
956 case STATE_RADIO_RX_ON_LINK:
957 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
958 break;
959 case STATE_RADIO_RX_OFF:
960 case STATE_RADIO_RX_OFF_LINK:
961 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
962 break;
963 case STATE_DEEP_SLEEP:
964 case STATE_SLEEP:
965 case STATE_STANDBY:
966 case STATE_AWAKE:
967 retval = rt2400pci_set_state(rt2x00dev, state);
968 break;
969 default:
970 retval = -ENOTSUPP;
971 break;
972 }
973
974 return retval;
975 }
976
977 /*
978 * TX descriptor initialization
979 */
980 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
981 struct sk_buff *skb,
982 struct txentry_desc *txdesc,
983 struct ieee80211_tx_control *control)
984 {
985 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
986 __le32 *txd = skbdesc->desc;
987 u32 word;
988
989 /*
990 * Start writing the descriptor words.
991 */
992 rt2x00_desc_read(txd, 2, &word);
993 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skbdesc->data_len);
994 rt2x00_desc_write(txd, 2, word);
995
996 rt2x00_desc_read(txd, 3, &word);
997 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
998 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
999 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1000 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1001 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1002 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1003 rt2x00_desc_write(txd, 3, word);
1004
1005 rt2x00_desc_read(txd, 4, &word);
1006 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
1007 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1008 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1009 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
1010 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1011 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1012 rt2x00_desc_write(txd, 4, word);
1013
1014 rt2x00_desc_read(txd, 0, &word);
1015 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1016 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1017 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1018 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1019 rt2x00_set_field32(&word, TXD_W0_ACK,
1020 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1021 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1022 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1023 rt2x00_set_field32(&word, TXD_W0_RTS,
1024 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1025 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1026 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1027 !!(control->flags &
1028 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1029 rt2x00_desc_write(txd, 0, word);
1030 }
1031
1032 /*
1033 * TX data initialization
1034 */
1035 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1036 const unsigned int queue)
1037 {
1038 u32 reg;
1039
1040 if (queue == RT2X00_BCN_QUEUE_BEACON) {
1041 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1042 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1043 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1044 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1045 }
1046 return;
1047 }
1048
1049 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1050 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO,
1051 (queue == IEEE80211_TX_QUEUE_DATA0));
1052 rt2x00_set_field32(&reg, TXCSR0_KICK_TX,
1053 (queue == IEEE80211_TX_QUEUE_DATA1));
1054 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
1055 (queue == RT2X00_BCN_QUEUE_ATIM));
1056 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1057 }
1058
1059 /*
1060 * RX control handlers
1061 */
1062 static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1063 struct rxdone_entry_desc *rxdesc)
1064 {
1065 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1066 u32 word0;
1067 u32 word2;
1068
1069 rt2x00_desc_read(priv_rx->desc, 0, &word0);
1070 rt2x00_desc_read(priv_rx->desc, 2, &word2);
1071
1072 rxdesc->flags = 0;
1073 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1074 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1075 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1076 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1077
1078 /*
1079 * Obtain the status about this packet.
1080 */
1081 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1082 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1083 entry->queue->rt2x00dev->rssi_offset;
1084 rxdesc->ofdm = 0;
1085 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1086 rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
1087 }
1088
1089 /*
1090 * Interrupt functions.
1091 */
1092 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1093 const enum ieee80211_tx_queue queue_idx)
1094 {
1095 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1096 struct queue_entry_priv_pci_tx *priv_tx;
1097 struct queue_entry *entry;
1098 struct txdone_entry_desc txdesc;
1099 u32 word;
1100
1101 while (!rt2x00queue_empty(queue)) {
1102 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1103 priv_tx = entry->priv_data;
1104 rt2x00_desc_read(priv_tx->desc, 0, &word);
1105
1106 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1107 !rt2x00_get_field32(word, TXD_W0_VALID))
1108 break;
1109
1110 /*
1111 * Obtain the status about this packet.
1112 */
1113 txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT);
1114 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1115
1116 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1117 }
1118 }
1119
1120 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1121 {
1122 struct rt2x00_dev *rt2x00dev = dev_instance;
1123 u32 reg;
1124
1125 /*
1126 * Get the interrupt sources & saved to local variable.
1127 * Write register value back to clear pending interrupts.
1128 */
1129 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1130 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1131
1132 if (!reg)
1133 return IRQ_NONE;
1134
1135 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1136 return IRQ_HANDLED;
1137
1138 /*
1139 * Handle interrupts, walk through all bits
1140 * and run the tasks, the bits are checked in order of
1141 * priority.
1142 */
1143
1144 /*
1145 * 1 - Beacon timer expired interrupt.
1146 */
1147 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1148 rt2x00lib_beacondone(rt2x00dev);
1149
1150 /*
1151 * 2 - Rx ring done interrupt.
1152 */
1153 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1154 rt2x00pci_rxdone(rt2x00dev);
1155
1156 /*
1157 * 3 - Atim ring transmit done interrupt.
1158 */
1159 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1160 rt2400pci_txdone(rt2x00dev, RT2X00_BCN_QUEUE_ATIM);
1161
1162 /*
1163 * 4 - Priority ring transmit done interrupt.
1164 */
1165 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1166 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1167
1168 /*
1169 * 5 - Tx ring transmit done interrupt.
1170 */
1171 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1172 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1173
1174 return IRQ_HANDLED;
1175 }
1176
1177 /*
1178 * Device probe functions.
1179 */
1180 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1181 {
1182 struct eeprom_93cx6 eeprom;
1183 u32 reg;
1184 u16 word;
1185 u8 *mac;
1186
1187 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1188
1189 eeprom.data = rt2x00dev;
1190 eeprom.register_read = rt2400pci_eepromregister_read;
1191 eeprom.register_write = rt2400pci_eepromregister_write;
1192 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1193 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1194 eeprom.reg_data_in = 0;
1195 eeprom.reg_data_out = 0;
1196 eeprom.reg_data_clock = 0;
1197 eeprom.reg_chip_select = 0;
1198
1199 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1200 EEPROM_SIZE / sizeof(u16));
1201
1202 /*
1203 * Start validation of the data that has been read.
1204 */
1205 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1206 if (!is_valid_ether_addr(mac)) {
1207 DECLARE_MAC_BUF(macbuf);
1208
1209 random_ether_addr(mac);
1210 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1211 }
1212
1213 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1214 if (word == 0xffff) {
1215 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1216 return -EINVAL;
1217 }
1218
1219 return 0;
1220 }
1221
1222 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1223 {
1224 u32 reg;
1225 u16 value;
1226 u16 eeprom;
1227
1228 /*
1229 * Read EEPROM word for configuration.
1230 */
1231 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1232
1233 /*
1234 * Identify RF chipset.
1235 */
1236 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1237 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1238 rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1239
1240 if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1241 !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1242 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1243 return -ENODEV;
1244 }
1245
1246 /*
1247 * Identify default antenna configuration.
1248 */
1249 rt2x00dev->default_ant.tx =
1250 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1251 rt2x00dev->default_ant.rx =
1252 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1253
1254 /*
1255 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1256 * I am not 100% sure about this, but the legacy drivers do not
1257 * indicate antenna swapping in software is required when
1258 * diversity is enabled.
1259 */
1260 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1261 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1262 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1263 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1264
1265 /*
1266 * Store led mode, for correct led behaviour.
1267 */
1268 #ifdef CONFIG_RT2400PCI_LEDS
1269 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1270
1271 switch (value) {
1272 case LED_MODE_ASUS:
1273 case LED_MODE_ALPHA:
1274 case LED_MODE_DEFAULT:
1275 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1276 break;
1277 case LED_MODE_TXRX_ACTIVITY:
1278 rt2x00dev->led_flags =
1279 LED_SUPPORT_RADIO | LED_SUPPORT_ACTIVITY;
1280 break;
1281 case LED_MODE_SIGNAL_STRENGTH:
1282 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1283 break;
1284 }
1285 #endif /* CONFIG_RT2400PCI_LEDS */
1286
1287 /*
1288 * Detect if this device has an hardware controlled radio.
1289 */
1290 #ifdef CONFIG_RT2400PCI_RFKILL
1291 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1292 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1293 #endif /* CONFIG_RT2400PCI_RFKILL */
1294
1295 /*
1296 * Check if the BBP tuning should be enabled.
1297 */
1298 if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1299 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1300
1301 return 0;
1302 }
1303
1304 /*
1305 * RF value list for RF2420 & RF2421
1306 * Supports: 2.4 GHz
1307 */
1308 static const struct rf_channel rf_vals_bg[] = {
1309 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1310 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1311 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1312 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1313 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1314 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1315 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1316 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1317 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1318 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1319 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1320 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1321 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1322 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1323 };
1324
1325 static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1326 {
1327 struct hw_mode_spec *spec = &rt2x00dev->spec;
1328 u8 *txpower;
1329 unsigned int i;
1330
1331 /*
1332 * Initialize all hw fields.
1333 */
1334 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1335 rt2x00dev->hw->extra_tx_headroom = 0;
1336 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1337 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1338 rt2x00dev->hw->queues = 2;
1339
1340 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1341 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1342 rt2x00_eeprom_addr(rt2x00dev,
1343 EEPROM_MAC_ADDR_0));
1344
1345 /*
1346 * Convert tx_power array in eeprom.
1347 */
1348 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1349 for (i = 0; i < 14; i++)
1350 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1351
1352 /*
1353 * Initialize hw_mode information.
1354 */
1355 spec->supported_bands = SUPPORT_BAND_2GHZ;
1356 spec->supported_rates = SUPPORT_RATE_CCK;
1357 spec->tx_power_a = NULL;
1358 spec->tx_power_bg = txpower;
1359 spec->tx_power_default = DEFAULT_TXPOWER;
1360
1361 spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1362 spec->channels = rf_vals_bg;
1363 }
1364
1365 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1366 {
1367 int retval;
1368
1369 /*
1370 * Allocate eeprom data.
1371 */
1372 retval = rt2400pci_validate_eeprom(rt2x00dev);
1373 if (retval)
1374 return retval;
1375
1376 retval = rt2400pci_init_eeprom(rt2x00dev);
1377 if (retval)
1378 return retval;
1379
1380 /*
1381 * Initialize hw specifications.
1382 */
1383 rt2400pci_probe_hw_mode(rt2x00dev);
1384
1385 /*
1386 * This device requires the atim queue
1387 */
1388 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1389
1390 /*
1391 * Set the rssi offset.
1392 */
1393 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1394
1395 return 0;
1396 }
1397
1398 /*
1399 * IEEE80211 stack callback functions.
1400 */
1401 static void rt2400pci_configure_filter(struct ieee80211_hw *hw,
1402 unsigned int changed_flags,
1403 unsigned int *total_flags,
1404 int mc_count,
1405 struct dev_addr_list *mc_list)
1406 {
1407 struct rt2x00_dev *rt2x00dev = hw->priv;
1408 u32 reg;
1409
1410 /*
1411 * Mask off any flags we are going to ignore from
1412 * the total_flags field.
1413 */
1414 *total_flags &=
1415 FIF_ALLMULTI |
1416 FIF_FCSFAIL |
1417 FIF_PLCPFAIL |
1418 FIF_CONTROL |
1419 FIF_OTHER_BSS |
1420 FIF_PROMISC_IN_BSS;
1421
1422 /*
1423 * Apply some rules to the filters:
1424 * - Some filters imply different filters to be set.
1425 * - Some things we can't filter out at all.
1426 */
1427 *total_flags |= FIF_ALLMULTI;
1428 if (*total_flags & FIF_OTHER_BSS ||
1429 *total_flags & FIF_PROMISC_IN_BSS)
1430 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1431
1432 /*
1433 * Check if there is any work left for us.
1434 */
1435 if (rt2x00dev->packet_filter == *total_flags)
1436 return;
1437 rt2x00dev->packet_filter = *total_flags;
1438
1439 /*
1440 * Start configuration steps.
1441 * Note that the version error will always be dropped
1442 * since there is no filter for it at this time.
1443 */
1444 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1445 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1446 !(*total_flags & FIF_FCSFAIL));
1447 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1448 !(*total_flags & FIF_PLCPFAIL));
1449 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1450 !(*total_flags & FIF_CONTROL));
1451 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1452 !(*total_flags & FIF_PROMISC_IN_BSS));
1453 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1454 !(*total_flags & FIF_PROMISC_IN_BSS));
1455 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1456 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1457 }
1458
1459 static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1460 u32 short_retry, u32 long_retry)
1461 {
1462 struct rt2x00_dev *rt2x00dev = hw->priv;
1463 u32 reg;
1464
1465 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1466 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1467 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1468 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1469
1470 return 0;
1471 }
1472
1473 static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1474 int queue,
1475 const struct ieee80211_tx_queue_params *params)
1476 {
1477 struct rt2x00_dev *rt2x00dev = hw->priv;
1478
1479 /*
1480 * We don't support variating cw_min and cw_max variables
1481 * per queue. So by default we only configure the TX queue,
1482 * and ignore all other configurations.
1483 */
1484 if (queue != IEEE80211_TX_QUEUE_DATA0)
1485 return -EINVAL;
1486
1487 if (rt2x00mac_conf_tx(hw, queue, params))
1488 return -EINVAL;
1489
1490 /*
1491 * Write configuration to register.
1492 */
1493 rt2400pci_config_cw(rt2x00dev,
1494 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1495
1496 return 0;
1497 }
1498
1499 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1500 {
1501 struct rt2x00_dev *rt2x00dev = hw->priv;
1502 u64 tsf;
1503 u32 reg;
1504
1505 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1506 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1507 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1508 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1509
1510 return tsf;
1511 }
1512
1513 static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1514 struct ieee80211_tx_control *control)
1515 {
1516 struct rt2x00_dev *rt2x00dev = hw->priv;
1517 struct rt2x00_intf *intf = vif_to_intf(control->vif);
1518 struct queue_entry_priv_pci_tx *priv_tx;
1519 struct skb_frame_desc *skbdesc;
1520
1521 if (unlikely(!intf->beacon))
1522 return -ENOBUFS;
1523
1524 priv_tx = intf->beacon->priv_data;
1525
1526 /*
1527 * Fill in skb descriptor
1528 */
1529 skbdesc = get_skb_frame_desc(skb);
1530 memset(skbdesc, 0, sizeof(*skbdesc));
1531 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
1532 skbdesc->data = skb->data;
1533 skbdesc->data_len = skb->len;
1534 skbdesc->desc = priv_tx->desc;
1535 skbdesc->desc_len = intf->beacon->queue->desc_size;
1536 skbdesc->entry = intf->beacon;
1537
1538 /*
1539 * mac80211 doesn't provide the control->queue variable
1540 * for beacons. Set our own queue identification so
1541 * it can be used during descriptor initialization.
1542 */
1543 control->queue = RT2X00_BCN_QUEUE_BEACON;
1544 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
1545
1546 /*
1547 * Enable beacon generation.
1548 * Write entire beacon with descriptor to register,
1549 * and kick the beacon generator.
1550 */
1551 memcpy(priv_tx->data, skb->data, skb->len);
1552 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
1553
1554 return 0;
1555 }
1556
1557 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1558 {
1559 struct rt2x00_dev *rt2x00dev = hw->priv;
1560 u32 reg;
1561
1562 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1563 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1564 }
1565
1566 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1567 .tx = rt2x00mac_tx,
1568 .start = rt2x00mac_start,
1569 .stop = rt2x00mac_stop,
1570 .add_interface = rt2x00mac_add_interface,
1571 .remove_interface = rt2x00mac_remove_interface,
1572 .config = rt2x00mac_config,
1573 .config_interface = rt2x00mac_config_interface,
1574 .configure_filter = rt2400pci_configure_filter,
1575 .get_stats = rt2x00mac_get_stats,
1576 .set_retry_limit = rt2400pci_set_retry_limit,
1577 .bss_info_changed = rt2x00mac_bss_info_changed,
1578 .conf_tx = rt2400pci_conf_tx,
1579 .get_tx_stats = rt2x00mac_get_tx_stats,
1580 .get_tsf = rt2400pci_get_tsf,
1581 .beacon_update = rt2400pci_beacon_update,
1582 .tx_last_beacon = rt2400pci_tx_last_beacon,
1583 };
1584
1585 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1586 .irq_handler = rt2400pci_interrupt,
1587 .probe_hw = rt2400pci_probe_hw,
1588 .initialize = rt2x00pci_initialize,
1589 .uninitialize = rt2x00pci_uninitialize,
1590 .init_rxentry = rt2400pci_init_rxentry,
1591 .init_txentry = rt2400pci_init_txentry,
1592 .set_device_state = rt2400pci_set_device_state,
1593 .rfkill_poll = rt2400pci_rfkill_poll,
1594 .link_stats = rt2400pci_link_stats,
1595 .reset_tuner = rt2400pci_reset_tuner,
1596 .link_tuner = rt2400pci_link_tuner,
1597 .led_brightness = rt2400pci_led_brightness,
1598 .write_tx_desc = rt2400pci_write_tx_desc,
1599 .write_tx_data = rt2x00pci_write_tx_data,
1600 .kick_tx_queue = rt2400pci_kick_tx_queue,
1601 .fill_rxdone = rt2400pci_fill_rxdone,
1602 .config_intf = rt2400pci_config_intf,
1603 .config_preamble = rt2400pci_config_preamble,
1604 .config = rt2400pci_config,
1605 };
1606
1607 static const struct data_queue_desc rt2400pci_queue_rx = {
1608 .entry_num = RX_ENTRIES,
1609 .data_size = DATA_FRAME_SIZE,
1610 .desc_size = RXD_DESC_SIZE,
1611 .priv_size = sizeof(struct queue_entry_priv_pci_rx),
1612 };
1613
1614 static const struct data_queue_desc rt2400pci_queue_tx = {
1615 .entry_num = TX_ENTRIES,
1616 .data_size = DATA_FRAME_SIZE,
1617 .desc_size = TXD_DESC_SIZE,
1618 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1619 };
1620
1621 static const struct data_queue_desc rt2400pci_queue_bcn = {
1622 .entry_num = BEACON_ENTRIES,
1623 .data_size = MGMT_FRAME_SIZE,
1624 .desc_size = TXD_DESC_SIZE,
1625 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1626 };
1627
1628 static const struct data_queue_desc rt2400pci_queue_atim = {
1629 .entry_num = ATIM_ENTRIES,
1630 .data_size = DATA_FRAME_SIZE,
1631 .desc_size = TXD_DESC_SIZE,
1632 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1633 };
1634
1635 static const struct rt2x00_ops rt2400pci_ops = {
1636 .name = KBUILD_MODNAME,
1637 .max_sta_intf = 1,
1638 .max_ap_intf = 1,
1639 .eeprom_size = EEPROM_SIZE,
1640 .rf_size = RF_SIZE,
1641 .rx = &rt2400pci_queue_rx,
1642 .tx = &rt2400pci_queue_tx,
1643 .bcn = &rt2400pci_queue_bcn,
1644 .atim = &rt2400pci_queue_atim,
1645 .lib = &rt2400pci_rt2x00_ops,
1646 .hw = &rt2400pci_mac80211_ops,
1647 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1648 .debugfs = &rt2400pci_rt2x00debug,
1649 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1650 };
1651
1652 /*
1653 * RT2400pci module information.
1654 */
1655 static struct pci_device_id rt2400pci_device_table[] = {
1656 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1657 { 0, }
1658 };
1659
1660 MODULE_AUTHOR(DRV_PROJECT);
1661 MODULE_VERSION(DRV_VERSION);
1662 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1663 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1664 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1665 MODULE_LICENSE("GPL");
1666
1667 static struct pci_driver rt2400pci_driver = {
1668 .name = KBUILD_MODNAME,
1669 .id_table = rt2400pci_device_table,
1670 .probe = rt2x00pci_probe,
1671 .remove = __devexit_p(rt2x00pci_remove),
1672 .suspend = rt2x00pci_suspend,
1673 .resume = rt2x00pci_resume,
1674 };
1675
1676 static int __init rt2400pci_init(void)
1677 {
1678 return pci_register_driver(&rt2400pci_driver);
1679 }
1680
1681 static void __exit rt2400pci_exit(void)
1682 {
1683 pci_unregister_driver(&rt2400pci_driver);
1684 }
1685
1686 module_init(rt2400pci_init);
1687 module_exit(rt2400pci_exit);
Linux kernel - Deliverables
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