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rt2x00: Refactor beacon code to make use of start- and stop_queue
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
1 /*
2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt2400pci
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
25 */
26
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
34 #include <linux/slab.h>
35
36 #include "rt2x00.h"
37 #include "rt2x00pci.h"
38 #include "rt2400pci.h"
39
40 /*
41 * Register access.
42 * All access to the CSR registers will go through the methods
43 * rt2x00pci_register_read and rt2x00pci_register_write.
44 * BBP and RF register require indirect register access,
45 * and use the CSR registers BBPCSR and RFCSR to achieve this.
46 * These indirect registers work with busy bits,
47 * and we will try maximal REGISTER_BUSY_COUNT times to access
48 * the register while taking a REGISTER_BUSY_DELAY us delay
49 * between each attampt. When the busy bit is still set at that time,
50 * the access attempt is considered to have failed,
51 * and we will print an error.
52 */
53 #define WAIT_FOR_BBP(__dev, __reg) \
54 rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
55 #define WAIT_FOR_RF(__dev, __reg) \
56 rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
57
58 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
59 const unsigned int word, const u8 value)
60 {
61 u32 reg;
62
63 mutex_lock(&rt2x00dev->csr_mutex);
64
65 /*
66 * Wait until the BBP becomes available, afterwards we
67 * can safely write the new data into the register.
68 */
69 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
70 reg = 0;
71 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
72 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
73 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
74 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
75
76 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
77 }
78
79 mutex_unlock(&rt2x00dev->csr_mutex);
80 }
81
82 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
83 const unsigned int word, u8 *value)
84 {
85 u32 reg;
86
87 mutex_lock(&rt2x00dev->csr_mutex);
88
89 /*
90 * Wait until the BBP becomes available, afterwards we
91 * can safely write the read request into the register.
92 * After the data has been written, we wait until hardware
93 * returns the correct value, if at any time the register
94 * doesn't become available in time, reg will be 0xffffffff
95 * which means we return 0xff to the caller.
96 */
97 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
98 reg = 0;
99 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
100 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
101 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
102
103 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
104
105 WAIT_FOR_BBP(rt2x00dev, &reg);
106 }
107
108 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
109
110 mutex_unlock(&rt2x00dev->csr_mutex);
111 }
112
113 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
114 const unsigned int word, const u32 value)
115 {
116 u32 reg;
117
118 mutex_lock(&rt2x00dev->csr_mutex);
119
120 /*
121 * Wait until the RF becomes available, afterwards we
122 * can safely write the new data into the register.
123 */
124 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
125 reg = 0;
126 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
127 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
128 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
129 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
130
131 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
132 rt2x00_rf_write(rt2x00dev, word, value);
133 }
134
135 mutex_unlock(&rt2x00dev->csr_mutex);
136 }
137
138 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
139 {
140 struct rt2x00_dev *rt2x00dev = eeprom->data;
141 u32 reg;
142
143 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
144
145 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
146 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
147 eeprom->reg_data_clock =
148 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
149 eeprom->reg_chip_select =
150 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
151 }
152
153 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
154 {
155 struct rt2x00_dev *rt2x00dev = eeprom->data;
156 u32 reg = 0;
157
158 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
159 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
160 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
161 !!eeprom->reg_data_clock);
162 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
163 !!eeprom->reg_chip_select);
164
165 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
166 }
167
168 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
169 static const struct rt2x00debug rt2400pci_rt2x00debug = {
170 .owner = THIS_MODULE,
171 .csr = {
172 .read = rt2x00pci_register_read,
173 .write = rt2x00pci_register_write,
174 .flags = RT2X00DEBUGFS_OFFSET,
175 .word_base = CSR_REG_BASE,
176 .word_size = sizeof(u32),
177 .word_count = CSR_REG_SIZE / sizeof(u32),
178 },
179 .eeprom = {
180 .read = rt2x00_eeprom_read,
181 .write = rt2x00_eeprom_write,
182 .word_base = EEPROM_BASE,
183 .word_size = sizeof(u16),
184 .word_count = EEPROM_SIZE / sizeof(u16),
185 },
186 .bbp = {
187 .read = rt2400pci_bbp_read,
188 .write = rt2400pci_bbp_write,
189 .word_base = BBP_BASE,
190 .word_size = sizeof(u8),
191 .word_count = BBP_SIZE / sizeof(u8),
192 },
193 .rf = {
194 .read = rt2x00_rf_read,
195 .write = rt2400pci_rf_write,
196 .word_base = RF_BASE,
197 .word_size = sizeof(u32),
198 .word_count = RF_SIZE / sizeof(u32),
199 },
200 };
201 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
202
203 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
204 {
205 u32 reg;
206
207 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
208 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
209 }
210
211 #ifdef CONFIG_RT2X00_LIB_LEDS
212 static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
213 enum led_brightness brightness)
214 {
215 struct rt2x00_led *led =
216 container_of(led_cdev, struct rt2x00_led, led_dev);
217 unsigned int enabled = brightness != LED_OFF;
218 u32 reg;
219
220 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
221
222 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
223 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
224 else if (led->type == LED_TYPE_ACTIVITY)
225 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
226
227 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
228 }
229
230 static int rt2400pci_blink_set(struct led_classdev *led_cdev,
231 unsigned long *delay_on,
232 unsigned long *delay_off)
233 {
234 struct rt2x00_led *led =
235 container_of(led_cdev, struct rt2x00_led, led_dev);
236 u32 reg;
237
238 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
239 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
240 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
241 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
242
243 return 0;
244 }
245
246 static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
247 struct rt2x00_led *led,
248 enum led_type type)
249 {
250 led->rt2x00dev = rt2x00dev;
251 led->type = type;
252 led->led_dev.brightness_set = rt2400pci_brightness_set;
253 led->led_dev.blink_set = rt2400pci_blink_set;
254 led->flags = LED_INITIALIZED;
255 }
256 #endif /* CONFIG_RT2X00_LIB_LEDS */
257
258 /*
259 * Configuration handlers.
260 */
261 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
262 const unsigned int filter_flags)
263 {
264 u32 reg;
265
266 /*
267 * Start configuration steps.
268 * Note that the version error will always be dropped
269 * since there is no filter for it at this time.
270 */
271 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
272 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
273 !(filter_flags & FIF_FCSFAIL));
274 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
275 !(filter_flags & FIF_PLCPFAIL));
276 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
277 !(filter_flags & FIF_CONTROL));
278 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
279 !(filter_flags & FIF_PROMISC_IN_BSS));
280 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
281 !(filter_flags & FIF_PROMISC_IN_BSS) &&
282 !rt2x00dev->intf_ap_count);
283 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
284 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
285 }
286
287 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
288 struct rt2x00_intf *intf,
289 struct rt2x00intf_conf *conf,
290 const unsigned int flags)
291 {
292 unsigned int bcn_preload;
293 u32 reg;
294
295 if (flags & CONFIG_UPDATE_TYPE) {
296 /*
297 * Enable beacon config
298 */
299 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
300 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
301 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
302 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
303
304 /*
305 * Enable synchronisation.
306 */
307 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
308 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
309 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
310 }
311
312 if (flags & CONFIG_UPDATE_MAC)
313 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
314 conf->mac, sizeof(conf->mac));
315
316 if (flags & CONFIG_UPDATE_BSSID)
317 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
318 conf->bssid, sizeof(conf->bssid));
319 }
320
321 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
322 struct rt2x00lib_erp *erp,
323 u32 changed)
324 {
325 int preamble_mask;
326 u32 reg;
327
328 /*
329 * When short preamble is enabled, we should set bit 0x08
330 */
331 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
332 preamble_mask = erp->short_preamble << 3;
333
334 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
335 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x1ff);
336 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0x13a);
337 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
338 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
339 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
340
341 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
342 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
343 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
344 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
345 GET_DURATION(ACK_SIZE, 10));
346 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
347
348 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
349 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
350 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
351 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
352 GET_DURATION(ACK_SIZE, 20));
353 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
354
355 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
356 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
357 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
358 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
359 GET_DURATION(ACK_SIZE, 55));
360 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
361
362 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
363 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
364 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
365 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
366 GET_DURATION(ACK_SIZE, 110));
367 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
368 }
369
370 if (changed & BSS_CHANGED_BASIC_RATES)
371 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
372
373 if (changed & BSS_CHANGED_ERP_SLOT) {
374 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
375 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
376 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
377
378 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
379 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
380 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
381 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
382
383 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
384 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
385 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
386 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
387 }
388
389 if (changed & BSS_CHANGED_BEACON_INT) {
390 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
391 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
392 erp->beacon_int * 16);
393 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
394 erp->beacon_int * 16);
395 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
396 }
397 }
398
399 static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
400 struct antenna_setup *ant)
401 {
402 u8 r1;
403 u8 r4;
404
405 /*
406 * We should never come here because rt2x00lib is supposed
407 * to catch this and send us the correct antenna explicitely.
408 */
409 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
410 ant->tx == ANTENNA_SW_DIVERSITY);
411
412 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
413 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
414
415 /*
416 * Configure the TX antenna.
417 */
418 switch (ant->tx) {
419 case ANTENNA_HW_DIVERSITY:
420 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
421 break;
422 case ANTENNA_A:
423 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
424 break;
425 case ANTENNA_B:
426 default:
427 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
428 break;
429 }
430
431 /*
432 * Configure the RX antenna.
433 */
434 switch (ant->rx) {
435 case ANTENNA_HW_DIVERSITY:
436 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
437 break;
438 case ANTENNA_A:
439 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
440 break;
441 case ANTENNA_B:
442 default:
443 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
444 break;
445 }
446
447 rt2400pci_bbp_write(rt2x00dev, 4, r4);
448 rt2400pci_bbp_write(rt2x00dev, 1, r1);
449 }
450
451 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
452 struct rf_channel *rf)
453 {
454 /*
455 * Switch on tuning bits.
456 */
457 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
458 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
459
460 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
461 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
462 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
463
464 /*
465 * RF2420 chipset don't need any additional actions.
466 */
467 if (rt2x00_rf(rt2x00dev, RF2420))
468 return;
469
470 /*
471 * For the RT2421 chipsets we need to write an invalid
472 * reference clock rate to activate auto_tune.
473 * After that we set the value back to the correct channel.
474 */
475 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
476 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
477 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
478
479 msleep(1);
480
481 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
482 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
483 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
484
485 msleep(1);
486
487 /*
488 * Switch off tuning bits.
489 */
490 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
491 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
492
493 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
494 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
495
496 /*
497 * Clear false CRC during channel switch.
498 */
499 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
500 }
501
502 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
503 {
504 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
505 }
506
507 static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
508 struct rt2x00lib_conf *libconf)
509 {
510 u32 reg;
511
512 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
513 rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
514 libconf->conf->long_frame_max_tx_count);
515 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
516 libconf->conf->short_frame_max_tx_count);
517 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
518 }
519
520 static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
521 struct rt2x00lib_conf *libconf)
522 {
523 enum dev_state state =
524 (libconf->conf->flags & IEEE80211_CONF_PS) ?
525 STATE_SLEEP : STATE_AWAKE;
526 u32 reg;
527
528 if (state == STATE_SLEEP) {
529 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
530 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
531 (rt2x00dev->beacon_int - 20) * 16);
532 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
533 libconf->conf->listen_interval - 1);
534
535 /* We must first disable autowake before it can be enabled */
536 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
537 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
538
539 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
540 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
541 } else {
542 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
543 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
544 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
545 }
546
547 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
548 }
549
550 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
551 struct rt2x00lib_conf *libconf,
552 const unsigned int flags)
553 {
554 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
555 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
556 if (flags & IEEE80211_CONF_CHANGE_POWER)
557 rt2400pci_config_txpower(rt2x00dev,
558 libconf->conf->power_level);
559 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
560 rt2400pci_config_retry_limit(rt2x00dev, libconf);
561 if (flags & IEEE80211_CONF_CHANGE_PS)
562 rt2400pci_config_ps(rt2x00dev, libconf);
563 }
564
565 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
566 const int cw_min, const int cw_max)
567 {
568 u32 reg;
569
570 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
571 rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
572 rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
573 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
574 }
575
576 /*
577 * Link tuning
578 */
579 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
580 struct link_qual *qual)
581 {
582 u32 reg;
583 u8 bbp;
584
585 /*
586 * Update FCS error count from register.
587 */
588 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
589 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
590
591 /*
592 * Update False CCA count from register.
593 */
594 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
595 qual->false_cca = bbp;
596 }
597
598 static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
599 struct link_qual *qual, u8 vgc_level)
600 {
601 if (qual->vgc_level_reg != vgc_level) {
602 rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
603 qual->vgc_level = vgc_level;
604 qual->vgc_level_reg = vgc_level;
605 }
606 }
607
608 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
609 struct link_qual *qual)
610 {
611 rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
612 }
613
614 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
615 struct link_qual *qual, const u32 count)
616 {
617 /*
618 * The link tuner should not run longer then 60 seconds,
619 * and should run once every 2 seconds.
620 */
621 if (count > 60 || !(count & 1))
622 return;
623
624 /*
625 * Base r13 link tuning on the false cca count.
626 */
627 if ((qual->false_cca > 512) && (qual->vgc_level < 0x20))
628 rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
629 else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08))
630 rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
631 }
632
633 /*
634 * Queue handlers.
635 */
636 static void rt2400pci_start_queue(struct data_queue *queue)
637 {
638 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
639 u32 reg;
640
641 switch (queue->qid) {
642 case QID_RX:
643 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
644 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
645 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
646 break;
647 case QID_BEACON:
648 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
649 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
650 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
651 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
652 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
653 break;
654 default:
655 break;
656 }
657 }
658
659 static void rt2400pci_kick_queue(struct data_queue *queue)
660 {
661 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
662 u32 reg;
663
664 switch (queue->qid) {
665 case QID_AC_VO:
666 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
667 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
668 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
669 break;
670 case QID_AC_VI:
671 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
672 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
673 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
674 break;
675 case QID_ATIM:
676 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
677 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
678 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
679 break;
680 default:
681 break;
682 }
683 }
684
685 static void rt2400pci_stop_queue(struct data_queue *queue)
686 {
687 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
688 u32 reg;
689
690 switch (queue->qid) {
691 case QID_AC_VO:
692 case QID_AC_VI:
693 case QID_ATIM:
694 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
695 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
696 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
697 break;
698 case QID_RX:
699 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
700 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
701 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
702 break;
703 case QID_BEACON:
704 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
705 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
706 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
707 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
708 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
709 break;
710 default:
711 break;
712 }
713 }
714
715 /*
716 * Initialization functions.
717 */
718 static bool rt2400pci_get_entry_state(struct queue_entry *entry)
719 {
720 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
721 u32 word;
722
723 if (entry->queue->qid == QID_RX) {
724 rt2x00_desc_read(entry_priv->desc, 0, &word);
725
726 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
727 } else {
728 rt2x00_desc_read(entry_priv->desc, 0, &word);
729
730 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
731 rt2x00_get_field32(word, TXD_W0_VALID));
732 }
733 }
734
735 static void rt2400pci_clear_entry(struct queue_entry *entry)
736 {
737 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
738 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
739 u32 word;
740
741 if (entry->queue->qid == QID_RX) {
742 rt2x00_desc_read(entry_priv->desc, 2, &word);
743 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
744 rt2x00_desc_write(entry_priv->desc, 2, word);
745
746 rt2x00_desc_read(entry_priv->desc, 1, &word);
747 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
748 rt2x00_desc_write(entry_priv->desc, 1, word);
749
750 rt2x00_desc_read(entry_priv->desc, 0, &word);
751 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
752 rt2x00_desc_write(entry_priv->desc, 0, word);
753 } else {
754 rt2x00_desc_read(entry_priv->desc, 0, &word);
755 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
756 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
757 rt2x00_desc_write(entry_priv->desc, 0, word);
758 }
759 }
760
761 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
762 {
763 struct queue_entry_priv_pci *entry_priv;
764 u32 reg;
765
766 /*
767 * Initialize registers.
768 */
769 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
770 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
771 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
772 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
773 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
774 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
775
776 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
777 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
778 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
779 entry_priv->desc_dma);
780 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
781
782 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
783 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
784 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
785 entry_priv->desc_dma);
786 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
787
788 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
789 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
790 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
791 entry_priv->desc_dma);
792 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
793
794 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
795 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
796 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
797 entry_priv->desc_dma);
798 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
799
800 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
801 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
802 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
803 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
804
805 entry_priv = rt2x00dev->rx->entries[0].priv_data;
806 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
807 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
808 entry_priv->desc_dma);
809 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
810
811 return 0;
812 }
813
814 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
815 {
816 u32 reg;
817
818 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
819 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
820 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
821 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
822
823 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
824 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
825 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
826 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
827 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
828
829 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
830 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
831 (rt2x00dev->rx->data_size / 128));
832 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
833
834 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
835 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
836 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
837 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
838 rt2x00_set_field32(&reg, CSR14_TCFP, 0);
839 rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
840 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
841 rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
842 rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
843 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
844
845 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
846
847 rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
848 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
849 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
850 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
851 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
852 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
853
854 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
855 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
856 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
857 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
858 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
859 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
860 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
861 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
862
863 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
864
865 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
866 return -EBUSY;
867
868 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
869 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
870
871 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
872 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
873 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
874
875 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
876 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
877 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
878 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
879 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
880 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
881
882 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
883 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
884 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
885 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
886 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
887
888 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
889 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
890 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
891 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
892
893 /*
894 * We must clear the FCS and FIFO error count.
895 * These registers are cleared on read,
896 * so we may pass a useless variable to store the value.
897 */
898 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
899 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
900
901 return 0;
902 }
903
904 static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
905 {
906 unsigned int i;
907 u8 value;
908
909 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
910 rt2400pci_bbp_read(rt2x00dev, 0, &value);
911 if ((value != 0xff) && (value != 0x00))
912 return 0;
913 udelay(REGISTER_BUSY_DELAY);
914 }
915
916 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
917 return -EACCES;
918 }
919
920 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
921 {
922 unsigned int i;
923 u16 eeprom;
924 u8 reg_id;
925 u8 value;
926
927 if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
928 return -EACCES;
929
930 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
931 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
932 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
933 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
934 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
935 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
936 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
937 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
938 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
939 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
940 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
941 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
942 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
943 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
944
945 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
946 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
947
948 if (eeprom != 0xffff && eeprom != 0x0000) {
949 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
950 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
951 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
952 }
953 }
954
955 return 0;
956 }
957
958 /*
959 * Device state switch handlers.
960 */
961 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
962 enum dev_state state)
963 {
964 int mask = (state == STATE_RADIO_IRQ_OFF) ||
965 (state == STATE_RADIO_IRQ_OFF_ISR);
966 u32 reg;
967
968 /*
969 * When interrupts are being enabled, the interrupt registers
970 * should clear the register to assure a clean state.
971 */
972 if (state == STATE_RADIO_IRQ_ON) {
973 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
974 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
975 }
976
977 /*
978 * Only toggle the interrupts bits we are going to use.
979 * Non-checked interrupt bits are disabled by default.
980 */
981 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
982 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
983 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
984 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
985 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
986 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
987 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
988 }
989
990 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
991 {
992 /*
993 * Initialize all registers.
994 */
995 if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
996 rt2400pci_init_registers(rt2x00dev) ||
997 rt2400pci_init_bbp(rt2x00dev)))
998 return -EIO;
999
1000 return 0;
1001 }
1002
1003 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1004 {
1005 /*
1006 * Disable power
1007 */
1008 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1009 }
1010
1011 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
1012 enum dev_state state)
1013 {
1014 u32 reg, reg2;
1015 unsigned int i;
1016 char put_to_sleep;
1017 char bbp_state;
1018 char rf_state;
1019
1020 put_to_sleep = (state != STATE_AWAKE);
1021
1022 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1023 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1024 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1025 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1026 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1027 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1028
1029 /*
1030 * Device is not guaranteed to be in the requested state yet.
1031 * We must wait until the register indicates that the
1032 * device has entered the correct state.
1033 */
1034 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1035 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg2);
1036 bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
1037 rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
1038 if (bbp_state == state && rf_state == state)
1039 return 0;
1040 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1041 msleep(10);
1042 }
1043
1044 return -EBUSY;
1045 }
1046
1047 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1048 enum dev_state state)
1049 {
1050 int retval = 0;
1051
1052 switch (state) {
1053 case STATE_RADIO_ON:
1054 retval = rt2400pci_enable_radio(rt2x00dev);
1055 break;
1056 case STATE_RADIO_OFF:
1057 rt2400pci_disable_radio(rt2x00dev);
1058 break;
1059 case STATE_RADIO_IRQ_ON:
1060 case STATE_RADIO_IRQ_ON_ISR:
1061 case STATE_RADIO_IRQ_OFF:
1062 case STATE_RADIO_IRQ_OFF_ISR:
1063 rt2400pci_toggle_irq(rt2x00dev, state);
1064 break;
1065 case STATE_DEEP_SLEEP:
1066 case STATE_SLEEP:
1067 case STATE_STANDBY:
1068 case STATE_AWAKE:
1069 retval = rt2400pci_set_state(rt2x00dev, state);
1070 break;
1071 default:
1072 retval = -ENOTSUPP;
1073 break;
1074 }
1075
1076 if (unlikely(retval))
1077 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1078 state, retval);
1079
1080 return retval;
1081 }
1082
1083 /*
1084 * TX descriptor initialization
1085 */
1086 static void rt2400pci_write_tx_desc(struct queue_entry *entry,
1087 struct txentry_desc *txdesc)
1088 {
1089 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1090 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1091 __le32 *txd = entry_priv->desc;
1092 u32 word;
1093
1094 /*
1095 * Start writing the descriptor words.
1096 */
1097 rt2x00_desc_read(txd, 1, &word);
1098 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1099 rt2x00_desc_write(txd, 1, word);
1100
1101 rt2x00_desc_read(txd, 2, &word);
1102 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length);
1103 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length);
1104 rt2x00_desc_write(txd, 2, word);
1105
1106 rt2x00_desc_read(txd, 3, &word);
1107 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1108 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1109 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1110 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1111 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1112 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1113 rt2x00_desc_write(txd, 3, word);
1114
1115 rt2x00_desc_read(txd, 4, &word);
1116 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
1117 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1118 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1119 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
1120 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1121 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1122 rt2x00_desc_write(txd, 4, word);
1123
1124 /*
1125 * Writing TXD word 0 must the last to prevent a race condition with
1126 * the device, whereby the device may take hold of the TXD before we
1127 * finished updating it.
1128 */
1129 rt2x00_desc_read(txd, 0, &word);
1130 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1131 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1132 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1133 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1134 rt2x00_set_field32(&word, TXD_W0_ACK,
1135 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1136 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1137 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1138 rt2x00_set_field32(&word, TXD_W0_RTS,
1139 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1140 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1141 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1142 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1143 rt2x00_desc_write(txd, 0, word);
1144
1145 /*
1146 * Register descriptor details in skb frame descriptor.
1147 */
1148 skbdesc->desc = txd;
1149 skbdesc->desc_len = TXD_DESC_SIZE;
1150 }
1151
1152 /*
1153 * TX data initialization
1154 */
1155 static void rt2400pci_write_beacon(struct queue_entry *entry,
1156 struct txentry_desc *txdesc)
1157 {
1158 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1159 u32 reg;
1160
1161 /*
1162 * Disable beaconing while we are reloading the beacon data,
1163 * otherwise we might be sending out invalid data.
1164 */
1165 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1166 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1167 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1168
1169 rt2x00queue_map_txskb(entry);
1170
1171 /*
1172 * Write the TX descriptor for the beacon.
1173 */
1174 rt2400pci_write_tx_desc(entry, txdesc);
1175
1176 /*
1177 * Dump beacon to userspace through debugfs.
1178 */
1179 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1180
1181 /*
1182 * Enable beaconing again.
1183 */
1184 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1185 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1186 }
1187
1188 /*
1189 * RX control handlers
1190 */
1191 static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1192 struct rxdone_entry_desc *rxdesc)
1193 {
1194 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1195 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1196 u32 word0;
1197 u32 word2;
1198 u32 word3;
1199 u32 word4;
1200 u64 tsf;
1201 u32 rx_low;
1202 u32 rx_high;
1203
1204 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1205 rt2x00_desc_read(entry_priv->desc, 2, &word2);
1206 rt2x00_desc_read(entry_priv->desc, 3, &word3);
1207 rt2x00_desc_read(entry_priv->desc, 4, &word4);
1208
1209 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1210 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1211 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1212 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1213
1214 /*
1215 * We only get the lower 32bits from the timestamp,
1216 * to get the full 64bits we must complement it with
1217 * the timestamp from get_tsf().
1218 * Note that when a wraparound of the lower 32bits
1219 * has occurred between the frame arrival and the get_tsf()
1220 * call, we must decrease the higher 32bits with 1 to get
1221 * to correct value.
1222 */
1223 tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw);
1224 rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1225 rx_high = upper_32_bits(tsf);
1226
1227 if ((u32)tsf <= rx_low)
1228 rx_high--;
1229
1230 /*
1231 * Obtain the status about this packet.
1232 * The signal is the PLCP value, and needs to be stripped
1233 * of the preamble bit (0x08).
1234 */
1235 rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
1236 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1237 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
1238 entry->queue->rt2x00dev->rssi_offset;
1239 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1240
1241 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1242 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1243 rxdesc->dev_flags |= RXDONE_MY_BSS;
1244 }
1245
1246 /*
1247 * Interrupt functions.
1248 */
1249 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1250 const enum data_queue_qid queue_idx)
1251 {
1252 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1253 struct queue_entry_priv_pci *entry_priv;
1254 struct queue_entry *entry;
1255 struct txdone_entry_desc txdesc;
1256 u32 word;
1257
1258 while (!rt2x00queue_empty(queue)) {
1259 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1260 entry_priv = entry->priv_data;
1261 rt2x00_desc_read(entry_priv->desc, 0, &word);
1262
1263 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1264 !rt2x00_get_field32(word, TXD_W0_VALID))
1265 break;
1266
1267 /*
1268 * Obtain the status about this packet.
1269 */
1270 txdesc.flags = 0;
1271 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1272 case 0: /* Success */
1273 case 1: /* Success with retry */
1274 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1275 break;
1276 case 2: /* Failure, excessive retries */
1277 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1278 /* Don't break, this is a failed frame! */
1279 default: /* Failure */
1280 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1281 }
1282 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1283
1284 rt2x00lib_txdone(entry, &txdesc);
1285 }
1286 }
1287
1288 static irqreturn_t rt2400pci_interrupt_thread(int irq, void *dev_instance)
1289 {
1290 struct rt2x00_dev *rt2x00dev = dev_instance;
1291 u32 reg = rt2x00dev->irqvalue[0];
1292
1293 /*
1294 * Handle interrupts, walk through all bits
1295 * and run the tasks, the bits are checked in order of
1296 * priority.
1297 */
1298
1299 /*
1300 * 1 - Beacon timer expired interrupt.
1301 */
1302 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1303 rt2x00lib_beacondone(rt2x00dev);
1304
1305 /*
1306 * 2 - Rx ring done interrupt.
1307 */
1308 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1309 rt2x00pci_rxdone(rt2x00dev);
1310
1311 /*
1312 * 3 - Atim ring transmit done interrupt.
1313 */
1314 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1315 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1316
1317 /*
1318 * 4 - Priority ring transmit done interrupt.
1319 */
1320 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1321 rt2400pci_txdone(rt2x00dev, QID_AC_VO);
1322
1323 /*
1324 * 5 - Tx ring transmit done interrupt.
1325 */
1326 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1327 rt2400pci_txdone(rt2x00dev, QID_AC_VI);
1328
1329 /* Enable interrupts again. */
1330 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
1331 STATE_RADIO_IRQ_ON_ISR);
1332 return IRQ_HANDLED;
1333 }
1334
1335 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1336 {
1337 struct rt2x00_dev *rt2x00dev = dev_instance;
1338 u32 reg;
1339
1340 /*
1341 * Get the interrupt sources & saved to local variable.
1342 * Write register value back to clear pending interrupts.
1343 */
1344 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1345 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1346
1347 if (!reg)
1348 return IRQ_NONE;
1349
1350 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1351 return IRQ_HANDLED;
1352
1353 /* Store irqvalues for use in the interrupt thread. */
1354 rt2x00dev->irqvalue[0] = reg;
1355
1356 /* Disable interrupts, will be enabled again in the interrupt thread. */
1357 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
1358 STATE_RADIO_IRQ_OFF_ISR);
1359
1360 return IRQ_WAKE_THREAD;
1361 }
1362
1363 /*
1364 * Device probe functions.
1365 */
1366 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1367 {
1368 struct eeprom_93cx6 eeprom;
1369 u32 reg;
1370 u16 word;
1371 u8 *mac;
1372
1373 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1374
1375 eeprom.data = rt2x00dev;
1376 eeprom.register_read = rt2400pci_eepromregister_read;
1377 eeprom.register_write = rt2400pci_eepromregister_write;
1378 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1379 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1380 eeprom.reg_data_in = 0;
1381 eeprom.reg_data_out = 0;
1382 eeprom.reg_data_clock = 0;
1383 eeprom.reg_chip_select = 0;
1384
1385 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1386 EEPROM_SIZE / sizeof(u16));
1387
1388 /*
1389 * Start validation of the data that has been read.
1390 */
1391 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1392 if (!is_valid_ether_addr(mac)) {
1393 random_ether_addr(mac);
1394 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1395 }
1396
1397 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1398 if (word == 0xffff) {
1399 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1400 return -EINVAL;
1401 }
1402
1403 return 0;
1404 }
1405
1406 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1407 {
1408 u32 reg;
1409 u16 value;
1410 u16 eeprom;
1411
1412 /*
1413 * Read EEPROM word for configuration.
1414 */
1415 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1416
1417 /*
1418 * Identify RF chipset.
1419 */
1420 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1421 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1422 rt2x00_set_chip(rt2x00dev, RT2460, value,
1423 rt2x00_get_field32(reg, CSR0_REVISION));
1424
1425 if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
1426 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1427 return -ENODEV;
1428 }
1429
1430 /*
1431 * Identify default antenna configuration.
1432 */
1433 rt2x00dev->default_ant.tx =
1434 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1435 rt2x00dev->default_ant.rx =
1436 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1437
1438 /*
1439 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1440 * I am not 100% sure about this, but the legacy drivers do not
1441 * indicate antenna swapping in software is required when
1442 * diversity is enabled.
1443 */
1444 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1445 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1446 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1447 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1448
1449 /*
1450 * Store led mode, for correct led behaviour.
1451 */
1452 #ifdef CONFIG_RT2X00_LIB_LEDS
1453 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1454
1455 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1456 if (value == LED_MODE_TXRX_ACTIVITY ||
1457 value == LED_MODE_DEFAULT ||
1458 value == LED_MODE_ASUS)
1459 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1460 LED_TYPE_ACTIVITY);
1461 #endif /* CONFIG_RT2X00_LIB_LEDS */
1462
1463 /*
1464 * Detect if this device has an hardware controlled radio.
1465 */
1466 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1467 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1468
1469 /*
1470 * Check if the BBP tuning should be enabled.
1471 */
1472 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1473 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
1474
1475 return 0;
1476 }
1477
1478 /*
1479 * RF value list for RF2420 & RF2421
1480 * Supports: 2.4 GHz
1481 */
1482 static const struct rf_channel rf_vals_b[] = {
1483 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1484 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1485 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1486 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1487 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1488 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1489 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1490 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1491 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1492 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1493 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1494 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1495 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1496 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1497 };
1498
1499 static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1500 {
1501 struct hw_mode_spec *spec = &rt2x00dev->spec;
1502 struct channel_info *info;
1503 char *tx_power;
1504 unsigned int i;
1505
1506 /*
1507 * Initialize all hw fields.
1508 */
1509 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1510 IEEE80211_HW_SIGNAL_DBM |
1511 IEEE80211_HW_SUPPORTS_PS |
1512 IEEE80211_HW_PS_NULLFUNC_STACK;
1513
1514 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1515 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1516 rt2x00_eeprom_addr(rt2x00dev,
1517 EEPROM_MAC_ADDR_0));
1518
1519 /*
1520 * Initialize hw_mode information.
1521 */
1522 spec->supported_bands = SUPPORT_BAND_2GHZ;
1523 spec->supported_rates = SUPPORT_RATE_CCK;
1524
1525 spec->num_channels = ARRAY_SIZE(rf_vals_b);
1526 spec->channels = rf_vals_b;
1527
1528 /*
1529 * Create channel information array
1530 */
1531 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
1532 if (!info)
1533 return -ENOMEM;
1534
1535 spec->channels_info = info;
1536
1537 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1538 for (i = 0; i < 14; i++) {
1539 info[i].max_power = TXPOWER_FROM_DEV(MAX_TXPOWER);
1540 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1541 }
1542
1543 return 0;
1544 }
1545
1546 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1547 {
1548 int retval;
1549
1550 /*
1551 * Allocate eeprom data.
1552 */
1553 retval = rt2400pci_validate_eeprom(rt2x00dev);
1554 if (retval)
1555 return retval;
1556
1557 retval = rt2400pci_init_eeprom(rt2x00dev);
1558 if (retval)
1559 return retval;
1560
1561 /*
1562 * Initialize hw specifications.
1563 */
1564 retval = rt2400pci_probe_hw_mode(rt2x00dev);
1565 if (retval)
1566 return retval;
1567
1568 /*
1569 * This device requires the atim queue and DMA-mapped skbs.
1570 */
1571 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1572 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1573
1574 /*
1575 * Set the rssi offset.
1576 */
1577 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1578
1579 return 0;
1580 }
1581
1582 /*
1583 * IEEE80211 stack callback functions.
1584 */
1585 static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
1586 const struct ieee80211_tx_queue_params *params)
1587 {
1588 struct rt2x00_dev *rt2x00dev = hw->priv;
1589
1590 /*
1591 * We don't support variating cw_min and cw_max variables
1592 * per queue. So by default we only configure the TX queue,
1593 * and ignore all other configurations.
1594 */
1595 if (queue != 0)
1596 return -EINVAL;
1597
1598 if (rt2x00mac_conf_tx(hw, queue, params))
1599 return -EINVAL;
1600
1601 /*
1602 * Write configuration to register.
1603 */
1604 rt2400pci_config_cw(rt2x00dev,
1605 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1606
1607 return 0;
1608 }
1609
1610 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1611 {
1612 struct rt2x00_dev *rt2x00dev = hw->priv;
1613 u64 tsf;
1614 u32 reg;
1615
1616 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1617 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1618 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1619 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1620
1621 return tsf;
1622 }
1623
1624 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1625 {
1626 struct rt2x00_dev *rt2x00dev = hw->priv;
1627 u32 reg;
1628
1629 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1630 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1631 }
1632
1633 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1634 .tx = rt2x00mac_tx,
1635 .start = rt2x00mac_start,
1636 .stop = rt2x00mac_stop,
1637 .add_interface = rt2x00mac_add_interface,
1638 .remove_interface = rt2x00mac_remove_interface,
1639 .config = rt2x00mac_config,
1640 .configure_filter = rt2x00mac_configure_filter,
1641 .sw_scan_start = rt2x00mac_sw_scan_start,
1642 .sw_scan_complete = rt2x00mac_sw_scan_complete,
1643 .get_stats = rt2x00mac_get_stats,
1644 .bss_info_changed = rt2x00mac_bss_info_changed,
1645 .conf_tx = rt2400pci_conf_tx,
1646 .get_tsf = rt2400pci_get_tsf,
1647 .tx_last_beacon = rt2400pci_tx_last_beacon,
1648 .rfkill_poll = rt2x00mac_rfkill_poll,
1649 .flush = rt2x00mac_flush,
1650 };
1651
1652 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1653 .irq_handler = rt2400pci_interrupt,
1654 .irq_handler_thread = rt2400pci_interrupt_thread,
1655 .probe_hw = rt2400pci_probe_hw,
1656 .initialize = rt2x00pci_initialize,
1657 .uninitialize = rt2x00pci_uninitialize,
1658 .get_entry_state = rt2400pci_get_entry_state,
1659 .clear_entry = rt2400pci_clear_entry,
1660 .set_device_state = rt2400pci_set_device_state,
1661 .rfkill_poll = rt2400pci_rfkill_poll,
1662 .link_stats = rt2400pci_link_stats,
1663 .reset_tuner = rt2400pci_reset_tuner,
1664 .link_tuner = rt2400pci_link_tuner,
1665 .start_queue = rt2400pci_start_queue,
1666 .kick_queue = rt2400pci_kick_queue,
1667 .stop_queue = rt2400pci_stop_queue,
1668 .write_tx_desc = rt2400pci_write_tx_desc,
1669 .write_beacon = rt2400pci_write_beacon,
1670 .fill_rxdone = rt2400pci_fill_rxdone,
1671 .config_filter = rt2400pci_config_filter,
1672 .config_intf = rt2400pci_config_intf,
1673 .config_erp = rt2400pci_config_erp,
1674 .config_ant = rt2400pci_config_ant,
1675 .config = rt2400pci_config,
1676 };
1677
1678 static const struct data_queue_desc rt2400pci_queue_rx = {
1679 .entry_num = 24,
1680 .data_size = DATA_FRAME_SIZE,
1681 .desc_size = RXD_DESC_SIZE,
1682 .priv_size = sizeof(struct queue_entry_priv_pci),
1683 };
1684
1685 static const struct data_queue_desc rt2400pci_queue_tx = {
1686 .entry_num = 24,
1687 .data_size = DATA_FRAME_SIZE,
1688 .desc_size = TXD_DESC_SIZE,
1689 .priv_size = sizeof(struct queue_entry_priv_pci),
1690 };
1691
1692 static const struct data_queue_desc rt2400pci_queue_bcn = {
1693 .entry_num = 1,
1694 .data_size = MGMT_FRAME_SIZE,
1695 .desc_size = TXD_DESC_SIZE,
1696 .priv_size = sizeof(struct queue_entry_priv_pci),
1697 };
1698
1699 static const struct data_queue_desc rt2400pci_queue_atim = {
1700 .entry_num = 8,
1701 .data_size = DATA_FRAME_SIZE,
1702 .desc_size = TXD_DESC_SIZE,
1703 .priv_size = sizeof(struct queue_entry_priv_pci),
1704 };
1705
1706 static const struct rt2x00_ops rt2400pci_ops = {
1707 .name = KBUILD_MODNAME,
1708 .max_sta_intf = 1,
1709 .max_ap_intf = 1,
1710 .eeprom_size = EEPROM_SIZE,
1711 .rf_size = RF_SIZE,
1712 .tx_queues = NUM_TX_QUEUES,
1713 .extra_tx_headroom = 0,
1714 .rx = &rt2400pci_queue_rx,
1715 .tx = &rt2400pci_queue_tx,
1716 .bcn = &rt2400pci_queue_bcn,
1717 .atim = &rt2400pci_queue_atim,
1718 .lib = &rt2400pci_rt2x00_ops,
1719 .hw = &rt2400pci_mac80211_ops,
1720 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1721 .debugfs = &rt2400pci_rt2x00debug,
1722 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1723 };
1724
1725 /*
1726 * RT2400pci module information.
1727 */
1728 static DEFINE_PCI_DEVICE_TABLE(rt2400pci_device_table) = {
1729 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1730 { 0, }
1731 };
1732
1733 MODULE_AUTHOR(DRV_PROJECT);
1734 MODULE_VERSION(DRV_VERSION);
1735 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1736 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1737 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1738 MODULE_LICENSE("GPL");
1739
1740 static struct pci_driver rt2400pci_driver = {
1741 .name = KBUILD_MODNAME,
1742 .id_table = rt2400pci_device_table,
1743 .probe = rt2x00pci_probe,
1744 .remove = __devexit_p(rt2x00pci_remove),
1745 .suspend = rt2x00pci_suspend,
1746 .resume = rt2x00pci_resume,
1747 };
1748
1749 static int __init rt2400pci_init(void)
1750 {
1751 return pci_register_driver(&rt2400pci_driver);
1752 }
1753
1754 static void __exit rt2400pci_exit(void)
1755 {
1756 pci_unregister_driver(&rt2400pci_driver);
1757 }
1758
1759 module_init(rt2400pci_init);
1760 module_exit(rt2400pci_exit);
Linux kernel - Deliverables
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