2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
28 * Set enviroment defines for rt2x00.h
30 #define DRV_NAME "rt2500pci"
32 #include <linux/delay.h>
33 #include <linux/etherdevice.h>
34 #include <linux/init.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/eeprom_93cx6.h>
41 #include "rt2x00pci.h"
42 #include "rt2500pci.h"
46 * All access to the CSR registers will go through the methods
47 * rt2x00pci_register_read and rt2x00pci_register_write.
48 * BBP and RF register require indirect register access,
49 * and use the CSR registers BBPCSR and RFCSR to achieve this.
50 * These indirect registers work with busy bits,
51 * and we will try maximal REGISTER_BUSY_COUNT times to access
52 * the register while taking a REGISTER_BUSY_DELAY us delay
53 * between each attampt. When the busy bit is still set at that time,
54 * the access attempt is considered to have failed,
55 * and we will print an error.
57 static u32
rt2500pci_bbp_check(const struct rt2x00_dev
*rt2x00dev
)
62 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
63 rt2x00pci_register_read(rt2x00dev
, BBPCSR
, ®
);
64 if (!rt2x00_get_field32(reg
, BBPCSR_BUSY
))
66 udelay(REGISTER_BUSY_DELAY
);
72 static void rt2500pci_bbp_write(const struct rt2x00_dev
*rt2x00dev
,
73 const unsigned int word
, const u8 value
)
78 * Wait until the BBP becomes ready.
80 reg
= rt2500pci_bbp_check(rt2x00dev
);
81 if (rt2x00_get_field32(reg
, BBPCSR_BUSY
)) {
82 ERROR(rt2x00dev
, "BBPCSR register busy. Write failed.\n");
87 * Write the data into the BBP.
90 rt2x00_set_field32(®
, BBPCSR_VALUE
, value
);
91 rt2x00_set_field32(®
, BBPCSR_REGNUM
, word
);
92 rt2x00_set_field32(®
, BBPCSR_BUSY
, 1);
93 rt2x00_set_field32(®
, BBPCSR_WRITE_CONTROL
, 1);
95 rt2x00pci_register_write(rt2x00dev
, BBPCSR
, reg
);
98 static void rt2500pci_bbp_read(const struct rt2x00_dev
*rt2x00dev
,
99 const unsigned int word
, u8
*value
)
104 * Wait until the BBP becomes ready.
106 reg
= rt2500pci_bbp_check(rt2x00dev
);
107 if (rt2x00_get_field32(reg
, BBPCSR_BUSY
)) {
108 ERROR(rt2x00dev
, "BBPCSR register busy. Read failed.\n");
113 * Write the request into the BBP.
116 rt2x00_set_field32(®
, BBPCSR_REGNUM
, word
);
117 rt2x00_set_field32(®
, BBPCSR_BUSY
, 1);
118 rt2x00_set_field32(®
, BBPCSR_WRITE_CONTROL
, 0);
120 rt2x00pci_register_write(rt2x00dev
, BBPCSR
, reg
);
123 * Wait until the BBP becomes ready.
125 reg
= rt2500pci_bbp_check(rt2x00dev
);
126 if (rt2x00_get_field32(reg
, BBPCSR_BUSY
)) {
127 ERROR(rt2x00dev
, "BBPCSR register busy. Read failed.\n");
132 *value
= rt2x00_get_field32(reg
, BBPCSR_VALUE
);
135 static void rt2500pci_rf_write(const struct rt2x00_dev
*rt2x00dev
,
136 const unsigned int word
, const u32 value
)
144 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
145 rt2x00pci_register_read(rt2x00dev
, RFCSR
, ®
);
146 if (!rt2x00_get_field32(reg
, RFCSR_BUSY
))
148 udelay(REGISTER_BUSY_DELAY
);
151 ERROR(rt2x00dev
, "RFCSR register busy. Write failed.\n");
156 rt2x00_set_field32(®
, RFCSR_VALUE
, value
);
157 rt2x00_set_field32(®
, RFCSR_NUMBER_OF_BITS
, 20);
158 rt2x00_set_field32(®
, RFCSR_IF_SELECT
, 0);
159 rt2x00_set_field32(®
, RFCSR_BUSY
, 1);
161 rt2x00pci_register_write(rt2x00dev
, RFCSR
, reg
);
162 rt2x00_rf_write(rt2x00dev
, word
, value
);
165 static void rt2500pci_eepromregister_read(struct eeprom_93cx6
*eeprom
)
167 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
170 rt2x00pci_register_read(rt2x00dev
, CSR21
, ®
);
172 eeprom
->reg_data_in
= !!rt2x00_get_field32(reg
, CSR21_EEPROM_DATA_IN
);
173 eeprom
->reg_data_out
= !!rt2x00_get_field32(reg
, CSR21_EEPROM_DATA_OUT
);
174 eeprom
->reg_data_clock
=
175 !!rt2x00_get_field32(reg
, CSR21_EEPROM_DATA_CLOCK
);
176 eeprom
->reg_chip_select
=
177 !!rt2x00_get_field32(reg
, CSR21_EEPROM_CHIP_SELECT
);
180 static void rt2500pci_eepromregister_write(struct eeprom_93cx6
*eeprom
)
182 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
185 rt2x00_set_field32(®
, CSR21_EEPROM_DATA_IN
, !!eeprom
->reg_data_in
);
186 rt2x00_set_field32(®
, CSR21_EEPROM_DATA_OUT
, !!eeprom
->reg_data_out
);
187 rt2x00_set_field32(®
, CSR21_EEPROM_DATA_CLOCK
,
188 !!eeprom
->reg_data_clock
);
189 rt2x00_set_field32(®
, CSR21_EEPROM_CHIP_SELECT
,
190 !!eeprom
->reg_chip_select
);
192 rt2x00pci_register_write(rt2x00dev
, CSR21
, reg
);
195 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
196 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
198 static void rt2500pci_read_csr(const struct rt2x00_dev
*rt2x00dev
,
199 const unsigned int word
, u32
*data
)
201 rt2x00pci_register_read(rt2x00dev
, CSR_OFFSET(word
), data
);
204 static void rt2500pci_write_csr(const struct rt2x00_dev
*rt2x00dev
,
205 const unsigned int word
, u32 data
)
207 rt2x00pci_register_write(rt2x00dev
, CSR_OFFSET(word
), data
);
210 static const struct rt2x00debug rt2500pci_rt2x00debug
= {
211 .owner
= THIS_MODULE
,
213 .read
= rt2500pci_read_csr
,
214 .write
= rt2500pci_write_csr
,
215 .word_size
= sizeof(u32
),
216 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
219 .read
= rt2x00_eeprom_read
,
220 .write
= rt2x00_eeprom_write
,
221 .word_size
= sizeof(u16
),
222 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
225 .read
= rt2500pci_bbp_read
,
226 .write
= rt2500pci_bbp_write
,
227 .word_size
= sizeof(u8
),
228 .word_count
= BBP_SIZE
/ sizeof(u8
),
231 .read
= rt2x00_rf_read
,
232 .write
= rt2500pci_rf_write
,
233 .word_size
= sizeof(u32
),
234 .word_count
= RF_SIZE
/ sizeof(u32
),
237 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
239 #ifdef CONFIG_RT2500PCI_RFKILL
240 static int rt2500pci_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
244 rt2x00pci_register_read(rt2x00dev
, GPIOCSR
, ®
);
245 return rt2x00_get_field32(reg
, GPIOCSR_BIT0
);
247 #endif /* CONFIG_RT2400PCI_RFKILL */
250 * Configuration handlers.
252 static void rt2500pci_config_mac_addr(struct rt2x00_dev
*rt2x00dev
, u8
*addr
)
256 memset(®
, 0, sizeof(reg
));
257 memcpy(®
, addr
, ETH_ALEN
);
260 * The MAC address is passed to us as an array of bytes,
261 * that array is little endian, so no need for byte ordering.
263 rt2x00pci_register_multiwrite(rt2x00dev
, CSR3
, ®
, sizeof(reg
));
266 static void rt2500pci_config_bssid(struct rt2x00_dev
*rt2x00dev
, u8
*bssid
)
270 memset(®
, 0, sizeof(reg
));
271 memcpy(®
, bssid
, ETH_ALEN
);
274 * The BSSID is passed to us as an array of bytes,
275 * that array is little endian, so no need for byte ordering.
277 rt2x00pci_register_multiwrite(rt2x00dev
, CSR5
, ®
, sizeof(reg
));
280 static void rt2500pci_config_packet_filter(struct rt2x00_dev
*rt2x00dev
,
281 const unsigned int filter
)
283 int promisc
= !!(filter
& IFF_PROMISC
);
284 int multicast
= !!(filter
& IFF_MULTICAST
);
285 int broadcast
= !!(filter
& IFF_BROADCAST
);
288 rt2x00pci_register_read(rt2x00dev
, RXCSR0
, ®
);
289 rt2x00_set_field32(®
, RXCSR0_DROP_NOT_TO_ME
, !promisc
);
290 rt2x00_set_field32(®
, RXCSR0_DROP_MCAST
, !multicast
);
291 rt2x00_set_field32(®
, RXCSR0_DROP_BCAST
, !broadcast
);
292 rt2x00pci_register_write(rt2x00dev
, RXCSR0
, reg
);
295 static void rt2500pci_config_type(struct rt2x00_dev
*rt2x00dev
, const int type
)
299 rt2x00pci_register_write(rt2x00dev
, CSR14
, 0);
302 * Apply hardware packet filter.
304 rt2x00pci_register_read(rt2x00dev
, RXCSR0
, ®
);
306 if (!is_monitor_present(&rt2x00dev
->interface
) &&
307 (type
== IEEE80211_IF_TYPE_IBSS
|| type
== IEEE80211_IF_TYPE_STA
))
308 rt2x00_set_field32(®
, RXCSR0_DROP_TODS
, 1);
310 rt2x00_set_field32(®
, RXCSR0_DROP_TODS
, 0);
313 * If there is a non-monitor interface present
314 * the packet should be strict (even if a monitor interface is present!).
315 * When there is only 1 interface present which is in monitor mode
316 * we should start accepting _all_ frames.
318 if (is_interface_present(&rt2x00dev
->interface
)) {
319 rt2x00_set_field32(®
, RXCSR0_DROP_CRC
, 1);
320 rt2x00_set_field32(®
, RXCSR0_DROP_PHYSICAL
, 1);
321 rt2x00_set_field32(®
, RXCSR0_DROP_CONTROL
, 1);
322 rt2x00_set_field32(®
, RXCSR0_DROP_VERSION_ERROR
, 1);
323 } else if (is_monitor_present(&rt2x00dev
->interface
)) {
324 rt2x00_set_field32(®
, RXCSR0_DROP_CRC
, 0);
325 rt2x00_set_field32(®
, RXCSR0_DROP_PHYSICAL
, 0);
326 rt2x00_set_field32(®
, RXCSR0_DROP_CONTROL
, 0);
327 rt2x00_set_field32(®
, RXCSR0_DROP_VERSION_ERROR
, 0);
330 rt2x00pci_register_write(rt2x00dev
, RXCSR0
, reg
);
333 * Enable beacon config
335 rt2x00pci_register_read(rt2x00dev
, BCNCSR1
, ®
);
336 rt2x00_set_field32(®
, BCNCSR1_PRELOAD
,
337 PREAMBLE
+ get_duration(IEEE80211_HEADER
, 2));
338 rt2x00_set_field32(®
, BCNCSR1_BEACON_CWMIN
,
339 rt2x00lib_get_ring(rt2x00dev
,
340 IEEE80211_TX_QUEUE_BEACON
)
342 rt2x00pci_register_write(rt2x00dev
, BCNCSR1
, reg
);
345 * Enable synchronisation.
347 rt2x00pci_register_read(rt2x00dev
, CSR14
, ®
);
348 if (is_interface_present(&rt2x00dev
->interface
)) {
349 rt2x00_set_field32(®
, CSR14_TSF_COUNT
, 1);
350 rt2x00_set_field32(®
, CSR14_TBCN
, 1);
353 rt2x00_set_field32(®
, CSR14_BEACON_GEN
, 0);
354 if (type
== IEEE80211_IF_TYPE_IBSS
|| type
== IEEE80211_IF_TYPE_AP
)
355 rt2x00_set_field32(®
, CSR14_TSF_SYNC
, 2);
356 else if (type
== IEEE80211_IF_TYPE_STA
)
357 rt2x00_set_field32(®
, CSR14_TSF_SYNC
, 1);
358 else if (is_monitor_present(&rt2x00dev
->interface
) &&
359 !is_interface_present(&rt2x00dev
->interface
))
360 rt2x00_set_field32(®
, CSR14_TSF_SYNC
, 0);
362 rt2x00pci_register_write(rt2x00dev
, CSR14
, reg
);
365 static void rt2500pci_config_rate(struct rt2x00_dev
*rt2x00dev
, const int rate
)
367 struct ieee80211_conf
*conf
= &rt2x00dev
->hw
->conf
;
372 if (DEVICE_GET_RATE_FIELD(rate
, PREAMBLE
))
373 preamble
= SHORT_PREAMBLE
;
377 reg
= DEVICE_GET_RATE_FIELD(rate
, RATEMASK
) & DEV_BASIC_RATEMASK
;
378 rt2x00pci_register_write(rt2x00dev
, ARCSR1
, reg
);
380 rt2x00pci_register_read(rt2x00dev
, TXCSR1
, ®
);
381 value
= ((conf
->flags
& IEEE80211_CONF_SHORT_SLOT_TIME
) ?
383 PLCP
+ preamble
+ get_duration(ACK_SIZE
, 10);
384 rt2x00_set_field32(®
, TXCSR1_ACK_TIMEOUT
, value
);
385 value
= SIFS
+ PLCP
+ preamble
+ get_duration(ACK_SIZE
, 10);
386 rt2x00_set_field32(®
, TXCSR1_ACK_CONSUME_TIME
, value
);
387 rt2x00pci_register_write(rt2x00dev
, TXCSR1
, reg
);
389 preamble
= DEVICE_GET_RATE_FIELD(rate
, PREAMBLE
) ? 0x08 : 0x00;
391 rt2x00pci_register_read(rt2x00dev
, ARCSR2
, ®
);
392 rt2x00_set_field32(®
, ARCSR2_SIGNAL
, 0x00 | preamble
);
393 rt2x00_set_field32(®
, ARCSR2_SERVICE
, 0x04);
394 rt2x00_set_field32(®
, ARCSR2_LENGTH
, get_duration(ACK_SIZE
, 10));
395 rt2x00pci_register_write(rt2x00dev
, ARCSR2
, reg
);
397 rt2x00pci_register_read(rt2x00dev
, ARCSR3
, ®
);
398 rt2x00_set_field32(®
, ARCSR3_SIGNAL
, 0x01 | preamble
);
399 rt2x00_set_field32(®
, ARCSR3_SERVICE
, 0x04);
400 rt2x00_set_field32(®
, ARCSR2_LENGTH
, get_duration(ACK_SIZE
, 20));
401 rt2x00pci_register_write(rt2x00dev
, ARCSR3
, reg
);
403 rt2x00pci_register_read(rt2x00dev
, ARCSR4
, ®
);
404 rt2x00_set_field32(®
, ARCSR4_SIGNAL
, 0x02 | preamble
);
405 rt2x00_set_field32(®
, ARCSR4_SERVICE
, 0x04);
406 rt2x00_set_field32(®
, ARCSR2_LENGTH
, get_duration(ACK_SIZE
, 55));
407 rt2x00pci_register_write(rt2x00dev
, ARCSR4
, reg
);
409 rt2x00pci_register_read(rt2x00dev
, ARCSR5
, ®
);
410 rt2x00_set_field32(®
, ARCSR5_SIGNAL
, 0x03 | preamble
);
411 rt2x00_set_field32(®
, ARCSR5_SERVICE
, 0x84);
412 rt2x00_set_field32(®
, ARCSR2_LENGTH
, get_duration(ACK_SIZE
, 110));
413 rt2x00pci_register_write(rt2x00dev
, ARCSR5
, reg
);
416 static void rt2500pci_config_phymode(struct rt2x00_dev
*rt2x00dev
,
419 struct ieee80211_hw_mode
*mode
;
420 struct ieee80211_rate
*rate
;
422 if (phymode
== MODE_IEEE80211A
)
423 rt2x00dev
->curr_hwmode
= HWMODE_A
;
424 else if (phymode
== MODE_IEEE80211B
)
425 rt2x00dev
->curr_hwmode
= HWMODE_B
;
427 rt2x00dev
->curr_hwmode
= HWMODE_G
;
429 mode
= &rt2x00dev
->hwmodes
[rt2x00dev
->curr_hwmode
];
430 rate
= &mode
->rates
[mode
->num_rates
- 1];
432 rt2500pci_config_rate(rt2x00dev
, rate
->val2
);
435 static void rt2500pci_config_channel(struct rt2x00_dev
*rt2x00dev
,
436 const int index
, const int channel
,
439 struct rf_channel reg
;
443 * Fill rf_reg structure.
445 memcpy(®
, &rt2x00dev
->spec
.channels
[index
], sizeof(reg
));
450 rt2x00_set_field32(®
.rf3
, RF3_TXPOWER
, TXPOWER_TO_DEV(txpower
));
453 * Switch on tuning bits.
454 * For RT2523 devices we do not need to update the R1 register.
456 if (!rt2x00_rf(&rt2x00dev
->chip
, RF2523
))
457 rt2x00_set_field32(®
.rf1
, RF1_TUNER
, 1);
458 rt2x00_set_field32(®
.rf3
, RF3_TUNER
, 1);
461 * For RT2525 we should first set the channel to half band higher.
463 if (rt2x00_rf(&rt2x00dev
->chip
, RF2525
)) {
464 static const u32 vals
[] = {
465 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
466 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
467 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
468 0x00080d2e, 0x00080d3a
471 rt2500pci_rf_write(rt2x00dev
, 1, reg
.rf1
);
472 rt2500pci_rf_write(rt2x00dev
, 2, vals
[channel
- 1]);
473 rt2500pci_rf_write(rt2x00dev
, 3, reg
.rf3
);
475 rt2500pci_rf_write(rt2x00dev
, 4, reg
.rf4
);
478 rt2500pci_rf_write(rt2x00dev
, 1, reg
.rf1
);
479 rt2500pci_rf_write(rt2x00dev
, 2, reg
.rf2
);
480 rt2500pci_rf_write(rt2x00dev
, 3, reg
.rf3
);
482 rt2500pci_rf_write(rt2x00dev
, 4, reg
.rf4
);
485 * Channel 14 requires the Japan filter bit to be set.
488 rt2x00_set_field8(&r70
, BBP_R70_JAPAN_FILTER
, channel
== 14);
489 rt2500pci_bbp_write(rt2x00dev
, 70, r70
);
494 * Switch off tuning bits.
495 * For RT2523 devices we do not need to update the R1 register.
497 if (!rt2x00_rf(&rt2x00dev
->chip
, RF2523
)) {
498 rt2x00_set_field32(®
.rf1
, RF1_TUNER
, 0);
499 rt2500pci_rf_write(rt2x00dev
, 1, reg
.rf1
);
502 rt2x00_set_field32(®
.rf3
, RF3_TUNER
, 0);
503 rt2500pci_rf_write(rt2x00dev
, 3, reg
.rf3
);
506 * Clear false CRC during channel switch.
508 rt2x00pci_register_read(rt2x00dev
, CNT0
, ®
.rf1
);
511 static void rt2500pci_config_txpower(struct rt2x00_dev
*rt2x00dev
,
516 rt2x00_rf_read(rt2x00dev
, 3, &rf3
);
517 rt2x00_set_field32(&rf3
, RF3_TXPOWER
, TXPOWER_TO_DEV(txpower
));
518 rt2500pci_rf_write(rt2x00dev
, 3, rf3
);
521 static void rt2500pci_config_antenna(struct rt2x00_dev
*rt2x00dev
,
522 const int antenna_tx
, const int antenna_rx
)
528 rt2x00pci_register_read(rt2x00dev
, BBPCSR1
, ®
);
529 rt2500pci_bbp_read(rt2x00dev
, 14, &r14
);
530 rt2500pci_bbp_read(rt2x00dev
, 2, &r2
);
533 * Configure the TX antenna.
535 switch (antenna_tx
) {
536 case ANTENNA_SW_DIVERSITY
:
537 case ANTENNA_HW_DIVERSITY
:
538 rt2x00_set_field8(&r2
, BBP_R2_TX_ANTENNA
, 2);
539 rt2x00_set_field32(®
, BBPCSR1_CCK
, 2);
540 rt2x00_set_field32(®
, BBPCSR1_OFDM
, 2);
543 rt2x00_set_field8(&r2
, BBP_R2_TX_ANTENNA
, 0);
544 rt2x00_set_field32(®
, BBPCSR1_CCK
, 0);
545 rt2x00_set_field32(®
, BBPCSR1_OFDM
, 0);
548 rt2x00_set_field8(&r2
, BBP_R2_TX_ANTENNA
, 2);
549 rt2x00_set_field32(®
, BBPCSR1_CCK
, 2);
550 rt2x00_set_field32(®
, BBPCSR1_OFDM
, 2);
555 * Configure the RX antenna.
557 switch (antenna_rx
) {
558 case ANTENNA_SW_DIVERSITY
:
559 case ANTENNA_HW_DIVERSITY
:
560 rt2x00_set_field8(&r14
, BBP_R14_RX_ANTENNA
, 2);
563 rt2x00_set_field8(&r14
, BBP_R14_RX_ANTENNA
, 0);
566 rt2x00_set_field8(&r14
, BBP_R14_RX_ANTENNA
, 2);
571 * RT2525E and RT5222 need to flip TX I/Q
573 if (rt2x00_rf(&rt2x00dev
->chip
, RF2525E
) ||
574 rt2x00_rf(&rt2x00dev
->chip
, RF5222
)) {
575 rt2x00_set_field8(&r2
, BBP_R2_TX_IQ_FLIP
, 1);
576 rt2x00_set_field32(®
, BBPCSR1_CCK_FLIP
, 1);
577 rt2x00_set_field32(®
, BBPCSR1_OFDM_FLIP
, 1);
580 * RT2525E does not need RX I/Q Flip.
582 if (rt2x00_rf(&rt2x00dev
->chip
, RF2525E
))
583 rt2x00_set_field8(&r14
, BBP_R14_RX_IQ_FLIP
, 0);
585 rt2x00_set_field32(®
, BBPCSR1_CCK_FLIP
, 0);
586 rt2x00_set_field32(®
, BBPCSR1_OFDM_FLIP
, 0);
589 rt2x00pci_register_write(rt2x00dev
, BBPCSR1
, reg
);
590 rt2500pci_bbp_write(rt2x00dev
, 14, r14
);
591 rt2500pci_bbp_write(rt2x00dev
, 2, r2
);
594 static void rt2500pci_config_duration(struct rt2x00_dev
*rt2x00dev
,
595 const int short_slot_time
,
596 const int beacon_int
)
600 rt2x00pci_register_read(rt2x00dev
, CSR11
, ®
);
601 rt2x00_set_field32(®
, CSR11_SLOT_TIME
,
602 short_slot_time
? SHORT_SLOT_TIME
: SLOT_TIME
);
603 rt2x00pci_register_write(rt2x00dev
, CSR11
, reg
);
605 rt2x00pci_register_read(rt2x00dev
, CSR18
, ®
);
606 rt2x00_set_field32(®
, CSR18_SIFS
, SIFS
);
607 rt2x00_set_field32(®
, CSR18_PIFS
,
608 short_slot_time
? SHORT_PIFS
: PIFS
);
609 rt2x00pci_register_write(rt2x00dev
, CSR18
, reg
);
611 rt2x00pci_register_read(rt2x00dev
, CSR19
, ®
);
612 rt2x00_set_field32(®
, CSR19_DIFS
,
613 short_slot_time
? SHORT_DIFS
: DIFS
);
614 rt2x00_set_field32(®
, CSR19_EIFS
, EIFS
);
615 rt2x00pci_register_write(rt2x00dev
, CSR19
, reg
);
617 rt2x00pci_register_read(rt2x00dev
, TXCSR1
, ®
);
618 rt2x00_set_field32(®
, TXCSR1_TSF_OFFSET
, IEEE80211_HEADER
);
619 rt2x00_set_field32(®
, TXCSR1_AUTORESPONDER
, 1);
620 rt2x00pci_register_write(rt2x00dev
, TXCSR1
, reg
);
622 rt2x00pci_register_read(rt2x00dev
, CSR12
, ®
);
623 rt2x00_set_field32(®
, CSR12_BEACON_INTERVAL
, beacon_int
* 16);
624 rt2x00_set_field32(®
, CSR12_CFP_MAX_DURATION
, beacon_int
* 16);
625 rt2x00pci_register_write(rt2x00dev
, CSR12
, reg
);
628 static void rt2500pci_config(struct rt2x00_dev
*rt2x00dev
,
629 const unsigned int flags
,
630 struct ieee80211_conf
*conf
)
632 int short_slot_time
= conf
->flags
& IEEE80211_CONF_SHORT_SLOT_TIME
;
634 if (flags
& CONFIG_UPDATE_PHYMODE
)
635 rt2500pci_config_phymode(rt2x00dev
, conf
->phymode
);
636 if (flags
& CONFIG_UPDATE_CHANNEL
)
637 rt2500pci_config_channel(rt2x00dev
, conf
->channel_val
,
638 conf
->channel
, conf
->power_level
);
639 if ((flags
& CONFIG_UPDATE_TXPOWER
) && !(flags
& CONFIG_UPDATE_CHANNEL
))
640 rt2500pci_config_txpower(rt2x00dev
, conf
->power_level
);
641 if (flags
& CONFIG_UPDATE_ANTENNA
)
642 rt2500pci_config_antenna(rt2x00dev
, conf
->antenna_sel_tx
,
643 conf
->antenna_sel_rx
);
644 if (flags
& (CONFIG_UPDATE_SLOT_TIME
| CONFIG_UPDATE_BEACON_INT
))
645 rt2500pci_config_duration(rt2x00dev
, short_slot_time
,
652 static void rt2500pci_enable_led(struct rt2x00_dev
*rt2x00dev
)
656 rt2x00pci_register_read(rt2x00dev
, LEDCSR
, ®
);
658 rt2x00_set_field32(®
, LEDCSR_ON_PERIOD
, 70);
659 rt2x00_set_field32(®
, LEDCSR_OFF_PERIOD
, 30);
661 if (rt2x00dev
->led_mode
== LED_MODE_TXRX_ACTIVITY
) {
662 rt2x00_set_field32(®
, LEDCSR_LINK
, 1);
663 rt2x00_set_field32(®
, LEDCSR_ACTIVITY
, 0);
664 } else if (rt2x00dev
->led_mode
== LED_MODE_ASUS
) {
665 rt2x00_set_field32(®
, LEDCSR_LINK
, 0);
666 rt2x00_set_field32(®
, LEDCSR_ACTIVITY
, 1);
668 rt2x00_set_field32(®
, LEDCSR_LINK
, 1);
669 rt2x00_set_field32(®
, LEDCSR_ACTIVITY
, 1);
672 rt2x00pci_register_write(rt2x00dev
, LEDCSR
, reg
);
675 static void rt2500pci_disable_led(struct rt2x00_dev
*rt2x00dev
)
679 rt2x00pci_register_read(rt2x00dev
, LEDCSR
, ®
);
680 rt2x00_set_field32(®
, LEDCSR_LINK
, 0);
681 rt2x00_set_field32(®
, LEDCSR_ACTIVITY
, 0);
682 rt2x00pci_register_write(rt2x00dev
, LEDCSR
, reg
);
688 static void rt2500pci_link_stats(struct rt2x00_dev
*rt2x00dev
)
693 * Update FCS error count from register.
695 rt2x00pci_register_read(rt2x00dev
, CNT0
, ®
);
696 rt2x00dev
->link
.rx_failed
= rt2x00_get_field32(reg
, CNT0_FCS_ERROR
);
699 * Update False CCA count from register.
701 rt2x00pci_register_read(rt2x00dev
, CNT3
, ®
);
702 rt2x00dev
->link
.false_cca
= rt2x00_get_field32(reg
, CNT3_FALSE_CCA
);
705 static void rt2500pci_reset_tuner(struct rt2x00_dev
*rt2x00dev
)
707 rt2500pci_bbp_write(rt2x00dev
, 17, 0x48);
708 rt2x00dev
->link
.vgc_level
= 0x48;
711 static void rt2500pci_link_tuner(struct rt2x00_dev
*rt2x00dev
)
713 int rssi
= rt2x00_get_link_rssi(&rt2x00dev
->link
);
717 * To prevent collisions with MAC ASIC on chipsets
718 * up to version C the link tuning should halt after 20
721 if (rt2x00_get_rev(&rt2x00dev
->chip
) < RT2560_VERSION_D
&&
722 rt2x00dev
->link
.count
> 20)
725 rt2500pci_bbp_read(rt2x00dev
, 17, &r17
);
728 * Chipset versions C and lower should directly continue
729 * to the dynamic CCA tuning.
731 if (rt2x00_get_rev(&rt2x00dev
->chip
) < RT2560_VERSION_D
)
732 goto dynamic_cca_tune
;
735 * A too low RSSI will cause too much false CCA which will
736 * then corrupt the R17 tuning. To remidy this the tuning should
737 * be stopped (While making sure the R17 value will not exceed limits)
739 if (rssi
< -80 && rt2x00dev
->link
.count
> 20) {
741 r17
= rt2x00dev
->link
.vgc_level
;
742 rt2500pci_bbp_write(rt2x00dev
, 17, r17
);
748 * Special big-R17 for short distance
752 rt2500pci_bbp_write(rt2x00dev
, 17, 0x50);
757 * Special mid-R17 for middle distance
761 rt2500pci_bbp_write(rt2x00dev
, 17, 0x41);
766 * Leave short or middle distance condition, restore r17
767 * to the dynamic tuning range.
770 rt2500pci_bbp_write(rt2x00dev
, 17, rt2x00dev
->link
.vgc_level
);
777 * R17 is inside the dynamic tuning range,
778 * start tuning the link based on the false cca counter.
780 if (rt2x00dev
->link
.false_cca
> 512 && r17
< 0x40) {
781 rt2500pci_bbp_write(rt2x00dev
, 17, ++r17
);
782 rt2x00dev
->link
.vgc_level
= r17
;
783 } else if (rt2x00dev
->link
.false_cca
< 100 && r17
> 0x32) {
784 rt2500pci_bbp_write(rt2x00dev
, 17, --r17
);
785 rt2x00dev
->link
.vgc_level
= r17
;
790 * Initialization functions.
792 static void rt2500pci_init_rxring(struct rt2x00_dev
*rt2x00dev
)
794 struct data_ring
*ring
= rt2x00dev
->rx
;
795 struct data_desc
*rxd
;
799 memset(ring
->data_addr
, 0x00, rt2x00_get_ring_size(ring
));
801 for (i
= 0; i
< ring
->stats
.limit
; i
++) {
802 rxd
= ring
->entry
[i
].priv
;
804 rt2x00_desc_read(rxd
, 1, &word
);
805 rt2x00_set_field32(&word
, RXD_W1_BUFFER_ADDRESS
,
806 ring
->entry
[i
].data_dma
);
807 rt2x00_desc_write(rxd
, 1, word
);
809 rt2x00_desc_read(rxd
, 0, &word
);
810 rt2x00_set_field32(&word
, RXD_W0_OWNER_NIC
, 1);
811 rt2x00_desc_write(rxd
, 0, word
);
814 rt2x00_ring_index_clear(rt2x00dev
->rx
);
817 static void rt2500pci_init_txring(struct rt2x00_dev
*rt2x00dev
, const int queue
)
819 struct data_ring
*ring
= rt2x00lib_get_ring(rt2x00dev
, queue
);
820 struct data_desc
*txd
;
824 memset(ring
->data_addr
, 0x00, rt2x00_get_ring_size(ring
));
826 for (i
= 0; i
< ring
->stats
.limit
; i
++) {
827 txd
= ring
->entry
[i
].priv
;
829 rt2x00_desc_read(txd
, 1, &word
);
830 rt2x00_set_field32(&word
, TXD_W1_BUFFER_ADDRESS
,
831 ring
->entry
[i
].data_dma
);
832 rt2x00_desc_write(txd
, 1, word
);
834 rt2x00_desc_read(txd
, 0, &word
);
835 rt2x00_set_field32(&word
, TXD_W0_VALID
, 0);
836 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 0);
837 rt2x00_desc_write(txd
, 0, word
);
840 rt2x00_ring_index_clear(ring
);
843 static int rt2500pci_init_rings(struct rt2x00_dev
*rt2x00dev
)
850 rt2500pci_init_rxring(rt2x00dev
);
851 rt2500pci_init_txring(rt2x00dev
, IEEE80211_TX_QUEUE_DATA0
);
852 rt2500pci_init_txring(rt2x00dev
, IEEE80211_TX_QUEUE_DATA1
);
853 rt2500pci_init_txring(rt2x00dev
, IEEE80211_TX_QUEUE_AFTER_BEACON
);
854 rt2500pci_init_txring(rt2x00dev
, IEEE80211_TX_QUEUE_BEACON
);
857 * Initialize registers.
859 rt2x00pci_register_read(rt2x00dev
, TXCSR2
, ®
);
860 rt2x00_set_field32(®
, TXCSR2_TXD_SIZE
,
861 rt2x00dev
->tx
[IEEE80211_TX_QUEUE_DATA0
].desc_size
);
862 rt2x00_set_field32(®
, TXCSR2_NUM_TXD
,
863 rt2x00dev
->tx
[IEEE80211_TX_QUEUE_DATA1
].stats
.limit
);
864 rt2x00_set_field32(®
, TXCSR2_NUM_ATIM
,
865 rt2x00dev
->bcn
[1].stats
.limit
);
866 rt2x00_set_field32(®
, TXCSR2_NUM_PRIO
,
867 rt2x00dev
->tx
[IEEE80211_TX_QUEUE_DATA0
].stats
.limit
);
868 rt2x00pci_register_write(rt2x00dev
, TXCSR2
, reg
);
870 rt2x00pci_register_read(rt2x00dev
, TXCSR3
, ®
);
871 rt2x00_set_field32(®
, TXCSR3_TX_RING_REGISTER
,
872 rt2x00dev
->tx
[IEEE80211_TX_QUEUE_DATA1
].data_dma
);
873 rt2x00pci_register_write(rt2x00dev
, TXCSR3
, reg
);
875 rt2x00pci_register_read(rt2x00dev
, TXCSR5
, ®
);
876 rt2x00_set_field32(®
, TXCSR5_PRIO_RING_REGISTER
,
877 rt2x00dev
->tx
[IEEE80211_TX_QUEUE_DATA0
].data_dma
);
878 rt2x00pci_register_write(rt2x00dev
, TXCSR5
, reg
);
880 rt2x00pci_register_read(rt2x00dev
, TXCSR4
, ®
);
881 rt2x00_set_field32(®
, TXCSR4_ATIM_RING_REGISTER
,
882 rt2x00dev
->bcn
[1].data_dma
);
883 rt2x00pci_register_write(rt2x00dev
, TXCSR4
, reg
);
885 rt2x00pci_register_read(rt2x00dev
, TXCSR6
, ®
);
886 rt2x00_set_field32(®
, TXCSR6_BEACON_RING_REGISTER
,
887 rt2x00dev
->bcn
[0].data_dma
);
888 rt2x00pci_register_write(rt2x00dev
, TXCSR6
, reg
);
890 rt2x00pci_register_read(rt2x00dev
, RXCSR1
, ®
);
891 rt2x00_set_field32(®
, RXCSR1_RXD_SIZE
, rt2x00dev
->rx
->desc_size
);
892 rt2x00_set_field32(®
, RXCSR1_NUM_RXD
, rt2x00dev
->rx
->stats
.limit
);
893 rt2x00pci_register_write(rt2x00dev
, RXCSR1
, reg
);
895 rt2x00pci_register_read(rt2x00dev
, RXCSR2
, ®
);
896 rt2x00_set_field32(®
, RXCSR2_RX_RING_REGISTER
,
897 rt2x00dev
->rx
->data_dma
);
898 rt2x00pci_register_write(rt2x00dev
, RXCSR2
, reg
);
903 static int rt2500pci_init_registers(struct rt2x00_dev
*rt2x00dev
)
907 rt2x00pci_register_write(rt2x00dev
, PSCSR0
, 0x00020002);
908 rt2x00pci_register_write(rt2x00dev
, PSCSR1
, 0x00000002);
909 rt2x00pci_register_write(rt2x00dev
, PSCSR2
, 0x00020002);
910 rt2x00pci_register_write(rt2x00dev
, PSCSR3
, 0x00000002);
912 rt2x00pci_register_read(rt2x00dev
, TIMECSR
, ®
);
913 rt2x00_set_field32(®
, TIMECSR_US_COUNT
, 33);
914 rt2x00_set_field32(®
, TIMECSR_US_64_COUNT
, 63);
915 rt2x00_set_field32(®
, TIMECSR_BEACON_EXPECT
, 0);
916 rt2x00pci_register_write(rt2x00dev
, TIMECSR
, reg
);
918 rt2x00pci_register_read(rt2x00dev
, CSR9
, ®
);
919 rt2x00_set_field32(®
, CSR9_MAX_FRAME_UNIT
,
920 rt2x00dev
->rx
->data_size
/ 128);
921 rt2x00pci_register_write(rt2x00dev
, CSR9
, reg
);
924 * Always use CWmin and CWmax set in descriptor.
926 rt2x00pci_register_read(rt2x00dev
, CSR11
, ®
);
927 rt2x00_set_field32(®
, CSR11_CW_SELECT
, 0);
928 rt2x00pci_register_write(rt2x00dev
, CSR11
, reg
);
930 rt2x00pci_register_write(rt2x00dev
, CNT3
, 0);
932 rt2x00pci_register_read(rt2x00dev
, TXCSR8
, ®
);
933 rt2x00_set_field32(®
, TXCSR8_BBP_ID0
, 10);
934 rt2x00_set_field32(®
, TXCSR8_BBP_ID0_VALID
, 1);
935 rt2x00_set_field32(®
, TXCSR8_BBP_ID1
, 11);
936 rt2x00_set_field32(®
, TXCSR8_BBP_ID1_VALID
, 1);
937 rt2x00_set_field32(®
, TXCSR8_BBP_ID2
, 13);
938 rt2x00_set_field32(®
, TXCSR8_BBP_ID2_VALID
, 1);
939 rt2x00_set_field32(®
, TXCSR8_BBP_ID3
, 12);
940 rt2x00_set_field32(®
, TXCSR8_BBP_ID3_VALID
, 1);
941 rt2x00pci_register_write(rt2x00dev
, TXCSR8
, reg
);
943 rt2x00pci_register_read(rt2x00dev
, ARTCSR0
, ®
);
944 rt2x00_set_field32(®
, ARTCSR0_ACK_CTS_1MBS
, 112);
945 rt2x00_set_field32(®
, ARTCSR0_ACK_CTS_2MBS
, 56);
946 rt2x00_set_field32(®
, ARTCSR0_ACK_CTS_5_5MBS
, 20);
947 rt2x00_set_field32(®
, ARTCSR0_ACK_CTS_11MBS
, 10);
948 rt2x00pci_register_write(rt2x00dev
, ARTCSR0
, reg
);
950 rt2x00pci_register_read(rt2x00dev
, ARTCSR1
, ®
);
951 rt2x00_set_field32(®
, ARTCSR1_ACK_CTS_6MBS
, 45);
952 rt2x00_set_field32(®
, ARTCSR1_ACK_CTS_9MBS
, 37);
953 rt2x00_set_field32(®
, ARTCSR1_ACK_CTS_12MBS
, 33);
954 rt2x00_set_field32(®
, ARTCSR1_ACK_CTS_18MBS
, 29);
955 rt2x00pci_register_write(rt2x00dev
, ARTCSR1
, reg
);
957 rt2x00pci_register_read(rt2x00dev
, ARTCSR2
, ®
);
958 rt2x00_set_field32(®
, ARTCSR2_ACK_CTS_24MBS
, 29);
959 rt2x00_set_field32(®
, ARTCSR2_ACK_CTS_36MBS
, 25);
960 rt2x00_set_field32(®
, ARTCSR2_ACK_CTS_48MBS
, 25);
961 rt2x00_set_field32(®
, ARTCSR2_ACK_CTS_54MBS
, 25);
962 rt2x00pci_register_write(rt2x00dev
, ARTCSR2
, reg
);
964 rt2x00pci_register_read(rt2x00dev
, RXCSR3
, ®
);
965 rt2x00_set_field32(®
, RXCSR3_BBP_ID0
, 47); /* CCK Signal */
966 rt2x00_set_field32(®
, RXCSR3_BBP_ID0_VALID
, 1);
967 rt2x00_set_field32(®
, RXCSR3_BBP_ID1
, 51); /* Rssi */
968 rt2x00_set_field32(®
, RXCSR3_BBP_ID1_VALID
, 1);
969 rt2x00_set_field32(®
, RXCSR3_BBP_ID2
, 42); /* OFDM Rate */
970 rt2x00_set_field32(®
, RXCSR3_BBP_ID2_VALID
, 1);
971 rt2x00_set_field32(®
, RXCSR3_BBP_ID3
, 51); /* RSSI */
972 rt2x00_set_field32(®
, RXCSR3_BBP_ID3_VALID
, 1);
973 rt2x00pci_register_write(rt2x00dev
, RXCSR3
, reg
);
975 rt2x00pci_register_read(rt2x00dev
, PCICSR
, ®
);
976 rt2x00_set_field32(®
, PCICSR_BIG_ENDIAN
, 0);
977 rt2x00_set_field32(®
, PCICSR_RX_TRESHOLD
, 0);
978 rt2x00_set_field32(®
, PCICSR_TX_TRESHOLD
, 3);
979 rt2x00_set_field32(®
, PCICSR_BURST_LENTH
, 1);
980 rt2x00_set_field32(®
, PCICSR_ENABLE_CLK
, 1);
981 rt2x00_set_field32(®
, PCICSR_READ_MULTIPLE
, 1);
982 rt2x00_set_field32(®
, PCICSR_WRITE_INVALID
, 1);
983 rt2x00pci_register_write(rt2x00dev
, PCICSR
, reg
);
985 rt2x00pci_register_write(rt2x00dev
, PWRCSR0
, 0x3f3b3100);
987 rt2x00pci_register_write(rt2x00dev
, GPIOCSR
, 0x0000ff00);
988 rt2x00pci_register_write(rt2x00dev
, TESTCSR
, 0x000000f0);
990 if (rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, STATE_AWAKE
))
993 rt2x00pci_register_write(rt2x00dev
, MACCSR0
, 0x00213223);
994 rt2x00pci_register_write(rt2x00dev
, MACCSR1
, 0x00235518);
996 rt2x00pci_register_read(rt2x00dev
, MACCSR2
, ®
);
997 rt2x00_set_field32(®
, MACCSR2_DELAY
, 64);
998 rt2x00pci_register_write(rt2x00dev
, MACCSR2
, reg
);
1000 rt2x00pci_register_read(rt2x00dev
, RALINKCSR
, ®
);
1001 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_DATA0
, 17);
1002 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_ID0
, 26);
1003 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_VALID0
, 1);
1004 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_DATA1
, 0);
1005 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_ID1
, 26);
1006 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_VALID1
, 1);
1007 rt2x00pci_register_write(rt2x00dev
, RALINKCSR
, reg
);
1009 rt2x00pci_register_write(rt2x00dev
, BBPCSR1
, 0x82188200);
1011 rt2x00pci_register_write(rt2x00dev
, TXACKCSR0
, 0x00000020);
1013 rt2x00pci_register_read(rt2x00dev
, CSR1
, ®
);
1014 rt2x00_set_field32(®
, CSR1_SOFT_RESET
, 1);
1015 rt2x00_set_field32(®
, CSR1_BBP_RESET
, 0);
1016 rt2x00_set_field32(®
, CSR1_HOST_READY
, 0);
1017 rt2x00pci_register_write(rt2x00dev
, CSR1
, reg
);
1019 rt2x00pci_register_read(rt2x00dev
, CSR1
, ®
);
1020 rt2x00_set_field32(®
, CSR1_SOFT_RESET
, 0);
1021 rt2x00_set_field32(®
, CSR1_HOST_READY
, 1);
1022 rt2x00pci_register_write(rt2x00dev
, CSR1
, reg
);
1025 * We must clear the FCS and FIFO error count.
1026 * These registers are cleared on read,
1027 * so we may pass a useless variable to store the value.
1029 rt2x00pci_register_read(rt2x00dev
, CNT0
, ®
);
1030 rt2x00pci_register_read(rt2x00dev
, CNT4
, ®
);
1035 static int rt2500pci_init_bbp(struct rt2x00_dev
*rt2x00dev
)
1042 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1043 rt2500pci_bbp_read(rt2x00dev
, 0, &value
);
1044 if ((value
!= 0xff) && (value
!= 0x00))
1045 goto continue_csr_init
;
1046 NOTICE(rt2x00dev
, "Waiting for BBP register.\n");
1047 udelay(REGISTER_BUSY_DELAY
);
1050 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
1054 rt2500pci_bbp_write(rt2x00dev
, 3, 0x02);
1055 rt2500pci_bbp_write(rt2x00dev
, 4, 0x19);
1056 rt2500pci_bbp_write(rt2x00dev
, 14, 0x1c);
1057 rt2500pci_bbp_write(rt2x00dev
, 15, 0x30);
1058 rt2500pci_bbp_write(rt2x00dev
, 16, 0xac);
1059 rt2500pci_bbp_write(rt2x00dev
, 18, 0x18);
1060 rt2500pci_bbp_write(rt2x00dev
, 19, 0xff);
1061 rt2500pci_bbp_write(rt2x00dev
, 20, 0x1e);
1062 rt2500pci_bbp_write(rt2x00dev
, 21, 0x08);
1063 rt2500pci_bbp_write(rt2x00dev
, 22, 0x08);
1064 rt2500pci_bbp_write(rt2x00dev
, 23, 0x08);
1065 rt2500pci_bbp_write(rt2x00dev
, 24, 0x70);
1066 rt2500pci_bbp_write(rt2x00dev
, 25, 0x40);
1067 rt2500pci_bbp_write(rt2x00dev
, 26, 0x08);
1068 rt2500pci_bbp_write(rt2x00dev
, 27, 0x23);
1069 rt2500pci_bbp_write(rt2x00dev
, 30, 0x10);
1070 rt2500pci_bbp_write(rt2x00dev
, 31, 0x2b);
1071 rt2500pci_bbp_write(rt2x00dev
, 32, 0xb9);
1072 rt2500pci_bbp_write(rt2x00dev
, 34, 0x12);
1073 rt2500pci_bbp_write(rt2x00dev
, 35, 0x50);
1074 rt2500pci_bbp_write(rt2x00dev
, 39, 0xc4);
1075 rt2500pci_bbp_write(rt2x00dev
, 40, 0x02);
1076 rt2500pci_bbp_write(rt2x00dev
, 41, 0x60);
1077 rt2500pci_bbp_write(rt2x00dev
, 53, 0x10);
1078 rt2500pci_bbp_write(rt2x00dev
, 54, 0x18);
1079 rt2500pci_bbp_write(rt2x00dev
, 56, 0x08);
1080 rt2500pci_bbp_write(rt2x00dev
, 57, 0x10);
1081 rt2500pci_bbp_write(rt2x00dev
, 58, 0x08);
1082 rt2500pci_bbp_write(rt2x00dev
, 61, 0x6d);
1083 rt2500pci_bbp_write(rt2x00dev
, 62, 0x10);
1085 DEBUG(rt2x00dev
, "Start initialization from EEPROM...\n");
1086 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
1087 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
1089 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
1090 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
1091 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
1092 DEBUG(rt2x00dev
, "BBP: 0x%02x, value: 0x%02x.\n",
1094 rt2500pci_bbp_write(rt2x00dev
, reg_id
, value
);
1097 DEBUG(rt2x00dev
, "...End initialization from EEPROM.\n");
1103 * Device state switch handlers.
1105 static void rt2500pci_toggle_rx(struct rt2x00_dev
*rt2x00dev
,
1106 enum dev_state state
)
1110 rt2x00pci_register_read(rt2x00dev
, RXCSR0
, ®
);
1111 rt2x00_set_field32(®
, RXCSR0_DISABLE_RX
,
1112 state
== STATE_RADIO_RX_OFF
);
1113 rt2x00pci_register_write(rt2x00dev
, RXCSR0
, reg
);
1116 static void rt2500pci_toggle_irq(struct rt2x00_dev
*rt2x00dev
,
1117 enum dev_state state
)
1119 int mask
= (state
== STATE_RADIO_IRQ_OFF
);
1123 * When interrupts are being enabled, the interrupt registers
1124 * should clear the register to assure a clean state.
1126 if (state
== STATE_RADIO_IRQ_ON
) {
1127 rt2x00pci_register_read(rt2x00dev
, CSR7
, ®
);
1128 rt2x00pci_register_write(rt2x00dev
, CSR7
, reg
);
1132 * Only toggle the interrupts bits we are going to use.
1133 * Non-checked interrupt bits are disabled by default.
1135 rt2x00pci_register_read(rt2x00dev
, CSR8
, ®
);
1136 rt2x00_set_field32(®
, CSR8_TBCN_EXPIRE
, mask
);
1137 rt2x00_set_field32(®
, CSR8_TXDONE_TXRING
, mask
);
1138 rt2x00_set_field32(®
, CSR8_TXDONE_ATIMRING
, mask
);
1139 rt2x00_set_field32(®
, CSR8_TXDONE_PRIORING
, mask
);
1140 rt2x00_set_field32(®
, CSR8_RXDONE
, mask
);
1141 rt2x00pci_register_write(rt2x00dev
, CSR8
, reg
);
1144 static int rt2500pci_enable_radio(struct rt2x00_dev
*rt2x00dev
)
1147 * Initialize all registers.
1149 if (rt2500pci_init_rings(rt2x00dev
) ||
1150 rt2500pci_init_registers(rt2x00dev
) ||
1151 rt2500pci_init_bbp(rt2x00dev
)) {
1152 ERROR(rt2x00dev
, "Register initialization failed.\n");
1157 * Enable interrupts.
1159 rt2500pci_toggle_irq(rt2x00dev
, STATE_RADIO_IRQ_ON
);
1164 rt2500pci_enable_led(rt2x00dev
);
1169 static void rt2500pci_disable_radio(struct rt2x00_dev
*rt2x00dev
)
1176 rt2500pci_disable_led(rt2x00dev
);
1178 rt2x00pci_register_write(rt2x00dev
, PWRCSR0
, 0);
1181 * Disable synchronisation.
1183 rt2x00pci_register_write(rt2x00dev
, CSR14
, 0);
1188 rt2x00pci_register_read(rt2x00dev
, TXCSR0
, ®
);
1189 rt2x00_set_field32(®
, TXCSR0_ABORT
, 1);
1190 rt2x00pci_register_write(rt2x00dev
, TXCSR0
, reg
);
1193 * Disable interrupts.
1195 rt2500pci_toggle_irq(rt2x00dev
, STATE_RADIO_IRQ_OFF
);
1198 static int rt2500pci_set_state(struct rt2x00_dev
*rt2x00dev
,
1199 enum dev_state state
)
1207 put_to_sleep
= (state
!= STATE_AWAKE
);
1209 rt2x00pci_register_read(rt2x00dev
, PWRCSR1
, ®
);
1210 rt2x00_set_field32(®
, PWRCSR1_SET_STATE
, 1);
1211 rt2x00_set_field32(®
, PWRCSR1_BBP_DESIRE_STATE
, state
);
1212 rt2x00_set_field32(®
, PWRCSR1_RF_DESIRE_STATE
, state
);
1213 rt2x00_set_field32(®
, PWRCSR1_PUT_TO_SLEEP
, put_to_sleep
);
1214 rt2x00pci_register_write(rt2x00dev
, PWRCSR1
, reg
);
1217 * Device is not guaranteed to be in the requested state yet.
1218 * We must wait until the register indicates that the
1219 * device has entered the correct state.
1221 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1222 rt2x00pci_register_read(rt2x00dev
, PWRCSR1
, ®
);
1223 bbp_state
= rt2x00_get_field32(reg
, PWRCSR1_BBP_CURR_STATE
);
1224 rf_state
= rt2x00_get_field32(reg
, PWRCSR1_RF_CURR_STATE
);
1225 if (bbp_state
== state
&& rf_state
== state
)
1230 NOTICE(rt2x00dev
, "Device failed to enter state %d, "
1231 "current device state: bbp %d and rf %d.\n",
1232 state
, bbp_state
, rf_state
);
1237 static int rt2500pci_set_device_state(struct rt2x00_dev
*rt2x00dev
,
1238 enum dev_state state
)
1243 case STATE_RADIO_ON
:
1244 retval
= rt2500pci_enable_radio(rt2x00dev
);
1246 case STATE_RADIO_OFF
:
1247 rt2500pci_disable_radio(rt2x00dev
);
1249 case STATE_RADIO_RX_ON
:
1250 case STATE_RADIO_RX_OFF
:
1251 rt2500pci_toggle_rx(rt2x00dev
, state
);
1253 case STATE_DEEP_SLEEP
:
1257 retval
= rt2500pci_set_state(rt2x00dev
, state
);
1268 * TX descriptor initialization
1270 static void rt2500pci_write_tx_desc(struct rt2x00_dev
*rt2x00dev
,
1271 struct data_desc
*txd
,
1272 struct data_entry_desc
*desc
,
1273 struct ieee80211_hdr
*ieee80211hdr
,
1274 unsigned int length
,
1275 struct ieee80211_tx_control
*control
)
1280 * Start writing the descriptor words.
1282 rt2x00_desc_read(txd
, 2, &word
);
1283 rt2x00_set_field32(&word
, TXD_W2_IV_OFFSET
, IEEE80211_HEADER
);
1284 rt2x00_set_field32(&word
, TXD_W2_AIFS
, desc
->aifs
);
1285 rt2x00_set_field32(&word
, TXD_W2_CWMIN
, desc
->cw_min
);
1286 rt2x00_set_field32(&word
, TXD_W2_CWMAX
, desc
->cw_max
);
1287 rt2x00_desc_write(txd
, 2, word
);
1289 rt2x00_desc_read(txd
, 3, &word
);
1290 rt2x00_set_field32(&word
, TXD_W3_PLCP_SIGNAL
, desc
->signal
);
1291 rt2x00_set_field32(&word
, TXD_W3_PLCP_SERVICE
, desc
->service
);
1292 rt2x00_set_field32(&word
, TXD_W3_PLCP_LENGTH_LOW
, desc
->length_low
);
1293 rt2x00_set_field32(&word
, TXD_W3_PLCP_LENGTH_HIGH
, desc
->length_high
);
1294 rt2x00_desc_write(txd
, 3, word
);
1296 rt2x00_desc_read(txd
, 10, &word
);
1297 rt2x00_set_field32(&word
, TXD_W10_RTS
,
1298 test_bit(ENTRY_TXD_RTS_FRAME
, &desc
->flags
));
1299 rt2x00_desc_write(txd
, 10, word
);
1301 rt2x00_desc_read(txd
, 0, &word
);
1302 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 1);
1303 rt2x00_set_field32(&word
, TXD_W0_VALID
, 1);
1304 rt2x00_set_field32(&word
, TXD_W0_MORE_FRAG
,
1305 test_bit(ENTRY_TXD_MORE_FRAG
, &desc
->flags
));
1306 rt2x00_set_field32(&word
, TXD_W0_ACK
,
1307 !(control
->flags
& IEEE80211_TXCTL_NO_ACK
));
1308 rt2x00_set_field32(&word
, TXD_W0_TIMESTAMP
,
1309 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &desc
->flags
));
1310 rt2x00_set_field32(&word
, TXD_W0_OFDM
,
1311 test_bit(ENTRY_TXD_OFDM_RATE
, &desc
->flags
));
1312 rt2x00_set_field32(&word
, TXD_W0_CIPHER_OWNER
, 1);
1313 rt2x00_set_field32(&word
, TXD_W0_IFS
, desc
->ifs
);
1314 rt2x00_set_field32(&word
, TXD_W0_RETRY_MODE
,
1316 IEEE80211_TXCTL_LONG_RETRY_LIMIT
));
1317 rt2x00_set_field32(&word
, TXD_W0_DATABYTE_COUNT
, length
);
1318 rt2x00_set_field32(&word
, TXD_W0_CIPHER_ALG
, CIPHER_NONE
);
1319 rt2x00_desc_write(txd
, 0, word
);
1323 * TX data initialization
1325 static void rt2500pci_kick_tx_queue(struct rt2x00_dev
*rt2x00dev
,
1330 if (queue
== IEEE80211_TX_QUEUE_BEACON
) {
1331 rt2x00pci_register_read(rt2x00dev
, CSR14
, ®
);
1332 if (!rt2x00_get_field32(reg
, CSR14_BEACON_GEN
)) {
1333 rt2x00_set_field32(®
, CSR14_BEACON_GEN
, 1);
1334 rt2x00pci_register_write(rt2x00dev
, CSR14
, reg
);
1339 rt2x00pci_register_read(rt2x00dev
, TXCSR0
, ®
);
1340 if (queue
== IEEE80211_TX_QUEUE_DATA0
)
1341 rt2x00_set_field32(®
, TXCSR0_KICK_PRIO
, 1);
1342 else if (queue
== IEEE80211_TX_QUEUE_DATA1
)
1343 rt2x00_set_field32(®
, TXCSR0_KICK_TX
, 1);
1344 else if (queue
== IEEE80211_TX_QUEUE_AFTER_BEACON
)
1345 rt2x00_set_field32(®
, TXCSR0_KICK_ATIM
, 1);
1346 rt2x00pci_register_write(rt2x00dev
, TXCSR0
, reg
);
1350 * RX control handlers
1352 static int rt2500pci_fill_rxdone(struct data_entry
*entry
,
1353 int *signal
, int *rssi
, int *ofdm
, int *size
)
1355 struct data_desc
*rxd
= entry
->priv
;
1359 rt2x00_desc_read(rxd
, 0, &word0
);
1360 rt2x00_desc_read(rxd
, 2, &word2
);
1362 if (rt2x00_get_field32(word0
, RXD_W0_CRC_ERROR
) ||
1363 rt2x00_get_field32(word0
, RXD_W0_PHYSICAL_ERROR
) ||
1364 rt2x00_get_field32(word0
, RXD_W0_ICV_ERROR
))
1367 *signal
= rt2x00_get_field32(word2
, RXD_W2_SIGNAL
);
1368 *rssi
= rt2x00_get_field32(word2
, RXD_W2_RSSI
) -
1369 entry
->ring
->rt2x00dev
->rssi_offset
;
1370 *ofdm
= rt2x00_get_field32(word0
, RXD_W0_OFDM
);
1371 *size
= rt2x00_get_field32(word0
, RXD_W0_DATABYTE_COUNT
);
1377 * Interrupt functions.
1379 static void rt2500pci_txdone(struct rt2x00_dev
*rt2x00dev
, const int queue
)
1381 struct data_ring
*ring
= rt2x00lib_get_ring(rt2x00dev
, queue
);
1382 struct data_entry
*entry
;
1383 struct data_desc
*txd
;
1388 while (!rt2x00_ring_empty(ring
)) {
1389 entry
= rt2x00_get_data_entry_done(ring
);
1391 rt2x00_desc_read(txd
, 0, &word
);
1393 if (rt2x00_get_field32(word
, TXD_W0_OWNER_NIC
) ||
1394 !rt2x00_get_field32(word
, TXD_W0_VALID
))
1398 * Obtain the status about this packet.
1400 tx_status
= rt2x00_get_field32(word
, TXD_W0_RESULT
);
1401 retry
= rt2x00_get_field32(word
, TXD_W0_RETRY_COUNT
);
1403 rt2x00lib_txdone(entry
, tx_status
, retry
);
1406 * Make this entry available for reuse.
1409 rt2x00_set_field32(&word
, TXD_W0_VALID
, 0);
1410 rt2x00_desc_write(txd
, 0, word
);
1411 rt2x00_ring_index_done_inc(ring
);
1415 * If the data ring was full before the txdone handler
1416 * we must make sure the packet queue in the mac80211 stack
1417 * is reenabled when the txdone handler has finished.
1419 entry
= ring
->entry
;
1420 if (!rt2x00_ring_full(ring
))
1421 ieee80211_wake_queue(rt2x00dev
->hw
,
1422 entry
->tx_status
.control
.queue
);
1425 static irqreturn_t
rt2500pci_interrupt(int irq
, void *dev_instance
)
1427 struct rt2x00_dev
*rt2x00dev
= dev_instance
;
1431 * Get the interrupt sources & saved to local variable.
1432 * Write register value back to clear pending interrupts.
1434 rt2x00pci_register_read(rt2x00dev
, CSR7
, ®
);
1435 rt2x00pci_register_write(rt2x00dev
, CSR7
, reg
);
1440 if (!test_bit(DEVICE_ENABLED_RADIO
, &rt2x00dev
->flags
))
1444 * Handle interrupts, walk through all bits
1445 * and run the tasks, the bits are checked in order of
1450 * 1 - Beacon timer expired interrupt.
1452 if (rt2x00_get_field32(reg
, CSR7_TBCN_EXPIRE
))
1453 rt2x00lib_beacondone(rt2x00dev
);
1456 * 2 - Rx ring done interrupt.
1458 if (rt2x00_get_field32(reg
, CSR7_RXDONE
))
1459 rt2x00pci_rxdone(rt2x00dev
);
1462 * 3 - Atim ring transmit done interrupt.
1464 if (rt2x00_get_field32(reg
, CSR7_TXDONE_ATIMRING
))
1465 rt2500pci_txdone(rt2x00dev
, IEEE80211_TX_QUEUE_AFTER_BEACON
);
1468 * 4 - Priority ring transmit done interrupt.
1470 if (rt2x00_get_field32(reg
, CSR7_TXDONE_PRIORING
))
1471 rt2500pci_txdone(rt2x00dev
, IEEE80211_TX_QUEUE_DATA0
);
1474 * 5 - Tx ring transmit done interrupt.
1476 if (rt2x00_get_field32(reg
, CSR7_TXDONE_TXRING
))
1477 rt2500pci_txdone(rt2x00dev
, IEEE80211_TX_QUEUE_DATA1
);
1483 * Device probe functions.
1485 static int rt2500pci_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
1487 struct eeprom_93cx6 eeprom
;
1492 rt2x00pci_register_read(rt2x00dev
, CSR21
, ®
);
1494 eeprom
.data
= rt2x00dev
;
1495 eeprom
.register_read
= rt2500pci_eepromregister_read
;
1496 eeprom
.register_write
= rt2500pci_eepromregister_write
;
1497 eeprom
.width
= rt2x00_get_field32(reg
, CSR21_TYPE_93C46
) ?
1498 PCI_EEPROM_WIDTH_93C46
: PCI_EEPROM_WIDTH_93C66
;
1499 eeprom
.reg_data_in
= 0;
1500 eeprom
.reg_data_out
= 0;
1501 eeprom
.reg_data_clock
= 0;
1502 eeprom
.reg_chip_select
= 0;
1504 eeprom_93cx6_multiread(&eeprom
, EEPROM_BASE
, rt2x00dev
->eeprom
,
1505 EEPROM_SIZE
/ sizeof(u16
));
1508 * Start validation of the data that has been read.
1510 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
1511 if (!is_valid_ether_addr(mac
)) {
1512 DECLARE_MAC_BUF(macbuf
);
1514 random_ether_addr(mac
);
1515 EEPROM(rt2x00dev
, "MAC: %s\n",
1516 print_mac(macbuf
, mac
));
1519 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &word
);
1520 if (word
== 0xffff) {
1521 rt2x00_set_field16(&word
, EEPROM_ANTENNA_NUM
, 2);
1522 rt2x00_set_field16(&word
, EEPROM_ANTENNA_TX_DEFAULT
, 0);
1523 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RX_DEFAULT
, 0);
1524 rt2x00_set_field16(&word
, EEPROM_ANTENNA_LED_MODE
, 0);
1525 rt2x00_set_field16(&word
, EEPROM_ANTENNA_DYN_TXAGC
, 0);
1526 rt2x00_set_field16(&word
, EEPROM_ANTENNA_HARDWARE_RADIO
, 0);
1527 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RF_TYPE
, RF2522
);
1528 rt2x00_eeprom_write(rt2x00dev
, EEPROM_ANTENNA
, word
);
1529 EEPROM(rt2x00dev
, "Antenna: 0x%04x\n", word
);
1532 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &word
);
1533 if (word
== 0xffff) {
1534 rt2x00_set_field16(&word
, EEPROM_NIC_CARDBUS_ACCEL
, 0);
1535 rt2x00_set_field16(&word
, EEPROM_NIC_DYN_BBP_TUNE
, 0);
1536 rt2x00_set_field16(&word
, EEPROM_NIC_CCK_TX_POWER
, 0);
1537 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC
, word
);
1538 EEPROM(rt2x00dev
, "NIC: 0x%04x\n", word
);
1541 rt2x00_eeprom_read(rt2x00dev
, EEPROM_CALIBRATE_OFFSET
, &word
);
1542 if (word
== 0xffff) {
1543 rt2x00_set_field16(&word
, EEPROM_CALIBRATE_OFFSET_RSSI
,
1544 DEFAULT_RSSI_OFFSET
);
1545 rt2x00_eeprom_write(rt2x00dev
, EEPROM_CALIBRATE_OFFSET
, word
);
1546 EEPROM(rt2x00dev
, "Calibrate offset: 0x%04x\n", word
);
1552 static int rt2500pci_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
1559 * Read EEPROM word for configuration.
1561 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
1564 * Identify RF chipset.
1566 value
= rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RF_TYPE
);
1567 rt2x00pci_register_read(rt2x00dev
, CSR0
, ®
);
1568 rt2x00_set_chip(rt2x00dev
, RT2560
, value
, reg
);
1570 if (!rt2x00_rf(&rt2x00dev
->chip
, RF2522
) &&
1571 !rt2x00_rf(&rt2x00dev
->chip
, RF2523
) &&
1572 !rt2x00_rf(&rt2x00dev
->chip
, RF2524
) &&
1573 !rt2x00_rf(&rt2x00dev
->chip
, RF2525
) &&
1574 !rt2x00_rf(&rt2x00dev
->chip
, RF2525E
) &&
1575 !rt2x00_rf(&rt2x00dev
->chip
, RF5222
)) {
1576 ERROR(rt2x00dev
, "Invalid RF chipset detected.\n");
1581 * Identify default antenna configuration.
1583 rt2x00dev
->hw
->conf
.antenna_sel_tx
=
1584 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TX_DEFAULT
);
1585 rt2x00dev
->hw
->conf
.antenna_sel_rx
=
1586 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RX_DEFAULT
);
1589 * Store led mode, for correct led behaviour.
1591 rt2x00dev
->led_mode
=
1592 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_LED_MODE
);
1595 * Detect if this device has an hardware controlled radio.
1597 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_HARDWARE_RADIO
))
1598 __set_bit(DEVICE_SUPPORT_HW_BUTTON
, &rt2x00dev
->flags
);
1601 * Check if the BBP tuning should be enabled.
1603 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
1605 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_DYN_BBP_TUNE
))
1606 __set_bit(CONFIG_DISABLE_LINK_TUNING
, &rt2x00dev
->flags
);
1609 * Read the RSSI <-> dBm offset information.
1611 rt2x00_eeprom_read(rt2x00dev
, EEPROM_CALIBRATE_OFFSET
, &eeprom
);
1612 rt2x00dev
->rssi_offset
=
1613 rt2x00_get_field16(eeprom
, EEPROM_CALIBRATE_OFFSET_RSSI
);
1619 * RF value list for RF2522
1622 static const struct rf_channel rf_vals_bg_2522
[] = {
1623 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1624 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1625 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1626 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1627 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1628 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1629 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1630 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1631 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1632 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1633 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1634 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1635 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1636 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1640 * RF value list for RF2523
1643 static const struct rf_channel rf_vals_bg_2523
[] = {
1644 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1645 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1646 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1647 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1648 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1649 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1650 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1651 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1652 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1653 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1654 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1655 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1656 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1657 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1661 * RF value list for RF2524
1664 static const struct rf_channel rf_vals_bg_2524
[] = {
1665 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1666 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1667 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1668 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1669 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1670 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1671 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1672 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1673 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1674 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1675 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1676 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1677 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1678 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1682 * RF value list for RF2525
1685 static const struct rf_channel rf_vals_bg_2525
[] = {
1686 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1687 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1688 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1689 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1690 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1691 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1692 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1693 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1694 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1695 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1696 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1697 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1698 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1699 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1703 * RF value list for RF2525e
1706 static const struct rf_channel rf_vals_bg_2525e
[] = {
1707 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1708 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1709 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1710 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1711 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1712 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1713 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1714 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1715 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1716 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1717 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1718 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1719 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1720 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1724 * RF value list for RF5222
1725 * Supports: 2.4 GHz & 5.2 GHz
1727 static const struct rf_channel rf_vals_5222
[] = {
1728 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1729 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1730 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1731 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1732 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1733 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1734 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1735 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1736 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1737 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1738 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1739 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1740 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1741 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1743 /* 802.11 UNI / HyperLan 2 */
1744 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1745 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1746 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1747 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1748 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1749 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1750 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1751 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1753 /* 802.11 HyperLan 2 */
1754 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1755 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1756 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1757 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1758 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1759 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1760 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1761 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1762 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1763 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1766 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1767 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1768 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1769 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1770 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1773 static void rt2500pci_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
1775 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
1780 * Initialize all hw fields.
1782 rt2x00dev
->hw
->flags
=
1783 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
1784 IEEE80211_HW_MONITOR_DURING_OPER
|
1785 IEEE80211_HW_NO_PROBE_FILTERING
;
1786 rt2x00dev
->hw
->extra_tx_headroom
= 0;
1787 rt2x00dev
->hw
->max_signal
= MAX_SIGNAL
;
1788 rt2x00dev
->hw
->max_rssi
= MAX_RX_SSI
;
1789 rt2x00dev
->hw
->queues
= 2;
1791 SET_IEEE80211_DEV(rt2x00dev
->hw
, &rt2x00dev_pci(rt2x00dev
)->dev
);
1792 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
1793 rt2x00_eeprom_addr(rt2x00dev
,
1794 EEPROM_MAC_ADDR_0
));
1797 * Convert tx_power array in eeprom.
1799 txpower
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_START
);
1800 for (i
= 0; i
< 14; i
++)
1801 txpower
[i
] = TXPOWER_FROM_DEV(txpower
[i
]);
1804 * Initialize hw_mode information.
1806 spec
->num_modes
= 2;
1807 spec
->num_rates
= 12;
1808 spec
->tx_power_a
= NULL
;
1809 spec
->tx_power_bg
= txpower
;
1810 spec
->tx_power_default
= DEFAULT_TXPOWER
;
1812 if (rt2x00_rf(&rt2x00dev
->chip
, RF2522
)) {
1813 spec
->num_channels
= ARRAY_SIZE(rf_vals_bg_2522
);
1814 spec
->channels
= rf_vals_bg_2522
;
1815 } else if (rt2x00_rf(&rt2x00dev
->chip
, RF2523
)) {
1816 spec
->num_channels
= ARRAY_SIZE(rf_vals_bg_2523
);
1817 spec
->channels
= rf_vals_bg_2523
;
1818 } else if (rt2x00_rf(&rt2x00dev
->chip
, RF2524
)) {
1819 spec
->num_channels
= ARRAY_SIZE(rf_vals_bg_2524
);
1820 spec
->channels
= rf_vals_bg_2524
;
1821 } else if (rt2x00_rf(&rt2x00dev
->chip
, RF2525
)) {
1822 spec
->num_channels
= ARRAY_SIZE(rf_vals_bg_2525
);
1823 spec
->channels
= rf_vals_bg_2525
;
1824 } else if (rt2x00_rf(&rt2x00dev
->chip
, RF2525E
)) {
1825 spec
->num_channels
= ARRAY_SIZE(rf_vals_bg_2525e
);
1826 spec
->channels
= rf_vals_bg_2525e
;
1827 } else if (rt2x00_rf(&rt2x00dev
->chip
, RF5222
)) {
1828 spec
->num_channels
= ARRAY_SIZE(rf_vals_5222
);
1829 spec
->channels
= rf_vals_5222
;
1830 spec
->num_modes
= 3;
1834 static int rt2500pci_probe_hw(struct rt2x00_dev
*rt2x00dev
)
1839 * Allocate eeprom data.
1841 retval
= rt2500pci_validate_eeprom(rt2x00dev
);
1845 retval
= rt2500pci_init_eeprom(rt2x00dev
);
1850 * Initialize hw specifications.
1852 rt2500pci_probe_hw_mode(rt2x00dev
);
1855 * This device requires the beacon ring
1857 __set_bit(REQUIRE_BEACON_RING
, &rt2x00dev
->flags
);
1860 * Set the rssi offset.
1862 rt2x00dev
->rssi_offset
= DEFAULT_RSSI_OFFSET
;
1868 * IEEE80211 stack callback functions.
1870 static int rt2500pci_set_retry_limit(struct ieee80211_hw
*hw
,
1871 u32 short_retry
, u32 long_retry
)
1873 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1876 rt2x00pci_register_read(rt2x00dev
, CSR11
, ®
);
1877 rt2x00_set_field32(®
, CSR11_LONG_RETRY
, long_retry
);
1878 rt2x00_set_field32(®
, CSR11_SHORT_RETRY
, short_retry
);
1879 rt2x00pci_register_write(rt2x00dev
, CSR11
, reg
);
1884 static u64
rt2500pci_get_tsf(struct ieee80211_hw
*hw
)
1886 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1890 rt2x00pci_register_read(rt2x00dev
, CSR17
, ®
);
1891 tsf
= (u64
) rt2x00_get_field32(reg
, CSR17_HIGH_TSFTIMER
) << 32;
1892 rt2x00pci_register_read(rt2x00dev
, CSR16
, ®
);
1893 tsf
|= rt2x00_get_field32(reg
, CSR16_LOW_TSFTIMER
);
1898 static void rt2500pci_reset_tsf(struct ieee80211_hw
*hw
)
1900 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1902 rt2x00pci_register_write(rt2x00dev
, CSR16
, 0);
1903 rt2x00pci_register_write(rt2x00dev
, CSR17
, 0);
1906 static int rt2500pci_tx_last_beacon(struct ieee80211_hw
*hw
)
1908 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1911 rt2x00pci_register_read(rt2x00dev
, CSR15
, ®
);
1912 return rt2x00_get_field32(reg
, CSR15_BEACON_SENT
);
1915 static const struct ieee80211_ops rt2500pci_mac80211_ops
= {
1917 .add_interface
= rt2x00mac_add_interface
,
1918 .remove_interface
= rt2x00mac_remove_interface
,
1919 .config
= rt2x00mac_config
,
1920 .config_interface
= rt2x00mac_config_interface
,
1921 .set_multicast_list
= rt2x00mac_set_multicast_list
,
1922 .get_stats
= rt2x00mac_get_stats
,
1923 .set_retry_limit
= rt2500pci_set_retry_limit
,
1924 .conf_tx
= rt2x00mac_conf_tx
,
1925 .get_tx_stats
= rt2x00mac_get_tx_stats
,
1926 .get_tsf
= rt2500pci_get_tsf
,
1927 .reset_tsf
= rt2500pci_reset_tsf
,
1928 .beacon_update
= rt2x00pci_beacon_update
,
1929 .tx_last_beacon
= rt2500pci_tx_last_beacon
,
1932 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops
= {
1933 .irq_handler
= rt2500pci_interrupt
,
1934 .probe_hw
= rt2500pci_probe_hw
,
1935 .initialize
= rt2x00pci_initialize
,
1936 .uninitialize
= rt2x00pci_uninitialize
,
1937 .set_device_state
= rt2500pci_set_device_state
,
1938 #ifdef CONFIG_RT2500PCI_RFKILL
1939 .rfkill_poll
= rt2500pci_rfkill_poll
,
1940 #endif /* CONFIG_RT2500PCI_RFKILL */
1941 .link_stats
= rt2500pci_link_stats
,
1942 .reset_tuner
= rt2500pci_reset_tuner
,
1943 .link_tuner
= rt2500pci_link_tuner
,
1944 .write_tx_desc
= rt2500pci_write_tx_desc
,
1945 .write_tx_data
= rt2x00pci_write_tx_data
,
1946 .kick_tx_queue
= rt2500pci_kick_tx_queue
,
1947 .fill_rxdone
= rt2500pci_fill_rxdone
,
1948 .config_mac_addr
= rt2500pci_config_mac_addr
,
1949 .config_bssid
= rt2500pci_config_bssid
,
1950 .config_packet_filter
= rt2500pci_config_packet_filter
,
1951 .config_type
= rt2500pci_config_type
,
1952 .config
= rt2500pci_config
,
1955 static const struct rt2x00_ops rt2500pci_ops
= {
1957 .rxd_size
= RXD_DESC_SIZE
,
1958 .txd_size
= TXD_DESC_SIZE
,
1959 .eeprom_size
= EEPROM_SIZE
,
1961 .lib
= &rt2500pci_rt2x00_ops
,
1962 .hw
= &rt2500pci_mac80211_ops
,
1963 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1964 .debugfs
= &rt2500pci_rt2x00debug
,
1965 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1969 * RT2500pci module information.
1971 static struct pci_device_id rt2500pci_device_table
[] = {
1972 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops
) },
1976 MODULE_AUTHOR(DRV_PROJECT
);
1977 MODULE_VERSION(DRV_VERSION
);
1978 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1979 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1980 MODULE_DEVICE_TABLE(pci
, rt2500pci_device_table
);
1981 MODULE_LICENSE("GPL");
1983 static struct pci_driver rt2500pci_driver
= {
1985 .id_table
= rt2500pci_device_table
,
1986 .probe
= rt2x00pci_probe
,
1987 .remove
= __devexit_p(rt2x00pci_remove
),
1988 .suspend
= rt2x00pci_suspend
,
1989 .resume
= rt2x00pci_resume
,
1992 static int __init
rt2500pci_init(void)
1994 return pci_register_driver(&rt2500pci_driver
);
1997 static void __exit
rt2500pci_exit(void)
1999 pci_unregister_driver(&rt2500pci_driver
);
2002 module_init(rt2500pci_init
);
2003 module_exit(rt2500pci_exit
);