drivers/net/wireless/rt2x00/rt2500usb.h

   1 /*
   2         Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2500usb
  23         Abstract: Data structures and registers for the rt2500usb module.
  24         Supported chipsets: RT2570.
  25  */
  26
  27 #ifndef RT2500USB_H
  28 #define RT2500USB_H
  29
  30 /*
  31  * RF chip defines.
  32  */
  33 #define RF2522                          0x0000
  34 #define RF2523                          0x0001
  35 #define RF2524                          0x0002
  36 #define RF2525                          0x0003
  37 #define RF2525E                         0x0005
  38 #define RF5222                          0x0010
  39
  40 /*
  41  * RT2570 version
  42  */
  43 #define RT2570_VERSION_B                2
  44 #define RT2570_VERSION_C                3
  45 #define RT2570_VERSION_D                4
  46
  47 /*
  48  * Signal information.
  49  * Default offset is required for RSSI <-> dBm conversion.
  50  */
  51 #define DEFAULT_RSSI_OFFSET             120
  52
  53 /*
  54  * Register layout information.
  55  */
  56 #define CSR_REG_BASE                    0x0400
  57 #define CSR_REG_SIZE                    0x0100
  58 #define EEPROM_BASE                     0x0000
  59 #define EEPROM_SIZE                     0x006a
  60 #define BBP_BASE                        0x0000
  61 #define BBP_SIZE                        0x0060
  62 #define RF_BASE                         0x0004
  63 #define RF_SIZE                         0x0010
  64
  65 /*
  66  * Number of TX queues.
  67  */
  68 #define NUM_TX_QUEUES                   2
  69
  70 /*
  71  * Control/Status Registers(CSR).
  72  * Some values are set in TU, whereas 1 TU == 1024 us.
  73  */
  74
  75 /*
  76  * MAC_CSR0: ASIC revision number.
  77  */
  78 #define MAC_CSR0                        0x0400
  79
  80 /*
  81  * MAC_CSR1: System control.
  82  * SOFT_RESET: Software reset, 1: reset, 0: normal.
  83  * BBP_RESET: Hardware reset, 1: reset, 0, release.
  84  * HOST_READY: Host ready after initialization.
  85  */
  86 #define MAC_CSR1                        0x0402
  87 #define MAC_CSR1_SOFT_RESET             FIELD16(0x00000001)
  88 #define MAC_CSR1_BBP_RESET              FIELD16(0x00000002)
  89 #define MAC_CSR1_HOST_READY             FIELD16(0x00000004)
  90
  91 /*
  92  * MAC_CSR2: STA MAC register 0.
  93  */
  94 #define MAC_CSR2                        0x0404
  95 #define MAC_CSR2_BYTE0                  FIELD16(0x00ff)
  96 #define MAC_CSR2_BYTE1                  FIELD16(0xff00)
  97
  98 /*
  99  * MAC_CSR3: STA MAC register 1.
 100  */
 101 #define MAC_CSR3                        0x0406
 102 #define MAC_CSR3_BYTE2                  FIELD16(0x00ff)
 103 #define MAC_CSR3_BYTE3                  FIELD16(0xff00)
 104
 105 /*
 106  * MAC_CSR4: STA MAC register 2.
 107  */
 108 #define MAC_CSR4                        0X0408
 109 #define MAC_CSR4_BYTE4                  FIELD16(0x00ff)
 110 #define MAC_CSR4_BYTE5                  FIELD16(0xff00)
 111
 112 /*
 113  * MAC_CSR5: BSSID register 0.
 114  */
 115 #define MAC_CSR5                        0x040a
 116 #define MAC_CSR5_BYTE0                  FIELD16(0x00ff)
 117 #define MAC_CSR5_BYTE1                  FIELD16(0xff00)
 118
 119 /*
 120  * MAC_CSR6: BSSID register 1.
 121  */
 122 #define MAC_CSR6                        0x040c
 123 #define MAC_CSR6_BYTE2                  FIELD16(0x00ff)
 124 #define MAC_CSR6_BYTE3                  FIELD16(0xff00)
 125
 126 /*
 127  * MAC_CSR7: BSSID register 2.
 128  */
 129 #define MAC_CSR7                        0x040e
 130 #define MAC_CSR7_BYTE4                  FIELD16(0x00ff)
 131 #define MAC_CSR7_BYTE5                  FIELD16(0xff00)
 132
 133 /*
 134  * MAC_CSR8: Max frame length.
 135  */
 136 #define MAC_CSR8                        0x0410
 137 #define MAC_CSR8_MAX_FRAME_UNIT         FIELD16(0x0fff)
 138
 139 /*
 140  * Misc MAC_CSR registers.
 141  * MAC_CSR9: Timer control.
 142  * MAC_CSR10: Slot time.
 143  * MAC_CSR11: SIFS.
 144  * MAC_CSR12: EIFS.
 145  * MAC_CSR13: Power mode0.
 146  * MAC_CSR14: Power mode1.
 147  * MAC_CSR15: Power saving transition0
 148  * MAC_CSR16: Power saving transition1
 149  */
 150 #define MAC_CSR9                        0x0412
 151 #define MAC_CSR10                       0x0414
 152 #define MAC_CSR11                       0x0416
 153 #define MAC_CSR12                       0x0418
 154 #define MAC_CSR13                       0x041a
 155 #define MAC_CSR14                       0x041c
 156 #define MAC_CSR15                       0x041e
 157 #define MAC_CSR16                       0x0420
 158
 159 /*
 160  * MAC_CSR17: Manual power control / status register.
 161  * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
 162  * SET_STATE: Set state. Write 1 to trigger, self cleared.
 163  * BBP_DESIRE_STATE: BBP desired state.
 164  * RF_DESIRE_STATE: RF desired state.
 165  * BBP_CURRENT_STATE: BBP current state.
 166  * RF_CURRENT_STATE: RF current state.
 167  * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
 168  */
 169 #define MAC_CSR17                       0x0422
 170 #define MAC_CSR17_SET_STATE             FIELD16(0x0001)
 171 #define MAC_CSR17_BBP_DESIRE_STATE      FIELD16(0x0006)
 172 #define MAC_CSR17_RF_DESIRE_STATE       FIELD16(0x0018)
 173 #define MAC_CSR17_BBP_CURR_STATE        FIELD16(0x0060)
 174 #define MAC_CSR17_RF_CURR_STATE         FIELD16(0x0180)
 175 #define MAC_CSR17_PUT_TO_SLEEP          FIELD16(0x0200)
 176
 177 /*
 178  * MAC_CSR18: Wakeup timer register.
 179  * DELAY_AFTER_BEACON: Delay after Tbcn expired in units of 1/16 TU.
 180  * BEACONS_BEFORE_WAKEUP: Number of beacon before wakeup.
 181  * AUTO_WAKE: Enable auto wakeup / sleep mechanism.
 182  */
 183 #define MAC_CSR18                       0x0424
 184 #define MAC_CSR18_DELAY_AFTER_BEACON    FIELD16(0x00ff)
 185 #define MAC_CSR18_BEACONS_BEFORE_WAKEUP FIELD16(0x7f00)
 186 #define MAC_CSR18_AUTO_WAKE             FIELD16(0x8000)
 187
 188 /*
 189  * MAC_CSR19: GPIO control register.
 190  */
 191 #define MAC_CSR19                       0x0426
 192 #define MAC_CSR19_BIT0                  FIELD16(0x0001)
 193 #define MAC_CSR19_BIT1                  FIELD16(0x0002)
 194 #define MAC_CSR19_BIT2                  FIELD16(0x0004)
 195 #define MAC_CSR19_BIT3                  FIELD16(0x0008)
 196 #define MAC_CSR19_BIT4                  FIELD16(0x0010)
 197 #define MAC_CSR19_BIT5                  FIELD16(0x0020)
 198 #define MAC_CSR19_BIT6                  FIELD16(0x0040)
 199 #define MAC_CSR19_BIT7                  FIELD16(0x0080)
 200 #define MAC_CSR19_BIT8                  FIELD16(0x0100)
 201
 202 /*
 203  * MAC_CSR20: LED control register.
 204  * ACTIVITY: 0: idle, 1: active.
 205  * LINK: 0: linkoff, 1: linkup.
 206  * ACTIVITY_POLARITY: 0: active low, 1: active high.
 207  */
 208 #define MAC_CSR20                       0x0428
 209 #define MAC_CSR20_ACTIVITY              FIELD16(0x0001)
 210 #define MAC_CSR20_LINK                  FIELD16(0x0002)
 211 #define MAC_CSR20_ACTIVITY_POLARITY     FIELD16(0x0004)
 212
 213 /*
 214  * MAC_CSR21: LED control register.
 215  * ON_PERIOD: On period, default 70ms.
 216  * OFF_PERIOD: Off period, default 30ms.
 217  */
 218 #define MAC_CSR21                       0x042a
 219 #define MAC_CSR21_ON_PERIOD             FIELD16(0x00ff)
 220 #define MAC_CSR21_OFF_PERIOD            FIELD16(0xff00)
 221
 222 /*
 223  * MAC_CSR22: Collision window control register.
 224  */
 225 #define MAC_CSR22                       0x042c
 226
 227 /*
 228  * Transmit related CSRs.
 229  * Some values are set in TU, whereas 1 TU == 1024 us.
 230  */
 231
 232 /*
 233  * TXRX_CSR0: Security control register.
 234  */
 235 #define TXRX_CSR0                       0x0440
 236 #define TXRX_CSR0_ALGORITHM             FIELD16(0x0007)
 237 #define TXRX_CSR0_IV_OFFSET             FIELD16(0x01f8)
 238 #define TXRX_CSR0_KEY_ID                FIELD16(0x1e00)
 239
 240 /*
 241  * TXRX_CSR1: TX configuration.
 242  * ACK_TIMEOUT: ACK Timeout in unit of 1-us.
 243  * TSF_OFFSET: TSF offset in MAC header.
 244  * AUTO_SEQUENCE: Let ASIC control frame sequence number.
 245  */
 246 #define TXRX_CSR1                       0x0442
 247 #define TXRX_CSR1_ACK_TIMEOUT           FIELD16(0x00ff)
 248 #define TXRX_CSR1_TSF_OFFSET            FIELD16(0x7f00)
 249 #define TXRX_CSR1_AUTO_SEQUENCE         FIELD16(0x8000)
 250
 251 /*
 252  * TXRX_CSR2: RX control.
 253  * DISABLE_RX: Disable rx engine.
 254  * DROP_CRC: Drop crc error.
 255  * DROP_PHYSICAL: Drop physical error.
 256  * DROP_CONTROL: Drop control frame.
 257  * DROP_NOT_TO_ME: Drop not to me unicast frame.
 258  * DROP_TODS: Drop frame tods bit is true.
 259  * DROP_VERSION_ERROR: Drop version error frame.
 260  * DROP_MCAST: Drop multicast frames.
 261  * DROP_BCAST: Drop broadcast frames.
 262  */
 263 #define TXRX_CSR2                       0x0444
 264 #define TXRX_CSR2_DISABLE_RX            FIELD16(0x0001)
 265 #define TXRX_CSR2_DROP_CRC              FIELD16(0x0002)
 266 #define TXRX_CSR2_DROP_PHYSICAL         FIELD16(0x0004)
 267 #define TXRX_CSR2_DROP_CONTROL          FIELD16(0x0008)
 268 #define TXRX_CSR2_DROP_NOT_TO_ME        FIELD16(0x0010)
 269 #define TXRX_CSR2_DROP_TODS             FIELD16(0x0020)
 270 #define TXRX_CSR2_DROP_VERSION_ERROR    FIELD16(0x0040)
 271 #define TXRX_CSR2_DROP_MULTICAST        FIELD16(0x0200)
 272 #define TXRX_CSR2_DROP_BROADCAST        FIELD16(0x0400)
 273
 274 /*
 275  * RX BBP ID registers
 276  * TXRX_CSR3: CCK RX BBP ID.
 277  * TXRX_CSR4: OFDM RX BBP ID.
 278  */
 279 #define TXRX_CSR3                       0x0446
 280 #define TXRX_CSR4                       0x0448
 281
 282 /*
 283  * TXRX_CSR5: CCK TX BBP ID0.
 284  */
 285 #define TXRX_CSR5                       0x044a
 286 #define TXRX_CSR5_BBP_ID0               FIELD16(0x007f)
 287 #define TXRX_CSR5_BBP_ID0_VALID         FIELD16(0x0080)
 288 #define TXRX_CSR5_BBP_ID1               FIELD16(0x7f00)
 289 #define TXRX_CSR5_BBP_ID1_VALID         FIELD16(0x8000)
 290
 291 /*
 292  * TXRX_CSR6: CCK TX BBP ID1.
 293  */
 294 #define TXRX_CSR6                       0x044c
 295 #define TXRX_CSR6_BBP_ID0               FIELD16(0x007f)
 296 #define TXRX_CSR6_BBP_ID0_VALID         FIELD16(0x0080)
 297 #define TXRX_CSR6_BBP_ID1               FIELD16(0x7f00)
 298 #define TXRX_CSR6_BBP_ID1_VALID         FIELD16(0x8000)
 299
 300 /*
 301  * TXRX_CSR7: OFDM TX BBP ID0.
 302  */
 303 #define TXRX_CSR7                       0x044e
 304 #define TXRX_CSR7_BBP_ID0               FIELD16(0x007f)
 305 #define TXRX_CSR7_BBP_ID0_VALID         FIELD16(0x0080)
 306 #define TXRX_CSR7_BBP_ID1               FIELD16(0x7f00)
 307 #define TXRX_CSR7_BBP_ID1_VALID         FIELD16(0x8000)
 308
 309 /*
 310  * TXRX_CSR8: OFDM TX BBP ID1.
 311  */
 312 #define TXRX_CSR8                       0x0450
 313 #define TXRX_CSR8_BBP_ID0               FIELD16(0x007f)
 314 #define TXRX_CSR8_BBP_ID0_VALID         FIELD16(0x0080)
 315 #define TXRX_CSR8_BBP_ID1               FIELD16(0x7f00)
 316 #define TXRX_CSR8_BBP_ID1_VALID         FIELD16(0x8000)
 317
 318 /*
 319  * TXRX_CSR9: TX ACK time-out.
 320  */
 321 #define TXRX_CSR9                       0x0452
 322
 323 /*
 324  * TXRX_CSR10: Auto responder control.
 325  */
 326 #define TXRX_CSR10                      0x0454
 327 #define TXRX_CSR10_AUTORESPOND_PREAMBLE FIELD16(0x0004)
 328
 329 /*
 330  * TXRX_CSR11: Auto responder basic rate.
 331  */
 332 #define TXRX_CSR11                      0x0456
 333
 334 /*
 335  * ACK/CTS time registers.
 336  */
 337 #define TXRX_CSR12                      0x0458
 338 #define TXRX_CSR13                      0x045a
 339 #define TXRX_CSR14                      0x045c
 340 #define TXRX_CSR15                      0x045e
 341 #define TXRX_CSR16                      0x0460
 342 #define TXRX_CSR17                      0x0462
 343
 344 /*
 345  * TXRX_CSR18: Synchronization control register.
 346  */
 347 #define TXRX_CSR18                      0x0464
 348 #define TXRX_CSR18_OFFSET               FIELD16(0x000f)
 349 #define TXRX_CSR18_INTERVAL             FIELD16(0xfff0)
 350
 351 /*
 352  * TXRX_CSR19: Synchronization control register.
 353  * TSF_COUNT: Enable TSF auto counting.
 354  * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
 355  * TBCN: Enable Tbcn with reload value.
 356  * BEACON_GEN: Enable beacon generator.
 357  */
 358 #define TXRX_CSR19                      0x0466
 359 #define TXRX_CSR19_TSF_COUNT            FIELD16(0x0001)
 360 #define TXRX_CSR19_TSF_SYNC             FIELD16(0x0006)
 361 #define TXRX_CSR19_TBCN                 FIELD16(0x0008)
 362 #define TXRX_CSR19_BEACON_GEN           FIELD16(0x0010)
 363
 364 /*
 365  * TXRX_CSR20: Tx BEACON offset time control register.
 366  * OFFSET: In units of usec.
 367  * BCN_EXPECT_WINDOW: Default: 2^CWmin
 368  */
 369 #define TXRX_CSR20                      0x0468
 370 #define TXRX_CSR20_OFFSET               FIELD16(0x1fff)
 371 #define TXRX_CSR20_BCN_EXPECT_WINDOW    FIELD16(0xe000)
 372
 373 /*
 374  * TXRX_CSR21
 375  */
 376 #define TXRX_CSR21                      0x046a
 377
 378 /*
 379  * Encryption related CSRs.
 380  *
 381  */
 382
 383 /*
 384  * SEC_CSR0: Shared key 0, word 0
 385  * SEC_CSR1: Shared key 0, word 1
 386  * SEC_CSR2: Shared key 0, word 2
 387  * SEC_CSR3: Shared key 0, word 3
 388  * SEC_CSR4: Shared key 0, word 4
 389  * SEC_CSR5: Shared key 0, word 5
 390  * SEC_CSR6: Shared key 0, word 6
 391  * SEC_CSR7: Shared key 0, word 7
 392  */
 393 #define SEC_CSR0                        0x0480
 394 #define SEC_CSR1                        0x0482
 395 #define SEC_CSR2                        0x0484
 396 #define SEC_CSR3                        0x0486
 397 #define SEC_CSR4                        0x0488
 398 #define SEC_CSR5                        0x048a
 399 #define SEC_CSR6                        0x048c
 400 #define SEC_CSR7                        0x048e
 401
 402 /*
 403  * SEC_CSR8: Shared key 1, word 0
 404  * SEC_CSR9: Shared key 1, word 1
 405  * SEC_CSR10: Shared key 1, word 2
 406  * SEC_CSR11: Shared key 1, word 3
 407  * SEC_CSR12: Shared key 1, word 4
 408  * SEC_CSR13: Shared key 1, word 5
 409  * SEC_CSR14: Shared key 1, word 6
 410  * SEC_CSR15: Shared key 1, word 7
 411  */
 412 #define SEC_CSR8                        0x0490
 413 #define SEC_CSR9                        0x0492
 414 #define SEC_CSR10                       0x0494
 415 #define SEC_CSR11                       0x0496
 416 #define SEC_CSR12                       0x0498
 417 #define SEC_CSR13                       0x049a
 418 #define SEC_CSR14                       0x049c
 419 #define SEC_CSR15                       0x049e
 420
 421 /*
 422  * SEC_CSR16: Shared key 2, word 0
 423  * SEC_CSR17: Shared key 2, word 1
 424  * SEC_CSR18: Shared key 2, word 2
 425  * SEC_CSR19: Shared key 2, word 3
 426  * SEC_CSR20: Shared key 2, word 4
 427  * SEC_CSR21: Shared key 2, word 5
 428  * SEC_CSR22: Shared key 2, word 6
 429  * SEC_CSR23: Shared key 2, word 7
 430  */
 431 #define SEC_CSR16                       0x04a0
 432 #define SEC_CSR17                       0x04a2
 433 #define SEC_CSR18                       0X04A4
 434 #define SEC_CSR19                       0x04a6
 435 #define SEC_CSR20                       0x04a8
 436 #define SEC_CSR21                       0x04aa
 437 #define SEC_CSR22                       0x04ac
 438 #define SEC_CSR23                       0x04ae
 439
 440 /*
 441  * SEC_CSR24: Shared key 3, word 0
 442  * SEC_CSR25: Shared key 3, word 1
 443  * SEC_CSR26: Shared key 3, word 2
 444  * SEC_CSR27: Shared key 3, word 3
 445  * SEC_CSR28: Shared key 3, word 4
 446  * SEC_CSR29: Shared key 3, word 5
 447  * SEC_CSR30: Shared key 3, word 6
 448  * SEC_CSR31: Shared key 3, word 7
 449  */
 450 #define SEC_CSR24                       0x04b0
 451 #define SEC_CSR25                       0x04b2
 452 #define SEC_CSR26                       0x04b4
 453 #define SEC_CSR27                       0x04b6
 454 #define SEC_CSR28                       0x04b8
 455 #define SEC_CSR29                       0x04ba
 456 #define SEC_CSR30                       0x04bc
 457 #define SEC_CSR31                       0x04be
 458
 459 #define KEY_ENTRY(__idx) \
 460         ( SEC_CSR0 + ((__idx) * 16) )
 461
 462 /*
 463  * PHY control registers.
 464  */
 465
 466 /*
 467  * PHY_CSR0: RF switching timing control.
 468  */
 469 #define PHY_CSR0                        0x04c0
 470
 471 /*
 472  * PHY_CSR1: TX PA configuration.
 473  */
 474 #define PHY_CSR1                        0x04c2
 475
 476 /*
 477  * MAC configuration registers.
 478  */
 479
 480 /*
 481  * PHY_CSR2: TX MAC configuration.
 482  * NOTE: Both register fields are complete dummy,
 483  * documentation and legacy drivers are unclear un
 484  * what this register means or what fields exists.
 485  */
 486 #define PHY_CSR2                        0x04c4
 487 #define PHY_CSR2_LNA                    FIELD16(0x0002)
 488 #define PHY_CSR2_LNA_MODE               FIELD16(0x3000)
 489
 490 /*
 491  * PHY_CSR3: RX MAC configuration.
 492  */
 493 #define PHY_CSR3                        0x04c6
 494
 495 /*
 496  * PHY_CSR4: Interface configuration.
 497  */
 498 #define PHY_CSR4                        0x04c8
 499 #define PHY_CSR4_LOW_RF_LE              FIELD16(0x0001)
 500
 501 /*
 502  * BBP pre-TX registers.
 503  * PHY_CSR5: BBP pre-TX CCK.
 504  */
 505 #define PHY_CSR5                        0x04ca
 506 #define PHY_CSR5_CCK                    FIELD16(0x0003)
 507 #define PHY_CSR5_CCK_FLIP               FIELD16(0x0004)
 508
 509 /*
 510  * BBP pre-TX registers.
 511  * PHY_CSR6: BBP pre-TX OFDM.
 512  */
 513 #define PHY_CSR6                        0x04cc
 514 #define PHY_CSR6_OFDM                   FIELD16(0x0003)
 515 #define PHY_CSR6_OFDM_FLIP              FIELD16(0x0004)
 516
 517 /*
 518  * PHY_CSR7: BBP access register 0.
 519  * BBP_DATA: BBP data.
 520  * BBP_REG_ID: BBP register ID.
 521  * BBP_READ_CONTROL: 0: write, 1: read.
 522  */
 523 #define PHY_CSR7                        0x04ce
 524 #define PHY_CSR7_DATA                   FIELD16(0x00ff)
 525 #define PHY_CSR7_REG_ID                 FIELD16(0x7f00)
 526 #define PHY_CSR7_READ_CONTROL           FIELD16(0x8000)
 527
 528 /*
 529  * PHY_CSR8: BBP access register 1.
 530  * BBP_BUSY: ASIC is busy execute BBP programming.
 531  */
 532 #define PHY_CSR8                        0x04d0
 533 #define PHY_CSR8_BUSY                   FIELD16(0x0001)
 534
 535 /*
 536  * PHY_CSR9: RF access register.
 537  * RF_VALUE: Register value + id to program into rf/if.
 538  */
 539 #define PHY_CSR9                        0x04d2
 540 #define PHY_CSR9_RF_VALUE               FIELD16(0xffff)
 541
 542 /*
 543  * PHY_CSR10: RF access register.
 544  * RF_VALUE: Register value + id to program into rf/if.
 545  * RF_NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
 546  * RF_IF_SELECT: Chip to program: 0: rf, 1: if.
 547  * RF_PLL_LD: Rf pll_ld status.
 548  * RF_BUSY: 1: asic is busy execute rf programming.
 549  */
 550 #define PHY_CSR10                       0x04d4
 551 #define PHY_CSR10_RF_VALUE              FIELD16(0x00ff)
 552 #define PHY_CSR10_RF_NUMBER_OF_BITS     FIELD16(0x1f00)
 553 #define PHY_CSR10_RF_IF_SELECT          FIELD16(0x2000)
 554 #define PHY_CSR10_RF_PLL_LD             FIELD16(0x4000)
 555 #define PHY_CSR10_RF_BUSY               FIELD16(0x8000)
 556
 557 /*
 558  * STA_CSR0: FCS error count.
 559  * FCS_ERROR: FCS error count, cleared when read.
 560  */
 561 #define STA_CSR0                        0x04e0
 562 #define STA_CSR0_FCS_ERROR              FIELD16(0xffff)
 563
 564 /*
 565  * STA_CSR1: PLCP error count.
 566  */
 567 #define STA_CSR1                        0x04e2
 568
 569 /*
 570  * STA_CSR2: LONG error count.
 571  */
 572 #define STA_CSR2                        0x04e4
 573
 574 /*
 575  * STA_CSR3: CCA false alarm.
 576  * FALSE_CCA_ERROR: False CCA error count, cleared when read.
 577  */
 578 #define STA_CSR3                        0x04e6
 579 #define STA_CSR3_FALSE_CCA_ERROR        FIELD16(0xffff)
 580
 581 /*
 582  * STA_CSR4: RX FIFO overflow.
 583  */
 584 #define STA_CSR4                        0x04e8
 585
 586 /*
 587  * STA_CSR5: Beacon sent counter.
 588  */
 589 #define STA_CSR5                        0x04ea
 590
 591 /*
 592  *  Statistics registers
 593  */
 594 #define STA_CSR6                        0x04ec
 595 #define STA_CSR7                        0x04ee
 596 #define STA_CSR8                        0x04f0
 597 #define STA_CSR9                        0x04f2
 598 #define STA_CSR10                       0x04f4
 599
 600 /*
 601  * BBP registers.
 602  * The wordsize of the BBP is 8 bits.
 603  */
 604
 605 /*
 606  * R2: TX antenna control
 607  */
 608 #define BBP_R2_TX_ANTENNA               FIELD8(0x03)
 609 #define BBP_R2_TX_IQ_FLIP               FIELD8(0x04)
 610
 611 /*
 612  * R14: RX antenna control
 613  */
 614 #define BBP_R14_RX_ANTENNA              FIELD8(0x03)
 615 #define BBP_R14_RX_IQ_FLIP              FIELD8(0x04)
 616
 617 /*
 618  * RF registers.
 619  */
 620
 621 /*
 622  * RF 1
 623  */
 624 #define RF1_TUNER                       FIELD32(0x00020000)
 625
 626 /*
 627  * RF 3
 628  */
 629 #define RF3_TUNER                       FIELD32(0x00000100)
 630 #define RF3_TXPOWER                     FIELD32(0x00003e00)
 631
 632 /*
 633  * EEPROM contents.
 634  */
 635
 636 /*
 637  * HW MAC address.
 638  */
 639 #define EEPROM_MAC_ADDR_0               0x0002
 640 #define EEPROM_MAC_ADDR_BYTE0           FIELD16(0x00ff)
 641 #define EEPROM_MAC_ADDR_BYTE1           FIELD16(0xff00)
 642 #define EEPROM_MAC_ADDR1                0x0003
 643 #define EEPROM_MAC_ADDR_BYTE2           FIELD16(0x00ff)
 644 #define EEPROM_MAC_ADDR_BYTE3           FIELD16(0xff00)
 645 #define EEPROM_MAC_ADDR_2               0x0004
 646 #define EEPROM_MAC_ADDR_BYTE4           FIELD16(0x00ff)
 647 #define EEPROM_MAC_ADDR_BYTE5           FIELD16(0xff00)
 648
 649 /*
 650  * EEPROM antenna.
 651  * ANTENNA_NUM: Number of antenna's.
 652  * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
 653  * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
 654  * LED_MODE: 0: default, 1: TX/RX activity, 2: Single (ignore link), 3: rsvd.
 655  * DYN_TXAGC: Dynamic TX AGC control.
 656  * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
 657  * RF_TYPE: Rf_type of this adapter.
 658  */
 659 #define EEPROM_ANTENNA                  0x000b
 660 #define EEPROM_ANTENNA_NUM              FIELD16(0x0003)
 661 #define EEPROM_ANTENNA_TX_DEFAULT       FIELD16(0x000c)
 662 #define EEPROM_ANTENNA_RX_DEFAULT       FIELD16(0x0030)
 663 #define EEPROM_ANTENNA_LED_MODE         FIELD16(0x01c0)
 664 #define EEPROM_ANTENNA_DYN_TXAGC        FIELD16(0x0200)
 665 #define EEPROM_ANTENNA_HARDWARE_RADIO   FIELD16(0x0400)
 666 #define EEPROM_ANTENNA_RF_TYPE          FIELD16(0xf800)
 667
 668 /*
 669  * EEPROM NIC config.
 670  * CARDBUS_ACCEL: 0: enable, 1: disable.
 671  * DYN_BBP_TUNE: 0: enable, 1: disable.
 672  * CCK_TX_POWER: CCK TX power compensation.
 673  */
 674 #define EEPROM_NIC                      0x000c
 675 #define EEPROM_NIC_CARDBUS_ACCEL        FIELD16(0x0001)
 676 #define EEPROM_NIC_DYN_BBP_TUNE         FIELD16(0x0002)
 677 #define EEPROM_NIC_CCK_TX_POWER         FIELD16(0x000c)
 678
 679 /*
 680  * EEPROM geography.
 681  * GEO: Default geography setting for device.
 682  */
 683 #define EEPROM_GEOGRAPHY                0x000d
 684 #define EEPROM_GEOGRAPHY_GEO            FIELD16(0x0f00)
 685
 686 /*
 687  * EEPROM BBP.
 688  */
 689 #define EEPROM_BBP_START                0x000e
 690 #define EEPROM_BBP_SIZE                 16
 691 #define EEPROM_BBP_VALUE                FIELD16(0x00ff)
 692 #define EEPROM_BBP_REG_ID               FIELD16(0xff00)
 693
 694 /*
 695  * EEPROM TXPOWER
 696  */
 697 #define EEPROM_TXPOWER_START            0x001e
 698 #define EEPROM_TXPOWER_SIZE             7
 699 #define EEPROM_TXPOWER_1                FIELD16(0x00ff)
 700 #define EEPROM_TXPOWER_2                FIELD16(0xff00)
 701
 702 /*
 703  * EEPROM Tuning threshold
 704  */
 705 #define EEPROM_BBPTUNE                  0x0030
 706 #define EEPROM_BBPTUNE_THRESHOLD        FIELD16(0x00ff)
 707
 708 /*
 709  * EEPROM BBP R24 Tuning.
 710  */
 711 #define EEPROM_BBPTUNE_R24              0x0031
 712 #define EEPROM_BBPTUNE_R24_LOW          FIELD16(0x00ff)
 713 #define EEPROM_BBPTUNE_R24_HIGH         FIELD16(0xff00)
 714
 715 /*
 716  * EEPROM BBP R25 Tuning.
 717  */
 718 #define EEPROM_BBPTUNE_R25              0x0032
 719 #define EEPROM_BBPTUNE_R25_LOW          FIELD16(0x00ff)
 720 #define EEPROM_BBPTUNE_R25_HIGH         FIELD16(0xff00)
 721
 722 /*
 723  * EEPROM BBP R24 Tuning.
 724  */
 725 #define EEPROM_BBPTUNE_R61              0x0033
 726 #define EEPROM_BBPTUNE_R61_LOW          FIELD16(0x00ff)
 727 #define EEPROM_BBPTUNE_R61_HIGH         FIELD16(0xff00)
 728
 729 /*
 730  * EEPROM BBP VGC Tuning.
 731  */
 732 #define EEPROM_BBPTUNE_VGC              0x0034
 733 #define EEPROM_BBPTUNE_VGCUPPER         FIELD16(0x00ff)
 734 #define EEPROM_BBPTUNE_VGCLOWER         FIELD16(0xff00)
 735
 736 /*
 737  * EEPROM BBP R17 Tuning.
 738  */
 739 #define EEPROM_BBPTUNE_R17              0x0035
 740 #define EEPROM_BBPTUNE_R17_LOW          FIELD16(0x00ff)
 741 #define EEPROM_BBPTUNE_R17_HIGH         FIELD16(0xff00)
 742
 743 /*
 744  * RSSI <-> dBm offset calibration
 745  */
 746 #define EEPROM_CALIBRATE_OFFSET         0x0036
 747 #define EEPROM_CALIBRATE_OFFSET_RSSI    FIELD16(0x00ff)
 748
 749 /*
 750  * DMA descriptor defines.
 751  */
 752 #define TXD_DESC_SIZE                   ( 5 * sizeof(__le32) )
 753 #define RXD_DESC_SIZE                   ( 4 * sizeof(__le32) )
 754
 755 /*
 756  * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
 757  */
 758
 759 /*
 760  * Word0
 761  */
 762 #define TXD_W0_PACKET_ID                FIELD32(0x0000000f)
 763 #define TXD_W0_RETRY_LIMIT              FIELD32(0x000000f0)
 764 #define TXD_W0_MORE_FRAG                FIELD32(0x00000100)
 765 #define TXD_W0_ACK                      FIELD32(0x00000200)
 766 #define TXD_W0_TIMESTAMP                FIELD32(0x00000400)
 767 #define TXD_W0_OFDM                     FIELD32(0x00000800)
 768 #define TXD_W0_NEW_SEQ                  FIELD32(0x00001000)
 769 #define TXD_W0_IFS                      FIELD32(0x00006000)
 770 #define TXD_W0_DATABYTE_COUNT           FIELD32(0x0fff0000)
 771 #define TXD_W0_CIPHER                   FIELD32(0x20000000)
 772 #define TXD_W0_KEY_ID                   FIELD32(0xc0000000)
 773
 774 /*
 775  * Word1
 776  */
 777 #define TXD_W1_IV_OFFSET                FIELD32(0x0000003f)
 778 #define TXD_W1_AIFS                     FIELD32(0x000000c0)
 779 #define TXD_W1_CWMIN                    FIELD32(0x00000f00)
 780 #define TXD_W1_CWMAX                    FIELD32(0x0000f000)
 781
 782 /*
 783  * Word2: PLCP information
 784  */
 785 #define TXD_W2_PLCP_SIGNAL              FIELD32(0x000000ff)
 786 #define TXD_W2_PLCP_SERVICE             FIELD32(0x0000ff00)
 787 #define TXD_W2_PLCP_LENGTH_LOW          FIELD32(0x00ff0000)
 788 #define TXD_W2_PLCP_LENGTH_HIGH         FIELD32(0xff000000)
 789
 790 /*
 791  * Word3
 792  */
 793 #define TXD_W3_IV                       FIELD32(0xffffffff)
 794
 795 /*
 796  * Word4
 797  */
 798 #define TXD_W4_EIV                      FIELD32(0xffffffff)
 799
 800 /*
 801  * RX descriptor format for RX Ring.
 802  */
 803
 804 /*
 805  * Word0
 806  */
 807 #define RXD_W0_UNICAST_TO_ME            FIELD32(0x00000002)
 808 #define RXD_W0_MULTICAST                FIELD32(0x00000004)
 809 #define RXD_W0_BROADCAST                FIELD32(0x00000008)
 810 #define RXD_W0_MY_BSS                   FIELD32(0x00000010)
 811 #define RXD_W0_CRC_ERROR                FIELD32(0x00000020)
 812 #define RXD_W0_OFDM                     FIELD32(0x00000040)
 813 #define RXD_W0_PHYSICAL_ERROR           FIELD32(0x00000080)
 814 #define RXD_W0_CIPHER                   FIELD32(0x00000100)
 815 #define RXD_W0_CIPHER_ERROR             FIELD32(0x00000200)
 816 #define RXD_W0_DATABYTE_COUNT           FIELD32(0x0fff0000)
 817
 818 /*
 819  * Word1
 820  */
 821 #define RXD_W1_RSSI                     FIELD32(0x000000ff)
 822 #define RXD_W1_SIGNAL                   FIELD32(0x0000ff00)
 823
 824 /*
 825  * Word2
 826  */
 827 #define RXD_W2_IV                       FIELD32(0xffffffff)
 828
 829 /*
 830  * Word3
 831  */
 832 #define RXD_W3_EIV                      FIELD32(0xffffffff)
 833
 834 /*
 835  * Macros for converting txpower from EEPROM to mac80211 value
 836  * and from mac80211 value to register value.
 837  */
 838 #define MIN_TXPOWER     0
 839 #define MAX_TXPOWER     31
 840 #define DEFAULT_TXPOWER 24
 841
 842 #define TXPOWER_FROM_DEV(__txpower) \
 843         (((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
 844
 845 #define TXPOWER_TO_DEV(__txpower) \
 846         clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)
 847
 848 #endif /* RT2500USB_H */