drivers/net/wireless/rt2x00/rt2800.h

   1 /*
   2         Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
   3         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   4         Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   5         Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   6         Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
   7         Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
   8         Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
   9         Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  10         Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
  11         <http://rt2x00.serialmonkey.com>
  12
  13         This program is free software; you can redistribute it and/or modify
  14         it under the terms of the GNU General Public License as published by
  15         the Free Software Foundation; either version 2 of the License, or
  16         (at your option) any later version.
  17
  18         This program is distributed in the hope that it will be useful,
  19         but WITHOUT ANY WARRANTY; without even the implied warranty of
  20         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21         GNU General Public License for more details.
  22
  23         You should have received a copy of the GNU General Public License
  24         along with this program; if not, write to the
  25         Free Software Foundation, Inc.,
  26         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  27  */
  28
  29 /*
  30         Module: rt2800
  31         Abstract: Data structures and registers for the rt2800 modules.
  32         Supported chipsets: RT2800E, RT2800ED & RT2800U.
  33  */
  34
  35 #ifndef RT2800_H
  36 #define RT2800_H
  37
  38 /*
  39  * RF chip defines.
  40  *
  41  * RF2820 2.4G 2T3R
  42  * RF2850 2.4G/5G 2T3R
  43  * RF2720 2.4G 1T2R
  44  * RF2750 2.4G/5G 1T2R
  45  * RF3020 2.4G 1T1R
  46  * RF2020 2.4G B/G
  47  * RF3021 2.4G 1T2R
  48  * RF3022 2.4G 2T2R
  49  * RF3052 2.4G/5G 2T2R
  50  * RF2853 2.4G/5G 3T3R
  51  * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390)
  52  * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392)
  53  * RF3053 2.4G/5G 3T3R(RT3883/RT3563/RT3573/RT3593/RT3662)
  54  * RF5360 2.4G 1T1R
  55  * RF5370 2.4G 1T1R
  56  * RF5390 2.4G 1T1R
  57  */
  58 #define RF2820                          0x0001
  59 #define RF2850                          0x0002
  60 #define RF2720                          0x0003
  61 #define RF2750                          0x0004
  62 #define RF3020                          0x0005
  63 #define RF2020                          0x0006
  64 #define RF3021                          0x0007
  65 #define RF3022                          0x0008
  66 #define RF3052                          0x0009
  67 #define RF2853                          0x000a
  68 #define RF3320                          0x000b
  69 #define RF3322                          0x000c
  70 #define RF3053                          0x000d
  71 #define RF5360                          0x5360
  72 #define RF5370                          0x5370
  73 #define RF5372                          0x5372
  74 #define RF5390                          0x5390
  75
  76 /*
  77  * Chipset revisions.
  78  */
  79 #define REV_RT2860C                     0x0100
  80 #define REV_RT2860D                     0x0101
  81 #define REV_RT2872E                     0x0200
  82 #define REV_RT3070E                     0x0200
  83 #define REV_RT3070F                     0x0201
  84 #define REV_RT3071E                     0x0211
  85 #define REV_RT3090E                     0x0211
  86 #define REV_RT3390E                     0x0211
  87 #define REV_RT5390F                     0x0502
  88 #define REV_RT5390R                     0x1502
  89
  90 /*
  91  * Signal information.
  92  * Default offset is required for RSSI <-> dBm conversion.
  93  */
  94 #define DEFAULT_RSSI_OFFSET             120
  95
  96 /*
  97  * Register layout information.
  98  */
  99 #define CSR_REG_BASE                    0x1000
 100 #define CSR_REG_SIZE                    0x0800
 101 #define EEPROM_BASE                     0x0000
 102 #define EEPROM_SIZE                     0x0110
 103 #define BBP_BASE                        0x0000
 104 #define BBP_SIZE                        0x00ff
 105 #define RF_BASE                         0x0004
 106 #define RF_SIZE                         0x0010
 107 #define RFCSR_BASE                      0x0000
 108 #define RFCSR_SIZE                      0x0040
 109
 110 /*
 111  * Number of TX queues.
 112  */
 113 #define NUM_TX_QUEUES                   4
 114
 115 /*
 116  * Registers.
 117  */
 118
 119 /*
 120  * E2PROM_CSR: PCI EEPROM control register.
 121  * RELOAD: Write 1 to reload eeprom content.
 122  * TYPE: 0: 93c46, 1:93c66.
 123  * LOAD_STATUS: 1:loading, 0:done.
 124  */
 125 #define E2PROM_CSR                      0x0004
 126 #define E2PROM_CSR_DATA_CLOCK           FIELD32(0x00000001)
 127 #define E2PROM_CSR_CHIP_SELECT          FIELD32(0x00000002)
 128 #define E2PROM_CSR_DATA_IN              FIELD32(0x00000004)
 129 #define E2PROM_CSR_DATA_OUT             FIELD32(0x00000008)
 130 #define E2PROM_CSR_TYPE                 FIELD32(0x00000030)
 131 #define E2PROM_CSR_LOAD_STATUS          FIELD32(0x00000040)
 132 #define E2PROM_CSR_RELOAD               FIELD32(0x00000080)
 133
 134 /*
 135  * AUX_CTRL: Aux/PCI-E related configuration
 136  */
 137 #define AUX_CTRL                        0x10c
 138 #define AUX_CTRL_WAKE_PCIE_EN           FIELD32(0x00000002)
 139 #define AUX_CTRL_FORCE_PCIE_CLK         FIELD32(0x00000400)
 140
 141 /*
 142  * OPT_14: Unknown register used by rt3xxx devices.
 143  */
 144 #define OPT_14_CSR                      0x0114
 145 #define OPT_14_CSR_BIT0                 FIELD32(0x00000001)
 146
 147 /*
 148  * INT_SOURCE_CSR: Interrupt source register.
 149  * Write one to clear corresponding bit.
 150  * TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO
 151  */
 152 #define INT_SOURCE_CSR                  0x0200
 153 #define INT_SOURCE_CSR_RXDELAYINT       FIELD32(0x00000001)
 154 #define INT_SOURCE_CSR_TXDELAYINT       FIELD32(0x00000002)
 155 #define INT_SOURCE_CSR_RX_DONE          FIELD32(0x00000004)
 156 #define INT_SOURCE_CSR_AC0_DMA_DONE     FIELD32(0x00000008)
 157 #define INT_SOURCE_CSR_AC1_DMA_DONE     FIELD32(0x00000010)
 158 #define INT_SOURCE_CSR_AC2_DMA_DONE     FIELD32(0x00000020)
 159 #define INT_SOURCE_CSR_AC3_DMA_DONE     FIELD32(0x00000040)
 160 #define INT_SOURCE_CSR_HCCA_DMA_DONE    FIELD32(0x00000080)
 161 #define INT_SOURCE_CSR_MGMT_DMA_DONE    FIELD32(0x00000100)
 162 #define INT_SOURCE_CSR_MCU_COMMAND      FIELD32(0x00000200)
 163 #define INT_SOURCE_CSR_RXTX_COHERENT    FIELD32(0x00000400)
 164 #define INT_SOURCE_CSR_TBTT             FIELD32(0x00000800)
 165 #define INT_SOURCE_CSR_PRE_TBTT         FIELD32(0x00001000)
 166 #define INT_SOURCE_CSR_TX_FIFO_STATUS   FIELD32(0x00002000)
 167 #define INT_SOURCE_CSR_AUTO_WAKEUP      FIELD32(0x00004000)
 168 #define INT_SOURCE_CSR_GPTIMER          FIELD32(0x00008000)
 169 #define INT_SOURCE_CSR_RX_COHERENT      FIELD32(0x00010000)
 170 #define INT_SOURCE_CSR_TX_COHERENT      FIELD32(0x00020000)
 171
 172 /*
 173  * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
 174  */
 175 #define INT_MASK_CSR                    0x0204
 176 #define INT_MASK_CSR_RXDELAYINT         FIELD32(0x00000001)
 177 #define INT_MASK_CSR_TXDELAYINT         FIELD32(0x00000002)
 178 #define INT_MASK_CSR_RX_DONE            FIELD32(0x00000004)
 179 #define INT_MASK_CSR_AC0_DMA_DONE       FIELD32(0x00000008)
 180 #define INT_MASK_CSR_AC1_DMA_DONE       FIELD32(0x00000010)
 181 #define INT_MASK_CSR_AC2_DMA_DONE       FIELD32(0x00000020)
 182 #define INT_MASK_CSR_AC3_DMA_DONE       FIELD32(0x00000040)
 183 #define INT_MASK_CSR_HCCA_DMA_DONE      FIELD32(0x00000080)
 184 #define INT_MASK_CSR_MGMT_DMA_DONE      FIELD32(0x00000100)
 185 #define INT_MASK_CSR_MCU_COMMAND        FIELD32(0x00000200)
 186 #define INT_MASK_CSR_RXTX_COHERENT      FIELD32(0x00000400)
 187 #define INT_MASK_CSR_TBTT               FIELD32(0x00000800)
 188 #define INT_MASK_CSR_PRE_TBTT           FIELD32(0x00001000)
 189 #define INT_MASK_CSR_TX_FIFO_STATUS     FIELD32(0x00002000)
 190 #define INT_MASK_CSR_AUTO_WAKEUP        FIELD32(0x00004000)
 191 #define INT_MASK_CSR_GPTIMER            FIELD32(0x00008000)
 192 #define INT_MASK_CSR_RX_COHERENT        FIELD32(0x00010000)
 193 #define INT_MASK_CSR_TX_COHERENT        FIELD32(0x00020000)
 194
 195 /*
 196  * WPDMA_GLO_CFG
 197  */
 198 #define WPDMA_GLO_CFG                   0x0208
 199 #define WPDMA_GLO_CFG_ENABLE_TX_DMA     FIELD32(0x00000001)
 200 #define WPDMA_GLO_CFG_TX_DMA_BUSY       FIELD32(0x00000002)
 201 #define WPDMA_GLO_CFG_ENABLE_RX_DMA     FIELD32(0x00000004)
 202 #define WPDMA_GLO_CFG_RX_DMA_BUSY       FIELD32(0x00000008)
 203 #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
 204 #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
 205 #define WPDMA_GLO_CFG_BIG_ENDIAN        FIELD32(0x00000080)
 206 #define WPDMA_GLO_CFG_RX_HDR_SCATTER    FIELD32(0x0000ff00)
 207 #define WPDMA_GLO_CFG_HDR_SEG_LEN       FIELD32(0xffff0000)
 208
 209 /*
 210  * WPDMA_RST_IDX
 211  */
 212 #define WPDMA_RST_IDX                   0x020c
 213 #define WPDMA_RST_IDX_DTX_IDX0          FIELD32(0x00000001)
 214 #define WPDMA_RST_IDX_DTX_IDX1          FIELD32(0x00000002)
 215 #define WPDMA_RST_IDX_DTX_IDX2          FIELD32(0x00000004)
 216 #define WPDMA_RST_IDX_DTX_IDX3          FIELD32(0x00000008)
 217 #define WPDMA_RST_IDX_DTX_IDX4          FIELD32(0x00000010)
 218 #define WPDMA_RST_IDX_DTX_IDX5          FIELD32(0x00000020)
 219 #define WPDMA_RST_IDX_DRX_IDX0          FIELD32(0x00010000)
 220
 221 /*
 222  * DELAY_INT_CFG
 223  */
 224 #define DELAY_INT_CFG                   0x0210
 225 #define DELAY_INT_CFG_RXMAX_PTIME       FIELD32(0x000000ff)
 226 #define DELAY_INT_CFG_RXMAX_PINT        FIELD32(0x00007f00)
 227 #define DELAY_INT_CFG_RXDLY_INT_EN      FIELD32(0x00008000)
 228 #define DELAY_INT_CFG_TXMAX_PTIME       FIELD32(0x00ff0000)
 229 #define DELAY_INT_CFG_TXMAX_PINT        FIELD32(0x7f000000)
 230 #define DELAY_INT_CFG_TXDLY_INT_EN      FIELD32(0x80000000)
 231
 232 /*
 233  * WMM_AIFSN_CFG: Aifsn for each EDCA AC
 234  * AIFSN0: AC_VO
 235  * AIFSN1: AC_VI
 236  * AIFSN2: AC_BE
 237  * AIFSN3: AC_BK
 238  */
 239 #define WMM_AIFSN_CFG                   0x0214
 240 #define WMM_AIFSN_CFG_AIFSN0            FIELD32(0x0000000f)
 241 #define WMM_AIFSN_CFG_AIFSN1            FIELD32(0x000000f0)
 242 #define WMM_AIFSN_CFG_AIFSN2            FIELD32(0x00000f00)
 243 #define WMM_AIFSN_CFG_AIFSN3            FIELD32(0x0000f000)
 244
 245 /*
 246  * WMM_CWMIN_CSR: CWmin for each EDCA AC
 247  * CWMIN0: AC_VO
 248  * CWMIN1: AC_VI
 249  * CWMIN2: AC_BE
 250  * CWMIN3: AC_BK
 251  */
 252 #define WMM_CWMIN_CFG                   0x0218
 253 #define WMM_CWMIN_CFG_CWMIN0            FIELD32(0x0000000f)
 254 #define WMM_CWMIN_CFG_CWMIN1            FIELD32(0x000000f0)
 255 #define WMM_CWMIN_CFG_CWMIN2            FIELD32(0x00000f00)
 256 #define WMM_CWMIN_CFG_CWMIN3            FIELD32(0x0000f000)
 257
 258 /*
 259  * WMM_CWMAX_CSR: CWmax for each EDCA AC
 260  * CWMAX0: AC_VO
 261  * CWMAX1: AC_VI
 262  * CWMAX2: AC_BE
 263  * CWMAX3: AC_BK
 264  */
 265 #define WMM_CWMAX_CFG                   0x021c
 266 #define WMM_CWMAX_CFG_CWMAX0            FIELD32(0x0000000f)
 267 #define WMM_CWMAX_CFG_CWMAX1            FIELD32(0x000000f0)
 268 #define WMM_CWMAX_CFG_CWMAX2            FIELD32(0x00000f00)
 269 #define WMM_CWMAX_CFG_CWMAX3            FIELD32(0x0000f000)
 270
 271 /*
 272  * AC_TXOP0: AC_VO/AC_VI TXOP register
 273  * AC0TXOP: AC_VO in unit of 32us
 274  * AC1TXOP: AC_VI in unit of 32us
 275  */
 276 #define WMM_TXOP0_CFG                   0x0220
 277 #define WMM_TXOP0_CFG_AC0TXOP           FIELD32(0x0000ffff)
 278 #define WMM_TXOP0_CFG_AC1TXOP           FIELD32(0xffff0000)
 279
 280 /*
 281  * AC_TXOP1: AC_BE/AC_BK TXOP register
 282  * AC2TXOP: AC_BE in unit of 32us
 283  * AC3TXOP: AC_BK in unit of 32us
 284  */
 285 #define WMM_TXOP1_CFG                   0x0224
 286 #define WMM_TXOP1_CFG_AC2TXOP           FIELD32(0x0000ffff)
 287 #define WMM_TXOP1_CFG_AC3TXOP           FIELD32(0xffff0000)
 288
 289 /*
 290  * GPIO_CTRL_CFG:
 291  * GPIOD: GPIO direction, 0: Output, 1: Input
 292  */
 293 #define GPIO_CTRL_CFG                   0x0228
 294 #define GPIO_CTRL_CFG_BIT0              FIELD32(0x00000001)
 295 #define GPIO_CTRL_CFG_BIT1              FIELD32(0x00000002)
 296 #define GPIO_CTRL_CFG_BIT2              FIELD32(0x00000004)
 297 #define GPIO_CTRL_CFG_BIT3              FIELD32(0x00000008)
 298 #define GPIO_CTRL_CFG_BIT4              FIELD32(0x00000010)
 299 #define GPIO_CTRL_CFG_BIT5              FIELD32(0x00000020)
 300 #define GPIO_CTRL_CFG_BIT6              FIELD32(0x00000040)
 301 #define GPIO_CTRL_CFG_BIT7              FIELD32(0x00000080)
 302 #define GPIO_CTRL_CFG_GPIOD_BIT0        FIELD32(0x00000100)
 303 #define GPIO_CTRL_CFG_GPIOD_BIT1        FIELD32(0x00000200)
 304 #define GPIO_CTRL_CFG_GPIOD_BIT2        FIELD32(0x00000400)
 305 #define GPIO_CTRL_CFG_GPIOD_BIT3        FIELD32(0x00000800)
 306 #define GPIO_CTRL_CFG_GPIOD_BIT4        FIELD32(0x00001000)
 307 #define GPIO_CTRL_CFG_GPIOD_BIT5        FIELD32(0x00002000)
 308 #define GPIO_CTRL_CFG_GPIOD_BIT6        FIELD32(0x00004000)
 309 #define GPIO_CTRL_CFG_GPIOD_BIT7        FIELD32(0x00008000)
 310
 311 /*
 312  * MCU_CMD_CFG
 313  */
 314 #define MCU_CMD_CFG                     0x022c
 315
 316 /*
 317  * AC_VO register offsets
 318  */
 319 #define TX_BASE_PTR0                    0x0230
 320 #define TX_MAX_CNT0                     0x0234
 321 #define TX_CTX_IDX0                     0x0238
 322 #define TX_DTX_IDX0                     0x023c
 323
 324 /*
 325  * AC_VI register offsets
 326  */
 327 #define TX_BASE_PTR1                    0x0240
 328 #define TX_MAX_CNT1                     0x0244
 329 #define TX_CTX_IDX1                     0x0248
 330 #define TX_DTX_IDX1                     0x024c
 331
 332 /*
 333  * AC_BE register offsets
 334  */
 335 #define TX_BASE_PTR2                    0x0250
 336 #define TX_MAX_CNT2                     0x0254
 337 #define TX_CTX_IDX2                     0x0258
 338 #define TX_DTX_IDX2                     0x025c
 339
 340 /*
 341  * AC_BK register offsets
 342  */
 343 #define TX_BASE_PTR3                    0x0260
 344 #define TX_MAX_CNT3                     0x0264
 345 #define TX_CTX_IDX3                     0x0268
 346 #define TX_DTX_IDX3                     0x026c
 347
 348 /*
 349  * HCCA register offsets
 350  */
 351 #define TX_BASE_PTR4                    0x0270
 352 #define TX_MAX_CNT4                     0x0274
 353 #define TX_CTX_IDX4                     0x0278
 354 #define TX_DTX_IDX4                     0x027c
 355
 356 /*
 357  * MGMT register offsets
 358  */
 359 #define TX_BASE_PTR5                    0x0280
 360 #define TX_MAX_CNT5                     0x0284
 361 #define TX_CTX_IDX5                     0x0288
 362 #define TX_DTX_IDX5                     0x028c
 363
 364 /*
 365  * RX register offsets
 366  */
 367 #define RX_BASE_PTR                     0x0290
 368 #define RX_MAX_CNT                      0x0294
 369 #define RX_CRX_IDX                      0x0298
 370 #define RX_DRX_IDX                      0x029c
 371
 372 /*
 373  * USB_DMA_CFG
 374  * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
 375  * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
 376  * PHY_CLEAR: phy watch dog enable.
 377  * TX_CLEAR: Clear USB DMA TX path.
 378  * TXOP_HALT: Halt TXOP count down when TX buffer is full.
 379  * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
 380  * RX_BULK_EN: Enable USB DMA Rx.
 381  * TX_BULK_EN: Enable USB DMA Tx.
 382  * EP_OUT_VALID: OUT endpoint data valid.
 383  * RX_BUSY: USB DMA RX FSM busy.
 384  * TX_BUSY: USB DMA TX FSM busy.
 385  */
 386 #define USB_DMA_CFG                     0x02a0
 387 #define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
 388 #define USB_DMA_CFG_RX_BULK_AGG_LIMIT   FIELD32(0x0000ff00)
 389 #define USB_DMA_CFG_PHY_CLEAR           FIELD32(0x00010000)
 390 #define USB_DMA_CFG_TX_CLEAR            FIELD32(0x00080000)
 391 #define USB_DMA_CFG_TXOP_HALT           FIELD32(0x00100000)
 392 #define USB_DMA_CFG_RX_BULK_AGG_EN      FIELD32(0x00200000)
 393 #define USB_DMA_CFG_RX_BULK_EN          FIELD32(0x00400000)
 394 #define USB_DMA_CFG_TX_BULK_EN          FIELD32(0x00800000)
 395 #define USB_DMA_CFG_EP_OUT_VALID        FIELD32(0x3f000000)
 396 #define USB_DMA_CFG_RX_BUSY             FIELD32(0x40000000)
 397 #define USB_DMA_CFG_TX_BUSY             FIELD32(0x80000000)
 398
 399 /*
 400  * US_CYC_CNT
 401  * BT_MODE_EN: Bluetooth mode enable
 402  * CLOCK CYCLE: Clock cycle count in 1us.
 403  * PCI:0x21, PCIE:0x7d, USB:0x1e
 404  */
 405 #define US_CYC_CNT                      0x02a4
 406 #define US_CYC_CNT_BT_MODE_EN           FIELD32(0x00000100)
 407 #define US_CYC_CNT_CLOCK_CYCLE          FIELD32(0x000000ff)
 408
 409 /*
 410  * PBF_SYS_CTRL
 411  * HOST_RAM_WRITE: enable Host program ram write selection
 412  */
 413 #define PBF_SYS_CTRL                    0x0400
 414 #define PBF_SYS_CTRL_READY              FIELD32(0x00000080)
 415 #define PBF_SYS_CTRL_HOST_RAM_WRITE     FIELD32(0x00010000)
 416
 417 /*
 418  * HOST-MCU shared memory
 419  */
 420 #define HOST_CMD_CSR                    0x0404
 421 #define HOST_CMD_CSR_HOST_COMMAND       FIELD32(0x000000ff)
 422
 423 /*
 424  * PBF registers
 425  * Most are for debug. Driver doesn't touch PBF register.
 426  */
 427 #define PBF_CFG                         0x0408
 428 #define PBF_MAX_PCNT                    0x040c
 429 #define PBF_CTRL                        0x0410
 430 #define PBF_INT_STA                     0x0414
 431 #define PBF_INT_ENA                     0x0418
 432
 433 /*
 434  * BCN_OFFSET0:
 435  */
 436 #define BCN_OFFSET0                     0x042c
 437 #define BCN_OFFSET0_BCN0                FIELD32(0x000000ff)
 438 #define BCN_OFFSET0_BCN1                FIELD32(0x0000ff00)
 439 #define BCN_OFFSET0_BCN2                FIELD32(0x00ff0000)
 440 #define BCN_OFFSET0_BCN3                FIELD32(0xff000000)
 441
 442 /*
 443  * BCN_OFFSET1:
 444  */
 445 #define BCN_OFFSET1                     0x0430
 446 #define BCN_OFFSET1_BCN4                FIELD32(0x000000ff)
 447 #define BCN_OFFSET1_BCN5                FIELD32(0x0000ff00)
 448 #define BCN_OFFSET1_BCN6                FIELD32(0x00ff0000)
 449 #define BCN_OFFSET1_BCN7                FIELD32(0xff000000)
 450
 451 /*
 452  * TXRXQ_PCNT: PBF register
 453  * PCNT_TX0Q: Page count for TX hardware queue 0
 454  * PCNT_TX1Q: Page count for TX hardware queue 1
 455  * PCNT_TX2Q: Page count for TX hardware queue 2
 456  * PCNT_RX0Q: Page count for RX hardware queue
 457  */
 458 #define TXRXQ_PCNT                      0x0438
 459 #define TXRXQ_PCNT_TX0Q                 FIELD32(0x000000ff)
 460 #define TXRXQ_PCNT_TX1Q                 FIELD32(0x0000ff00)
 461 #define TXRXQ_PCNT_TX2Q                 FIELD32(0x00ff0000)
 462 #define TXRXQ_PCNT_RX0Q                 FIELD32(0xff000000)
 463
 464 /*
 465  * PBF register
 466  * Debug. Driver doesn't touch PBF register.
 467  */
 468 #define PBF_DBG                         0x043c
 469
 470 /*
 471  * RF registers
 472  */
 473 #define RF_CSR_CFG                      0x0500
 474 #define RF_CSR_CFG_DATA                 FIELD32(0x000000ff)
 475 #define RF_CSR_CFG_REGNUM               FIELD32(0x00003f00)
 476 #define RF_CSR_CFG_WRITE                FIELD32(0x00010000)
 477 #define RF_CSR_CFG_BUSY                 FIELD32(0x00020000)
 478
 479 /*
 480  * EFUSE_CSR: RT30x0 EEPROM
 481  */
 482 #define EFUSE_CTRL                      0x0580
 483 #define EFUSE_CTRL_ADDRESS_IN           FIELD32(0x03fe0000)
 484 #define EFUSE_CTRL_MODE                 FIELD32(0x000000c0)
 485 #define EFUSE_CTRL_KICK                 FIELD32(0x40000000)
 486 #define EFUSE_CTRL_PRESENT              FIELD32(0x80000000)
 487
 488 /*
 489  * EFUSE_DATA0
 490  */
 491 #define EFUSE_DATA0                     0x0590
 492
 493 /*
 494  * EFUSE_DATA1
 495  */
 496 #define EFUSE_DATA1                     0x0594
 497
 498 /*
 499  * EFUSE_DATA2
 500  */
 501 #define EFUSE_DATA2                     0x0598
 502
 503 /*
 504  * EFUSE_DATA3
 505  */
 506 #define EFUSE_DATA3                     0x059c
 507
 508 /*
 509  * LDO_CFG0
 510  */
 511 #define LDO_CFG0                        0x05d4
 512 #define LDO_CFG0_DELAY3                 FIELD32(0x000000ff)
 513 #define LDO_CFG0_DELAY2                 FIELD32(0x0000ff00)
 514 #define LDO_CFG0_DELAY1                 FIELD32(0x00ff0000)
 515 #define LDO_CFG0_BGSEL                  FIELD32(0x03000000)
 516 #define LDO_CFG0_LDO_CORE_VLEVEL        FIELD32(0x1c000000)
 517 #define LD0_CFG0_LDO25_LEVEL            FIELD32(0x60000000)
 518 #define LDO_CFG0_LDO25_LARGEA           FIELD32(0x80000000)
 519
 520 /*
 521  * GPIO_SWITCH
 522  */
 523 #define GPIO_SWITCH                     0x05dc
 524 #define GPIO_SWITCH_0                   FIELD32(0x00000001)
 525 #define GPIO_SWITCH_1                   FIELD32(0x00000002)
 526 #define GPIO_SWITCH_2                   FIELD32(0x00000004)
 527 #define GPIO_SWITCH_3                   FIELD32(0x00000008)
 528 #define GPIO_SWITCH_4                   FIELD32(0x00000010)
 529 #define GPIO_SWITCH_5                   FIELD32(0x00000020)
 530 #define GPIO_SWITCH_6                   FIELD32(0x00000040)
 531 #define GPIO_SWITCH_7                   FIELD32(0x00000080)
 532
 533 /*
 534  * MAC Control/Status Registers(CSR).
 535  * Some values are set in TU, whereas 1 TU == 1024 us.
 536  */
 537
 538 /*
 539  * MAC_CSR0: ASIC revision number.
 540  * ASIC_REV: 0
 541  * ASIC_VER: 2860 or 2870
 542  */
 543 #define MAC_CSR0                        0x1000
 544 #define MAC_CSR0_REVISION               FIELD32(0x0000ffff)
 545 #define MAC_CSR0_CHIPSET                FIELD32(0xffff0000)
 546
 547 /*
 548  * MAC_SYS_CTRL:
 549  */
 550 #define MAC_SYS_CTRL                    0x1004
 551 #define MAC_SYS_CTRL_RESET_CSR          FIELD32(0x00000001)
 552 #define MAC_SYS_CTRL_RESET_BBP          FIELD32(0x00000002)
 553 #define MAC_SYS_CTRL_ENABLE_TX          FIELD32(0x00000004)
 554 #define MAC_SYS_CTRL_ENABLE_RX          FIELD32(0x00000008)
 555 #define MAC_SYS_CTRL_CONTINUOUS_TX      FIELD32(0x00000010)
 556 #define MAC_SYS_CTRL_LOOPBACK           FIELD32(0x00000020)
 557 #define MAC_SYS_CTRL_WLAN_HALT          FIELD32(0x00000040)
 558 #define MAC_SYS_CTRL_RX_TIMESTAMP       FIELD32(0x00000080)
 559
 560 /*
 561  * MAC_ADDR_DW0: STA MAC register 0
 562  */
 563 #define MAC_ADDR_DW0                    0x1008
 564 #define MAC_ADDR_DW0_BYTE0              FIELD32(0x000000ff)
 565 #define MAC_ADDR_DW0_BYTE1              FIELD32(0x0000ff00)
 566 #define MAC_ADDR_DW0_BYTE2              FIELD32(0x00ff0000)
 567 #define MAC_ADDR_DW0_BYTE3              FIELD32(0xff000000)
 568
 569 /*
 570  * MAC_ADDR_DW1: STA MAC register 1
 571  * UNICAST_TO_ME_MASK:
 572  * Used to mask off bits from byte 5 of the MAC address
 573  * to determine the UNICAST_TO_ME bit for RX frames.
 574  * The full mask is complemented by BSS_ID_MASK:
 575  *    MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
 576  */
 577 #define MAC_ADDR_DW1                    0x100c
 578 #define MAC_ADDR_DW1_BYTE4              FIELD32(0x000000ff)
 579 #define MAC_ADDR_DW1_BYTE5              FIELD32(0x0000ff00)
 580 #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
 581
 582 /*
 583  * MAC_BSSID_DW0: BSSID register 0
 584  */
 585 #define MAC_BSSID_DW0                   0x1010
 586 #define MAC_BSSID_DW0_BYTE0             FIELD32(0x000000ff)
 587 #define MAC_BSSID_DW0_BYTE1             FIELD32(0x0000ff00)
 588 #define MAC_BSSID_DW0_BYTE2             FIELD32(0x00ff0000)
 589 #define MAC_BSSID_DW0_BYTE3             FIELD32(0xff000000)
 590
 591 /*
 592  * MAC_BSSID_DW1: BSSID register 1
 593  * BSS_ID_MASK:
 594  *     0: 1-BSSID mode (BSS index = 0)
 595  *     1: 2-BSSID mode (BSS index: Byte5, bit 0)
 596  *     2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
 597  *     3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
 598  * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
 599  * BSSID. This will make sure that those bits will be ignored
 600  * when determining the MY_BSS of RX frames.
 601  */
 602 #define MAC_BSSID_DW1                   0x1014
 603 #define MAC_BSSID_DW1_BYTE4             FIELD32(0x000000ff)
 604 #define MAC_BSSID_DW1_BYTE5             FIELD32(0x0000ff00)
 605 #define MAC_BSSID_DW1_BSS_ID_MASK       FIELD32(0x00030000)
 606 #define MAC_BSSID_DW1_BSS_BCN_NUM       FIELD32(0x001c0000)
 607
 608 /*
 609  * MAX_LEN_CFG: Maximum frame length register.
 610  * MAX_MPDU: rt2860b max 16k bytes
 611  * MAX_PSDU: Maximum PSDU length
 612  *      (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
 613  */
 614 #define MAX_LEN_CFG                     0x1018
 615 #define MAX_LEN_CFG_MAX_MPDU            FIELD32(0x00000fff)
 616 #define MAX_LEN_CFG_MAX_PSDU            FIELD32(0x00003000)
 617 #define MAX_LEN_CFG_MIN_PSDU            FIELD32(0x0000c000)
 618 #define MAX_LEN_CFG_MIN_MPDU            FIELD32(0x000f0000)
 619
 620 /*
 621  * BBP_CSR_CFG: BBP serial control register
 622  * VALUE: Register value to program into BBP
 623  * REG_NUM: Selected BBP register
 624  * READ_CONTROL: 0 write BBP, 1 read BBP
 625  * BUSY: ASIC is busy executing BBP commands
 626  * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
 627  * BBP_RW_MODE: 0 serial, 1 parallel
 628  */
 629 #define BBP_CSR_CFG                     0x101c
 630 #define BBP_CSR_CFG_VALUE               FIELD32(0x000000ff)
 631 #define BBP_CSR_CFG_REGNUM              FIELD32(0x0000ff00)
 632 #define BBP_CSR_CFG_READ_CONTROL        FIELD32(0x00010000)
 633 #define BBP_CSR_CFG_BUSY                FIELD32(0x00020000)
 634 #define BBP_CSR_CFG_BBP_PAR_DUR         FIELD32(0x00040000)
 635 #define BBP_CSR_CFG_BBP_RW_MODE         FIELD32(0x00080000)
 636
 637 /*
 638  * RF_CSR_CFG0: RF control register
 639  * REGID_AND_VALUE: Register value to program into RF
 640  * BITWIDTH: Selected RF register
 641  * STANDBYMODE: 0 high when standby, 1 low when standby
 642  * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
 643  * BUSY: ASIC is busy executing RF commands
 644  */
 645 #define RF_CSR_CFG0                     0x1020
 646 #define RF_CSR_CFG0_REGID_AND_VALUE     FIELD32(0x00ffffff)
 647 #define RF_CSR_CFG0_BITWIDTH            FIELD32(0x1f000000)
 648 #define RF_CSR_CFG0_REG_VALUE_BW        FIELD32(0x1fffffff)
 649 #define RF_CSR_CFG0_STANDBYMODE         FIELD32(0x20000000)
 650 #define RF_CSR_CFG0_SEL                 FIELD32(0x40000000)
 651 #define RF_CSR_CFG0_BUSY                FIELD32(0x80000000)
 652
 653 /*
 654  * RF_CSR_CFG1: RF control register
 655  * REGID_AND_VALUE: Register value to program into RF
 656  * RFGAP: Gap between BB_CONTROL_RF and RF_LE
 657  *        0: 3 system clock cycle (37.5usec)
 658  *        1: 5 system clock cycle (62.5usec)
 659  */
 660 #define RF_CSR_CFG1                     0x1024
 661 #define RF_CSR_CFG1_REGID_AND_VALUE     FIELD32(0x00ffffff)
 662 #define RF_CSR_CFG1_RFGAP               FIELD32(0x1f000000)
 663
 664 /*
 665  * RF_CSR_CFG2: RF control register
 666  * VALUE: Register value to program into RF
 667  */
 668 #define RF_CSR_CFG2                     0x1028
 669 #define RF_CSR_CFG2_VALUE               FIELD32(0x00ffffff)
 670
 671 /*
 672  * LED_CFG: LED control
 673  * ON_PERIOD: LED active time (ms) during TX (only used for LED mode 1)
 674  * OFF_PERIOD: LED inactive time (ms) during TX (only used for LED mode 1)
 675  * SLOW_BLINK_PERIOD: LED blink interval in seconds (only used for LED mode 2)
 676  * color LED's:
 677  *   0: off
 678  *   1: blinking upon TX2
 679  *   2: periodic slow blinking
 680  *   3: always on
 681  * LED polarity:
 682  *   0: active low
 683  *   1: active high
 684  */
 685 #define LED_CFG                         0x102c
 686 #define LED_CFG_ON_PERIOD               FIELD32(0x000000ff)
 687 #define LED_CFG_OFF_PERIOD              FIELD32(0x0000ff00)
 688 #define LED_CFG_SLOW_BLINK_PERIOD       FIELD32(0x003f0000)
 689 #define LED_CFG_R_LED_MODE              FIELD32(0x03000000)
 690 #define LED_CFG_G_LED_MODE              FIELD32(0x0c000000)
 691 #define LED_CFG_Y_LED_MODE              FIELD32(0x30000000)
 692 #define LED_CFG_LED_POLAR               FIELD32(0x40000000)
 693
 694 /*
 695  * AMPDU_BA_WINSIZE: Force BlockAck window size
 696  * FORCE_WINSIZE_ENABLE:
 697  *   0: Disable forcing of BlockAck window size
 698  *   1: Enable forcing of BlockAck window size, overwrites values BlockAck
 699  *      window size values in the TXWI
 700  * FORCE_WINSIZE: BlockAck window size
 701  */
 702 #define AMPDU_BA_WINSIZE                0x1040
 703 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE FIELD32(0x00000020)
 704 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE  FIELD32(0x0000001f)
 705
 706 /*
 707  * XIFS_TIME_CFG: MAC timing
 708  * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
 709  * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
 710  * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
 711  *      when MAC doesn't reference BBP signal BBRXEND
 712  * EIFS: unit 1us
 713  * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
 714  *
 715  */
 716 #define XIFS_TIME_CFG                   0x1100
 717 #define XIFS_TIME_CFG_CCKM_SIFS_TIME    FIELD32(0x000000ff)
 718 #define XIFS_TIME_CFG_OFDM_SIFS_TIME    FIELD32(0x0000ff00)
 719 #define XIFS_TIME_CFG_OFDM_XIFS_TIME    FIELD32(0x000f0000)
 720 #define XIFS_TIME_CFG_EIFS              FIELD32(0x1ff00000)
 721 #define XIFS_TIME_CFG_BB_RXEND_ENABLE   FIELD32(0x20000000)
 722
 723 /*
 724  * BKOFF_SLOT_CFG:
 725  */
 726 #define BKOFF_SLOT_CFG                  0x1104
 727 #define BKOFF_SLOT_CFG_SLOT_TIME        FIELD32(0x000000ff)
 728 #define BKOFF_SLOT_CFG_CC_DELAY_TIME    FIELD32(0x0000ff00)
 729
 730 /*
 731  * NAV_TIME_CFG:
 732  */
 733 #define NAV_TIME_CFG                    0x1108
 734 #define NAV_TIME_CFG_SIFS               FIELD32(0x000000ff)
 735 #define NAV_TIME_CFG_SLOT_TIME          FIELD32(0x0000ff00)
 736 #define NAV_TIME_CFG_EIFS               FIELD32(0x01ff0000)
 737 #define NAV_TIME_ZERO_SIFS              FIELD32(0x02000000)
 738
 739 /*
 740  * CH_TIME_CFG: count as channel busy
 741  * EIFS_BUSY: Count EIFS as channel busy
 742  * NAV_BUSY: Count NAS as channel busy
 743  * RX_BUSY: Count RX as channel busy
 744  * TX_BUSY: Count TX as channel busy
 745  * TMR_EN: Enable channel statistics timer
 746  */
 747 #define CH_TIME_CFG                     0x110c
 748 #define CH_TIME_CFG_EIFS_BUSY           FIELD32(0x00000010)
 749 #define CH_TIME_CFG_NAV_BUSY            FIELD32(0x00000008)
 750 #define CH_TIME_CFG_RX_BUSY             FIELD32(0x00000004)
 751 #define CH_TIME_CFG_TX_BUSY             FIELD32(0x00000002)
 752 #define CH_TIME_CFG_TMR_EN              FIELD32(0x00000001)
 753
 754 /*
 755  * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
 756  */
 757 #define PBF_LIFE_TIMER                  0x1110
 758
 759 /*
 760  * BCN_TIME_CFG:
 761  * BEACON_INTERVAL: in unit of 1/16 TU
 762  * TSF_TICKING: Enable TSF auto counting
 763  * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
 764  * BEACON_GEN: Enable beacon generator
 765  */
 766 #define BCN_TIME_CFG                    0x1114
 767 #define BCN_TIME_CFG_BEACON_INTERVAL    FIELD32(0x0000ffff)
 768 #define BCN_TIME_CFG_TSF_TICKING        FIELD32(0x00010000)
 769 #define BCN_TIME_CFG_TSF_SYNC           FIELD32(0x00060000)
 770 #define BCN_TIME_CFG_TBTT_ENABLE        FIELD32(0x00080000)
 771 #define BCN_TIME_CFG_BEACON_GEN         FIELD32(0x00100000)
 772 #define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
 773
 774 /*
 775  * TBTT_SYNC_CFG:
 776  * BCN_AIFSN: Beacon AIFSN after TBTT interrupt in slots
 777  * BCN_CWMIN: Beacon CWMin after TBTT interrupt in slots
 778  */
 779 #define TBTT_SYNC_CFG                   0x1118
 780 #define TBTT_SYNC_CFG_TBTT_ADJUST       FIELD32(0x000000ff)
 781 #define TBTT_SYNC_CFG_BCN_EXP_WIN       FIELD32(0x0000ff00)
 782 #define TBTT_SYNC_CFG_BCN_AIFSN         FIELD32(0x000f0000)
 783 #define TBTT_SYNC_CFG_BCN_CWMIN         FIELD32(0x00f00000)
 784
 785 /*
 786  * TSF_TIMER_DW0: Local lsb TSF timer, read-only
 787  */
 788 #define TSF_TIMER_DW0                   0x111c
 789 #define TSF_TIMER_DW0_LOW_WORD          FIELD32(0xffffffff)
 790
 791 /*
 792  * TSF_TIMER_DW1: Local msb TSF timer, read-only
 793  */
 794 #define TSF_TIMER_DW1                   0x1120
 795 #define TSF_TIMER_DW1_HIGH_WORD         FIELD32(0xffffffff)
 796
 797 /*
 798  * TBTT_TIMER: TImer remains till next TBTT, read-only
 799  */
 800 #define TBTT_TIMER                      0x1124
 801
 802 /*
 803  * INT_TIMER_CFG: timer configuration
 804  * PRE_TBTT_TIMER: leadtime to tbtt for pretbtt interrupt in units of 1/16 TU
 805  * GP_TIMER: period of general purpose timer in units of 1/16 TU
 806  */
 807 #define INT_TIMER_CFG                   0x1128
 808 #define INT_TIMER_CFG_PRE_TBTT_TIMER    FIELD32(0x0000ffff)
 809 #define INT_TIMER_CFG_GP_TIMER          FIELD32(0xffff0000)
 810
 811 /*
 812  * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
 813  */
 814 #define INT_TIMER_EN                    0x112c
 815 #define INT_TIMER_EN_PRE_TBTT_TIMER     FIELD32(0x00000001)
 816 #define INT_TIMER_EN_GP_TIMER           FIELD32(0x00000002)
 817
 818 /*
 819  * CH_IDLE_STA: channel idle time (in us)
 820  */
 821 #define CH_IDLE_STA                     0x1130
 822
 823 /*
 824  * CH_BUSY_STA: channel busy time on primary channel (in us)
 825  */
 826 #define CH_BUSY_STA                     0x1134
 827
 828 /*
 829  * CH_BUSY_STA_SEC: channel busy time on secondary channel in HT40 mode (in us)
 830  */
 831 #define CH_BUSY_STA_SEC                 0x1138
 832
 833 /*
 834  * MAC_STATUS_CFG:
 835  * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
 836  *      if 1 or higher one of the 2 registers is busy.
 837  */
 838 #define MAC_STATUS_CFG                  0x1200
 839 #define MAC_STATUS_CFG_BBP_RF_BUSY      FIELD32(0x00000003)
 840
 841 /*
 842  * PWR_PIN_CFG:
 843  */
 844 #define PWR_PIN_CFG                     0x1204
 845
 846 /*
 847  * AUTOWAKEUP_CFG: Manual power control / status register
 848  * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
 849  * AUTOWAKE: 0:sleep, 1:awake
 850  */
 851 #define AUTOWAKEUP_CFG                  0x1208
 852 #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME   FIELD32(0x000000ff)
 853 #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
 854 #define AUTOWAKEUP_CFG_AUTOWAKE         FIELD32(0x00008000)
 855
 856 /*
 857  * EDCA_AC0_CFG:
 858  */
 859 #define EDCA_AC0_CFG                    0x1300
 860 #define EDCA_AC0_CFG_TX_OP              FIELD32(0x000000ff)
 861 #define EDCA_AC0_CFG_AIFSN              FIELD32(0x00000f00)
 862 #define EDCA_AC0_CFG_CWMIN              FIELD32(0x0000f000)
 863 #define EDCA_AC0_CFG_CWMAX              FIELD32(0x000f0000)
 864
 865 /*
 866  * EDCA_AC1_CFG:
 867  */
 868 #define EDCA_AC1_CFG                    0x1304
 869 #define EDCA_AC1_CFG_TX_OP              FIELD32(0x000000ff)
 870 #define EDCA_AC1_CFG_AIFSN              FIELD32(0x00000f00)
 871 #define EDCA_AC1_CFG_CWMIN              FIELD32(0x0000f000)
 872 #define EDCA_AC1_CFG_CWMAX              FIELD32(0x000f0000)
 873
 874 /*
 875  * EDCA_AC2_CFG:
 876  */
 877 #define EDCA_AC2_CFG                    0x1308
 878 #define EDCA_AC2_CFG_TX_OP              FIELD32(0x000000ff)
 879 #define EDCA_AC2_CFG_AIFSN              FIELD32(0x00000f00)
 880 #define EDCA_AC2_CFG_CWMIN              FIELD32(0x0000f000)
 881 #define EDCA_AC2_CFG_CWMAX              FIELD32(0x000f0000)
 882
 883 /*
 884  * EDCA_AC3_CFG:
 885  */
 886 #define EDCA_AC3_CFG                    0x130c
 887 #define EDCA_AC3_CFG_TX_OP              FIELD32(0x000000ff)
 888 #define EDCA_AC3_CFG_AIFSN              FIELD32(0x00000f00)
 889 #define EDCA_AC3_CFG_CWMIN              FIELD32(0x0000f000)
 890 #define EDCA_AC3_CFG_CWMAX              FIELD32(0x000f0000)
 891
 892 /*
 893  * EDCA_TID_AC_MAP:
 894  */
 895 #define EDCA_TID_AC_MAP                 0x1310
 896
 897 /*
 898  * TX_PWR_CFG:
 899  */
 900 #define TX_PWR_CFG_RATE0                FIELD32(0x0000000f)
 901 #define TX_PWR_CFG_RATE1                FIELD32(0x000000f0)
 902 #define TX_PWR_CFG_RATE2                FIELD32(0x00000f00)
 903 #define TX_PWR_CFG_RATE3                FIELD32(0x0000f000)
 904 #define TX_PWR_CFG_RATE4                FIELD32(0x000f0000)
 905 #define TX_PWR_CFG_RATE5                FIELD32(0x00f00000)
 906 #define TX_PWR_CFG_RATE6                FIELD32(0x0f000000)
 907 #define TX_PWR_CFG_RATE7                FIELD32(0xf0000000)
 908
 909 /*
 910  * TX_PWR_CFG_0:
 911  */
 912 #define TX_PWR_CFG_0                    0x1314
 913 #define TX_PWR_CFG_0_1MBS               FIELD32(0x0000000f)
 914 #define TX_PWR_CFG_0_2MBS               FIELD32(0x000000f0)
 915 #define TX_PWR_CFG_0_55MBS              FIELD32(0x00000f00)
 916 #define TX_PWR_CFG_0_11MBS              FIELD32(0x0000f000)
 917 #define TX_PWR_CFG_0_6MBS               FIELD32(0x000f0000)
 918 #define TX_PWR_CFG_0_9MBS               FIELD32(0x00f00000)
 919 #define TX_PWR_CFG_0_12MBS              FIELD32(0x0f000000)
 920 #define TX_PWR_CFG_0_18MBS              FIELD32(0xf0000000)
 921
 922 /*
 923  * TX_PWR_CFG_1:
 924  */
 925 #define TX_PWR_CFG_1                    0x1318
 926 #define TX_PWR_CFG_1_24MBS              FIELD32(0x0000000f)
 927 #define TX_PWR_CFG_1_36MBS              FIELD32(0x000000f0)
 928 #define TX_PWR_CFG_1_48MBS              FIELD32(0x00000f00)
 929 #define TX_PWR_CFG_1_54MBS              FIELD32(0x0000f000)
 930 #define TX_PWR_CFG_1_MCS0               FIELD32(0x000f0000)
 931 #define TX_PWR_CFG_1_MCS1               FIELD32(0x00f00000)
 932 #define TX_PWR_CFG_1_MCS2               FIELD32(0x0f000000)
 933 #define TX_PWR_CFG_1_MCS3               FIELD32(0xf0000000)
 934
 935 /*
 936  * TX_PWR_CFG_2:
 937  */
 938 #define TX_PWR_CFG_2                    0x131c
 939 #define TX_PWR_CFG_2_MCS4               FIELD32(0x0000000f)
 940 #define TX_PWR_CFG_2_MCS5               FIELD32(0x000000f0)
 941 #define TX_PWR_CFG_2_MCS6               FIELD32(0x00000f00)
 942 #define TX_PWR_CFG_2_MCS7               FIELD32(0x0000f000)
 943 #define TX_PWR_CFG_2_MCS8               FIELD32(0x000f0000)
 944 #define TX_PWR_CFG_2_MCS9               FIELD32(0x00f00000)
 945 #define TX_PWR_CFG_2_MCS10              FIELD32(0x0f000000)
 946 #define TX_PWR_CFG_2_MCS11              FIELD32(0xf0000000)
 947
 948 /*
 949  * TX_PWR_CFG_3:
 950  */
 951 #define TX_PWR_CFG_3                    0x1320
 952 #define TX_PWR_CFG_3_MCS12              FIELD32(0x0000000f)
 953 #define TX_PWR_CFG_3_MCS13              FIELD32(0x000000f0)
 954 #define TX_PWR_CFG_3_MCS14              FIELD32(0x00000f00)
 955 #define TX_PWR_CFG_3_MCS15              FIELD32(0x0000f000)
 956 #define TX_PWR_CFG_3_UKNOWN1            FIELD32(0x000f0000)
 957 #define TX_PWR_CFG_3_UKNOWN2            FIELD32(0x00f00000)
 958 #define TX_PWR_CFG_3_UKNOWN3            FIELD32(0x0f000000)
 959 #define TX_PWR_CFG_3_UKNOWN4            FIELD32(0xf0000000)
 960
 961 /*
 962  * TX_PWR_CFG_4:
 963  */
 964 #define TX_PWR_CFG_4                    0x1324
 965 #define TX_PWR_CFG_4_UKNOWN5            FIELD32(0x0000000f)
 966 #define TX_PWR_CFG_4_UKNOWN6            FIELD32(0x000000f0)
 967 #define TX_PWR_CFG_4_UKNOWN7            FIELD32(0x00000f00)
 968 #define TX_PWR_CFG_4_UKNOWN8            FIELD32(0x0000f000)
 969
 970 /*
 971  * TX_PIN_CFG:
 972  */
 973 #define TX_PIN_CFG                      0x1328
 974 #define TX_PIN_CFG_PA_PE_DISABLE        0xfcfffff0
 975 #define TX_PIN_CFG_PA_PE_A0_EN          FIELD32(0x00000001)
 976 #define TX_PIN_CFG_PA_PE_G0_EN          FIELD32(0x00000002)
 977 #define TX_PIN_CFG_PA_PE_A1_EN          FIELD32(0x00000004)
 978 #define TX_PIN_CFG_PA_PE_G1_EN          FIELD32(0x00000008)
 979 #define TX_PIN_CFG_PA_PE_A0_POL         FIELD32(0x00000010)
 980 #define TX_PIN_CFG_PA_PE_G0_POL         FIELD32(0x00000020)
 981 #define TX_PIN_CFG_PA_PE_A1_POL         FIELD32(0x00000040)
 982 #define TX_PIN_CFG_PA_PE_G1_POL         FIELD32(0x00000080)
 983 #define TX_PIN_CFG_LNA_PE_A0_EN         FIELD32(0x00000100)
 984 #define TX_PIN_CFG_LNA_PE_G0_EN         FIELD32(0x00000200)
 985 #define TX_PIN_CFG_LNA_PE_A1_EN         FIELD32(0x00000400)
 986 #define TX_PIN_CFG_LNA_PE_G1_EN         FIELD32(0x00000800)
 987 #define TX_PIN_CFG_LNA_PE_A0_POL        FIELD32(0x00001000)
 988 #define TX_PIN_CFG_LNA_PE_G0_POL        FIELD32(0x00002000)
 989 #define TX_PIN_CFG_LNA_PE_A1_POL        FIELD32(0x00004000)
 990 #define TX_PIN_CFG_LNA_PE_G1_POL        FIELD32(0x00008000)
 991 #define TX_PIN_CFG_RFTR_EN              FIELD32(0x00010000)
 992 #define TX_PIN_CFG_RFTR_POL             FIELD32(0x00020000)
 993 #define TX_PIN_CFG_TRSW_EN              FIELD32(0x00040000)
 994 #define TX_PIN_CFG_TRSW_POL             FIELD32(0x00080000)
 995 #define TX_PIN_CFG_PA_PE_A2_EN          FIELD32(0x01000000)
 996 #define TX_PIN_CFG_PA_PE_G2_EN          FIELD32(0x02000000)
 997 #define TX_PIN_CFG_PA_PE_A2_POL         FIELD32(0x04000000)
 998 #define TX_PIN_CFG_PA_PE_G2_POL         FIELD32(0x08000000)
 999 #define TX_PIN_CFG_LNA_PE_A2_EN         FIELD32(0x10000000)
1000 #define TX_PIN_CFG_LNA_PE_G2_EN         FIELD32(0x20000000)
1001 #define TX_PIN_CFG_LNA_PE_A2_POL        FIELD32(0x40000000)
1002 #define TX_PIN_CFG_LNA_PE_G2_POL        FIELD32(0x80000000)
1003
1004 /*
1005  * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
1006  */
1007 #define TX_BAND_CFG                     0x132c
1008 #define TX_BAND_CFG_HT40_MINUS          FIELD32(0x00000001)
1009 #define TX_BAND_CFG_A                   FIELD32(0x00000002)
1010 #define TX_BAND_CFG_BG                  FIELD32(0x00000004)
1011
1012 /*
1013  * TX_SW_CFG0:
1014  */
1015 #define TX_SW_CFG0                      0x1330
1016
1017 /*
1018  * TX_SW_CFG1:
1019  */
1020 #define TX_SW_CFG1                      0x1334
1021
1022 /*
1023  * TX_SW_CFG2:
1024  */
1025 #define TX_SW_CFG2                      0x1338
1026
1027 /*
1028  * TXOP_THRES_CFG:
1029  */
1030 #define TXOP_THRES_CFG                  0x133c
1031
1032 /*
1033  * TXOP_CTRL_CFG:
1034  * TIMEOUT_TRUN_EN: Enable/Disable TXOP timeout truncation
1035  * AC_TRUN_EN: Enable/Disable truncation for AC change
1036  * TXRATEGRP_TRUN_EN: Enable/Disable truncation for TX rate group change
1037  * USER_MODE_TRUN_EN: Enable/Disable truncation for user TXOP mode
1038  * MIMO_PS_TRUN_EN: Enable/Disable truncation for MIMO PS RTS/CTS
1039  * RESERVED_TRUN_EN: Reserved
1040  * LSIG_TXOP_EN: Enable/Disable L-SIG TXOP protection
1041  * EXT_CCA_EN: Enable/Disable extension channel CCA reference (Defer 40Mhz
1042  *             transmissions if extension CCA is clear).
1043  * EXT_CCA_DLY: Extension CCA signal delay time (unit: us)
1044  * EXT_CWMIN: CwMin for extension channel backoff
1045  *            0: Disabled
1046  *
1047  */
1048 #define TXOP_CTRL_CFG                   0x1340
1049 #define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN   FIELD32(0x00000001)
1050 #define TXOP_CTRL_CFG_AC_TRUN_EN        FIELD32(0x00000002)
1051 #define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN FIELD32(0x00000004)
1052 #define TXOP_CTRL_CFG_USER_MODE_TRUN_EN FIELD32(0x00000008)
1053 #define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN   FIELD32(0x00000010)
1054 #define TXOP_CTRL_CFG_RESERVED_TRUN_EN  FIELD32(0x00000020)
1055 #define TXOP_CTRL_CFG_LSIG_TXOP_EN      FIELD32(0x00000040)
1056 #define TXOP_CTRL_CFG_EXT_CCA_EN        FIELD32(0x00000080)
1057 #define TXOP_CTRL_CFG_EXT_CCA_DLY       FIELD32(0x0000ff00)
1058 #define TXOP_CTRL_CFG_EXT_CWMIN         FIELD32(0x000f0000)
1059
1060 /*
1061  * TX_RTS_CFG:
1062  * RTS_THRES: unit:byte
1063  * RTS_FBK_EN: enable rts rate fallback
1064  */
1065 #define TX_RTS_CFG                      0x1344
1066 #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
1067 #define TX_RTS_CFG_RTS_THRES            FIELD32(0x00ffff00)
1068 #define TX_RTS_CFG_RTS_FBK_EN           FIELD32(0x01000000)
1069
1070 /*
1071  * TX_TIMEOUT_CFG:
1072  * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
1073  * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
1074  * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
1075  *                it is recommended that:
1076  *                (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
1077  */
1078 #define TX_TIMEOUT_CFG                  0x1348
1079 #define TX_TIMEOUT_CFG_MPDU_LIFETIME    FIELD32(0x000000f0)
1080 #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT   FIELD32(0x0000ff00)
1081 #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT    FIELD32(0x00ff0000)
1082
1083 /*
1084  * TX_RTY_CFG:
1085  * SHORT_RTY_LIMIT: short retry limit
1086  * LONG_RTY_LIMIT: long retry limit
1087  * LONG_RTY_THRE: Long retry threshoold
1088  * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
1089  *                   0:expired by retry limit, 1: expired by mpdu life timer
1090  * AGG_RTY_MODE: Aggregate MPDU retry mode
1091  *               0:expired by retry limit, 1: expired by mpdu life timer
1092  * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
1093  */
1094 #define TX_RTY_CFG                      0x134c
1095 #define TX_RTY_CFG_SHORT_RTY_LIMIT      FIELD32(0x000000ff)
1096 #define TX_RTY_CFG_LONG_RTY_LIMIT       FIELD32(0x0000ff00)
1097 #define TX_RTY_CFG_LONG_RTY_THRE        FIELD32(0x0fff0000)
1098 #define TX_RTY_CFG_NON_AGG_RTY_MODE     FIELD32(0x10000000)
1099 #define TX_RTY_CFG_AGG_RTY_MODE         FIELD32(0x20000000)
1100 #define TX_RTY_CFG_TX_AUTO_FB_ENABLE    FIELD32(0x40000000)
1101
1102 /*
1103  * TX_LINK_CFG:
1104  * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
1105  * MFB_ENABLE: TX apply remote MFB 1:enable
1106  * REMOTE_UMFS_ENABLE: remote unsolicit  MFB enable
1107  *                     0: not apply remote remote unsolicit (MFS=7)
1108  * TX_MRQ_EN: MCS request TX enable
1109  * TX_RDG_EN: RDG TX enable
1110  * TX_CF_ACK_EN: Piggyback CF-ACK enable
1111  * REMOTE_MFB: remote MCS feedback
1112  * REMOTE_MFS: remote MCS feedback sequence number
1113  */
1114 #define TX_LINK_CFG                     0x1350
1115 #define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
1116 #define TX_LINK_CFG_MFB_ENABLE          FIELD32(0x00000100)
1117 #define TX_LINK_CFG_REMOTE_UMFS_ENABLE  FIELD32(0x00000200)
1118 #define TX_LINK_CFG_TX_MRQ_EN           FIELD32(0x00000400)
1119 #define TX_LINK_CFG_TX_RDG_EN           FIELD32(0x00000800)
1120 #define TX_LINK_CFG_TX_CF_ACK_EN        FIELD32(0x00001000)
1121 #define TX_LINK_CFG_REMOTE_MFB          FIELD32(0x00ff0000)
1122 #define TX_LINK_CFG_REMOTE_MFS          FIELD32(0xff000000)
1123
1124 /*
1125  * HT_FBK_CFG0:
1126  */
1127 #define HT_FBK_CFG0                     0x1354
1128 #define HT_FBK_CFG0_HTMCS0FBK           FIELD32(0x0000000f)
1129 #define HT_FBK_CFG0_HTMCS1FBK           FIELD32(0x000000f0)
1130 #define HT_FBK_CFG0_HTMCS2FBK           FIELD32(0x00000f00)
1131 #define HT_FBK_CFG0_HTMCS3FBK           FIELD32(0x0000f000)
1132 #define HT_FBK_CFG0_HTMCS4FBK           FIELD32(0x000f0000)
1133 #define HT_FBK_CFG0_HTMCS5FBK           FIELD32(0x00f00000)
1134 #define HT_FBK_CFG0_HTMCS6FBK           FIELD32(0x0f000000)
1135 #define HT_FBK_CFG0_HTMCS7FBK           FIELD32(0xf0000000)
1136
1137 /*
1138  * HT_FBK_CFG1:
1139  */
1140 #define HT_FBK_CFG1                     0x1358
1141 #define HT_FBK_CFG1_HTMCS8FBK           FIELD32(0x0000000f)
1142 #define HT_FBK_CFG1_HTMCS9FBK           FIELD32(0x000000f0)
1143 #define HT_FBK_CFG1_HTMCS10FBK          FIELD32(0x00000f00)
1144 #define HT_FBK_CFG1_HTMCS11FBK          FIELD32(0x0000f000)
1145 #define HT_FBK_CFG1_HTMCS12FBK          FIELD32(0x000f0000)
1146 #define HT_FBK_CFG1_HTMCS13FBK          FIELD32(0x00f00000)
1147 #define HT_FBK_CFG1_HTMCS14FBK          FIELD32(0x0f000000)
1148 #define HT_FBK_CFG1_HTMCS15FBK          FIELD32(0xf0000000)
1149
1150 /*
1151  * LG_FBK_CFG0:
1152  */
1153 #define LG_FBK_CFG0                     0x135c
1154 #define LG_FBK_CFG0_OFDMMCS0FBK         FIELD32(0x0000000f)
1155 #define LG_FBK_CFG0_OFDMMCS1FBK         FIELD32(0x000000f0)
1156 #define LG_FBK_CFG0_OFDMMCS2FBK         FIELD32(0x00000f00)
1157 #define LG_FBK_CFG0_OFDMMCS3FBK         FIELD32(0x0000f000)
1158 #define LG_FBK_CFG0_OFDMMCS4FBK         FIELD32(0x000f0000)
1159 #define LG_FBK_CFG0_OFDMMCS5FBK         FIELD32(0x00f00000)
1160 #define LG_FBK_CFG0_OFDMMCS6FBK         FIELD32(0x0f000000)
1161 #define LG_FBK_CFG0_OFDMMCS7FBK         FIELD32(0xf0000000)
1162
1163 /*
1164  * LG_FBK_CFG1:
1165  */
1166 #define LG_FBK_CFG1                     0x1360
1167 #define LG_FBK_CFG0_CCKMCS0FBK          FIELD32(0x0000000f)
1168 #define LG_FBK_CFG0_CCKMCS1FBK          FIELD32(0x000000f0)
1169 #define LG_FBK_CFG0_CCKMCS2FBK          FIELD32(0x00000f00)
1170 #define LG_FBK_CFG0_CCKMCS3FBK          FIELD32(0x0000f000)
1171
1172 /*
1173  * CCK_PROT_CFG: CCK Protection
1174  * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
1175  * PROTECT_CTRL: Protection control frame type for CCK TX
1176  *               0:none, 1:RTS/CTS, 2:CTS-to-self
1177  * PROTECT_NAV_SHORT: TXOP protection type for CCK TX with short NAV
1178  * PROTECT_NAV_LONG: TXOP protection type for CCK TX with long NAV
1179  * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
1180  * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
1181  * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
1182  * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
1183  * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
1184  * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
1185  * RTS_TH_EN: RTS threshold enable on CCK TX
1186  */
1187 #define CCK_PROT_CFG                    0x1364
1188 #define CCK_PROT_CFG_PROTECT_RATE       FIELD32(0x0000ffff)
1189 #define CCK_PROT_CFG_PROTECT_CTRL       FIELD32(0x00030000)
1190 #define CCK_PROT_CFG_PROTECT_NAV_SHORT  FIELD32(0x00040000)
1191 #define CCK_PROT_CFG_PROTECT_NAV_LONG   FIELD32(0x00080000)
1192 #define CCK_PROT_CFG_TX_OP_ALLOW_CCK    FIELD32(0x00100000)
1193 #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM   FIELD32(0x00200000)
1194 #define CCK_PROT_CFG_TX_OP_ALLOW_MM20   FIELD32(0x00400000)
1195 #define CCK_PROT_CFG_TX_OP_ALLOW_MM40   FIELD32(0x00800000)
1196 #define CCK_PROT_CFG_TX_OP_ALLOW_GF20   FIELD32(0x01000000)
1197 #define CCK_PROT_CFG_TX_OP_ALLOW_GF40   FIELD32(0x02000000)
1198 #define CCK_PROT_CFG_RTS_TH_EN          FIELD32(0x04000000)
1199
1200 /*
1201  * OFDM_PROT_CFG: OFDM Protection
1202  */
1203 #define OFDM_PROT_CFG                   0x1368
1204 #define OFDM_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
1205 #define OFDM_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
1206 #define OFDM_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1207 #define OFDM_PROT_CFG_PROTECT_NAV_LONG  FIELD32(0x00080000)
1208 #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
1209 #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
1210 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
1211 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
1212 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
1213 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
1214 #define OFDM_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
1215
1216 /*
1217  * MM20_PROT_CFG: MM20 Protection
1218  */
1219 #define MM20_PROT_CFG                   0x136c
1220 #define MM20_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
1221 #define MM20_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
1222 #define MM20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1223 #define MM20_PROT_CFG_PROTECT_NAV_LONG  FIELD32(0x00080000)
1224 #define MM20_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
1225 #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
1226 #define MM20_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
1227 #define MM20_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
1228 #define MM20_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
1229 #define MM20_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
1230 #define MM20_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
1231
1232 /*
1233  * MM40_PROT_CFG: MM40 Protection
1234  */
1235 #define MM40_PROT_CFG                   0x1370
1236 #define MM40_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
1237 #define MM40_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
1238 #define MM40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1239 #define MM40_PROT_CFG_PROTECT_NAV_LONG  FIELD32(0x00080000)
1240 #define MM40_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
1241 #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
1242 #define MM40_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
1243 #define MM40_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
1244 #define MM40_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
1245 #define MM40_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
1246 #define MM40_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
1247
1248 /*
1249  * GF20_PROT_CFG: GF20 Protection
1250  */
1251 #define GF20_PROT_CFG                   0x1374
1252 #define GF20_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
1253 #define GF20_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
1254 #define GF20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1255 #define GF20_PROT_CFG_PROTECT_NAV_LONG  FIELD32(0x00080000)
1256 #define GF20_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
1257 #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
1258 #define GF20_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
1259 #define GF20_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
1260 #define GF20_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
1261 #define GF20_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
1262 #define GF20_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
1263
1264 /*
1265  * GF40_PROT_CFG: GF40 Protection
1266  */
1267 #define GF40_PROT_CFG                   0x1378
1268 #define GF40_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
1269 #define GF40_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
1270 #define GF40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1271 #define GF40_PROT_CFG_PROTECT_NAV_LONG  FIELD32(0x00080000)
1272 #define GF40_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
1273 #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
1274 #define GF40_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
1275 #define GF40_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
1276 #define GF40_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
1277 #define GF40_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
1278 #define GF40_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
1279
1280 /*
1281  * EXP_CTS_TIME:
1282  */
1283 #define EXP_CTS_TIME                    0x137c
1284
1285 /*
1286  * EXP_ACK_TIME:
1287  */
1288 #define EXP_ACK_TIME                    0x1380
1289
1290 /*
1291  * RX_FILTER_CFG: RX configuration register.
1292  */
1293 #define RX_FILTER_CFG                   0x1400
1294 #define RX_FILTER_CFG_DROP_CRC_ERROR    FIELD32(0x00000001)
1295 #define RX_FILTER_CFG_DROP_PHY_ERROR    FIELD32(0x00000002)
1296 #define RX_FILTER_CFG_DROP_NOT_TO_ME    FIELD32(0x00000004)
1297 #define RX_FILTER_CFG_DROP_NOT_MY_BSSD  FIELD32(0x00000008)
1298 #define RX_FILTER_CFG_DROP_VER_ERROR    FIELD32(0x00000010)
1299 #define RX_FILTER_CFG_DROP_MULTICAST    FIELD32(0x00000020)
1300 #define RX_FILTER_CFG_DROP_BROADCAST    FIELD32(0x00000040)
1301 #define RX_FILTER_CFG_DROP_DUPLICATE    FIELD32(0x00000080)
1302 #define RX_FILTER_CFG_DROP_CF_END_ACK   FIELD32(0x00000100)
1303 #define RX_FILTER_CFG_DROP_CF_END       FIELD32(0x00000200)
1304 #define RX_FILTER_CFG_DROP_ACK          FIELD32(0x00000400)
1305 #define RX_FILTER_CFG_DROP_CTS          FIELD32(0x00000800)
1306 #define RX_FILTER_CFG_DROP_RTS          FIELD32(0x00001000)
1307 #define RX_FILTER_CFG_DROP_PSPOLL       FIELD32(0x00002000)
1308 #define RX_FILTER_CFG_DROP_BA           FIELD32(0x00004000)
1309 #define RX_FILTER_CFG_DROP_BAR          FIELD32(0x00008000)
1310 #define RX_FILTER_CFG_DROP_CNTL         FIELD32(0x00010000)
1311
1312 /*
1313  * AUTO_RSP_CFG:
1314  * AUTORESPONDER: 0: disable, 1: enable
1315  * BAC_ACK_POLICY: 0:long, 1:short preamble
1316  * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1317  * CTS_40_MREF: Response CTS 40MHz duplicate mode
1318  * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1319  * DUAL_CTS_EN: Power bit value in control frame
1320  * ACK_CTS_PSM_BIT:Power bit value in control frame
1321  */
1322 #define AUTO_RSP_CFG                    0x1404
1323 #define AUTO_RSP_CFG_AUTORESPONDER      FIELD32(0x00000001)
1324 #define AUTO_RSP_CFG_BAC_ACK_POLICY     FIELD32(0x00000002)
1325 #define AUTO_RSP_CFG_CTS_40_MMODE       FIELD32(0x00000004)
1326 #define AUTO_RSP_CFG_CTS_40_MREF        FIELD32(0x00000008)
1327 #define AUTO_RSP_CFG_AR_PREAMBLE        FIELD32(0x00000010)
1328 #define AUTO_RSP_CFG_DUAL_CTS_EN        FIELD32(0x00000040)
1329 #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT    FIELD32(0x00000080)
1330
1331 /*
1332  * LEGACY_BASIC_RATE:
1333  */
1334 #define LEGACY_BASIC_RATE               0x1408
1335
1336 /*
1337  * HT_BASIC_RATE:
1338  */
1339 #define HT_BASIC_RATE                   0x140c
1340
1341 /*
1342  * HT_CTRL_CFG:
1343  */
1344 #define HT_CTRL_CFG                     0x1410
1345
1346 /*
1347  * SIFS_COST_CFG:
1348  */
1349 #define SIFS_COST_CFG                   0x1414
1350
1351 /*
1352  * RX_PARSER_CFG:
1353  * Set NAV for all received frames
1354  */
1355 #define RX_PARSER_CFG                   0x1418
1356
1357 /*
1358  * TX_SEC_CNT0:
1359  */
1360 #define TX_SEC_CNT0                     0x1500
1361
1362 /*
1363  * RX_SEC_CNT0:
1364  */
1365 #define RX_SEC_CNT0                     0x1504
1366
1367 /*
1368  * CCMP_FC_MUTE:
1369  */
1370 #define CCMP_FC_MUTE                    0x1508
1371
1372 /*
1373  * TXOP_HLDR_ADDR0:
1374  */
1375 #define TXOP_HLDR_ADDR0                 0x1600
1376
1377 /*
1378  * TXOP_HLDR_ADDR1:
1379  */
1380 #define TXOP_HLDR_ADDR1                 0x1604
1381
1382 /*
1383  * TXOP_HLDR_ET:
1384  */
1385 #define TXOP_HLDR_ET                    0x1608
1386
1387 /*
1388  * QOS_CFPOLL_RA_DW0:
1389  */
1390 #define QOS_CFPOLL_RA_DW0               0x160c
1391
1392 /*
1393  * QOS_CFPOLL_RA_DW1:
1394  */
1395 #define QOS_CFPOLL_RA_DW1               0x1610
1396
1397 /*
1398  * QOS_CFPOLL_QC:
1399  */
1400 #define QOS_CFPOLL_QC                   0x1614
1401
1402 /*
1403  * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1404  */
1405 #define RX_STA_CNT0                     0x1700
1406 #define RX_STA_CNT0_CRC_ERR             FIELD32(0x0000ffff)
1407 #define RX_STA_CNT0_PHY_ERR             FIELD32(0xffff0000)
1408
1409 /*
1410  * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1411  */
1412 #define RX_STA_CNT1                     0x1704
1413 #define RX_STA_CNT1_FALSE_CCA           FIELD32(0x0000ffff)
1414 #define RX_STA_CNT1_PLCP_ERR            FIELD32(0xffff0000)
1415
1416 /*
1417  * RX_STA_CNT2:
1418  */
1419 #define RX_STA_CNT2                     0x1708
1420 #define RX_STA_CNT2_RX_DUPLI_COUNT      FIELD32(0x0000ffff)
1421 #define RX_STA_CNT2_RX_FIFO_OVERFLOW    FIELD32(0xffff0000)
1422
1423 /*
1424  * TX_STA_CNT0: TX Beacon count
1425  */
1426 #define TX_STA_CNT0                     0x170c
1427 #define TX_STA_CNT0_TX_FAIL_COUNT       FIELD32(0x0000ffff)
1428 #define TX_STA_CNT0_TX_BEACON_COUNT     FIELD32(0xffff0000)
1429
1430 /*
1431  * TX_STA_CNT1: TX tx count
1432  */
1433 #define TX_STA_CNT1                     0x1710
1434 #define TX_STA_CNT1_TX_SUCCESS          FIELD32(0x0000ffff)
1435 #define TX_STA_CNT1_TX_RETRANSMIT       FIELD32(0xffff0000)
1436
1437 /*
1438  * TX_STA_CNT2: TX tx count
1439  */
1440 #define TX_STA_CNT2                     0x1714
1441 #define TX_STA_CNT2_TX_ZERO_LEN_COUNT   FIELD32(0x0000ffff)
1442 #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1443
1444 /*
1445  * TX_STA_FIFO: TX Result for specific PID status fifo register.
1446  *
1447  * This register is implemented as FIFO with 16 entries in the HW. Each
1448  * register read fetches the next tx result. If the FIFO is full because
1449  * it wasn't read fast enough after the according interrupt (TX_FIFO_STATUS)
1450  * triggered, the hw seems to simply drop further tx results.
1451  *
1452  * VALID: 1: this tx result is valid
1453  *        0: no valid tx result -> driver should stop reading
1454  * PID_TYPE: The PID latched from the PID field in the TXWI, can be used
1455  *           to match a frame with its tx result (even though the PID is
1456  *           only 4 bits wide).
1457  * PID_QUEUE: Part of PID_TYPE, this is the queue index number (0-3)
1458  * PID_ENTRY: Part of PID_TYPE, this is the queue entry index number (1-3)
1459  *            This identification number is calculated by ((idx % 3) + 1).
1460  * TX_SUCCESS: Indicates tx success (1) or failure (0)
1461  * TX_AGGRE: Indicates if the frame was part of an aggregate (1) or not (0)
1462  * TX_ACK_REQUIRED: Indicates if the frame needed to get ack'ed (1) or not (0)
1463  * WCID: The wireless client ID.
1464  * MCS: The tx rate used during the last transmission of this frame, be it
1465  *      successful or not.
1466  * PHYMODE: The phymode used for the transmission.
1467  */
1468 #define TX_STA_FIFO                     0x1718
1469 #define TX_STA_FIFO_VALID               FIELD32(0x00000001)
1470 #define TX_STA_FIFO_PID_TYPE            FIELD32(0x0000001e)
1471 #define TX_STA_FIFO_PID_QUEUE           FIELD32(0x00000006)
1472 #define TX_STA_FIFO_PID_ENTRY           FIELD32(0x00000018)
1473 #define TX_STA_FIFO_TX_SUCCESS          FIELD32(0x00000020)
1474 #define TX_STA_FIFO_TX_AGGRE            FIELD32(0x00000040)
1475 #define TX_STA_FIFO_TX_ACK_REQUIRED     FIELD32(0x00000080)
1476 #define TX_STA_FIFO_WCID                FIELD32(0x0000ff00)
1477 #define TX_STA_FIFO_SUCCESS_RATE        FIELD32(0xffff0000)
1478 #define TX_STA_FIFO_MCS                 FIELD32(0x007f0000)
1479 #define TX_STA_FIFO_PHYMODE             FIELD32(0xc0000000)
1480
1481 /*
1482  * TX_AGG_CNT: Debug counter
1483  */
1484 #define TX_AGG_CNT                      0x171c
1485 #define TX_AGG_CNT_NON_AGG_TX_COUNT     FIELD32(0x0000ffff)
1486 #define TX_AGG_CNT_AGG_TX_COUNT         FIELD32(0xffff0000)
1487
1488 /*
1489  * TX_AGG_CNT0:
1490  */
1491 #define TX_AGG_CNT0                     0x1720
1492 #define TX_AGG_CNT0_AGG_SIZE_1_COUNT    FIELD32(0x0000ffff)
1493 #define TX_AGG_CNT0_AGG_SIZE_2_COUNT    FIELD32(0xffff0000)
1494
1495 /*
1496  * TX_AGG_CNT1:
1497  */
1498 #define TX_AGG_CNT1                     0x1724
1499 #define TX_AGG_CNT1_AGG_SIZE_3_COUNT    FIELD32(0x0000ffff)
1500 #define TX_AGG_CNT1_AGG_SIZE_4_COUNT    FIELD32(0xffff0000)
1501
1502 /*
1503  * TX_AGG_CNT2:
1504  */
1505 #define TX_AGG_CNT2                     0x1728
1506 #define TX_AGG_CNT2_AGG_SIZE_5_COUNT    FIELD32(0x0000ffff)
1507 #define TX_AGG_CNT2_AGG_SIZE_6_COUNT    FIELD32(0xffff0000)
1508
1509 /*
1510  * TX_AGG_CNT3:
1511  */
1512 #define TX_AGG_CNT3                     0x172c
1513 #define TX_AGG_CNT3_AGG_SIZE_7_COUNT    FIELD32(0x0000ffff)
1514 #define TX_AGG_CNT3_AGG_SIZE_8_COUNT    FIELD32(0xffff0000)
1515
1516 /*
1517  * TX_AGG_CNT4:
1518  */
1519 #define TX_AGG_CNT4                     0x1730
1520 #define TX_AGG_CNT4_AGG_SIZE_9_COUNT    FIELD32(0x0000ffff)
1521 #define TX_AGG_CNT4_AGG_SIZE_10_COUNT   FIELD32(0xffff0000)
1522
1523 /*
1524  * TX_AGG_CNT5:
1525  */
1526 #define TX_AGG_CNT5                     0x1734
1527 #define TX_AGG_CNT5_AGG_SIZE_11_COUNT   FIELD32(0x0000ffff)
1528 #define TX_AGG_CNT5_AGG_SIZE_12_COUNT   FIELD32(0xffff0000)
1529
1530 /*
1531  * TX_AGG_CNT6:
1532  */
1533 #define TX_AGG_CNT6                     0x1738
1534 #define TX_AGG_CNT6_AGG_SIZE_13_COUNT   FIELD32(0x0000ffff)
1535 #define TX_AGG_CNT6_AGG_SIZE_14_COUNT   FIELD32(0xffff0000)
1536
1537 /*
1538  * TX_AGG_CNT7:
1539  */
1540 #define TX_AGG_CNT7                     0x173c
1541 #define TX_AGG_CNT7_AGG_SIZE_15_COUNT   FIELD32(0x0000ffff)
1542 #define TX_AGG_CNT7_AGG_SIZE_16_COUNT   FIELD32(0xffff0000)
1543
1544 /*
1545  * MPDU_DENSITY_CNT:
1546  * TX_ZERO_DEL: TX zero length delimiter count
1547  * RX_ZERO_DEL: RX zero length delimiter count
1548  */
1549 #define MPDU_DENSITY_CNT                0x1740
1550 #define MPDU_DENSITY_CNT_TX_ZERO_DEL    FIELD32(0x0000ffff)
1551 #define MPDU_DENSITY_CNT_RX_ZERO_DEL    FIELD32(0xffff0000)
1552
1553 /*
1554  * Security key table memory.
1555  *
1556  * The pairwise key table shares some memory with the beacon frame
1557  * buffers 6 and 7. That basically means that when beacon 6 & 7
1558  * are used we should only use the reduced pairwise key table which
1559  * has a maximum of 222 entries.
1560  *
1561  * ---------------------------------------------
1562  * |0x4000 | Pairwise Key   | Reduced Pairwise |
1563  * |       | Table          | Key Table        |
1564  * |       | Size: 256 * 32 | Size: 222 * 32   |
1565  * |0x5BC0 |                |-------------------
1566  * |       |                | Beacon 6         |
1567  * |0x5DC0 |                |-------------------
1568  * |       |                | Beacon 7         |
1569  * |0x5FC0 |                |-------------------
1570  * |0x5FFF |                |
1571  * --------------------------
1572  *
1573  * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1574  * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1575  * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
1576  * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
1577  * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
1578  * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
1579  */
1580 #define MAC_WCID_BASE                   0x1800
1581 #define PAIRWISE_KEY_TABLE_BASE         0x4000
1582 #define MAC_IVEIV_TABLE_BASE            0x6000
1583 #define MAC_WCID_ATTRIBUTE_BASE         0x6800
1584 #define SHARED_KEY_TABLE_BASE           0x6c00
1585 #define SHARED_KEY_MODE_BASE            0x7000
1586
1587 #define MAC_WCID_ENTRY(__idx) \
1588         (MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)))
1589 #define PAIRWISE_KEY_ENTRY(__idx) \
1590         (PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
1591 #define MAC_IVEIV_ENTRY(__idx) \
1592         (MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)))
1593 #define MAC_WCID_ATTR_ENTRY(__idx) \
1594         (MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)))
1595 #define SHARED_KEY_ENTRY(__idx) \
1596         (SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
1597 #define SHARED_KEY_MODE_ENTRY(__idx) \
1598         (SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)))
1599
1600 struct mac_wcid_entry {
1601         u8 mac[6];
1602         u8 reserved[2];
1603 } __packed;
1604
1605 struct hw_key_entry {
1606         u8 key[16];
1607         u8 tx_mic[8];
1608         u8 rx_mic[8];
1609 } __packed;
1610
1611 struct mac_iveiv_entry {
1612         u8 iv[8];
1613 } __packed;
1614
1615 /*
1616  * MAC_WCID_ATTRIBUTE:
1617  */
1618 #define MAC_WCID_ATTRIBUTE_KEYTAB       FIELD32(0x00000001)
1619 #define MAC_WCID_ATTRIBUTE_CIPHER       FIELD32(0x0000000e)
1620 #define MAC_WCID_ATTRIBUTE_BSS_IDX      FIELD32(0x00000070)
1621 #define MAC_WCID_ATTRIBUTE_RX_WIUDF     FIELD32(0x00000380)
1622 #define MAC_WCID_ATTRIBUTE_CIPHER_EXT   FIELD32(0x00000400)
1623 #define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT  FIELD32(0x00000800)
1624 #define MAC_WCID_ATTRIBUTE_WAPI_MCBC    FIELD32(0x00008000)
1625 #define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000)
1626
1627 /*
1628  * SHARED_KEY_MODE:
1629  */
1630 #define SHARED_KEY_MODE_BSS0_KEY0       FIELD32(0x00000007)
1631 #define SHARED_KEY_MODE_BSS0_KEY1       FIELD32(0x00000070)
1632 #define SHARED_KEY_MODE_BSS0_KEY2       FIELD32(0x00000700)
1633 #define SHARED_KEY_MODE_BSS0_KEY3       FIELD32(0x00007000)
1634 #define SHARED_KEY_MODE_BSS1_KEY0       FIELD32(0x00070000)
1635 #define SHARED_KEY_MODE_BSS1_KEY1       FIELD32(0x00700000)
1636 #define SHARED_KEY_MODE_BSS1_KEY2       FIELD32(0x07000000)
1637 #define SHARED_KEY_MODE_BSS1_KEY3       FIELD32(0x70000000)
1638
1639 /*
1640  * HOST-MCU communication
1641  */
1642
1643 /*
1644  * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
1645  * CMD_TOKEN: Command id, 0xff disable status reporting.
1646  */
1647 #define H2M_MAILBOX_CSR                 0x7010
1648 #define H2M_MAILBOX_CSR_ARG0            FIELD32(0x000000ff)
1649 #define H2M_MAILBOX_CSR_ARG1            FIELD32(0x0000ff00)
1650 #define H2M_MAILBOX_CSR_CMD_TOKEN       FIELD32(0x00ff0000)
1651 #define H2M_MAILBOX_CSR_OWNER           FIELD32(0xff000000)
1652
1653 /*
1654  * H2M_MAILBOX_CID:
1655  * Free slots contain 0xff. MCU will store command's token to lowest free slot.
1656  * If all slots are occupied status will be dropped.
1657  */
1658 #define H2M_MAILBOX_CID                 0x7014
1659 #define H2M_MAILBOX_CID_CMD0            FIELD32(0x000000ff)
1660 #define H2M_MAILBOX_CID_CMD1            FIELD32(0x0000ff00)
1661 #define H2M_MAILBOX_CID_CMD2            FIELD32(0x00ff0000)
1662 #define H2M_MAILBOX_CID_CMD3            FIELD32(0xff000000)
1663
1664 /*
1665  * H2M_MAILBOX_STATUS:
1666  * Command status will be saved to same slot as command id.
1667  */
1668 #define H2M_MAILBOX_STATUS              0x701c
1669
1670 /*
1671  * H2M_INT_SRC:
1672  */
1673 #define H2M_INT_SRC                     0x7024
1674
1675 /*
1676  * H2M_BBP_AGENT:
1677  */
1678 #define H2M_BBP_AGENT                   0x7028
1679
1680 /*
1681  * MCU_LEDCS: LED control for MCU Mailbox.
1682  */
1683 #define MCU_LEDCS_LED_MODE              FIELD8(0x1f)
1684 #define MCU_LEDCS_POLARITY              FIELD8(0x01)
1685
1686 /*
1687  * HW_CS_CTS_BASE:
1688  * Carrier-sense CTS frame base address.
1689  * It's where mac stores carrier-sense frame for carrier-sense function.
1690  */
1691 #define HW_CS_CTS_BASE                  0x7700
1692
1693 /*
1694  * HW_DFS_CTS_BASE:
1695  * DFS CTS frame base address. It's where mac stores CTS frame for DFS.
1696  */
1697 #define HW_DFS_CTS_BASE                 0x7780
1698
1699 /*
1700  * TXRX control registers - base address 0x3000
1701  */
1702
1703 /*
1704  * TXRX_CSR1:
1705  * rt2860b  UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1706  */
1707 #define TXRX_CSR1                       0x77d0
1708
1709 /*
1710  * HW_DEBUG_SETTING_BASE:
1711  * since NULL frame won't be that long (256 byte)
1712  * We steal 16 tail bytes to save debugging settings
1713  */
1714 #define HW_DEBUG_SETTING_BASE           0x77f0
1715 #define HW_DEBUG_SETTING_BASE2          0x7770
1716
1717 /*
1718  * HW_BEACON_BASE
1719  * In order to support maximum 8 MBSS and its maximum length
1720  * is 512 bytes for each beacon
1721  * Three section discontinue memory segments will be used.
1722  * 1. The original region for BCN 0~3
1723  * 2. Extract memory from FCE table for BCN 4~5
1724  * 3. Extract memory from Pair-wise key table for BCN 6~7
1725  *    It occupied those memory of wcid 238~253 for BCN 6
1726  *    and wcid 222~237 for BCN 7 (see Security key table memory
1727  *    for more info).
1728  *
1729  * IMPORTANT NOTE: Not sure why legacy driver does this,
1730  * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
1731  */
1732 #define HW_BEACON_BASE0                 0x7800
1733 #define HW_BEACON_BASE1                 0x7a00
1734 #define HW_BEACON_BASE2                 0x7c00
1735 #define HW_BEACON_BASE3                 0x7e00
1736 #define HW_BEACON_BASE4                 0x7200
1737 #define HW_BEACON_BASE5                 0x7400
1738 #define HW_BEACON_BASE6                 0x5dc0
1739 #define HW_BEACON_BASE7                 0x5bc0
1740
1741 #define HW_BEACON_OFFSET(__index) \
1742         (((__index) < 4) ? (HW_BEACON_BASE0 + (__index * 0x0200)) : \
1743           (((__index) < 6) ? (HW_BEACON_BASE4 + ((__index - 4) * 0x0200)) : \
1744           (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))))
1745
1746 /*
1747  * BBP registers.
1748  * The wordsize of the BBP is 8 bits.
1749  */
1750
1751 /*
1752  * BBP 1: TX Antenna & Power Control
1753  * POWER_CTRL:
1754  * 0 - normal,
1755  * 1 - drop tx power by 6dBm,
1756  * 2 - drop tx power by 12dBm,
1757  * 3 - increase tx power by 6dBm
1758  */
1759 #define BBP1_TX_POWER_CTRL              FIELD8(0x07)
1760 #define BBP1_TX_ANTENNA                 FIELD8(0x18)
1761
1762 /*
1763  * BBP 3: RX Antenna
1764  */
1765 #define BBP3_RX_ADC                             FIELD8(0x03)
1766 #define BBP3_RX_ANTENNA                 FIELD8(0x18)
1767 #define BBP3_HT40_MINUS                 FIELD8(0x20)
1768
1769 /*
1770  * BBP 4: Bandwidth
1771  */
1772 #define BBP4_TX_BF                      FIELD8(0x01)
1773 #define BBP4_BANDWIDTH                  FIELD8(0x18)
1774 #define BBP4_MAC_IF_CTRL                FIELD8(0x40)
1775
1776 /*
1777  * BBP 109
1778  */
1779 #define BBP109_TX0_POWER                FIELD8(0x0f)
1780 #define BBP109_TX1_POWER                FIELD8(0xf0)
1781
1782 /*
1783  * BBP 138: Unknown
1784  */
1785 #define BBP138_RX_ADC1                  FIELD8(0x02)
1786 #define BBP138_RX_ADC2                  FIELD8(0x04)
1787 #define BBP138_TX_DAC1                  FIELD8(0x20)
1788 #define BBP138_TX_DAC2                  FIELD8(0x40)
1789
1790 /*
1791  * BBP 152: Rx Ant
1792  */
1793 #define BBP152_RX_DEFAULT_ANT           FIELD8(0x80)
1794
1795 /*
1796  * RFCSR registers
1797  * The wordsize of the RFCSR is 8 bits.
1798  */
1799
1800 /*
1801  * RFCSR 1:
1802  */
1803 #define RFCSR1_RF_BLOCK_EN              FIELD8(0x01)
1804 #define RFCSR1_PLL_PD                   FIELD8(0x02)
1805 #define RFCSR1_RX0_PD                   FIELD8(0x04)
1806 #define RFCSR1_TX0_PD                   FIELD8(0x08)
1807 #define RFCSR1_RX1_PD                   FIELD8(0x10)
1808 #define RFCSR1_TX1_PD                   FIELD8(0x20)
1809 #define RFCSR1_RX2_PD                   FIELD8(0x40)
1810 #define RFCSR1_TX2_PD                   FIELD8(0x80)
1811
1812 /*
1813  * RFCSR 2:
1814  */
1815 #define RFCSR2_RESCAL_EN                FIELD8(0x80)
1816
1817 /*
1818  * RFCSR 3:
1819  */
1820 #define RFCSR3_K                        FIELD8(0x0f)
1821 /* Bits [7-4] for RF3320 (RT3370/RT3390), on other chipsets reserved */
1822 #define RFCSR3_PA1_BIAS_CCK             FIELD8(0x70);
1823 #define RFCSR3_PA2_CASCODE_BIAS_CCKK    FIELD8(0x80);
1824
1825 /*
1826  * FRCSR 5:
1827  */
1828 #define RFCSR5_R1                       FIELD8(0x0c)
1829
1830 /*
1831  * RFCSR 6:
1832  */
1833 #define RFCSR6_R1                       FIELD8(0x03)
1834 #define RFCSR6_R2                       FIELD8(0x40)
1835 #define RFCSR6_TXDIV            FIELD8(0x0c)
1836
1837 /*
1838  * RFCSR 7:
1839  */
1840 #define RFCSR7_RF_TUNING                FIELD8(0x01)
1841 #define RFCSR7_BIT1                     FIELD8(0x02)
1842 #define RFCSR7_BIT2                     FIELD8(0x04)
1843 #define RFCSR7_BIT3                     FIELD8(0x08)
1844 #define RFCSR7_BIT4                     FIELD8(0x10)
1845 #define RFCSR7_BIT5                     FIELD8(0x20)
1846 #define RFCSR7_BITS67                   FIELD8(0xc0)
1847
1848 /*
1849  * RFCSR 11:
1850  */
1851 #define RFCSR11_R                       FIELD8(0x03)
1852
1853 /*
1854  * RFCSR 12:
1855  */
1856 #define RFCSR12_TX_POWER                FIELD8(0x1f)
1857 #define RFCSR12_DR0                             FIELD8(0xe0)
1858
1859 /*
1860  * RFCSR 13:
1861  */
1862 #define RFCSR13_TX_POWER                FIELD8(0x1f)
1863 #define RFCSR13_DR0                             FIELD8(0xe0)
1864
1865 /*
1866  * RFCSR 15:
1867  */
1868 #define RFCSR15_TX_LO2_EN               FIELD8(0x08)
1869
1870 /*
1871  * RFCSR 16:
1872  */
1873 #define RFCSR16_TXMIXER_GAIN            FIELD8(0x07)
1874
1875 /*
1876  * RFCSR 17:
1877  */
1878 #define RFCSR17_TXMIXER_GAIN            FIELD8(0x07)
1879 #define RFCSR17_TX_LO1_EN               FIELD8(0x08)
1880 #define RFCSR17_R                       FIELD8(0x20)
1881 #define RFCSR17_CODE                   FIELD8(0x7f)
1882
1883 /*
1884  * RFCSR 20:
1885  */
1886 #define RFCSR20_RX_LO1_EN               FIELD8(0x08)
1887
1888 /*
1889  * RFCSR 21:
1890  */
1891 #define RFCSR21_RX_LO2_EN               FIELD8(0x08)
1892
1893 /*
1894  * RFCSR 22:
1895  */
1896 #define RFCSR22_BASEBAND_LOOPBACK       FIELD8(0x01)
1897
1898 /*
1899  * RFCSR 23:
1900  */
1901 #define RFCSR23_FREQ_OFFSET             FIELD8(0x7f)
1902
1903 /*
1904  * RFCSR 24:
1905  */
1906 #define RFCSR24_TX_AGC_FC               FIELD8(0x1f)
1907 #define RFCSR24_TX_H20M                 FIELD8(0x20)
1908 #define RFCSR24_TX_CALIB                FIELD8(0x7f)
1909
1910 /*
1911  * RFCSR 27:
1912  */
1913 #define RFCSR27_R1                      FIELD8(0x03)
1914 #define RFCSR27_R2                      FIELD8(0x04)
1915 #define RFCSR27_R3                      FIELD8(0x30)
1916 #define RFCSR27_R4                      FIELD8(0x40)
1917
1918 /*
1919  * RFCSR 30:
1920  */
1921 #define RFCSR30_TX_H20M                 FIELD8(0x02)
1922 #define RFCSR30_RX_H20M                 FIELD8(0x04)
1923 #define RFCSR30_RX_VCM                  FIELD8(0x18)
1924 #define RFCSR30_RF_CALIBRATION          FIELD8(0x80)
1925
1926 /*
1927  * RFCSR 31:
1928  */
1929 #define RFCSR31_RX_AGC_FC               FIELD8(0x1f)
1930 #define RFCSR31_RX_H20M                 FIELD8(0x20)
1931 #define RFCSR31_RX_CALIB                FIELD8(0x7f)
1932
1933 /*
1934  * RFCSR 38:
1935  */
1936 #define RFCSR38_RX_LO1_EN               FIELD8(0x20)
1937
1938 /*
1939  * RFCSR 39:
1940  */
1941 #define RFCSR39_RX_LO2_EN               FIELD8(0x80)
1942
1943 /*
1944  * RFCSR 49:
1945  */
1946 #define RFCSR49_TX                      FIELD8(0x3f)
1947
1948 /*
1949  * RF registers
1950  */
1951
1952 /*
1953  * RF 2
1954  */
1955 #define RF2_ANTENNA_RX2                 FIELD32(0x00000040)
1956 #define RF2_ANTENNA_TX1                 FIELD32(0x00004000)
1957 #define RF2_ANTENNA_RX1                 FIELD32(0x00020000)
1958
1959 /*
1960  * RF 3
1961  */
1962 #define RF3_TXPOWER_G                   FIELD32(0x00003e00)
1963 #define RF3_TXPOWER_A_7DBM_BOOST        FIELD32(0x00000200)
1964 #define RF3_TXPOWER_A                   FIELD32(0x00003c00)
1965
1966 /*
1967  * RF 4
1968  */
1969 #define RF4_TXPOWER_G                   FIELD32(0x000007c0)
1970 #define RF4_TXPOWER_A_7DBM_BOOST        FIELD32(0x00000040)
1971 #define RF4_TXPOWER_A                   FIELD32(0x00000780)
1972 #define RF4_FREQ_OFFSET                 FIELD32(0x001f8000)
1973 #define RF4_HT40                        FIELD32(0x00200000)
1974
1975 /*
1976  * EEPROM content.
1977  * The wordsize of the EEPROM is 16 bits.
1978  */
1979
1980 /*
1981  * Chip ID
1982  */
1983 #define EEPROM_CHIP_ID                  0x0000
1984
1985 /*
1986  * EEPROM Version
1987  */
1988 #define EEPROM_VERSION                  0x0001
1989 #define EEPROM_VERSION_FAE              FIELD16(0x00ff)
1990 #define EEPROM_VERSION_VERSION          FIELD16(0xff00)
1991
1992 /*
1993  * HW MAC address.
1994  */
1995 #define EEPROM_MAC_ADDR_0               0x0002
1996 #define EEPROM_MAC_ADDR_BYTE0           FIELD16(0x00ff)
1997 #define EEPROM_MAC_ADDR_BYTE1           FIELD16(0xff00)
1998 #define EEPROM_MAC_ADDR_1               0x0003
1999 #define EEPROM_MAC_ADDR_BYTE2           FIELD16(0x00ff)
2000 #define EEPROM_MAC_ADDR_BYTE3           FIELD16(0xff00)
2001 #define EEPROM_MAC_ADDR_2               0x0004
2002 #define EEPROM_MAC_ADDR_BYTE4           FIELD16(0x00ff)
2003 #define EEPROM_MAC_ADDR_BYTE5           FIELD16(0xff00)
2004
2005 /*
2006  * EEPROM NIC Configuration 0
2007  * RXPATH: 1: 1R, 2: 2R, 3: 3R
2008  * TXPATH: 1: 1T, 2: 2T, 3: 3T
2009  * RF_TYPE: RFIC type
2010  */
2011 #define EEPROM_NIC_CONF0                0x001a
2012 #define EEPROM_NIC_CONF0_RXPATH         FIELD16(0x000f)
2013 #define EEPROM_NIC_CONF0_TXPATH         FIELD16(0x00f0)
2014 #define EEPROM_NIC_CONF0_RF_TYPE                FIELD16(0x0f00)
2015
2016 /*
2017  * EEPROM NIC Configuration 1
2018  * HW_RADIO: 0: disable, 1: enable
2019  * EXTERNAL_TX_ALC: 0: disable, 1: enable
2020  * EXTERNAL_LNA_2G: 0: disable, 1: enable
2021  * EXTERNAL_LNA_5G: 0: disable, 1: enable
2022  * CARDBUS_ACCEL: 0: enable, 1: disable
2023  * BW40M_SB_2G: 0: disable, 1: enable
2024  * BW40M_SB_5G: 0: disable, 1: enable
2025  * WPS_PBC: 0: disable, 1: enable
2026  * BW40M_2G: 0: enable, 1: disable
2027  * BW40M_5G: 0: enable, 1: disable
2028  * BROADBAND_EXT_LNA: 0: disable, 1: enable
2029  * ANT_DIVERSITY: 00: Disable, 01: Diversity,
2030  *                                10: Main antenna, 11: Aux antenna
2031  * INTERNAL_TX_ALC: 0: disable, 1: enable
2032  * BT_COEXIST: 0: disable, 1: enable
2033  * DAC_TEST: 0: disable, 1: enable
2034  */
2035 #define EEPROM_NIC_CONF1                0x001b
2036 #define EEPROM_NIC_CONF1_HW_RADIO               FIELD16(0x0001)
2037 #define EEPROM_NIC_CONF1_EXTERNAL_TX_ALC                FIELD16(0x0002)
2038 #define EEPROM_NIC_CONF1_EXTERNAL_LNA_2G                FIELD16(0x0004)
2039 #define EEPROM_NIC_CONF1_EXTERNAL_LNA_5G                FIELD16(0x0008)
2040 #define EEPROM_NIC_CONF1_CARDBUS_ACCEL          FIELD16(0x0010)
2041 #define EEPROM_NIC_CONF1_BW40M_SB_2G            FIELD16(0x0020)
2042 #define EEPROM_NIC_CONF1_BW40M_SB_5G            FIELD16(0x0040)
2043 #define EEPROM_NIC_CONF1_WPS_PBC                FIELD16(0x0080)
2044 #define EEPROM_NIC_CONF1_BW40M_2G               FIELD16(0x0100)
2045 #define EEPROM_NIC_CONF1_BW40M_5G               FIELD16(0x0200)
2046 #define EEPROM_NIC_CONF1_BROADBAND_EXT_LNA              FIELD16(0x400)
2047 #define EEPROM_NIC_CONF1_ANT_DIVERSITY          FIELD16(0x1800)
2048 #define EEPROM_NIC_CONF1_INTERNAL_TX_ALC                FIELD16(0x2000)
2049 #define EEPROM_NIC_CONF1_BT_COEXIST             FIELD16(0x4000)
2050 #define EEPROM_NIC_CONF1_DAC_TEST               FIELD16(0x8000)
2051
2052 /*
2053  * EEPROM frequency
2054  */
2055 #define EEPROM_FREQ                     0x001d
2056 #define EEPROM_FREQ_OFFSET              FIELD16(0x00ff)
2057 #define EEPROM_FREQ_LED_MODE            FIELD16(0x7f00)
2058 #define EEPROM_FREQ_LED_POLARITY        FIELD16(0x1000)
2059
2060 /*
2061  * EEPROM LED
2062  * POLARITY_RDY_G: Polarity RDY_G setting.
2063  * POLARITY_RDY_A: Polarity RDY_A setting.
2064  * POLARITY_ACT: Polarity ACT setting.
2065  * POLARITY_GPIO_0: Polarity GPIO0 setting.
2066  * POLARITY_GPIO_1: Polarity GPIO1 setting.
2067  * POLARITY_GPIO_2: Polarity GPIO2 setting.
2068  * POLARITY_GPIO_3: Polarity GPIO3 setting.
2069  * POLARITY_GPIO_4: Polarity GPIO4 setting.
2070  * LED_MODE: Led mode.
2071  */
2072 #define EEPROM_LED_AG_CONF              0x001e
2073 #define EEPROM_LED_ACT_CONF             0x001f
2074 #define EEPROM_LED_POLARITY             0x0020
2075 #define EEPROM_LED_POLARITY_RDY_BG      FIELD16(0x0001)
2076 #define EEPROM_LED_POLARITY_RDY_A       FIELD16(0x0002)
2077 #define EEPROM_LED_POLARITY_ACT         FIELD16(0x0004)
2078 #define EEPROM_LED_POLARITY_GPIO_0      FIELD16(0x0008)
2079 #define EEPROM_LED_POLARITY_GPIO_1      FIELD16(0x0010)
2080 #define EEPROM_LED_POLARITY_GPIO_2      FIELD16(0x0020)
2081 #define EEPROM_LED_POLARITY_GPIO_3      FIELD16(0x0040)
2082 #define EEPROM_LED_POLARITY_GPIO_4      FIELD16(0x0080)
2083 #define EEPROM_LED_LED_MODE             FIELD16(0x1f00)
2084
2085 /*
2086  * EEPROM NIC Configuration 2
2087  * RX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
2088  * TX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
2089  * CRYSTAL: 00: Reserved, 01: One crystal, 10: Two crystal, 11: Reserved
2090  */
2091 #define EEPROM_NIC_CONF2                0x0021
2092 #define EEPROM_NIC_CONF2_RX_STREAM              FIELD16(0x000f)
2093 #define EEPROM_NIC_CONF2_TX_STREAM              FIELD16(0x00f0)
2094 #define EEPROM_NIC_CONF2_CRYSTAL                FIELD16(0x0600)
2095
2096 /*
2097  * EEPROM LNA
2098  */
2099 #define EEPROM_LNA                      0x0022
2100 #define EEPROM_LNA_BG                   FIELD16(0x00ff)
2101 #define EEPROM_LNA_A0                   FIELD16(0xff00)
2102
2103 /*
2104  * EEPROM RSSI BG offset
2105  */
2106 #define EEPROM_RSSI_BG                  0x0023
2107 #define EEPROM_RSSI_BG_OFFSET0          FIELD16(0x00ff)
2108 #define EEPROM_RSSI_BG_OFFSET1          FIELD16(0xff00)
2109
2110 /*
2111  * EEPROM RSSI BG2 offset
2112  */
2113 #define EEPROM_RSSI_BG2                 0x0024
2114 #define EEPROM_RSSI_BG2_OFFSET2         FIELD16(0x00ff)
2115 #define EEPROM_RSSI_BG2_LNA_A1          FIELD16(0xff00)
2116
2117 /*
2118  * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2).
2119  */
2120 #define EEPROM_TXMIXER_GAIN_BG          0x0024
2121 #define EEPROM_TXMIXER_GAIN_BG_VAL      FIELD16(0x0007)
2122
2123 /*
2124  * EEPROM RSSI A offset
2125  */
2126 #define EEPROM_RSSI_A                   0x0025
2127 #define EEPROM_RSSI_A_OFFSET0           FIELD16(0x00ff)
2128 #define EEPROM_RSSI_A_OFFSET1           FIELD16(0xff00)
2129
2130 /*
2131  * EEPROM RSSI A2 offset
2132  */
2133 #define EEPROM_RSSI_A2                  0x0026
2134 #define EEPROM_RSSI_A2_OFFSET2          FIELD16(0x00ff)
2135 #define EEPROM_RSSI_A2_LNA_A2           FIELD16(0xff00)
2136
2137 /*
2138  * EEPROM TXMIXER GAIN A offset (note overlaps with EEPROM RSSI A2).
2139  */
2140 #define EEPROM_TXMIXER_GAIN_A           0x0026
2141 #define EEPROM_TXMIXER_GAIN_A_VAL       FIELD16(0x0007)
2142
2143 /*
2144  * EEPROM EIRP Maximum TX power values(unit: dbm)
2145  */
2146 #define EEPROM_EIRP_MAX_TX_POWER        0x0027
2147 #define EEPROM_EIRP_MAX_TX_POWER_2GHZ   FIELD16(0x00ff)
2148 #define EEPROM_EIRP_MAX_TX_POWER_5GHZ   FIELD16(0xff00)
2149
2150 /*
2151  * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
2152  * This is delta in 40MHZ.
2153  * VALUE: Tx Power dalta value, MAX=4(unit: dbm)
2154  * TYPE: 1: Plus the delta value, 0: minus the delta value
2155  * ENABLE: enable tx power compensation for 40BW
2156  */
2157 #define EEPROM_TXPOWER_DELTA            0x0028
2158 #define EEPROM_TXPOWER_DELTA_VALUE_2G   FIELD16(0x003f)
2159 #define EEPROM_TXPOWER_DELTA_TYPE_2G    FIELD16(0x0040)
2160 #define EEPROM_TXPOWER_DELTA_ENABLE_2G  FIELD16(0x0080)
2161 #define EEPROM_TXPOWER_DELTA_VALUE_5G   FIELD16(0x3f00)
2162 #define EEPROM_TXPOWER_DELTA_TYPE_5G    FIELD16(0x4000)
2163 #define EEPROM_TXPOWER_DELTA_ENABLE_5G  FIELD16(0x8000)
2164
2165 /*
2166  * EEPROM TXPOWER 802.11BG
2167  */
2168 #define EEPROM_TXPOWER_BG1              0x0029
2169 #define EEPROM_TXPOWER_BG2              0x0030
2170 #define EEPROM_TXPOWER_BG_SIZE          7
2171 #define EEPROM_TXPOWER_BG_1             FIELD16(0x00ff)
2172 #define EEPROM_TXPOWER_BG_2             FIELD16(0xff00)
2173
2174 /*
2175  * EEPROM temperature compensation boundaries 802.11BG
2176  * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
2177  *         reduced by (agc_step * -4)
2178  * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
2179  *         reduced by (agc_step * -3)
2180  */
2181 #define EEPROM_TSSI_BOUND_BG1           0x0037
2182 #define EEPROM_TSSI_BOUND_BG1_MINUS4    FIELD16(0x00ff)
2183 #define EEPROM_TSSI_BOUND_BG1_MINUS3    FIELD16(0xff00)
2184
2185 /*
2186  * EEPROM temperature compensation boundaries 802.11BG
2187  * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
2188  *         reduced by (agc_step * -2)
2189  * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
2190  *         reduced by (agc_step * -1)
2191  */
2192 #define EEPROM_TSSI_BOUND_BG2           0x0038
2193 #define EEPROM_TSSI_BOUND_BG2_MINUS2    FIELD16(0x00ff)
2194 #define EEPROM_TSSI_BOUND_BG2_MINUS1    FIELD16(0xff00)
2195
2196 /*
2197  * EEPROM temperature compensation boundaries 802.11BG
2198  * REF: Reference TSSI value, no tx power changes needed
2199  * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
2200  *        increased by (agc_step * 1)
2201  */
2202 #define EEPROM_TSSI_BOUND_BG3           0x0039
2203 #define EEPROM_TSSI_BOUND_BG3_REF       FIELD16(0x00ff)
2204 #define EEPROM_TSSI_BOUND_BG3_PLUS1     FIELD16(0xff00)
2205
2206 /*
2207  * EEPROM temperature compensation boundaries 802.11BG
2208  * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
2209  *        increased by (agc_step * 2)
2210  * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
2211  *        increased by (agc_step * 3)
2212  */
2213 #define EEPROM_TSSI_BOUND_BG4           0x003a
2214 #define EEPROM_TSSI_BOUND_BG4_PLUS2     FIELD16(0x00ff)
2215 #define EEPROM_TSSI_BOUND_BG4_PLUS3     FIELD16(0xff00)
2216
2217 /*
2218  * EEPROM temperature compensation boundaries 802.11BG
2219  * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
2220  *        increased by (agc_step * 4)
2221  * AGC_STEP: Temperature compensation step.
2222  */
2223 #define EEPROM_TSSI_BOUND_BG5           0x003b
2224 #define EEPROM_TSSI_BOUND_BG5_PLUS4     FIELD16(0x00ff)
2225 #define EEPROM_TSSI_BOUND_BG5_AGC_STEP  FIELD16(0xff00)
2226
2227 /*
2228  * EEPROM TXPOWER 802.11A
2229  */
2230 #define EEPROM_TXPOWER_A1               0x003c
2231 #define EEPROM_TXPOWER_A2               0x0053
2232 #define EEPROM_TXPOWER_A_SIZE           6
2233 #define EEPROM_TXPOWER_A_1              FIELD16(0x00ff)
2234 #define EEPROM_TXPOWER_A_2              FIELD16(0xff00)
2235
2236 /*
2237  * EEPROM temperature compensation boundaries 802.11A
2238  * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
2239  *         reduced by (agc_step * -4)
2240  * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
2241  *         reduced by (agc_step * -3)
2242  */
2243 #define EEPROM_TSSI_BOUND_A1            0x006a
2244 #define EEPROM_TSSI_BOUND_A1_MINUS4     FIELD16(0x00ff)
2245 #define EEPROM_TSSI_BOUND_A1_MINUS3     FIELD16(0xff00)
2246
2247 /*
2248  * EEPROM temperature compensation boundaries 802.11A
2249  * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
2250  *         reduced by (agc_step * -2)
2251  * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
2252  *         reduced by (agc_step * -1)
2253  */
2254 #define EEPROM_TSSI_BOUND_A2            0x006b
2255 #define EEPROM_TSSI_BOUND_A2_MINUS2     FIELD16(0x00ff)
2256 #define EEPROM_TSSI_BOUND_A2_MINUS1     FIELD16(0xff00)
2257
2258 /*
2259  * EEPROM temperature compensation boundaries 802.11A
2260  * REF: Reference TSSI value, no tx power changes needed
2261  * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
2262  *        increased by (agc_step * 1)
2263  */
2264 #define EEPROM_TSSI_BOUND_A3            0x006c
2265 #define EEPROM_TSSI_BOUND_A3_REF        FIELD16(0x00ff)
2266 #define EEPROM_TSSI_BOUND_A3_PLUS1      FIELD16(0xff00)
2267
2268 /*
2269  * EEPROM temperature compensation boundaries 802.11A
2270  * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
2271  *        increased by (agc_step * 2)
2272  * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
2273  *        increased by (agc_step * 3)
2274  */
2275 #define EEPROM_TSSI_BOUND_A4            0x006d
2276 #define EEPROM_TSSI_BOUND_A4_PLUS2      FIELD16(0x00ff)
2277 #define EEPROM_TSSI_BOUND_A4_PLUS3      FIELD16(0xff00)
2278
2279 /*
2280  * EEPROM temperature compensation boundaries 802.11A
2281  * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
2282  *        increased by (agc_step * 4)
2283  * AGC_STEP: Temperature compensation step.
2284  */
2285 #define EEPROM_TSSI_BOUND_A5            0x006e
2286 #define EEPROM_TSSI_BOUND_A5_PLUS4      FIELD16(0x00ff)
2287 #define EEPROM_TSSI_BOUND_A5_AGC_STEP   FIELD16(0xff00)
2288
2289 /*
2290  * EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode
2291  */
2292 #define EEPROM_TXPOWER_BYRATE           0x006f
2293 #define EEPROM_TXPOWER_BYRATE_SIZE      9
2294
2295 #define EEPROM_TXPOWER_BYRATE_RATE0     FIELD16(0x000f)
2296 #define EEPROM_TXPOWER_BYRATE_RATE1     FIELD16(0x00f0)
2297 #define EEPROM_TXPOWER_BYRATE_RATE2     FIELD16(0x0f00)
2298 #define EEPROM_TXPOWER_BYRATE_RATE3     FIELD16(0xf000)
2299
2300 /*
2301  * EEPROM BBP.
2302  */
2303 #define EEPROM_BBP_START                0x0078
2304 #define EEPROM_BBP_SIZE                 16
2305 #define EEPROM_BBP_VALUE                FIELD16(0x00ff)
2306 #define EEPROM_BBP_REG_ID               FIELD16(0xff00)
2307
2308 /*
2309  * MCU mailbox commands.
2310  * MCU_SLEEP - go to power-save mode.
2311  *             arg1: 1: save as much power as possible, 0: save less power.
2312  *             status: 1: success, 2: already asleep,
2313  *                     3: maybe MAC is busy so can't finish this task.
2314  * MCU_RADIO_OFF
2315  *             arg0: 0: do power-saving, NOT turn off radio.
2316  */
2317 #define MCU_SLEEP                       0x30
2318 #define MCU_WAKEUP                      0x31
2319 #define MCU_RADIO_OFF                   0x35
2320 #define MCU_CURRENT                     0x36
2321 #define MCU_LED                         0x50
2322 #define MCU_LED_STRENGTH                0x51
2323 #define MCU_LED_AG_CONF         0x52
2324 #define MCU_LED_ACT_CONF                0x53
2325 #define MCU_LED_LED_POLARITY            0x54
2326 #define MCU_RADAR                       0x60
2327 #define MCU_BOOT_SIGNAL                 0x72
2328 #define MCU_ANT_SELECT                  0X73
2329 #define MCU_BBP_SIGNAL                  0x80
2330 #define MCU_POWER_SAVE                  0x83
2331 #define MCU_BAND_SELECT         0x91
2332
2333 /*
2334  * MCU mailbox tokens
2335  */
2336 #define TOKEN_SLEEP                     1
2337 #define TOKEN_RADIO_OFF                 2
2338 #define TOKEN_WAKEUP                    3
2339
2340
2341 /*
2342  * DMA descriptor defines.
2343  */
2344 #define TXWI_DESC_SIZE                  (4 * sizeof(__le32))
2345 #define RXWI_DESC_SIZE                  (4 * sizeof(__le32))
2346
2347 /*
2348  * TX WI structure
2349  */
2350
2351 /*
2352  * Word0
2353  * FRAG: 1 To inform TKIP engine this is a fragment.
2354  * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
2355  * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
2356  * BW: Channel bandwidth 0:20MHz, 1:40 MHz (for legacy rates this will
2357  *     duplicate the frame to both channels).
2358  * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
2359  * AMPDU: 1: this frame is eligible for AMPDU aggregation, the hw will
2360  *        aggregate consecutive frames with the same RA and QoS TID. If
2361  *        a frame A with the same RA and QoS TID but AMPDU=0 is queued
2362  *        directly after a frame B with AMPDU=1, frame A might still
2363  *        get aggregated into the AMPDU started by frame B. So, setting
2364  *        AMPDU to 0 does _not_ necessarily mean the frame is sent as
2365  *        MPDU, it can still end up in an AMPDU if the previous frame
2366  *        was tagged as AMPDU.
2367  */
2368 #define TXWI_W0_FRAG                    FIELD32(0x00000001)
2369 #define TXWI_W0_MIMO_PS                 FIELD32(0x00000002)
2370 #define TXWI_W0_CF_ACK                  FIELD32(0x00000004)
2371 #define TXWI_W0_TS                      FIELD32(0x00000008)
2372 #define TXWI_W0_AMPDU                   FIELD32(0x00000010)
2373 #define TXWI_W0_MPDU_DENSITY            FIELD32(0x000000e0)
2374 #define TXWI_W0_TX_OP                   FIELD32(0x00000300)
2375 #define TXWI_W0_MCS                     FIELD32(0x007f0000)
2376 #define TXWI_W0_BW                      FIELD32(0x00800000)
2377 #define TXWI_W0_SHORT_GI                FIELD32(0x01000000)
2378 #define TXWI_W0_STBC                    FIELD32(0x06000000)
2379 #define TXWI_W0_IFS                     FIELD32(0x08000000)
2380 #define TXWI_W0_PHYMODE                 FIELD32(0xc0000000)
2381
2382 /*
2383  * Word1
2384  * ACK: 0: No Ack needed, 1: Ack needed
2385  * NSEQ: 0: Don't assign hw sequence number, 1: Assign hw sequence number
2386  * BW_WIN_SIZE: BA windows size of the recipient
2387  * WIRELESS_CLI_ID: Client ID for WCID table access
2388  * MPDU_TOTAL_BYTE_COUNT: Length of 802.11 frame
2389  * PACKETID: Will be latched into the TX_STA_FIFO register once the according
2390  *           frame was processed. If multiple frames are aggregated together
2391  *           (AMPDU==1) the reported tx status will always contain the packet
2392  *           id of the first frame. 0: Don't report tx status for this frame.
2393  * PACKETID_QUEUE: Part of PACKETID, This is the queue index (0-3)
2394  * PACKETID_ENTRY: Part of PACKETID, THis is the queue entry index (1-3)
2395  *                 This identification number is calculated by ((idx % 3) + 1).
2396  *                 The (+1) is required to prevent PACKETID to become 0.
2397  */
2398 #define TXWI_W1_ACK                     FIELD32(0x00000001)
2399 #define TXWI_W1_NSEQ                    FIELD32(0x00000002)
2400 #define TXWI_W1_BW_WIN_SIZE             FIELD32(0x000000fc)
2401 #define TXWI_W1_WIRELESS_CLI_ID         FIELD32(0x0000ff00)
2402 #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT   FIELD32(0x0fff0000)
2403 #define TXWI_W1_PACKETID                FIELD32(0xf0000000)
2404 #define TXWI_W1_PACKETID_QUEUE          FIELD32(0x30000000)
2405 #define TXWI_W1_PACKETID_ENTRY          FIELD32(0xc0000000)
2406
2407 /*
2408  * Word2
2409  */
2410 #define TXWI_W2_IV                      FIELD32(0xffffffff)
2411
2412 /*
2413  * Word3
2414  */
2415 #define TXWI_W3_EIV                     FIELD32(0xffffffff)
2416
2417 /*
2418  * RX WI structure
2419  */
2420
2421 /*
2422  * Word0
2423  */
2424 #define RXWI_W0_WIRELESS_CLI_ID         FIELD32(0x000000ff)
2425 #define RXWI_W0_KEY_INDEX               FIELD32(0x00000300)
2426 #define RXWI_W0_BSSID                   FIELD32(0x00001c00)
2427 #define RXWI_W0_UDF                     FIELD32(0x0000e000)
2428 #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT   FIELD32(0x0fff0000)
2429 #define RXWI_W0_TID                     FIELD32(0xf0000000)
2430
2431 /*
2432  * Word1
2433  */
2434 #define RXWI_W1_FRAG                    FIELD32(0x0000000f)
2435 #define RXWI_W1_SEQUENCE                FIELD32(0x0000fff0)
2436 #define RXWI_W1_MCS                     FIELD32(0x007f0000)
2437 #define RXWI_W1_BW                      FIELD32(0x00800000)
2438 #define RXWI_W1_SHORT_GI                FIELD32(0x01000000)
2439 #define RXWI_W1_STBC                    FIELD32(0x06000000)
2440 #define RXWI_W1_PHYMODE                 FIELD32(0xc0000000)
2441
2442 /*
2443  * Word2
2444  */
2445 #define RXWI_W2_RSSI0                   FIELD32(0x000000ff)
2446 #define RXWI_W2_RSSI1                   FIELD32(0x0000ff00)
2447 #define RXWI_W2_RSSI2                   FIELD32(0x00ff0000)
2448
2449 /*
2450  * Word3
2451  */
2452 #define RXWI_W3_SNR0                    FIELD32(0x000000ff)
2453 #define RXWI_W3_SNR1                    FIELD32(0x0000ff00)
2454
2455 /*
2456  * Macros for converting txpower from EEPROM to mac80211 value
2457  * and from mac80211 value to register value.
2458  */
2459 #define MIN_G_TXPOWER   0
2460 #define MIN_A_TXPOWER   -7
2461 #define MAX_G_TXPOWER   31
2462 #define MAX_A_TXPOWER   15
2463 #define DEFAULT_TXPOWER 5
2464
2465 #define TXPOWER_G_FROM_DEV(__txpower) \
2466         ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
2467
2468 #define TXPOWER_G_TO_DEV(__txpower) \
2469         clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
2470
2471 #define TXPOWER_A_FROM_DEV(__txpower) \
2472         ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
2473
2474 #define TXPOWER_A_TO_DEV(__txpower) \
2475         clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
2476
2477 /*
2478  *  Board's maximun TX power limitation
2479  */
2480 #define EIRP_MAX_TX_POWER_LIMIT 0x50
2481
2482 /*
2483  * Number of TBTT intervals after which we have to adjust
2484  * the hw beacon timer.
2485  */
2486 #define BCN_TBTT_OFFSET 64
2487
2488 /*
2489  * RT2800 driver data structure
2490  */
2491 struct rt2800_drv_data {
2492         u8 calibration_bw20;
2493         u8 calibration_bw40;
2494         u8 bbp25;
2495         u8 bbp26;
2496         u8 txmixer_gain_24g;
2497         u8 txmixer_gain_5g;
2498         unsigned int tbtt_tick;
2499 };
2500
2501 #endif /* RT2800_H */