drivers/net/wireless/rt2x00/rt2800.h

   1 /*
   2         Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
   3         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   4         Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   5         Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   6         Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
   7         Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
   8         Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
   9         Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  10         Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
  11         <http://rt2x00.serialmonkey.com>
  12
  13         This program is free software; you can redistribute it and/or modify
  14         it under the terms of the GNU General Public License as published by
  15         the Free Software Foundation; either version 2 of the License, or
  16         (at your option) any later version.
  17
  18         This program is distributed in the hope that it will be useful,
  19         but WITHOUT ANY WARRANTY; without even the implied warranty of
  20         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21         GNU General Public License for more details.
  22
  23         You should have received a copy of the GNU General Public License
  24         along with this program; if not, write to the
  25         Free Software Foundation, Inc.,
  26         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  27  */
  28
  29 /*
  30         Module: rt2800
  31         Abstract: Data structures and registers for the rt2800 modules.
  32         Supported chipsets: RT2800E, RT2800ED & RT2800U.
  33  */
  34
  35 #ifndef RT2800_H
  36 #define RT2800_H
  37
  38 /*
  39  * RF chip defines.
  40  *
  41  * RF2820 2.4G 2T3R
  42  * RF2850 2.4G/5G 2T3R
  43  * RF2720 2.4G 1T2R
  44  * RF2750 2.4G/5G 1T2R
  45  * RF3020 2.4G 1T1R
  46  * RF2020 2.4G B/G
  47  * RF3021 2.4G 1T2R
  48  * RF3022 2.4G 2T2R
  49  * RF3052 2.4G/5G 2T2R
  50  * RF2853 2.4G/5G 3T3R
  51  * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390)
  52  * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392)
  53  * RF3053 2.4G/5G 3T3R(RT3883/RT3563/RT3573/RT3593/RT3662)
  54  * RF5592 2.4G/5G 2T2R
  55  * RF5360 2.4G 1T1R
  56  * RF5370 2.4G 1T1R
  57  * RF5390 2.4G 1T1R
  58  */
  59 #define RF2820                          0x0001
  60 #define RF2850                          0x0002
  61 #define RF2720                          0x0003
  62 #define RF2750                          0x0004
  63 #define RF3020                          0x0005
  64 #define RF2020                          0x0006
  65 #define RF3021                          0x0007
  66 #define RF3022                          0x0008
  67 #define RF3052                          0x0009
  68 #define RF2853                          0x000a
  69 #define RF3320                          0x000b
  70 #define RF3322                          0x000c
  71 #define RF3053                          0x000d
  72 #define RF5592                          0x000f
  73 #define RF3290                          0x3290
  74 #define RF5360                          0x5360
  75 #define RF5370                          0x5370
  76 #define RF5372                          0x5372
  77 #define RF5390                          0x5390
  78 #define RF5392                          0x5392
  79
  80 /*
  81  * Chipset revisions.
  82  */
  83 #define REV_RT2860C                     0x0100
  84 #define REV_RT2860D                     0x0101
  85 #define REV_RT2872E                     0x0200
  86 #define REV_RT3070E                     0x0200
  87 #define REV_RT3070F                     0x0201
  88 #define REV_RT3071E                     0x0211
  89 #define REV_RT3090E                     0x0211
  90 #define REV_RT3390E                     0x0211
  91 #define REV_RT3593E                     0x0211
  92 #define REV_RT5390F                     0x0502
  93 #define REV_RT5390R                     0x1502
  94 #define REV_RT5592C                     0x0221
  95
  96 #define DEFAULT_RSSI_OFFSET             120
  97
  98 /*
  99  * Register layout information.
 100  */
 101 #define CSR_REG_BASE                    0x1000
 102 #define CSR_REG_SIZE                    0x0800
 103 #define EEPROM_BASE                     0x0000
 104 #define EEPROM_SIZE                     0x0200
 105 #define BBP_BASE                        0x0000
 106 #define BBP_SIZE                        0x00ff
 107 #define RF_BASE                         0x0004
 108 #define RF_SIZE                         0x0010
 109 #define RFCSR_BASE                      0x0000
 110 #define RFCSR_SIZE                      0x0040
 111
 112 /*
 113  * Number of TX queues.
 114  */
 115 #define NUM_TX_QUEUES                   4
 116
 117 /*
 118  * Registers.
 119  */
 120
 121
 122 /*
 123  * MAC_CSR0_3290: MAC_CSR0 for RT3290 to identity MAC version number.
 124  */
 125 #define MAC_CSR0_3290                           0x0000
 126
 127 /*
 128  * E2PROM_CSR: PCI EEPROM control register.
 129  * RELOAD: Write 1 to reload eeprom content.
 130  * TYPE: 0: 93c46, 1:93c66.
 131  * LOAD_STATUS: 1:loading, 0:done.
 132  */
 133 #define E2PROM_CSR                      0x0004
 134 #define E2PROM_CSR_DATA_CLOCK           FIELD32(0x00000001)
 135 #define E2PROM_CSR_CHIP_SELECT          FIELD32(0x00000002)
 136 #define E2PROM_CSR_DATA_IN              FIELD32(0x00000004)
 137 #define E2PROM_CSR_DATA_OUT             FIELD32(0x00000008)
 138 #define E2PROM_CSR_TYPE                 FIELD32(0x00000030)
 139 #define E2PROM_CSR_LOAD_STATUS          FIELD32(0x00000040)
 140 #define E2PROM_CSR_RELOAD               FIELD32(0x00000080)
 141
 142 /*
 143  * CMB_CTRL_CFG
 144  */
 145 #define CMB_CTRL                0x0020
 146 #define AUX_OPT_BIT0            FIELD32(0x00000001)
 147 #define AUX_OPT_BIT1            FIELD32(0x00000002)
 148 #define AUX_OPT_BIT2            FIELD32(0x00000004)
 149 #define AUX_OPT_BIT3            FIELD32(0x00000008)
 150 #define AUX_OPT_BIT4            FIELD32(0x00000010)
 151 #define AUX_OPT_BIT5            FIELD32(0x00000020)
 152 #define AUX_OPT_BIT6            FIELD32(0x00000040)
 153 #define AUX_OPT_BIT7            FIELD32(0x00000080)
 154 #define AUX_OPT_BIT8            FIELD32(0x00000100)
 155 #define AUX_OPT_BIT9            FIELD32(0x00000200)
 156 #define AUX_OPT_BIT10           FIELD32(0x00000400)
 157 #define AUX_OPT_BIT11           FIELD32(0x00000800)
 158 #define AUX_OPT_BIT12           FIELD32(0x00001000)
 159 #define AUX_OPT_BIT13           FIELD32(0x00002000)
 160 #define AUX_OPT_BIT14           FIELD32(0x00004000)
 161 #define AUX_OPT_BIT15           FIELD32(0x00008000)
 162 #define LDO25_LEVEL             FIELD32(0x00030000)
 163 #define LDO25_LARGEA            FIELD32(0x00040000)
 164 #define LDO25_FRC_ON            FIELD32(0x00080000)
 165 #define CMB_RSV                 FIELD32(0x00300000)
 166 #define XTAL_RDY                FIELD32(0x00400000)
 167 #define PLL_LD                  FIELD32(0x00800000)
 168 #define LDO_CORE_LEVEL          FIELD32(0x0F000000)
 169 #define LDO_BGSEL               FIELD32(0x30000000)
 170 #define LDO3_EN                 FIELD32(0x40000000)
 171 #define LDO0_EN                 FIELD32(0x80000000)
 172
 173 /*
 174  * EFUSE_CSR_3290: RT3290 EEPROM
 175  */
 176 #define EFUSE_CTRL_3290                 0x0024
 177
 178 /*
 179  * EFUSE_DATA3 of 3290
 180  */
 181 #define EFUSE_DATA3_3290                0x0028
 182
 183 /*
 184  * EFUSE_DATA2 of 3290
 185  */
 186 #define EFUSE_DATA2_3290                0x002c
 187
 188 /*
 189  * EFUSE_DATA1 of 3290
 190  */
 191 #define EFUSE_DATA1_3290                0x0030
 192
 193 /*
 194  * EFUSE_DATA0 of 3290
 195  */
 196 #define EFUSE_DATA0_3290                0x0034
 197
 198 /*
 199  * OSC_CTRL_CFG
 200  * Ring oscillator configuration
 201  */
 202 #define OSC_CTRL                0x0038
 203 #define OSC_REF_CYCLE           FIELD32(0x00001fff)
 204 #define OSC_RSV                 FIELD32(0x0000e000)
 205 #define OSC_CAL_CNT             FIELD32(0x0fff0000)
 206 #define OSC_CAL_ACK             FIELD32(0x10000000)
 207 #define OSC_CLK_32K_VLD         FIELD32(0x20000000)
 208 #define OSC_CAL_REQ             FIELD32(0x40000000)
 209 #define OSC_ROSC_EN             FIELD32(0x80000000)
 210
 211 /*
 212  * COEX_CFG_0
 213  */
 214 #define COEX_CFG0                       0x0040
 215 #define COEX_CFG_ANT            FIELD32(0xff000000)
 216 /*
 217  * COEX_CFG_1
 218  */
 219 #define COEX_CFG1                       0x0044
 220
 221 /*
 222  * COEX_CFG_2
 223  */
 224 #define COEX_CFG2                       0x0048
 225 #define BT_COEX_CFG1            FIELD32(0xff000000)
 226 #define BT_COEX_CFG0            FIELD32(0x00ff0000)
 227 #define WL_COEX_CFG1            FIELD32(0x0000ff00)
 228 #define WL_COEX_CFG0            FIELD32(0x000000ff)
 229 /*
 230  * PLL_CTRL_CFG
 231  * PLL configuration register
 232  */
 233 #define PLL_CTRL                0x0050
 234 #define PLL_RESERVED_INPUT1     FIELD32(0x000000ff)
 235 #define PLL_RESERVED_INPUT2     FIELD32(0x0000ff00)
 236 #define PLL_CONTROL             FIELD32(0x00070000)
 237 #define PLL_LPF_R1              FIELD32(0x00080000)
 238 #define PLL_LPF_C1_CTRL FIELD32(0x00300000)
 239 #define PLL_LPF_C2_CTRL FIELD32(0x00c00000)
 240 #define PLL_CP_CURRENT_CTRL     FIELD32(0x03000000)
 241 #define PLL_PFD_DELAY_CTRL      FIELD32(0x0c000000)
 242 #define PLL_LOCK_CTRL           FIELD32(0x70000000)
 243 #define PLL_VBGBK_EN            FIELD32(0x80000000)
 244
 245
 246 /*
 247  * WLAN_CTRL_CFG
 248  * RT3290 wlan configuration
 249  */
 250 #define WLAN_FUN_CTRL                   0x0080
 251 #define WLAN_EN                         FIELD32(0x00000001)
 252 #define WLAN_CLK_EN                     FIELD32(0x00000002)
 253 #define WLAN_RSV1                       FIELD32(0x00000004)
 254 #define WLAN_RESET                      FIELD32(0x00000008)
 255 #define PCIE_APP0_CLK_REQ               FIELD32(0x00000010)
 256 #define FRC_WL_ANT_SET                  FIELD32(0x00000020)
 257 #define INV_TR_SW0                      FIELD32(0x00000040)
 258 #define WLAN_GPIO_IN_BIT0               FIELD32(0x00000100)
 259 #define WLAN_GPIO_IN_BIT1               FIELD32(0x00000200)
 260 #define WLAN_GPIO_IN_BIT2               FIELD32(0x00000400)
 261 #define WLAN_GPIO_IN_BIT3               FIELD32(0x00000800)
 262 #define WLAN_GPIO_IN_BIT4               FIELD32(0x00001000)
 263 #define WLAN_GPIO_IN_BIT5               FIELD32(0x00002000)
 264 #define WLAN_GPIO_IN_BIT6               FIELD32(0x00004000)
 265 #define WLAN_GPIO_IN_BIT7               FIELD32(0x00008000)
 266 #define WLAN_GPIO_IN_BIT_ALL            FIELD32(0x0000ff00)
 267 #define WLAN_GPIO_OUT_BIT0              FIELD32(0x00010000)
 268 #define WLAN_GPIO_OUT_BIT1              FIELD32(0x00020000)
 269 #define WLAN_GPIO_OUT_BIT2              FIELD32(0x00040000)
 270 #define WLAN_GPIO_OUT_BIT3              FIELD32(0x00050000)
 271 #define WLAN_GPIO_OUT_BIT4              FIELD32(0x00100000)
 272 #define WLAN_GPIO_OUT_BIT5              FIELD32(0x00200000)
 273 #define WLAN_GPIO_OUT_BIT6              FIELD32(0x00400000)
 274 #define WLAN_GPIO_OUT_BIT7              FIELD32(0x00800000)
 275 #define WLAN_GPIO_OUT_BIT_ALL           FIELD32(0x00ff0000)
 276 #define WLAN_GPIO_OUT_OE_BIT0           FIELD32(0x01000000)
 277 #define WLAN_GPIO_OUT_OE_BIT1           FIELD32(0x02000000)
 278 #define WLAN_GPIO_OUT_OE_BIT2           FIELD32(0x04000000)
 279 #define WLAN_GPIO_OUT_OE_BIT3           FIELD32(0x08000000)
 280 #define WLAN_GPIO_OUT_OE_BIT4           FIELD32(0x10000000)
 281 #define WLAN_GPIO_OUT_OE_BIT5           FIELD32(0x20000000)
 282 #define WLAN_GPIO_OUT_OE_BIT6           FIELD32(0x40000000)
 283 #define WLAN_GPIO_OUT_OE_BIT7           FIELD32(0x80000000)
 284 #define WLAN_GPIO_OUT_OE_BIT_ALL        FIELD32(0xff000000)
 285
 286 /*
 287  * AUX_CTRL: Aux/PCI-E related configuration
 288  */
 289 #define AUX_CTRL                        0x10c
 290 #define AUX_CTRL_WAKE_PCIE_EN           FIELD32(0x00000002)
 291 #define AUX_CTRL_FORCE_PCIE_CLK         FIELD32(0x00000400)
 292
 293 /*
 294  * OPT_14: Unknown register used by rt3xxx devices.
 295  */
 296 #define OPT_14_CSR                      0x0114
 297 #define OPT_14_CSR_BIT0                 FIELD32(0x00000001)
 298
 299 /*
 300  * INT_SOURCE_CSR: Interrupt source register.
 301  * Write one to clear corresponding bit.
 302  * TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO
 303  */
 304 #define INT_SOURCE_CSR                  0x0200
 305 #define INT_SOURCE_CSR_RXDELAYINT       FIELD32(0x00000001)
 306 #define INT_SOURCE_CSR_TXDELAYINT       FIELD32(0x00000002)
 307 #define INT_SOURCE_CSR_RX_DONE          FIELD32(0x00000004)
 308 #define INT_SOURCE_CSR_AC0_DMA_DONE     FIELD32(0x00000008)
 309 #define INT_SOURCE_CSR_AC1_DMA_DONE     FIELD32(0x00000010)
 310 #define INT_SOURCE_CSR_AC2_DMA_DONE     FIELD32(0x00000020)
 311 #define INT_SOURCE_CSR_AC3_DMA_DONE     FIELD32(0x00000040)
 312 #define INT_SOURCE_CSR_HCCA_DMA_DONE    FIELD32(0x00000080)
 313 #define INT_SOURCE_CSR_MGMT_DMA_DONE    FIELD32(0x00000100)
 314 #define INT_SOURCE_CSR_MCU_COMMAND      FIELD32(0x00000200)
 315 #define INT_SOURCE_CSR_RXTX_COHERENT    FIELD32(0x00000400)
 316 #define INT_SOURCE_CSR_TBTT             FIELD32(0x00000800)
 317 #define INT_SOURCE_CSR_PRE_TBTT         FIELD32(0x00001000)
 318 #define INT_SOURCE_CSR_TX_FIFO_STATUS   FIELD32(0x00002000)
 319 #define INT_SOURCE_CSR_AUTO_WAKEUP      FIELD32(0x00004000)
 320 #define INT_SOURCE_CSR_GPTIMER          FIELD32(0x00008000)
 321 #define INT_SOURCE_CSR_RX_COHERENT      FIELD32(0x00010000)
 322 #define INT_SOURCE_CSR_TX_COHERENT      FIELD32(0x00020000)
 323
 324 /*
 325  * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
 326  */
 327 #define INT_MASK_CSR                    0x0204
 328 #define INT_MASK_CSR_RXDELAYINT         FIELD32(0x00000001)
 329 #define INT_MASK_CSR_TXDELAYINT         FIELD32(0x00000002)
 330 #define INT_MASK_CSR_RX_DONE            FIELD32(0x00000004)
 331 #define INT_MASK_CSR_AC0_DMA_DONE       FIELD32(0x00000008)
 332 #define INT_MASK_CSR_AC1_DMA_DONE       FIELD32(0x00000010)
 333 #define INT_MASK_CSR_AC2_DMA_DONE       FIELD32(0x00000020)
 334 #define INT_MASK_CSR_AC3_DMA_DONE       FIELD32(0x00000040)
 335 #define INT_MASK_CSR_HCCA_DMA_DONE      FIELD32(0x00000080)
 336 #define INT_MASK_CSR_MGMT_DMA_DONE      FIELD32(0x00000100)
 337 #define INT_MASK_CSR_MCU_COMMAND        FIELD32(0x00000200)
 338 #define INT_MASK_CSR_RXTX_COHERENT      FIELD32(0x00000400)
 339 #define INT_MASK_CSR_TBTT               FIELD32(0x00000800)
 340 #define INT_MASK_CSR_PRE_TBTT           FIELD32(0x00001000)
 341 #define INT_MASK_CSR_TX_FIFO_STATUS     FIELD32(0x00002000)
 342 #define INT_MASK_CSR_AUTO_WAKEUP        FIELD32(0x00004000)
 343 #define INT_MASK_CSR_GPTIMER            FIELD32(0x00008000)
 344 #define INT_MASK_CSR_RX_COHERENT        FIELD32(0x00010000)
 345 #define INT_MASK_CSR_TX_COHERENT        FIELD32(0x00020000)
 346
 347 /*
 348  * WPDMA_GLO_CFG
 349  */
 350 #define WPDMA_GLO_CFG                   0x0208
 351 #define WPDMA_GLO_CFG_ENABLE_TX_DMA     FIELD32(0x00000001)
 352 #define WPDMA_GLO_CFG_TX_DMA_BUSY       FIELD32(0x00000002)
 353 #define WPDMA_GLO_CFG_ENABLE_RX_DMA     FIELD32(0x00000004)
 354 #define WPDMA_GLO_CFG_RX_DMA_BUSY       FIELD32(0x00000008)
 355 #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
 356 #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
 357 #define WPDMA_GLO_CFG_BIG_ENDIAN        FIELD32(0x00000080)
 358 #define WPDMA_GLO_CFG_RX_HDR_SCATTER    FIELD32(0x0000ff00)
 359 #define WPDMA_GLO_CFG_HDR_SEG_LEN       FIELD32(0xffff0000)
 360
 361 /*
 362  * WPDMA_RST_IDX
 363  */
 364 #define WPDMA_RST_IDX                   0x020c
 365 #define WPDMA_RST_IDX_DTX_IDX0          FIELD32(0x00000001)
 366 #define WPDMA_RST_IDX_DTX_IDX1          FIELD32(0x00000002)
 367 #define WPDMA_RST_IDX_DTX_IDX2          FIELD32(0x00000004)
 368 #define WPDMA_RST_IDX_DTX_IDX3          FIELD32(0x00000008)
 369 #define WPDMA_RST_IDX_DTX_IDX4          FIELD32(0x00000010)
 370 #define WPDMA_RST_IDX_DTX_IDX5          FIELD32(0x00000020)
 371 #define WPDMA_RST_IDX_DRX_IDX0          FIELD32(0x00010000)
 372
 373 /*
 374  * DELAY_INT_CFG
 375  */
 376 #define DELAY_INT_CFG                   0x0210
 377 #define DELAY_INT_CFG_RXMAX_PTIME       FIELD32(0x000000ff)
 378 #define DELAY_INT_CFG_RXMAX_PINT        FIELD32(0x00007f00)
 379 #define DELAY_INT_CFG_RXDLY_INT_EN      FIELD32(0x00008000)
 380 #define DELAY_INT_CFG_TXMAX_PTIME       FIELD32(0x00ff0000)
 381 #define DELAY_INT_CFG_TXMAX_PINT        FIELD32(0x7f000000)
 382 #define DELAY_INT_CFG_TXDLY_INT_EN      FIELD32(0x80000000)
 383
 384 /*
 385  * WMM_AIFSN_CFG: Aifsn for each EDCA AC
 386  * AIFSN0: AC_VO
 387  * AIFSN1: AC_VI
 388  * AIFSN2: AC_BE
 389  * AIFSN3: AC_BK
 390  */
 391 #define WMM_AIFSN_CFG                   0x0214
 392 #define WMM_AIFSN_CFG_AIFSN0            FIELD32(0x0000000f)
 393 #define WMM_AIFSN_CFG_AIFSN1            FIELD32(0x000000f0)
 394 #define WMM_AIFSN_CFG_AIFSN2            FIELD32(0x00000f00)
 395 #define WMM_AIFSN_CFG_AIFSN3            FIELD32(0x0000f000)
 396
 397 /*
 398  * WMM_CWMIN_CSR: CWmin for each EDCA AC
 399  * CWMIN0: AC_VO
 400  * CWMIN1: AC_VI
 401  * CWMIN2: AC_BE
 402  * CWMIN3: AC_BK
 403  */
 404 #define WMM_CWMIN_CFG                   0x0218
 405 #define WMM_CWMIN_CFG_CWMIN0            FIELD32(0x0000000f)
 406 #define WMM_CWMIN_CFG_CWMIN1            FIELD32(0x000000f0)
 407 #define WMM_CWMIN_CFG_CWMIN2            FIELD32(0x00000f00)
 408 #define WMM_CWMIN_CFG_CWMIN3            FIELD32(0x0000f000)
 409
 410 /*
 411  * WMM_CWMAX_CSR: CWmax for each EDCA AC
 412  * CWMAX0: AC_VO
 413  * CWMAX1: AC_VI
 414  * CWMAX2: AC_BE
 415  * CWMAX3: AC_BK
 416  */
 417 #define WMM_CWMAX_CFG                   0x021c
 418 #define WMM_CWMAX_CFG_CWMAX0            FIELD32(0x0000000f)
 419 #define WMM_CWMAX_CFG_CWMAX1            FIELD32(0x000000f0)
 420 #define WMM_CWMAX_CFG_CWMAX2            FIELD32(0x00000f00)
 421 #define WMM_CWMAX_CFG_CWMAX3            FIELD32(0x0000f000)
 422
 423 /*
 424  * AC_TXOP0: AC_VO/AC_VI TXOP register
 425  * AC0TXOP: AC_VO in unit of 32us
 426  * AC1TXOP: AC_VI in unit of 32us
 427  */
 428 #define WMM_TXOP0_CFG                   0x0220
 429 #define WMM_TXOP0_CFG_AC0TXOP           FIELD32(0x0000ffff)
 430 #define WMM_TXOP0_CFG_AC1TXOP           FIELD32(0xffff0000)
 431
 432 /*
 433  * AC_TXOP1: AC_BE/AC_BK TXOP register
 434  * AC2TXOP: AC_BE in unit of 32us
 435  * AC3TXOP: AC_BK in unit of 32us
 436  */
 437 #define WMM_TXOP1_CFG                   0x0224
 438 #define WMM_TXOP1_CFG_AC2TXOP           FIELD32(0x0000ffff)
 439 #define WMM_TXOP1_CFG_AC3TXOP           FIELD32(0xffff0000)
 440
 441 /*
 442  * GPIO_CTRL:
 443  *      GPIO_CTRL_VALx: GPIO value
 444  *      GPIO_CTRL_DIRx: GPIO direction: 0 = output; 1 = input
 445  */
 446 #define GPIO_CTRL                       0x0228
 447 #define GPIO_CTRL_VAL0                  FIELD32(0x00000001)
 448 #define GPIO_CTRL_VAL1                  FIELD32(0x00000002)
 449 #define GPIO_CTRL_VAL2                  FIELD32(0x00000004)
 450 #define GPIO_CTRL_VAL3                  FIELD32(0x00000008)
 451 #define GPIO_CTRL_VAL4                  FIELD32(0x00000010)
 452 #define GPIO_CTRL_VAL5                  FIELD32(0x00000020)
 453 #define GPIO_CTRL_VAL6                  FIELD32(0x00000040)
 454 #define GPIO_CTRL_VAL7                  FIELD32(0x00000080)
 455 #define GPIO_CTRL_DIR0                  FIELD32(0x00000100)
 456 #define GPIO_CTRL_DIR1                  FIELD32(0x00000200)
 457 #define GPIO_CTRL_DIR2                  FIELD32(0x00000400)
 458 #define GPIO_CTRL_DIR3                  FIELD32(0x00000800)
 459 #define GPIO_CTRL_DIR4                  FIELD32(0x00001000)
 460 #define GPIO_CTRL_DIR5                  FIELD32(0x00002000)
 461 #define GPIO_CTRL_DIR6                  FIELD32(0x00004000)
 462 #define GPIO_CTRL_DIR7                  FIELD32(0x00008000)
 463 #define GPIO_CTRL_VAL8                  FIELD32(0x00010000)
 464 #define GPIO_CTRL_VAL9                  FIELD32(0x00020000)
 465 #define GPIO_CTRL_VAL10                 FIELD32(0x00040000)
 466 #define GPIO_CTRL_DIR8                  FIELD32(0x01000000)
 467 #define GPIO_CTRL_DIR9                  FIELD32(0x02000000)
 468 #define GPIO_CTRL_DIR10                 FIELD32(0x04000000)
 469
 470 /*
 471  * MCU_CMD_CFG
 472  */
 473 #define MCU_CMD_CFG                     0x022c
 474
 475 /*
 476  * AC_VO register offsets
 477  */
 478 #define TX_BASE_PTR0                    0x0230
 479 #define TX_MAX_CNT0                     0x0234
 480 #define TX_CTX_IDX0                     0x0238
 481 #define TX_DTX_IDX0                     0x023c
 482
 483 /*
 484  * AC_VI register offsets
 485  */
 486 #define TX_BASE_PTR1                    0x0240
 487 #define TX_MAX_CNT1                     0x0244
 488 #define TX_CTX_IDX1                     0x0248
 489 #define TX_DTX_IDX1                     0x024c
 490
 491 /*
 492  * AC_BE register offsets
 493  */
 494 #define TX_BASE_PTR2                    0x0250
 495 #define TX_MAX_CNT2                     0x0254
 496 #define TX_CTX_IDX2                     0x0258
 497 #define TX_DTX_IDX2                     0x025c
 498
 499 /*
 500  * AC_BK register offsets
 501  */
 502 #define TX_BASE_PTR3                    0x0260
 503 #define TX_MAX_CNT3                     0x0264
 504 #define TX_CTX_IDX3                     0x0268
 505 #define TX_DTX_IDX3                     0x026c
 506
 507 /*
 508  * HCCA register offsets
 509  */
 510 #define TX_BASE_PTR4                    0x0270
 511 #define TX_MAX_CNT4                     0x0274
 512 #define TX_CTX_IDX4                     0x0278
 513 #define TX_DTX_IDX4                     0x027c
 514
 515 /*
 516  * MGMT register offsets
 517  */
 518 #define TX_BASE_PTR5                    0x0280
 519 #define TX_MAX_CNT5                     0x0284
 520 #define TX_CTX_IDX5                     0x0288
 521 #define TX_DTX_IDX5                     0x028c
 522
 523 /*
 524  * RX register offsets
 525  */
 526 #define RX_BASE_PTR                     0x0290
 527 #define RX_MAX_CNT                      0x0294
 528 #define RX_CRX_IDX                      0x0298
 529 #define RX_DRX_IDX                      0x029c
 530
 531 /*
 532  * USB_DMA_CFG
 533  * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
 534  * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
 535  * PHY_CLEAR: phy watch dog enable.
 536  * TX_CLEAR: Clear USB DMA TX path.
 537  * TXOP_HALT: Halt TXOP count down when TX buffer is full.
 538  * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
 539  * RX_BULK_EN: Enable USB DMA Rx.
 540  * TX_BULK_EN: Enable USB DMA Tx.
 541  * EP_OUT_VALID: OUT endpoint data valid.
 542  * RX_BUSY: USB DMA RX FSM busy.
 543  * TX_BUSY: USB DMA TX FSM busy.
 544  */
 545 #define USB_DMA_CFG                     0x02a0
 546 #define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
 547 #define USB_DMA_CFG_RX_BULK_AGG_LIMIT   FIELD32(0x0000ff00)
 548 #define USB_DMA_CFG_PHY_CLEAR           FIELD32(0x00010000)
 549 #define USB_DMA_CFG_TX_CLEAR            FIELD32(0x00080000)
 550 #define USB_DMA_CFG_TXOP_HALT           FIELD32(0x00100000)
 551 #define USB_DMA_CFG_RX_BULK_AGG_EN      FIELD32(0x00200000)
 552 #define USB_DMA_CFG_RX_BULK_EN          FIELD32(0x00400000)
 553 #define USB_DMA_CFG_TX_BULK_EN          FIELD32(0x00800000)
 554 #define USB_DMA_CFG_EP_OUT_VALID        FIELD32(0x3f000000)
 555 #define USB_DMA_CFG_RX_BUSY             FIELD32(0x40000000)
 556 #define USB_DMA_CFG_TX_BUSY             FIELD32(0x80000000)
 557
 558 /*
 559  * US_CYC_CNT
 560  * BT_MODE_EN: Bluetooth mode enable
 561  * CLOCK CYCLE: Clock cycle count in 1us.
 562  * PCI:0x21, PCIE:0x7d, USB:0x1e
 563  */
 564 #define US_CYC_CNT                      0x02a4
 565 #define US_CYC_CNT_BT_MODE_EN           FIELD32(0x00000100)
 566 #define US_CYC_CNT_CLOCK_CYCLE          FIELD32(0x000000ff)
 567
 568 /*
 569  * PBF_SYS_CTRL
 570  * HOST_RAM_WRITE: enable Host program ram write selection
 571  */
 572 #define PBF_SYS_CTRL                    0x0400
 573 #define PBF_SYS_CTRL_READY              FIELD32(0x00000080)
 574 #define PBF_SYS_CTRL_HOST_RAM_WRITE     FIELD32(0x00010000)
 575
 576 /*
 577  * HOST-MCU shared memory
 578  */
 579 #define HOST_CMD_CSR                    0x0404
 580 #define HOST_CMD_CSR_HOST_COMMAND       FIELD32(0x000000ff)
 581
 582 /*
 583  * PBF registers
 584  * Most are for debug. Driver doesn't touch PBF register.
 585  */
 586 #define PBF_CFG                         0x0408
 587 #define PBF_MAX_PCNT                    0x040c
 588 #define PBF_CTRL                        0x0410
 589 #define PBF_INT_STA                     0x0414
 590 #define PBF_INT_ENA                     0x0418
 591
 592 /*
 593  * BCN_OFFSET0:
 594  */
 595 #define BCN_OFFSET0                     0x042c
 596 #define BCN_OFFSET0_BCN0                FIELD32(0x000000ff)
 597 #define BCN_OFFSET0_BCN1                FIELD32(0x0000ff00)
 598 #define BCN_OFFSET0_BCN2                FIELD32(0x00ff0000)
 599 #define BCN_OFFSET0_BCN3                FIELD32(0xff000000)
 600
 601 /*
 602  * BCN_OFFSET1:
 603  */
 604 #define BCN_OFFSET1                     0x0430
 605 #define BCN_OFFSET1_BCN4                FIELD32(0x000000ff)
 606 #define BCN_OFFSET1_BCN5                FIELD32(0x0000ff00)
 607 #define BCN_OFFSET1_BCN6                FIELD32(0x00ff0000)
 608 #define BCN_OFFSET1_BCN7                FIELD32(0xff000000)
 609
 610 /*
 611  * TXRXQ_PCNT: PBF register
 612  * PCNT_TX0Q: Page count for TX hardware queue 0
 613  * PCNT_TX1Q: Page count for TX hardware queue 1
 614  * PCNT_TX2Q: Page count for TX hardware queue 2
 615  * PCNT_RX0Q: Page count for RX hardware queue
 616  */
 617 #define TXRXQ_PCNT                      0x0438
 618 #define TXRXQ_PCNT_TX0Q                 FIELD32(0x000000ff)
 619 #define TXRXQ_PCNT_TX1Q                 FIELD32(0x0000ff00)
 620 #define TXRXQ_PCNT_TX2Q                 FIELD32(0x00ff0000)
 621 #define TXRXQ_PCNT_RX0Q                 FIELD32(0xff000000)
 622
 623 /*
 624  * PBF register
 625  * Debug. Driver doesn't touch PBF register.
 626  */
 627 #define PBF_DBG                         0x043c
 628
 629 /*
 630  * RF registers
 631  */
 632 #define RF_CSR_CFG                      0x0500
 633 #define RF_CSR_CFG_DATA                 FIELD32(0x000000ff)
 634 #define RF_CSR_CFG_REGNUM               FIELD32(0x00003f00)
 635 #define RF_CSR_CFG_WRITE                FIELD32(0x00010000)
 636 #define RF_CSR_CFG_BUSY                 FIELD32(0x00020000)
 637
 638 /*
 639  * EFUSE_CSR: RT30x0 EEPROM
 640  */
 641 #define EFUSE_CTRL                      0x0580
 642 #define EFUSE_CTRL_ADDRESS_IN           FIELD32(0x03fe0000)
 643 #define EFUSE_CTRL_MODE                 FIELD32(0x000000c0)
 644 #define EFUSE_CTRL_KICK                 FIELD32(0x40000000)
 645 #define EFUSE_CTRL_PRESENT              FIELD32(0x80000000)
 646
 647 /*
 648  * EFUSE_DATA0
 649  */
 650 #define EFUSE_DATA0                     0x0590
 651
 652 /*
 653  * EFUSE_DATA1
 654  */
 655 #define EFUSE_DATA1                     0x0594
 656
 657 /*
 658  * EFUSE_DATA2
 659  */
 660 #define EFUSE_DATA2                     0x0598
 661
 662 /*
 663  * EFUSE_DATA3
 664  */
 665 #define EFUSE_DATA3                     0x059c
 666
 667 /*
 668  * LDO_CFG0
 669  */
 670 #define LDO_CFG0                        0x05d4
 671 #define LDO_CFG0_DELAY3                 FIELD32(0x000000ff)
 672 #define LDO_CFG0_DELAY2                 FIELD32(0x0000ff00)
 673 #define LDO_CFG0_DELAY1                 FIELD32(0x00ff0000)
 674 #define LDO_CFG0_BGSEL                  FIELD32(0x03000000)
 675 #define LDO_CFG0_LDO_CORE_VLEVEL        FIELD32(0x1c000000)
 676 #define LD0_CFG0_LDO25_LEVEL            FIELD32(0x60000000)
 677 #define LDO_CFG0_LDO25_LARGEA           FIELD32(0x80000000)
 678
 679 /*
 680  * GPIO_SWITCH
 681  */
 682 #define GPIO_SWITCH                     0x05dc
 683 #define GPIO_SWITCH_0                   FIELD32(0x00000001)
 684 #define GPIO_SWITCH_1                   FIELD32(0x00000002)
 685 #define GPIO_SWITCH_2                   FIELD32(0x00000004)
 686 #define GPIO_SWITCH_3                   FIELD32(0x00000008)
 687 #define GPIO_SWITCH_4                   FIELD32(0x00000010)
 688 #define GPIO_SWITCH_5                   FIELD32(0x00000020)
 689 #define GPIO_SWITCH_6                   FIELD32(0x00000040)
 690 #define GPIO_SWITCH_7                   FIELD32(0x00000080)
 691
 692 /*
 693  * FIXME: where the DEBUG_INDEX name come from?
 694  */
 695 #define MAC_DEBUG_INDEX                 0x05e8
 696 #define MAC_DEBUG_INDEX_XTAL            FIELD32(0x80000000)
 697
 698 /*
 699  * MAC Control/Status Registers(CSR).
 700  * Some values are set in TU, whereas 1 TU == 1024 us.
 701  */
 702
 703 /*
 704  * MAC_CSR0: ASIC revision number.
 705  * ASIC_REV: 0
 706  * ASIC_VER: 2860 or 2870
 707  */
 708 #define MAC_CSR0                        0x1000
 709 #define MAC_CSR0_REVISION               FIELD32(0x0000ffff)
 710 #define MAC_CSR0_CHIPSET                FIELD32(0xffff0000)
 711
 712 /*
 713  * MAC_SYS_CTRL:
 714  */
 715 #define MAC_SYS_CTRL                    0x1004
 716 #define MAC_SYS_CTRL_RESET_CSR          FIELD32(0x00000001)
 717 #define MAC_SYS_CTRL_RESET_BBP          FIELD32(0x00000002)
 718 #define MAC_SYS_CTRL_ENABLE_TX          FIELD32(0x00000004)
 719 #define MAC_SYS_CTRL_ENABLE_RX          FIELD32(0x00000008)
 720 #define MAC_SYS_CTRL_CONTINUOUS_TX      FIELD32(0x00000010)
 721 #define MAC_SYS_CTRL_LOOPBACK           FIELD32(0x00000020)
 722 #define MAC_SYS_CTRL_WLAN_HALT          FIELD32(0x00000040)
 723 #define MAC_SYS_CTRL_RX_TIMESTAMP       FIELD32(0x00000080)
 724
 725 /*
 726  * MAC_ADDR_DW0: STA MAC register 0
 727  */
 728 #define MAC_ADDR_DW0                    0x1008
 729 #define MAC_ADDR_DW0_BYTE0              FIELD32(0x000000ff)
 730 #define MAC_ADDR_DW0_BYTE1              FIELD32(0x0000ff00)
 731 #define MAC_ADDR_DW0_BYTE2              FIELD32(0x00ff0000)
 732 #define MAC_ADDR_DW0_BYTE3              FIELD32(0xff000000)
 733
 734 /*
 735  * MAC_ADDR_DW1: STA MAC register 1
 736  * UNICAST_TO_ME_MASK:
 737  * Used to mask off bits from byte 5 of the MAC address
 738  * to determine the UNICAST_TO_ME bit for RX frames.
 739  * The full mask is complemented by BSS_ID_MASK:
 740  *    MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
 741  */
 742 #define MAC_ADDR_DW1                    0x100c
 743 #define MAC_ADDR_DW1_BYTE4              FIELD32(0x000000ff)
 744 #define MAC_ADDR_DW1_BYTE5              FIELD32(0x0000ff00)
 745 #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
 746
 747 /*
 748  * MAC_BSSID_DW0: BSSID register 0
 749  */
 750 #define MAC_BSSID_DW0                   0x1010
 751 #define MAC_BSSID_DW0_BYTE0             FIELD32(0x000000ff)
 752 #define MAC_BSSID_DW0_BYTE1             FIELD32(0x0000ff00)
 753 #define MAC_BSSID_DW0_BYTE2             FIELD32(0x00ff0000)
 754 #define MAC_BSSID_DW0_BYTE3             FIELD32(0xff000000)
 755
 756 /*
 757  * MAC_BSSID_DW1: BSSID register 1
 758  * BSS_ID_MASK:
 759  *     0: 1-BSSID mode (BSS index = 0)
 760  *     1: 2-BSSID mode (BSS index: Byte5, bit 0)
 761  *     2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
 762  *     3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
 763  * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
 764  * BSSID. This will make sure that those bits will be ignored
 765  * when determining the MY_BSS of RX frames.
 766  */
 767 #define MAC_BSSID_DW1                   0x1014
 768 #define MAC_BSSID_DW1_BYTE4             FIELD32(0x000000ff)
 769 #define MAC_BSSID_DW1_BYTE5             FIELD32(0x0000ff00)
 770 #define MAC_BSSID_DW1_BSS_ID_MASK       FIELD32(0x00030000)
 771 #define MAC_BSSID_DW1_BSS_BCN_NUM       FIELD32(0x001c0000)
 772
 773 /*
 774  * MAX_LEN_CFG: Maximum frame length register.
 775  * MAX_MPDU: rt2860b max 16k bytes
 776  * MAX_PSDU: Maximum PSDU length
 777  *      (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
 778  */
 779 #define MAX_LEN_CFG                     0x1018
 780 #define MAX_LEN_CFG_MAX_MPDU            FIELD32(0x00000fff)
 781 #define MAX_LEN_CFG_MAX_PSDU            FIELD32(0x00003000)
 782 #define MAX_LEN_CFG_MIN_PSDU            FIELD32(0x0000c000)
 783 #define MAX_LEN_CFG_MIN_MPDU            FIELD32(0x000f0000)
 784
 785 /*
 786  * BBP_CSR_CFG: BBP serial control register
 787  * VALUE: Register value to program into BBP
 788  * REG_NUM: Selected BBP register
 789  * READ_CONTROL: 0 write BBP, 1 read BBP
 790  * BUSY: ASIC is busy executing BBP commands
 791  * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
 792  * BBP_RW_MODE: 0 serial, 1 parallel
 793  */
 794 #define BBP_CSR_CFG                     0x101c
 795 #define BBP_CSR_CFG_VALUE               FIELD32(0x000000ff)
 796 #define BBP_CSR_CFG_REGNUM              FIELD32(0x0000ff00)
 797 #define BBP_CSR_CFG_READ_CONTROL        FIELD32(0x00010000)
 798 #define BBP_CSR_CFG_BUSY                FIELD32(0x00020000)
 799 #define BBP_CSR_CFG_BBP_PAR_DUR         FIELD32(0x00040000)
 800 #define BBP_CSR_CFG_BBP_RW_MODE         FIELD32(0x00080000)
 801
 802 /*
 803  * RF_CSR_CFG0: RF control register
 804  * REGID_AND_VALUE: Register value to program into RF
 805  * BITWIDTH: Selected RF register
 806  * STANDBYMODE: 0 high when standby, 1 low when standby
 807  * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
 808  * BUSY: ASIC is busy executing RF commands
 809  */
 810 #define RF_CSR_CFG0                     0x1020
 811 #define RF_CSR_CFG0_REGID_AND_VALUE     FIELD32(0x00ffffff)
 812 #define RF_CSR_CFG0_BITWIDTH            FIELD32(0x1f000000)
 813 #define RF_CSR_CFG0_REG_VALUE_BW        FIELD32(0x1fffffff)
 814 #define RF_CSR_CFG0_STANDBYMODE         FIELD32(0x20000000)
 815 #define RF_CSR_CFG0_SEL                 FIELD32(0x40000000)
 816 #define RF_CSR_CFG0_BUSY                FIELD32(0x80000000)
 817
 818 /*
 819  * RF_CSR_CFG1: RF control register
 820  * REGID_AND_VALUE: Register value to program into RF
 821  * RFGAP: Gap between BB_CONTROL_RF and RF_LE
 822  *        0: 3 system clock cycle (37.5usec)
 823  *        1: 5 system clock cycle (62.5usec)
 824  */
 825 #define RF_CSR_CFG1                     0x1024
 826 #define RF_CSR_CFG1_REGID_AND_VALUE     FIELD32(0x00ffffff)
 827 #define RF_CSR_CFG1_RFGAP               FIELD32(0x1f000000)
 828
 829 /*
 830  * RF_CSR_CFG2: RF control register
 831  * VALUE: Register value to program into RF
 832  */
 833 #define RF_CSR_CFG2                     0x1028
 834 #define RF_CSR_CFG2_VALUE               FIELD32(0x00ffffff)
 835
 836 /*
 837  * LED_CFG: LED control
 838  * ON_PERIOD: LED active time (ms) during TX (only used for LED mode 1)
 839  * OFF_PERIOD: LED inactive time (ms) during TX (only used for LED mode 1)
 840  * SLOW_BLINK_PERIOD: LED blink interval in seconds (only used for LED mode 2)
 841  * color LED's:
 842  *   0: off
 843  *   1: blinking upon TX2
 844  *   2: periodic slow blinking
 845  *   3: always on
 846  * LED polarity:
 847  *   0: active low
 848  *   1: active high
 849  */
 850 #define LED_CFG                         0x102c
 851 #define LED_CFG_ON_PERIOD               FIELD32(0x000000ff)
 852 #define LED_CFG_OFF_PERIOD              FIELD32(0x0000ff00)
 853 #define LED_CFG_SLOW_BLINK_PERIOD       FIELD32(0x003f0000)
 854 #define LED_CFG_R_LED_MODE              FIELD32(0x03000000)
 855 #define LED_CFG_G_LED_MODE              FIELD32(0x0c000000)
 856 #define LED_CFG_Y_LED_MODE              FIELD32(0x30000000)
 857 #define LED_CFG_LED_POLAR               FIELD32(0x40000000)
 858
 859 /*
 860  * AMPDU_BA_WINSIZE: Force BlockAck window size
 861  * FORCE_WINSIZE_ENABLE:
 862  *   0: Disable forcing of BlockAck window size
 863  *   1: Enable forcing of BlockAck window size, overwrites values BlockAck
 864  *      window size values in the TXWI
 865  * FORCE_WINSIZE: BlockAck window size
 866  */
 867 #define AMPDU_BA_WINSIZE                0x1040
 868 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE FIELD32(0x00000020)
 869 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE  FIELD32(0x0000001f)
 870
 871 /*
 872  * XIFS_TIME_CFG: MAC timing
 873  * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
 874  * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
 875  * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
 876  *      when MAC doesn't reference BBP signal BBRXEND
 877  * EIFS: unit 1us
 878  * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
 879  *
 880  */
 881 #define XIFS_TIME_CFG                   0x1100
 882 #define XIFS_TIME_CFG_CCKM_SIFS_TIME    FIELD32(0x000000ff)
 883 #define XIFS_TIME_CFG_OFDM_SIFS_TIME    FIELD32(0x0000ff00)
 884 #define XIFS_TIME_CFG_OFDM_XIFS_TIME    FIELD32(0x000f0000)
 885 #define XIFS_TIME_CFG_EIFS              FIELD32(0x1ff00000)
 886 #define XIFS_TIME_CFG_BB_RXEND_ENABLE   FIELD32(0x20000000)
 887
 888 /*
 889  * BKOFF_SLOT_CFG:
 890  */
 891 #define BKOFF_SLOT_CFG                  0x1104
 892 #define BKOFF_SLOT_CFG_SLOT_TIME        FIELD32(0x000000ff)
 893 #define BKOFF_SLOT_CFG_CC_DELAY_TIME    FIELD32(0x0000ff00)
 894
 895 /*
 896  * NAV_TIME_CFG:
 897  */
 898 #define NAV_TIME_CFG                    0x1108
 899 #define NAV_TIME_CFG_SIFS               FIELD32(0x000000ff)
 900 #define NAV_TIME_CFG_SLOT_TIME          FIELD32(0x0000ff00)
 901 #define NAV_TIME_CFG_EIFS               FIELD32(0x01ff0000)
 902 #define NAV_TIME_ZERO_SIFS              FIELD32(0x02000000)
 903
 904 /*
 905  * CH_TIME_CFG: count as channel busy
 906  * EIFS_BUSY: Count EIFS as channel busy
 907  * NAV_BUSY: Count NAS as channel busy
 908  * RX_BUSY: Count RX as channel busy
 909  * TX_BUSY: Count TX as channel busy
 910  * TMR_EN: Enable channel statistics timer
 911  */
 912 #define CH_TIME_CFG                     0x110c
 913 #define CH_TIME_CFG_EIFS_BUSY           FIELD32(0x00000010)
 914 #define CH_TIME_CFG_NAV_BUSY            FIELD32(0x00000008)
 915 #define CH_TIME_CFG_RX_BUSY             FIELD32(0x00000004)
 916 #define CH_TIME_CFG_TX_BUSY             FIELD32(0x00000002)
 917 #define CH_TIME_CFG_TMR_EN              FIELD32(0x00000001)
 918
 919 /*
 920  * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
 921  */
 922 #define PBF_LIFE_TIMER                  0x1110
 923
 924 /*
 925  * BCN_TIME_CFG:
 926  * BEACON_INTERVAL: in unit of 1/16 TU
 927  * TSF_TICKING: Enable TSF auto counting
 928  * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
 929  * BEACON_GEN: Enable beacon generator
 930  */
 931 #define BCN_TIME_CFG                    0x1114
 932 #define BCN_TIME_CFG_BEACON_INTERVAL    FIELD32(0x0000ffff)
 933 #define BCN_TIME_CFG_TSF_TICKING        FIELD32(0x00010000)
 934 #define BCN_TIME_CFG_TSF_SYNC           FIELD32(0x00060000)
 935 #define BCN_TIME_CFG_TBTT_ENABLE        FIELD32(0x00080000)
 936 #define BCN_TIME_CFG_BEACON_GEN         FIELD32(0x00100000)
 937 #define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
 938
 939 /*
 940  * TBTT_SYNC_CFG:
 941  * BCN_AIFSN: Beacon AIFSN after TBTT interrupt in slots
 942  * BCN_CWMIN: Beacon CWMin after TBTT interrupt in slots
 943  */
 944 #define TBTT_SYNC_CFG                   0x1118
 945 #define TBTT_SYNC_CFG_TBTT_ADJUST       FIELD32(0x000000ff)
 946 #define TBTT_SYNC_CFG_BCN_EXP_WIN       FIELD32(0x0000ff00)
 947 #define TBTT_SYNC_CFG_BCN_AIFSN         FIELD32(0x000f0000)
 948 #define TBTT_SYNC_CFG_BCN_CWMIN         FIELD32(0x00f00000)
 949
 950 /*
 951  * TSF_TIMER_DW0: Local lsb TSF timer, read-only
 952  */
 953 #define TSF_TIMER_DW0                   0x111c
 954 #define TSF_TIMER_DW0_LOW_WORD          FIELD32(0xffffffff)
 955
 956 /*
 957  * TSF_TIMER_DW1: Local msb TSF timer, read-only
 958  */
 959 #define TSF_TIMER_DW1                   0x1120
 960 #define TSF_TIMER_DW1_HIGH_WORD         FIELD32(0xffffffff)
 961
 962 /*
 963  * TBTT_TIMER: TImer remains till next TBTT, read-only
 964  */
 965 #define TBTT_TIMER                      0x1124
 966
 967 /*
 968  * INT_TIMER_CFG: timer configuration
 969  * PRE_TBTT_TIMER: leadtime to tbtt for pretbtt interrupt in units of 1/16 TU
 970  * GP_TIMER: period of general purpose timer in units of 1/16 TU
 971  */
 972 #define INT_TIMER_CFG                   0x1128
 973 #define INT_TIMER_CFG_PRE_TBTT_TIMER    FIELD32(0x0000ffff)
 974 #define INT_TIMER_CFG_GP_TIMER          FIELD32(0xffff0000)
 975
 976 /*
 977  * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
 978  */
 979 #define INT_TIMER_EN                    0x112c
 980 #define INT_TIMER_EN_PRE_TBTT_TIMER     FIELD32(0x00000001)
 981 #define INT_TIMER_EN_GP_TIMER           FIELD32(0x00000002)
 982
 983 /*
 984  * CH_IDLE_STA: channel idle time (in us)
 985  */
 986 #define CH_IDLE_STA                     0x1130
 987
 988 /*
 989  * CH_BUSY_STA: channel busy time on primary channel (in us)
 990  */
 991 #define CH_BUSY_STA                     0x1134
 992
 993 /*
 994  * CH_BUSY_STA_SEC: channel busy time on secondary channel in HT40 mode (in us)
 995  */
 996 #define CH_BUSY_STA_SEC                 0x1138
 997
 998 /*
 999  * MAC_STATUS_CFG:
1000  * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
1001  *      if 1 or higher one of the 2 registers is busy.
1002  */
1003 #define MAC_STATUS_CFG                  0x1200
1004 #define MAC_STATUS_CFG_BBP_RF_BUSY      FIELD32(0x00000003)
1005
1006 /*
1007  * PWR_PIN_CFG:
1008  */
1009 #define PWR_PIN_CFG                     0x1204
1010
1011 /*
1012  * AUTOWAKEUP_CFG: Manual power control / status register
1013  * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
1014  * AUTOWAKE: 0:sleep, 1:awake
1015  */
1016 #define AUTOWAKEUP_CFG                  0x1208
1017 #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME   FIELD32(0x000000ff)
1018 #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
1019 #define AUTOWAKEUP_CFG_AUTOWAKE         FIELD32(0x00008000)
1020
1021 /*
1022  * EDCA_AC0_CFG:
1023  */
1024 #define EDCA_AC0_CFG                    0x1300
1025 #define EDCA_AC0_CFG_TX_OP              FIELD32(0x000000ff)
1026 #define EDCA_AC0_CFG_AIFSN              FIELD32(0x00000f00)
1027 #define EDCA_AC0_CFG_CWMIN              FIELD32(0x0000f000)
1028 #define EDCA_AC0_CFG_CWMAX              FIELD32(0x000f0000)
1029
1030 /*
1031  * EDCA_AC1_CFG:
1032  */
1033 #define EDCA_AC1_CFG                    0x1304
1034 #define EDCA_AC1_CFG_TX_OP              FIELD32(0x000000ff)
1035 #define EDCA_AC1_CFG_AIFSN              FIELD32(0x00000f00)
1036 #define EDCA_AC1_CFG_CWMIN              FIELD32(0x0000f000)
1037 #define EDCA_AC1_CFG_CWMAX              FIELD32(0x000f0000)
1038
1039 /*
1040  * EDCA_AC2_CFG:
1041  */
1042 #define EDCA_AC2_CFG                    0x1308
1043 #define EDCA_AC2_CFG_TX_OP              FIELD32(0x000000ff)
1044 #define EDCA_AC2_CFG_AIFSN              FIELD32(0x00000f00)
1045 #define EDCA_AC2_CFG_CWMIN              FIELD32(0x0000f000)
1046 #define EDCA_AC2_CFG_CWMAX              FIELD32(0x000f0000)
1047
1048 /*
1049  * EDCA_AC3_CFG:
1050  */
1051 #define EDCA_AC3_CFG                    0x130c
1052 #define EDCA_AC3_CFG_TX_OP              FIELD32(0x000000ff)
1053 #define EDCA_AC3_CFG_AIFSN              FIELD32(0x00000f00)
1054 #define EDCA_AC3_CFG_CWMIN              FIELD32(0x0000f000)
1055 #define EDCA_AC3_CFG_CWMAX              FIELD32(0x000f0000)
1056
1057 /*
1058  * EDCA_TID_AC_MAP:
1059  */
1060 #define EDCA_TID_AC_MAP                 0x1310
1061
1062 /*
1063  * TX_PWR_CFG:
1064  */
1065 #define TX_PWR_CFG_RATE0                FIELD32(0x0000000f)
1066 #define TX_PWR_CFG_RATE1                FIELD32(0x000000f0)
1067 #define TX_PWR_CFG_RATE2                FIELD32(0x00000f00)
1068 #define TX_PWR_CFG_RATE3                FIELD32(0x0000f000)
1069 #define TX_PWR_CFG_RATE4                FIELD32(0x000f0000)
1070 #define TX_PWR_CFG_RATE5                FIELD32(0x00f00000)
1071 #define TX_PWR_CFG_RATE6                FIELD32(0x0f000000)
1072 #define TX_PWR_CFG_RATE7                FIELD32(0xf0000000)
1073
1074 /*
1075  * TX_PWR_CFG_0:
1076  */
1077 #define TX_PWR_CFG_0                    0x1314
1078 #define TX_PWR_CFG_0_1MBS               FIELD32(0x0000000f)
1079 #define TX_PWR_CFG_0_2MBS               FIELD32(0x000000f0)
1080 #define TX_PWR_CFG_0_55MBS              FIELD32(0x00000f00)
1081 #define TX_PWR_CFG_0_11MBS              FIELD32(0x0000f000)
1082 #define TX_PWR_CFG_0_6MBS               FIELD32(0x000f0000)
1083 #define TX_PWR_CFG_0_9MBS               FIELD32(0x00f00000)
1084 #define TX_PWR_CFG_0_12MBS              FIELD32(0x0f000000)
1085 #define TX_PWR_CFG_0_18MBS              FIELD32(0xf0000000)
1086 /* bits for 3T devices */
1087 #define TX_PWR_CFG_0_CCK1_CH0           FIELD32(0x0000000f)
1088 #define TX_PWR_CFG_0_CCK1_CH1           FIELD32(0x000000f0)
1089 #define TX_PWR_CFG_0_CCK5_CH0           FIELD32(0x00000f00)
1090 #define TX_PWR_CFG_0_CCK5_CH1           FIELD32(0x0000f000)
1091 #define TX_PWR_CFG_0_OFDM6_CH0          FIELD32(0x000f0000)
1092 #define TX_PWR_CFG_0_OFDM6_CH1          FIELD32(0x00f00000)
1093 #define TX_PWR_CFG_0_OFDM12_CH0         FIELD32(0x0f000000)
1094 #define TX_PWR_CFG_0_OFDM12_CH1         FIELD32(0xf0000000)
1095
1096 /*
1097  * TX_PWR_CFG_1:
1098  */
1099 #define TX_PWR_CFG_1                    0x1318
1100 #define TX_PWR_CFG_1_24MBS              FIELD32(0x0000000f)
1101 #define TX_PWR_CFG_1_36MBS              FIELD32(0x000000f0)
1102 #define TX_PWR_CFG_1_48MBS              FIELD32(0x00000f00)
1103 #define TX_PWR_CFG_1_54MBS              FIELD32(0x0000f000)
1104 #define TX_PWR_CFG_1_MCS0               FIELD32(0x000f0000)
1105 #define TX_PWR_CFG_1_MCS1               FIELD32(0x00f00000)
1106 #define TX_PWR_CFG_1_MCS2               FIELD32(0x0f000000)
1107 #define TX_PWR_CFG_1_MCS3               FIELD32(0xf0000000)
1108 /* bits for 3T devices */
1109 #define TX_PWR_CFG_1_OFDM24_CH0         FIELD32(0x0000000f)
1110 #define TX_PWR_CFG_1_OFDM24_CH1         FIELD32(0x000000f0)
1111 #define TX_PWR_CFG_1_OFDM48_CH0         FIELD32(0x00000f00)
1112 #define TX_PWR_CFG_1_OFDM48_CH1         FIELD32(0x0000f000)
1113 #define TX_PWR_CFG_1_MCS0_CH0           FIELD32(0x000f0000)
1114 #define TX_PWR_CFG_1_MCS0_CH1           FIELD32(0x00f00000)
1115 #define TX_PWR_CFG_1_MCS2_CH0           FIELD32(0x0f000000)
1116 #define TX_PWR_CFG_1_MCS2_CH1           FIELD32(0xf0000000)
1117
1118 /*
1119  * TX_PWR_CFG_2:
1120  */
1121 #define TX_PWR_CFG_2                    0x131c
1122 #define TX_PWR_CFG_2_MCS4               FIELD32(0x0000000f)
1123 #define TX_PWR_CFG_2_MCS5               FIELD32(0x000000f0)
1124 #define TX_PWR_CFG_2_MCS6               FIELD32(0x00000f00)
1125 #define TX_PWR_CFG_2_MCS7               FIELD32(0x0000f000)
1126 #define TX_PWR_CFG_2_MCS8               FIELD32(0x000f0000)
1127 #define TX_PWR_CFG_2_MCS9               FIELD32(0x00f00000)
1128 #define TX_PWR_CFG_2_MCS10              FIELD32(0x0f000000)
1129 #define TX_PWR_CFG_2_MCS11              FIELD32(0xf0000000)
1130 /* bits for 3T devices */
1131 #define TX_PWR_CFG_2_MCS4_CH0           FIELD32(0x0000000f)
1132 #define TX_PWR_CFG_2_MCS4_CH1           FIELD32(0x000000f0)
1133 #define TX_PWR_CFG_2_MCS6_CH0           FIELD32(0x00000f00)
1134 #define TX_PWR_CFG_2_MCS6_CH1           FIELD32(0x0000f000)
1135 #define TX_PWR_CFG_2_MCS8_CH0           FIELD32(0x000f0000)
1136 #define TX_PWR_CFG_2_MCS8_CH1           FIELD32(0x00f00000)
1137 #define TX_PWR_CFG_2_MCS10_CH0          FIELD32(0x0f000000)
1138 #define TX_PWR_CFG_2_MCS10_CH1          FIELD32(0xf0000000)
1139
1140 /*
1141  * TX_PWR_CFG_3:
1142  */
1143 #define TX_PWR_CFG_3                    0x1320
1144 #define TX_PWR_CFG_3_MCS12              FIELD32(0x0000000f)
1145 #define TX_PWR_CFG_3_MCS13              FIELD32(0x000000f0)
1146 #define TX_PWR_CFG_3_MCS14              FIELD32(0x00000f00)
1147 #define TX_PWR_CFG_3_MCS15              FIELD32(0x0000f000)
1148 #define TX_PWR_CFG_3_UKNOWN1            FIELD32(0x000f0000)
1149 #define TX_PWR_CFG_3_UKNOWN2            FIELD32(0x00f00000)
1150 #define TX_PWR_CFG_3_UKNOWN3            FIELD32(0x0f000000)
1151 #define TX_PWR_CFG_3_UKNOWN4            FIELD32(0xf0000000)
1152 /* bits for 3T devices */
1153 #define TX_PWR_CFG_3_MCS12_CH0          FIELD32(0x0000000f)
1154 #define TX_PWR_CFG_3_MCS12_CH1          FIELD32(0x000000f0)
1155 #define TX_PWR_CFG_3_MCS14_CH0          FIELD32(0x00000f00)
1156 #define TX_PWR_CFG_3_MCS14_CH1          FIELD32(0x0000f000)
1157 #define TX_PWR_CFG_3_STBC0_CH0          FIELD32(0x000f0000)
1158 #define TX_PWR_CFG_3_STBC0_CH1          FIELD32(0x00f00000)
1159 #define TX_PWR_CFG_3_STBC2_CH0          FIELD32(0x0f000000)
1160 #define TX_PWR_CFG_3_STBC2_CH1          FIELD32(0xf0000000)
1161
1162 /*
1163  * TX_PWR_CFG_4:
1164  */
1165 #define TX_PWR_CFG_4                    0x1324
1166 #define TX_PWR_CFG_4_UKNOWN5            FIELD32(0x0000000f)
1167 #define TX_PWR_CFG_4_UKNOWN6            FIELD32(0x000000f0)
1168 #define TX_PWR_CFG_4_UKNOWN7            FIELD32(0x00000f00)
1169 #define TX_PWR_CFG_4_UKNOWN8            FIELD32(0x0000f000)
1170 /* bits for 3T devices */
1171 #define TX_PWR_CFG_3_STBC4_CH0          FIELD32(0x0000000f)
1172 #define TX_PWR_CFG_3_STBC4_CH1          FIELD32(0x000000f0)
1173 #define TX_PWR_CFG_3_STBC6_CH0          FIELD32(0x00000f00)
1174 #define TX_PWR_CFG_3_STBC6_CH1          FIELD32(0x0000f000)
1175
1176 /*
1177  * TX_PIN_CFG:
1178  */
1179 #define TX_PIN_CFG                      0x1328
1180 #define TX_PIN_CFG_PA_PE_DISABLE        0xfcfffff0
1181 #define TX_PIN_CFG_PA_PE_A0_EN          FIELD32(0x00000001)
1182 #define TX_PIN_CFG_PA_PE_G0_EN          FIELD32(0x00000002)
1183 #define TX_PIN_CFG_PA_PE_A1_EN          FIELD32(0x00000004)
1184 #define TX_PIN_CFG_PA_PE_G1_EN          FIELD32(0x00000008)
1185 #define TX_PIN_CFG_PA_PE_A0_POL         FIELD32(0x00000010)
1186 #define TX_PIN_CFG_PA_PE_G0_POL         FIELD32(0x00000020)
1187 #define TX_PIN_CFG_PA_PE_A1_POL         FIELD32(0x00000040)
1188 #define TX_PIN_CFG_PA_PE_G1_POL         FIELD32(0x00000080)
1189 #define TX_PIN_CFG_LNA_PE_A0_EN         FIELD32(0x00000100)
1190 #define TX_PIN_CFG_LNA_PE_G0_EN         FIELD32(0x00000200)
1191 #define TX_PIN_CFG_LNA_PE_A1_EN         FIELD32(0x00000400)
1192 #define TX_PIN_CFG_LNA_PE_G1_EN         FIELD32(0x00000800)
1193 #define TX_PIN_CFG_LNA_PE_A0_POL        FIELD32(0x00001000)
1194 #define TX_PIN_CFG_LNA_PE_G0_POL        FIELD32(0x00002000)
1195 #define TX_PIN_CFG_LNA_PE_A1_POL        FIELD32(0x00004000)
1196 #define TX_PIN_CFG_LNA_PE_G1_POL        FIELD32(0x00008000)
1197 #define TX_PIN_CFG_RFTR_EN              FIELD32(0x00010000)
1198 #define TX_PIN_CFG_RFTR_POL             FIELD32(0x00020000)
1199 #define TX_PIN_CFG_TRSW_EN              FIELD32(0x00040000)
1200 #define TX_PIN_CFG_TRSW_POL             FIELD32(0x00080000)
1201 #define TX_PIN_CFG_PA_PE_A2_EN          FIELD32(0x01000000)
1202 #define TX_PIN_CFG_PA_PE_G2_EN          FIELD32(0x02000000)
1203 #define TX_PIN_CFG_PA_PE_A2_POL         FIELD32(0x04000000)
1204 #define TX_PIN_CFG_PA_PE_G2_POL         FIELD32(0x08000000)
1205 #define TX_PIN_CFG_LNA_PE_A2_EN         FIELD32(0x10000000)
1206 #define TX_PIN_CFG_LNA_PE_G2_EN         FIELD32(0x20000000)
1207 #define TX_PIN_CFG_LNA_PE_A2_POL        FIELD32(0x40000000)
1208 #define TX_PIN_CFG_LNA_PE_G2_POL        FIELD32(0x80000000)
1209
1210 /*
1211  * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
1212  */
1213 #define TX_BAND_CFG                     0x132c
1214 #define TX_BAND_CFG_HT40_MINUS          FIELD32(0x00000001)
1215 #define TX_BAND_CFG_A                   FIELD32(0x00000002)
1216 #define TX_BAND_CFG_BG                  FIELD32(0x00000004)
1217
1218 /*
1219  * TX_SW_CFG0:
1220  */
1221 #define TX_SW_CFG0                      0x1330
1222
1223 /*
1224  * TX_SW_CFG1:
1225  */
1226 #define TX_SW_CFG1                      0x1334
1227
1228 /*
1229  * TX_SW_CFG2:
1230  */
1231 #define TX_SW_CFG2                      0x1338
1232
1233 /*
1234  * TXOP_THRES_CFG:
1235  */
1236 #define TXOP_THRES_CFG                  0x133c
1237
1238 /*
1239  * TXOP_CTRL_CFG:
1240  * TIMEOUT_TRUN_EN: Enable/Disable TXOP timeout truncation
1241  * AC_TRUN_EN: Enable/Disable truncation for AC change
1242  * TXRATEGRP_TRUN_EN: Enable/Disable truncation for TX rate group change
1243  * USER_MODE_TRUN_EN: Enable/Disable truncation for user TXOP mode
1244  * MIMO_PS_TRUN_EN: Enable/Disable truncation for MIMO PS RTS/CTS
1245  * RESERVED_TRUN_EN: Reserved
1246  * LSIG_TXOP_EN: Enable/Disable L-SIG TXOP protection
1247  * EXT_CCA_EN: Enable/Disable extension channel CCA reference (Defer 40Mhz
1248  *             transmissions if extension CCA is clear).
1249  * EXT_CCA_DLY: Extension CCA signal delay time (unit: us)
1250  * EXT_CWMIN: CwMin for extension channel backoff
1251  *            0: Disabled
1252  *
1253  */
1254 #define TXOP_CTRL_CFG                   0x1340
1255 #define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN   FIELD32(0x00000001)
1256 #define TXOP_CTRL_CFG_AC_TRUN_EN        FIELD32(0x00000002)
1257 #define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN FIELD32(0x00000004)
1258 #define TXOP_CTRL_CFG_USER_MODE_TRUN_EN FIELD32(0x00000008)
1259 #define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN   FIELD32(0x00000010)
1260 #define TXOP_CTRL_CFG_RESERVED_TRUN_EN  FIELD32(0x00000020)
1261 #define TXOP_CTRL_CFG_LSIG_TXOP_EN      FIELD32(0x00000040)
1262 #define TXOP_CTRL_CFG_EXT_CCA_EN        FIELD32(0x00000080)
1263 #define TXOP_CTRL_CFG_EXT_CCA_DLY       FIELD32(0x0000ff00)
1264 #define TXOP_CTRL_CFG_EXT_CWMIN         FIELD32(0x000f0000)
1265
1266 /*
1267  * TX_RTS_CFG:
1268  * RTS_THRES: unit:byte
1269  * RTS_FBK_EN: enable rts rate fallback
1270  */
1271 #define TX_RTS_CFG                      0x1344
1272 #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
1273 #define TX_RTS_CFG_RTS_THRES            FIELD32(0x00ffff00)
1274 #define TX_RTS_CFG_RTS_FBK_EN           FIELD32(0x01000000)
1275
1276 /*
1277  * TX_TIMEOUT_CFG:
1278  * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
1279  * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
1280  * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
1281  *                it is recommended that:
1282  *                (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
1283  */
1284 #define TX_TIMEOUT_CFG                  0x1348
1285 #define TX_TIMEOUT_CFG_MPDU_LIFETIME    FIELD32(0x000000f0)
1286 #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT   FIELD32(0x0000ff00)
1287 #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT    FIELD32(0x00ff0000)
1288
1289 /*
1290  * TX_RTY_CFG:
1291  * SHORT_RTY_LIMIT: short retry limit
1292  * LONG_RTY_LIMIT: long retry limit
1293  * LONG_RTY_THRE: Long retry threshoold
1294  * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
1295  *                   0:expired by retry limit, 1: expired by mpdu life timer
1296  * AGG_RTY_MODE: Aggregate MPDU retry mode
1297  *               0:expired by retry limit, 1: expired by mpdu life timer
1298  * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
1299  */
1300 #define TX_RTY_CFG                      0x134c
1301 #define TX_RTY_CFG_SHORT_RTY_LIMIT      FIELD32(0x000000ff)
1302 #define TX_RTY_CFG_LONG_RTY_LIMIT       FIELD32(0x0000ff00)
1303 #define TX_RTY_CFG_LONG_RTY_THRE        FIELD32(0x0fff0000)
1304 #define TX_RTY_CFG_NON_AGG_RTY_MODE     FIELD32(0x10000000)
1305 #define TX_RTY_CFG_AGG_RTY_MODE         FIELD32(0x20000000)
1306 #define TX_RTY_CFG_TX_AUTO_FB_ENABLE    FIELD32(0x40000000)
1307
1308 /*
1309  * TX_LINK_CFG:
1310  * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
1311  * MFB_ENABLE: TX apply remote MFB 1:enable
1312  * REMOTE_UMFS_ENABLE: remote unsolicit  MFB enable
1313  *                     0: not apply remote remote unsolicit (MFS=7)
1314  * TX_MRQ_EN: MCS request TX enable
1315  * TX_RDG_EN: RDG TX enable
1316  * TX_CF_ACK_EN: Piggyback CF-ACK enable
1317  * REMOTE_MFB: remote MCS feedback
1318  * REMOTE_MFS: remote MCS feedback sequence number
1319  */
1320 #define TX_LINK_CFG                     0x1350
1321 #define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
1322 #define TX_LINK_CFG_MFB_ENABLE          FIELD32(0x00000100)
1323 #define TX_LINK_CFG_REMOTE_UMFS_ENABLE  FIELD32(0x00000200)
1324 #define TX_LINK_CFG_TX_MRQ_EN           FIELD32(0x00000400)
1325 #define TX_LINK_CFG_TX_RDG_EN           FIELD32(0x00000800)
1326 #define TX_LINK_CFG_TX_CF_ACK_EN        FIELD32(0x00001000)
1327 #define TX_LINK_CFG_REMOTE_MFB          FIELD32(0x00ff0000)
1328 #define TX_LINK_CFG_REMOTE_MFS          FIELD32(0xff000000)
1329
1330 /*
1331  * HT_FBK_CFG0:
1332  */
1333 #define HT_FBK_CFG0                     0x1354
1334 #define HT_FBK_CFG0_HTMCS0FBK           FIELD32(0x0000000f)
1335 #define HT_FBK_CFG0_HTMCS1FBK           FIELD32(0x000000f0)
1336 #define HT_FBK_CFG0_HTMCS2FBK           FIELD32(0x00000f00)
1337 #define HT_FBK_CFG0_HTMCS3FBK           FIELD32(0x0000f000)
1338 #define HT_FBK_CFG0_HTMCS4FBK           FIELD32(0x000f0000)
1339 #define HT_FBK_CFG0_HTMCS5FBK           FIELD32(0x00f00000)
1340 #define HT_FBK_CFG0_HTMCS6FBK           FIELD32(0x0f000000)
1341 #define HT_FBK_CFG0_HTMCS7FBK           FIELD32(0xf0000000)
1342
1343 /*
1344  * HT_FBK_CFG1:
1345  */
1346 #define HT_FBK_CFG1                     0x1358
1347 #define HT_FBK_CFG1_HTMCS8FBK           FIELD32(0x0000000f)
1348 #define HT_FBK_CFG1_HTMCS9FBK           FIELD32(0x000000f0)
1349 #define HT_FBK_CFG1_HTMCS10FBK          FIELD32(0x00000f00)
1350 #define HT_FBK_CFG1_HTMCS11FBK          FIELD32(0x0000f000)
1351 #define HT_FBK_CFG1_HTMCS12FBK          FIELD32(0x000f0000)
1352 #define HT_FBK_CFG1_HTMCS13FBK          FIELD32(0x00f00000)
1353 #define HT_FBK_CFG1_HTMCS14FBK          FIELD32(0x0f000000)
1354 #define HT_FBK_CFG1_HTMCS15FBK          FIELD32(0xf0000000)
1355
1356 /*
1357  * LG_FBK_CFG0:
1358  */
1359 #define LG_FBK_CFG0                     0x135c
1360 #define LG_FBK_CFG0_OFDMMCS0FBK         FIELD32(0x0000000f)
1361 #define LG_FBK_CFG0_OFDMMCS1FBK         FIELD32(0x000000f0)
1362 #define LG_FBK_CFG0_OFDMMCS2FBK         FIELD32(0x00000f00)
1363 #define LG_FBK_CFG0_OFDMMCS3FBK         FIELD32(0x0000f000)
1364 #define LG_FBK_CFG0_OFDMMCS4FBK         FIELD32(0x000f0000)
1365 #define LG_FBK_CFG0_OFDMMCS5FBK         FIELD32(0x00f00000)
1366 #define LG_FBK_CFG0_OFDMMCS6FBK         FIELD32(0x0f000000)
1367 #define LG_FBK_CFG0_OFDMMCS7FBK         FIELD32(0xf0000000)
1368
1369 /*
1370  * LG_FBK_CFG1:
1371  */
1372 #define LG_FBK_CFG1                     0x1360
1373 #define LG_FBK_CFG0_CCKMCS0FBK          FIELD32(0x0000000f)
1374 #define LG_FBK_CFG0_CCKMCS1FBK          FIELD32(0x000000f0)
1375 #define LG_FBK_CFG0_CCKMCS2FBK          FIELD32(0x00000f00)
1376 #define LG_FBK_CFG0_CCKMCS3FBK          FIELD32(0x0000f000)
1377
1378 /*
1379  * CCK_PROT_CFG: CCK Protection
1380  * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
1381  * PROTECT_CTRL: Protection control frame type for CCK TX
1382  *               0:none, 1:RTS/CTS, 2:CTS-to-self
1383  * PROTECT_NAV_SHORT: TXOP protection type for CCK TX with short NAV
1384  * PROTECT_NAV_LONG: TXOP protection type for CCK TX with long NAV
1385  * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
1386  * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
1387  * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
1388  * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
1389  * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
1390  * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
1391  * RTS_TH_EN: RTS threshold enable on CCK TX
1392  */
1393 #define CCK_PROT_CFG                    0x1364
1394 #define CCK_PROT_CFG_PROTECT_RATE       FIELD32(0x0000ffff)
1395 #define CCK_PROT_CFG_PROTECT_CTRL       FIELD32(0x00030000)
1396 #define CCK_PROT_CFG_PROTECT_NAV_SHORT  FIELD32(0x00040000)
1397 #define CCK_PROT_CFG_PROTECT_NAV_LONG   FIELD32(0x00080000)
1398 #define CCK_PROT_CFG_TX_OP_ALLOW_CCK    FIELD32(0x00100000)
1399 #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM   FIELD32(0x00200000)
1400 #define CCK_PROT_CFG_TX_OP_ALLOW_MM20   FIELD32(0x00400000)
1401 #define CCK_PROT_CFG_TX_OP_ALLOW_MM40   FIELD32(0x00800000)
1402 #define CCK_PROT_CFG_TX_OP_ALLOW_GF20   FIELD32(0x01000000)
1403 #define CCK_PROT_CFG_TX_OP_ALLOW_GF40   FIELD32(0x02000000)
1404 #define CCK_PROT_CFG_RTS_TH_EN          FIELD32(0x04000000)
1405
1406 /*
1407  * OFDM_PROT_CFG: OFDM Protection
1408  */
1409 #define OFDM_PROT_CFG                   0x1368
1410 #define OFDM_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
1411 #define OFDM_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
1412 #define OFDM_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1413 #define OFDM_PROT_CFG_PROTECT_NAV_LONG  FIELD32(0x00080000)
1414 #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
1415 #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
1416 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
1417 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
1418 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
1419 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
1420 #define OFDM_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
1421
1422 /*
1423  * MM20_PROT_CFG: MM20 Protection
1424  */
1425 #define MM20_PROT_CFG                   0x136c
1426 #define MM20_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
1427 #define MM20_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
1428 #define MM20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1429 #define MM20_PROT_CFG_PROTECT_NAV_LONG  FIELD32(0x00080000)
1430 #define MM20_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
1431 #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
1432 #define MM20_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
1433 #define MM20_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
1434 #define MM20_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
1435 #define MM20_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
1436 #define MM20_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
1437
1438 /*
1439  * MM40_PROT_CFG: MM40 Protection
1440  */
1441 #define MM40_PROT_CFG                   0x1370
1442 #define MM40_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
1443 #define MM40_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
1444 #define MM40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1445 #define MM40_PROT_CFG_PROTECT_NAV_LONG  FIELD32(0x00080000)
1446 #define MM40_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
1447 #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
1448 #define MM40_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
1449 #define MM40_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
1450 #define MM40_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
1451 #define MM40_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
1452 #define MM40_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
1453
1454 /*
1455  * GF20_PROT_CFG: GF20 Protection
1456  */
1457 #define GF20_PROT_CFG                   0x1374
1458 #define GF20_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
1459 #define GF20_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
1460 #define GF20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1461 #define GF20_PROT_CFG_PROTECT_NAV_LONG  FIELD32(0x00080000)
1462 #define GF20_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
1463 #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
1464 #define GF20_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
1465 #define GF20_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
1466 #define GF20_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
1467 #define GF20_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
1468 #define GF20_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
1469
1470 /*
1471  * GF40_PROT_CFG: GF40 Protection
1472  */
1473 #define GF40_PROT_CFG                   0x1378
1474 #define GF40_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
1475 #define GF40_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
1476 #define GF40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1477 #define GF40_PROT_CFG_PROTECT_NAV_LONG  FIELD32(0x00080000)
1478 #define GF40_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
1479 #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
1480 #define GF40_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
1481 #define GF40_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
1482 #define GF40_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
1483 #define GF40_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
1484 #define GF40_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
1485
1486 /*
1487  * EXP_CTS_TIME:
1488  */
1489 #define EXP_CTS_TIME                    0x137c
1490
1491 /*
1492  * EXP_ACK_TIME:
1493  */
1494 #define EXP_ACK_TIME                    0x1380
1495
1496 /* TX_PWR_CFG_5 */
1497 #define TX_PWR_CFG_5                    0x1384
1498 #define TX_PWR_CFG_5_MCS16_CH0          FIELD32(0x0000000f)
1499 #define TX_PWR_CFG_5_MCS16_CH1          FIELD32(0x000000f0)
1500 #define TX_PWR_CFG_5_MCS16_CH2          FIELD32(0x00000f00)
1501 #define TX_PWR_CFG_5_MCS18_CH0          FIELD32(0x000f0000)
1502 #define TX_PWR_CFG_5_MCS18_CH1          FIELD32(0x00f00000)
1503 #define TX_PWR_CFG_5_MCS18_CH2          FIELD32(0x0f000000)
1504
1505 /* TX_PWR_CFG_6 */
1506 #define TX_PWR_CFG_6                    0x1388
1507 #define TX_PWR_CFG_6_MCS20_CH0          FIELD32(0x0000000f)
1508 #define TX_PWR_CFG_6_MCS20_CH1          FIELD32(0x000000f0)
1509 #define TX_PWR_CFG_6_MCS20_CH2          FIELD32(0x00000f00)
1510 #define TX_PWR_CFG_6_MCS22_CH0          FIELD32(0x000f0000)
1511 #define TX_PWR_CFG_6_MCS22_CH1          FIELD32(0x00f00000)
1512 #define TX_PWR_CFG_6_MCS22_CH2          FIELD32(0x0f000000)
1513
1514 /* TX_PWR_CFG_0_EXT */
1515 #define TX_PWR_CFG_0_EXT                0x1390
1516 #define TX_PWR_CFG_0_EXT_CCK1_CH2       FIELD32(0x0000000f)
1517 #define TX_PWR_CFG_0_EXT_CCK5_CH2       FIELD32(0x00000f00)
1518 #define TX_PWR_CFG_0_EXT_OFDM6_CH2      FIELD32(0x000f0000)
1519 #define TX_PWR_CFG_0_EXT_OFDM12_CH2     FIELD32(0x0f000000)
1520
1521 /* TX_PWR_CFG_1_EXT */
1522 #define TX_PWR_CFG_1_EXT                0x1394
1523 #define TX_PWR_CFG_1_EXT_OFDM24_CH2     FIELD32(0x0000000f)
1524 #define TX_PWR_CFG_1_EXT_OFDM48_CH2     FIELD32(0x00000f00)
1525 #define TX_PWR_CFG_1_EXT_MCS0_CH2       FIELD32(0x000f0000)
1526 #define TX_PWR_CFG_1_EXT_MCS2_CH2       FIELD32(0x0f000000)
1527
1528 /* TX_PWR_CFG_2_EXT */
1529 #define TX_PWR_CFG_2_EXT                0x1398
1530 #define TX_PWR_CFG_2_EXT_MCS4_CH2       FIELD32(0x0000000f)
1531 #define TX_PWR_CFG_2_EXT_MCS6_CH2       FIELD32(0x00000f00)
1532 #define TX_PWR_CFG_2_EXT_MCS8_CH2       FIELD32(0x000f0000)
1533 #define TX_PWR_CFG_2_EXT_MCS10_CH2      FIELD32(0x0f000000)
1534
1535 /* TX_PWR_CFG_3_EXT */
1536 #define TX_PWR_CFG_3_EXT                0x139c
1537 #define TX_PWR_CFG_3_EXT_MCS12_CH2      FIELD32(0x0000000f)
1538 #define TX_PWR_CFG_3_EXT_MCS14_CH2      FIELD32(0x00000f00)
1539 #define TX_PWR_CFG_3_EXT_STBC0_CH2      FIELD32(0x000f0000)
1540 #define TX_PWR_CFG_3_EXT_STBC2_CH2      FIELD32(0x0f000000)
1541
1542 /* TX_PWR_CFG_4_EXT */
1543 #define TX_PWR_CFG_4_EXT                0x13a0
1544 #define TX_PWR_CFG_4_EXT_STBC4_CH2      FIELD32(0x0000000f)
1545 #define TX_PWR_CFG_4_EXT_STBC6_CH2      FIELD32(0x00000f00)
1546
1547 /* TX_PWR_CFG_7 */
1548 #define TX_PWR_CFG_7                    0x13d4
1549 #define TX_PWR_CFG_7_OFDM54_CH0         FIELD32(0x0000000f)
1550 #define TX_PWR_CFG_7_OFDM54_CH1         FIELD32(0x000000f0)
1551 #define TX_PWR_CFG_7_OFDM54_CH2         FIELD32(0x00000f00)
1552 #define TX_PWR_CFG_7_MCS7_CH0           FIELD32(0x000f0000)
1553 #define TX_PWR_CFG_7_MCS7_CH1           FIELD32(0x00f00000)
1554 #define TX_PWR_CFG_7_MCS7_CH2           FIELD32(0x0f000000)
1555
1556 /* TX_PWR_CFG_8 */
1557 #define TX_PWR_CFG_8                    0x13d8
1558 #define TX_PWR_CFG_8_MCS15_CH0          FIELD32(0x0000000f)
1559 #define TX_PWR_CFG_8_MCS15_CH1          FIELD32(0x000000f0)
1560 #define TX_PWR_CFG_8_MCS15_CH2          FIELD32(0x00000f00)
1561 #define TX_PWR_CFG_8_MCS23_CH0          FIELD32(0x000f0000)
1562 #define TX_PWR_CFG_8_MCS23_CH1          FIELD32(0x00f00000)
1563 #define TX_PWR_CFG_8_MCS23_CH2          FIELD32(0x0f000000)
1564
1565 /* TX_PWR_CFG_9 */
1566 #define TX_PWR_CFG_9                    0x13dc
1567 #define TX_PWR_CFG_9_STBC7_CH0          FIELD32(0x0000000f)
1568 #define TX_PWR_CFG_9_STBC7_CH1          FIELD32(0x000000f0)
1569 #define TX_PWR_CFG_9_STBC7_CH2          FIELD32(0x00000f00)
1570
1571 /*
1572  * RX_FILTER_CFG: RX configuration register.
1573  */
1574 #define RX_FILTER_CFG                   0x1400
1575 #define RX_FILTER_CFG_DROP_CRC_ERROR    FIELD32(0x00000001)
1576 #define RX_FILTER_CFG_DROP_PHY_ERROR    FIELD32(0x00000002)
1577 #define RX_FILTER_CFG_DROP_NOT_TO_ME    FIELD32(0x00000004)
1578 #define RX_FILTER_CFG_DROP_NOT_MY_BSSD  FIELD32(0x00000008)
1579 #define RX_FILTER_CFG_DROP_VER_ERROR    FIELD32(0x00000010)
1580 #define RX_FILTER_CFG_DROP_MULTICAST    FIELD32(0x00000020)
1581 #define RX_FILTER_CFG_DROP_BROADCAST    FIELD32(0x00000040)
1582 #define RX_FILTER_CFG_DROP_DUPLICATE    FIELD32(0x00000080)
1583 #define RX_FILTER_CFG_DROP_CF_END_ACK   FIELD32(0x00000100)
1584 #define RX_FILTER_CFG_DROP_CF_END       FIELD32(0x00000200)
1585 #define RX_FILTER_CFG_DROP_ACK          FIELD32(0x00000400)
1586 #define RX_FILTER_CFG_DROP_CTS          FIELD32(0x00000800)
1587 #define RX_FILTER_CFG_DROP_RTS          FIELD32(0x00001000)
1588 #define RX_FILTER_CFG_DROP_PSPOLL       FIELD32(0x00002000)
1589 #define RX_FILTER_CFG_DROP_BA           FIELD32(0x00004000)
1590 #define RX_FILTER_CFG_DROP_BAR          FIELD32(0x00008000)
1591 #define RX_FILTER_CFG_DROP_CNTL         FIELD32(0x00010000)
1592
1593 /*
1594  * AUTO_RSP_CFG:
1595  * AUTORESPONDER: 0: disable, 1: enable
1596  * BAC_ACK_POLICY: 0:long, 1:short preamble
1597  * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1598  * CTS_40_MREF: Response CTS 40MHz duplicate mode
1599  * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1600  * DUAL_CTS_EN: Power bit value in control frame
1601  * ACK_CTS_PSM_BIT:Power bit value in control frame
1602  */
1603 #define AUTO_RSP_CFG                    0x1404
1604 #define AUTO_RSP_CFG_AUTORESPONDER      FIELD32(0x00000001)
1605 #define AUTO_RSP_CFG_BAC_ACK_POLICY     FIELD32(0x00000002)
1606 #define AUTO_RSP_CFG_CTS_40_MMODE       FIELD32(0x00000004)
1607 #define AUTO_RSP_CFG_CTS_40_MREF        FIELD32(0x00000008)
1608 #define AUTO_RSP_CFG_AR_PREAMBLE        FIELD32(0x00000010)
1609 #define AUTO_RSP_CFG_DUAL_CTS_EN        FIELD32(0x00000040)
1610 #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT    FIELD32(0x00000080)
1611
1612 /*
1613  * LEGACY_BASIC_RATE:
1614  */
1615 #define LEGACY_BASIC_RATE               0x1408
1616
1617 /*
1618  * HT_BASIC_RATE:
1619  */
1620 #define HT_BASIC_RATE                   0x140c
1621
1622 /*
1623  * HT_CTRL_CFG:
1624  */
1625 #define HT_CTRL_CFG                     0x1410
1626
1627 /*
1628  * SIFS_COST_CFG:
1629  */
1630 #define SIFS_COST_CFG                   0x1414
1631
1632 /*
1633  * RX_PARSER_CFG:
1634  * Set NAV for all received frames
1635  */
1636 #define RX_PARSER_CFG                   0x1418
1637
1638 /*
1639  * TX_SEC_CNT0:
1640  */
1641 #define TX_SEC_CNT0                     0x1500
1642
1643 /*
1644  * RX_SEC_CNT0:
1645  */
1646 #define RX_SEC_CNT0                     0x1504
1647
1648 /*
1649  * CCMP_FC_MUTE:
1650  */
1651 #define CCMP_FC_MUTE                    0x1508
1652
1653 /*
1654  * TXOP_HLDR_ADDR0:
1655  */
1656 #define TXOP_HLDR_ADDR0                 0x1600
1657
1658 /*
1659  * TXOP_HLDR_ADDR1:
1660  */
1661 #define TXOP_HLDR_ADDR1                 0x1604
1662
1663 /*
1664  * TXOP_HLDR_ET:
1665  */
1666 #define TXOP_HLDR_ET                    0x1608
1667
1668 /*
1669  * QOS_CFPOLL_RA_DW0:
1670  */
1671 #define QOS_CFPOLL_RA_DW0               0x160c
1672
1673 /*
1674  * QOS_CFPOLL_RA_DW1:
1675  */
1676 #define QOS_CFPOLL_RA_DW1               0x1610
1677
1678 /*
1679  * QOS_CFPOLL_QC:
1680  */
1681 #define QOS_CFPOLL_QC                   0x1614
1682
1683 /*
1684  * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1685  */
1686 #define RX_STA_CNT0                     0x1700
1687 #define RX_STA_CNT0_CRC_ERR             FIELD32(0x0000ffff)
1688 #define RX_STA_CNT0_PHY_ERR             FIELD32(0xffff0000)
1689
1690 /*
1691  * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1692  */
1693 #define RX_STA_CNT1                     0x1704
1694 #define RX_STA_CNT1_FALSE_CCA           FIELD32(0x0000ffff)
1695 #define RX_STA_CNT1_PLCP_ERR            FIELD32(0xffff0000)
1696
1697 /*
1698  * RX_STA_CNT2:
1699  */
1700 #define RX_STA_CNT2                     0x1708
1701 #define RX_STA_CNT2_RX_DUPLI_COUNT      FIELD32(0x0000ffff)
1702 #define RX_STA_CNT2_RX_FIFO_OVERFLOW    FIELD32(0xffff0000)
1703
1704 /*
1705  * TX_STA_CNT0: TX Beacon count
1706  */
1707 #define TX_STA_CNT0                     0x170c
1708 #define TX_STA_CNT0_TX_FAIL_COUNT       FIELD32(0x0000ffff)
1709 #define TX_STA_CNT0_TX_BEACON_COUNT     FIELD32(0xffff0000)
1710
1711 /*
1712  * TX_STA_CNT1: TX tx count
1713  */
1714 #define TX_STA_CNT1                     0x1710
1715 #define TX_STA_CNT1_TX_SUCCESS          FIELD32(0x0000ffff)
1716 #define TX_STA_CNT1_TX_RETRANSMIT       FIELD32(0xffff0000)
1717
1718 /*
1719  * TX_STA_CNT2: TX tx count
1720  */
1721 #define TX_STA_CNT2                     0x1714
1722 #define TX_STA_CNT2_TX_ZERO_LEN_COUNT   FIELD32(0x0000ffff)
1723 #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1724
1725 /*
1726  * TX_STA_FIFO: TX Result for specific PID status fifo register.
1727  *
1728  * This register is implemented as FIFO with 16 entries in the HW. Each
1729  * register read fetches the next tx result. If the FIFO is full because
1730  * it wasn't read fast enough after the according interrupt (TX_FIFO_STATUS)
1731  * triggered, the hw seems to simply drop further tx results.
1732  *
1733  * VALID: 1: this tx result is valid
1734  *        0: no valid tx result -> driver should stop reading
1735  * PID_TYPE: The PID latched from the PID field in the TXWI, can be used
1736  *           to match a frame with its tx result (even though the PID is
1737  *           only 4 bits wide).
1738  * PID_QUEUE: Part of PID_TYPE, this is the queue index number (0-3)
1739  * PID_ENTRY: Part of PID_TYPE, this is the queue entry index number (1-3)
1740  *            This identification number is calculated by ((idx % 3) + 1).
1741  * TX_SUCCESS: Indicates tx success (1) or failure (0)
1742  * TX_AGGRE: Indicates if the frame was part of an aggregate (1) or not (0)
1743  * TX_ACK_REQUIRED: Indicates if the frame needed to get ack'ed (1) or not (0)
1744  * WCID: The wireless client ID.
1745  * MCS: The tx rate used during the last transmission of this frame, be it
1746  *      successful or not.
1747  * PHYMODE: The phymode used for the transmission.
1748  */
1749 #define TX_STA_FIFO                     0x1718
1750 #define TX_STA_FIFO_VALID               FIELD32(0x00000001)
1751 #define TX_STA_FIFO_PID_TYPE            FIELD32(0x0000001e)
1752 #define TX_STA_FIFO_PID_QUEUE           FIELD32(0x00000006)
1753 #define TX_STA_FIFO_PID_ENTRY           FIELD32(0x00000018)
1754 #define TX_STA_FIFO_TX_SUCCESS          FIELD32(0x00000020)
1755 #define TX_STA_FIFO_TX_AGGRE            FIELD32(0x00000040)
1756 #define TX_STA_FIFO_TX_ACK_REQUIRED     FIELD32(0x00000080)
1757 #define TX_STA_FIFO_WCID                FIELD32(0x0000ff00)
1758 #define TX_STA_FIFO_SUCCESS_RATE        FIELD32(0xffff0000)
1759 #define TX_STA_FIFO_MCS                 FIELD32(0x007f0000)
1760 #define TX_STA_FIFO_PHYMODE             FIELD32(0xc0000000)
1761
1762 /*
1763  * TX_AGG_CNT: Debug counter
1764  */
1765 #define TX_AGG_CNT                      0x171c
1766 #define TX_AGG_CNT_NON_AGG_TX_COUNT     FIELD32(0x0000ffff)
1767 #define TX_AGG_CNT_AGG_TX_COUNT         FIELD32(0xffff0000)
1768
1769 /*
1770  * TX_AGG_CNT0:
1771  */
1772 #define TX_AGG_CNT0                     0x1720
1773 #define TX_AGG_CNT0_AGG_SIZE_1_COUNT    FIELD32(0x0000ffff)
1774 #define TX_AGG_CNT0_AGG_SIZE_2_COUNT    FIELD32(0xffff0000)
1775
1776 /*
1777  * TX_AGG_CNT1:
1778  */
1779 #define TX_AGG_CNT1                     0x1724
1780 #define TX_AGG_CNT1_AGG_SIZE_3_COUNT    FIELD32(0x0000ffff)
1781 #define TX_AGG_CNT1_AGG_SIZE_4_COUNT    FIELD32(0xffff0000)
1782
1783 /*
1784  * TX_AGG_CNT2:
1785  */
1786 #define TX_AGG_CNT2                     0x1728
1787 #define TX_AGG_CNT2_AGG_SIZE_5_COUNT    FIELD32(0x0000ffff)
1788 #define TX_AGG_CNT2_AGG_SIZE_6_COUNT    FIELD32(0xffff0000)
1789
1790 /*
1791  * TX_AGG_CNT3:
1792  */
1793 #define TX_AGG_CNT3                     0x172c
1794 #define TX_AGG_CNT3_AGG_SIZE_7_COUNT    FIELD32(0x0000ffff)
1795 #define TX_AGG_CNT3_AGG_SIZE_8_COUNT    FIELD32(0xffff0000)
1796
1797 /*
1798  * TX_AGG_CNT4:
1799  */
1800 #define TX_AGG_CNT4                     0x1730
1801 #define TX_AGG_CNT4_AGG_SIZE_9_COUNT    FIELD32(0x0000ffff)
1802 #define TX_AGG_CNT4_AGG_SIZE_10_COUNT   FIELD32(0xffff0000)
1803
1804 /*
1805  * TX_AGG_CNT5:
1806  */
1807 #define TX_AGG_CNT5                     0x1734
1808 #define TX_AGG_CNT5_AGG_SIZE_11_COUNT   FIELD32(0x0000ffff)
1809 #define TX_AGG_CNT5_AGG_SIZE_12_COUNT   FIELD32(0xffff0000)
1810
1811 /*
1812  * TX_AGG_CNT6:
1813  */
1814 #define TX_AGG_CNT6                     0x1738
1815 #define TX_AGG_CNT6_AGG_SIZE_13_COUNT   FIELD32(0x0000ffff)
1816 #define TX_AGG_CNT6_AGG_SIZE_14_COUNT   FIELD32(0xffff0000)
1817
1818 /*
1819  * TX_AGG_CNT7:
1820  */
1821 #define TX_AGG_CNT7                     0x173c
1822 #define TX_AGG_CNT7_AGG_SIZE_15_COUNT   FIELD32(0x0000ffff)
1823 #define TX_AGG_CNT7_AGG_SIZE_16_COUNT   FIELD32(0xffff0000)
1824
1825 /*
1826  * MPDU_DENSITY_CNT:
1827  * TX_ZERO_DEL: TX zero length delimiter count
1828  * RX_ZERO_DEL: RX zero length delimiter count
1829  */
1830 #define MPDU_DENSITY_CNT                0x1740
1831 #define MPDU_DENSITY_CNT_TX_ZERO_DEL    FIELD32(0x0000ffff)
1832 #define MPDU_DENSITY_CNT_RX_ZERO_DEL    FIELD32(0xffff0000)
1833
1834 /*
1835  * Security key table memory.
1836  *
1837  * The pairwise key table shares some memory with the beacon frame
1838  * buffers 6 and 7. That basically means that when beacon 6 & 7
1839  * are used we should only use the reduced pairwise key table which
1840  * has a maximum of 222 entries.
1841  *
1842  * ---------------------------------------------
1843  * |0x4000 | Pairwise Key   | Reduced Pairwise |
1844  * |       | Table          | Key Table        |
1845  * |       | Size: 256 * 32 | Size: 222 * 32   |
1846  * |0x5BC0 |                |-------------------
1847  * |       |                | Beacon 6         |
1848  * |0x5DC0 |                |-------------------
1849  * |       |                | Beacon 7         |
1850  * |0x5FC0 |                |-------------------
1851  * |0x5FFF |                |
1852  * --------------------------
1853  *
1854  * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1855  * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1856  * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
1857  * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
1858  * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
1859  * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
1860  */
1861 #define MAC_WCID_BASE                   0x1800
1862 #define PAIRWISE_KEY_TABLE_BASE         0x4000
1863 #define MAC_IVEIV_TABLE_BASE            0x6000
1864 #define MAC_WCID_ATTRIBUTE_BASE         0x6800
1865 #define SHARED_KEY_TABLE_BASE           0x6c00
1866 #define SHARED_KEY_MODE_BASE            0x7000
1867
1868 #define MAC_WCID_ENTRY(__idx) \
1869         (MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)))
1870 #define PAIRWISE_KEY_ENTRY(__idx) \
1871         (PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
1872 #define MAC_IVEIV_ENTRY(__idx) \
1873         (MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)))
1874 #define MAC_WCID_ATTR_ENTRY(__idx) \
1875         (MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)))
1876 #define SHARED_KEY_ENTRY(__idx) \
1877         (SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
1878 #define SHARED_KEY_MODE_ENTRY(__idx) \
1879         (SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)))
1880
1881 struct mac_wcid_entry {
1882         u8 mac[6];
1883         u8 reserved[2];
1884 } __packed;
1885
1886 struct hw_key_entry {
1887         u8 key[16];
1888         u8 tx_mic[8];
1889         u8 rx_mic[8];
1890 } __packed;
1891
1892 struct mac_iveiv_entry {
1893         u8 iv[8];
1894 } __packed;
1895
1896 /*
1897  * MAC_WCID_ATTRIBUTE:
1898  */
1899 #define MAC_WCID_ATTRIBUTE_KEYTAB       FIELD32(0x00000001)
1900 #define MAC_WCID_ATTRIBUTE_CIPHER       FIELD32(0x0000000e)
1901 #define MAC_WCID_ATTRIBUTE_BSS_IDX      FIELD32(0x00000070)
1902 #define MAC_WCID_ATTRIBUTE_RX_WIUDF     FIELD32(0x00000380)
1903 #define MAC_WCID_ATTRIBUTE_CIPHER_EXT   FIELD32(0x00000400)
1904 #define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT  FIELD32(0x00000800)
1905 #define MAC_WCID_ATTRIBUTE_WAPI_MCBC    FIELD32(0x00008000)
1906 #define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000)
1907
1908 /*
1909  * SHARED_KEY_MODE:
1910  */
1911 #define SHARED_KEY_MODE_BSS0_KEY0       FIELD32(0x00000007)
1912 #define SHARED_KEY_MODE_BSS0_KEY1       FIELD32(0x00000070)
1913 #define SHARED_KEY_MODE_BSS0_KEY2       FIELD32(0x00000700)
1914 #define SHARED_KEY_MODE_BSS0_KEY3       FIELD32(0x00007000)
1915 #define SHARED_KEY_MODE_BSS1_KEY0       FIELD32(0x00070000)
1916 #define SHARED_KEY_MODE_BSS1_KEY1       FIELD32(0x00700000)
1917 #define SHARED_KEY_MODE_BSS1_KEY2       FIELD32(0x07000000)
1918 #define SHARED_KEY_MODE_BSS1_KEY3       FIELD32(0x70000000)
1919
1920 /*
1921  * HOST-MCU communication
1922  */
1923
1924 /*
1925  * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
1926  * CMD_TOKEN: Command id, 0xff disable status reporting.
1927  */
1928 #define H2M_MAILBOX_CSR                 0x7010
1929 #define H2M_MAILBOX_CSR_ARG0            FIELD32(0x000000ff)
1930 #define H2M_MAILBOX_CSR_ARG1            FIELD32(0x0000ff00)
1931 #define H2M_MAILBOX_CSR_CMD_TOKEN       FIELD32(0x00ff0000)
1932 #define H2M_MAILBOX_CSR_OWNER           FIELD32(0xff000000)
1933
1934 /*
1935  * H2M_MAILBOX_CID:
1936  * Free slots contain 0xff. MCU will store command's token to lowest free slot.
1937  * If all slots are occupied status will be dropped.
1938  */
1939 #define H2M_MAILBOX_CID                 0x7014
1940 #define H2M_MAILBOX_CID_CMD0            FIELD32(0x000000ff)
1941 #define H2M_MAILBOX_CID_CMD1            FIELD32(0x0000ff00)
1942 #define H2M_MAILBOX_CID_CMD2            FIELD32(0x00ff0000)
1943 #define H2M_MAILBOX_CID_CMD3            FIELD32(0xff000000)
1944
1945 /*
1946  * H2M_MAILBOX_STATUS:
1947  * Command status will be saved to same slot as command id.
1948  */
1949 #define H2M_MAILBOX_STATUS              0x701c
1950
1951 /*
1952  * H2M_INT_SRC:
1953  */
1954 #define H2M_INT_SRC                     0x7024
1955
1956 /*
1957  * H2M_BBP_AGENT:
1958  */
1959 #define H2M_BBP_AGENT                   0x7028
1960
1961 /*
1962  * MCU_LEDCS: LED control for MCU Mailbox.
1963  */
1964 #define MCU_LEDCS_LED_MODE              FIELD8(0x1f)
1965 #define MCU_LEDCS_POLARITY              FIELD8(0x01)
1966
1967 /*
1968  * HW_CS_CTS_BASE:
1969  * Carrier-sense CTS frame base address.
1970  * It's where mac stores carrier-sense frame for carrier-sense function.
1971  */
1972 #define HW_CS_CTS_BASE                  0x7700
1973
1974 /*
1975  * HW_DFS_CTS_BASE:
1976  * DFS CTS frame base address. It's where mac stores CTS frame for DFS.
1977  */
1978 #define HW_DFS_CTS_BASE                 0x7780
1979
1980 /*
1981  * TXRX control registers - base address 0x3000
1982  */
1983
1984 /*
1985  * TXRX_CSR1:
1986  * rt2860b  UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1987  */
1988 #define TXRX_CSR1                       0x77d0
1989
1990 /*
1991  * HW_DEBUG_SETTING_BASE:
1992  * since NULL frame won't be that long (256 byte)
1993  * We steal 16 tail bytes to save debugging settings
1994  */
1995 #define HW_DEBUG_SETTING_BASE           0x77f0
1996 #define HW_DEBUG_SETTING_BASE2          0x7770
1997
1998 /*
1999  * HW_BEACON_BASE
2000  * In order to support maximum 8 MBSS and its maximum length
2001  * is 512 bytes for each beacon
2002  * Three section discontinue memory segments will be used.
2003  * 1. The original region for BCN 0~3
2004  * 2. Extract memory from FCE table for BCN 4~5
2005  * 3. Extract memory from Pair-wise key table for BCN 6~7
2006  *    It occupied those memory of wcid 238~253 for BCN 6
2007  *    and wcid 222~237 for BCN 7 (see Security key table memory
2008  *    for more info).
2009  *
2010  * IMPORTANT NOTE: Not sure why legacy driver does this,
2011  * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
2012  */
2013 #define HW_BEACON_BASE0                 0x7800
2014 #define HW_BEACON_BASE1                 0x7a00
2015 #define HW_BEACON_BASE2                 0x7c00
2016 #define HW_BEACON_BASE3                 0x7e00
2017 #define HW_BEACON_BASE4                 0x7200
2018 #define HW_BEACON_BASE5                 0x7400
2019 #define HW_BEACON_BASE6                 0x5dc0
2020 #define HW_BEACON_BASE7                 0x5bc0
2021
2022 #define HW_BEACON_BASE(__index) \
2023         (((__index) < 4) ? (HW_BEACON_BASE0 + (__index * 0x0200)) : \
2024           (((__index) < 6) ? (HW_BEACON_BASE4 + ((__index - 4) * 0x0200)) : \
2025           (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))))
2026
2027 #define BEACON_BASE_TO_OFFSET(_base)    (((_base) - 0x4000) / 64)
2028
2029 /*
2030  * BBP registers.
2031  * The wordsize of the BBP is 8 bits.
2032  */
2033
2034 /*
2035  * BBP 1: TX Antenna & Power Control
2036  * POWER_CTRL:
2037  * 0 - normal,
2038  * 1 - drop tx power by 6dBm,
2039  * 2 - drop tx power by 12dBm,
2040  * 3 - increase tx power by 6dBm
2041  */
2042 #define BBP1_TX_POWER_CTRL              FIELD8(0x07)
2043 #define BBP1_TX_ANTENNA                 FIELD8(0x18)
2044
2045 /*
2046  * BBP 3: RX Antenna
2047  */
2048 #define BBP3_RX_ADC                     FIELD8(0x03)
2049 #define BBP3_RX_ANTENNA                 FIELD8(0x18)
2050 #define BBP3_HT40_MINUS                 FIELD8(0x20)
2051 #define BBP3_ADC_MODE_SWITCH            FIELD8(0x40)
2052 #define BBP3_ADC_INIT_MODE              FIELD8(0x80)
2053
2054 /*
2055  * BBP 4: Bandwidth
2056  */
2057 #define BBP4_TX_BF                      FIELD8(0x01)
2058 #define BBP4_BANDWIDTH                  FIELD8(0x18)
2059 #define BBP4_MAC_IF_CTRL                FIELD8(0x40)
2060
2061 /* BBP27 */
2062 #define BBP27_RX_CHAIN_SEL              FIELD8(0x60)
2063
2064 /*
2065  * BBP 47: Bandwidth
2066  */
2067 #define BBP47_TSSI_REPORT_SEL           FIELD8(0x03)
2068 #define BBP47_TSSI_UPDATE_REQ           FIELD8(0x04)
2069 #define BBP47_TSSI_TSSI_MODE            FIELD8(0x18)
2070 #define BBP47_TSSI_ADC6                 FIELD8(0x80)
2071
2072 /*
2073  * BBP 49
2074  */
2075 #define BBP49_UPDATE_FLAG               FIELD8(0x01)
2076
2077 /*
2078  * BBP 105:
2079  * - bit0: detect SIG on primary channel only (on 40MHz bandwidth)
2080  * - bit1: FEQ (Feed Forward Compensation) for independend streams
2081  * - bit2: MLD (Maximum Likehood Detection) for 2 streams (reserved on single
2082  *         stream)
2083  * - bit4: channel estimation updates based on remodulation of
2084  *         L-SIG and HT-SIG symbols
2085  */
2086 #define BBP105_DETECT_SIG_ON_PRIMARY    FIELD8(0x01)
2087 #define BBP105_FEQ                      FIELD8(0x02)
2088 #define BBP105_MLD                      FIELD8(0x04)
2089 #define BBP105_SIG_REMODULATION         FIELD8(0x08)
2090
2091 /*
2092  * BBP 109
2093  */
2094 #define BBP109_TX0_POWER                FIELD8(0x0f)
2095 #define BBP109_TX1_POWER                FIELD8(0xf0)
2096
2097 /* BBP 110 */
2098 #define BBP110_TX2_POWER                FIELD8(0x0f)
2099
2100
2101 /*
2102  * BBP 138: Unknown
2103  */
2104 #define BBP138_RX_ADC1                  FIELD8(0x02)
2105 #define BBP138_RX_ADC2                  FIELD8(0x04)
2106 #define BBP138_TX_DAC1                  FIELD8(0x20)
2107 #define BBP138_TX_DAC2                  FIELD8(0x40)
2108
2109 /*
2110  * BBP 152: Rx Ant
2111  */
2112 #define BBP152_RX_DEFAULT_ANT           FIELD8(0x80)
2113
2114 /*
2115  * BBP 254: unknown
2116  */
2117 #define BBP254_BIT7                     FIELD8(0x80)
2118
2119 /*
2120  * RFCSR registers
2121  * The wordsize of the RFCSR is 8 bits.
2122  */
2123
2124 /*
2125  * RFCSR 1:
2126  */
2127 #define RFCSR1_RF_BLOCK_EN              FIELD8(0x01)
2128 #define RFCSR1_PLL_PD                   FIELD8(0x02)
2129 #define RFCSR1_RX0_PD                   FIELD8(0x04)
2130 #define RFCSR1_TX0_PD                   FIELD8(0x08)
2131 #define RFCSR1_RX1_PD                   FIELD8(0x10)
2132 #define RFCSR1_TX1_PD                   FIELD8(0x20)
2133 #define RFCSR1_RX2_PD                   FIELD8(0x40)
2134 #define RFCSR1_TX2_PD                   FIELD8(0x80)
2135
2136 /*
2137  * RFCSR 2:
2138  */
2139 #define RFCSR2_RESCAL_EN                FIELD8(0x80)
2140
2141 /*
2142  * RFCSR 3:
2143  */
2144 #define RFCSR3_K                        FIELD8(0x0f)
2145 /* Bits [7-4] for RF3320 (RT3370/RT3390), on other chipsets reserved */
2146 #define RFCSR3_PA1_BIAS_CCK             FIELD8(0x70)
2147 #define RFCSR3_PA2_CASCODE_BIAS_CCKK    FIELD8(0x80)
2148 /* Bits for RF3290/RF5360/RF5370/RF5372/RF5390/RF5392 */
2149 #define RFCSR3_VCOCAL_EN                FIELD8(0x80)
2150 /* Bits for RF3050 */
2151 #define RFCSR3_BIT1                     FIELD8(0x02)
2152 #define RFCSR3_BIT2                     FIELD8(0x04)
2153 #define RFCSR3_BIT3                     FIELD8(0x08)
2154 #define RFCSR3_BIT4                     FIELD8(0x10)
2155 #define RFCSR3_BIT5                     FIELD8(0x20)
2156
2157 /*
2158  * FRCSR 5:
2159  */
2160 #define RFCSR5_R1                       FIELD8(0x0c)
2161
2162 /*
2163  * RFCSR 6:
2164  */
2165 #define RFCSR6_R1                       FIELD8(0x03)
2166 #define RFCSR6_R2                       FIELD8(0x40)
2167 #define RFCSR6_TXDIV            FIELD8(0x0c)
2168 /* bits for RF3053 */
2169 #define RFCSR6_VCO_IC                   FIELD8(0xc0)
2170
2171 /*
2172  * RFCSR 7:
2173  */
2174 #define RFCSR7_RF_TUNING                FIELD8(0x01)
2175 #define RFCSR7_BIT1                     FIELD8(0x02)
2176 #define RFCSR7_BIT2                     FIELD8(0x04)
2177 #define RFCSR7_BIT3                     FIELD8(0x08)
2178 #define RFCSR7_BIT4                     FIELD8(0x10)
2179 #define RFCSR7_BIT5                     FIELD8(0x20)
2180 #define RFCSR7_BITS67                   FIELD8(0xc0)
2181
2182 /*
2183  * RFCSR 9:
2184  */
2185 #define RFCSR9_K                        FIELD8(0x0f)
2186 #define RFCSR9_N                        FIELD8(0x10)
2187 #define RFCSR9_UNKNOWN                  FIELD8(0x60)
2188 #define RFCSR9_MOD                      FIELD8(0x80)
2189
2190 /*
2191  * RFCSR 11:
2192  */
2193 #define RFCSR11_R                       FIELD8(0x03)
2194 #define RFCSR11_PLL_MOD                 FIELD8(0x0c)
2195 #define RFCSR11_MOD                     FIELD8(0xc0)
2196 /* bits for RF3053 */
2197 /* TODO: verify RFCSR11_MOD usage on other chips */
2198 #define RFCSR11_PLL_IDOH                FIELD8(0x40)
2199
2200
2201 /*
2202  * RFCSR 12:
2203  */
2204 #define RFCSR12_TX_POWER                FIELD8(0x1f)
2205 #define RFCSR12_DR0                             FIELD8(0xe0)
2206
2207 /*
2208  * RFCSR 13:
2209  */
2210 #define RFCSR13_TX_POWER                FIELD8(0x1f)
2211 #define RFCSR13_DR0                             FIELD8(0xe0)
2212
2213 /*
2214  * RFCSR 15:
2215  */
2216 #define RFCSR15_TX_LO2_EN               FIELD8(0x08)
2217
2218 /*
2219  * RFCSR 16:
2220  */
2221 #define RFCSR16_TXMIXER_GAIN            FIELD8(0x07)
2222
2223 /*
2224  * RFCSR 17:
2225  */
2226 #define RFCSR17_TXMIXER_GAIN            FIELD8(0x07)
2227 #define RFCSR17_TX_LO1_EN               FIELD8(0x08)
2228 #define RFCSR17_R                       FIELD8(0x20)
2229 #define RFCSR17_CODE                   FIELD8(0x7f)
2230
2231 /* RFCSR 18 */
2232 #define RFCSR18_XO_TUNE_BYPASS          FIELD8(0x40)
2233
2234
2235 /*
2236  * RFCSR 20:
2237  */
2238 #define RFCSR20_RX_LO1_EN               FIELD8(0x08)
2239
2240 /*
2241  * RFCSR 21:
2242  */
2243 #define RFCSR21_RX_LO2_EN               FIELD8(0x08)
2244
2245 /*
2246  * RFCSR 22:
2247  */
2248 #define RFCSR22_BASEBAND_LOOPBACK       FIELD8(0x01)
2249
2250 /*
2251  * RFCSR 23:
2252  */
2253 #define RFCSR23_FREQ_OFFSET             FIELD8(0x7f)
2254
2255 /*
2256  * RFCSR 24:
2257  */
2258 #define RFCSR24_TX_AGC_FC               FIELD8(0x1f)
2259 #define RFCSR24_TX_H20M                 FIELD8(0x20)
2260 #define RFCSR24_TX_CALIB                FIELD8(0x7f)
2261
2262 /*
2263  * RFCSR 27:
2264  */
2265 #define RFCSR27_R1                      FIELD8(0x03)
2266 #define RFCSR27_R2                      FIELD8(0x04)
2267 #define RFCSR27_R3                      FIELD8(0x30)
2268 #define RFCSR27_R4                      FIELD8(0x40)
2269
2270 /*
2271  * RFCSR 29:
2272  */
2273 #define RFCSR29_ADC6_TEST               FIELD8(0x01)
2274 #define RFCSR29_ADC6_INT_TEST           FIELD8(0x02)
2275 #define RFCSR29_RSSI_RESET              FIELD8(0x04)
2276 #define RFCSR29_RSSI_ON                 FIELD8(0x08)
2277 #define RFCSR29_RSSI_RIP_CTRL           FIELD8(0x30)
2278 #define RFCSR29_RSSI_GAIN               FIELD8(0xc0)
2279
2280 /*
2281  * RFCSR 30:
2282  */
2283 #define RFCSR30_TX_H20M                 FIELD8(0x02)
2284 #define RFCSR30_RX_H20M                 FIELD8(0x04)
2285 #define RFCSR30_RX_VCM                  FIELD8(0x18)
2286 #define RFCSR30_RF_CALIBRATION          FIELD8(0x80)
2287
2288 /*
2289  * RFCSR 31:
2290  */
2291 #define RFCSR31_RX_AGC_FC               FIELD8(0x1f)
2292 #define RFCSR31_RX_H20M                 FIELD8(0x20)
2293 #define RFCSR31_RX_CALIB                FIELD8(0x7f)
2294
2295 /* RFCSR 32 bits for RF3053 */
2296 #define RFCSR32_TX_AGC_FC               FIELD8(0xf8)
2297
2298 /* RFCSR 36 bits for RF3053 */
2299 #define RFCSR36_RF_BS                   FIELD8(0x80)
2300
2301 /*
2302  * RFCSR 38:
2303  */
2304 #define RFCSR38_RX_LO1_EN               FIELD8(0x20)
2305
2306 /*
2307  * RFCSR 39:
2308  */
2309 #define RFCSR39_RX_DIV                  FIELD8(0x40)
2310 #define RFCSR39_RX_LO2_EN               FIELD8(0x80)
2311
2312 /*
2313  * RFCSR 49:
2314  */
2315 #define RFCSR49_TX                      FIELD8(0x3f)
2316 #define RFCSR49_EP                      FIELD8(0xc0)
2317 /* bits for RT3593 */
2318 #define RFCSR49_TX_LO1_IC               FIELD8(0x1c)
2319 #define RFCSR49_TX_DIV                  FIELD8(0x20)
2320
2321 /*
2322  * RFCSR 50:
2323  */
2324 #define RFCSR50_TX                      FIELD8(0x3f)
2325 #define RFCSR50_EP                      FIELD8(0xc0)
2326 /* bits for RT3593 */
2327 #define RFCSR50_TX_LO1_EN               FIELD8(0x20)
2328 #define RFCSR50_TX_LO2_EN               FIELD8(0x10)
2329
2330 /* RFCSR 51 */
2331 /* bits for RT3593 */
2332 #define RFCSR51_BITS01                  FIELD8(0x03)
2333 #define RFCSR51_BITS24                  FIELD8(0x1c)
2334 #define RFCSR51_BITS57                  FIELD8(0xe0)
2335
2336 #define RFCSR53_TX_POWER                FIELD8(0x3f)
2337 #define RFCSR53_UNKNOWN                 FIELD8(0xc0)
2338
2339 #define RFCSR54_TX_POWER                FIELD8(0x3f)
2340 #define RFCSR54_UNKNOWN                 FIELD8(0xc0)
2341
2342 #define RFCSR55_TX_POWER                FIELD8(0x3f)
2343 #define RFCSR55_UNKNOWN                 FIELD8(0xc0)
2344
2345 #define RFCSR57_DRV_CC                  FIELD8(0xfc)
2346
2347
2348 /*
2349  * RF registers
2350  */
2351
2352 /*
2353  * RF 2
2354  */
2355 #define RF2_ANTENNA_RX2                 FIELD32(0x00000040)
2356 #define RF2_ANTENNA_TX1                 FIELD32(0x00004000)
2357 #define RF2_ANTENNA_RX1                 FIELD32(0x00020000)
2358
2359 /*
2360  * RF 3
2361  */
2362 #define RF3_TXPOWER_G                   FIELD32(0x00003e00)
2363 #define RF3_TXPOWER_A_7DBM_BOOST        FIELD32(0x00000200)
2364 #define RF3_TXPOWER_A                   FIELD32(0x00003c00)
2365
2366 /*
2367  * RF 4
2368  */
2369 #define RF4_TXPOWER_G                   FIELD32(0x000007c0)
2370 #define RF4_TXPOWER_A_7DBM_BOOST        FIELD32(0x00000040)
2371 #define RF4_TXPOWER_A                   FIELD32(0x00000780)
2372 #define RF4_FREQ_OFFSET                 FIELD32(0x001f8000)
2373 #define RF4_HT40                        FIELD32(0x00200000)
2374
2375 /*
2376  * EEPROM content.
2377  * The wordsize of the EEPROM is 16 bits.
2378  */
2379
2380 enum rt2800_eeprom_word {
2381         EEPROM_CHIP_ID = 0,
2382         EEPROM_VERSION,
2383         EEPROM_MAC_ADDR_0,
2384         EEPROM_MAC_ADDR_1,
2385         EEPROM_MAC_ADDR_2,
2386         EEPROM_NIC_CONF0,
2387         EEPROM_NIC_CONF1,
2388         EEPROM_FREQ,
2389         EEPROM_LED_AG_CONF,
2390         EEPROM_LED_ACT_CONF,
2391         EEPROM_LED_POLARITY,
2392         EEPROM_NIC_CONF2,
2393         EEPROM_LNA,
2394         EEPROM_RSSI_BG,
2395         EEPROM_RSSI_BG2,
2396         EEPROM_TXMIXER_GAIN_BG,
2397         EEPROM_RSSI_A,
2398         EEPROM_RSSI_A2,
2399         EEPROM_TXMIXER_GAIN_A,
2400         EEPROM_EIRP_MAX_TX_POWER,
2401         EEPROM_TXPOWER_DELTA,
2402         EEPROM_TXPOWER_BG1,
2403         EEPROM_TXPOWER_BG2,
2404         EEPROM_TSSI_BOUND_BG1,
2405         EEPROM_TSSI_BOUND_BG2,
2406         EEPROM_TSSI_BOUND_BG3,
2407         EEPROM_TSSI_BOUND_BG4,
2408         EEPROM_TSSI_BOUND_BG5,
2409         EEPROM_TXPOWER_A1,
2410         EEPROM_TXPOWER_A2,
2411         EEPROM_TSSI_BOUND_A1,
2412         EEPROM_TSSI_BOUND_A2,
2413         EEPROM_TSSI_BOUND_A3,
2414         EEPROM_TSSI_BOUND_A4,
2415         EEPROM_TSSI_BOUND_A5,
2416         EEPROM_TXPOWER_BYRATE,
2417         EEPROM_BBP_START,
2418
2419         /* IDs for extended EEPROM format used by three-chain devices */
2420         EEPROM_EXT_LNA2,
2421         EEPROM_EXT_TXPOWER_BG3,
2422         EEPROM_EXT_TXPOWER_A3,
2423
2424         /* New values must be added before this */
2425         EEPROM_WORD_COUNT
2426 };
2427
2428 /*
2429  * EEPROM Version
2430  */
2431 #define EEPROM_VERSION_FAE              FIELD16(0x00ff)
2432 #define EEPROM_VERSION_VERSION          FIELD16(0xff00)
2433
2434 /*
2435  * HW MAC address.
2436  */
2437 #define EEPROM_MAC_ADDR_BYTE0           FIELD16(0x00ff)
2438 #define EEPROM_MAC_ADDR_BYTE1           FIELD16(0xff00)
2439 #define EEPROM_MAC_ADDR_BYTE2           FIELD16(0x00ff)
2440 #define EEPROM_MAC_ADDR_BYTE3           FIELD16(0xff00)
2441 #define EEPROM_MAC_ADDR_BYTE4           FIELD16(0x00ff)
2442 #define EEPROM_MAC_ADDR_BYTE5           FIELD16(0xff00)
2443
2444 /*
2445  * EEPROM NIC Configuration 0
2446  * RXPATH: 1: 1R, 2: 2R, 3: 3R
2447  * TXPATH: 1: 1T, 2: 2T, 3: 3T
2448  * RF_TYPE: RFIC type
2449  */
2450 #define EEPROM_NIC_CONF0_RXPATH         FIELD16(0x000f)
2451 #define EEPROM_NIC_CONF0_TXPATH         FIELD16(0x00f0)
2452 #define EEPROM_NIC_CONF0_RF_TYPE                FIELD16(0x0f00)
2453
2454 /*
2455  * EEPROM NIC Configuration 1
2456  * HW_RADIO: 0: disable, 1: enable
2457  * EXTERNAL_TX_ALC: 0: disable, 1: enable
2458  * EXTERNAL_LNA_2G: 0: disable, 1: enable
2459  * EXTERNAL_LNA_5G: 0: disable, 1: enable
2460  * CARDBUS_ACCEL: 0: enable, 1: disable
2461  * BW40M_SB_2G: 0: disable, 1: enable
2462  * BW40M_SB_5G: 0: disable, 1: enable
2463  * WPS_PBC: 0: disable, 1: enable
2464  * BW40M_2G: 0: enable, 1: disable
2465  * BW40M_5G: 0: enable, 1: disable
2466  * BROADBAND_EXT_LNA: 0: disable, 1: enable
2467  * ANT_DIVERSITY: 00: Disable, 01: Diversity,
2468  *                                10: Main antenna, 11: Aux antenna
2469  * INTERNAL_TX_ALC: 0: disable, 1: enable
2470  * BT_COEXIST: 0: disable, 1: enable
2471  * DAC_TEST: 0: disable, 1: enable
2472  */
2473 #define EEPROM_NIC_CONF1_HW_RADIO               FIELD16(0x0001)
2474 #define EEPROM_NIC_CONF1_EXTERNAL_TX_ALC                FIELD16(0x0002)
2475 #define EEPROM_NIC_CONF1_EXTERNAL_LNA_2G                FIELD16(0x0004)
2476 #define EEPROM_NIC_CONF1_EXTERNAL_LNA_5G                FIELD16(0x0008)
2477 #define EEPROM_NIC_CONF1_CARDBUS_ACCEL          FIELD16(0x0010)
2478 #define EEPROM_NIC_CONF1_BW40M_SB_2G            FIELD16(0x0020)
2479 #define EEPROM_NIC_CONF1_BW40M_SB_5G            FIELD16(0x0040)
2480 #define EEPROM_NIC_CONF1_WPS_PBC                FIELD16(0x0080)
2481 #define EEPROM_NIC_CONF1_BW40M_2G               FIELD16(0x0100)
2482 #define EEPROM_NIC_CONF1_BW40M_5G               FIELD16(0x0200)
2483 #define EEPROM_NIC_CONF1_BROADBAND_EXT_LNA              FIELD16(0x400)
2484 #define EEPROM_NIC_CONF1_ANT_DIVERSITY          FIELD16(0x1800)
2485 #define EEPROM_NIC_CONF1_INTERNAL_TX_ALC                FIELD16(0x2000)
2486 #define EEPROM_NIC_CONF1_BT_COEXIST             FIELD16(0x4000)
2487 #define EEPROM_NIC_CONF1_DAC_TEST               FIELD16(0x8000)
2488
2489 /*
2490  * EEPROM frequency
2491  */
2492 #define EEPROM_FREQ_OFFSET              FIELD16(0x00ff)
2493 #define EEPROM_FREQ_LED_MODE            FIELD16(0x7f00)
2494 #define EEPROM_FREQ_LED_POLARITY        FIELD16(0x1000)
2495
2496 /*
2497  * EEPROM LED
2498  * POLARITY_RDY_G: Polarity RDY_G setting.
2499  * POLARITY_RDY_A: Polarity RDY_A setting.
2500  * POLARITY_ACT: Polarity ACT setting.
2501  * POLARITY_GPIO_0: Polarity GPIO0 setting.
2502  * POLARITY_GPIO_1: Polarity GPIO1 setting.
2503  * POLARITY_GPIO_2: Polarity GPIO2 setting.
2504  * POLARITY_GPIO_3: Polarity GPIO3 setting.
2505  * POLARITY_GPIO_4: Polarity GPIO4 setting.
2506  * LED_MODE: Led mode.
2507  */
2508 #define EEPROM_LED_POLARITY_RDY_BG      FIELD16(0x0001)
2509 #define EEPROM_LED_POLARITY_RDY_A       FIELD16(0x0002)
2510 #define EEPROM_LED_POLARITY_ACT         FIELD16(0x0004)
2511 #define EEPROM_LED_POLARITY_GPIO_0      FIELD16(0x0008)
2512 #define EEPROM_LED_POLARITY_GPIO_1      FIELD16(0x0010)
2513 #define EEPROM_LED_POLARITY_GPIO_2      FIELD16(0x0020)
2514 #define EEPROM_LED_POLARITY_GPIO_3      FIELD16(0x0040)
2515 #define EEPROM_LED_POLARITY_GPIO_4      FIELD16(0x0080)
2516 #define EEPROM_LED_LED_MODE             FIELD16(0x1f00)
2517
2518 /*
2519  * EEPROM NIC Configuration 2
2520  * RX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
2521  * TX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
2522  * CRYSTAL: 00: Reserved, 01: One crystal, 10: Two crystal, 11: Reserved
2523  */
2524 #define EEPROM_NIC_CONF2_RX_STREAM              FIELD16(0x000f)
2525 #define EEPROM_NIC_CONF2_TX_STREAM              FIELD16(0x00f0)
2526 #define EEPROM_NIC_CONF2_CRYSTAL                FIELD16(0x0600)
2527
2528 /*
2529  * EEPROM LNA
2530  */
2531 #define EEPROM_LNA_BG                   FIELD16(0x00ff)
2532 #define EEPROM_LNA_A0                   FIELD16(0xff00)
2533
2534 /*
2535  * EEPROM RSSI BG offset
2536  */
2537 #define EEPROM_RSSI_BG_OFFSET0          FIELD16(0x00ff)
2538 #define EEPROM_RSSI_BG_OFFSET1          FIELD16(0xff00)
2539
2540 /*
2541  * EEPROM RSSI BG2 offset
2542  */
2543 #define EEPROM_RSSI_BG2_OFFSET2         FIELD16(0x00ff)
2544 #define EEPROM_RSSI_BG2_LNA_A1          FIELD16(0xff00)
2545
2546 /*
2547  * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2).
2548  */
2549 #define EEPROM_TXMIXER_GAIN_BG_VAL      FIELD16(0x0007)
2550
2551 /*
2552  * EEPROM RSSI A offset
2553  */
2554 #define EEPROM_RSSI_A_OFFSET0           FIELD16(0x00ff)
2555 #define EEPROM_RSSI_A_OFFSET1           FIELD16(0xff00)
2556
2557 /*
2558  * EEPROM RSSI A2 offset
2559  */
2560 #define EEPROM_RSSI_A2_OFFSET2          FIELD16(0x00ff)
2561 #define EEPROM_RSSI_A2_LNA_A2           FIELD16(0xff00)
2562
2563 /*
2564  * EEPROM TXMIXER GAIN A offset (note overlaps with EEPROM RSSI A2).
2565  */
2566 #define EEPROM_TXMIXER_GAIN_A_VAL       FIELD16(0x0007)
2567
2568 /*
2569  * EEPROM EIRP Maximum TX power values(unit: dbm)
2570  */
2571 #define EEPROM_EIRP_MAX_TX_POWER_2GHZ   FIELD16(0x00ff)
2572 #define EEPROM_EIRP_MAX_TX_POWER_5GHZ   FIELD16(0xff00)
2573
2574 /*
2575  * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
2576  * This is delta in 40MHZ.
2577  * VALUE: Tx Power dalta value, MAX=4(unit: dbm)
2578  * TYPE: 1: Plus the delta value, 0: minus the delta value
2579  * ENABLE: enable tx power compensation for 40BW
2580  */
2581 #define EEPROM_TXPOWER_DELTA_VALUE_2G   FIELD16(0x003f)
2582 #define EEPROM_TXPOWER_DELTA_TYPE_2G    FIELD16(0x0040)
2583 #define EEPROM_TXPOWER_DELTA_ENABLE_2G  FIELD16(0x0080)
2584 #define EEPROM_TXPOWER_DELTA_VALUE_5G   FIELD16(0x3f00)
2585 #define EEPROM_TXPOWER_DELTA_TYPE_5G    FIELD16(0x4000)
2586 #define EEPROM_TXPOWER_DELTA_ENABLE_5G  FIELD16(0x8000)
2587
2588 /*
2589  * EEPROM TXPOWER 802.11BG
2590  */
2591 #define EEPROM_TXPOWER_BG_SIZE          7
2592 #define EEPROM_TXPOWER_BG_1             FIELD16(0x00ff)
2593 #define EEPROM_TXPOWER_BG_2             FIELD16(0xff00)
2594
2595 /*
2596  * EEPROM temperature compensation boundaries 802.11BG
2597  * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
2598  *         reduced by (agc_step * -4)
2599  * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
2600  *         reduced by (agc_step * -3)
2601  */
2602 #define EEPROM_TSSI_BOUND_BG1_MINUS4    FIELD16(0x00ff)
2603 #define EEPROM_TSSI_BOUND_BG1_MINUS3    FIELD16(0xff00)
2604
2605 /*
2606  * EEPROM temperature compensation boundaries 802.11BG
2607  * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
2608  *         reduced by (agc_step * -2)
2609  * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
2610  *         reduced by (agc_step * -1)
2611  */
2612 #define EEPROM_TSSI_BOUND_BG2_MINUS2    FIELD16(0x00ff)
2613 #define EEPROM_TSSI_BOUND_BG2_MINUS1    FIELD16(0xff00)
2614
2615 /*
2616  * EEPROM temperature compensation boundaries 802.11BG
2617  * REF: Reference TSSI value, no tx power changes needed
2618  * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
2619  *        increased by (agc_step * 1)
2620  */
2621 #define EEPROM_TSSI_BOUND_BG3_REF       FIELD16(0x00ff)
2622 #define EEPROM_TSSI_BOUND_BG3_PLUS1     FIELD16(0xff00)
2623
2624 /*
2625  * EEPROM temperature compensation boundaries 802.11BG
2626  * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
2627  *        increased by (agc_step * 2)
2628  * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
2629  *        increased by (agc_step * 3)
2630  */
2631 #define EEPROM_TSSI_BOUND_BG4_PLUS2     FIELD16(0x00ff)
2632 #define EEPROM_TSSI_BOUND_BG4_PLUS3     FIELD16(0xff00)
2633
2634 /*
2635  * EEPROM temperature compensation boundaries 802.11BG
2636  * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
2637  *        increased by (agc_step * 4)
2638  * AGC_STEP: Temperature compensation step.
2639  */
2640 #define EEPROM_TSSI_BOUND_BG5_PLUS4     FIELD16(0x00ff)
2641 #define EEPROM_TSSI_BOUND_BG5_AGC_STEP  FIELD16(0xff00)
2642
2643 /*
2644  * EEPROM TXPOWER 802.11A
2645  */
2646 #define EEPROM_TXPOWER_A_SIZE           6
2647 #define EEPROM_TXPOWER_A_1              FIELD16(0x00ff)
2648 #define EEPROM_TXPOWER_A_2              FIELD16(0xff00)
2649
2650 /* EEPROM_TXPOWER_{A,G} fields for RT3593 */
2651 #define EEPROM_TXPOWER_ALC              FIELD8(0x1f)
2652 #define EEPROM_TXPOWER_FINE_CTRL        FIELD8(0xe0)
2653
2654 /*
2655  * EEPROM temperature compensation boundaries 802.11A
2656  * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
2657  *         reduced by (agc_step * -4)
2658  * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
2659  *         reduced by (agc_step * -3)
2660  */
2661 #define EEPROM_TSSI_BOUND_A1_MINUS4     FIELD16(0x00ff)
2662 #define EEPROM_TSSI_BOUND_A1_MINUS3     FIELD16(0xff00)
2663
2664 /*
2665  * EEPROM temperature compensation boundaries 802.11A
2666  * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
2667  *         reduced by (agc_step * -2)
2668  * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
2669  *         reduced by (agc_step * -1)
2670  */
2671 #define EEPROM_TSSI_BOUND_A2_MINUS2     FIELD16(0x00ff)
2672 #define EEPROM_TSSI_BOUND_A2_MINUS1     FIELD16(0xff00)
2673
2674 /*
2675  * EEPROM temperature compensation boundaries 802.11A
2676  * REF: Reference TSSI value, no tx power changes needed
2677  * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
2678  *        increased by (agc_step * 1)
2679  */
2680 #define EEPROM_TSSI_BOUND_A3_REF        FIELD16(0x00ff)
2681 #define EEPROM_TSSI_BOUND_A3_PLUS1      FIELD16(0xff00)
2682
2683 /*
2684  * EEPROM temperature compensation boundaries 802.11A
2685  * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
2686  *        increased by (agc_step * 2)
2687  * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
2688  *        increased by (agc_step * 3)
2689  */
2690 #define EEPROM_TSSI_BOUND_A4_PLUS2      FIELD16(0x00ff)
2691 #define EEPROM_TSSI_BOUND_A4_PLUS3      FIELD16(0xff00)
2692
2693 /*
2694  * EEPROM temperature compensation boundaries 802.11A
2695  * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
2696  *        increased by (agc_step * 4)
2697  * AGC_STEP: Temperature compensation step.
2698  */
2699 #define EEPROM_TSSI_BOUND_A5_PLUS4      FIELD16(0x00ff)
2700 #define EEPROM_TSSI_BOUND_A5_AGC_STEP   FIELD16(0xff00)
2701
2702 /*
2703  * EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode
2704  */
2705 #define EEPROM_TXPOWER_BYRATE_SIZE      9
2706
2707 #define EEPROM_TXPOWER_BYRATE_RATE0     FIELD16(0x000f)
2708 #define EEPROM_TXPOWER_BYRATE_RATE1     FIELD16(0x00f0)
2709 #define EEPROM_TXPOWER_BYRATE_RATE2     FIELD16(0x0f00)
2710 #define EEPROM_TXPOWER_BYRATE_RATE3     FIELD16(0xf000)
2711
2712 /*
2713  * EEPROM BBP.
2714  */
2715 #define EEPROM_BBP_SIZE                 16
2716 #define EEPROM_BBP_VALUE                FIELD16(0x00ff)
2717 #define EEPROM_BBP_REG_ID               FIELD16(0xff00)
2718
2719 /* EEPROM_EXT_LNA2 */
2720 #define EEPROM_EXT_LNA2_A1              FIELD16(0x00ff)
2721 #define EEPROM_EXT_LNA2_A2              FIELD16(0xff00)
2722
2723 /*
2724  * EEPROM IQ Calibration, unlike other entries those are byte addresses.
2725  */
2726
2727 #define EEPROM_IQ_GAIN_CAL_TX0_2G                       0x130
2728 #define EEPROM_IQ_PHASE_CAL_TX0_2G                      0x131
2729 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_2G                 0x132
2730 #define EEPROM_IQ_GAIN_CAL_TX1_2G                       0x133
2731 #define EEPROM_IQ_PHASE_CAL_TX1_2G                      0x134
2732 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_2G                 0x135
2733 #define EEPROM_IQ_GAIN_CAL_RX0_2G                       0x136
2734 #define EEPROM_IQ_PHASE_CAL_RX0_2G                      0x137
2735 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_2G                 0x138
2736 #define EEPROM_IQ_GAIN_CAL_RX1_2G                       0x139
2737 #define EEPROM_IQ_PHASE_CAL_RX1_2G                      0x13A
2738 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_2G                 0x13B
2739 #define EEPROM_RF_IQ_COMPENSATION_CONTROL               0x13C
2740 #define EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL     0x13D
2741 #define EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G          0x144
2742 #define EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G         0x145
2743 #define EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G        0X146
2744 #define EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G       0x147
2745 #define EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G        0x148
2746 #define EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G       0x149
2747 #define EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G          0x14A
2748 #define EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G         0x14B
2749 #define EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G        0X14C
2750 #define EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G       0x14D
2751 #define EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G        0x14E
2752 #define EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G       0x14F
2753 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH36_TO_CH64_5G    0x150
2754 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH36_TO_CH64_5G    0x151
2755 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH100_TO_CH138_5G  0x152
2756 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH100_TO_CH138_5G  0x153
2757 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH140_TO_CH165_5G  0x154
2758 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH140_TO_CH165_5G  0x155
2759 #define EEPROM_IQ_GAIN_CAL_RX0_CH36_TO_CH64_5G          0x156
2760 #define EEPROM_IQ_PHASE_CAL_RX0_CH36_TO_CH64_5G         0x157
2761 #define EEPROM_IQ_GAIN_CAL_RX0_CH100_TO_CH138_5G        0X158
2762 #define EEPROM_IQ_PHASE_CAL_RX0_CH100_TO_CH138_5G       0x159
2763 #define EEPROM_IQ_GAIN_CAL_RX0_CH140_TO_CH165_5G        0x15A
2764 #define EEPROM_IQ_PHASE_CAL_RX0_CH140_TO_CH165_5G       0x15B
2765 #define EEPROM_IQ_GAIN_CAL_RX1_CH36_TO_CH64_5G          0x15C
2766 #define EEPROM_IQ_PHASE_CAL_RX1_CH36_TO_CH64_5G         0x15D
2767 #define EEPROM_IQ_GAIN_CAL_RX1_CH100_TO_CH138_5G        0X15E
2768 #define EEPROM_IQ_PHASE_CAL_RX1_CH100_TO_CH138_5G       0x15F
2769 #define EEPROM_IQ_GAIN_CAL_RX1_CH140_TO_CH165_5G        0x160
2770 #define EEPROM_IQ_PHASE_CAL_RX1_CH140_TO_CH165_5G       0x161
2771 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH36_TO_CH64_5G    0x162
2772 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH36_TO_CH64_5G    0x163
2773 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH100_TO_CH138_5G  0x164
2774 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH100_TO_CH138_5G  0x165
2775 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH140_TO_CH165_5G  0x166
2776 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH140_TO_CH165_5G  0x167
2777
2778 /*
2779  * MCU mailbox commands.
2780  * MCU_SLEEP - go to power-save mode.
2781  *             arg1: 1: save as much power as possible, 0: save less power.
2782  *             status: 1: success, 2: already asleep,
2783  *                     3: maybe MAC is busy so can't finish this task.
2784  * MCU_RADIO_OFF
2785  *             arg0: 0: do power-saving, NOT turn off radio.
2786  */
2787 #define MCU_SLEEP                       0x30
2788 #define MCU_WAKEUP                      0x31
2789 #define MCU_RADIO_OFF                   0x35
2790 #define MCU_CURRENT                     0x36
2791 #define MCU_LED                         0x50
2792 #define MCU_LED_STRENGTH                0x51
2793 #define MCU_LED_AG_CONF         0x52
2794 #define MCU_LED_ACT_CONF                0x53
2795 #define MCU_LED_LED_POLARITY            0x54
2796 #define MCU_RADAR                       0x60
2797 #define MCU_BOOT_SIGNAL                 0x72
2798 #define MCU_ANT_SELECT                  0X73
2799 #define MCU_FREQ_OFFSET                 0x74
2800 #define MCU_BBP_SIGNAL                  0x80
2801 #define MCU_POWER_SAVE                  0x83
2802 #define MCU_BAND_SELECT         0x91
2803
2804 /*
2805  * MCU mailbox tokens
2806  */
2807 #define TOKEN_SLEEP                     1
2808 #define TOKEN_RADIO_OFF                 2
2809 #define TOKEN_WAKEUP                    3
2810
2811
2812 /*
2813  * DMA descriptor defines.
2814  */
2815
2816 #define TXWI_DESC_SIZE_4WORDS           (4 * sizeof(__le32))
2817 #define TXWI_DESC_SIZE_5WORDS           (5 * sizeof(__le32))
2818
2819 #define RXWI_DESC_SIZE_4WORDS           (4 * sizeof(__le32))
2820 #define RXWI_DESC_SIZE_5WORDS           (5 * sizeof(__le32))
2821 #define RXWI_DESC_SIZE_6WORDS           (6 * sizeof(__le32))
2822
2823 /*
2824  * TX WI structure
2825  */
2826
2827 /*
2828  * Word0
2829  * FRAG: 1 To inform TKIP engine this is a fragment.
2830  * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
2831  * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
2832  * BW: Channel bandwidth 0:20MHz, 1:40 MHz (for legacy rates this will
2833  *     duplicate the frame to both channels).
2834  * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
2835  * AMPDU: 1: this frame is eligible for AMPDU aggregation, the hw will
2836  *        aggregate consecutive frames with the same RA and QoS TID. If
2837  *        a frame A with the same RA and QoS TID but AMPDU=0 is queued
2838  *        directly after a frame B with AMPDU=1, frame A might still
2839  *        get aggregated into the AMPDU started by frame B. So, setting
2840  *        AMPDU to 0 does _not_ necessarily mean the frame is sent as
2841  *        MPDU, it can still end up in an AMPDU if the previous frame
2842  *        was tagged as AMPDU.
2843  */
2844 #define TXWI_W0_FRAG                    FIELD32(0x00000001)
2845 #define TXWI_W0_MIMO_PS                 FIELD32(0x00000002)
2846 #define TXWI_W0_CF_ACK                  FIELD32(0x00000004)
2847 #define TXWI_W0_TS                      FIELD32(0x00000008)
2848 #define TXWI_W0_AMPDU                   FIELD32(0x00000010)
2849 #define TXWI_W0_MPDU_DENSITY            FIELD32(0x000000e0)
2850 #define TXWI_W0_TX_OP                   FIELD32(0x00000300)
2851 #define TXWI_W0_MCS                     FIELD32(0x007f0000)
2852 #define TXWI_W0_BW                      FIELD32(0x00800000)
2853 #define TXWI_W0_SHORT_GI                FIELD32(0x01000000)
2854 #define TXWI_W0_STBC                    FIELD32(0x06000000)
2855 #define TXWI_W0_IFS                     FIELD32(0x08000000)
2856 #define TXWI_W0_PHYMODE                 FIELD32(0xc0000000)
2857
2858 /*
2859  * Word1
2860  * ACK: 0: No Ack needed, 1: Ack needed
2861  * NSEQ: 0: Don't assign hw sequence number, 1: Assign hw sequence number
2862  * BW_WIN_SIZE: BA windows size of the recipient
2863  * WIRELESS_CLI_ID: Client ID for WCID table access
2864  * MPDU_TOTAL_BYTE_COUNT: Length of 802.11 frame
2865  * PACKETID: Will be latched into the TX_STA_FIFO register once the according
2866  *           frame was processed. If multiple frames are aggregated together
2867  *           (AMPDU==1) the reported tx status will always contain the packet
2868  *           id of the first frame. 0: Don't report tx status for this frame.
2869  * PACKETID_QUEUE: Part of PACKETID, This is the queue index (0-3)
2870  * PACKETID_ENTRY: Part of PACKETID, THis is the queue entry index (1-3)
2871  *                 This identification number is calculated by ((idx % 3) + 1).
2872  *                 The (+1) is required to prevent PACKETID to become 0.
2873  */
2874 #define TXWI_W1_ACK                     FIELD32(0x00000001)
2875 #define TXWI_W1_NSEQ                    FIELD32(0x00000002)
2876 #define TXWI_W1_BW_WIN_SIZE             FIELD32(0x000000fc)
2877 #define TXWI_W1_WIRELESS_CLI_ID         FIELD32(0x0000ff00)
2878 #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT   FIELD32(0x0fff0000)
2879 #define TXWI_W1_PACKETID                FIELD32(0xf0000000)
2880 #define TXWI_W1_PACKETID_QUEUE          FIELD32(0x30000000)
2881 #define TXWI_W1_PACKETID_ENTRY          FIELD32(0xc0000000)
2882
2883 /*
2884  * Word2
2885  */
2886 #define TXWI_W2_IV                      FIELD32(0xffffffff)
2887
2888 /*
2889  * Word3
2890  */
2891 #define TXWI_W3_EIV                     FIELD32(0xffffffff)
2892
2893 /*
2894  * RX WI structure
2895  */
2896
2897 /*
2898  * Word0
2899  */
2900 #define RXWI_W0_WIRELESS_CLI_ID         FIELD32(0x000000ff)
2901 #define RXWI_W0_KEY_INDEX               FIELD32(0x00000300)
2902 #define RXWI_W0_BSSID                   FIELD32(0x00001c00)
2903 #define RXWI_W0_UDF                     FIELD32(0x0000e000)
2904 #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT   FIELD32(0x0fff0000)
2905 #define RXWI_W0_TID                     FIELD32(0xf0000000)
2906
2907 /*
2908  * Word1
2909  */
2910 #define RXWI_W1_FRAG                    FIELD32(0x0000000f)
2911 #define RXWI_W1_SEQUENCE                FIELD32(0x0000fff0)
2912 #define RXWI_W1_MCS                     FIELD32(0x007f0000)
2913 #define RXWI_W1_BW                      FIELD32(0x00800000)
2914 #define RXWI_W1_SHORT_GI                FIELD32(0x01000000)
2915 #define RXWI_W1_STBC                    FIELD32(0x06000000)
2916 #define RXWI_W1_PHYMODE                 FIELD32(0xc0000000)
2917
2918 /*
2919  * Word2
2920  */
2921 #define RXWI_W2_RSSI0                   FIELD32(0x000000ff)
2922 #define RXWI_W2_RSSI1                   FIELD32(0x0000ff00)
2923 #define RXWI_W2_RSSI2                   FIELD32(0x00ff0000)
2924
2925 /*
2926  * Word3
2927  */
2928 #define RXWI_W3_SNR0                    FIELD32(0x000000ff)
2929 #define RXWI_W3_SNR1                    FIELD32(0x0000ff00)
2930
2931 /*
2932  * Macros for converting txpower from EEPROM to mac80211 value
2933  * and from mac80211 value to register value.
2934  */
2935 #define MIN_G_TXPOWER   0
2936 #define MIN_A_TXPOWER   -7
2937 #define MAX_G_TXPOWER   31
2938 #define MAX_A_TXPOWER   15
2939 #define DEFAULT_TXPOWER 5
2940
2941 #define MIN_A_TXPOWER_3593      0
2942 #define MAX_A_TXPOWER_3593      31
2943
2944 #define TXPOWER_G_FROM_DEV(__txpower) \
2945         ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
2946
2947 #define TXPOWER_A_FROM_DEV(__txpower) \
2948         ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
2949
2950 /*
2951  *  Board's maximun TX power limitation
2952  */
2953 #define EIRP_MAX_TX_POWER_LIMIT 0x50
2954
2955 /*
2956  * Number of TBTT intervals after which we have to adjust
2957  * the hw beacon timer.
2958  */
2959 #define BCN_TBTT_OFFSET 64
2960
2961 /*
2962  * RT2800 driver data structure
2963  */
2964 struct rt2800_drv_data {
2965         u8 calibration_bw20;
2966         u8 calibration_bw40;
2967         u8 bbp25;
2968         u8 bbp26;
2969         u8 txmixer_gain_24g;
2970         u8 txmixer_gain_5g;
2971         unsigned int tbtt_tick;
2972 };
2973
2974 #endif /* RT2800_H */