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Merge branch 'for-linus' of git://git.samba.org/sfrench/cifs-2.6
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800.h
1 /*
2 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
4 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
5 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
6 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
7 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
8 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
9 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
10 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
11 <http://rt2x00.serialmonkey.com>
12
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
17
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with this program; if not, write to the
25 Free Software Foundation, Inc.,
26 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 */
28
29 /*
30 Module: rt2800
31 Abstract: Data structures and registers for the rt2800 modules.
32 Supported chipsets: RT2800E, RT2800ED & RT2800U.
33 */
34
35 #ifndef RT2800_H
36 #define RT2800_H
37
38 /*
39 * RF chip defines.
40 *
41 * RF2820 2.4G 2T3R
42 * RF2850 2.4G/5G 2T3R
43 * RF2720 2.4G 1T2R
44 * RF2750 2.4G/5G 1T2R
45 * RF3020 2.4G 1T1R
46 * RF2020 2.4G B/G
47 * RF3021 2.4G 1T2R
48 * RF3022 2.4G 2T2R
49 * RF3052 2.4G/5G 2T2R
50 * RF2853 2.4G/5G 3T3R
51 * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390)
52 * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392)
53 * RF3053 2.4G/5G 3T3R(RT3883/RT3563/RT3573/RT3593/RT3662)
54 * RF5592 2.4G/5G 2T2R
55 * RF5360 2.4G 1T1R
56 * RF5370 2.4G 1T1R
57 * RF5390 2.4G 1T1R
58 */
59 #define RF2820 0x0001
60 #define RF2850 0x0002
61 #define RF2720 0x0003
62 #define RF2750 0x0004
63 #define RF3020 0x0005
64 #define RF2020 0x0006
65 #define RF3021 0x0007
66 #define RF3022 0x0008
67 #define RF3052 0x0009
68 #define RF2853 0x000a
69 #define RF3320 0x000b
70 #define RF3322 0x000c
71 #define RF3053 0x000d
72 #define RF5592 0x000f
73 #define RF3290 0x3290
74 #define RF5360 0x5360
75 #define RF5370 0x5370
76 #define RF5372 0x5372
77 #define RF5390 0x5390
78 #define RF5392 0x5392
79
80 /*
81 * Chipset revisions.
82 */
83 #define REV_RT2860C 0x0100
84 #define REV_RT2860D 0x0101
85 #define REV_RT2872E 0x0200
86 #define REV_RT3070E 0x0200
87 #define REV_RT3070F 0x0201
88 #define REV_RT3071E 0x0211
89 #define REV_RT3090E 0x0211
90 #define REV_RT3390E 0x0211
91 #define REV_RT5390F 0x0502
92 #define REV_RT5390R 0x1502
93 #define REV_RT5592C 0x0221
94
95 #define DEFAULT_RSSI_OFFSET 120
96
97 /*
98 * Register layout information.
99 */
100 #define CSR_REG_BASE 0x1000
101 #define CSR_REG_SIZE 0x0800
102 #define EEPROM_BASE 0x0000
103 #define EEPROM_SIZE 0x0200
104 #define BBP_BASE 0x0000
105 #define BBP_SIZE 0x00ff
106 #define RF_BASE 0x0004
107 #define RF_SIZE 0x0010
108 #define RFCSR_BASE 0x0000
109 #define RFCSR_SIZE 0x0040
110
111 /*
112 * Number of TX queues.
113 */
114 #define NUM_TX_QUEUES 4
115
116 /*
117 * Registers.
118 */
119
120
121 /*
122 * MAC_CSR0_3290: MAC_CSR0 for RT3290 to identity MAC version number.
123 */
124 #define MAC_CSR0_3290 0x0000
125
126 /*
127 * E2PROM_CSR: PCI EEPROM control register.
128 * RELOAD: Write 1 to reload eeprom content.
129 * TYPE: 0: 93c46, 1:93c66.
130 * LOAD_STATUS: 1:loading, 0:done.
131 */
132 #define E2PROM_CSR 0x0004
133 #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
134 #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
135 #define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
136 #define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
137 #define E2PROM_CSR_TYPE FIELD32(0x00000030)
138 #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
139 #define E2PROM_CSR_RELOAD FIELD32(0x00000080)
140
141 /*
142 * CMB_CTRL_CFG
143 */
144 #define CMB_CTRL 0x0020
145 #define AUX_OPT_BIT0 FIELD32(0x00000001)
146 #define AUX_OPT_BIT1 FIELD32(0x00000002)
147 #define AUX_OPT_BIT2 FIELD32(0x00000004)
148 #define AUX_OPT_BIT3 FIELD32(0x00000008)
149 #define AUX_OPT_BIT4 FIELD32(0x00000010)
150 #define AUX_OPT_BIT5 FIELD32(0x00000020)
151 #define AUX_OPT_BIT6 FIELD32(0x00000040)
152 #define AUX_OPT_BIT7 FIELD32(0x00000080)
153 #define AUX_OPT_BIT8 FIELD32(0x00000100)
154 #define AUX_OPT_BIT9 FIELD32(0x00000200)
155 #define AUX_OPT_BIT10 FIELD32(0x00000400)
156 #define AUX_OPT_BIT11 FIELD32(0x00000800)
157 #define AUX_OPT_BIT12 FIELD32(0x00001000)
158 #define AUX_OPT_BIT13 FIELD32(0x00002000)
159 #define AUX_OPT_BIT14 FIELD32(0x00004000)
160 #define AUX_OPT_BIT15 FIELD32(0x00008000)
161 #define LDO25_LEVEL FIELD32(0x00030000)
162 #define LDO25_LARGEA FIELD32(0x00040000)
163 #define LDO25_FRC_ON FIELD32(0x00080000)
164 #define CMB_RSV FIELD32(0x00300000)
165 #define XTAL_RDY FIELD32(0x00400000)
166 #define PLL_LD FIELD32(0x00800000)
167 #define LDO_CORE_LEVEL FIELD32(0x0F000000)
168 #define LDO_BGSEL FIELD32(0x30000000)
169 #define LDO3_EN FIELD32(0x40000000)
170 #define LDO0_EN FIELD32(0x80000000)
171
172 /*
173 * EFUSE_CSR_3290: RT3290 EEPROM
174 */
175 #define EFUSE_CTRL_3290 0x0024
176
177 /*
178 * EFUSE_DATA3 of 3290
179 */
180 #define EFUSE_DATA3_3290 0x0028
181
182 /*
183 * EFUSE_DATA2 of 3290
184 */
185 #define EFUSE_DATA2_3290 0x002c
186
187 /*
188 * EFUSE_DATA1 of 3290
189 */
190 #define EFUSE_DATA1_3290 0x0030
191
192 /*
193 * EFUSE_DATA0 of 3290
194 */
195 #define EFUSE_DATA0_3290 0x0034
196
197 /*
198 * OSC_CTRL_CFG
199 * Ring oscillator configuration
200 */
201 #define OSC_CTRL 0x0038
202 #define OSC_REF_CYCLE FIELD32(0x00001fff)
203 #define OSC_RSV FIELD32(0x0000e000)
204 #define OSC_CAL_CNT FIELD32(0x0fff0000)
205 #define OSC_CAL_ACK FIELD32(0x10000000)
206 #define OSC_CLK_32K_VLD FIELD32(0x20000000)
207 #define OSC_CAL_REQ FIELD32(0x40000000)
208 #define OSC_ROSC_EN FIELD32(0x80000000)
209
210 /*
211 * COEX_CFG_0
212 */
213 #define COEX_CFG0 0x0040
214 #define COEX_CFG_ANT FIELD32(0xff000000)
215 /*
216 * COEX_CFG_1
217 */
218 #define COEX_CFG1 0x0044
219
220 /*
221 * COEX_CFG_2
222 */
223 #define COEX_CFG2 0x0048
224 #define BT_COEX_CFG1 FIELD32(0xff000000)
225 #define BT_COEX_CFG0 FIELD32(0x00ff0000)
226 #define WL_COEX_CFG1 FIELD32(0x0000ff00)
227 #define WL_COEX_CFG0 FIELD32(0x000000ff)
228 /*
229 * PLL_CTRL_CFG
230 * PLL configuration register
231 */
232 #define PLL_CTRL 0x0050
233 #define PLL_RESERVED_INPUT1 FIELD32(0x000000ff)
234 #define PLL_RESERVED_INPUT2 FIELD32(0x0000ff00)
235 #define PLL_CONTROL FIELD32(0x00070000)
236 #define PLL_LPF_R1 FIELD32(0x00080000)
237 #define PLL_LPF_C1_CTRL FIELD32(0x00300000)
238 #define PLL_LPF_C2_CTRL FIELD32(0x00c00000)
239 #define PLL_CP_CURRENT_CTRL FIELD32(0x03000000)
240 #define PLL_PFD_DELAY_CTRL FIELD32(0x0c000000)
241 #define PLL_LOCK_CTRL FIELD32(0x70000000)
242 #define PLL_VBGBK_EN FIELD32(0x80000000)
243
244
245 /*
246 * WLAN_CTRL_CFG
247 * RT3290 wlan configuration
248 */
249 #define WLAN_FUN_CTRL 0x0080
250 #define WLAN_EN FIELD32(0x00000001)
251 #define WLAN_CLK_EN FIELD32(0x00000002)
252 #define WLAN_RSV1 FIELD32(0x00000004)
253 #define WLAN_RESET FIELD32(0x00000008)
254 #define PCIE_APP0_CLK_REQ FIELD32(0x00000010)
255 #define FRC_WL_ANT_SET FIELD32(0x00000020)
256 #define INV_TR_SW0 FIELD32(0x00000040)
257 #define WLAN_GPIO_IN_BIT0 FIELD32(0x00000100)
258 #define WLAN_GPIO_IN_BIT1 FIELD32(0x00000200)
259 #define WLAN_GPIO_IN_BIT2 FIELD32(0x00000400)
260 #define WLAN_GPIO_IN_BIT3 FIELD32(0x00000800)
261 #define WLAN_GPIO_IN_BIT4 FIELD32(0x00001000)
262 #define WLAN_GPIO_IN_BIT5 FIELD32(0x00002000)
263 #define WLAN_GPIO_IN_BIT6 FIELD32(0x00004000)
264 #define WLAN_GPIO_IN_BIT7 FIELD32(0x00008000)
265 #define WLAN_GPIO_IN_BIT_ALL FIELD32(0x0000ff00)
266 #define WLAN_GPIO_OUT_BIT0 FIELD32(0x00010000)
267 #define WLAN_GPIO_OUT_BIT1 FIELD32(0x00020000)
268 #define WLAN_GPIO_OUT_BIT2 FIELD32(0x00040000)
269 #define WLAN_GPIO_OUT_BIT3 FIELD32(0x00050000)
270 #define WLAN_GPIO_OUT_BIT4 FIELD32(0x00100000)
271 #define WLAN_GPIO_OUT_BIT5 FIELD32(0x00200000)
272 #define WLAN_GPIO_OUT_BIT6 FIELD32(0x00400000)
273 #define WLAN_GPIO_OUT_BIT7 FIELD32(0x00800000)
274 #define WLAN_GPIO_OUT_BIT_ALL FIELD32(0x00ff0000)
275 #define WLAN_GPIO_OUT_OE_BIT0 FIELD32(0x01000000)
276 #define WLAN_GPIO_OUT_OE_BIT1 FIELD32(0x02000000)
277 #define WLAN_GPIO_OUT_OE_BIT2 FIELD32(0x04000000)
278 #define WLAN_GPIO_OUT_OE_BIT3 FIELD32(0x08000000)
279 #define WLAN_GPIO_OUT_OE_BIT4 FIELD32(0x10000000)
280 #define WLAN_GPIO_OUT_OE_BIT5 FIELD32(0x20000000)
281 #define WLAN_GPIO_OUT_OE_BIT6 FIELD32(0x40000000)
282 #define WLAN_GPIO_OUT_OE_BIT7 FIELD32(0x80000000)
283 #define WLAN_GPIO_OUT_OE_BIT_ALL FIELD32(0xff000000)
284
285 /*
286 * AUX_CTRL: Aux/PCI-E related configuration
287 */
288 #define AUX_CTRL 0x10c
289 #define AUX_CTRL_WAKE_PCIE_EN FIELD32(0x00000002)
290 #define AUX_CTRL_FORCE_PCIE_CLK FIELD32(0x00000400)
291
292 /*
293 * OPT_14: Unknown register used by rt3xxx devices.
294 */
295 #define OPT_14_CSR 0x0114
296 #define OPT_14_CSR_BIT0 FIELD32(0x00000001)
297
298 /*
299 * INT_SOURCE_CSR: Interrupt source register.
300 * Write one to clear corresponding bit.
301 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO
302 */
303 #define INT_SOURCE_CSR 0x0200
304 #define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
305 #define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
306 #define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
307 #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
308 #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
309 #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
310 #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
311 #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
312 #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
313 #define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
314 #define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
315 #define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
316 #define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
317 #define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
318 #define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
319 #define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
320 #define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
321 #define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
322
323 /*
324 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
325 */
326 #define INT_MASK_CSR 0x0204
327 #define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
328 #define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
329 #define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
330 #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
331 #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
332 #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
333 #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
334 #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
335 #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
336 #define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
337 #define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
338 #define INT_MASK_CSR_TBTT FIELD32(0x00000800)
339 #define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
340 #define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
341 #define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
342 #define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
343 #define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
344 #define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
345
346 /*
347 * WPDMA_GLO_CFG
348 */
349 #define WPDMA_GLO_CFG 0x0208
350 #define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
351 #define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
352 #define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
353 #define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
354 #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
355 #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
356 #define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
357 #define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
358 #define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
359
360 /*
361 * WPDMA_RST_IDX
362 */
363 #define WPDMA_RST_IDX 0x020c
364 #define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
365 #define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
366 #define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
367 #define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
368 #define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
369 #define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
370 #define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
371
372 /*
373 * DELAY_INT_CFG
374 */
375 #define DELAY_INT_CFG 0x0210
376 #define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
377 #define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
378 #define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
379 #define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
380 #define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
381 #define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
382
383 /*
384 * WMM_AIFSN_CFG: Aifsn for each EDCA AC
385 * AIFSN0: AC_VO
386 * AIFSN1: AC_VI
387 * AIFSN2: AC_BE
388 * AIFSN3: AC_BK
389 */
390 #define WMM_AIFSN_CFG 0x0214
391 #define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
392 #define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
393 #define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
394 #define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
395
396 /*
397 * WMM_CWMIN_CSR: CWmin for each EDCA AC
398 * CWMIN0: AC_VO
399 * CWMIN1: AC_VI
400 * CWMIN2: AC_BE
401 * CWMIN3: AC_BK
402 */
403 #define WMM_CWMIN_CFG 0x0218
404 #define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
405 #define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
406 #define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
407 #define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
408
409 /*
410 * WMM_CWMAX_CSR: CWmax for each EDCA AC
411 * CWMAX0: AC_VO
412 * CWMAX1: AC_VI
413 * CWMAX2: AC_BE
414 * CWMAX3: AC_BK
415 */
416 #define WMM_CWMAX_CFG 0x021c
417 #define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
418 #define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
419 #define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
420 #define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
421
422 /*
423 * AC_TXOP0: AC_VO/AC_VI TXOP register
424 * AC0TXOP: AC_VO in unit of 32us
425 * AC1TXOP: AC_VI in unit of 32us
426 */
427 #define WMM_TXOP0_CFG 0x0220
428 #define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
429 #define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
430
431 /*
432 * AC_TXOP1: AC_BE/AC_BK TXOP register
433 * AC2TXOP: AC_BE in unit of 32us
434 * AC3TXOP: AC_BK in unit of 32us
435 */
436 #define WMM_TXOP1_CFG 0x0224
437 #define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
438 #define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
439
440 /*
441 * GPIO_CTRL:
442 * GPIO_CTRL_VALx: GPIO value
443 * GPIO_CTRL_DIRx: GPIO direction: 0 = output; 1 = input
444 */
445 #define GPIO_CTRL 0x0228
446 #define GPIO_CTRL_VAL0 FIELD32(0x00000001)
447 #define GPIO_CTRL_VAL1 FIELD32(0x00000002)
448 #define GPIO_CTRL_VAL2 FIELD32(0x00000004)
449 #define GPIO_CTRL_VAL3 FIELD32(0x00000008)
450 #define GPIO_CTRL_VAL4 FIELD32(0x00000010)
451 #define GPIO_CTRL_VAL5 FIELD32(0x00000020)
452 #define GPIO_CTRL_VAL6 FIELD32(0x00000040)
453 #define GPIO_CTRL_VAL7 FIELD32(0x00000080)
454 #define GPIO_CTRL_DIR0 FIELD32(0x00000100)
455 #define GPIO_CTRL_DIR1 FIELD32(0x00000200)
456 #define GPIO_CTRL_DIR2 FIELD32(0x00000400)
457 #define GPIO_CTRL_DIR3 FIELD32(0x00000800)
458 #define GPIO_CTRL_DIR4 FIELD32(0x00001000)
459 #define GPIO_CTRL_DIR5 FIELD32(0x00002000)
460 #define GPIO_CTRL_DIR6 FIELD32(0x00004000)
461 #define GPIO_CTRL_DIR7 FIELD32(0x00008000)
462 #define GPIO_CTRL_VAL8 FIELD32(0x00010000)
463 #define GPIO_CTRL_VAL9 FIELD32(0x00020000)
464 #define GPIO_CTRL_VAL10 FIELD32(0x00040000)
465 #define GPIO_CTRL_DIR8 FIELD32(0x01000000)
466 #define GPIO_CTRL_DIR9 FIELD32(0x02000000)
467 #define GPIO_CTRL_DIR10 FIELD32(0x04000000)
468
469 /*
470 * MCU_CMD_CFG
471 */
472 #define MCU_CMD_CFG 0x022c
473
474 /*
475 * AC_VO register offsets
476 */
477 #define TX_BASE_PTR0 0x0230
478 #define TX_MAX_CNT0 0x0234
479 #define TX_CTX_IDX0 0x0238
480 #define TX_DTX_IDX0 0x023c
481
482 /*
483 * AC_VI register offsets
484 */
485 #define TX_BASE_PTR1 0x0240
486 #define TX_MAX_CNT1 0x0244
487 #define TX_CTX_IDX1 0x0248
488 #define TX_DTX_IDX1 0x024c
489
490 /*
491 * AC_BE register offsets
492 */
493 #define TX_BASE_PTR2 0x0250
494 #define TX_MAX_CNT2 0x0254
495 #define TX_CTX_IDX2 0x0258
496 #define TX_DTX_IDX2 0x025c
497
498 /*
499 * AC_BK register offsets
500 */
501 #define TX_BASE_PTR3 0x0260
502 #define TX_MAX_CNT3 0x0264
503 #define TX_CTX_IDX3 0x0268
504 #define TX_DTX_IDX3 0x026c
505
506 /*
507 * HCCA register offsets
508 */
509 #define TX_BASE_PTR4 0x0270
510 #define TX_MAX_CNT4 0x0274
511 #define TX_CTX_IDX4 0x0278
512 #define TX_DTX_IDX4 0x027c
513
514 /*
515 * MGMT register offsets
516 */
517 #define TX_BASE_PTR5 0x0280
518 #define TX_MAX_CNT5 0x0284
519 #define TX_CTX_IDX5 0x0288
520 #define TX_DTX_IDX5 0x028c
521
522 /*
523 * RX register offsets
524 */
525 #define RX_BASE_PTR 0x0290
526 #define RX_MAX_CNT 0x0294
527 #define RX_CRX_IDX 0x0298
528 #define RX_DRX_IDX 0x029c
529
530 /*
531 * USB_DMA_CFG
532 * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
533 * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
534 * PHY_CLEAR: phy watch dog enable.
535 * TX_CLEAR: Clear USB DMA TX path.
536 * TXOP_HALT: Halt TXOP count down when TX buffer is full.
537 * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
538 * RX_BULK_EN: Enable USB DMA Rx.
539 * TX_BULK_EN: Enable USB DMA Tx.
540 * EP_OUT_VALID: OUT endpoint data valid.
541 * RX_BUSY: USB DMA RX FSM busy.
542 * TX_BUSY: USB DMA TX FSM busy.
543 */
544 #define USB_DMA_CFG 0x02a0
545 #define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
546 #define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00)
547 #define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000)
548 #define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000)
549 #define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000)
550 #define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000)
551 #define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000)
552 #define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000)
553 #define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000)
554 #define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000)
555 #define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000)
556
557 /*
558 * US_CYC_CNT
559 * BT_MODE_EN: Bluetooth mode enable
560 * CLOCK CYCLE: Clock cycle count in 1us.
561 * PCI:0x21, PCIE:0x7d, USB:0x1e
562 */
563 #define US_CYC_CNT 0x02a4
564 #define US_CYC_CNT_BT_MODE_EN FIELD32(0x00000100)
565 #define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff)
566
567 /*
568 * PBF_SYS_CTRL
569 * HOST_RAM_WRITE: enable Host program ram write selection
570 */
571 #define PBF_SYS_CTRL 0x0400
572 #define PBF_SYS_CTRL_READY FIELD32(0x00000080)
573 #define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
574
575 /*
576 * HOST-MCU shared memory
577 */
578 #define HOST_CMD_CSR 0x0404
579 #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
580
581 /*
582 * PBF registers
583 * Most are for debug. Driver doesn't touch PBF register.
584 */
585 #define PBF_CFG 0x0408
586 #define PBF_MAX_PCNT 0x040c
587 #define PBF_CTRL 0x0410
588 #define PBF_INT_STA 0x0414
589 #define PBF_INT_ENA 0x0418
590
591 /*
592 * BCN_OFFSET0:
593 */
594 #define BCN_OFFSET0 0x042c
595 #define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
596 #define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
597 #define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
598 #define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
599
600 /*
601 * BCN_OFFSET1:
602 */
603 #define BCN_OFFSET1 0x0430
604 #define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
605 #define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
606 #define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
607 #define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
608
609 /*
610 * TXRXQ_PCNT: PBF register
611 * PCNT_TX0Q: Page count for TX hardware queue 0
612 * PCNT_TX1Q: Page count for TX hardware queue 1
613 * PCNT_TX2Q: Page count for TX hardware queue 2
614 * PCNT_RX0Q: Page count for RX hardware queue
615 */
616 #define TXRXQ_PCNT 0x0438
617 #define TXRXQ_PCNT_TX0Q FIELD32(0x000000ff)
618 #define TXRXQ_PCNT_TX1Q FIELD32(0x0000ff00)
619 #define TXRXQ_PCNT_TX2Q FIELD32(0x00ff0000)
620 #define TXRXQ_PCNT_RX0Q FIELD32(0xff000000)
621
622 /*
623 * PBF register
624 * Debug. Driver doesn't touch PBF register.
625 */
626 #define PBF_DBG 0x043c
627
628 /*
629 * RF registers
630 */
631 #define RF_CSR_CFG 0x0500
632 #define RF_CSR_CFG_DATA FIELD32(0x000000ff)
633 #define RF_CSR_CFG_REGNUM FIELD32(0x00003f00)
634 #define RF_CSR_CFG_WRITE FIELD32(0x00010000)
635 #define RF_CSR_CFG_BUSY FIELD32(0x00020000)
636
637 /*
638 * EFUSE_CSR: RT30x0 EEPROM
639 */
640 #define EFUSE_CTRL 0x0580
641 #define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000)
642 #define EFUSE_CTRL_MODE FIELD32(0x000000c0)
643 #define EFUSE_CTRL_KICK FIELD32(0x40000000)
644 #define EFUSE_CTRL_PRESENT FIELD32(0x80000000)
645
646 /*
647 * EFUSE_DATA0
648 */
649 #define EFUSE_DATA0 0x0590
650
651 /*
652 * EFUSE_DATA1
653 */
654 #define EFUSE_DATA1 0x0594
655
656 /*
657 * EFUSE_DATA2
658 */
659 #define EFUSE_DATA2 0x0598
660
661 /*
662 * EFUSE_DATA3
663 */
664 #define EFUSE_DATA3 0x059c
665
666 /*
667 * LDO_CFG0
668 */
669 #define LDO_CFG0 0x05d4
670 #define LDO_CFG0_DELAY3 FIELD32(0x000000ff)
671 #define LDO_CFG0_DELAY2 FIELD32(0x0000ff00)
672 #define LDO_CFG0_DELAY1 FIELD32(0x00ff0000)
673 #define LDO_CFG0_BGSEL FIELD32(0x03000000)
674 #define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000)
675 #define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000)
676 #define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000)
677
678 /*
679 * GPIO_SWITCH
680 */
681 #define GPIO_SWITCH 0x05dc
682 #define GPIO_SWITCH_0 FIELD32(0x00000001)
683 #define GPIO_SWITCH_1 FIELD32(0x00000002)
684 #define GPIO_SWITCH_2 FIELD32(0x00000004)
685 #define GPIO_SWITCH_3 FIELD32(0x00000008)
686 #define GPIO_SWITCH_4 FIELD32(0x00000010)
687 #define GPIO_SWITCH_5 FIELD32(0x00000020)
688 #define GPIO_SWITCH_6 FIELD32(0x00000040)
689 #define GPIO_SWITCH_7 FIELD32(0x00000080)
690
691 /*
692 * FIXME: where the DEBUG_INDEX name come from?
693 */
694 #define MAC_DEBUG_INDEX 0x05e8
695 #define MAC_DEBUG_INDEX_XTAL FIELD32(0x80000000)
696
697 /*
698 * MAC Control/Status Registers(CSR).
699 * Some values are set in TU, whereas 1 TU == 1024 us.
700 */
701
702 /*
703 * MAC_CSR0: ASIC revision number.
704 * ASIC_REV: 0
705 * ASIC_VER: 2860 or 2870
706 */
707 #define MAC_CSR0 0x1000
708 #define MAC_CSR0_REVISION FIELD32(0x0000ffff)
709 #define MAC_CSR0_CHIPSET FIELD32(0xffff0000)
710
711 /*
712 * MAC_SYS_CTRL:
713 */
714 #define MAC_SYS_CTRL 0x1004
715 #define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
716 #define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
717 #define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
718 #define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
719 #define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
720 #define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
721 #define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
722 #define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
723
724 /*
725 * MAC_ADDR_DW0: STA MAC register 0
726 */
727 #define MAC_ADDR_DW0 0x1008
728 #define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
729 #define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
730 #define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
731 #define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
732
733 /*
734 * MAC_ADDR_DW1: STA MAC register 1
735 * UNICAST_TO_ME_MASK:
736 * Used to mask off bits from byte 5 of the MAC address
737 * to determine the UNICAST_TO_ME bit for RX frames.
738 * The full mask is complemented by BSS_ID_MASK:
739 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
740 */
741 #define MAC_ADDR_DW1 0x100c
742 #define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
743 #define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
744 #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
745
746 /*
747 * MAC_BSSID_DW0: BSSID register 0
748 */
749 #define MAC_BSSID_DW0 0x1010
750 #define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
751 #define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
752 #define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
753 #define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
754
755 /*
756 * MAC_BSSID_DW1: BSSID register 1
757 * BSS_ID_MASK:
758 * 0: 1-BSSID mode (BSS index = 0)
759 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
760 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
761 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
762 * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
763 * BSSID. This will make sure that those bits will be ignored
764 * when determining the MY_BSS of RX frames.
765 */
766 #define MAC_BSSID_DW1 0x1014
767 #define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
768 #define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
769 #define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
770 #define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
771
772 /*
773 * MAX_LEN_CFG: Maximum frame length register.
774 * MAX_MPDU: rt2860b max 16k bytes
775 * MAX_PSDU: Maximum PSDU length
776 * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
777 */
778 #define MAX_LEN_CFG 0x1018
779 #define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
780 #define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
781 #define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
782 #define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
783
784 /*
785 * BBP_CSR_CFG: BBP serial control register
786 * VALUE: Register value to program into BBP
787 * REG_NUM: Selected BBP register
788 * READ_CONTROL: 0 write BBP, 1 read BBP
789 * BUSY: ASIC is busy executing BBP commands
790 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
791 * BBP_RW_MODE: 0 serial, 1 parallel
792 */
793 #define BBP_CSR_CFG 0x101c
794 #define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
795 #define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
796 #define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
797 #define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
798 #define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
799 #define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
800
801 /*
802 * RF_CSR_CFG0: RF control register
803 * REGID_AND_VALUE: Register value to program into RF
804 * BITWIDTH: Selected RF register
805 * STANDBYMODE: 0 high when standby, 1 low when standby
806 * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
807 * BUSY: ASIC is busy executing RF commands
808 */
809 #define RF_CSR_CFG0 0x1020
810 #define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
811 #define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
812 #define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
813 #define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
814 #define RF_CSR_CFG0_SEL FIELD32(0x40000000)
815 #define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
816
817 /*
818 * RF_CSR_CFG1: RF control register
819 * REGID_AND_VALUE: Register value to program into RF
820 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
821 * 0: 3 system clock cycle (37.5usec)
822 * 1: 5 system clock cycle (62.5usec)
823 */
824 #define RF_CSR_CFG1 0x1024
825 #define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
826 #define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
827
828 /*
829 * RF_CSR_CFG2: RF control register
830 * VALUE: Register value to program into RF
831 */
832 #define RF_CSR_CFG2 0x1028
833 #define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
834
835 /*
836 * LED_CFG: LED control
837 * ON_PERIOD: LED active time (ms) during TX (only used for LED mode 1)
838 * OFF_PERIOD: LED inactive time (ms) during TX (only used for LED mode 1)
839 * SLOW_BLINK_PERIOD: LED blink interval in seconds (only used for LED mode 2)
840 * color LED's:
841 * 0: off
842 * 1: blinking upon TX2
843 * 2: periodic slow blinking
844 * 3: always on
845 * LED polarity:
846 * 0: active low
847 * 1: active high
848 */
849 #define LED_CFG 0x102c
850 #define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
851 #define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
852 #define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
853 #define LED_CFG_R_LED_MODE FIELD32(0x03000000)
854 #define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
855 #define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
856 #define LED_CFG_LED_POLAR FIELD32(0x40000000)
857
858 /*
859 * AMPDU_BA_WINSIZE: Force BlockAck window size
860 * FORCE_WINSIZE_ENABLE:
861 * 0: Disable forcing of BlockAck window size
862 * 1: Enable forcing of BlockAck window size, overwrites values BlockAck
863 * window size values in the TXWI
864 * FORCE_WINSIZE: BlockAck window size
865 */
866 #define AMPDU_BA_WINSIZE 0x1040
867 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE FIELD32(0x00000020)
868 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE FIELD32(0x0000001f)
869
870 /*
871 * XIFS_TIME_CFG: MAC timing
872 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
873 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
874 * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
875 * when MAC doesn't reference BBP signal BBRXEND
876 * EIFS: unit 1us
877 * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
878 *
879 */
880 #define XIFS_TIME_CFG 0x1100
881 #define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
882 #define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
883 #define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
884 #define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
885 #define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
886
887 /*
888 * BKOFF_SLOT_CFG:
889 */
890 #define BKOFF_SLOT_CFG 0x1104
891 #define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
892 #define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
893
894 /*
895 * NAV_TIME_CFG:
896 */
897 #define NAV_TIME_CFG 0x1108
898 #define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
899 #define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
900 #define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
901 #define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
902
903 /*
904 * CH_TIME_CFG: count as channel busy
905 * EIFS_BUSY: Count EIFS as channel busy
906 * NAV_BUSY: Count NAS as channel busy
907 * RX_BUSY: Count RX as channel busy
908 * TX_BUSY: Count TX as channel busy
909 * TMR_EN: Enable channel statistics timer
910 */
911 #define CH_TIME_CFG 0x110c
912 #define CH_TIME_CFG_EIFS_BUSY FIELD32(0x00000010)
913 #define CH_TIME_CFG_NAV_BUSY FIELD32(0x00000008)
914 #define CH_TIME_CFG_RX_BUSY FIELD32(0x00000004)
915 #define CH_TIME_CFG_TX_BUSY FIELD32(0x00000002)
916 #define CH_TIME_CFG_TMR_EN FIELD32(0x00000001)
917
918 /*
919 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
920 */
921 #define PBF_LIFE_TIMER 0x1110
922
923 /*
924 * BCN_TIME_CFG:
925 * BEACON_INTERVAL: in unit of 1/16 TU
926 * TSF_TICKING: Enable TSF auto counting
927 * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
928 * BEACON_GEN: Enable beacon generator
929 */
930 #define BCN_TIME_CFG 0x1114
931 #define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
932 #define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
933 #define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
934 #define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
935 #define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
936 #define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
937
938 /*
939 * TBTT_SYNC_CFG:
940 * BCN_AIFSN: Beacon AIFSN after TBTT interrupt in slots
941 * BCN_CWMIN: Beacon CWMin after TBTT interrupt in slots
942 */
943 #define TBTT_SYNC_CFG 0x1118
944 #define TBTT_SYNC_CFG_TBTT_ADJUST FIELD32(0x000000ff)
945 #define TBTT_SYNC_CFG_BCN_EXP_WIN FIELD32(0x0000ff00)
946 #define TBTT_SYNC_CFG_BCN_AIFSN FIELD32(0x000f0000)
947 #define TBTT_SYNC_CFG_BCN_CWMIN FIELD32(0x00f00000)
948
949 /*
950 * TSF_TIMER_DW0: Local lsb TSF timer, read-only
951 */
952 #define TSF_TIMER_DW0 0x111c
953 #define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
954
955 /*
956 * TSF_TIMER_DW1: Local msb TSF timer, read-only
957 */
958 #define TSF_TIMER_DW1 0x1120
959 #define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
960
961 /*
962 * TBTT_TIMER: TImer remains till next TBTT, read-only
963 */
964 #define TBTT_TIMER 0x1124
965
966 /*
967 * INT_TIMER_CFG: timer configuration
968 * PRE_TBTT_TIMER: leadtime to tbtt for pretbtt interrupt in units of 1/16 TU
969 * GP_TIMER: period of general purpose timer in units of 1/16 TU
970 */
971 #define INT_TIMER_CFG 0x1128
972 #define INT_TIMER_CFG_PRE_TBTT_TIMER FIELD32(0x0000ffff)
973 #define INT_TIMER_CFG_GP_TIMER FIELD32(0xffff0000)
974
975 /*
976 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
977 */
978 #define INT_TIMER_EN 0x112c
979 #define INT_TIMER_EN_PRE_TBTT_TIMER FIELD32(0x00000001)
980 #define INT_TIMER_EN_GP_TIMER FIELD32(0x00000002)
981
982 /*
983 * CH_IDLE_STA: channel idle time (in us)
984 */
985 #define CH_IDLE_STA 0x1130
986
987 /*
988 * CH_BUSY_STA: channel busy time on primary channel (in us)
989 */
990 #define CH_BUSY_STA 0x1134
991
992 /*
993 * CH_BUSY_STA_SEC: channel busy time on secondary channel in HT40 mode (in us)
994 */
995 #define CH_BUSY_STA_SEC 0x1138
996
997 /*
998 * MAC_STATUS_CFG:
999 * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
1000 * if 1 or higher one of the 2 registers is busy.
1001 */
1002 #define MAC_STATUS_CFG 0x1200
1003 #define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
1004
1005 /*
1006 * PWR_PIN_CFG:
1007 */
1008 #define PWR_PIN_CFG 0x1204
1009
1010 /*
1011 * AUTOWAKEUP_CFG: Manual power control / status register
1012 * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
1013 * AUTOWAKE: 0:sleep, 1:awake
1014 */
1015 #define AUTOWAKEUP_CFG 0x1208
1016 #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
1017 #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
1018 #define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
1019
1020 /*
1021 * EDCA_AC0_CFG:
1022 */
1023 #define EDCA_AC0_CFG 0x1300
1024 #define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
1025 #define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
1026 #define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
1027 #define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
1028
1029 /*
1030 * EDCA_AC1_CFG:
1031 */
1032 #define EDCA_AC1_CFG 0x1304
1033 #define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
1034 #define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
1035 #define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
1036 #define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
1037
1038 /*
1039 * EDCA_AC2_CFG:
1040 */
1041 #define EDCA_AC2_CFG 0x1308
1042 #define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
1043 #define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
1044 #define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
1045 #define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
1046
1047 /*
1048 * EDCA_AC3_CFG:
1049 */
1050 #define EDCA_AC3_CFG 0x130c
1051 #define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
1052 #define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
1053 #define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
1054 #define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
1055
1056 /*
1057 * EDCA_TID_AC_MAP:
1058 */
1059 #define EDCA_TID_AC_MAP 0x1310
1060
1061 /*
1062 * TX_PWR_CFG:
1063 */
1064 #define TX_PWR_CFG_RATE0 FIELD32(0x0000000f)
1065 #define TX_PWR_CFG_RATE1 FIELD32(0x000000f0)
1066 #define TX_PWR_CFG_RATE2 FIELD32(0x00000f00)
1067 #define TX_PWR_CFG_RATE3 FIELD32(0x0000f000)
1068 #define TX_PWR_CFG_RATE4 FIELD32(0x000f0000)
1069 #define TX_PWR_CFG_RATE5 FIELD32(0x00f00000)
1070 #define TX_PWR_CFG_RATE6 FIELD32(0x0f000000)
1071 #define TX_PWR_CFG_RATE7 FIELD32(0xf0000000)
1072
1073 /*
1074 * TX_PWR_CFG_0:
1075 */
1076 #define TX_PWR_CFG_0 0x1314
1077 #define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
1078 #define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
1079 #define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
1080 #define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
1081 #define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
1082 #define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
1083 #define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
1084 #define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
1085
1086 /*
1087 * TX_PWR_CFG_1:
1088 */
1089 #define TX_PWR_CFG_1 0x1318
1090 #define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
1091 #define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
1092 #define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
1093 #define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
1094 #define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
1095 #define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
1096 #define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
1097 #define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
1098
1099 /*
1100 * TX_PWR_CFG_2:
1101 */
1102 #define TX_PWR_CFG_2 0x131c
1103 #define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
1104 #define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
1105 #define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
1106 #define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
1107 #define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
1108 #define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
1109 #define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
1110 #define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
1111
1112 /*
1113 * TX_PWR_CFG_3:
1114 */
1115 #define TX_PWR_CFG_3 0x1320
1116 #define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
1117 #define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
1118 #define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
1119 #define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
1120 #define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
1121 #define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
1122 #define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
1123 #define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
1124
1125 /*
1126 * TX_PWR_CFG_4:
1127 */
1128 #define TX_PWR_CFG_4 0x1324
1129 #define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
1130 #define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
1131 #define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
1132 #define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
1133
1134 /*
1135 * TX_PIN_CFG:
1136 */
1137 #define TX_PIN_CFG 0x1328
1138 #define TX_PIN_CFG_PA_PE_DISABLE 0xfcfffff0
1139 #define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
1140 #define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
1141 #define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
1142 #define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
1143 #define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
1144 #define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
1145 #define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
1146 #define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
1147 #define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
1148 #define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
1149 #define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
1150 #define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
1151 #define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
1152 #define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
1153 #define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
1154 #define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
1155 #define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
1156 #define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
1157 #define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
1158 #define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
1159 #define TX_PIN_CFG_PA_PE_A2_EN FIELD32(0x01000000)
1160 #define TX_PIN_CFG_PA_PE_G2_EN FIELD32(0x02000000)
1161 #define TX_PIN_CFG_PA_PE_A2_POL FIELD32(0x04000000)
1162 #define TX_PIN_CFG_PA_PE_G2_POL FIELD32(0x08000000)
1163 #define TX_PIN_CFG_LNA_PE_A2_EN FIELD32(0x10000000)
1164 #define TX_PIN_CFG_LNA_PE_G2_EN FIELD32(0x20000000)
1165 #define TX_PIN_CFG_LNA_PE_A2_POL FIELD32(0x40000000)
1166 #define TX_PIN_CFG_LNA_PE_G2_POL FIELD32(0x80000000)
1167
1168 /*
1169 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
1170 */
1171 #define TX_BAND_CFG 0x132c
1172 #define TX_BAND_CFG_HT40_MINUS FIELD32(0x00000001)
1173 #define TX_BAND_CFG_A FIELD32(0x00000002)
1174 #define TX_BAND_CFG_BG FIELD32(0x00000004)
1175
1176 /*
1177 * TX_SW_CFG0:
1178 */
1179 #define TX_SW_CFG0 0x1330
1180
1181 /*
1182 * TX_SW_CFG1:
1183 */
1184 #define TX_SW_CFG1 0x1334
1185
1186 /*
1187 * TX_SW_CFG2:
1188 */
1189 #define TX_SW_CFG2 0x1338
1190
1191 /*
1192 * TXOP_THRES_CFG:
1193 */
1194 #define TXOP_THRES_CFG 0x133c
1195
1196 /*
1197 * TXOP_CTRL_CFG:
1198 * TIMEOUT_TRUN_EN: Enable/Disable TXOP timeout truncation
1199 * AC_TRUN_EN: Enable/Disable truncation for AC change
1200 * TXRATEGRP_TRUN_EN: Enable/Disable truncation for TX rate group change
1201 * USER_MODE_TRUN_EN: Enable/Disable truncation for user TXOP mode
1202 * MIMO_PS_TRUN_EN: Enable/Disable truncation for MIMO PS RTS/CTS
1203 * RESERVED_TRUN_EN: Reserved
1204 * LSIG_TXOP_EN: Enable/Disable L-SIG TXOP protection
1205 * EXT_CCA_EN: Enable/Disable extension channel CCA reference (Defer 40Mhz
1206 * transmissions if extension CCA is clear).
1207 * EXT_CCA_DLY: Extension CCA signal delay time (unit: us)
1208 * EXT_CWMIN: CwMin for extension channel backoff
1209 * 0: Disabled
1210 *
1211 */
1212 #define TXOP_CTRL_CFG 0x1340
1213 #define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN FIELD32(0x00000001)
1214 #define TXOP_CTRL_CFG_AC_TRUN_EN FIELD32(0x00000002)
1215 #define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN FIELD32(0x00000004)
1216 #define TXOP_CTRL_CFG_USER_MODE_TRUN_EN FIELD32(0x00000008)
1217 #define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN FIELD32(0x00000010)
1218 #define TXOP_CTRL_CFG_RESERVED_TRUN_EN FIELD32(0x00000020)
1219 #define TXOP_CTRL_CFG_LSIG_TXOP_EN FIELD32(0x00000040)
1220 #define TXOP_CTRL_CFG_EXT_CCA_EN FIELD32(0x00000080)
1221 #define TXOP_CTRL_CFG_EXT_CCA_DLY FIELD32(0x0000ff00)
1222 #define TXOP_CTRL_CFG_EXT_CWMIN FIELD32(0x000f0000)
1223
1224 /*
1225 * TX_RTS_CFG:
1226 * RTS_THRES: unit:byte
1227 * RTS_FBK_EN: enable rts rate fallback
1228 */
1229 #define TX_RTS_CFG 0x1344
1230 #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
1231 #define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
1232 #define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
1233
1234 /*
1235 * TX_TIMEOUT_CFG:
1236 * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
1237 * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
1238 * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
1239 * it is recommended that:
1240 * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
1241 */
1242 #define TX_TIMEOUT_CFG 0x1348
1243 #define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
1244 #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
1245 #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
1246
1247 /*
1248 * TX_RTY_CFG:
1249 * SHORT_RTY_LIMIT: short retry limit
1250 * LONG_RTY_LIMIT: long retry limit
1251 * LONG_RTY_THRE: Long retry threshoold
1252 * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
1253 * 0:expired by retry limit, 1: expired by mpdu life timer
1254 * AGG_RTY_MODE: Aggregate MPDU retry mode
1255 * 0:expired by retry limit, 1: expired by mpdu life timer
1256 * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
1257 */
1258 #define TX_RTY_CFG 0x134c
1259 #define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
1260 #define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
1261 #define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
1262 #define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
1263 #define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
1264 #define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
1265
1266 /*
1267 * TX_LINK_CFG:
1268 * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
1269 * MFB_ENABLE: TX apply remote MFB 1:enable
1270 * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
1271 * 0: not apply remote remote unsolicit (MFS=7)
1272 * TX_MRQ_EN: MCS request TX enable
1273 * TX_RDG_EN: RDG TX enable
1274 * TX_CF_ACK_EN: Piggyback CF-ACK enable
1275 * REMOTE_MFB: remote MCS feedback
1276 * REMOTE_MFS: remote MCS feedback sequence number
1277 */
1278 #define TX_LINK_CFG 0x1350
1279 #define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
1280 #define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
1281 #define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
1282 #define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
1283 #define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
1284 #define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
1285 #define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
1286 #define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
1287
1288 /*
1289 * HT_FBK_CFG0:
1290 */
1291 #define HT_FBK_CFG0 0x1354
1292 #define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
1293 #define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
1294 #define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
1295 #define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
1296 #define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
1297 #define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
1298 #define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
1299 #define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
1300
1301 /*
1302 * HT_FBK_CFG1:
1303 */
1304 #define HT_FBK_CFG1 0x1358
1305 #define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
1306 #define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
1307 #define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
1308 #define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
1309 #define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
1310 #define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
1311 #define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
1312 #define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
1313
1314 /*
1315 * LG_FBK_CFG0:
1316 */
1317 #define LG_FBK_CFG0 0x135c
1318 #define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
1319 #define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
1320 #define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
1321 #define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
1322 #define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
1323 #define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
1324 #define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
1325 #define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
1326
1327 /*
1328 * LG_FBK_CFG1:
1329 */
1330 #define LG_FBK_CFG1 0x1360
1331 #define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
1332 #define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
1333 #define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
1334 #define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
1335
1336 /*
1337 * CCK_PROT_CFG: CCK Protection
1338 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
1339 * PROTECT_CTRL: Protection control frame type for CCK TX
1340 * 0:none, 1:RTS/CTS, 2:CTS-to-self
1341 * PROTECT_NAV_SHORT: TXOP protection type for CCK TX with short NAV
1342 * PROTECT_NAV_LONG: TXOP protection type for CCK TX with long NAV
1343 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
1344 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
1345 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
1346 * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
1347 * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
1348 * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
1349 * RTS_TH_EN: RTS threshold enable on CCK TX
1350 */
1351 #define CCK_PROT_CFG 0x1364
1352 #define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1353 #define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1354 #define CCK_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1355 #define CCK_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1356 #define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1357 #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1358 #define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1359 #define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1360 #define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1361 #define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1362 #define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1363
1364 /*
1365 * OFDM_PROT_CFG: OFDM Protection
1366 */
1367 #define OFDM_PROT_CFG 0x1368
1368 #define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1369 #define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1370 #define OFDM_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1371 #define OFDM_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1372 #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1373 #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1374 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1375 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1376 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1377 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1378 #define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1379
1380 /*
1381 * MM20_PROT_CFG: MM20 Protection
1382 */
1383 #define MM20_PROT_CFG 0x136c
1384 #define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1385 #define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1386 #define MM20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1387 #define MM20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1388 #define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1389 #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1390 #define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1391 #define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1392 #define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1393 #define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1394 #define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1395
1396 /*
1397 * MM40_PROT_CFG: MM40 Protection
1398 */
1399 #define MM40_PROT_CFG 0x1370
1400 #define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1401 #define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1402 #define MM40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1403 #define MM40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1404 #define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1405 #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1406 #define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1407 #define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1408 #define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1409 #define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1410 #define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1411
1412 /*
1413 * GF20_PROT_CFG: GF20 Protection
1414 */
1415 #define GF20_PROT_CFG 0x1374
1416 #define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1417 #define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1418 #define GF20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1419 #define GF20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1420 #define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1421 #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1422 #define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1423 #define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1424 #define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1425 #define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1426 #define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1427
1428 /*
1429 * GF40_PROT_CFG: GF40 Protection
1430 */
1431 #define GF40_PROT_CFG 0x1378
1432 #define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1433 #define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1434 #define GF40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1435 #define GF40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1436 #define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1437 #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1438 #define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1439 #define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1440 #define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1441 #define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1442 #define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1443
1444 /*
1445 * EXP_CTS_TIME:
1446 */
1447 #define EXP_CTS_TIME 0x137c
1448
1449 /*
1450 * EXP_ACK_TIME:
1451 */
1452 #define EXP_ACK_TIME 0x1380
1453
1454 /*
1455 * RX_FILTER_CFG: RX configuration register.
1456 */
1457 #define RX_FILTER_CFG 0x1400
1458 #define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1459 #define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1460 #define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1461 #define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1462 #define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1463 #define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1464 #define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1465 #define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1466 #define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1467 #define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1468 #define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1469 #define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1470 #define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1471 #define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1472 #define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1473 #define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1474 #define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1475
1476 /*
1477 * AUTO_RSP_CFG:
1478 * AUTORESPONDER: 0: disable, 1: enable
1479 * BAC_ACK_POLICY: 0:long, 1:short preamble
1480 * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1481 * CTS_40_MREF: Response CTS 40MHz duplicate mode
1482 * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1483 * DUAL_CTS_EN: Power bit value in control frame
1484 * ACK_CTS_PSM_BIT:Power bit value in control frame
1485 */
1486 #define AUTO_RSP_CFG 0x1404
1487 #define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1488 #define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1489 #define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1490 #define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1491 #define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1492 #define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1493 #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1494
1495 /*
1496 * LEGACY_BASIC_RATE:
1497 */
1498 #define LEGACY_BASIC_RATE 0x1408
1499
1500 /*
1501 * HT_BASIC_RATE:
1502 */
1503 #define HT_BASIC_RATE 0x140c
1504
1505 /*
1506 * HT_CTRL_CFG:
1507 */
1508 #define HT_CTRL_CFG 0x1410
1509
1510 /*
1511 * SIFS_COST_CFG:
1512 */
1513 #define SIFS_COST_CFG 0x1414
1514
1515 /*
1516 * RX_PARSER_CFG:
1517 * Set NAV for all received frames
1518 */
1519 #define RX_PARSER_CFG 0x1418
1520
1521 /*
1522 * TX_SEC_CNT0:
1523 */
1524 #define TX_SEC_CNT0 0x1500
1525
1526 /*
1527 * RX_SEC_CNT0:
1528 */
1529 #define RX_SEC_CNT0 0x1504
1530
1531 /*
1532 * CCMP_FC_MUTE:
1533 */
1534 #define CCMP_FC_MUTE 0x1508
1535
1536 /*
1537 * TXOP_HLDR_ADDR0:
1538 */
1539 #define TXOP_HLDR_ADDR0 0x1600
1540
1541 /*
1542 * TXOP_HLDR_ADDR1:
1543 */
1544 #define TXOP_HLDR_ADDR1 0x1604
1545
1546 /*
1547 * TXOP_HLDR_ET:
1548 */
1549 #define TXOP_HLDR_ET 0x1608
1550
1551 /*
1552 * QOS_CFPOLL_RA_DW0:
1553 */
1554 #define QOS_CFPOLL_RA_DW0 0x160c
1555
1556 /*
1557 * QOS_CFPOLL_RA_DW1:
1558 */
1559 #define QOS_CFPOLL_RA_DW1 0x1610
1560
1561 /*
1562 * QOS_CFPOLL_QC:
1563 */
1564 #define QOS_CFPOLL_QC 0x1614
1565
1566 /*
1567 * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1568 */
1569 #define RX_STA_CNT0 0x1700
1570 #define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1571 #define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1572
1573 /*
1574 * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1575 */
1576 #define RX_STA_CNT1 0x1704
1577 #define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1578 #define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1579
1580 /*
1581 * RX_STA_CNT2:
1582 */
1583 #define RX_STA_CNT2 0x1708
1584 #define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1585 #define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1586
1587 /*
1588 * TX_STA_CNT0: TX Beacon count
1589 */
1590 #define TX_STA_CNT0 0x170c
1591 #define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1592 #define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1593
1594 /*
1595 * TX_STA_CNT1: TX tx count
1596 */
1597 #define TX_STA_CNT1 0x1710
1598 #define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1599 #define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1600
1601 /*
1602 * TX_STA_CNT2: TX tx count
1603 */
1604 #define TX_STA_CNT2 0x1714
1605 #define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1606 #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1607
1608 /*
1609 * TX_STA_FIFO: TX Result for specific PID status fifo register.
1610 *
1611 * This register is implemented as FIFO with 16 entries in the HW. Each
1612 * register read fetches the next tx result. If the FIFO is full because
1613 * it wasn't read fast enough after the according interrupt (TX_FIFO_STATUS)
1614 * triggered, the hw seems to simply drop further tx results.
1615 *
1616 * VALID: 1: this tx result is valid
1617 * 0: no valid tx result -> driver should stop reading
1618 * PID_TYPE: The PID latched from the PID field in the TXWI, can be used
1619 * to match a frame with its tx result (even though the PID is
1620 * only 4 bits wide).
1621 * PID_QUEUE: Part of PID_TYPE, this is the queue index number (0-3)
1622 * PID_ENTRY: Part of PID_TYPE, this is the queue entry index number (1-3)
1623 * This identification number is calculated by ((idx % 3) + 1).
1624 * TX_SUCCESS: Indicates tx success (1) or failure (0)
1625 * TX_AGGRE: Indicates if the frame was part of an aggregate (1) or not (0)
1626 * TX_ACK_REQUIRED: Indicates if the frame needed to get ack'ed (1) or not (0)
1627 * WCID: The wireless client ID.
1628 * MCS: The tx rate used during the last transmission of this frame, be it
1629 * successful or not.
1630 * PHYMODE: The phymode used for the transmission.
1631 */
1632 #define TX_STA_FIFO 0x1718
1633 #define TX_STA_FIFO_VALID FIELD32(0x00000001)
1634 #define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1635 #define TX_STA_FIFO_PID_QUEUE FIELD32(0x00000006)
1636 #define TX_STA_FIFO_PID_ENTRY FIELD32(0x00000018)
1637 #define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1638 #define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1639 #define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1640 #define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1641 #define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
1642 #define TX_STA_FIFO_MCS FIELD32(0x007f0000)
1643 #define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000)
1644
1645 /*
1646 * TX_AGG_CNT: Debug counter
1647 */
1648 #define TX_AGG_CNT 0x171c
1649 #define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1650 #define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1651
1652 /*
1653 * TX_AGG_CNT0:
1654 */
1655 #define TX_AGG_CNT0 0x1720
1656 #define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1657 #define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1658
1659 /*
1660 * TX_AGG_CNT1:
1661 */
1662 #define TX_AGG_CNT1 0x1724
1663 #define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1664 #define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1665
1666 /*
1667 * TX_AGG_CNT2:
1668 */
1669 #define TX_AGG_CNT2 0x1728
1670 #define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1671 #define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1672
1673 /*
1674 * TX_AGG_CNT3:
1675 */
1676 #define TX_AGG_CNT3 0x172c
1677 #define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1678 #define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1679
1680 /*
1681 * TX_AGG_CNT4:
1682 */
1683 #define TX_AGG_CNT4 0x1730
1684 #define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1685 #define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1686
1687 /*
1688 * TX_AGG_CNT5:
1689 */
1690 #define TX_AGG_CNT5 0x1734
1691 #define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1692 #define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1693
1694 /*
1695 * TX_AGG_CNT6:
1696 */
1697 #define TX_AGG_CNT6 0x1738
1698 #define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1699 #define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1700
1701 /*
1702 * TX_AGG_CNT7:
1703 */
1704 #define TX_AGG_CNT7 0x173c
1705 #define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1706 #define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1707
1708 /*
1709 * MPDU_DENSITY_CNT:
1710 * TX_ZERO_DEL: TX zero length delimiter count
1711 * RX_ZERO_DEL: RX zero length delimiter count
1712 */
1713 #define MPDU_DENSITY_CNT 0x1740
1714 #define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1715 #define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1716
1717 /*
1718 * Security key table memory.
1719 *
1720 * The pairwise key table shares some memory with the beacon frame
1721 * buffers 6 and 7. That basically means that when beacon 6 & 7
1722 * are used we should only use the reduced pairwise key table which
1723 * has a maximum of 222 entries.
1724 *
1725 * ---------------------------------------------
1726 * |0x4000 | Pairwise Key | Reduced Pairwise |
1727 * | | Table | Key Table |
1728 * | | Size: 256 * 32 | Size: 222 * 32 |
1729 * |0x5BC0 | |-------------------
1730 * | | | Beacon 6 |
1731 * |0x5DC0 | |-------------------
1732 * | | | Beacon 7 |
1733 * |0x5FC0 | |-------------------
1734 * |0x5FFF | |
1735 * --------------------------
1736 *
1737 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1738 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1739 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
1740 * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
1741 * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
1742 * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
1743 */
1744 #define MAC_WCID_BASE 0x1800
1745 #define PAIRWISE_KEY_TABLE_BASE 0x4000
1746 #define MAC_IVEIV_TABLE_BASE 0x6000
1747 #define MAC_WCID_ATTRIBUTE_BASE 0x6800
1748 #define SHARED_KEY_TABLE_BASE 0x6c00
1749 #define SHARED_KEY_MODE_BASE 0x7000
1750
1751 #define MAC_WCID_ENTRY(__idx) \
1752 (MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)))
1753 #define PAIRWISE_KEY_ENTRY(__idx) \
1754 (PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
1755 #define MAC_IVEIV_ENTRY(__idx) \
1756 (MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)))
1757 #define MAC_WCID_ATTR_ENTRY(__idx) \
1758 (MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)))
1759 #define SHARED_KEY_ENTRY(__idx) \
1760 (SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
1761 #define SHARED_KEY_MODE_ENTRY(__idx) \
1762 (SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)))
1763
1764 struct mac_wcid_entry {
1765 u8 mac[6];
1766 u8 reserved[2];
1767 } __packed;
1768
1769 struct hw_key_entry {
1770 u8 key[16];
1771 u8 tx_mic[8];
1772 u8 rx_mic[8];
1773 } __packed;
1774
1775 struct mac_iveiv_entry {
1776 u8 iv[8];
1777 } __packed;
1778
1779 /*
1780 * MAC_WCID_ATTRIBUTE:
1781 */
1782 #define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
1783 #define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
1784 #define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
1785 #define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
1786 #define MAC_WCID_ATTRIBUTE_CIPHER_EXT FIELD32(0x00000400)
1787 #define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT FIELD32(0x00000800)
1788 #define MAC_WCID_ATTRIBUTE_WAPI_MCBC FIELD32(0x00008000)
1789 #define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000)
1790
1791 /*
1792 * SHARED_KEY_MODE:
1793 */
1794 #define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
1795 #define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
1796 #define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
1797 #define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
1798 #define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
1799 #define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
1800 #define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
1801 #define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
1802
1803 /*
1804 * HOST-MCU communication
1805 */
1806
1807 /*
1808 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
1809 * CMD_TOKEN: Command id, 0xff disable status reporting.
1810 */
1811 #define H2M_MAILBOX_CSR 0x7010
1812 #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
1813 #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
1814 #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
1815 #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
1816
1817 /*
1818 * H2M_MAILBOX_CID:
1819 * Free slots contain 0xff. MCU will store command's token to lowest free slot.
1820 * If all slots are occupied status will be dropped.
1821 */
1822 #define H2M_MAILBOX_CID 0x7014
1823 #define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
1824 #define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
1825 #define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
1826 #define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
1827
1828 /*
1829 * H2M_MAILBOX_STATUS:
1830 * Command status will be saved to same slot as command id.
1831 */
1832 #define H2M_MAILBOX_STATUS 0x701c
1833
1834 /*
1835 * H2M_INT_SRC:
1836 */
1837 #define H2M_INT_SRC 0x7024
1838
1839 /*
1840 * H2M_BBP_AGENT:
1841 */
1842 #define H2M_BBP_AGENT 0x7028
1843
1844 /*
1845 * MCU_LEDCS: LED control for MCU Mailbox.
1846 */
1847 #define MCU_LEDCS_LED_MODE FIELD8(0x1f)
1848 #define MCU_LEDCS_POLARITY FIELD8(0x01)
1849
1850 /*
1851 * HW_CS_CTS_BASE:
1852 * Carrier-sense CTS frame base address.
1853 * It's where mac stores carrier-sense frame for carrier-sense function.
1854 */
1855 #define HW_CS_CTS_BASE 0x7700
1856
1857 /*
1858 * HW_DFS_CTS_BASE:
1859 * DFS CTS frame base address. It's where mac stores CTS frame for DFS.
1860 */
1861 #define HW_DFS_CTS_BASE 0x7780
1862
1863 /*
1864 * TXRX control registers - base address 0x3000
1865 */
1866
1867 /*
1868 * TXRX_CSR1:
1869 * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1870 */
1871 #define TXRX_CSR1 0x77d0
1872
1873 /*
1874 * HW_DEBUG_SETTING_BASE:
1875 * since NULL frame won't be that long (256 byte)
1876 * We steal 16 tail bytes to save debugging settings
1877 */
1878 #define HW_DEBUG_SETTING_BASE 0x77f0
1879 #define HW_DEBUG_SETTING_BASE2 0x7770
1880
1881 /*
1882 * HW_BEACON_BASE
1883 * In order to support maximum 8 MBSS and its maximum length
1884 * is 512 bytes for each beacon
1885 * Three section discontinue memory segments will be used.
1886 * 1. The original region for BCN 0~3
1887 * 2. Extract memory from FCE table for BCN 4~5
1888 * 3. Extract memory from Pair-wise key table for BCN 6~7
1889 * It occupied those memory of wcid 238~253 for BCN 6
1890 * and wcid 222~237 for BCN 7 (see Security key table memory
1891 * for more info).
1892 *
1893 * IMPORTANT NOTE: Not sure why legacy driver does this,
1894 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
1895 */
1896 #define HW_BEACON_BASE0 0x7800
1897 #define HW_BEACON_BASE1 0x7a00
1898 #define HW_BEACON_BASE2 0x7c00
1899 #define HW_BEACON_BASE3 0x7e00
1900 #define HW_BEACON_BASE4 0x7200
1901 #define HW_BEACON_BASE5 0x7400
1902 #define HW_BEACON_BASE6 0x5dc0
1903 #define HW_BEACON_BASE7 0x5bc0
1904
1905 #define HW_BEACON_OFFSET(__index) \
1906 (((__index) < 4) ? (HW_BEACON_BASE0 + (__index * 0x0200)) : \
1907 (((__index) < 6) ? (HW_BEACON_BASE4 + ((__index - 4) * 0x0200)) : \
1908 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))))
1909
1910 /*
1911 * BBP registers.
1912 * The wordsize of the BBP is 8 bits.
1913 */
1914
1915 /*
1916 * BBP 1: TX Antenna & Power Control
1917 * POWER_CTRL:
1918 * 0 - normal,
1919 * 1 - drop tx power by 6dBm,
1920 * 2 - drop tx power by 12dBm,
1921 * 3 - increase tx power by 6dBm
1922 */
1923 #define BBP1_TX_POWER_CTRL FIELD8(0x07)
1924 #define BBP1_TX_ANTENNA FIELD8(0x18)
1925
1926 /*
1927 * BBP 3: RX Antenna
1928 */
1929 #define BBP3_RX_ADC FIELD8(0x03)
1930 #define BBP3_RX_ANTENNA FIELD8(0x18)
1931 #define BBP3_HT40_MINUS FIELD8(0x20)
1932 #define BBP3_ADC_MODE_SWITCH FIELD8(0x40)
1933 #define BBP3_ADC_INIT_MODE FIELD8(0x80)
1934
1935 /*
1936 * BBP 4: Bandwidth
1937 */
1938 #define BBP4_TX_BF FIELD8(0x01)
1939 #define BBP4_BANDWIDTH FIELD8(0x18)
1940 #define BBP4_MAC_IF_CTRL FIELD8(0x40)
1941
1942 /* BBP27 */
1943 #define BBP27_RX_CHAIN_SEL FIELD8(0x60)
1944
1945 /*
1946 * BBP 47: Bandwidth
1947 */
1948 #define BBP47_TSSI_REPORT_SEL FIELD8(0x03)
1949 #define BBP47_TSSI_UPDATE_REQ FIELD8(0x04)
1950 #define BBP47_TSSI_TSSI_MODE FIELD8(0x18)
1951 #define BBP47_TSSI_ADC6 FIELD8(0x80)
1952
1953 /*
1954 * BBP 49
1955 */
1956 #define BBP49_UPDATE_FLAG FIELD8(0x01)
1957
1958 /*
1959 * BBP 105:
1960 * - bit0: detect SIG on primary channel only (on 40MHz bandwidth)
1961 * - bit1: FEQ (Feed Forward Compensation) for independend streams
1962 * - bit2: MLD (Maximum Likehood Detection) for 2 streams (reserved on single
1963 * stream)
1964 * - bit4: channel estimation updates based on remodulation of
1965 * L-SIG and HT-SIG symbols
1966 */
1967 #define BBP105_DETECT_SIG_ON_PRIMARY FIELD8(0x01)
1968 #define BBP105_FEQ FIELD8(0x02)
1969 #define BBP105_MLD FIELD8(0x04)
1970 #define BBP105_SIG_REMODULATION FIELD8(0x08)
1971
1972 /*
1973 * BBP 109
1974 */
1975 #define BBP109_TX0_POWER FIELD8(0x0f)
1976 #define BBP109_TX1_POWER FIELD8(0xf0)
1977
1978 /*
1979 * BBP 138: Unknown
1980 */
1981 #define BBP138_RX_ADC1 FIELD8(0x02)
1982 #define BBP138_RX_ADC2 FIELD8(0x04)
1983 #define BBP138_TX_DAC1 FIELD8(0x20)
1984 #define BBP138_TX_DAC2 FIELD8(0x40)
1985
1986 /*
1987 * BBP 152: Rx Ant
1988 */
1989 #define BBP152_RX_DEFAULT_ANT FIELD8(0x80)
1990
1991 /*
1992 * BBP 254: unknown
1993 */
1994 #define BBP254_BIT7 FIELD8(0x80)
1995
1996 /*
1997 * RFCSR registers
1998 * The wordsize of the RFCSR is 8 bits.
1999 */
2000
2001 /*
2002 * RFCSR 1:
2003 */
2004 #define RFCSR1_RF_BLOCK_EN FIELD8(0x01)
2005 #define RFCSR1_PLL_PD FIELD8(0x02)
2006 #define RFCSR1_RX0_PD FIELD8(0x04)
2007 #define RFCSR1_TX0_PD FIELD8(0x08)
2008 #define RFCSR1_RX1_PD FIELD8(0x10)
2009 #define RFCSR1_TX1_PD FIELD8(0x20)
2010 #define RFCSR1_RX2_PD FIELD8(0x40)
2011 #define RFCSR1_TX2_PD FIELD8(0x80)
2012
2013 /*
2014 * RFCSR 2:
2015 */
2016 #define RFCSR2_RESCAL_EN FIELD8(0x80)
2017
2018 /*
2019 * RFCSR 3:
2020 */
2021 #define RFCSR3_K FIELD8(0x0f)
2022 /* Bits [7-4] for RF3320 (RT3370/RT3390), on other chipsets reserved */
2023 #define RFCSR3_PA1_BIAS_CCK FIELD8(0x70)
2024 #define RFCSR3_PA2_CASCODE_BIAS_CCKK FIELD8(0x80)
2025 /* Bits for RF3290/RF5360/RF5370/RF5372/RF5390/RF5392 */
2026 #define RFCSR3_VCOCAL_EN FIELD8(0x80)
2027
2028 /*
2029 * FRCSR 5:
2030 */
2031 #define RFCSR5_R1 FIELD8(0x0c)
2032
2033 /*
2034 * RFCSR 6:
2035 */
2036 #define RFCSR6_R1 FIELD8(0x03)
2037 #define RFCSR6_R2 FIELD8(0x40)
2038 #define RFCSR6_TXDIV FIELD8(0x0c)
2039
2040 /*
2041 * RFCSR 7:
2042 */
2043 #define RFCSR7_RF_TUNING FIELD8(0x01)
2044 #define RFCSR7_BIT1 FIELD8(0x02)
2045 #define RFCSR7_BIT2 FIELD8(0x04)
2046 #define RFCSR7_BIT3 FIELD8(0x08)
2047 #define RFCSR7_BIT4 FIELD8(0x10)
2048 #define RFCSR7_BIT5 FIELD8(0x20)
2049 #define RFCSR7_BITS67 FIELD8(0xc0)
2050
2051 /*
2052 * RFCSR 9:
2053 */
2054 #define RFCSR9_K FIELD8(0x0f)
2055 #define RFCSR9_N FIELD8(0x10)
2056 #define RFCSR9_UNKNOWN FIELD8(0x60)
2057 #define RFCSR9_MOD FIELD8(0x80)
2058
2059 /*
2060 * RFCSR 11:
2061 */
2062 #define RFCSR11_R FIELD8(0x03)
2063 #define RFCSR11_MOD FIELD8(0xc0)
2064
2065 /*
2066 * RFCSR 12:
2067 */
2068 #define RFCSR12_TX_POWER FIELD8(0x1f)
2069 #define RFCSR12_DR0 FIELD8(0xe0)
2070
2071 /*
2072 * RFCSR 13:
2073 */
2074 #define RFCSR13_TX_POWER FIELD8(0x1f)
2075 #define RFCSR13_DR0 FIELD8(0xe0)
2076
2077 /*
2078 * RFCSR 15:
2079 */
2080 #define RFCSR15_TX_LO2_EN FIELD8(0x08)
2081
2082 /*
2083 * RFCSR 16:
2084 */
2085 #define RFCSR16_TXMIXER_GAIN FIELD8(0x07)
2086
2087 /*
2088 * RFCSR 17:
2089 */
2090 #define RFCSR17_TXMIXER_GAIN FIELD8(0x07)
2091 #define RFCSR17_TX_LO1_EN FIELD8(0x08)
2092 #define RFCSR17_R FIELD8(0x20)
2093 #define RFCSR17_CODE FIELD8(0x7f)
2094
2095 /*
2096 * RFCSR 20:
2097 */
2098 #define RFCSR20_RX_LO1_EN FIELD8(0x08)
2099
2100 /*
2101 * RFCSR 21:
2102 */
2103 #define RFCSR21_RX_LO2_EN FIELD8(0x08)
2104
2105 /*
2106 * RFCSR 22:
2107 */
2108 #define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
2109
2110 /*
2111 * RFCSR 23:
2112 */
2113 #define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
2114
2115 /*
2116 * RFCSR 24:
2117 */
2118 #define RFCSR24_TX_AGC_FC FIELD8(0x1f)
2119 #define RFCSR24_TX_H20M FIELD8(0x20)
2120 #define RFCSR24_TX_CALIB FIELD8(0x7f)
2121
2122 /*
2123 * RFCSR 27:
2124 */
2125 #define RFCSR27_R1 FIELD8(0x03)
2126 #define RFCSR27_R2 FIELD8(0x04)
2127 #define RFCSR27_R3 FIELD8(0x30)
2128 #define RFCSR27_R4 FIELD8(0x40)
2129
2130 /*
2131 * RFCSR 29:
2132 */
2133 #define RFCSR29_ADC6_TEST FIELD8(0x01)
2134 #define RFCSR29_ADC6_INT_TEST FIELD8(0x02)
2135 #define RFCSR29_RSSI_RESET FIELD8(0x04)
2136 #define RFCSR29_RSSI_ON FIELD8(0x08)
2137 #define RFCSR29_RSSI_RIP_CTRL FIELD8(0x30)
2138 #define RFCSR29_RSSI_GAIN FIELD8(0xc0)
2139
2140 /*
2141 * RFCSR 30:
2142 */
2143 #define RFCSR30_TX_H20M FIELD8(0x02)
2144 #define RFCSR30_RX_H20M FIELD8(0x04)
2145 #define RFCSR30_RX_VCM FIELD8(0x18)
2146 #define RFCSR30_RF_CALIBRATION FIELD8(0x80)
2147
2148 /*
2149 * RFCSR 31:
2150 */
2151 #define RFCSR31_RX_AGC_FC FIELD8(0x1f)
2152 #define RFCSR31_RX_H20M FIELD8(0x20)
2153 #define RFCSR31_RX_CALIB FIELD8(0x7f)
2154
2155 /*
2156 * RFCSR 38:
2157 */
2158 #define RFCSR38_RX_LO1_EN FIELD8(0x20)
2159
2160 /*
2161 * RFCSR 39:
2162 */
2163 #define RFCSR39_RX_LO2_EN FIELD8(0x80)
2164
2165 /*
2166 * RFCSR 49:
2167 */
2168 #define RFCSR49_TX FIELD8(0x3f)
2169 #define RFCSR49_EP FIELD8(0xc0)
2170
2171 /*
2172 * RFCSR 50:
2173 */
2174 #define RFCSR50_TX FIELD8(0x3f)
2175 #define RFCSR50_EP FIELD8(0xc0)
2176
2177 /*
2178 * RF registers
2179 */
2180
2181 /*
2182 * RF 2
2183 */
2184 #define RF2_ANTENNA_RX2 FIELD32(0x00000040)
2185 #define RF2_ANTENNA_TX1 FIELD32(0x00004000)
2186 #define RF2_ANTENNA_RX1 FIELD32(0x00020000)
2187
2188 /*
2189 * RF 3
2190 */
2191 #define RF3_TXPOWER_G FIELD32(0x00003e00)
2192 #define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
2193 #define RF3_TXPOWER_A FIELD32(0x00003c00)
2194
2195 /*
2196 * RF 4
2197 */
2198 #define RF4_TXPOWER_G FIELD32(0x000007c0)
2199 #define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
2200 #define RF4_TXPOWER_A FIELD32(0x00000780)
2201 #define RF4_FREQ_OFFSET FIELD32(0x001f8000)
2202 #define RF4_HT40 FIELD32(0x00200000)
2203
2204 /*
2205 * EEPROM content.
2206 * The wordsize of the EEPROM is 16 bits.
2207 */
2208
2209 /*
2210 * Chip ID
2211 */
2212 #define EEPROM_CHIP_ID 0x0000
2213
2214 /*
2215 * EEPROM Version
2216 */
2217 #define EEPROM_VERSION 0x0001
2218 #define EEPROM_VERSION_FAE FIELD16(0x00ff)
2219 #define EEPROM_VERSION_VERSION FIELD16(0xff00)
2220
2221 /*
2222 * HW MAC address.
2223 */
2224 #define EEPROM_MAC_ADDR_0 0x0002
2225 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
2226 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
2227 #define EEPROM_MAC_ADDR_1 0x0003
2228 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
2229 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
2230 #define EEPROM_MAC_ADDR_2 0x0004
2231 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
2232 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
2233
2234 /*
2235 * EEPROM NIC Configuration 0
2236 * RXPATH: 1: 1R, 2: 2R, 3: 3R
2237 * TXPATH: 1: 1T, 2: 2T, 3: 3T
2238 * RF_TYPE: RFIC type
2239 */
2240 #define EEPROM_NIC_CONF0 0x001a
2241 #define EEPROM_NIC_CONF0_RXPATH FIELD16(0x000f)
2242 #define EEPROM_NIC_CONF0_TXPATH FIELD16(0x00f0)
2243 #define EEPROM_NIC_CONF0_RF_TYPE FIELD16(0x0f00)
2244
2245 /*
2246 * EEPROM NIC Configuration 1
2247 * HW_RADIO: 0: disable, 1: enable
2248 * EXTERNAL_TX_ALC: 0: disable, 1: enable
2249 * EXTERNAL_LNA_2G: 0: disable, 1: enable
2250 * EXTERNAL_LNA_5G: 0: disable, 1: enable
2251 * CARDBUS_ACCEL: 0: enable, 1: disable
2252 * BW40M_SB_2G: 0: disable, 1: enable
2253 * BW40M_SB_5G: 0: disable, 1: enable
2254 * WPS_PBC: 0: disable, 1: enable
2255 * BW40M_2G: 0: enable, 1: disable
2256 * BW40M_5G: 0: enable, 1: disable
2257 * BROADBAND_EXT_LNA: 0: disable, 1: enable
2258 * ANT_DIVERSITY: 00: Disable, 01: Diversity,
2259 * 10: Main antenna, 11: Aux antenna
2260 * INTERNAL_TX_ALC: 0: disable, 1: enable
2261 * BT_COEXIST: 0: disable, 1: enable
2262 * DAC_TEST: 0: disable, 1: enable
2263 */
2264 #define EEPROM_NIC_CONF1 0x001b
2265 #define EEPROM_NIC_CONF1_HW_RADIO FIELD16(0x0001)
2266 #define EEPROM_NIC_CONF1_EXTERNAL_TX_ALC FIELD16(0x0002)
2267 #define EEPROM_NIC_CONF1_EXTERNAL_LNA_2G FIELD16(0x0004)
2268 #define EEPROM_NIC_CONF1_EXTERNAL_LNA_5G FIELD16(0x0008)
2269 #define EEPROM_NIC_CONF1_CARDBUS_ACCEL FIELD16(0x0010)
2270 #define EEPROM_NIC_CONF1_BW40M_SB_2G FIELD16(0x0020)
2271 #define EEPROM_NIC_CONF1_BW40M_SB_5G FIELD16(0x0040)
2272 #define EEPROM_NIC_CONF1_WPS_PBC FIELD16(0x0080)
2273 #define EEPROM_NIC_CONF1_BW40M_2G FIELD16(0x0100)
2274 #define EEPROM_NIC_CONF1_BW40M_5G FIELD16(0x0200)
2275 #define EEPROM_NIC_CONF1_BROADBAND_EXT_LNA FIELD16(0x400)
2276 #define EEPROM_NIC_CONF1_ANT_DIVERSITY FIELD16(0x1800)
2277 #define EEPROM_NIC_CONF1_INTERNAL_TX_ALC FIELD16(0x2000)
2278 #define EEPROM_NIC_CONF1_BT_COEXIST FIELD16(0x4000)
2279 #define EEPROM_NIC_CONF1_DAC_TEST FIELD16(0x8000)
2280
2281 /*
2282 * EEPROM frequency
2283 */
2284 #define EEPROM_FREQ 0x001d
2285 #define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
2286 #define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
2287 #define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
2288
2289 /*
2290 * EEPROM LED
2291 * POLARITY_RDY_G: Polarity RDY_G setting.
2292 * POLARITY_RDY_A: Polarity RDY_A setting.
2293 * POLARITY_ACT: Polarity ACT setting.
2294 * POLARITY_GPIO_0: Polarity GPIO0 setting.
2295 * POLARITY_GPIO_1: Polarity GPIO1 setting.
2296 * POLARITY_GPIO_2: Polarity GPIO2 setting.
2297 * POLARITY_GPIO_3: Polarity GPIO3 setting.
2298 * POLARITY_GPIO_4: Polarity GPIO4 setting.
2299 * LED_MODE: Led mode.
2300 */
2301 #define EEPROM_LED_AG_CONF 0x001e
2302 #define EEPROM_LED_ACT_CONF 0x001f
2303 #define EEPROM_LED_POLARITY 0x0020
2304 #define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
2305 #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
2306 #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
2307 #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
2308 #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
2309 #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
2310 #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
2311 #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
2312 #define EEPROM_LED_LED_MODE FIELD16(0x1f00)
2313
2314 /*
2315 * EEPROM NIC Configuration 2
2316 * RX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
2317 * TX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
2318 * CRYSTAL: 00: Reserved, 01: One crystal, 10: Two crystal, 11: Reserved
2319 */
2320 #define EEPROM_NIC_CONF2 0x0021
2321 #define EEPROM_NIC_CONF2_RX_STREAM FIELD16(0x000f)
2322 #define EEPROM_NIC_CONF2_TX_STREAM FIELD16(0x00f0)
2323 #define EEPROM_NIC_CONF2_CRYSTAL FIELD16(0x0600)
2324
2325 /*
2326 * EEPROM LNA
2327 */
2328 #define EEPROM_LNA 0x0022
2329 #define EEPROM_LNA_BG FIELD16(0x00ff)
2330 #define EEPROM_LNA_A0 FIELD16(0xff00)
2331
2332 /*
2333 * EEPROM RSSI BG offset
2334 */
2335 #define EEPROM_RSSI_BG 0x0023
2336 #define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
2337 #define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
2338
2339 /*
2340 * EEPROM RSSI BG2 offset
2341 */
2342 #define EEPROM_RSSI_BG2 0x0024
2343 #define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
2344 #define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
2345
2346 /*
2347 * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2).
2348 */
2349 #define EEPROM_TXMIXER_GAIN_BG 0x0024
2350 #define EEPROM_TXMIXER_GAIN_BG_VAL FIELD16(0x0007)
2351
2352 /*
2353 * EEPROM RSSI A offset
2354 */
2355 #define EEPROM_RSSI_A 0x0025
2356 #define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
2357 #define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
2358
2359 /*
2360 * EEPROM RSSI A2 offset
2361 */
2362 #define EEPROM_RSSI_A2 0x0026
2363 #define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
2364 #define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
2365
2366 /*
2367 * EEPROM TXMIXER GAIN A offset (note overlaps with EEPROM RSSI A2).
2368 */
2369 #define EEPROM_TXMIXER_GAIN_A 0x0026
2370 #define EEPROM_TXMIXER_GAIN_A_VAL FIELD16(0x0007)
2371
2372 /*
2373 * EEPROM EIRP Maximum TX power values(unit: dbm)
2374 */
2375 #define EEPROM_EIRP_MAX_TX_POWER 0x0027
2376 #define EEPROM_EIRP_MAX_TX_POWER_2GHZ FIELD16(0x00ff)
2377 #define EEPROM_EIRP_MAX_TX_POWER_5GHZ FIELD16(0xff00)
2378
2379 /*
2380 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
2381 * This is delta in 40MHZ.
2382 * VALUE: Tx Power dalta value, MAX=4(unit: dbm)
2383 * TYPE: 1: Plus the delta value, 0: minus the delta value
2384 * ENABLE: enable tx power compensation for 40BW
2385 */
2386 #define EEPROM_TXPOWER_DELTA 0x0028
2387 #define EEPROM_TXPOWER_DELTA_VALUE_2G FIELD16(0x003f)
2388 #define EEPROM_TXPOWER_DELTA_TYPE_2G FIELD16(0x0040)
2389 #define EEPROM_TXPOWER_DELTA_ENABLE_2G FIELD16(0x0080)
2390 #define EEPROM_TXPOWER_DELTA_VALUE_5G FIELD16(0x3f00)
2391 #define EEPROM_TXPOWER_DELTA_TYPE_5G FIELD16(0x4000)
2392 #define EEPROM_TXPOWER_DELTA_ENABLE_5G FIELD16(0x8000)
2393
2394 /*
2395 * EEPROM TXPOWER 802.11BG
2396 */
2397 #define EEPROM_TXPOWER_BG1 0x0029
2398 #define EEPROM_TXPOWER_BG2 0x0030
2399 #define EEPROM_TXPOWER_BG_SIZE 7
2400 #define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
2401 #define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
2402
2403 /*
2404 * EEPROM temperature compensation boundaries 802.11BG
2405 * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
2406 * reduced by (agc_step * -4)
2407 * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
2408 * reduced by (agc_step * -3)
2409 */
2410 #define EEPROM_TSSI_BOUND_BG1 0x0037
2411 #define EEPROM_TSSI_BOUND_BG1_MINUS4 FIELD16(0x00ff)
2412 #define EEPROM_TSSI_BOUND_BG1_MINUS3 FIELD16(0xff00)
2413
2414 /*
2415 * EEPROM temperature compensation boundaries 802.11BG
2416 * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
2417 * reduced by (agc_step * -2)
2418 * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
2419 * reduced by (agc_step * -1)
2420 */
2421 #define EEPROM_TSSI_BOUND_BG2 0x0038
2422 #define EEPROM_TSSI_BOUND_BG2_MINUS2 FIELD16(0x00ff)
2423 #define EEPROM_TSSI_BOUND_BG2_MINUS1 FIELD16(0xff00)
2424
2425 /*
2426 * EEPROM temperature compensation boundaries 802.11BG
2427 * REF: Reference TSSI value, no tx power changes needed
2428 * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
2429 * increased by (agc_step * 1)
2430 */
2431 #define EEPROM_TSSI_BOUND_BG3 0x0039
2432 #define EEPROM_TSSI_BOUND_BG3_REF FIELD16(0x00ff)
2433 #define EEPROM_TSSI_BOUND_BG3_PLUS1 FIELD16(0xff00)
2434
2435 /*
2436 * EEPROM temperature compensation boundaries 802.11BG
2437 * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
2438 * increased by (agc_step * 2)
2439 * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
2440 * increased by (agc_step * 3)
2441 */
2442 #define EEPROM_TSSI_BOUND_BG4 0x003a
2443 #define EEPROM_TSSI_BOUND_BG4_PLUS2 FIELD16(0x00ff)
2444 #define EEPROM_TSSI_BOUND_BG4_PLUS3 FIELD16(0xff00)
2445
2446 /*
2447 * EEPROM temperature compensation boundaries 802.11BG
2448 * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
2449 * increased by (agc_step * 4)
2450 * AGC_STEP: Temperature compensation step.
2451 */
2452 #define EEPROM_TSSI_BOUND_BG5 0x003b
2453 #define EEPROM_TSSI_BOUND_BG5_PLUS4 FIELD16(0x00ff)
2454 #define EEPROM_TSSI_BOUND_BG5_AGC_STEP FIELD16(0xff00)
2455
2456 /*
2457 * EEPROM TXPOWER 802.11A
2458 */
2459 #define EEPROM_TXPOWER_A1 0x003c
2460 #define EEPROM_TXPOWER_A2 0x0053
2461 #define EEPROM_TXPOWER_A_SIZE 6
2462 #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
2463 #define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
2464
2465 /*
2466 * EEPROM temperature compensation boundaries 802.11A
2467 * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
2468 * reduced by (agc_step * -4)
2469 * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
2470 * reduced by (agc_step * -3)
2471 */
2472 #define EEPROM_TSSI_BOUND_A1 0x006a
2473 #define EEPROM_TSSI_BOUND_A1_MINUS4 FIELD16(0x00ff)
2474 #define EEPROM_TSSI_BOUND_A1_MINUS3 FIELD16(0xff00)
2475
2476 /*
2477 * EEPROM temperature compensation boundaries 802.11A
2478 * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
2479 * reduced by (agc_step * -2)
2480 * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
2481 * reduced by (agc_step * -1)
2482 */
2483 #define EEPROM_TSSI_BOUND_A2 0x006b
2484 #define EEPROM_TSSI_BOUND_A2_MINUS2 FIELD16(0x00ff)
2485 #define EEPROM_TSSI_BOUND_A2_MINUS1 FIELD16(0xff00)
2486
2487 /*
2488 * EEPROM temperature compensation boundaries 802.11A
2489 * REF: Reference TSSI value, no tx power changes needed
2490 * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
2491 * increased by (agc_step * 1)
2492 */
2493 #define EEPROM_TSSI_BOUND_A3 0x006c
2494 #define EEPROM_TSSI_BOUND_A3_REF FIELD16(0x00ff)
2495 #define EEPROM_TSSI_BOUND_A3_PLUS1 FIELD16(0xff00)
2496
2497 /*
2498 * EEPROM temperature compensation boundaries 802.11A
2499 * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
2500 * increased by (agc_step * 2)
2501 * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
2502 * increased by (agc_step * 3)
2503 */
2504 #define EEPROM_TSSI_BOUND_A4 0x006d
2505 #define EEPROM_TSSI_BOUND_A4_PLUS2 FIELD16(0x00ff)
2506 #define EEPROM_TSSI_BOUND_A4_PLUS3 FIELD16(0xff00)
2507
2508 /*
2509 * EEPROM temperature compensation boundaries 802.11A
2510 * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
2511 * increased by (agc_step * 4)
2512 * AGC_STEP: Temperature compensation step.
2513 */
2514 #define EEPROM_TSSI_BOUND_A5 0x006e
2515 #define EEPROM_TSSI_BOUND_A5_PLUS4 FIELD16(0x00ff)
2516 #define EEPROM_TSSI_BOUND_A5_AGC_STEP FIELD16(0xff00)
2517
2518 /*
2519 * EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode
2520 */
2521 #define EEPROM_TXPOWER_BYRATE 0x006f
2522 #define EEPROM_TXPOWER_BYRATE_SIZE 9
2523
2524 #define EEPROM_TXPOWER_BYRATE_RATE0 FIELD16(0x000f)
2525 #define EEPROM_TXPOWER_BYRATE_RATE1 FIELD16(0x00f0)
2526 #define EEPROM_TXPOWER_BYRATE_RATE2 FIELD16(0x0f00)
2527 #define EEPROM_TXPOWER_BYRATE_RATE3 FIELD16(0xf000)
2528
2529 /*
2530 * EEPROM BBP.
2531 */
2532 #define EEPROM_BBP_START 0x0078
2533 #define EEPROM_BBP_SIZE 16
2534 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
2535 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
2536
2537 /*
2538 * EEPROM IQ Calibration, unlike other entries those are byte addresses.
2539 */
2540
2541 #define EEPROM_IQ_GAIN_CAL_TX0_2G 0x130
2542 #define EEPROM_IQ_PHASE_CAL_TX0_2G 0x131
2543 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_2G 0x132
2544 #define EEPROM_IQ_GAIN_CAL_TX1_2G 0x133
2545 #define EEPROM_IQ_PHASE_CAL_TX1_2G 0x134
2546 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_2G 0x135
2547 #define EEPROM_IQ_GAIN_CAL_RX0_2G 0x136
2548 #define EEPROM_IQ_PHASE_CAL_RX0_2G 0x137
2549 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_2G 0x138
2550 #define EEPROM_IQ_GAIN_CAL_RX1_2G 0x139
2551 #define EEPROM_IQ_PHASE_CAL_RX1_2G 0x13A
2552 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_2G 0x13B
2553 #define EEPROM_RF_IQ_COMPENSATION_CONTROL 0x13C
2554 #define EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL 0x13D
2555 #define EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G 0x144
2556 #define EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G 0x145
2557 #define EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G 0X146
2558 #define EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G 0x147
2559 #define EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G 0x148
2560 #define EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G 0x149
2561 #define EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G 0x14A
2562 #define EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G 0x14B
2563 #define EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G 0X14C
2564 #define EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G 0x14D
2565 #define EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G 0x14E
2566 #define EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G 0x14F
2567 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH36_TO_CH64_5G 0x150
2568 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH36_TO_CH64_5G 0x151
2569 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH100_TO_CH138_5G 0x152
2570 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH100_TO_CH138_5G 0x153
2571 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH140_TO_CH165_5G 0x154
2572 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH140_TO_CH165_5G 0x155
2573 #define EEPROM_IQ_GAIN_CAL_RX0_CH36_TO_CH64_5G 0x156
2574 #define EEPROM_IQ_PHASE_CAL_RX0_CH36_TO_CH64_5G 0x157
2575 #define EEPROM_IQ_GAIN_CAL_RX0_CH100_TO_CH138_5G 0X158
2576 #define EEPROM_IQ_PHASE_CAL_RX0_CH100_TO_CH138_5G 0x159
2577 #define EEPROM_IQ_GAIN_CAL_RX0_CH140_TO_CH165_5G 0x15A
2578 #define EEPROM_IQ_PHASE_CAL_RX0_CH140_TO_CH165_5G 0x15B
2579 #define EEPROM_IQ_GAIN_CAL_RX1_CH36_TO_CH64_5G 0x15C
2580 #define EEPROM_IQ_PHASE_CAL_RX1_CH36_TO_CH64_5G 0x15D
2581 #define EEPROM_IQ_GAIN_CAL_RX1_CH100_TO_CH138_5G 0X15E
2582 #define EEPROM_IQ_PHASE_CAL_RX1_CH100_TO_CH138_5G 0x15F
2583 #define EEPROM_IQ_GAIN_CAL_RX1_CH140_TO_CH165_5G 0x160
2584 #define EEPROM_IQ_PHASE_CAL_RX1_CH140_TO_CH165_5G 0x161
2585 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH36_TO_CH64_5G 0x162
2586 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH36_TO_CH64_5G 0x163
2587 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH100_TO_CH138_5G 0x164
2588 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH100_TO_CH138_5G 0x165
2589 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH140_TO_CH165_5G 0x166
2590 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH140_TO_CH165_5G 0x167
2591
2592 /*
2593 * MCU mailbox commands.
2594 * MCU_SLEEP - go to power-save mode.
2595 * arg1: 1: save as much power as possible, 0: save less power.
2596 * status: 1: success, 2: already asleep,
2597 * 3: maybe MAC is busy so can't finish this task.
2598 * MCU_RADIO_OFF
2599 * arg0: 0: do power-saving, NOT turn off radio.
2600 */
2601 #define MCU_SLEEP 0x30
2602 #define MCU_WAKEUP 0x31
2603 #define MCU_RADIO_OFF 0x35
2604 #define MCU_CURRENT 0x36
2605 #define MCU_LED 0x50
2606 #define MCU_LED_STRENGTH 0x51
2607 #define MCU_LED_AG_CONF 0x52
2608 #define MCU_LED_ACT_CONF 0x53
2609 #define MCU_LED_LED_POLARITY 0x54
2610 #define MCU_RADAR 0x60
2611 #define MCU_BOOT_SIGNAL 0x72
2612 #define MCU_ANT_SELECT 0X73
2613 #define MCU_BBP_SIGNAL 0x80
2614 #define MCU_POWER_SAVE 0x83
2615 #define MCU_BAND_SELECT 0x91
2616
2617 /*
2618 * MCU mailbox tokens
2619 */
2620 #define TOKEN_SLEEP 1
2621 #define TOKEN_RADIO_OFF 2
2622 #define TOKEN_WAKEUP 3
2623
2624
2625 /*
2626 * DMA descriptor defines.
2627 */
2628
2629 #define TXWI_DESC_SIZE_4WORDS (4 * sizeof(__le32))
2630 #define TXWI_DESC_SIZE_5WORDS (5 * sizeof(__le32))
2631
2632 #define RXWI_DESC_SIZE_4WORDS (4 * sizeof(__le32))
2633 #define RXWI_DESC_SIZE_6WORDS (6 * sizeof(__le32))
2634
2635 /*
2636 * TX WI structure
2637 */
2638
2639 /*
2640 * Word0
2641 * FRAG: 1 To inform TKIP engine this is a fragment.
2642 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
2643 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
2644 * BW: Channel bandwidth 0:20MHz, 1:40 MHz (for legacy rates this will
2645 * duplicate the frame to both channels).
2646 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
2647 * AMPDU: 1: this frame is eligible for AMPDU aggregation, the hw will
2648 * aggregate consecutive frames with the same RA and QoS TID. If
2649 * a frame A with the same RA and QoS TID but AMPDU=0 is queued
2650 * directly after a frame B with AMPDU=1, frame A might still
2651 * get aggregated into the AMPDU started by frame B. So, setting
2652 * AMPDU to 0 does _not_ necessarily mean the frame is sent as
2653 * MPDU, it can still end up in an AMPDU if the previous frame
2654 * was tagged as AMPDU.
2655 */
2656 #define TXWI_W0_FRAG FIELD32(0x00000001)
2657 #define TXWI_W0_MIMO_PS FIELD32(0x00000002)
2658 #define TXWI_W0_CF_ACK FIELD32(0x00000004)
2659 #define TXWI_W0_TS FIELD32(0x00000008)
2660 #define TXWI_W0_AMPDU FIELD32(0x00000010)
2661 #define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
2662 #define TXWI_W0_TX_OP FIELD32(0x00000300)
2663 #define TXWI_W0_MCS FIELD32(0x007f0000)
2664 #define TXWI_W0_BW FIELD32(0x00800000)
2665 #define TXWI_W0_SHORT_GI FIELD32(0x01000000)
2666 #define TXWI_W0_STBC FIELD32(0x06000000)
2667 #define TXWI_W0_IFS FIELD32(0x08000000)
2668 #define TXWI_W0_PHYMODE FIELD32(0xc0000000)
2669
2670 /*
2671 * Word1
2672 * ACK: 0: No Ack needed, 1: Ack needed
2673 * NSEQ: 0: Don't assign hw sequence number, 1: Assign hw sequence number
2674 * BW_WIN_SIZE: BA windows size of the recipient
2675 * WIRELESS_CLI_ID: Client ID for WCID table access
2676 * MPDU_TOTAL_BYTE_COUNT: Length of 802.11 frame
2677 * PACKETID: Will be latched into the TX_STA_FIFO register once the according
2678 * frame was processed. If multiple frames are aggregated together
2679 * (AMPDU==1) the reported tx status will always contain the packet
2680 * id of the first frame. 0: Don't report tx status for this frame.
2681 * PACKETID_QUEUE: Part of PACKETID, This is the queue index (0-3)
2682 * PACKETID_ENTRY: Part of PACKETID, THis is the queue entry index (1-3)
2683 * This identification number is calculated by ((idx % 3) + 1).
2684 * The (+1) is required to prevent PACKETID to become 0.
2685 */
2686 #define TXWI_W1_ACK FIELD32(0x00000001)
2687 #define TXWI_W1_NSEQ FIELD32(0x00000002)
2688 #define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
2689 #define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
2690 #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
2691 #define TXWI_W1_PACKETID FIELD32(0xf0000000)
2692 #define TXWI_W1_PACKETID_QUEUE FIELD32(0x30000000)
2693 #define TXWI_W1_PACKETID_ENTRY FIELD32(0xc0000000)
2694
2695 /*
2696 * Word2
2697 */
2698 #define TXWI_W2_IV FIELD32(0xffffffff)
2699
2700 /*
2701 * Word3
2702 */
2703 #define TXWI_W3_EIV FIELD32(0xffffffff)
2704
2705 /*
2706 * RX WI structure
2707 */
2708
2709 /*
2710 * Word0
2711 */
2712 #define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
2713 #define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
2714 #define RXWI_W0_BSSID FIELD32(0x00001c00)
2715 #define RXWI_W0_UDF FIELD32(0x0000e000)
2716 #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
2717 #define RXWI_W0_TID FIELD32(0xf0000000)
2718
2719 /*
2720 * Word1
2721 */
2722 #define RXWI_W1_FRAG FIELD32(0x0000000f)
2723 #define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
2724 #define RXWI_W1_MCS FIELD32(0x007f0000)
2725 #define RXWI_W1_BW FIELD32(0x00800000)
2726 #define RXWI_W1_SHORT_GI FIELD32(0x01000000)
2727 #define RXWI_W1_STBC FIELD32(0x06000000)
2728 #define RXWI_W1_PHYMODE FIELD32(0xc0000000)
2729
2730 /*
2731 * Word2
2732 */
2733 #define RXWI_W2_RSSI0 FIELD32(0x000000ff)
2734 #define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
2735 #define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
2736
2737 /*
2738 * Word3
2739 */
2740 #define RXWI_W3_SNR0 FIELD32(0x000000ff)
2741 #define RXWI_W3_SNR1 FIELD32(0x0000ff00)
2742
2743 /*
2744 * Macros for converting txpower from EEPROM to mac80211 value
2745 * and from mac80211 value to register value.
2746 */
2747 #define MIN_G_TXPOWER 0
2748 #define MIN_A_TXPOWER -7
2749 #define MAX_G_TXPOWER 31
2750 #define MAX_A_TXPOWER 15
2751 #define DEFAULT_TXPOWER 5
2752
2753 #define TXPOWER_G_FROM_DEV(__txpower) \
2754 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
2755
2756 #define TXPOWER_G_TO_DEV(__txpower) \
2757 clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
2758
2759 #define TXPOWER_A_FROM_DEV(__txpower) \
2760 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
2761
2762 #define TXPOWER_A_TO_DEV(__txpower) \
2763 clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
2764
2765 /*
2766 * Board's maximun TX power limitation
2767 */
2768 #define EIRP_MAX_TX_POWER_LIMIT 0x50
2769
2770 /*
2771 * Number of TBTT intervals after which we have to adjust
2772 * the hw beacon timer.
2773 */
2774 #define BCN_TBTT_OFFSET 64
2775
2776 /*
2777 * RT2800 driver data structure
2778 */
2779 struct rt2800_drv_data {
2780 u8 calibration_bw20;
2781 u8 calibration_bw40;
2782 u8 bbp25;
2783 u8 bbp26;
2784 u8 txmixer_gain_24g;
2785 u8 txmixer_gain_5g;
2786 unsigned int tbtt_tick;
2787 };
2788
2789 #endif /* RT2800_H */
Linux kernel - Deliverables
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